repo_name
stringlengths 6
79
| path
stringlengths 5
236
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stringclasses 54
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stringlengths 1
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| content
stringlengths 0
1.04M
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values |
|---|---|---|---|---|---|
grwlf/vsim
|
vhdl_ct/ct00165.vhd
|
1
|
7936
|
-- NEED RESULT: ARCH00165.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00165: One inertial transaction occurred on signal asg with slice name prefixed by an indexed name on LHS passed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00165
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00165(ARCH00165)
-- ENT00165_Test_Bench(ARCH00165_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00165 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00165 ;
--
architecture ARCH00165 of ENT00165 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00165.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00165" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <= transport
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00165" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)
(lowb+1 to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_2(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00165" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
-- Last transaction above is marked
s_st_arr1_vector(lowb) (lowb+1 to highb-1) <=
c_st_arr1_vector_1(highb)
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector(lowb) (lowb+1 to highb-1) =
c_st_arr1_vector_1(highb) (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00165" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00165" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00165 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00165_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00165_Test_Bench ;
--
architecture ARCH00165_Test_Bench of ENT00165_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00165 ( ARCH00165 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
) ;
end block L1 ;
end ARCH00165_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/VHDL_StratixIV_OrphanedGland/sha256/rtl/sha256_qp.vhd
|
4
|
13870
|
--
-- Copyright (c) 2011 OrphanedGland ([email protected])
-- Send donations to : 1PioyqqFWXbKryxysGqoq5XAu9MTRANCEP
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- SHA256 core using quasi-pipelining technique
-- Inspired by fpgaminer's sha256_transform.v
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end entity sha256_qp;
architecture sha256_qp_rtl of sha256_qp is
alias slv is std_logic_vector;
subtype msg is unsigned(511 downto 0);
subtype word is unsigned(31 downto 0);
function e0(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(1 downto 0) & x(31 downto 2)) xor (x(12 downto 0) & x(31 downto 13)) xor (x(21 downto 0) & x(31 downto 22));
end e0;
function e1(x: unsigned(31 downto 0)) return unsigned is
begin
return (x(5 downto 0) & x(31 downto 6)) xor (x(10 downto 0) & x(31 downto 11)) xor (x(24 downto 0) & x(31 downto 25));
end e1;
function s0(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 29) := x(6 downto 4) xor x(17 downto 15);
y(28 downto 0) := (x(3 downto 0) & x(31 downto 7)) xor (x(14 downto 0) & x(31 downto 18)) xor x(31 downto 3);
return y;
end s0;
function s1(x: unsigned(31 downto 0)) return unsigned is
variable y : unsigned(31 downto 0);
begin
y(31 downto 22) := x(16 downto 7) xor x(18 downto 9);
y(21 downto 0) := (x(6 downto 0) & x(31 downto 17)) xor (x(8 downto 0) & x(31 downto 19)) xor x(31 downto 10);
return y;
end s1;
function ch(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (not(x) and z);
end ch;
function maj(x: unsigned(31 downto 0); y: unsigned(31 downto 0); z: unsigned(31 downto 0)) return unsigned is
begin
return (x and y) xor (x and z) xor (y and z);
end maj;
type msg_array is array(0 to 63) of msg;
type word_array_64 is array(0 to 63) of word;
type word_array_65 is array(0 to 64) of word;
type word_array_66 is array(0 to 65) of word;
type hash_array is array(0 to 7) of word;
constant k : word_array_64 := ( X"428a2f98", X"71374491", X"b5c0fbcf", X"e9b5dba5", X"3956c25b", X"59f111f1", X"923f82a4", X"ab1c5ed5",
X"d807aa98", X"12835b01", X"243185be", X"550c7dc3", X"72be5d74", X"80deb1fe", X"9bdc06a7", X"c19bf174",
X"e49b69c1", X"efbe4786", X"0fc19dc6", X"240ca1cc", X"2de92c6f", X"4a7484aa", X"5cb0a9dc", X"76f988da",
X"983e5152", X"a831c66d", X"b00327c8", X"bf597fc7", X"c6e00bf3", X"d5a79147", X"06ca6351", X"14292967",
X"27b70a85", X"2e1b2138", X"4d2c6dfc", X"53380d13", X"650a7354", X"766a0abb", X"81c2c92e", X"92722c85",
X"a2bfe8a1", X"a81a664b", X"c24b8b70", X"c76c51a3", X"d192e819", X"d6990624", X"f40e3585", X"106aa070",
X"19a4c116", X"1e376c08", X"2748774c", X"34b0bcb5", X"391c0cb3", X"4ed8aa4a", X"5b9cca4f", X"682e6ff3",
X"748f82ee", X"78a5636f", X"84c87814", X"8cc70208", X"90befffa", X"a4506ceb", X"bef9a3f7", X"c67178f2" );
constant h_default : hash_array := ( X"6a09e667", X"bb67ae85", X"3c6ef372", X"a54ff53a", X"510e527f", X"9b05688c", X"1f83d9ab", X"5be0cd19" );
signal w : msg_array;
signal new_w : word_array_64;
signal a : word_array_66;
signal b : word_array_66;
signal c : word_array_66;
signal d : word_array_66;
signal e : word_array_66;
signal f : word_array_66;
signal g : word_array_66;
signal h : word_array_66;
signal hash : hash_array;
signal h_init : hash_array;
signal delta0 : word_array_64;
signal delta1 : word_array_64;
signal m1 : word_array_64;
signal m2 : word_array_64;
signal epsilon : word_array_65;
signal l : word_array_65;
signal alpha : word_array_66;
signal q_w : msg_array;
signal q_a : word_array_66;
signal q_b : word_array_66;
signal q_c : word_array_66;
signal q_d : word_array_66;
signal q_e : word_array_66;
signal q_f : word_array_66;
signal q_g : word_array_66;
signal q_h : word_array_66;
signal q_hash : hash_array;
signal q_m1 : word_array_64;
signal q_m2 : word_array_64;
signal q_l : word_array_65;
begin
output_mapping: for i in 0 to 7 generate
--digest((i+1)*32-1 downto i*32) <= slv(q_hash(7-i));
digest((i+1)*32-1 downto i*32) <= slv(q_hash(i));
end generate output_mapping;
default_h_gen: if default_h = true generate
h_init <= h_default;
end generate default_h_gen;
h_gen: if default_h = false generate
h_array_gen: for i in 0 to 7 generate
h_init(i) <= unsigned(h_in((i+1)*32-1 downto i*32));
end generate h_array_gen;
end generate h_gen;
hash_pipeline: for i in 0 to 65 generate
first_stage: if i = 0 generate
w(i) <= unsigned(msg_in);
a(i) <= h_init(0);
b(i) <= h_init(1);
c(i) <= h_init(2);
d(i) <= h_init(3);
e(i) <= h_init(4);
f(i) <= h_init(5);
g(i) <= h_init(6);
h(i) <= h_init(7);
delta0(i) <= h_init(3);
delta1(i) <= h_init(7);
m1(i) <= delta0(i) + delta1(i) + k(i) + w(i)(31 downto 0);
m2(i) <= delta1(i) + k(i) + w(i)(31 downto 0);
epsilon(i) <= e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6));
l(i) <= (others => '0');
alpha(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
end generate first_stage;
second_stage: if i = 1 generate
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= h_init(0);
b(i) <= h_init(1);
c(i) <= h_init(2);
d(i) <= h_init(3);
e(i) <= epsilon(i);
f(i) <= h_init(4);
g(i) <= h_init(5);
h(i) <= h_init(6);
delta0(i) <= h_init(2);
delta1(i) <= h_init(6);
m1(i) <= delta0(i) + delta1(i) + k(i) + w(i)(31 downto 0);
m2(i) <= delta1(i) + k(i) + w(i)(31 downto 0);
epsilon(i) <= q_m1(i-1) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6));
l(i) <= q_m2(i-1) + e1(h_init(4)) + ch(h_init(4), h_init(5), h_init(6));
alpha(i) <= e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
end generate second_stage;
third_stage: if i = 2 generate
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= alpha(i);
b(i) <= h_init(0);
c(i) <= h_init(1);
d(i) <= h_init(2);
e(i) <= epsilon(i);
f(i) <= q_e(i-1);
g(i) <= h_init(4); -- q_f(i-1)
h(i) <= h_init(5); -- q_g(i-1)
delta0(i) <= h_init(1);
delta1(i) <= h_init(5);
m1(i) <= delta0(i) + delta1(i) + k(i) + w(i)(31 downto 0);
m2(i) <= delta1(i) + k(i) + w(i)(31 downto 0);
epsilon(i) <= q_m1(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), h_init(4), h_init(5));
l(i) <= q_m2(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), h_init(4), h_init(5));
alpha(i) <= q_l(i-1) + e0(h_init(0)) + maj(h_init(0), h_init(1), h_init(2));
end generate third_stage;
normal_stage: if i > 2 and i < 64 generate
new_w(i) <= s1(q_w(i-1)(479 downto 448)) + q_w(i-1)(319 downto 288) + s0(q_w(i-1)(63 downto 32)) + q_w(i-1)(31 downto 0);
w(i) <= new_w(i) & q_w(i-1)(511 downto 32);
a(i) <= alpha(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= epsilon(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
delta0(i) <= q_b(i-1);
delta1(i) <= q_g(i-1);
m1(i) <= delta0(i) + delta1(i) + k(i) + w(i)(31 downto 0);
m2(i) <= delta1(i) + k(i) + w(i)(31 downto 0);
epsilon(i) <= q_m1(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1));
l(i) <= q_m2(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1));
alpha(i) <= q_l(i-1) + e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
end generate normal_stage;
second_last_stage: if i = 64 generate
a(i) <= alpha(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= epsilon(i);
f(i) <= q_e(i-1);
g(i) <= q_f(i-1);
h(i) <= q_g(i-1);
epsilon(i) <= q_m1(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1));
l(i) <= q_m2(i-1) + e1(q_e(i-1)) + ch(q_e(i-1), q_f(i-1), q_g(i-1));
alpha(i) <= q_l(i-1) + e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
end generate second_last_stage;
last_stage: if i = 65 generate
a(i) <= alpha(i);
b(i) <= q_a(i-1);
c(i) <= q_b(i-1);
d(i) <= q_c(i-1);
e(i) <= q_e(i-1);
f(i) <= q_f(i-1);
g(i) <= q_g(i-1);
h(i) <= q_h(i-1);
alpha(i) <= q_l(i-1) + e0(q_a(i-1)) + maj(q_a(i-1), q_b(i-1), q_c(i-1));
end generate last_stage;
end generate hash_pipeline;
hash(0) <= q_a(65) + h_init(0);
hash(1) <= q_b(65) + h_init(1);
hash(2) <= q_c(65) + h_init(2);
hash(3) <= q_d(65) + h_init(3);
hash(4) <= q_e(65) + h_init(4);
hash(5) <= q_f(65) + h_init(5);
hash(6) <= q_g(65) + h_init(6);
hash(7) <= q_h(65) + h_init(7);
registers : process(clk, reset) is
begin
if reset = '1' then
null;
elsif rising_edge(clk) then
q_w <= w;
q_a <= a;
q_b <= b;
q_c <= c;
q_d <= d;
q_e <= e;
q_f <= f;
q_g <= g;
q_h <= h;
q_hash <= hash;
q_m1 <= m1;
q_m2 <= m2;
q_l <= l;
end if;
end process registers;
end architecture sha256_qp_rtl;
|
gpl-3.0
|
grwlf/vsim
|
vhdl/IEEE/numeric_bit-body.vhdl
|
7
|
57051
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--======================= Package Body =========================================
--==============================================================================
package body NUMERIC_BIT is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: BIT) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input carry
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: BIT) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: BIT := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: BIT_VECTOR; COUNT: NATURAL) return BIT_VECTOR is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: BIT_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: BIT_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
---------------- Local Subprograms - Relational Operators --------------------
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) = BIT_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) < BIT_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) < BIT_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return BIT_VECTOR(L) <= BIT_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return BIT_VECTOR(INTERN_L) <= BIT_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--====================== Exported Functions ==================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := ARG;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
variable CBIT: BIT := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG(I)) xor CBIT;
CBIT := CBIT and not(XARG(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE), RESIZE(R, SIZE), '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
return ADD_UNSIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
return ADD_SIGNED(RESIZE(L, SIZE),
not(RESIZE(R, SIZE)),
'1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) := (others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := L;
XR := R;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
QNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
RNEG := TRUE;
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
DIVMOD(L, R, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
if L(L'LEFT)='1' then
XNUM := UNSIGNED(-L);
else
XNUM := UNSIGNED(L);
end if;
if R(R'LEFT)='1' then
XDENOM := UNSIGNED(-R);
RNEG := TRUE;
else
XDENOM := UNSIGNED(R);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_BIT.""mod"": modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L, SIZE), RESIZE(R, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R'LENGTH), R);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L, TO_UNSIGNED(R, L'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L, TO_SIGNED(R, L'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
variable SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L, SIZE), RESIZE(R, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R'LENGTH), R));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L, TO_UNSIGNED(R, L'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L, TO_SIGNED(R, L'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(BIT_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(BIT_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(BIT_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(BIT_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-V93
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-V93
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_BIT.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
if ARG(ARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(ARG));
else
return (- (TO_INTEGER(UNSIGNED(- (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_BIT.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER;
SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: BIT := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_BIT.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(BIT_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) and BIT_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) or BIT_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nand BIT_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) nor BIT_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xor BIT_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(BIT_VECTOR(L) xnor BIT_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '1';
end RISING_EDGE;
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN is
begin
return S'EVENT and S = '0';
end FALLING_EDGE;
--============================================================================
end NUMERIC_BIT;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00493.vhd
|
1
|
5811
|
-- NEED RESULT: ARCH00493: Aggregates with others choice associated with function return (locally static) passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00493
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (5)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00493(ARCH00493)
-- ENT00493_Test_Bench(ARCH00493_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00493 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
constant r1 : integer := 1 ;
constant a11 : boolean := false ;
constant a12 : boolean := true ;
constant a21 : integer := 1 ;
constant a22 : integer := 5 ;
constant b11 : integer := 0 ;
constant b12 : integer := 0 ;
constant b21 : integer := -5 ;
constant b22 : integer := -3 ;
constant c1 : integer := 0 ;
constant c2 : integer := 4 ;
constant d1 : integer := 3 ;
constant d2 : integer := 5 ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - r1 to r1 ;
-- f2 : rec_arr (-r1 to r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-r1 to r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range a11 to a12 ;
subtype arange2 is integer range a21 to a22 ;
subtype brange1 is integer range b11 to b12 ;
subtype brange2 is integer range b21 to b22 ;
subtype crange is integer range c1 to c2 ;
subtype drange is integer range d1 to d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00493 ;
--
architecture ARCH00493 of ENT00493 is
begin
B1 :
block
--
function f_arr_1 return st_arr_1 is
begin
return ( ( c_rec_1_1, others => c_rec_1_2 ),
others => (others => c_rec_1_1) ) ;
end f_arr_1 ;
function f_time_matrix return st_time_matrix is
begin
return
( st_time_matrix'right(1) =>
( st_time_matrix'right(2) => 10 ns, others => 5 fs),
others => (brange2'left => 10 ps, others => 15ms) ) ;
end f_time_matrix ;
function f_bit_vector return st_bit_vector is
begin
return
( 0 => '1', 2 => '1', others => '0' ) ;
end f_bit_vector ;
function f_string return st_string is
begin
return
( 3 => 'a', 4 => 'b', others => '0' ) ;
end f_string ;
function f_rec_1 return rec_1 is
begin
return
-- ( f2 => (r1 => true, others => false), f3 => 1, others => 0) ;
( f3 => 1, others => 0) ;
end f_rec_1 ;
begin
process
variable bool : boolean := true;
begin
bool := bool and f_arr_1(false, 1) = c_rec_1_1 ;
for i in 2 to 5 loop
bool := bool and f_arr_1(false, i) = c_rec_1_2 ;
end loop ;
for i in 1 to 5 loop
bool := bool and f_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
bool := bool and f_time_matrix(0, -3) = 10 ns ;
for i in integer'(-5) to -4 loop
bool := bool and f_time_matrix(0, i) = 5 fs ;
end loop ;
--
bool := bool and f_bit_vector = B"10100" ;
--
bool := bool and f_string = "ab0" ;
--
bool := bool and f_rec_1.f1 = 0 and f_rec_1.f4 = 0
and f_rec_1.f3 = 1 ;
-- bool := bool and f_rec_1.f2(1) = true
-- and f_rec_1.f2(0) = false and
-- f_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00493" ,
"Aggregates with others choice associated with function"
& " return (locally static)" ,
bool ) ;
wait ;
end process ;
end block B1 ;
end ARCH00493 ;
--
entity ENT00493_Test_Bench is
end ENT00493_Test_Bench ;
--
architecture ARCH00493_Test_Bench of ENT00493_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00493 ( ARCH00493 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00493_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00247.vhd
|
1
|
7437
|
-- NEED RESULT: ARCH00247: Test of operator overloading passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00247
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1 (3)
-- 2.1 (4)
-- 2.3.1 (1)
-- 2.3.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00247)
-- ENT00247_Test_Bench(ARCH00247_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
-- This test overloads the operators listed in LRM Section 7.2 on the
-- enumeration type t_enum1 in STANDARD_TYPES. For some of the operators,
-- a reasonable value is defined; in the other cases, only a stub value is
-- returned.
--
-- The operators "mod" and "rem" are defined for testing purposes as the
-- left and right projection operators, respectively (for test
-- objective 2.3.1 (1) ). They are called using both the operator notation
-- and function notation (for test objective 2.3.1 (2) ).
--
-- Objective 2.1 (4) is met by defining the operators in upper case and
-- by referencing them in lower case.
--
-- The type t_enum1 is taken from STANDARD_TYPES.
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00247 of E00000 is
-- logical operators
function "AND" ( left, right : in t_enum1 ) return t_enum1 is
begin
if t_enum1'pos(left) <= t_enum1'pos(right) then
return left;
else
return right ;
end if;
end ;
function "OR" ( left, right : in t_enum1 ) return t_enum1 is
begin
if t_enum1'pos(left) >= t_enum1'pos(right) then
return left;
else
return right ;
end if;
end ;
function "NAND" ( left, right : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
function "NOR" ( left, right : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
function "XOR" ( left, right : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
-- relational operators (these test 2.1 (3))
function "=" ( left, right : in t_enum1 ) return boolean is
begin
return t_enum1'pos(left) = t_enum1'pos(right) ;
end ;
function "/=" ( left, right : in t_enum1 ) return boolean is
begin
return t_enum1'pos(left) /= t_enum1'pos(right) ;
end ;
function "<" ( left, right : in t_enum1 ) return boolean is
begin
return t_enum1'pos(left) < t_enum1'pos(right) ;
end ;
function "<=" ( left, right : in t_enum1 ) return boolean is
begin
return t_enum1'pos(left) <= t_enum1'pos(right) ;
end ;
function ">" ( left, right : in t_enum1 ) return boolean is
begin
return t_enum1'pos(left) > t_enum1'pos(right) ;
end ;
function ">=" ( left, right : in t_enum1 ) return boolean is
begin
return t_enum1'pos(left) >= t_enum1'pos(right) ;
end ;
-- adding operators
function "+" ( left, right : in t_enum1 ) return t_enum1 is
begin
return t_enum1'val( ( t_enum1'pos(left) + t_enum1'pos(right) ) mod
( 1 + t_enum1'pos(right) ) ) ;
end ;
function "-" ( left, right : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
function "&" ( left, right : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
-- signs
function "+" ( operand : in t_enum1 ) return t_enum1 is
begin
return operand ;
end ;
function "-" ( operand : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
-- multiplying operators
function "*" ( left, right : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
function "/" ( left, right : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
function "MOD" ( left, right : in t_enum1 ) return t_enum1 is
begin
return left ;
end ;
function "REM" ( left, right : in t_enum1 ) return t_enum1 is
begin
return right ;
end ;
-- miscellaneous operators
function "**" ( left, right : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
function "ABS" ( operand : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
function "NOT" ( operand : in t_enum1 ) return t_enum1 is
begin
return t_enum1'left ;
end ;
begin
P :
process
begin
test_report ( "ARCH00247" ,
"Test of operator overloading" ,
-- logical operators
((t_enum1'left and t_enum1'right) = t_enum1'left) and
((t_enum1'left or t_enum1'right) = t_enum1'right) and
((t_enum1'left nand t_enum1'right) = t_enum1'left) and
((t_enum1'left nor t_enum1'right) = t_enum1'left) and
((t_enum1'left xor t_enum1'right) = t_enum1'left) and
-- relational operators
(t_enum1'left = t_enum1'left) and
(t_enum1'left /= t_enum1'right) and
(t_enum1'left < t_enum1'right) and
(t_enum1'left <= t_enum1'right) and
(t_enum1'right > t_enum1'left) and
(t_enum1'right >= t_enum1'left) and
-- adding operators
(t_enum1'left + t_enum1'right = t_enum1'right) and
(t_enum1'left - t_enum1'right = t_enum1'left) and
(t_enum1'left & t_enum1'right = t_enum1'left) and
-- signs
( + t_enum1'right = t_enum1'right) and
( - t_enum1'right = t_enum1'left) and
-- multiplying operators
(t_enum1'left mod t_enum1'right = t_enum1'left) and
(t_enum1'right mod t_enum1'left = t_enum1'right) and
(t_enum1'left rem t_enum1'right = t_enum1'right) and
(t_enum1'right rem t_enum1'left = t_enum1'left) and
("mod" (t_enum1'left , t_enum1'right) = t_enum1'left) and
("mod" (t_enum1'right, t_enum1'left ) = t_enum1'right) and
("rem" (t_enum1'left , t_enum1'right) = t_enum1'right) and
("rem" (t_enum1'right, t_enum1'left ) = t_enum1'left) and
-- miscellaneous operators
(t_enum1'left ** t_enum1'right = t_enum1'left) and
(t_enum1'right ** t_enum1'left = t_enum1'left) and
(abs (t_enum1'right ) = t_enum1'left) and
(not (t_enum1'right ) = t_enum1'left)
) ;
wait ;
end process P ;
end ARCH00247 ;
entity ENT00247_Test_Bench is
end ENT00247_Test_Bench ;
architecture ARCH00247_Test_Bench of ENT00247_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00247 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00247_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00216.vhd
|
1
|
5570
|
-- NEED RESULT: ENT00216: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00216: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00216: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00216: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00216
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00216(ARCH00216)
-- ENT00216_Test_Bench(ARCH00216_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00216 is
generic (G : integer) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00216 ;
--
--
architecture ARCH00216 of ENT00216 is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_arr1_vector : inout st_arr1_vector
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(2)(2) <= transport
c_st_arr1_vector_2(2)(2) after 10 ns ;
wait until s_st_arr1_vector(2)(2) =
c_st_arr1_vector_2(2)(2) ;
Test_Report (
"ENT00216",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(2)(2) =
c_st_arr1_vector_2(2)(2) )) ;
--
when 1
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(G)(G) <= transport
c_st_arr1_vector_2(G)(G) after 10 ns ;
wait until s_st_arr1_vector(G)(G) =
c_st_arr1_vector_2(G)(G) ;
Test_Report (
"ENT00216",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(G)(G) =
c_st_arr1_vector_2(G)(G) )) ;
--
when 2
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_2(1)(1) ;
s_st_arr1_vector(CG)(CG) <= transport
c_st_arr1_vector_2(CG)(CG) after 10 ns ;
wait until s_st_arr1_vector(CG)(CG) =
c_st_arr1_vector_2(CG)(CG) ;
Test_Report (
"ENT00216",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG)(CG) =
c_st_arr1_vector_2(CG)(CG) )) ;
--
when 3
=>
s_st_arr1_vector(1)(1) <= transport
c_st_arr1_vector_1(1)(1) ;
s_st_arr1_vector(CG'Attr)(CG'Attr) <= transport
c_st_arr1_vector_2(CG'Attr)(CG'Attr) after 10 ns ;
wait until s_st_arr1_vector(CG'Attr)(CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr) ;
Test_Report (
"ENT00216",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_arr1_vector(CG'Attr)(CG'Attr) =
c_st_arr1_vector_2(CG'Attr)(CG'Attr) )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_arr1_vector
, counter
, correct
, savtime
, chk_st_arr1_vector
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_arr1_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00216 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00216_Test_Bench is
end ENT00216_Test_Bench ;
--
--
architecture ARCH00216_Test_Bench of ENT00216_Test_Bench is
begin
L1:
block
component UUT
generic (G : integer) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00216 ( ARCH00216 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
;
end block L1 ;
end ARCH00216_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00008.vhd
|
1
|
5639
|
-- NEED RESULT: ARCH00008.P1: Wait has sens_list, condition, time passed
-- NEED RESULT: ARCH00008.GLB_PROC1: Wait has sens_list, condition, time passed
-- NEED RESULT: ARCH00008.P1: Wait has sens_list, condition passed
-- NEED RESULT: ARCH00008.GLB_PROC1: Wait has sens_list, condition passed
-- NEED RESULT: ARCH00008.P1: Wait has sens_list, time passed
-- NEED RESULT: ARCH00008.GLB_PROC1: Wait has sens_list, time passed
-- NEED RESULT: ARCH00008.P1: Wait has sens_list passed
-- NEED RESULT: ARCH00008.GLB_PROC1: Wait has sens_list passed
-- NEED RESULT: ARCH00008.P1: Wait has condition, time passed
-- NEED RESULT: ARCH00008.GLB_PROC1: Wait has condition, time passed
-- NEED RESULT: ARCH00008.P1: Wait has condition passed
-- NEED RESULT: ARCH00008.GLB_PROC1: Wait has condition passed
-- NEED RESULT: ARCH00008.GLB_PROC1: Wait has time passed
-- NEED RESULT: ARCH00008.P1: Wait has time passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00008
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (2)
-- 8.1 (3)
-- 8.1 (4)
-- 8.1 (6)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00008)
-- ENT00008_Test_Bench(ARCH00008_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
-- 11-DEC-1989 - GDT: in case 7, changed time clause from 0ns to 10ns and
-- modified test_report pass/fail condition
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00008 of E00000 is -- Check with simple names
signal Test_Case : Integer := 0 ;
constant Max_Test_Cases : Integer := 8 ;
procedure Glb_Proc1 is
variable Save : Integer;
begin
Save := Test_Case;
case Test_Case is
when 1 =>
wait on Test_Case until True for (Time'High - Std.Standard.Now) ;
test_report ( "ARCH00008.GLB_PROC1" ,
"Wait has sens_list, condition, time" ,
Save /= Test_Case ) ;
when 2 =>
wait on Test_Case until True ;
test_report ( "ARCH00008.GLB_PROC1" ,
"Wait has sens_list, condition" ,
Save /= Test_Case ) ;
when 3 =>
wait on Test_Case for (Time'High - Std.Standard.Now) ;
test_report ( "ARCH00008.GLB_PROC1" ,
"Wait has sens_list, time" ,
Save /= Test_Case ) ;
when 4 =>
wait on Test_Case ;
test_report ( "ARCH00008.GLB_PROC1" ,
"Wait has sens_list" ,
Save /= Test_Case ) ;
when 5 =>
wait until (Test_Case = Test_Case) for (Time'High - Std.Standard.Now) ;
test_report ( "ARCH00008.GLB_PROC1" ,
"Wait has condition, time" ,
Save /= Test_Case ) ;
when 6 =>
wait until (Test_Case = Test_Case) ;
test_report ( "ARCH00008.GLB_PROC1" ,
"Wait has condition" ,
Save /= Test_Case ) ;
when 7 =>
-- GDT 12-7-89: wait for 0 ns ;
wait for 10 ns ;
test_report ( "ARCH00008.GLB_PROC1" ,
"Wait has time" ,
-- GDT 12-7-89: Save = Test_Case ) ;
Save /= Test_Case ) ;
when 8 =>
wait ;
test_report ( "ARCH00008.GLB_PROC1" ,
"Wait with no clauses" ,
False ) ;
when others =>
wait on Test_Case ;
end case ;
end Glb_Proc1 ;
begin
Change_Test_Case :
process (Test_Case)
begin
if Test_Case < Max_Test_Cases then
Test_Case <= transport (Test_Case + 1) after 10 ns;
end if ;
end process Change_Test_Case ;
P1 :
process
variable Save : Integer;
begin
Save := Test_Case;
case Test_Case is
when 1 =>
wait on Test_Case until True for (Time'High - Std.Standard.Now) ;
test_report ( "ARCH00008.P1" ,
"Wait has sens_list, condition, time" ,
Save /= Test_Case ) ;
when 2 =>
wait on Test_Case until True ;
test_report ( "ARCH00008.P1" ,
"Wait has sens_list, condition" ,
Save /= Test_Case ) ;
when 3 =>
wait on Test_Case for (Time'High - Std.Standard.Now) ;
test_report ( "ARCH00008.P1" ,
"Wait has sens_list, time" ,
Save /= Test_Case ) ;
when 4 =>
wait on Test_Case ;
test_report ( "ARCH00008.P1" ,
"Wait has sens_list" ,
Save /= Test_Case ) ;
when 5 =>
wait until (Test_Case = Test_Case) for (Time'High - Std.Standard.Now) ;
test_report ( "ARCH00008.P1" ,
"Wait has condition, time" ,
Save /= Test_Case ) ;
when 6 =>
wait until (Test_Case = Test_Case) ;
test_report ( "ARCH00008.P1" ,
"Wait has condition" ,
Save /= Test_Case ) ;
when 7 =>
-- GDT 12-7-89: wait for 0 ns ;
wait for 10 ns ;
test_report ( "ARCH00008.P1" ,
"Wait has time" ,
-- GDT 12-7-89: Save = Test_Case ) ;
Save /= Test_Case ) ;
when 8 =>
wait ;
test_report ( "ARCH00008.P1" ,
"Wait with no clauses" ,
False ) ;
when others =>
wait on Test_Case ;
end case ;
end process P1 ;
P2 :
process
begin
Glb_Proc1 ;
end process P2 ;
end ARCH00008 ;
entity ENT00008_Test_Bench is
end ENT00008_Test_Bench ;
architecture ARCH00008_Test_Bench of ENT00008_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00008 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00008_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00242.vhd
|
1
|
4008
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00242
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00242)
-- ENT00242_Test_Bench(ARCH00242_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00242 of GENERIC_STANDARD_TYPES is
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
begin
L1:
block
port (
i_bit_vector_1, i_bit_vector_2 : linkage bit_vector
;
i_string_1, i_string_2 : linkage string
;
i_t_rec1_1, i_t_rec1_2 : linkage t_rec1
;
i_st_rec1_1, i_st_rec1_2 : linkage st_rec1
;
i_t_rec2_1, i_t_rec2_2 : linkage t_rec2
;
i_st_rec2_1, i_st_rec2_2 : linkage st_rec2
;
i_t_rec3_1, i_t_rec3_2 : linkage t_rec3
;
i_st_rec3_1, i_st_rec3_2 : linkage st_rec3
;
i_t_arr1_1, i_t_arr1_2 : linkage t_arr1
;
i_st_arr1_1, i_st_arr1_2 : linkage st_arr1
;
i_t_arr2_1, i_t_arr2_2 : linkage t_arr2
;
i_st_arr2_1, i_st_arr2_2 : linkage st_arr2
;
i_t_arr3_1, i_t_arr3_2 : linkage t_arr3
;
i_st_arr3_1, i_st_arr3_2 : linkage st_arr3
) ;
port map (
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
test_report ( "ENT00242" ,
"Associated composite linkage ports with generic subtypes" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00242 ;
--
entity ENT00242_Test_Bench is
end ENT00242_Test_Bench ;
--
architecture ARCH00242_Test_Bench of ENT00242_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00242 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00242_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_getinit_pkg.vhd
|
9
|
54741
|
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`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00416.vhd
|
1
|
9059
|
-- NEED RESULT: ARCH00416.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00416: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00416: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00416: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00416: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00416
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00416(ARCH00416)
-- ENT00416_Test_Bench(ARCH00416_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00416 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00416 ;
--
--
architecture ARCH00416 of ENT00416 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00416.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00416" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00416" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00416" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
-- c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f3(lowb,true)(lowb to highb-1) =
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00416" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00416" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f3(lowb,true)(lowb to highb-1)'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f3(lowb,true)(lowb to highb-1) <=
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 10 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 20 ns ,
c_st_rec3_2.f3(lowb,true)(lowb to highb-1) after 30 ns ,
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1.f3(lowb,true)(lowb to highb-1) after 40 ns ;
--
end ARCH00416 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00416_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00416_Test_Bench ;
--
--
architecture ARCH00416_Test_Bench of ENT00416_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00416 ( ARCH00416 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00416_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00025.vhd
|
1
|
7581
|
-- NEED RESULT: ENT00025: Associated composite in ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00025
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00025(ARCH00025)
-- ENT00025_Test_Bench(ARCH00025_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00025 is
port (
i_bit_vector_1, i_bit_vector_2 : in bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : in string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : in t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : in st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : in t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : in st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : in t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : in st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : in t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : in st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : in t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : in st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : in t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : in st_arr3
:= c_st_arr3_1
) ;
begin
end ENT00025 ;
--
architecture ARCH00025 of ENT00025 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
--
test_report ( "ENT00025" ,
"Associated composite in ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00025 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00025_Test_Bench is
end ENT00025_Test_Bench ;
--
architecture ARCH00025_Test_Bench of ENT00025_Test_Bench is
begin
L1:
block
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
component UUT
port (
i_bit_vector_1, i_bit_vector_2 : in bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : in string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : in t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : in st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : in t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : in st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : in t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : in st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : in t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : in st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : in t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : in st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : in t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : in st_arr3
:= c_st_arr3_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00025 ( ARCH00025 ) ;
--
begin
CIS1 : UUT
port map (
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
end block L1 ;
end ARCH00025_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00457.vhd
|
1
|
5068
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00457
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.2.4 (9)
-- 7.2.4 (10)
-- 7.2.4 (11)
-- 7.2.4 (12)
-- 7.2.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00457(ARCH00457)
-- ENT00457_Test_Bench(ARCH00457_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES ;
use WORK.ARITHMETIC.ALL ;
entity ENT00457 is
generic (
i_phys_1 : time := c_time_1 ;
i_phys_2 : time := c_time_2 ;
i_t_phys_1 : t_phys := c_t_phys_1 ;
i_t_phys_2 : t_phys := c_t_phys_2 ;
i_st_phys_1 : st_phys := c_st_phys_1 ;
i_st_phys_2 : st_phys := c_st_phys_2
) ;
port ( locally_static_correct : out boolean ;
globally_static_correct : out boolean ;
dynamic_correct : out boolean ) ;
end ENT00457 ;
architecture ARCH00457 of ENT00457 is
constant c2_phys_1 : integer :=
(i_phys_1 + 5 ns) / i_phys_1 + i_phys_1 / i_phys_2 +
i_phys_2 / i_phys_1 + (4 * i_phys_2) / i_phys_2 ;
constant c2_t_phys_1 : integer :=
(i_t_phys_1 + i_t_phys_1) / i_t_phys_1 + i_t_phys_1 / i_t_phys_2 +
i_t_phys_2 / i_t_phys_1 + (-6 * i_t_phys_2) / i_t_phys_2 ;
constant c2_st_phys_1 : integer :=
(i_t_phys_1) / i_st_phys_1 + i_st_phys_1 / i_t_phys_2 +
i_t_phys_2 / i_t_phys_1 + (5 * i_st_phys_2) / i_t_phys_2 ;
begin
process
variable bool : boolean := true ;
variable cons_correct, gen_correct, dyn_correct : boolean := true ;
--
variable v_phys_1 : time := i_phys_1 ;
variable v2_phys_1 : integer ;
variable v_phys_2 : time := i_phys_2 ;
variable v_t_phys_1 : t_phys := i_t_phys_1 ;
variable v2_t_phys_1 : integer ;
variable v_t_phys_2 : t_phys := i_t_phys_2 ;
variable v_st_phys_1 : st_phys := i_st_phys_1 ;
variable v2_st_phys_1 : integer ;
variable v_st_phys_2 : st_phys := i_st_phys_2 ;
--
begin
-- static expression
case bool is
when (
(c_time_1 + 5 ns) / c_time_1 + c_time_1 / c_time_2 +
c_time_2 / c_time_1 + (4 * c_time_2) / c_time_2
= 100010 and --xx and
(c_t_phys_1 + c_t_phys_1) / c_t_phys_1 + c_t_phys_1 / c_t_phys_2 +
c_t_phys_2 / c_t_phys_1 + (-6 * c_t_phys_2) / c_t_phys_2
= -170 and --xx and
(c_t_phys_1) / c_st_phys_1 + c_st_phys_1 / c_t_phys_2 +
c_t_phys_2 / c_t_phys_1 + (5 * c_st_phys_2) / c_t_phys_2
= 165 --xx
) =>
null ;
when others =>
cons_correct := false ;
end case ;
-- generic expression
gen_correct := c2_phys_1 = 100010 and --xx and
c2_t_phys_1 = -170 and --xx and
c2_st_phys_1 = 165 ; --xx ;
-- dynamic expression
v2_phys_1 :=
(v_phys_1 + 5 ns) / v_phys_1 + v_phys_1 / v_phys_2 +
v_phys_2 / v_phys_1 + (4 * v_phys_2) / c_time_2 ;
v2_t_phys_1 :=
(v_t_phys_1 + v_t_phys_1) / v_t_phys_1 + i_t_phys_1 / v_t_phys_2 +
v_t_phys_2 / i_t_phys_1 + (-6 * v_t_phys_2) / v_t_phys_2 ;
v2_st_phys_1 :=
(i_t_phys_1) / v_st_phys_1 + v_st_phys_1 / i_t_phys_2 +
v_t_phys_2 / v_t_phys_1 + (5 * v_st_phys_2) / v_t_phys_2 ;
dyn_correct := v2_phys_1 = 100010 and --xx and
v2_t_phys_1 = -170 and --xx and
v2_st_phys_1 = 165 ; --xx ;
locally_static_correct <= cons_correct ;
globally_static_correct <= gen_correct ;
dynamic_correct <= dyn_correct ;
wait ;
end process ;
end ARCH00457 ;
use WORK.STANDARD_TYPES.ALL ;
entity ENT00457_Test_Bench is
end ENT00457_Test_Bench ;
architecture ARCH00457_Test_Bench of ENT00457_Test_Bench is
begin
L1:
block
signal locally_static_correct, globally_static_correct,
dynamic_correct : boolean := false ;
component UUT
port ( locally_static_correct : out boolean := false ;
globally_static_correct : out boolean := false ;
dynamic_correct : out boolean := false ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00457 ( ARCH00457 ) ;
begin
CIS1 : UUT
port map ( locally_static_correct,
globally_static_correct,
dynamic_correct ) ;
process ( locally_static_correct, globally_static_correct,
dynamic_correct )
begin
if locally_static_correct and globally_static_correct and
dynamic_correct then
test_report ( "ARCH00457" ,
"* predefined for phycial types" ,
true ) ;
end if ;
end process ;
end block L1 ;
end ARCH00457_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00490.vhd
|
1
|
8474
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00490
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2.2 (3)
-- 7.3.2.2 (11)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00490(ARCH00490)
-- ENT00490_Test_Bench(ARCH00490_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00490 is
generic (
constant g_a11 : boolean := false ;
constant g_a12 : boolean := true ;
constant g_a21 : integer := 1 ;
constant g_a22 : integer := 5 ;
constant g_b11 : integer := 0 ;
constant g_b12 : integer := 0 ;
constant g_b21 : integer := -5 ;
constant g_b22 : integer := -3 ;
constant g_c1 : integer := 0 ;
constant g_c2 : integer := 4 ;
constant g_d1 : integer := 3 ;
constant g_d2 : integer := 5 ;
constant g_r1 : integer := 1
) ;
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - g_r1 to g_r1 ;
-- f2 : rec_arr (-g_r1 to g_r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-g_r1 to g_r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range g_a11 to g_a12 ;
subtype arange2 is integer range g_a21 to g_a22 ;
subtype brange1 is integer range g_b11 to g_b12 ;
subtype brange2 is integer range g_b21 to g_b22 ;
subtype crange is integer range g_c1 to g_c2 ;
subtype drange is integer range g_d1 to g_d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
--
end ENT00490 ;
--
architecture ARCH00490 of ENT00490 is
begin
B1 :
block
generic ( g_arr_1 : st_arr_1 ;
g_time_matrix : st_time_matrix ;
g_bit_vector : st_bit_vector ;
g_string : st_string ;
g_rec_1 : rec_1 ) ;
generic map ( ( others => (others => c_rec_1_1) ) ,
( others => (others => 15ms) ) ,
( others => '0' ) ,
( others => 'a' ) ,
-- ( f2 => (others => false), others => 0) ) ;
( others => 0) ) ;
--
procedure p3
is
variable bool : boolean := true ;
begin
for i in 1 to 5 loop
bool := bool and g_arr_1(false, i) = c_rec_1_1 ;
end loop ;
for i in 1 to 5 loop
bool := bool and g_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
for i in integer'(-5) to -3 loop
bool := bool and g_time_matrix(0, i) = 15 ms ;
end loop ;
--
bool := bool and g_bit_vector = B"00000" ;
--
bool := bool and g_string = "aaa" ;
--
bool := bool and g_rec_1.f1 = 0 and g_rec_1.f4 = 0
and g_rec_1.f3 = 0 ;
-- bool := bool and g_rec_1.f2(1) = false
-- and g_rec_1.f2(0) = false and
-- g_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00490" ,
"Aggregates with others choice associated with formal"
& " generic (generic and dynamic)" ,
bool ) ;
--
end p3;
procedure p2 (
constant d_a11 : boolean := false ;
constant d_a12 : boolean := true ;
constant d_a21 : integer := 1 ;
constant d_a22 : integer := 5 ;
constant d_b11 : integer := 0 ;
constant d_b12 : integer := 0 ;
constant d_b21 : integer := -5 ;
constant d_b22 : integer := -3 ;
constant d_c1 : integer := 0 ;
constant d_c2 : integer := 4 ;
constant d_d1 : integer := 3 ;
constant d_d2 : integer := 5 ;
constant d_r1 : integer := 1
)
is
--
type rec_arr is array ( integer range <> ) of boolean ;
type rec_1 is record
f1 : integer range - d_r1 to d_r1 ;
-- f2 : rec_arr (-d_r1 to d_r1) ;
f3, f4 : integer ;
end record ;
-- constant c_rec_arr : rec_arr (-d_r1 to d_r1) :=
-- (true, false, false) ;
-- constant c_rec_1_1 : rec_1 := (1, (true, false, false), 1, 0) ;
-- constant c_rec_1_2 : rec_1 := (0, (true, false, false), 0, 1) ;
constant c_rec_1_1 : rec_1 := (1, 1, 0) ;
constant c_rec_1_2 : rec_1 := (0, 0, 1) ;
--
type arr_1 is array ( boolean range <> , integer range <> )
of rec_1 ;
type time_matrix is array ( integer range <> , integer range <> )
of time ;
--
--
subtype arange1 is boolean range d_a11 to d_a12 ;
subtype arange2 is integer range d_a21 to d_a22 ;
subtype brange1 is integer range d_b11 to d_b12 ;
subtype brange2 is integer range d_b21 to d_b22 ;
subtype crange is integer range d_c1 to d_c2 ;
subtype drange is integer range d_d1 to d_d2 ;
--
subtype st_arr_1 is arr_1 ( arange1 , arange2 ) ;
subtype st_time_matrix is time_matrix ( brange1 , brange2 ) ;
subtype st_bit_vector is bit_vector ( crange ) ;
subtype st_string is string ( drange ) ;
--
procedure p1 ( p_arr_1 : st_arr_1 ;
p_time_matrix : st_time_matrix ;
p_bit_vector : st_bit_vector ;
p_string : st_string ;
p_rec_1 : rec_1 ) is
variable bool : boolean := true ;
begin
for i in 1 to 5 loop
bool := bool and p_arr_1(false, i) = c_rec_1_1 ;
end loop ;
for i in 1 to 5 loop
bool := bool and p_arr_1(true, i) = c_rec_1_1 ;
end loop ;
--
for i in integer'(-5) to -3 loop
bool := bool and p_time_matrix(0, i) = 15 ms ;
end loop ;
--
bool := bool and p_bit_vector = B"00000" ;
--
bool := bool and p_string = "aaa" ;
--
bool := bool and p_rec_1.f1 = 0 and p_rec_1.f4 = 0
and p_rec_1.f3 = 0 ;
-- bool := bool and p_rec_1.f2(1) = false
-- and p_rec_1.f2(0) = false and
-- p_rec_1.f2(-1) = false ;
--
--
test_report ( "ARCH00490" ,
"Aggregates with others choice associated with formal"
& " parameter (generic and dynamic)" ,
bool ) ;
end p1 ;
begin
p1 ( ( others => (others => c_rec_1_1) ) ,
( others => (others => 15ms) ) ,
( others => '0' ) ,
( others => 'a' ) ,
-- ( f2 => (others => false), others => 0) ) ;
( others => 0) ) ;
p3 ;
end p2 ;
begin
process
begin
p2( open, open, open, open, open, open, open, open,
open, open, open, open, open ) ;
wait ;
end process ;
end block B1 ;
end ARCH00490 ;
--
entity ENT00490_Test_Bench is
end ENT00490_Test_Bench ;
--
architecture ARCH00490_Test_Bench of ENT00490_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00490 ( ARCH00490 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00490_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_bin_cntr.vhd
|
9
|
21696
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14320)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/wr_bin_cntr.vhd
|
9
|
21696
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14320)
`protect data_block
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6KvQvSF41Q4fL6w+R8gcokctF9lIWW9ZUS/sr8w1asTE+/NLI4cL0MTG6cQznyG1QLVO2pTXQPJz
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VHn+brksRRg7O3HJwA==
`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00647.vhd
|
1
|
2828
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00647
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (6)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00647(ARCH00647)
-- ENT00647_Test_Bench(ARCH00647_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00647 is
port ( signal G1 : integer := 0 ;
signal G2, G3, G4 : in integer := 3 ) ;
end ENT00647 ;
--
architecture ARCH00647 of ENT00647 is
procedure Proc ( signal P1 : integer := 0 ;
signal P2, P3, P4 : in integer := 3 ) is
begin
test_report ( "ARCH00647" ,
"The keyword 'in' is optional in a "&
"signal declaration for a formal parameter of "&
"a procedure" ,
(P1 = 1) and
(P2 = 2) and
(P3 = 3) and
(P4 = 4) ) ;
end Proc ;
begin
process
begin
test_report ( "ARCH00647" ,
"The keyword 'in' is optional in a "&
"signal declaration for a formal port of "&
"an entity" ,
(G1 = 1) and
(G2 = 2) and
(G3 = 3) and
(G4 = 4) ) ;
Proc (P1 => G1, P2 => G2, P4 => G4) ;
wait ;
end process ;
L1 :
block
port ( signal BG1 : integer := 0 ;
signal BG2, BG3, BG4 : in integer := 3 ) ;
port map ( G1, G2, BG4 => G4 ) ;
begin
process
begin
test_report ( "ARCH00647" ,
"The keyword 'in' is optional in a "&
"signal declaration for a formal port of "&
"a block" ,
(BG1 = 1) and
(BG2 = 2) and
(BG3 = 3) and
(BG4 = 4) ) ;
wait ;
end process ;
end block L1 ;
end ARCH00647 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00647_Test_Bench is
end ENT00647_Test_Bench ;
architecture ARCH00647_Test_Bench of ENT00647_Test_Bench is
begin
L1:
block
component UUT
port ( signal CG1 : integer ;
signal CG2, CG4 : in integer ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00647 ( ARCH00647 )
port map ( G1 => CG1,
G2 => CG2,
G4 => CG4 );
signal S1 : integer := 1 ;
signal S2 : integer := 2 ;
signal S4 : integer := 4 ;
begin
CIS1 : UUT
port map ( S1, S2, S4 );
end block L1 ;
end ARCH00647_Test_Bench ;
--
|
gpl-3.0
|
SamuelLBau/Pool-Shot-Tracking-using-FPGA
|
examples/sparse_mm/solution1/syn/vhdl/sparse_mm.vhd
|
1
|
30066
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sparse_mm is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
a_address0 : OUT STD_LOGIC_VECTOR (21 downto 0);
a_ce0 : OUT STD_LOGIC;
a_q0 : IN STD_LOGIC_VECTOR (63 downto 0);
a_y : IN STD_LOGIC_VECTOR (31 downto 0);
a_x : IN STD_LOGIC_VECTOR (31 downto 0);
b_address0 : OUT STD_LOGIC_VECTOR (10 downto 0);
b_ce0 : OUT STD_LOGIC;
b_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
b_y : IN STD_LOGIC_VECTOR (31 downto 0);
b_x : IN STD_LOGIC_VECTOR (31 downto 0);
c_address0 : OUT STD_LOGIC_VECTOR (10 downto 0);
c_ce0 : OUT STD_LOGIC;
c_we0 : OUT STD_LOGIC;
c_d0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of sparse_mm is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"sparse_mm,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7vx690tffg1761-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.280000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=12,HLS_SYN_FF=462,HLS_SYN_LUT=355}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (17 downto 0) := "000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (17 downto 0) := "000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (17 downto 0) := "000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (17 downto 0) := "000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (17 downto 0) := "000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (17 downto 0) := "000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (17 downto 0) := "000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (17 downto 0) := "000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (17 downto 0) := "000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (17 downto 0) := "000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (17 downto 0) := "001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (17 downto 0) := "010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (17 downto 0) := "100000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
signal ap_CS_fsm : STD_LOGIC_VECTOR (17 downto 0) := "000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_34 : BOOLEAN;
signal ibx_cast_fu_145_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ibx_cast_reg_258 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_78 : BOOLEAN;
signal ibx_1_fu_154_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal ibx_1_reg_267 : STD_LOGIC_VECTOR (30 downto 0);
signal a_i_1_fu_165_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal a_i_1_reg_275 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_89 : BOOLEAN;
signal tmp_1_fu_160_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal column_cast_fu_190_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal column_cast_reg_289 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_105 : BOOLEAN;
signal value_reg_294 : STD_LOGIC_VECTOR (31 downto 0);
signal iay_1_fu_204_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal iay_1_reg_299 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_176_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_215_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_8_reg_304 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_122 : BOOLEAN;
signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC;
signal ap_sig_bdd_131 : BOOLEAN;
signal b_load_reg_314 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC;
signal ap_sig_bdd_139 : BOOLEAN;
signal grp_fu_228_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_7_reg_319 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC;
signal ap_sig_bdd_148 : BOOLEAN;
signal sum_1_fu_232_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC;
signal ap_sig_bdd_157 : BOOLEAN;
signal grp_fu_210_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_3_reg_329 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_166 : BOOLEAN;
signal ibx_reg_90 : STD_LOGIC_VECTOR (30 downto 0);
signal a_i_reg_101 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_fu_149_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_183 : BOOLEAN;
signal iay_reg_114 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_reg_129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_171_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_s_fu_223_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_4_fu_241_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_200 : BOOLEAN;
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_208 : BOOLEAN;
signal tmp_fu_149_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal column_fu_180_p4 : STD_LOGIC_VECTOR (30 downto 0);
signal grp_fu_215_p0 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_247 : BOOLEAN;
signal tmp_9_fu_219_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_237_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_210_ce : STD_LOGIC;
signal grp_fu_215_ce : STD_LOGIC;
signal grp_fu_228_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (17 downto 0);
component sparse_mm_mul_32s_32s_32_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component sparse_mm_mul_31ns_32s_32_3 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (30 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
sparse_mm_mul_32s_32s_32_3_U1 : component sparse_mm_mul_32s_32s_32_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => iay_reg_114,
din1 => b_x,
ce => grp_fu_210_ce,
dout => grp_fu_210_p2);
sparse_mm_mul_31ns_32s_32_3_U2 : component sparse_mm_mul_31ns_32s_32_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 31,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_215_p0,
din1 => b_x,
ce => grp_fu_215_ce,
dout => grp_fu_215_p2);
sparse_mm_mul_32s_32s_32_3_U3 : component sparse_mm_mul_32s_32s_32_3
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_load_reg_314,
din1 => value_reg_294,
ce => grp_fu_228_ce,
dout => grp_fu_228_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- a_i_reg_101 assign process. --
a_i_reg_101_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then
a_i_reg_101 <= a_i_1_reg_275;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_fu_149_p2)))) then
a_i_reg_101 <= ap_const_lv32_0;
end if;
end if;
end process;
-- iay_reg_114 assign process. --
iay_reg_114_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
iay_reg_114 <= iay_reg_114;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then
iay_reg_114 <= iay_1_reg_299;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_fu_149_p2)))) then
iay_reg_114 <= ap_const_lv32_0;
end if;
end if;
end process;
-- ibx_reg_90 assign process. --
ibx_reg_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (tmp_1_fu_160_p2 = ap_const_lv1_0))) then
ibx_reg_90 <= ibx_1_reg_267;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
ibx_reg_90 <= ap_const_lv31_0;
end if;
end if;
end process;
-- sum_reg_129 assign process. --
sum_reg_129_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then
sum_reg_129 <= sum_1_fu_232_p2;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_fu_149_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then
sum_reg_129 <= ap_const_lv32_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
a_i_1_reg_275 <= a_i_1_fu_165_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st11_fsm_10)) then
b_load_reg_314 <= b_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
column_cast_reg_289(30 downto 0) <= column_cast_fu_190_p1(30 downto 0);
value_reg_294 <= a_q0(63 downto 32);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_6_fu_176_p1)))) then
iay_1_reg_299 <= iay_1_fu_204_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
ibx_1_reg_267 <= ibx_1_fu_154_p2;
ibx_cast_reg_258(30 downto 0) <= ibx_cast_fu_145_p1(30 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
tmp_3_reg_329 <= grp_fu_210_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13)) then
tmp_7_reg_319 <= grp_fu_228_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
tmp_8_reg_304 <= grp_fu_215_p2;
end if;
end if;
end process;
ibx_cast_reg_258(31) <= '0';
column_cast_reg_289(31) <= '0';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, tmp_1_fu_160_p2, tmp_6_fu_176_p1, tmp_fu_149_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((ap_const_lv1_0 = tmp_fu_149_p2)) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
if (not((tmp_1_fu_160_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
if (not((ap_const_lv1_0 = tmp_6_fu_176_p1))) then
ap_NS_fsm <= ap_ST_st16_fsm_15;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXX";
end case;
end process;
a_address0 <= tmp_2_fu_171_p1(22 - 1 downto 0);
-- a_ce0 assign process. --
a_ce0_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st4_fsm_3, ap_sig_cseq_ST_st5_fsm_4)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) or (ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4))) then
a_ce0 <= ap_const_logic_1;
else
a_ce0 <= ap_const_logic_0;
end if;
end process;
a_i_1_fu_165_p2 <= std_logic_vector(unsigned(a_i_reg_101) + unsigned(ap_const_lv32_1));
-- ap_done assign process. --
ap_done_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_fu_149_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_fu_149_p2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_fu_149_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_fu_149_p2))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_105 assign process. --
ap_sig_bdd_105_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_105 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_122 assign process. --
ap_sig_bdd_122_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_122 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_131 assign process. --
ap_sig_bdd_131_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_131 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9));
end process;
-- ap_sig_bdd_139 assign process. --
ap_sig_bdd_139_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_139 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10));
end process;
-- ap_sig_bdd_148 assign process. --
ap_sig_bdd_148_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_148 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13));
end process;
-- ap_sig_bdd_157 assign process. --
ap_sig_bdd_157_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_157 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14));
end process;
-- ap_sig_bdd_166 assign process. --
ap_sig_bdd_166_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_166 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_183 assign process. --
ap_sig_bdd_183_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_183 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_200 assign process. --
ap_sig_bdd_200_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_200 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_208 assign process. --
ap_sig_bdd_208_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_208 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_247 assign process. --
ap_sig_bdd_247_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_247 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_34 assign process. --
ap_sig_bdd_34_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_34 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_78 assign process. --
ap_sig_bdd_78_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_78 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_89 assign process. --
ap_sig_bdd_89_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_89 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_cseq_ST_st10_fsm_9 assign process. --
ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_bdd_131)
begin
if (ap_sig_bdd_131) then
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st11_fsm_10 assign process. --
ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_bdd_139)
begin
if (ap_sig_bdd_139) then
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st14_fsm_13 assign process. --
ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_bdd_148)
begin
if (ap_sig_bdd_148) then
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st15_fsm_14 assign process. --
ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_bdd_157)
begin
if (ap_sig_bdd_157) then
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_166)
begin
if (ap_sig_bdd_166) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_183)
begin
if (ap_sig_bdd_183) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_34)
begin
if (ap_sig_bdd_34) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_78)
begin
if (ap_sig_bdd_78) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_89)
begin
if (ap_sig_bdd_89) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_200)
begin
if (ap_sig_bdd_200) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_208)
begin
if (ap_sig_bdd_208) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_105)
begin
if (ap_sig_bdd_105) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_247)
begin
if (ap_sig_bdd_247) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_122)
begin
if (ap_sig_bdd_122) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
b_address0 <= tmp_s_fu_223_p1(11 - 1 downto 0);
-- b_ce0 assign process. --
b_ce0_assign_proc : process(ap_sig_cseq_ST_st10_fsm_9)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9)) then
b_ce0 <= ap_const_logic_1;
else
b_ce0 <= ap_const_logic_0;
end if;
end process;
c_address0 <= tmp_4_fu_241_p1(11 - 1 downto 0);
-- c_ce0 assign process. --
c_ce0_assign_proc : process(ap_sig_cseq_ST_st18_fsm_17)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then
c_ce0 <= ap_const_logic_1;
else
c_ce0 <= ap_const_logic_0;
end if;
end process;
c_d0 <= sum_reg_129;
-- c_we0 assign process. --
c_we0_assign_proc : process(ap_sig_cseq_ST_st18_fsm_17)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then
c_we0 <= ap_const_logic_1;
else
c_we0 <= ap_const_logic_0;
end if;
end process;
column_cast_fu_190_p1 <= std_logic_vector(resize(unsigned(column_fu_180_p4),32));
column_fu_180_p4 <= a_q0(31 downto 1);
grp_fu_210_ce <= ap_const_logic_1;
grp_fu_215_ce <= ap_const_logic_1;
grp_fu_215_p0 <= column_cast_reg_289(31 - 1 downto 0);
grp_fu_228_ce <= ap_const_logic_1;
iay_1_fu_204_p2 <= std_logic_vector(signed(iay_reg_114) + signed(ap_const_lv32_1));
ibx_1_fu_154_p2 <= std_logic_vector(unsigned(ibx_reg_90) + unsigned(ap_const_lv31_1));
ibx_cast_fu_145_p1 <= std_logic_vector(resize(unsigned(ibx_reg_90),32));
sum_1_fu_232_p2 <= std_logic_vector(unsigned(tmp_7_reg_319) + unsigned(sum_reg_129));
tmp_1_fu_160_p2 <= "1" when (unsigned(iay_reg_114) < unsigned(a_y)) else "0";
tmp_2_fu_171_p1 <= std_logic_vector(resize(signed(a_i_reg_101),64));
tmp_4_fu_241_p1 <= std_logic_vector(resize(signed(tmp_5_fu_237_p2),64));
tmp_5_fu_237_p2 <= std_logic_vector(unsigned(tmp_3_reg_329) + unsigned(ibx_cast_reg_258));
tmp_6_fu_176_p1 <= a_q0(1 - 1 downto 0);
tmp_9_fu_219_p2 <= std_logic_vector(unsigned(tmp_8_reg_304) + unsigned(ibx_cast_reg_258));
tmp_fu_149_p1 <= b_x;
tmp_fu_149_p2 <= "1" when (signed(ibx_cast_fu_145_p1) < signed(tmp_fu_149_p1)) else "0";
tmp_s_fu_223_p1 <= std_logic_vector(resize(unsigned(tmp_9_fu_219_p2),64));
end behav;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00243.vhd
|
1
|
1930
|
-- NEED RESULT: ARCH00243: Formal parameter list is optional in a subprogram spec passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00243
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1 (1)
-- 2.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00243)
-- ENT00243_Test_Bench(ARCH00243_Test_Bench)
--
-- REVISION HISTORY:
--
-- 14-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00243 of E00000 is
procedure subprog is
begin
null ;
end subprog ;
procedure subprog_with_parms (j_in : in integer; j_out : out integer) is
begin
j_out := 2*j_in ;
end subprog_with_parms ;
function func return integer is
begin
return 100 ;
end func ;
function func_with_parms (j,k: integer) return integer is
begin
return j+k ;
end func_with_parms ;
begin
P :
process
variable i : integer ;
begin
subprog ;
subprog_with_parms(10, i) ;
test_report ( "ARCH00243" ,
"Formal parameter list is optional in a subprogram spec" ,
(i = 2*10) and
(func = 100) and
(func_with_parms(2,3) = 2+3)
) ;
wait ;
end process P ;
end ARCH00243 ;
entity ENT00243_Test_Bench is
end ENT00243_Test_Bench ;
architecture ARCH00243_Test_Bench of ENT00243_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00243 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00243_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00482.vhd
|
1
|
1696
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00482
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.1 (7)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00482)
-- ENT00482_Test_Bench(ARCH00482_Test_Bench)
--
-- REVISION HISTORY:
--
-- 7-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00482 of E00000 is
procedure Proc ;
procedure Proc ( a : Integer ) is
begin
null;
end Proc ;
procedure Proc ( a : Real ) ;
function Func return Integer is
begin
return 0;
end Func;
function Func return Real is
begin
return 0.0;
end Func ;
procedure Proc is
begin
null;
end Proc ;
procedure Proc ( a : Real ) is
begin
null;
end Proc;
attribute Attr : boolean ;
attribute Attr of Proc : procedure is false ;
attribute Attr of Func : function is true ;
begin
process
begin
test_report ( "ARCH00482" ,
"An attribute associated on an overloaded subprogram" ,
(Not Proc'Attr) and Func'Attr ) ;
wait ;
end process ;
end ARCH00482 ;
entity ENT00482_Test_Bench is
end ENT00482_Test_Bench ;
architecture ARCH00482_Test_Bench of ENT00482_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00482 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00482_Test_Bench ;
|
gpl-3.0
|
dcliche/mdsynth
|
rtl/src/pia_timer.vhd
|
1
|
15664
|
--===========================================================================--
-- --
-- pia_timer.vhd - Synthesizable Parallel Interface Adapter with Timer --
-- --
--===========================================================================--
--
-- File name : pia_timer.vhd
--
-- Entity name : pia_timer
--
-- Purpose : Implements 2 x 8 bit parallel I/O ports
-- with 8 bit presetable counter.
-- Port A Data = output connected to presettable counter input
-- Port B Data = input connected to counter output
-- Used with Digilent Spartan 3E starter board
-- to implement a single step trace function.
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
-- unisim.vcomponents
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : Register Memory Map
--
-- Base + $00 - Port A Data & Direction register
-- Base + $01 - Port A Control register
-- Base + $02 - Port B Data & Direction Direction Register
-- Base + $03 - Port B Control Register
--
-- Copyright (C) 2004 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version Author Date Description
-- 0.0 John Kent 1st May 2004 Initial version developed from ioport.vhd
--
-- 1.0 John Kent 22nd April 2006 Removed I/O ports and hard wired a binary
-- down counter. Port A is the preset output.
-- Port B is the timer count input.
-- CA1 & CB1 are interrupt inputs
-- CA2 is the counter load (active low)
-- CB2 is the counter reset (active high)
-- It may be necessary to offset the counter
-- to compensate for differences in cpu cycle
-- times between FPGA and real 6809 systems.
--
-- 1.1 John Kent 24th May 2006 Modified counter to subtract one from preset
-- so FPGA version of the CMC_BUG monitor is
-- compatible with the reference design.
--
-- 1.2 John Kent 30th May 2010 Revised header and added updated GPL
--
--===========================================================================----
--
-- Memory Map
--
-- IO + $00 - Port A Data & Direction register
-- IO + $01 - Port A Control register
-- IO + $02 - Port B Data & Direction Direction Register
-- IO + $03 - Port B Control Register
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity pia_timer is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
addr : in std_logic_vector(1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irqa : out std_logic;
irqb : out std_logic
);
end;
architecture pia_arch of pia_timer is
signal pa : std_logic_vector(7 downto 0);
signal porta_ddr : std_logic_vector(7 downto 0);
signal porta_data : std_logic_vector(7 downto 0);
signal porta_ctrl : std_logic_vector(5 downto 0);
signal porta_read : std_logic;
signal pb : std_logic_vector(7 downto 0);
signal portb_ddr : std_logic_vector(7 downto 0);
signal portb_data : std_logic_vector(7 downto 0);
signal portb_ctrl : std_logic_vector(5 downto 0);
signal portb_read : std_logic;
signal portb_write : std_logic;
signal ca1 : std_logic;
signal ca1_del : std_logic;
signal ca1_rise : std_logic;
signal ca1_fall : std_logic;
signal ca1_edge : std_logic;
signal irqa1 : std_logic := '0';
signal ca2 : std_logic;
signal ca2_del : std_logic;
signal ca2_rise : std_logic;
signal ca2_fall : std_logic;
signal ca2_edge : std_logic;
signal irqa2 : std_logic := '0';
signal ca2_out : std_logic;
signal cb1 : std_logic;
signal cb1_del : std_logic;
signal cb1_rise : std_logic;
signal cb1_fall : std_logic;
signal cb1_edge : std_logic;
signal irqb1 : std_logic := '0';
signal cb2 : std_logic;
signal cb2_del : std_logic;
signal cb2_rise : std_logic;
signal cb2_fall : std_logic;
signal cb2_edge : std_logic;
signal irqb2 : std_logic := '0';
signal cb2_out : std_logic;
-- 74193 down counter
signal timer : std_logic_vector(7 downto 0);
begin
--------------------------------
--
-- read I/O port
--
--------------------------------
pia_read : process( addr, cs,
irqa1, irqa2, irqb1, irqb2,
porta_ddr, portb_ddr,
porta_data, portb_data,
porta_ctrl, portb_ctrl,
pa, pb )
variable count : integer;
begin
data_out <= "00000000";
porta_read <= '0';
portb_read <= '0';
case addr is
when "00" =>
for count in 0 to 7 loop
if porta_ctrl(2) = '0' then
data_out(count) <= porta_ddr(count);
porta_read <= '0';
else
if porta_ddr(count) = '1' then
data_out(count) <= porta_data(count);
else
data_out(count) <= pa(count);
end if;
porta_read <= cs;
end if;
end loop;
portb_read <= '0';
when "01" =>
data_out <= irqa1 & irqa2 & porta_ctrl;
porta_read <= '0';
portb_read <= '0';
when "10" =>
for count in 0 to 7 loop
if portb_ctrl(2) = '0' then
data_out(count) <= portb_ddr(count);
portb_read <= '0';
else
if portb_ddr(count) = '1' then
data_out(count) <= portb_data(count);
else
data_out(count) <= pb(count);
end if;
portb_read <= cs;
end if;
end loop;
porta_read <= '0';
when "11" =>
data_out <= irqb1 & irqb2 & portb_ctrl;
porta_read <= '0';
portb_read <= '0';
when others =>
null;
end case;
end process;
---------------------------------
--
-- Write I/O ports
--
---------------------------------
pia_write : process( clk, rst, addr, cs, rw, data_in,
porta_ctrl, portb_ctrl,
porta_data, portb_data,
porta_ctrl, portb_ctrl,
porta_ddr, portb_ddr )
begin
if rst = '1' then
porta_ddr <= "00000000";
porta_data <= "00000000";
porta_ctrl <= "000000";
portb_ddr <= "00000000";
portb_data <= "00000000";
portb_ctrl <= "000000";
portb_write <= '0';
elsif clk'event and clk = '1' then
if cs = '1' and rw = '0' then
case addr is
when "00" =>
if porta_ctrl(2) = '0' then
porta_ddr <= data_in;
porta_data <= porta_data;
else
porta_ddr <= porta_ddr;
porta_data <= data_in;
end if;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
when "01" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= data_in(5 downto 0);
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
when "10" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
if portb_ctrl(2) = '0' then
portb_ddr <= data_in;
portb_data <= portb_data;
portb_write <= '0';
else
portb_ddr <= portb_ddr;
portb_data <= data_in;
portb_write <= '1';
end if;
portb_ctrl <= portb_ctrl;
when "11" =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= data_in(5 downto 0);
portb_write <= '0';
when others =>
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_ddr <= portb_ddr;
portb_data <= portb_data;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
end case;
else
porta_ddr <= porta_ddr;
porta_data <= porta_data;
porta_ctrl <= porta_ctrl;
portb_data <= portb_data;
portb_ddr <= portb_ddr;
portb_ctrl <= portb_ctrl;
portb_write <= '0';
end if;
end if;
end process;
---------------------------------
--
-- CA1 Edge detect
--
---------------------------------
ca1_input : process( clk, rst, ca1, ca1_del,
ca1_rise, ca1_fall, ca1_edge,
irqa1, porta_ctrl, porta_read )
begin
if rst = '1' then
ca1_del <= '0';
ca1_rise <= '0';
ca1_fall <= '0';
ca1_edge <= '0';
irqa1 <= '0';
elsif clk'event and clk = '0' then
ca1_del <= ca1;
ca1_rise <= (not ca1_del) and ca1;
ca1_fall <= ca1_del and (not ca1);
if ca1_edge = '1' then
irqa1 <= '1';
elsif porta_read = '1' then
irqa1 <= '0';
else
irqa1 <= irqa1;
end if;
end if;
if porta_ctrl(1) = '0' then
ca1_edge <= ca1_fall;
else
ca1_edge <= ca1_rise;
end if;
end process;
---------------------------------
--
-- CA2 Edge detect
--
---------------------------------
ca2_input : process( clk, rst, ca2, ca2_del,
ca2_rise, ca2_fall, ca2_edge,
irqa2, porta_ctrl, porta_read )
begin
if rst = '1' then
ca2_del <= '0';
ca2_rise <= '0';
ca2_fall <= '0';
ca2_edge <= '0';
irqa2 <= '0';
elsif clk'event and clk = '0' then
ca2_del <= ca2;
ca2_rise <= (not ca2_del) and ca2;
ca2_fall <= ca2_del and (not ca2);
if porta_ctrl(5) = '0' and ca2_edge = '1' then
irqa2 <= '1';
elsif porta_read = '1' then
irqa2 <= '0';
else
irqa2 <= irqa2;
end if;
end if;
if porta_ctrl(4) = '0' then
ca2_edge <= ca2_fall;
else
ca2_edge <= ca2_rise;
end if;
end process;
---------------------------------
--
-- CA2 output control
--
---------------------------------
ca2_output : process( clk, rst, porta_ctrl, porta_read, ca1_edge, ca2_out )
begin
if rst='1' then
ca2_out <= '0';
elsif clk'event and clk='0' then
case porta_ctrl(5 downto 3) is
when "100" => -- read PA clears, CA1 edge sets
if porta_read = '1' then
ca2_out <= '0';
elsif ca1_edge = '1' then
ca2_out <= '1';
else
ca2_out <= ca2_out;
end if;
when "101" => -- read PA clears, E sets
ca2_out <= not porta_read;
when "110" => -- set low
ca2_out <= '0';
when "111" => -- set high
ca2_out <= '1';
when others => -- no change
ca2_out <= ca2_out;
end case;
end if;
end process;
---------------------------------
--
-- CB1 Edge detect
--
---------------------------------
cb1_input : process( clk, rst, cb1, cb1_del,
cb1_rise, cb1_fall, cb1_edge,
irqb1, portb_ctrl, portb_read )
begin
if rst = '1' then
cb1_del <= '0';
cb1_rise <= '0';
cb1_fall <= '0';
cb1_edge <= '0';
irqb1 <= '0';
elsif clk'event and clk = '0' then
cb1_del <= cb1;
cb1_rise <= (not cb1_del) and cb1;
cb1_fall <= cb1_del and (not cb1);
if cb1_edge = '1' then
irqb1 <= '1';
elsif portb_read = '1' then
irqb1 <= '0';
else
irqb1 <= irqb1;
end if;
end if;
if portb_ctrl(1) = '0' then
cb1_edge <= cb1_fall;
else
cb1_edge <= cb1_rise;
end if;
end process;
---------------------------------
--
-- CB2 Edge detect
--
---------------------------------
cb2_input : process( clk, rst, cb2, cb2_del,
cb2_rise, cb2_fall, cb2_edge,
irqb2, portb_ctrl, portb_read )
begin
if rst = '1' then
cb2_del <= '0';
cb2_rise <= '0';
cb2_fall <= '0';
cb2_edge <= '0';
irqb2 <= '0';
elsif clk'event and clk = '0' then
cb2_del <= cb2;
cb2_rise <= (not cb2_del) and cb2;
cb2_fall <= cb2_del and (not cb2);
if portb_ctrl(5) = '0' and cb2_edge = '1' then
irqb2 <= '1';
elsif portb_read = '1' then
irqb2 <= '0';
else
irqb2 <= irqb2;
end if;
end if;
if portb_ctrl(4) = '0' then
cb2_edge <= cb2_fall;
else
cb2_edge <= cb2_rise;
end if;
end process;
---------------------------------
--
-- CB2 output control
--
---------------------------------
cb2_output : process( clk, rst, portb_ctrl, portb_write, cb1_edge, cb2_out )
begin
if rst='1' then
cb2_out <= '0';
elsif clk'event and clk='0' then
case portb_ctrl(5 downto 3) is
when "100" => -- write PB clears, CA1 edge sets
if portb_write = '1' then
cb2_out <= '0';
elsif cb1_edge = '1' then
cb2_out <= '1';
else
cb2_out <= cb2_out;
end if;
when "101" => -- write PB clears, E sets
cb2_out <= not portb_write;
when "110" => -- set low
cb2_out <= '0';
when "111" => -- set high
cb2_out <= '1';
when others => -- no change
cb2_out <= cb2_out;
end case;
end if;
end process;
---------------------------------
--
-- IRQ control
--
---------------------------------
pia_irq : process( irqa1, irqa2, irqb1, irqb2, porta_ctrl, portb_ctrl )
begin
irqa <= (irqa1 and porta_ctrl(0)) or (irqa2 and porta_ctrl(3));
irqb <= (irqb1 and portb_ctrl(0)) or (irqb2 and portb_ctrl(3));
end process;
---------------------------------
--
-- 2 x 74193 binary down counter
--
---------------------------------
--
-- On the reference 6809 board,
-- RTI takes one more clock cycle than System09
-- So subtract 1 from the porta_data preset value.
-- 11th July 2006 John Kent
-- RTI in CPU09 has been extended by one bus cycle
-- so remove the subtract by one offset on porta_data
--
pia_counter : process( clk, timer, porta_data, ca2_out, cb2_out)
begin
if cb2_out = '1' then
timer <= "00000000";
elsif ca2_out = '0' then
-- timer <= porta_data - "00000001";
timer <= porta_data;
elsif clk'event and clk='1' then
timer <= timer - "00000001";
end if;
pa <= "00000000";
pb <= timer;
ca1 <= timer(7);
cb1 <= timer(7);
ca2 <= '0';
cb2 <= '0';
end process;
end pia_arch;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00177.vhd
|
1
|
8979
|
-- NEED RESULT: ARCH00177.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00177: One inertial transaction occurred on signal asg with indexed name prefixed by a selected name on LHS passed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00177
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00177(ARCH00177)
-- ENT00177_Test_Bench(ARCH00177_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00177 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00177 ;
--
architecture ARCH00177 of ENT00177 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00177.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00177" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <= transport
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00177" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 10 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 20 ns,
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 30 ns,
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_2.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00177" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) <=
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_rec3.f3 (
s_st_rec3.f3'Left(1),s_st_rec3.f3'Left(2)) =
c_st_rec3_1.f3 (
s_st_rec3.f3'Right(1),s_st_rec3.f3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00177" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00177" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by a selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
--
end ARCH00177 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00177_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00177_Test_Bench ;
--
architecture ARCH00177_Test_Bench of ENT00177_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00177 ( ARCH00177 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
) ;
end block L1 ;
end ARCH00177_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00002.vhd
|
1
|
1858
|
-- NEED RESULT: ENT00002: 'begin' may be present in entity declarations passed
-- NEED RESULT: ENT00002_1: 'begin' may be absent in entity declarations passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00002
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00002(ARCH00002)
-- ENT00002_1(ARCH00002_1)
-- ENT00002_Test_Bench(ARCH00002_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00002 is
begin
end ENT00002 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00002_1 is
end ENT00002_1 ;
architecture ARCH00002 of ENT00002 is
begin
process
begin
test_report ( "ENT00002" ,
"'begin' may be present in entity declarations" ,
true ) ;
wait ;
end process ;
end ARCH00002 ;
architecture ARCH00002_1 of ENT00002_1 is
begin
process
begin
test_report ( "ENT00002_1" ,
"'begin' may be absent in entity declarations" ,
true ) ;
wait ;
end process ;
end ARCH00002_1 ;
entity ENT00002_Test_Bench is
end ENT00002_Test_Bench ;
architecture ARCH00002_Test_Bench of ENT00002_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00002 ( ARCH00002 ) ;
for CIS2 : UUT use entity WORK.ENT00002_1 ( ARCH00002_1 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
end block L1 ;
end ARCH00002_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00669.vhd
|
1
|
7610
|
-- NEED RESULT: ARCH00669: Variable default initial values - generic subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00669
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (1)
-- 4.3.1.3 (2)
-- 4.3.1.3 (3)
-- 4.3.1.3 (4)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00669)
-- ENT00669_Test_Bench(ARCH00669_Test_Bench)
--
-- REVISION HISTORY:
--
-- 01-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
--
architecture ARCH00669 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
variable va_boolean_1 : boolean ;
variable va_boolean_2 : boolean
:= d_boolean ;
variable va_bit_1 : bit ;
variable va_bit_2 : bit
:= d_bit ;
variable va_severity_level_1 : severity_level ;
variable va_severity_level_2 : severity_level
:= d_severity_level ;
variable va_character_1 : character ;
variable va_character_2 : character
:= d_character ;
variable va_t_enum1_1 : t_enum1 ;
variable va_t_enum1_2 : t_enum1
:= d_t_enum1 ;
variable va_st_enum1_1 : st_enum1 ;
variable va_st_enum1_2 : st_enum1
:= d_st_enum1 ;
variable va_integer_1 : integer ;
variable va_integer_2 : integer
:= d_integer ;
variable va_t_int1_1 : t_int1 ;
variable va_t_int1_2 : t_int1
:= d_t_int1 ;
variable va_st_int1_1 : st_int1 ;
variable va_st_int1_2 : st_int1
:= d_st_int1 ;
variable va_time_1 : time ;
variable va_time_2 : time
:= d_time ;
variable va_t_phys1_1 : t_phys1 ;
variable va_t_phys1_2 : t_phys1
:= d_t_phys1 ;
variable va_st_phys1_1 : st_phys1 ;
variable va_st_phys1_2 : st_phys1
:= d_st_phys1 ;
variable va_real_1 : real ;
variable va_real_2 : real
:= d_real ;
variable va_t_real1_1 : t_real1 ;
variable va_t_real1_2 : t_real1
:= d_t_real1 ;
variable va_st_real1_1 : st_real1 ;
variable va_st_real1_2 : st_real1
:= d_st_real1 ;
variable va_st_bit_vector_1 : st_bit_vector ;
variable va_st_bit_vector_2 : st_bit_vector
:= d_st_bit_vector ;
variable va_st_string_1 : st_string ;
variable va_st_string_2 : st_string
:= d_st_string ;
variable va_t_rec1_1 : t_rec1 ;
variable va_t_rec1_2 : t_rec1
:= d_t_rec1 ;
variable va_st_rec1_1 : st_rec1 ;
variable va_st_rec1_2 : st_rec1
:= d_st_rec1 ;
variable va_t_rec2_1 : t_rec2 ;
variable va_t_rec2_2 : t_rec2
:= d_t_rec2 ;
variable va_st_rec2_1 : st_rec2 ;
variable va_st_rec2_2 : st_rec2
:= d_st_rec2 ;
variable va_t_rec3_1 : t_rec3 ;
variable va_t_rec3_2 : t_rec3
:= d_t_rec3 ;
variable va_st_rec3_1 : st_rec3 ;
variable va_st_rec3_2 : st_rec3
:= d_st_rec3 ;
variable va_st_arr1_1 : st_arr1 ;
variable va_st_arr1_2 : st_arr1
:= d_st_arr1 ;
variable va_st_arr2_1 : st_arr2 ;
variable va_st_arr2_2 : st_arr2
:= d_st_arr2 ;
variable va_st_arr3_1 : st_arr3 ;
variable va_st_arr3_2 : st_arr3
:= d_st_arr3 ;
begin
correct := correct and
va_boolean_1 = va_boolean_2 and
va_boolean_2 = d_boolean ;
correct := correct and
va_bit_1 = va_bit_2 and
va_bit_2 = d_bit ;
correct := correct and
va_severity_level_1 = va_severity_level_2 and
va_severity_level_2 = d_severity_level ;
correct := correct and
va_character_1 = va_character_2 and
va_character_2 = d_character ;
correct := correct and
va_t_enum1_1 = va_t_enum1_2 and
va_t_enum1_2 = d_t_enum1 ;
correct := correct and
va_st_enum1_1 = va_st_enum1_2 and
va_st_enum1_2 = d_st_enum1 ;
correct := correct and
va_integer_1 = va_integer_2 and
va_integer_2 = d_integer ;
correct := correct and
va_t_int1_1 = va_t_int1_2 and
va_t_int1_2 = d_t_int1 ;
correct := correct and
va_st_int1_1 = va_st_int1_2 and
va_st_int1_2 = d_st_int1 ;
correct := correct and
va_time_1 = va_time_2 and
va_time_2 = d_time ;
correct := correct and
va_t_phys1_1 = va_t_phys1_2 and
va_t_phys1_2 = d_t_phys1 ;
correct := correct and
va_st_phys1_1 = va_st_phys1_2 and
va_st_phys1_2 = d_st_phys1 ;
correct := correct and
va_real_1 = va_real_2 and
va_real_2 = d_real ;
correct := correct and
va_t_real1_1 = va_t_real1_2 and
va_t_real1_2 = d_t_real1 ;
correct := correct and
va_st_real1_1 = va_st_real1_2 and
va_st_real1_2 = d_st_real1 ;
correct := correct and
va_st_bit_vector_1 = va_st_bit_vector_2 and
va_st_bit_vector_2 = d_st_bit_vector ;
correct := correct and
va_st_string_1 = va_st_string_2 and
va_st_string_2 = d_st_string ;
correct := correct and
va_t_rec1_1 = va_t_rec1_2 and
va_t_rec1_2 = d_t_rec1 ;
correct := correct and
va_st_rec1_1 = va_st_rec1_2 and
va_st_rec1_2 = d_st_rec1 ;
correct := correct and
va_t_rec2_1 = va_t_rec2_2 and
va_t_rec2_2 = d_t_rec2 ;
correct := correct and
va_st_rec2_1 = va_st_rec2_2 and
va_st_rec2_2 = d_st_rec2 ;
correct := correct and
va_t_rec3_1 = va_t_rec3_2 and
va_t_rec3_2 = d_t_rec3 ;
correct := correct and
va_st_rec3_1 = va_st_rec3_2 and
va_st_rec3_2 = d_st_rec3 ;
correct := correct and
va_st_arr1_1 = va_st_arr1_2 and
va_st_arr1_2 = d_st_arr1 ;
correct := correct and
va_st_arr2_1 = va_st_arr2_2 and
va_st_arr2_2 = d_st_arr2 ;
correct := correct and
va_st_arr3_1 = va_st_arr3_2 and
va_st_arr3_2 = d_st_arr3 ;
test_report ( "ARCH00669" ,
"Variable default initial values - generic subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00669 ;
--
entity ENT00669_Test_Bench is
end ENT00669_Test_Bench ;
--
architecture ARCH00669_Test_Bench of ENT00669_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00669 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00669_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00031.vhd
|
1
|
50570
|
-- NEED RESULT: ARCH00031.P1: Target of a variable assignment may be a aggregate of simple names passed
-- NEED RESULT: ARCH00031.P2: Target of a variable assignment may be a aggregate of simple names passed
-- NEED RESULT: ARCH00031.P3: Target of a variable assignment may be a aggregate of simple names passed
-- NEED RESULT: ARCH00031.P4: Target of a variable assignment may be a aggregate of simple names passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00031
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00031)
-- ENT00031_Test_Bench(ARCH00031_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00031 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
test_report ( "ARCH00031.P1" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00031.P2" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
test_report ( "ARCH00031.P3" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
type arr_boolean is
array (integer range -1 downto - 3 ) of
boolean ;
type arr_bit is
array (integer range -1 downto - 3 ) of
bit ;
type arr_severity_level is
array (integer range -1 downto - 3 ) of
severity_level ;
type arr_character is
array (integer range -1 downto - 3 ) of
character ;
type arr_st_enum1 is
array (integer range -1 downto - 3 ) of
st_enum1 ;
type arr_integer is
array (integer range -1 downto - 3 ) of
integer ;
type arr_st_int1 is
array (integer range -1 downto - 3 ) of
st_int1 ;
type arr_time is
array (integer range -1 downto - 3 ) of
time ;
type arr_st_phys1 is
array (integer range -1 downto - 3 ) of
st_phys1 ;
type arr_real is
array (integer range -1 downto - 3 ) of
real ;
type arr_st_real1 is
array (integer range -1 downto - 3 ) of
st_real1 ;
type arr_st_rec1 is
array (integer range -1 downto - 3 ) of
st_rec1 ;
type arr_st_rec2 is
array (integer range -1 downto - 3 ) of
st_rec2 ;
type arr_st_rec3 is
array (integer range -1 downto - 3 ) of
st_rec3 ;
type arr_st_arr1 is
array (integer range -1 downto - 3 ) of
st_arr1 ;
type arr_st_arr2 is
array (integer range -1 downto - 3 ) of
st_arr2 ;
type arr_st_arr3 is
array (integer range -1 downto - 3 ) of
st_arr3 ;
--
variable v_boolean_1 : boolean :=
c_boolean_1 ;
variable v_bit_1 : bit :=
c_bit_1 ;
variable v_severity_level_1 : severity_level :=
c_severity_level_1 ;
variable v_character_1 : character :=
c_character_1 ;
variable v_st_enum1_1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_1 : integer :=
c_integer_1 ;
variable v_st_int1_1 : st_int1 :=
c_st_int1_1 ;
variable v_time_1 : time :=
c_time_1 ;
variable v_st_phys1_1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_1 : real :=
c_real_1 ;
variable v_st_real1_1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_1 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_1 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_1 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_1 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_2 : boolean :=
c_boolean_1 ;
variable v_bit_2 : bit :=
c_bit_1 ;
variable v_severity_level_2 : severity_level :=
c_severity_level_1 ;
variable v_character_2 : character :=
c_character_1 ;
variable v_st_enum1_2 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_2 : integer :=
c_integer_1 ;
variable v_st_int1_2 : st_int1 :=
c_st_int1_1 ;
variable v_time_2 : time :=
c_time_1 ;
variable v_st_phys1_2 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_2 : real :=
c_real_1 ;
variable v_st_real1_2 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_2 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_2 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_2 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_2 : st_arr3 :=
c_st_arr3_1 ;
--
variable v_boolean_3 : boolean :=
c_boolean_1 ;
variable v_bit_3 : bit :=
c_bit_1 ;
variable v_severity_level_3 : severity_level :=
c_severity_level_1 ;
variable v_character_3 : character :=
c_character_1 ;
variable v_st_enum1_3 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer_3 : integer :=
c_integer_1 ;
variable v_st_int1_3 : st_int1 :=
c_st_int1_1 ;
variable v_time_3 : time :=
c_time_1 ;
variable v_st_phys1_3 : st_phys1 :=
c_st_phys1_1 ;
variable v_real_3 : real :=
c_real_1 ;
variable v_st_real1_3 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1_3 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2_3 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3_3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1_3 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2_3 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3_3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
v_boolean_2 : inout boolean
; v_bit_2 : inout bit
; v_severity_level_2 : inout severity_level
; v_character_2 : inout character
; v_st_enum1_2 : inout st_enum1
; v_integer_2 : inout integer
; v_st_int1_2 : inout st_int1
; v_time_2 : inout time
; v_st_phys1_2 : inout st_phys1
; v_real_2 : inout real
; v_st_real1_2 : inout st_real1
; v_st_rec1_2 : inout st_rec1
; v_st_rec2_2 : inout st_rec2
; v_st_rec3_2 : inout st_rec3
; v_st_arr1_2 : inout st_arr1
; v_st_arr2_2 : inout st_arr2
; v_st_arr3_2 : inout st_arr3
)
is
begin
( v_boolean_1
, v_boolean_2
, v_boolean_3
) := arr_boolean ' (
(Others => c_boolean_2)) ;
--
( v_bit_1
, v_bit_2
, v_bit_3
) := arr_bit ' (
(Others => c_bit_2)) ;
--
( v_severity_level_1
, v_severity_level_2
, v_severity_level_3
) := arr_severity_level ' (
(Others => c_severity_level_2)) ;
--
( v_character_1
, v_character_2
, v_character_3
) := arr_character ' (
(Others => c_character_2)) ;
--
( v_st_enum1_1
, v_st_enum1_2
, v_st_enum1_3
) := arr_st_enum1 ' (
(Others => c_st_enum1_2)) ;
--
( v_integer_1
, v_integer_2
, v_integer_3
) := arr_integer ' (
(Others => c_integer_2)) ;
--
( v_st_int1_1
, v_st_int1_2
, v_st_int1_3
) := arr_st_int1 ' (
(Others => c_st_int1_2)) ;
--
( v_time_1
, v_time_2
, v_time_3
) := arr_time ' (
(Others => c_time_2)) ;
--
( v_st_phys1_1
, v_st_phys1_2
, v_st_phys1_3
) := arr_st_phys1 ' (
(Others => c_st_phys1_2)) ;
--
( v_real_1
, v_real_2
, v_real_3
) := arr_real ' (
(Others => c_real_2)) ;
--
( v_st_real1_1
, v_st_real1_2
, v_st_real1_3
) := arr_st_real1 ' (
(Others => c_st_real1_2)) ;
--
( v_st_rec1_1
, v_st_rec1_2
, v_st_rec1_3
) := arr_st_rec1 ' (
(Others => c_st_rec1_2)) ;
--
( v_st_rec2_1
, v_st_rec2_2
, v_st_rec2_3
) := arr_st_rec2 ' (
(Others => c_st_rec2_2)) ;
--
( v_st_rec3_1
, v_st_rec3_2
, v_st_rec3_3
) := arr_st_rec3 ' (
(Others => c_st_rec3_2)) ;
--
( v_st_arr1_1
, v_st_arr1_2
, v_st_arr1_3
) := arr_st_arr1 ' (
(Others => c_st_arr1_2)) ;
--
( v_st_arr2_1
, v_st_arr2_2
, v_st_arr2_3
) := arr_st_arr2 ' (
(Others => c_st_arr2_2)) ;
--
( v_st_arr3_1
, v_st_arr3_2
, v_st_arr3_3
) := arr_st_arr3 ' (
(Others => c_st_arr3_2)) ;
--
--
end Proc1 ;
begin
Proc1 (
v_boolean_2
, v_bit_2
, v_severity_level_2
, v_character_2
, v_st_enum1_2
, v_integer_2
, v_st_int1_2
, v_time_2
, v_st_phys1_2
, v_real_2
, v_st_real1_2
, v_st_rec1_2
, v_st_rec2_2
, v_st_rec3_2
, v_st_arr1_2
, v_st_arr2_2
, v_st_arr3_2
) ;
correct := correct and
v_boolean_1 = c_boolean_2 ;
correct := correct and
v_bit_1 = c_bit_2 ;
correct := correct and
v_severity_level_1 = c_severity_level_2 ;
correct := correct and
v_character_1 = c_character_2 ;
correct := correct and
v_st_enum1_1 = c_st_enum1_2 ;
correct := correct and
v_integer_1 = c_integer_2 ;
correct := correct and
v_st_int1_1 = c_st_int1_2 ;
correct := correct and
v_time_1 = c_time_2 ;
correct := correct and
v_st_phys1_1 = c_st_phys1_2 ;
correct := correct and
v_real_1 = c_real_2 ;
correct := correct and
v_st_real1_1 = c_st_real1_2 ;
correct := correct and
v_st_rec1_1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_1 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_1 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_1 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_1 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_2 = c_boolean_2 ;
correct := correct and
v_bit_2 = c_bit_2 ;
correct := correct and
v_severity_level_2 = c_severity_level_2 ;
correct := correct and
v_character_2 = c_character_2 ;
correct := correct and
v_st_enum1_2 = c_st_enum1_2 ;
correct := correct and
v_integer_2 = c_integer_2 ;
correct := correct and
v_st_int1_2 = c_st_int1_2 ;
correct := correct and
v_time_2 = c_time_2 ;
correct := correct and
v_st_phys1_2 = c_st_phys1_2 ;
correct := correct and
v_real_2 = c_real_2 ;
correct := correct and
v_st_real1_2 = c_st_real1_2 ;
correct := correct and
v_st_rec1_2 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_2 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_2 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_2 = c_st_arr3_2 ;
--
correct := correct and
v_boolean_3 = c_boolean_2 ;
correct := correct and
v_bit_3 = c_bit_2 ;
correct := correct and
v_severity_level_3 = c_severity_level_2 ;
correct := correct and
v_character_3 = c_character_2 ;
correct := correct and
v_st_enum1_3 = c_st_enum1_2 ;
correct := correct and
v_integer_3 = c_integer_2 ;
correct := correct and
v_st_int1_3 = c_st_int1_2 ;
correct := correct and
v_time_3 = c_time_2 ;
correct := correct and
v_st_phys1_3 = c_st_phys1_2 ;
correct := correct and
v_real_3 = c_real_2 ;
correct := correct and
v_st_real1_3 = c_st_real1_2 ;
correct := correct and
v_st_rec1_3 = c_st_rec1_2 ;
correct := correct and
v_st_rec2_3 = c_st_rec2_2 ;
correct := correct and
v_st_rec3_3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1_3 = c_st_arr1_2 ;
correct := correct and
v_st_arr2_3 = c_st_arr2_2 ;
correct := correct and
v_st_arr3_3 = c_st_arr3_2 ;
--
test_report ( "ARCH00031.P4" ,
"Target of a variable assignment may be a " &
"aggregate of simple names" ,
correct) ;
end process P4 ;
--
end ARCH00031 ;
--
entity ENT00031_Test_Bench is
end ENT00031_Test_Bench ;
--
architecture ARCH00031_Test_Bench of ENT00031_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00031 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00031_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00687.vhd
|
1
|
28802
|
-- NEED RESULT: ARCH00687: Allocators with dynamic composite subtype indication passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00687
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (2)
-- 7.3.6 (9)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00687)
-- ENT00687_Test_Bench(ARCH00687_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.test_report ;
architecture ARCH00687 of E00000 is
procedure p1 (
constant lowb : integer := 1 ;
constant highb : integer := 10 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0
--
) is
--
-- assertion: c_xxxxx_2 >= c_xxxxx_1
-- enumeration types
-- predefined
-- boolean
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
type boolean_vector is array (integer range <>) of boolean ;
subtype boolean_vector_range1 is integer range lowb to highb ;
subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ;
constant c_st_boolean_vector_1 : st_boolean_vector :=
(others => c_boolean_1) ;
constant c_st_boolean_vector_2 : st_boolean_vector :=
(others => c_boolean_2) ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
--
constant c_bit_vector_1 : bit_vector := B"0000" ;
constant c_bit_vector_2 : bit_vector := B"1111" ;
subtype bit_vector_range1 is integer range lowb to highb ;
subtype st_bit_vector is bit_vector (bit_vector_range1) ;
constant c_st_bit_vector_1 : st_bit_vector :=
(others => c_bit_1) ;
constant c_st_bit_vector_2 : st_bit_vector :=
(others => c_bit_2) ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
type severity_level_vector is array (integer range <>) of severity_level ;
subtype severity_level_vector_range1 is integer range lowb to highb ;
subtype st_severity_level_vector is
severity_level_vector (severity_level_vector_range1) ;
constant c_st_severity_level_vector_1 : st_severity_level_vector :=
(others => c_severity_level_1) ;
constant c_st_severity_level_vector_2 : st_severity_level_vector :=
(others => c_severity_level_2) ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
--
constant c_string_1 : string := "ABC0000" ;
constant c_string_2 : string := "ABC1111" ;
subtype string_range1 is integer range lowb to highb ;
subtype st_string is string (string_range1) ;
constant c_st_string_1 : st_string :=
(others => c_character_1) ;
constant c_st_string_2 : st_string :=
(others => c_character_2) ;
-- user defined enumeration
type t_enum1 is (en1, en2, en3, en4) ;
constant c_t_enum1_1 : t_enum1 := en1 ;
constant c_t_enum1_2 : t_enum1 := en2 ;
subtype st_enum1 is t_enum1 range en4 downto en1 ;
constant c_st_enum1_1 : st_enum1 := en1 ;
constant c_st_enum1_2 : st_enum1 := en2 ;
--
type enum1_vector is array (integer range <>) of st_enum1 ;
subtype enum1_vector_range1 is integer range lowb to highb ;
subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ;
constant c_st_enum1_vector_1 : st_enum1_vector :=
(others => c_st_enum1_1) ;
constant c_st_enum1_vector_2 : st_enum1_vector :=
(others => c_st_enum1_2) ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
type integer_vector is array (integer range <>) of integer ;
subtype integer_vector_range1 is integer range lowb to highb ;
subtype st_integer_vector is integer_vector (integer_vector_range1) ;
constant c_st_integer_vector_1 : st_integer_vector :=
(others => c_integer_1) ;
constant c_st_integer_vector_2 : st_integer_vector :=
(others => c_integer_2) ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
type int1_vector is array (integer range <>) of st_int1 ;
subtype int1_vector_range1 is integer range lowb to highb ;
subtype st_int1_vector is int1_vector (int1_vector_range1) ;
constant c_st_int1_vector_1 : st_int1_vector :=
(others => c_st_int1_1) ;
constant c_st_int1_vector_2 : st_int1_vector :=
(others => c_st_int1_2) ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
type time_vector is array (integer range <>) of time ;
subtype time_vector_range1 is integer range lowb to highb ;
subtype st_time_vector is time_vector (time_vector_range1) ;
constant c_st_time_vector_1 : st_time_vector :=
(others => c_time_1) ;
constant c_st_time_vector_2 : st_time_vector :=
(others => c_time_2) ;
--
-- user defined physical type
type t_phys1 is range -100 to 1000
units
phys1_1 ;
phys1_2 = 10 phys1_1 ;
phys1_3 = 10 phys1_2 ;
phys1_4 = 10 phys1_3 ;
phys1_5 = 10 phys1_4 ;
end units ;
--
constant c_t_phys1_1 : t_phys1 := phys1_1 ;
constant c_t_phys1_2 : t_phys1 := phys1_2 ;
subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ;
constant c_st_phys1_1 : st_phys1 := phys1_2 ;
constant c_st_phys1_2 : st_phys1 := phys1_3 ;
--
type phys1_vector is array (integer range <>) of st_phys1 ;
subtype phys1_vector_range1 is integer range lowb to highb ;
subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ;
constant c_st_phys1_vector_1 : st_phys1_vector :=
(others => c_st_phys1_1) ;
constant c_st_phys1_vector_2 : st_phys1_vector :=
(others => c_st_phys1_2) ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
type real_vector is array (integer range <>) of real ;
subtype real_vector_range1 is integer range lowb to highb ;
subtype st_real_vector is real_vector (real_vector_range1) ;
constant c_st_real_vector_1 : st_real_vector :=
(others => c_real_1) ;
constant c_st_real_vector_2 : st_real_vector :=
(others => c_real_2) ;
--
-- user defined floating type
type t_real1 is range 0.0 to 1000.0 ;
constant c_t_real1_1 : t_real1 := 0.0 ;
constant c_t_real1_2 : t_real1 := 1.0 ;
subtype st_real1 is t_real1 range 8.0 to 80.0 ;
constant c_st_real1_1 : st_real1 := 8.0 ;
constant c_st_real1_2 : st_real1 := 9.0 ;
--
type real1_vector is array (integer range <>) of st_real1 ;
subtype real1_vector_range1 is integer range lowb to highb ;
subtype st_real1_vector is real1_vector (real1_vector_range1) ;
constant c_st_real1_vector_1 : st_real1_vector :=
(others => c_st_real1_1) ;
constant c_st_real1_vector_2 : st_real1_vector :=
(others => c_st_real1_2) ;
-- composite types
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
type rec1_vector is array (integer range <>) of st_rec1 ;
subtype rec1_vector_range1 is integer range lowb to highb ;
subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ;
constant c_st_rec1_vector_1 : st_rec1_vector :=
(others => c_st_rec1_1) ;
constant c_st_rec1_vector_2 : st_rec1_vector :=
(others => c_st_rec1_2) ;
--
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
type rec2_vector is array (integer range <>) of st_rec2 ;
subtype rec2_vector_range1 is integer range lowb to highb ;
subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ;
constant c_st_rec2_vector_1 : st_rec2_vector :=
(others => c_st_rec2_1) ;
constant c_st_rec2_vector_2 : st_rec2_vector :=
(others => c_st_rec2_2) ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
type arr1_vector is array (integer range <>) of st_arr1 ;
subtype arr1_vector_range1 is integer range lowb to highb ;
subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ;
constant c_st_arr1_vector_1 : st_arr1_vector :=
(others => c_st_arr1_1) ;
constant c_st_arr1_vector_2 : st_arr1_vector :=
(others => c_st_arr1_2) ;
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
type arr2_vector is array (integer range <>) of st_arr2 ;
subtype arr2_vector_range1 is integer range lowb to highb ;
subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ;
constant c_st_arr2_vector_1 : st_arr2_vector :=
(others => c_st_arr2_1) ;
constant c_st_arr2_vector_2 : st_arr2_vector :=
(others => c_st_arr2_2) ;
--
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
type rec3_vector is array (integer range <>) of st_rec3 ;
subtype rec3_vector_range1 is integer range lowb to highb ;
subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ;
constant c_st_rec3_vector_1 : st_rec3_vector :=
(others => c_st_rec3_1) ;
constant c_st_rec3_vector_2 : st_rec3_vector :=
(others => c_st_rec3_2) ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
type arr3_vector is array (integer range <>) of st_arr3 ;
subtype arr3_vector_range1 is integer range lowb to highb ;
subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ;
constant c_st_arr3_vector_1 : st_arr3_vector :=
(others => c_st_arr3_1) ;
constant c_st_arr3_vector_2 : st_arr3_vector :=
(others => c_st_arr3_2) ;
--
constant d_boolean : boolean := boolean'left ;
constant d_bit : bit := bit'left ;
constant d_severity_level : severity_level := severity_level'left ;
constant d_character : character := character'left ;
constant d_t_enum1 : t_enum1 := t_enum1'left ;
constant d_st_enum1 : st_enum1 := st_enum1'left ;
constant d_integer : integer := integer'left ;
constant d_t_int1 : t_int1 := t_int1'left ;
constant d_st_int1 : st_int1 := st_int1'left ;
constant d_time : time := time'left ;
constant d_t_phys1 : t_phys1 := t_phys1'left ;
constant d_st_phys1 : st_phys1 := st_phys1'left ;
constant d_real : real := real'left ;
constant d_t_real1 : t_real1 := t_real1'left ;
constant d_st_real1 : st_real1 := st_real1'left ;
constant d_st_bit_vector : st_bit_vector :=
(others => bit'left) ;
constant d_st_string : st_string :=
(others => character'left) ;
constant d_t_rec1 : t_rec1 :=
(lowb_i2, time'left, boolean'left, real'left) ;
constant d_st_rec1 : st_rec1 :=
(lowb_i2, time'left, boolean'left, real'left) ;
constant d_t_rec2 : t_rec2 :=
(boolean'left, d_st_rec1, time'left) ;
constant d_st_rec2 : st_rec2 :=
(boolean'left, d_st_rec1, time'left) ;
constant d_st_arr1 : st_arr1 :=
(others => st_int1'left) ;
constant d_st_arr2 : st_arr2 :=
(others => (others => d_st_arr1) ) ;
constant d_t_rec3 : t_rec3 :=
(boolean'left, d_st_rec2, d_st_arr2) ;
constant d_st_rec3 : st_rec3 :=
(boolean'left, d_st_rec2, d_st_arr2) ;
constant d_st_arr3 : st_arr3 :=
(others => (others => d_st_rec3) ) ;
-- enumeration types
-- predefined
-- boolean
function bf_boolean(to_resolve : boolean_vector) return boolean is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return boolean'left ;
else
for i in to_resolve'range loop
sum := sum + boolean'pos(to_resolve(i)) ;
end loop ;
return boolean'val(integer'pos(sum) mod
(boolean'pos(boolean'high) + 1)) ;
end if ;
end bf_boolean ;
--
--
-- bit
function bf_bit(to_resolve : bit_vector) return bit is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return bit'left ;
else
for i in to_resolve'range loop
sum := sum + bit'pos(to_resolve(i)) ;
end loop ;
return bit'val(integer'pos(sum) mod
(bit'pos(bit'high) + 1)) ;
end if ;
end bf_bit ;
--
-- severity_level
function bf_severity_level(to_resolve : severity_level_vector)
return severity_level is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return severity_level'left ;
else
for i in to_resolve'range loop
sum := sum + severity_level'pos(to_resolve(i)) ;
end loop ;
return severity_level'val(integer'pos(sum) mod
(severity_level'pos(severity_level'high) + 1)) ;
end if ;
end bf_severity_level ;
--
-- character
function bf_character(to_resolve : string) return character is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return character'left ;
else
for i in to_resolve'range loop
sum := sum + character'pos(to_resolve(i)) ;
end loop ;
return character'val(integer'pos(sum) mod
(character'pos(character'high) + 1)) ;
end if ;
end bf_character ;
--
--
-- user defined enumeration
function bf_enum1(to_resolve : enum1_vector) return st_enum1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_enum1'left ;
else
for i in to_resolve'range loop
sum := sum + t_enum1'pos(to_resolve(i)) ;
end loop ;
return t_enum1'val(integer'pos(sum) mod
(t_enum1'pos(t_enum1'high) + 1)) ;
end if ;
end bf_enum1 ;
--
--
-- integer types
-- predefined
function bf_integer(to_resolve : integer_vector) return integer is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return integer'left ;
else
for i in to_resolve'range loop
sum := sum + integer'pos(to_resolve(i)) ;
end loop ;
return sum ;
end if ;
end bf_integer ;
--
--
-- user defined integer type
function bf_int1(to_resolve : int1_vector) return st_int1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return st_int1'left ;
else
for i in to_resolve'range loop
sum := sum + t_int1'pos(to_resolve(i)) ;
end loop ;
return t_int1'val(integer'pos(sum) mod
(t_int1'pos(t_int1'high) + 1)) ;
end if ;
end bf_int1 ;
--
--
-- physical types
-- predefined
function bf_time(to_resolve : time_vector) return time is
variable sum : time := 0 fs;
begin
if to_resolve'length = 0 then
return time'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_time ;
--
--
-- user defined physical type
function bf_phys1(to_resolve : phys1_vector) return st_phys1 is
variable sum : integer := 0 ;
begin
if to_resolve'length = 0 then
return c_st_phys1_1 ;
else
for i in to_resolve'range loop
sum := sum + t_phys1'pos(to_resolve(i)) ;
end loop ;
return t_phys1'val(integer'pos(sum) mod
(t_phys1'pos(t_phys1'high) + 1)) ;
end if ;
end bf_phys1 ;
--
--
-- floating point types
-- predefined
function bf_real(to_resolve : real_vector) return real is
variable sum : real := 0.0 ;
begin
if to_resolve'length = 0 then
return real'left ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real ;
--
--
-- user defined floating type
function bf_real1(to_resolve : real1_vector) return st_real1 is
variable sum : t_real1 := 0.0 ;
begin
if to_resolve'length = 0 then
return c_st_real1_1 ;
else
for i in to_resolve'range loop
sum := sum + to_resolve(i) ;
end loop ;
return sum ;
end if ;
end bf_real1 ;
--
--
-- composite types
--
-- simple record
function bf_rec1(to_resolve : rec1_vector) return st_rec1 is
variable f1array : integer_vector (to_resolve'range) ;
variable f2array : time_vector (to_resolve'range) ;
variable f3array : boolean_vector (to_resolve'range) ;
variable f4array : real_vector (to_resolve'range) ;
variable result : st_rec1 ;
begin
if to_resolve'length = 0 then
return c_st_rec1_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
f4array(i) := to_resolve(i).f4 ;
end loop ;
result.f1 := bf_integer(f1array) ;
result.f2 := bf_time(f2array) ;
result.f3 := bf_boolean(f3array) ;
result.f4 := bf_real(f4array) ;
return result ;
end if ;
end bf_rec1 ;
--
--
-- more complex record
function bf_rec2(to_resolve : rec2_vector) return st_rec2 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec1_vector (to_resolve'range) ;
variable f3array : time_vector (to_resolve'range) ;
variable result : st_rec2 ;
begin
if to_resolve'length = 0 then
return c_st_rec2_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec1(f2array) ;
result.f3 := bf_time(f3array) ;
return result ;
end if ;
end bf_rec2 ;
--
--
-- simple array
function bf_arr1(to_resolve : arr1_vector) return st_arr1 is
variable temp : int1_vector (to_resolve'range) ;
variable result : st_arr1 ;
begin
if to_resolve'length = 0 then
return c_st_arr1_1 ;
else
for i in st_arr1'range loop
for j in to_resolve'range(1) loop
temp(j) := to_resolve(j)(i) ;
end loop;
result(i) := bf_int1(temp) ;
end loop ;
return result ;
end if ;
end bf_arr1 ;
--
--
-- more complex array
function bf_arr2(to_resolve : arr2_vector) return st_arr2 is
variable temp : arr1_vector (to_resolve'range) ;
variable result : st_arr2 ;
begin
if to_resolve'length = 0 then
return c_st_arr2_1 ;
else
for i in st_arr2'range(1) loop
for j in st_arr2'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_arr1(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr2 ;
--
--
-- most complex record
function bf_rec3(to_resolve : rec3_vector) return st_rec3 is
variable f1array : boolean_vector (to_resolve'range) ;
variable f2array : rec2_vector (to_resolve'range) ;
variable f3array : arr2_vector (to_resolve'range) ;
variable result : st_rec3 ;
begin
if to_resolve'length = 0 then
return c_st_rec3_1 ;
else
for i in to_resolve'range loop
f1array(i) := to_resolve(i).f1 ;
f2array(i) := to_resolve(i).f2 ;
f3array(i) := to_resolve(i).f3 ;
end loop ;
result.f1 := bf_boolean(f1array) ;
result.f2 := bf_rec2(f2array) ;
result.f3 := bf_arr2(f3array) ;
return result ;
end if ;
end bf_rec3 ;
--
--
-- most complex array
function bf_arr3(to_resolve : arr3_vector) return st_arr3 is
variable temp : rec3_vector (to_resolve'range) ;
variable result : st_arr3 ;
begin
if to_resolve'length = 0 then
return c_st_arr3_1 ;
else
for i in st_arr3'range(1) loop
for j in st_arr3'range(2) loop
for k in to_resolve'range loop
temp(k) := to_resolve(k)(i,j) ;
end loop ;
result(i, j) := bf_rec3(temp) ;
end loop ;
end loop ;
return result ;
end if ;
end bf_arr3 ;
--
variable correct : boolean := true ;
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
begin
correct := correct and
va_bit_vector_1.all = d_st_bit_vector ;
correct := correct and
va_string_1.all = d_st_string ;
correct := correct and
va_t_rec1_1.all = d_st_rec1 ;
correct := correct and
va_st_rec1_1.all = d_st_rec1 ;
correct := correct and
va_t_rec2_1.all = d_st_rec2 ;
correct := correct and
va_st_rec2_1.all = d_st_rec2 ;
correct := correct and
va_t_rec3_1.all = d_st_rec3 ;
correct := correct and
va_st_rec3_1.all = d_st_rec3 ;
correct := correct and
va_t_arr1_1.all = d_st_arr1 ;
correct := correct and
va_st_arr1_1.all = d_st_arr1 ;
correct := correct and
va_t_arr2_1.all = d_st_arr2 ;
correct := correct and
va_st_arr2_1.all = d_st_arr2 ;
correct := correct and
va_t_arr3_1.all = d_st_arr3 ;
correct := correct and
va_st_arr3_1.all = d_st_arr3 ;
test_report ( "ARCH00687" ,
"Allocators with dynamic composite subtype indication" ,
correct) ;
end p1 ;
begin
process
begin
p1 ;
wait ;
end process ;
end ARCH00687 ;
--
entity ENT00687_Test_Bench is
end ENT00687_Test_Bench ;
--
architecture ARCH00687_Test_Bench of ENT00687_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00687 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00687_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl/IEEE/old/misc.vhd
|
1
|
33966
|
--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--library SYNOPSYS;
--use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
--synopsys synthesis_off
--attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
end;
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 387
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 388
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 389
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_ULOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 390
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
return STD_LOGIC_VECTOR(Value);
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
-- pragma subpgm_id 391
begin
if V = 'Z' then
return vZ;
elsif V = 'U' then
return vU;
elsif V = '-' then
return vDC;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 392
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 393
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR is
-- pragma subpgm_id 394
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_LOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
-- pragma subpgm_id 395
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
elsif Value(i) = 'U' then
Result(i) := vU;
elsif Value(i) = '-' then
Result(i) := vDC;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 396
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 397
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: BIT_VECTOR (V'length-1 downto 0);
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result(i) := vU;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result(i) := vDC;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: - --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
-- pragma subpgm_id 398
variable Result: BIT;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: W --> 0"
severity WARNING;
end if;
when 'Z' =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
when 'U' =>
if ( Uflag ) then
Result := vU;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: U --> 0"
severity WARNING;
end if;
when '-' =>
if ( DCflag ) then
Result := vDC;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: - --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 399
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 400
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 401
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 402
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 403
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 404
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 405
variable result: STD_LOGIC;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 406
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 407
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 408
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 409
variable result: STD_LOGIC;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
-- pragma subpgm_id 410
begin
return not XOR_REDUCE(ARG);
end;
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 411
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
-- pragma subpgm_id 412
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
-- pragma subpgm_id 413
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
-- pragma subpgm_id 414
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
-- pragma subpgm_id 415
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
begin
return resolution_table(Input0, Input1);
end fun_WiredX;
--synopsys synthesis_on
end;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_write_fsm.vhd
|
9
|
61290
|
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`protect end_protected
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/logic_builtin.vhd
|
9
|
30405
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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UbOd4nCOWg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20768)
`protect data_block
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`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl/strconcat1.vhd
|
1
|
298
|
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture arch of ENT00001_Test_Bench is
signal s1 : integer := 33;
begin
terminator : process
begin
report "s1 = " & integer'image(s1);
assert false report "end of simulation" severity failure;
end process;
end;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00297.vhd
|
1
|
2010
|
-- NEED RESULT: ARCH00297: Predefined array types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00297
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 3.2.1.2 (1)
-- 3.2.1.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00297)
-- ENT00297_Test_Bench(ARCH00297_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00297 of E00000 is
begin
P :
process
variable alphabet : string (1 to 26) := "ABCDEFGHIJKLMNOPQRSTUVWXYZ" ;
variable very_short_string: string (1 to 1) := "!" ;
variable word : bit_vector (15 downto 0) := "1111000011110000" ;
variable byte : bit_vector (0 to 7) := "00110011" ;
begin
test_report ( "ARCH00297" ,
"Predefined array types" ,
(alphabet( 1) = 'A') and
(alphabet( 2) = 'B') and
(alphabet(25) = 'Y') and
(alphabet(26) = 'Z') and
(very_short_string(1) = '!') and
(word(15) = '1') and
(word(14) = '1') and
(word( 1) = '0') and
(byte( 0) = '0') and
(byte( 1) = '0') and
(byte( 6) = '1') and
(byte( 7) = '1')
) ;
wait ;
end process P ;
end ARCH00297 ;
entity ENT00297_Test_Bench is
end ENT00297_Test_Bench ;
architecture ARCH00297_Test_Bench of ENT00297_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00297 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00297_Test_Bench ;
|
gpl-3.0
|
dcliche/mdsynth
|
rtl/src/sound/envelope.vhd
|
1
|
3955
|
-- MDSynth Sound Chip
--
-- Copyright (c) 2016, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- ASDR Envelope
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity envelope is
port ( clk: in std_logic;
reset: in std_logic;
note_on: in std_logic;
attack_rate: in unsigned(3 downto 0);
release_rate: in unsigned(3 downto 0);
gain: out unsigned(5 downto 0);
phase: out std_logic_vector(1 downto 0));
end envelope;
architecture envelope_arch of envelope is
type phase_type is (
wait_phase,
attack_phase,
sustain_phase,
release_phase);
signal current_phase: phase_type := wait_phase;
signal current_gain: unsigned(25 downto 0); -- current_gain(25) is carry
begin
process (clk, reset)
begin
if (reset = '1') then
current_phase <= wait_phase;
current_gain <= to_unsigned(0, 26);
elsif (rising_edge(clk)) then
gain <= current_gain(24 downto 19);
case current_phase is
when wait_phase =>
phase <= "00";
if (note_on = '1') then
current_phase <= attack_phase;
end if;
when attack_phase =>
phase <= "01";
if (note_on = '1') then
if (current_gain(25) = '1') then
current_gain <= to_unsigned(33554431, 26);
current_phase <= sustain_phase;
else
current_gain <= current_gain + attack_rate;
end if;
else
current_phase <= release_phase;
end if;
when sustain_phase =>
phase <= "10";
if (note_on = '0') then
current_phase <= release_phase;
end if;
when release_phase =>
phase <= "11";
-- release
if (note_on = '1') then
-- We have a note on during release phase
-- Start a new attack phase
current_gain <= to_unsigned(0, 26);
current_phase <= attack_phase;
else
if (current_gain(25) = '1') then
current_gain <= to_unsigned(0, 26);
current_phase <= wait_phase;
else
current_gain <= current_gain - release_rate;
end if;
end if;
end case;
end if;
end process;
end envelope_arch;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00266.vhd
|
1
|
2926
|
-- NEED RESULT: ARCH00266: Configuration declarations may or may not have matching ending name passed
-- NEED RESULT: ARCH00266: Configuration declarations need not have configuration declarative items passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00266
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.3 (1)
-- 1.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00266(ARCH00266)
-- ENT00266_1(ARCH00266_1)
-- CONF00266
-- CONF00266_1
-- ENT00266_Test_Bench(ARCH00266_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
entity ENT00266 is
generic ( g3 : integer ) ;
port ( s3 : out integer ) ;
end ENT00266 ;
architecture ARCH00266 of ENT00266 is
component COMP1
end component ;
begin
C1 : COMP1;
end ARCH00266 ;
entity ENT00266_1 is
generic ( g1 : integer ) ;
port ( s1 : out integer ) ;
begin
end ENT00266_1 ;
architecture ARCH00266_1 of ENT00266_1 is
begin
s1 <= g1 ;
end ARCH00266_1 ;
configuration CONF00266 of WORK.ENT00266 is
for ARCH00266
for C1 : COMP1
use entity WORK.ENT00266_1 ( ARCH00266_1 )
generic map ( g3 )
port map ( s3 ) ;
end for ;
end for ;
end CONF00266 ;
configuration CONF00266_1 of WORK.ENT00266 is
for ARCH00266
for C1 : COMP1
use entity WORK.ENT00266_1 ( ARCH00266_1 )
generic map ( g3 )
port map ( s3 ) ;
end for ;
end for ;
end ;
use WORK.STANDARD_TYPES.all ;
entity ENT00266_Test_Bench is
end ENT00266_Test_Bench ;
architecture ARCH00266_Test_Bench of ENT00266_Test_Bench is
begin
L1:
block
constant c1 : integer := 5 ;
constant c2 : integer := 5 ;
signal s1, s2 : integer ;
component UUT
end component ;
for CIS1 : UUT use configuration WORK.CONF00266
generic map ( c1 )
port map ( s1 ) ;
for CIS2 : UUT use configuration WORK.CONF00266_1
generic map ( c2 )
port map ( s2 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
P00266 :
process ( s1, s2 )
begin
if s1 = c1 and s2 = c2 then
test_report ( "ARCH00266" ,
"Configuration declarations may or may not have"
& " matching ending name" ,
true ) ;
test_report ( "ARCH00266" ,
"Configuration declarations need not have"
& " configuration declarative items" ,
true ) ;
end if ;
end process P00266 ;
end block L1 ;
end ARCH00266_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00360.vhd
|
1
|
6015
|
-- NEED RESULT: ARCH00360.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00360: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00360: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00360
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00360(ARCH00360)
-- ENT00360_Test_Bench(ARCH00360_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00360 is
end ENT00360 ;
--
--
architecture ARCH00360 of ENT00360 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_arr1_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr1_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr1_vector_select : select_type := 1 ;
--
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
begin
CHG1 :
process ( s_st_arr1_vector )
variable correct : boolean ;
begin
case s_st_arr1_vector_cnt is
when 0
=> null ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00360.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_vector_select <= transport 2 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr1_vector_select <= transport 3 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00360" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00360" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00360" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr1_vector_savt <= transport Std.Standard.Now ;
chk_st_arr1_vector <= transport s_st_arr1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_vector_cnt <= transport s_st_arr1_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_arr1_vector(highb)(lowb to highb-1) <= transport
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns
when st_arr1_vector_select = 1 else
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when st_arr1_vector_select = 2 else
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
end ARCH00360 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00360_Test_Bench is
end ENT00360_Test_Bench ;
--
--
architecture ARCH00360_Test_Bench of ENT00360_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00360 ( ARCH00360 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00360_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00533.vhd
|
1
|
1761
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00533
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 14.1 (2)
-- 14.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00533)
-- ENT00533_Test_Bench(ARCH00533_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00533 of E00000 is
begin
P :
process
type ary is array ( integer range <> ) of integer ;
subtype st_ary is ary (1 to 10) ;
type rec is record
a,b : integer ;
end record ;
subtype st_rec is rec ;
attribute ary_attr : integer ;
attribute ary_attr of ary : type is 10 ;
attribute rec_attr : integer ;
attribute rec_attr of rec : type is 20 ;
begin
test_report ( "ARCH00533" ,
"Base attribute" ,
(ary'ary_attr = 10) and
(rec'rec_attr = 20) and
(t_enum1'base'leftof(en2) = en1) and
(st_enum1'rightof(en2) = en1) and
(st_enum1'base'leftof(en2) = en1) and
(t_int1'base'rightof(-1) = 0) and
(st_int1'base'leftof(1) = 0)
) ;
wait ;
end process P ;
end ARCH00533 ;
--
entity ENT00533_Test_Bench is
end ENT00533_Test_Bench ;
architecture ARCH00533_Test_Bench of ENT00533_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00533 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00533_Test_Bench ;
--
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00695.vhd
|
1
|
5439
|
-- NEED RESULT: ARCH00695: Type conversions in assoc. lists with out interface objects passed
-- NEED RESULT: ARCH00695: Type conversions in assoc. lists with out interface objects passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00695
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.3.2 (1)
-- 4.3.3.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00695
-- PKG00695/BODY
-- ENT00695(ARCH00695)
-- ENT00695_Test_Bench(ARCH00695_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
--
use WORK.STANDARD_TYPES.all ;
package PKG00695 is
function fintegertointeger ( P : integer ) return integer ;
function fintegertost_bit_vector ( P : integer ) return st_bit_vector ;
--
function fst_bit_vectortointeger ( P : st_bit_vector ) return integer ;
function fst_bit_vectortost_arr3 ( P : st_bit_vector ) return st_arr3 ;
--
function fst_arr3tost_bit_vector ( P : st_arr3 ) return st_bit_vector ;
function fst_arr3toboolean ( P : st_arr3 ) return boolean ;
--
function fbooleantost_arr3 ( P : boolean ) return st_arr3 ;
end PKG00695 ;
--
package body PKG00695 is
function fintegertointeger ( P : integer ) return integer is
begin
if P = c_integer_1 then
return c_integer_1 ;
else
return c_integer_2 ;
end if ;
end ;
function fintegertost_bit_vector ( P : integer ) return st_bit_vector is
begin
if P = c_integer_1 then
return c_st_bit_vector_1 ;
else
return c_st_bit_vector_2 ;
end if ;
end ;
--
function fst_bit_vectortointeger ( P : st_bit_vector ) return integer is
begin
if P = c_st_bit_vector_1 then
return c_integer_1 ;
else
return c_integer_2 ;
end if ;
end ;
function fst_bit_vectortost_arr3 ( P : st_bit_vector ) return st_arr3 is
begin
if P = c_st_bit_vector_1 then
return c_st_arr3_1 ;
else
return c_st_arr3_2 ;
end if ;
end ;
--
function fst_arr3tost_bit_vector ( P : st_arr3 ) return st_bit_vector is
begin
if P = c_st_arr3_1 then
return c_st_bit_vector_1 ;
else
return c_st_bit_vector_2 ;
end if ;
end ;
function fst_arr3toboolean ( P : st_arr3 ) return boolean is
begin
if P = c_st_arr3_1 then
return c_boolean_1 ;
else
return c_boolean_2 ;
end if ;
end ;
--
function fbooleantost_arr3 ( P : boolean ) return st_arr3 is
begin
if P = c_boolean_1 then
return c_st_arr3_1 ;
else
return c_st_arr3_2 ;
end if ;
end ;
end PKG00695 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00695.all ;
entity ENT00695 is
port (
signal s_st_arr3 : out st_arr3 ;
signal s2_integer : out integer
) ;
end ENT00695 ;
--
architecture ARCH00695 of ENT00695 is
procedure p1 (
variable v_boolean : out boolean ;
variable v2_integer : out integer
) is
variable correct : boolean := true ;
begin
v_boolean := c_boolean_2 ;
end p1 ;
begin
process
variable v_st_arr3 : st_arr3 ;
variable v2_integer : integer ;
begin
p1 (
fbooleantost_arr3
( v_boolean ) =>
v_st_arr3 ,
v2_integer =>
v2_integer
) ;
s_st_arr3 <= v_st_arr3 ;
s2_integer <= v2_integer ;
wait ;
end process ;
end ARCH00695 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00695.all ;
entity ENT00695_Test_Bench is
end ENT00695_Test_Bench ;
--
architecture ARCH00695_Test_Bench of ENT00695_Test_Bench is
begin
L1:
block
signal s_integer : integer := c_integer_1 ;
signal s2_integer : integer := c_integer_2 ;
signal toggle : boolean := false ;
component UUT
port (
signal s_st_bit_vector : out st_bit_vector ;
signal s2_integer : out integer
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00695 ( ARCH00695 )
port map (
fst_arr3tost_bit_vector
( s_st_arr3 ) =>
s_st_bit_vector ,
s2_integer =>
s2_integer
) ;
begin
toggle <= true ;
CIS1 : UUT
port map (
fst_bit_vectortointeger
( s_st_bit_vector ) =>
s_integer ,
s2_integer =>
s2_integer
) ;
process ( s2_integer, s_integer, toggle)
variable correct : boolean := true ;
begin
if toggle then
correct := correct and s_integer = c_integer_2 ;
test_report ( "ARCH00695" ,
"Type conversions in assoc. lists with out interface objects" ,
correct ) ;
end if ;
end process ;
end block L1 ;
end ARCH00695_Test_Bench ;
--
|
gpl-3.0
|
grwlf/vsim
|
vhdl/entity1.vhd
|
1
|
938
|
-- Simple entity test, in/out ports
entity main is
end entity main;
entity unit1 is
port (
inum : in integer;
oled : out integer);
end entity unit1;
architecture unit1_a of unit1 is
signal a : integer := 1;
begin
oled <= inum + a;
end architecture unit1_a;
architecture main of main is
constant CYCLES : integer := 100;
signal clk : integer := 0;
signal o1 : integer;
signal o2 : integer;
signal o : integer;
begin
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
end if;
end process;
u1:entity unit1(unit1_a) port map(inum=>clk, oled=>o1);
u2:entity unit1(unit1_a) port map(inum=>clk, oled=>o2);
clk <= clk + 1 after 1 us;
o <= o1 + o2;
reporter : process(o)
begin
report "o=" & integer'image(o);
end process;
end architecture main;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/pro000007.vhd
|
1
|
647
|
-------------------------------------------------------------------------------
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, wait-for.
entity ENT00003_Test_Bench is
end entity;
architecture ARCH00003_Test_Bench of ENT00003_Test_Bench is
signal tst : bit;
begin
process
begin
tst <= '0';
wait for 1 us;
tst <= '1';
wait for 1 us;
end process;
end ARCH00003_Test_Bench;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00223.vhd
|
1
|
5061
|
-- NEED RESULT: ENT00223: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00223: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00223: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00223: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00223
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00223(ARCH00223)
-- ENT00223_Test_Bench(ARCH00223_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00223 is
generic (G : integer) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00223 ;
--
--
architecture ARCH00223 of ENT00223 is
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
case counter is
when 0
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_2(1).f1 ;
s_st_rec3_vector(2).f2 <= transport
c_st_rec3_vector_2(2).f2 after 10 ns ;
wait until s_st_rec3_vector(2).f2 =
c_st_rec3_vector_2(2).f2 ;
Test_Report (
"ENT00223",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(2).f2 =
c_st_rec3_vector_2(2).f2 )) ;
--
when 1
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_1(1).f1 ;
s_st_rec3_vector(G).f2 <= transport
c_st_rec3_vector_2(G).f2 after 10 ns ;
wait until s_st_rec3_vector(G).f2 =
c_st_rec3_vector_2(G).f2 ;
Test_Report (
"ENT00223",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(G).f2 =
c_st_rec3_vector_2(G).f2 )) ;
--
when 2
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_2(1).f1 ;
s_st_rec3_vector(CG).f2 <= transport
c_st_rec3_vector_2(CG).f2 after 10 ns ;
wait until s_st_rec3_vector(CG).f2 =
c_st_rec3_vector_2(CG).f2 ;
Test_Report (
"ENT00223",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(CG).f2 =
c_st_rec3_vector_2(CG).f2 )) ;
--
when 3
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_1(1).f1 ;
s_st_rec3_vector(CG'Attr).f2 <= transport
c_st_rec3_vector_2(CG'Attr).f2 after 10 ns ;
wait until s_st_rec3_vector(CG'Attr).f2 =
c_st_rec3_vector_2(CG'Attr).f2 ;
Test_Report (
"ENT00223",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(CG'Attr).f2 =
c_st_rec3_vector_2(CG'Attr).f2 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_rec3_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00223 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00223_Test_Bench is
end ENT00223_Test_Bench ;
--
--
architecture ARCH00223_Test_Bench of ENT00223_Test_Bench is
begin
L1:
block
component UUT
generic (G : integer) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00223 ( ARCH00223 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
;
end block L1 ;
end ARCH00223_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/compare.vhd
|
9
|
11685
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
SC47WbDm2WnrYCHTmzsALGK0lcvqEtndfKnpUm/1Li8iGJv67zGxAH5r7t1K+mtqeqDMkuU0jk9O
Qw1TzRjzCw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jLkpnfppwLDLSuu/a6WMWvTJ9AXUpBVqeKeK4IcJiQy/6uuRD8fV6/tERFyvlG/UdJF/4sYiBKVF
wRg2zaR9QamYCA7sw6PSic+jxWW6+whSv3Tu9NBFe+/fuMxQ5PZMDAK6QG7JY18FWhtXKpYUx5KP
qrWS+3NUftPztLE7Z0w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gZ3yuuORF3u3liEnr1VR7TH8vY+EWZq7Ns5sUxBlSilcThMOhPg/JuMoYQ+w5nTi/7XGVa8pfqF9
WVxAOYepAxqhC6+wf7vcaatqH8RmkPC3tASzEthLz06b9zpjdh6UjykYbZUd5T6JxuhxoOLdNPj6
Ufx5TIW8GcUxPmc6nqIE+3mmTyynjXFZ27Y53vqazh0KXutx1KAs+3kqjY4HHn90cY+fs0cPMbi0
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jtoizc8frP13vPJP4G34VLmSMbYGe8Himnp4Hg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Yqf6+nAfPtFbxvhDlJTiBpJ72C9ti+zp19vAmQRjVODLsIa9qvrByHRh1OCrKVSsowMLBSgu5JBQ
87oulp32NcroYKLciVdd1o/nxHq05knHK7JCXdsJytb3gz8Fzutk0C+xjMHgvtH8m6uK5VFNwmSV
bUZaNyDRQvoraylOovI=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OyHCSvsx5p0fO3MzDTzcYYHxHBOrZaEjzlpGMhFbPOjBsUWPH+HJIV+bECmLGonEBpAvM28cK7Um
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Sa7+8311YLBnEpdn3669yqvxX4wJgm3AAGhPdQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6912)
`protect data_block
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QY9afbya/54/OxrzTRCi
`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00342.vhd
|
1
|
40119
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00342
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00342(ARCH00342)
-- ENT00342_Test_Bench(ARCH00342_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00342 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr2 : inout st_arr2
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
end ENT00342 ;
--
--
architecture ARCH00342 of ENT00342 is
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_boolean_vector )
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <= transport
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <= transport
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <= transport
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_boolean_vector_select select
s_st_boolean_vector(lowb) <= transport
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when 1,
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when 2,
--
c_st_boolean_vector_1(lowb) after 5 ns when 3 ;
--
CHG2 :
process ( s_st_severity_level_vector )
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <= transport
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <= transport
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <= transport
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_severity_level_vector_select select
s_st_severity_level_vector(lowb) <= transport
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when 1,
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when 2,
--
c_st_severity_level_vector_1(lowb) after 5 ns when 3 ;
--
CHG3 :
process ( s_st_string )
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <= transport
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <= transport
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <= transport
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_string_select select
s_st_string(highb) <= transport
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when 1,
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when 2,
--
c_st_string_1(highb) after 5 ns when 3 ;
--
CHG4 :
process ( s_st_enum1_vector )
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <= transport
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <= transport
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <= transport
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with st_enum1_vector_select select
s_st_enum1_vector(highb) <= transport
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when 1,
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when 2,
--
c_st_enum1_vector_1(highb) after 5 ns when 3 ;
--
CHG5 :
process ( s_st_integer_vector )
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <= transport
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <= transport
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <= transport
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_integer_vector_select select
s_st_integer_vector(lowb) <= transport
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when 1,
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when 2,
--
c_st_integer_vector_1(lowb) after 5 ns when 3 ;
--
CHG6 :
process ( s_st_time_vector )
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <= transport
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <= transport
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <= transport
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with st_time_vector_select select
s_st_time_vector(lowb) <= transport
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when 1,
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when 2,
--
c_st_time_vector_1(lowb) after 5 ns when 3 ;
--
CHG7 :
process ( s_st_real_vector )
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <= transport
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <= transport
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <= transport
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_real_vector_select select
s_st_real_vector(highb) <= transport
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when 1,
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when 2,
--
c_st_real_vector_1(highb) after 5 ns when 3 ;
--
CHG8 :
process ( s_st_rec1_vector )
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <= transport
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <= transport
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <= transport
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(highb) <= transport
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when 1,
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when 2,
--
c_st_rec1_vector_1(highb) after 5 ns when 3 ;
--
CHG9 :
process ( s_st_arr2_vector )
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <= transport
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <= transport
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <= transport
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb) <= transport
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb) after 5 ns when 3 ;
--
CHG10 :
process ( s_st_arr2 )
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <= transport
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00342.P10" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <= transport
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <= transport
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00342" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00342" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions completed entirely",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with st_arr2_select select
s_st_arr2(highb,false) <= transport
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when 1,
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when 2,
--
c_st_arr2_1(highb,false) after 5 ns when 3 ;
--
end ARCH00342 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00342_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
end ENT00342_Test_Bench ;
--
--
architecture ARCH00342_Test_Bench of ENT00342_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr2 : inout st_arr2
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00342 ( ARCH00342 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_time_vector
, s_st_real_vector
, s_st_rec1_vector
, s_st_arr2_vector
, s_st_arr2
)
;
end block L1 ;
end ARCH00342_Test_Bench ;
|
gpl-3.0
|
dcliche/mdsynth
|
rtl/src/sound/dac.vhd
|
1
|
2518
|
-- MDSynth Sound Chip
--
-- Copyright (c) 2012, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 10-bits DAC
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac is
generic(
MSBI : integer := 9
);
port ( clk: in std_logic;
dac_in: in std_logic_vector(MSBI downto 0);
reset: in std_logic;
dac_out: out std_logic);
end entity dac;
architecture dac_arch of dac is
signal delta_adder : std_logic_vector(MSBI+2 downto 0);
signal sigma_adder : std_logic_vector(MSBI+2 downto 0);
signal sigma_latch : std_logic_vector(MSBI+2 downto 0);
signal delta_b : std_logic_vector(MSBI+2 downto 0);
begin
delta_b(MSBI+2 downto MSBI+1) <= sigma_latch(MSBI+2) & sigma_latch(MSBI+2);
delta_b(MSBI downto 0) <= (others => '0');
delta_adder <= std_logic_vector(unsigned(dac_in) + unsigned(delta_b));
sigma_adder <= std_logic_vector(unsigned(delta_adder) + unsigned(sigma_latch));
process (clk, reset)
begin
if (reset = '1') then
sigma_latch <= ('1', others => '0');
dac_out <= '0';
elsif (rising_edge(clk)) then
sigma_latch <= sigma_adder;
dac_out <= sigma_latch(MSBI+2);
end if;
end process;
end architecture dac_arch;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00558.vhd
|
1
|
3218
|
-- NEED RESULT: ARCH00558: Variable declarations - composite static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00558
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (10)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00558)
-- ENT00558_Test_Bench(ARCH00558_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00558 of E00000 is
begin
process
variable correct : boolean := true ;
variable va_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
variable va_st_string_1 : st_string
:= c_st_string_1 ;
variable va_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
variable va_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
variable va_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
variable va_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
variable va_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
variable va_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
begin
correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and va_st_string_1 = c_st_string_1 ;
correct := correct and va_st_rec1_1 = c_st_rec1_1 ;
correct := correct and va_st_rec2_1 = c_st_rec2_1 ;
correct := correct and va_st_rec3_1 = c_st_rec3_1 ;
correct := correct and va_st_arr1_1 = c_st_arr1_1 ;
correct := correct and va_st_arr2_1 = c_st_arr2_1 ;
correct := correct and va_st_arr3_1 = c_st_arr3_1 ;
va_st_bit_vector_1 := c_st_bit_vector_2 ;
va_st_string_1 := c_st_string_2 ;
va_st_rec1_1 := c_st_rec1_2 ;
va_st_rec2_1 := c_st_rec2_2 ;
va_st_rec3_1 := c_st_rec3_2 ;
va_st_arr1_1 := c_st_arr1_2 ;
va_st_arr2_1 := c_st_arr2_2 ;
va_st_arr3_1 := c_st_arr3_2 ;
correct := correct and va_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and va_st_string_1 = c_st_string_2 ;
correct := correct and va_st_rec1_1 = c_st_rec1_2 ;
correct := correct and va_st_rec2_1 = c_st_rec2_2 ;
correct := correct and va_st_rec3_1 = c_st_rec3_2 ;
correct := correct and va_st_arr1_1 = c_st_arr1_2 ;
correct := correct and va_st_arr2_1 = c_st_arr2_2 ;
correct := correct and va_st_arr3_1 = c_st_arr3_2 ;
test_report ( "ARCH00558" ,
"Variable declarations - composite static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00558 ;
--
entity ENT00558_Test_Bench is
end ENT00558_Test_Bench ;
--
architecture ARCH00558_Test_Bench of ENT00558_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00558 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00558_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00241.vhd
|
1
|
4202
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00241
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00241)
-- ENT00241_Test_Bench(ARCH00241_Test_Bench)
--
-- REVISION HISTORY:
--
-- 15-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES ;
use STANDARD_TYPES.test_report, STANDARD_TYPES.switch,
STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle,
STANDARD_TYPES."=" ;
architecture ARCH00241 of GENERIC_STANDARD_TYPES is
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
--
begin
L1:
block
port (
i_boolean_1, i_boolean_2 : linkage boolean
;
i_bit_1, i_bit_2 : linkage bit
;
i_severity_level_1, i_severity_level_2 : linkage severity_level
;
i_character_1, i_character_2 : linkage character
;
i_t_enum1_1, i_t_enum1_2 : linkage t_enum1
;
i_st_enum1_1, i_st_enum1_2 : linkage st_enum1
;
i_integer_1, i_integer_2 : linkage integer
;
i_t_int1_1, i_t_int1_2 : linkage t_int1
;
i_st_int1_1, i_st_int1_2 : linkage st_int1
;
i_time_1, i_time_2 : linkage time
;
i_t_phys1_1, i_t_phys1_2 : linkage t_phys1
;
i_st_phys1_1, i_st_phys1_2 : linkage st_phys1
;
i_real_1, i_real_2 : linkage real
;
i_t_real1_1, i_t_real1_2 : linkage t_real1
;
i_st_real1_1, i_st_real1_2 : linkage st_real1
) ;
port map (
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
--
begin
process
variable correct : boolean := true ;
begin
test_report ( "ENT00241" ,
"Associated scalar linkage ports with generic subtypes" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00241 ;
--
entity ENT00241_Test_Bench is
end ENT00241_Test_Bench ;
--
architecture ARCH00241_Test_Bench of ENT00241_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00241 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00241_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl/entity3.vhd
|
1
|
1076
|
-- Simple entity test, array and indexed mappings
library ieee;
use ieee.std_logic_1164.all ;
entity main is
end entity main;
library ieee;
use ieee.std_logic_1164.all ;
entity unit1 is
port (
inum : in std_ulogic_vector (0 to 1);
oled : out std_ulogic);
begin
end;
architecture unit1 of unit1 is
begin
oled <= inum(0) and inum(1);
end architecture unit1;
architecture main of main is
constant CYCLES : integer := 100;
signal clk : integer := 0;
signal o1 : std_ulogic;
signal o2 : std_ulogic;
signal o : std_ulogic;
signal const_1 : std_ulogic := '1';
signal i : std_ulogic_vector (0 to 1);
begin
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
end if;
end process;
u1:entity unit1(unit1) port map(inum=>(0=>'0', 1=>const_1), oled=>o1);
u2:entity unit1(unit1) port map(inum=>i, oled=>o2);
i <= (others => '0');
o <= o1 and o2;
clk <= clk + 1 after 1 us;
end architecture main;
|
gpl-3.0
|
grwlf/vsim
|
vhdl/IEEE/numeric_std.vhdl
|
1
|
117361
|
-- --------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_STD. The NUMERIC_STD package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
--============================================================================
-- Arithmetic Operators:
--===========================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED;R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of SIZE L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of SIZE R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost
-- element, ARG'LEFT. The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED
-- vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED
-- vector COUNT times.
--============================================================================
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Match Functions
--============================================================================
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.2
function STD_MATCH (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.3
function STD_MATCH (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.4
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.5
function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED;
-- Result subtype: UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.2
function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED;
-- Result subtype: SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end NUMERIC_STD;
-- --------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_STD. The NUMERIC_STD package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
--==============================================================================
--============================= Package Body ===================================
--==============================================================================
package body NUMERIC_STD is
-- null range array constants
constant NAU: UNSIGNED(0 downto 1) := (others => '0');
constant NAS: SIGNED(0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING: BOOLEAN := FALSE; -- default to emit warnings
--=========================Local Subprograms =================================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
function SIGNED_NUM_BITS (ARG: INTEGER) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG: NATURAL) return NATURAL is
variable NBITS: NATURAL;
variable N: NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end UNSIGNED_NUM_BITS;
------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R: UNSIGNED; C: STD_LOGIC) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(L_LEFT downto 0) is R;
variable RESULT: UNSIGNED(L_LEFT downto 0);
variable CBIT: STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_SIGNED (L, R: SIGNED; C: STD_LOGIC) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(L_LEFT downto 0) is R;
variable RESULT: SIGNED(L_LEFT downto 0);
variable CBIT: STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end ADD_SIGNED;
-----------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM: UNSIGNED; XQUOT, XREMAIN: out UNSIGNED) is
variable TEMP: UNSIGNED(NUM'LENGTH downto 0);
variable QUOT: UNSIGNED(MAX(NUM'LENGTH, XDENOM'LENGTH)-1 downto 0);
alias DENOM: UNSIGNED(XDENOM'LENGTH-1 downto 0) is XDENOM;
variable TOPBIT: INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'RANGE loop
if DENOM(J)='1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "DIV, MOD, or REM by zero" severity ERROR;
for J in NUM'LENGTH-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1)='0'
report "internal error in the division algorithm"
severity ERROR;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'LENGTH);
XREMAIN := RESIZE(TEMP, XREMAIN'LENGTH);
end DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end XSLL;
function XSRL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end XSRL;
function XSRA (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0);
variable XCOUNT: NATURAL := COUNT;
begin
if ((ARG'LENGTH <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end XSRA;
function XROL (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end XROL;
function XROR (ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR
is
constant ARG_L: INTEGER := ARG'LENGTH-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end XROR;
-----------------Local Subprograms - Relational ops---------------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) = STD_LOGIC_VECTOR(R);
end UNSIGNED_EQUAL;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R: SIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) = STD_LOGIC_VECTOR(R);
end SIGNED_EQUAL;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) < STD_LOGIC_VECTOR(R);
end UNSIGNED_LESS;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS (L, R: SIGNED) return BOOLEAN is
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_LOGIC_VECTOR(INTERN_L) < STD_LOGIC_VECTOR(INTERN_R);
end SIGNED_LESS;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR(L) <= STD_LOGIC_VECTOR(R);
end UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R: SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L: SIGNED(0 to L'LENGTH-1);
variable INTERN_R: SIGNED(0 to R'LENGTH-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_LOGIC_VECTOR(INTERN_L) <= STD_LOGIC_VECTOR(INTERN_R);
end SIGNED_LESS_OR_EQUAL;
--=========================Exported Functions ==========================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: SIGNED(ARG_LEFT downto 0);
begin
if ARG'LENGTH < 1 then return NAS;
end if;
RESULT := TO_01(XARG, 'X');
if (RESULT(RESULT'LEFT)='X') then return RESULT;
end if;
if RESULT(RESULT'LEFT) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end "abs";
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT, XARG01 : SIGNED(ARG_LEFT downto 0);
variable CBIT: STD_LOGIC := '1';
begin
if ARG'LENGTH < 1 then return NAS;
end if;
XARG01 := TO_01(ARG, 'X');
if (XARG01(XARG01'LEFT)='X') then return XARG01;
end if;
for I in 0 to RESULT'LEFT loop
RESULT(I) := not(XARG01(I)) xor CBIT;
CBIT := CBIT and not(XARG01(I));
end loop;
return RESULT;
end "-";
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_UNSIGNED(L01, R01, '0');
end "+";
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_SIGNED(L01, R01, '0');
end "+";
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'LENGTH);
end "+";
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) + R;
end "+";
-- Id: A.7
function "+" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED(R, L'LENGTH);
end "+";
-- Id: A.8
function "+" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) + R;
end "+";
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_UNSIGNED(L01, not(R01), '1');
end "-";
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED is
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'LEFT)='X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'LEFT)='X') then return R01;
end if;
return ADD_SIGNED(L01, not(R01), '1');
end "-";
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'LENGTH);
end "-";
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) - R;
end "-";
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED(R, L'LENGTH);
end "-";
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) - R;
end "-";
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable RESULT: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0) :=
(others => '0');
variable ADVAL: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end "*";
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable RESULT: SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0');
variable ADVAL: SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := TO_01(L, 'X');
XR := TO_01(R, 'X');
if ((XL(L_LEFT)='X') or (XR(R_LEFT)='X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'LENGTH);
for I in 0 to L_LEFT-1 loop
if XL(I)='1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT)='1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end "*";
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'LENGTH);
end "*";
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED(L, R'LENGTH) * R;
end "*";
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED(R, L'LENGTH);
end "*";
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED(L, R'LENGTH) * R;
end "*";
--============================================================================
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FQUOT := (others => 'X');
return FQUOT;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FQUOT;
end "/";
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: SIGNED(L_LEFT downto 0) is L;
alias XXR: SIGNED(R_LEFT downto 0) is R;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable QNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FQUOT := (others => 'X');
return SIGNED(FQUOT);
end if;
if XL(XL'LEFT)='1' then
XNUM := UNSIGNED(-XL);
QNEG := TRUE;
else
XNUM := UNSIGNED(XL);
end if;
if XR(XR'LEFT)='1' then
XDENOM := UNSIGNED(-XR);
QNEG := not QNEG;
else
XDENOM := UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return SIGNED(FQUOT);
end "/";
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, QUOT: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(0)/='X'
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, QUOT: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
if (R_LENGTH > L'LENGTH) then
QUOT := (others => '0');
return RESIZE(QUOT, L'LENGTH);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'LENGTH);
return RESIZE(QUOT, L'LENGTH);
end "/";
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, QUOT: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'LENGTH);
if L_LENGTH > R'LENGTH and QUOT(0)/='X'
and QUOT(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => QUOT(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity WARNING;
end if;
return RESIZE(QUOT, R'LENGTH);
end "/";
--============================================================================
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end "rem";
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: SIGNED(L_LEFT downto 0) is L;
alias XXR: SIGNED(R_LEFT downto 0) is R;
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
XNUM := UNSIGNED(TO_01(XXL, 'X'));
XDENOM := UNSIGNED(TO_01(XXR, 'X'));
if ((XNUM(XNUM'LEFT)='X') or (XDENOM(XDENOM'LEFT)='X')) then
FREMAIN := (others => 'X');
return SIGNED(FREMAIN);
end if;
if XNUM(XNUM'LEFT)='1' then
XNUM := UNSIGNED(-SIGNED(XNUM));
RNEG := TRUE;
else
XNUM := UNSIGNED(XNUM);
end if;
if XDENOM(XDENOM'LEFT)='1' then
XDENOM := UNSIGNED(-SIGNED(XDENOM));
else
XDENOM := UNSIGNED(XDENOM);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "rem";
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := L rem XR;
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := XL rem R;
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "rem";
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: UNSIGNED(L_LEFT downto 0) is L;
alias XXR: UNSIGNED(R_LEFT downto 0) is R;
variable XL: UNSIGNED(L_LEFT downto 0);
variable XR: UNSIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end "mod";
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XXL: SIGNED(L_LEFT downto 0) is L;
alias XXR: SIGNED(R_LEFT downto 0) is R;
variable XL: SIGNED(L_LEFT downto 0);
variable XR: SIGNED(R_LEFT downto 0);
variable FQUOT: UNSIGNED(L'LENGTH-1 downto 0);
variable FREMAIN: UNSIGNED(R'LENGTH-1 downto 0);
variable XNUM: UNSIGNED(L'LENGTH-1 downto 0);
variable XDENOM: UNSIGNED(R'LENGTH-1 downto 0);
variable RNEG: BOOLEAN := FALSE;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'LEFT)='X') or (XR(XR'LEFT)='X')) then
FREMAIN := (others => 'X');
return SIGNED(FREMAIN);
end if;
if XL(XL'LEFT)='1' then
XNUM := UNSIGNED(-XL);
else
XNUM := UNSIGNED(XL);
end if;
if XR(XR'LEFT)='1' then
XDENOM := UNSIGNED(-XR);
RNEG := TRUE;
else
XDENOM := UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'LEFT)='1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN/="0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'LEFT)='1' and FREMAIN/="0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return SIGNED(FREMAIN);
end "mod";
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, UNSIGNED_NUM_BITS(R));
variable XR, XREM: UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED is
constant L_LENGTH: NATURAL := MAX(UNSIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED is
constant R_LENGTH: NATURAL := MAX(L'LENGTH, SIGNED_NUM_BITS(R));
variable XR, XREM: SIGNED(R_LENGTH-1 downto 0);
begin
if (L'LENGTH < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'LENGTH);
if R_LENGTH > L'LENGTH and XREM(0)/='X'
and XREM(R_LENGTH-1 downto L'LENGTH)
/= (R_LENGTH-1 downto L'LENGTH => XREM(L'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, L'LENGTH);
end "mod";
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED is
constant L_LENGTH: NATURAL := MAX(SIGNED_NUM_BITS(L), R'LENGTH);
variable XL, XREM: SIGNED(L_LENGTH-1 downto 0);
begin
if (R'LENGTH < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'LENGTH);
if L_LENGTH > R'LENGTH and XREM(0)/='X'
and XREM(L_LENGTH-1 downto R'LENGTH)
/= (L_LENGTH-1 downto R'LENGTH => XREM(R'LENGTH-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity WARNING;
end if;
return RESIZE(XREM, R'LENGTH);
end "mod";
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">";
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">";
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01);
end ">";
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'LENGTH), R01);
end ">";
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH));
end ">";
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'LENGTH));
end ">";
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<";
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<";
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R01'LENGTH), R01);
end "<";
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R01'LENGTH), R01);
end "<";
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'LENGTH));
end "<";
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS(L01, TO_SIGNED(R, L01'LENGTH));
end "<";
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<=";
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "<=";
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01);
end "<=";
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'LENGTH), R01);
end "<=";
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH));
end "<=";
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'LENGTH));
end "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">=";
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end ">=";
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'LENGTH), R01);
end ">=";
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R01'LENGTH), R01);
end ">=";
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'LENGTH));
end ">=";
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return 0 > R;
end if;
return not SIGNED_LESS(L01, TO_SIGNED(R, L01'LENGTH));
end ">=";
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "=";
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end "=";
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01);
end "=";
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R01'LENGTH), R01);
end "=";
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH));
end "=";
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return FALSE;
end if;
return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'LENGTH));
end "=";
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : UNSIGNED(L_LEFT downto 0);
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end "/=";
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
alias XR: SIGNED(R_LEFT downto 0) is R;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH);
variable L01 : SIGNED(L_LEFT downto 0);
variable R01 : SIGNED(R_LEFT downto 0);
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'LEFT)='X') or (R01(R01'LEFT)='X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end "/=";
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNSIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'LENGTH), R01));
end "/=";
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_LEFT: INTEGER := R'LENGTH-1;
alias XR: SIGNED(R_LEFT downto 0) is R;
variable R01 : SIGNED(R_LEFT downto 0);
begin
if (R'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(L) > R'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R01'LENGTH), R01));
end "/=";
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNSIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if UNSIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'LENGTH)));
end "/=";
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_LEFT: INTEGER := L'LENGTH-1;
alias XL: SIGNED(L_LEFT downto 0) is L;
variable L01 : SIGNED(L_LEFT downto 0);
begin
if (L'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity WARNING;
return TRUE;
end if;
if SIGNED_NUM_BITS(R) > L'LENGTH then return TRUE;
end if;
return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'LENGTH)));
end "/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XSRL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSLL(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XSRA(STD_LOGIC_VECTOR(ARG), COUNT));
end SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'LENGTH < 1) then return NAU;
end if;
return UNSIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROL(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'LENGTH < 1) then return NAS;
end if;
return SIGNED(XROR(STD_LOGIC_VECTOR(ARG), COUNT));
end ROTATE_RIGHT;
--============================================================================
--START-V93
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end "sll";
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end "srl";
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end "rol";
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end "ror";
--END-V93
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XXARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable XARG: UNSIGNED(ARG_LEFT downto 0);
variable RESULT: NATURAL := 0;
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
XARG := TO_01(XXARG, 'X');
if (XARG(XARG'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity WARNING;
return 0;
end if;
for I in XARG'RANGE loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER is
variable XARG: SIGNED(ARG'LENGTH-1 downto 0);
begin
if (ARG'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity WARNING;
return 0;
end if;
XARG := TO_01(ARG, 'X');
if (XARG(XARG'LEFT)='X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity WARNING;
return 0;
end if;
if XARG(XARG'LEFT) = '0' then
return TO_INTEGER(UNSIGNED(XARG));
else
return (- (TO_INTEGER(UNSIGNED(- (XARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL =0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED(SIZE-1 downto 0);
variable B_VAL: STD_LOGIC := '0';
variable I_VAL: INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL/=0) or (B_VAL/=RESULT(RESULT'LEFT))) then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector truncated"
severity WARNING;
end if;
return RESULT;
end TO_SIGNED;
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(not(STD_LOGIC_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED(L'LENGTH-1 downto 0);
begin
RESULT := UNSIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
-- Id: L.8
function "not" (L: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(not(STD_LOGIC_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R));
return RESULT;
end "xor";
--START-V93
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED is
variable RESULT: SIGNED(L'LENGTH-1 downto 0);
begin
RESULT := SIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R));
return RESULT;
end "xnor";
--END-V93
--============================================================================
-- support constants for STD_MATCH:
type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE: BOOLEAN_TABLE := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | U |
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | X |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | 0 |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | 1 |
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | Z |
(FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | W |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | L |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | H |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE) -- | - |
);
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN is
variable VALUE: STD_ULOGIC;
begin
return MATCH_TABLE(L, R);
end STD_MATCH;
-- Id: M.2
function STD_MATCH (L, R: UNSIGNED) return BOOLEAN is
alias LV: UNSIGNED(1 to L'LENGTH) is L;
alias RV: UNSIGNED(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.3
function STD_MATCH (L, R: SIGNED) return BOOLEAN is
alias LV: SIGNED(1 to L'LENGTH) is L;
alias RV: SIGNED(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.4
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN is
alias LV: STD_LOGIC_VECTOR(1 to L'LENGTH) is L;
alias RV: STD_LOGIC_VECTOR(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
-- Id: M.5
function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN is
alias LV: STD_ULOGIC_VECTOR(1 to L'LENGTH) is L;
alias RV: STD_ULOGIC_VECTOR(1 to R'LENGTH) is R;
begin
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity WARNING;
return FALSE;
else
for I in LV'LOW to LV'HIGH loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end STD_MATCH;
--============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED is
variable RESULT: UNSIGNED(S'LENGTH-1 downto 0);
variable BAD_ELEMENT: BOOLEAN := FALSE;
alias XS: UNSIGNED(S'LENGTH-1 downto 0) is S;
begin
if (S'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAU"
severity WARNING;
return NAU;
end if;
for I in RESULT'RANGE loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := TRUE;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'RANGE loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
-- Id: T.2
function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED is
variable RESULT: SIGNED(S'LENGTH-1 downto 0);
variable BAD_ELEMENT: BOOLEAN := FALSE;
alias XS: SIGNED(S'LENGTH-1 downto 0) is S;
begin
if (S'LENGTH < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAS"
severity WARNING;
return NAS;
end if;
for I in RESULT'RANGE loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := TRUE;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'RANGE loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
--============================================================================
end NUMERIC_STD;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00564.vhd
|
1
|
9248
|
-- NEED RESULT: ARCH00564: Aliasing - composite generic subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00564
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.4 (1)
-- 4.3.4 (2)
-- 4.3.4 (13)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00564)
-- ENT00564_Test_Bench(ARCH00564_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00564 of GENERIC_STANDARD_TYPES is
constant co_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
constant co_st_string_1 : st_string
:= c_st_string_1 ;
constant co_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
constant co_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
constant co_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
constant co_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
signal si_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
signal si_st_string_1 : st_string
:= c_st_string_1 ;
signal si_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal si_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal si_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal si_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
alias as_st_bit_vector_1 : st_bit_vector
is si_st_bit_vector_1 ;
alias as_st_string_1 : st_string
is si_st_string_1 ;
alias as_st_rec1_1 : st_rec1
is si_st_rec1_1 ;
alias as_st_rec2_1 : st_rec2
is si_st_rec2_1 ;
alias as_st_rec3_1 : st_rec3
is si_st_rec3_1 ;
alias as_st_arr1_1 : st_arr1
is si_st_arr1_1 ;
type test is (initial, intermediate, final) ;
signal synch : test := initial ;
signal s_correct1 : boolean ;
signal s_correct2 : boolean ;
begin
process
variable correct : boolean := true ;
begin
if synch = initial then
correct := correct and as_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and as_st_string_1 = c_st_string_1 ;
correct := correct and as_st_rec1_1 = c_st_rec1_1 ;
correct := correct and as_st_rec2_1 = c_st_rec2_1 ;
correct := correct and as_st_rec3_1 = c_st_rec3_1 ;
correct := correct and as_st_arr1_1 = c_st_arr1_1 ;
si_st_bit_vector_1 <= c_st_bit_vector_2 ;
si_st_string_1 <= c_st_string_2 ;
si_st_rec1_1 <= c_st_rec1_2 ;
si_st_rec2_1 <= c_st_rec2_2 ;
si_st_rec3_1 <= c_st_rec3_2 ;
si_st_arr1_1 <= c_st_arr1_2 ;
synch <= intermediate ;
as_st_bit_vector_1 <= transport c_st_bit_vector_1 after 1 ns ;
as_st_string_1 <= transport c_st_string_1 after 1 ns ;
as_st_rec1_1 <= transport c_st_rec1_1 after 1 ns ;
as_st_rec2_1 <= transport c_st_rec2_1 after 1 ns ;
as_st_rec3_1 <= transport c_st_rec3_1 after 1 ns ;
as_st_arr1_1 <= transport c_st_arr1_1 after 1 ns ;
synch <= transport final after 1 ns ;
s_correct1 <= correct ;
end if ;
wait ;
end process ;
process (synch)
procedure p1 is
variable correct : boolean ;
variable va_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
variable va_st_string_1 : st_string
:= c_st_string_1 ;
variable va_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
variable va_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
variable va_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
variable va_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
alias ac_st_bit_vector_1 : st_bit_vector
is co_st_bit_vector_1 ;
alias ac_st_string_1 : st_string
is co_st_string_1 ;
alias ac_st_rec1_1 : st_rec1
is co_st_rec1_1 ;
alias ac_st_rec2_1 : st_rec2
is co_st_rec2_1 ;
alias ac_st_rec3_1 : st_rec3
is co_st_rec3_1 ;
alias ac_st_arr1_1 : st_arr1
is co_st_arr1_1 ;
alias av_st_bit_vector_1 : st_bit_vector
is va_st_bit_vector_1 ;
alias av_st_string_1 : st_string
is va_st_string_1 ;
alias av_st_rec1_1 : st_rec1
is va_st_rec1_1 ;
alias av_st_rec2_1 : st_rec2
is va_st_rec2_1 ;
alias av_st_rec3_1 : st_rec3
is va_st_rec3_1 ;
alias av_st_arr1_1 : st_arr1
is va_st_arr1_1 ;
begin
if synch = intermediate then
-- test that variables denote same object
correct := s_correct1 ;
correct := correct and av_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and av_st_string_1 = c_st_string_1 ;
correct := correct and av_st_rec1_1 = c_st_rec1_1 ;
correct := correct and av_st_rec2_1 = c_st_rec2_1 ;
correct := correct and av_st_rec3_1 = c_st_rec3_1 ;
correct := correct and av_st_arr1_1 = c_st_arr1_1 ;
va_st_bit_vector_1 := c_st_bit_vector_2 ;
va_st_string_1 := c_st_string_2 ;
va_st_rec1_1 := c_st_rec1_2 ;
va_st_rec2_1 := c_st_rec2_2 ;
va_st_rec3_1 := c_st_rec3_2 ;
va_st_arr1_1 := c_st_arr1_2 ;
correct := correct and av_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and av_st_string_1 = c_st_string_2 ;
correct := correct and av_st_rec1_1 = c_st_rec1_2 ;
correct := correct and av_st_rec2_1 = c_st_rec2_2 ;
correct := correct and av_st_rec3_1 = c_st_rec3_2 ;
correct := correct and av_st_arr1_1 = c_st_arr1_2 ;
av_st_bit_vector_1 := c_st_bit_vector_1 ;
av_st_string_1 := c_st_string_1 ;
av_st_rec1_1 := c_st_rec1_1 ;
av_st_rec2_1 := c_st_rec2_1 ;
av_st_rec3_1 := c_st_rec3_1 ;
av_st_arr1_1 := c_st_arr1_1 ;
correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and va_st_string_1 = c_st_string_1 ;
correct := correct and va_st_rec1_1 = c_st_rec1_1 ;
correct := correct and va_st_rec2_1 = c_st_rec2_1 ;
correct := correct and va_st_rec3_1 = c_st_rec3_1 ;
correct := correct and va_st_arr1_1 = c_st_arr1_1 ;
-- test that signals denote same object
correct := correct and as_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and as_st_string_1 = c_st_string_2 ;
correct := correct and as_st_rec1_1 = c_st_rec1_2 ;
correct := correct and as_st_rec2_1 = c_st_rec2_2 ;
correct := correct and as_st_rec3_1 = c_st_rec3_2 ;
correct := correct and as_st_arr1_1 = c_st_arr1_2 ;
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and si_st_string_1 = c_st_string_2 ;
correct := correct and si_st_rec1_1 = c_st_rec1_2 ;
correct := correct and si_st_rec2_1 = c_st_rec2_2 ;
correct := correct and si_st_rec3_1 = c_st_rec3_2 ;
correct := correct and si_st_arr1_1 = c_st_arr1_2 ;
-- test that constants denote same object
correct := correct and ac_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and ac_st_string_1 = c_st_string_1 ;
correct := correct and ac_st_rec1_1 = c_st_rec1_1 ;
correct := correct and ac_st_rec2_1 = c_st_rec2_1 ;
correct := correct and ac_st_rec3_1 = c_st_rec3_1 ;
correct := correct and ac_st_arr1_1 = c_st_arr1_1 ;
s_correct2 <= correct ;
end if ;
end p1 ;
begin
p1 ;
end process ;
--
process (synch)
variable correct : boolean ;
begin
if synch = final then
correct := s_correct2 ;
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and si_st_string_1 = c_st_string_1 ;
correct := correct and si_st_rec1_1 = c_st_rec1_1 ;
correct := correct and si_st_rec2_1 = c_st_rec2_1 ;
correct := correct and si_st_rec3_1 = c_st_rec3_1 ;
correct := correct and si_st_arr1_1 = c_st_arr1_1 ;
test_report ( "ARCH00564" ,
"Aliasing - composite generic subtypes" ,
correct) ;
end if ;
end process ;
end ARCH00564 ;
--
entity ENT00564_Test_Bench is
end ENT00564_Test_Bench ;
--
architecture ARCH00564_Test_Bench of ENT00564_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00564 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00564_Test_Bench ;
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_gen_prim_wrapper_v6_init.vhd
|
9
|
605511
|
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`protect end_protected
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00684.vhd
|
1
|
4665
|
-- NEED RESULT: ARCH00684: Allocators with static composite subtype indication passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00684
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (2)
-- 7.3.6 (4)
-- 7.3.6 (7)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00684)
-- ENT00684_Test_Bench(ARCH00684_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00684 of E00000 is
begin
process
variable correct : boolean := true ;
type a_bit_vector is access bit_vector ;
variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector
:= new st_bit_vector ;
type a_string is access string ;
variable va_string_1, va_string_2 : a_string
:= new st_string ;
type a_t_rec1 is access t_rec1 ;
variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1
:= new st_rec1 ;
type a_st_rec1 is access st_rec1 ;
variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1
:= new st_rec1 ;
type a_t_rec2 is access t_rec2 ;
variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2
:= new st_rec2 ;
type a_st_rec2 is access st_rec2 ;
variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2
:= new st_rec2 ;
type a_t_rec3 is access t_rec3 ;
variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3
:= new st_rec3 ;
type a_st_rec3 is access st_rec3 ;
variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3
:= new st_rec3 ;
type a_t_arr1 is access t_arr1 ;
variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1
:= new st_arr1 ;
type a_st_arr1 is access st_arr1 ;
variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1
:= new st_arr1 ;
type a_t_arr2 is access t_arr2 ;
variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2
:= new st_arr2 ;
type a_st_arr2 is access st_arr2 ;
variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2
:= new st_arr2 ;
type a_t_arr3 is access t_arr3 ;
variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3
:= new st_arr3 ;
type a_st_arr3 is access st_arr3 ;
variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3
:= new st_arr3 ;
begin
correct := correct and
va_bit_vector_1.all = d_st_bit_vector ;
correct := correct and
va_string_1.all = d_st_string ;
correct := correct and
va_t_rec1_1.all = d_st_rec1 ;
correct := correct and
va_st_rec1_1.all = d_st_rec1 ;
correct := correct and
va_t_rec2_1.all = d_st_rec2 ;
correct := correct and
va_st_rec2_1.all = d_st_rec2 ;
correct := correct and
va_t_rec3_1.all = d_st_rec3 ;
correct := correct and
va_st_rec3_1.all = d_st_rec3 ;
correct := correct and
va_t_arr1_1.all = d_st_arr1 ;
correct := correct and
va_st_arr1_1.all = d_st_arr1 ;
correct := correct and
va_t_arr2_1.all = d_st_arr2 ;
correct := correct and
va_st_arr2_1.all = d_st_arr2 ;
correct := correct and
va_t_arr3_1.all = d_st_arr3 ;
correct := correct and
va_st_arr3_1.all = d_st_arr3 ;
test_report ( "ARCH00684" ,
"Allocators with static composite subtype indication" ,
correct) ;
wait ;
end process ;
end ARCH00684 ;
--
entity ENT00684_Test_Bench is
end ENT00684_Test_Bench ;
--
architecture ARCH00684_Test_Bench of ENT00684_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00684 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00684_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00156.vhd
|
1
|
24437
|
-- NEED RESULT: ARCH00156.P1: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156.P2: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156.P3: Multi inertial transactions occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: Old transactions were removed on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: One inertial transaction occurred on signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00156: Inertial semantics check on a signal asg with indexed name prefixed by an indexed name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed passed
-- NEED RESULT: P2: Inertial transactions entirely completed passed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00156
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00156)
-- ENT00156_Test_Bench(ARCH00156_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00156 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00156.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns,
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 30 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <= transport
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 100 ns;
--
when 5 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 10 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 20 ns,
c_st_arr1_vector_2(highb) (
st_arr1'Right) after 30 ns,
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_2(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr1_vector(lowb) (
st_arr1'Left) <=
c_st_arr1_vector_1(highb) (
st_arr1'Right) after 40 ns;
--
when 7 =>
correct :=
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr1_vector(lowb) (
st_arr1'Left) =
c_st_arr1_vector_1(highb) (
st_arr1'Right) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00156" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00156.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <= transport
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 10 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 20 ns,
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 30 ns,
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_2(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) <=
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr2_vector(lowb) (
st_arr2'Left(1),st_arr2'Left(2)) =
c_st_arr2_vector_1(highb) (
st_arr2'Right(1),st_arr2'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00156" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0 =>
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ;
--
when 1 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00156.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 3 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 5 ns;
--
when 4 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <= transport
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 100 ns;
--
when 5 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"Old transactions were removed on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 10 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 20 ns,
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 30 ns,
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ;
--
when 6 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_2(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"One inertial transaction occurred on signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
-- The following will mark last transaction above
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) <=
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) after 40 ns;
--
when 7 =>
correct :=
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8 =>
correct :=
correct and
s_st_arr3_vector(lowb) (
st_arr3'Left(1),st_arr3'Left(2)) =
c_st_arr3_vector_1(highb) (
st_arr3'Right(1),st_arr3'Right(2)) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00156" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00156" ,
"Inertial semantics check on a signal " &
"asg with indexed name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00156 ;
--
entity ENT00156_Test_Bench is
end ENT00156_Test_Bench ;
--
architecture ARCH00156_Test_Bench of ENT00156_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00156 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00156_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00682.vhd
|
1
|
2361
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00682
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.5 (2)
-- 7.3.5 (4)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00682)
-- ENT00682_Test_Bench(ARCH00682_Test_Bench)
--
-- REVISION HISTORY:
--
-- 7-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00682 of E00000 is
type int1 is range -10 to 10 ;
type arr1 is array ( int1 range <> ) of bit_vector ( 0 to 3 ) ;
type arr2 is array ( integer range <> ) of bit_vector ( 0 to 3 ) ;
begin
process
subtype st_arr1 is arr1 ( -5 to 5 ) ;
subtype st_arr2 is arr2 ( -5 to 5 ) ;
variable v_arr1_1, v_arr1_2, v_arr1_3 : st_arr1 ;
variable v_arr2_1, v_arr2_2, v_arr2_3 : st_arr2 ;
variable correct : boolean := True ;
procedure p1 ( p_arr1 : arr1 ;
p_arr2 : arr2 ) is
begin
correct := correct and p_arr1 = v_arr1_2 and
p_arr2 = v_arr2_2 ;
test_report ( "ARCH00682" ,
"Conversion to unconstrained array converts"
& " takes constraint from converted bounds" ,
correct ) ;
end p1 ;
begin
v_arr1_1 := (others => B"0101") ;
v_arr2_1 := (others => B"1010") ;
v_arr1_2 := (others => B"1010") ;
v_arr2_2 := (others => B"0101") ;
v_arr1_3 := st_arr1 ( v_arr2_1 ) ;
v_arr2_3 := st_arr2 ( v_arr1_1 ) ;
correct := correct and v_arr1_3 = v_arr1_2 and
v_arr2_3 = v_arr2_2 ;
test_report ( "ARCH00682" ,
"Conversion between array types with different index"
& " types" ,
correct ) ;
p1 ( arr1 ( v_arr2_1 ) , arr2 ( v_arr1_1 )) ;
wait ;
end process ;
end ARCH00682 ;
--
entity ENT00682_Test_Bench is
end ENT00682_Test_Bench ;
architecture ARCH00682_Test_Bench of ENT00682_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00682 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00682_Test_Bench ;
--
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/pro000003.vhd
|
1
|
728
|
-------------------------------------------------------------------------------
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, wait.
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture ARCH00001_Test_Bench of ENT00001_Test_Bench is
begin
main: process
begin
report "Start.";
wait for 10 fs;
report "Ten femtoseconds.";
wait for 990 fs;
report "One picosecond.";
wait ;
end process;
end;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00340.vhd
|
1
|
43402
|
-- NEED RESULT: ARCH00340.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340.P10: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00340: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P10: Transport transactions completed entirely passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00340
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00340(ARCH00340)
-- ENT00340_Test_Bench(ARCH00340_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00340 is
end ENT00340 ;
--
--
architecture ARCH00340 of ENT00340 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
begin
CHG1 :
process ( s_st_boolean_vector )
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <= transport
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <= transport
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <= transport
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_boolean_vector_select select
s_st_boolean_vector(lowb) <= transport
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when 1,
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when 2,
--
c_st_boolean_vector_1(lowb) after 5 ns when 3 ;
--
CHG2 :
process ( s_st_severity_level_vector )
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <= transport
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <= transport
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <= transport
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_severity_level_vector_select select
s_st_severity_level_vector(lowb) <= transport
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when 1,
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when 2,
--
c_st_severity_level_vector_1(lowb) after 5 ns when 3 ;
--
CHG3 :
process ( s_st_string )
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <= transport
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <= transport
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <= transport
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_string_select select
s_st_string(highb) <= transport
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when 1,
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when 2,
--
c_st_string_1(highb) after 5 ns when 3 ;
--
CHG4 :
process ( s_st_enum1_vector )
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <= transport
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <= transport
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <= transport
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with st_enum1_vector_select select
s_st_enum1_vector(highb) <= transport
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when 1,
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when 2,
--
c_st_enum1_vector_1(highb) after 5 ns when 3 ;
--
CHG5 :
process ( s_st_integer_vector )
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <= transport
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <= transport
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <= transport
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_integer_vector_select select
s_st_integer_vector(lowb) <= transport
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when 1,
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when 2,
--
c_st_integer_vector_1(lowb) after 5 ns when 3 ;
--
CHG6 :
process ( s_st_time_vector )
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <= transport
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <= transport
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <= transport
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with st_time_vector_select select
s_st_time_vector(lowb) <= transport
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when 1,
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when 2,
--
c_st_time_vector_1(lowb) after 5 ns when 3 ;
--
CHG7 :
process ( s_st_real_vector )
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <= transport
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <= transport
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <= transport
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_real_vector_select select
s_st_real_vector(highb) <= transport
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when 1,
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when 2,
--
c_st_real_vector_1(highb) after 5 ns when 3 ;
--
CHG8 :
process ( s_st_rec1_vector )
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <= transport
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <= transport
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <= transport
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(highb) <= transport
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when 1,
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when 2,
--
c_st_rec1_vector_1(highb) after 5 ns when 3 ;
--
CHG9 :
process ( s_st_arr2_vector )
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <= transport
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <= transport
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <= transport
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb) <= transport
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb) after 5 ns when 3 ;
--
CHG10 :
process ( s_st_arr2 )
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <= transport
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00340.P10" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <= transport
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <= transport
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00340" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00340" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions completed entirely",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with st_arr2_select select
s_st_arr2(highb,false) <= transport
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when 1,
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when 2,
--
c_st_arr2_1(highb,false) after 5 ns when 3 ;
--
end ARCH00340 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00340_Test_Bench is
end ENT00340_Test_Bench ;
--
--
architecture ARCH00340_Test_Bench of ENT00340_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00340 ( ARCH00340 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00340_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00694.vhd
|
1
|
5235
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00694
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.3.2 (1)
-- 4.3.3.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00694
-- PKG00694/BODY
-- ENT00694(ARCH00694)
-- ENT00694_Test_Bench(ARCH00694_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
--
use WORK.STANDARD_TYPES.all ;
package PKG00694 is
function fintegertointeger ( P : integer ) return integer ;
function fintegertost_bit_vector ( P : integer ) return st_bit_vector ;
--
function fst_bit_vectortointeger ( P : st_bit_vector ) return integer ;
function fst_bit_vectortost_arr3 ( P : st_bit_vector ) return st_arr3 ;
--
function fst_arr3tost_bit_vector ( P : st_arr3 ) return st_bit_vector ;
function fst_arr3toboolean ( P : st_arr3 ) return boolean ;
--
function fbooleantost_arr3 ( P : boolean ) return st_arr3 ;
end PKG00694 ;
--
package body PKG00694 is
function fintegertointeger ( P : integer ) return integer is
begin
if P = c_integer_1 then
return c_integer_1 ;
else
return c_integer_2 ;
end if ;
end ;
function fintegertost_bit_vector ( P : integer ) return st_bit_vector is
begin
if P = c_integer_1 then
return c_st_bit_vector_1 ;
else
return c_st_bit_vector_2 ;
end if ;
end ;
--
function fst_bit_vectortointeger ( P : st_bit_vector ) return integer is
begin
if P = c_st_bit_vector_1 then
return c_integer_1 ;
else
return c_integer_2 ;
end if ;
end ;
function fst_bit_vectortost_arr3 ( P : st_bit_vector ) return st_arr3 is
begin
if P = c_st_bit_vector_1 then
return c_st_arr3_1 ;
else
return c_st_arr3_2 ;
end if ;
end ;
--
function fst_arr3tost_bit_vector ( P : st_arr3 ) return st_bit_vector is
begin
if P = c_st_arr3_1 then
return c_st_bit_vector_1 ;
else
return c_st_bit_vector_2 ;
end if ;
end ;
function fst_arr3toboolean ( P : st_arr3 ) return boolean is
begin
if P = c_st_arr3_1 then
return c_boolean_1 ;
else
return c_boolean_2 ;
end if ;
end ;
--
function fbooleantost_arr3 ( P : boolean ) return st_arr3 is
begin
if P = c_boolean_1 then
return c_st_arr3_1 ;
else
return c_st_arr3_2 ;
end if ;
end ;
end PKG00694 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00694.all ;
entity ENT00694 is
port (
signal s_st_arr3 : in st_arr3 ;
signal s2_integer : out integer
) ;
end ENT00694 ;
--
architecture ARCH00694 of ENT00694 is
procedure p1 (
v_boolean : boolean ;
variable v2_integer : out integer
) is
variable correct : boolean := true ;
begin
if v_boolean = c_boolean_1 then
v2_integer := c_integer_1 ;
test_report ( "ARCH00694" ,
"Type conversions in assoc. lists with in interface objects" ,
correct ) ;
end if ;
end p1 ;
begin
process
variable v_st_arr3 : st_arr3 ;
variable v2_integer : integer ;
begin
v_st_arr3 := s_st_arr3 ;
p1 (
v_boolean =>
fst_arr3toboolean
( v_st_arr3 ) ,
v2_integer =>
v2_integer
) ;
s2_integer <= v2_integer ;
wait ;
end process ;
end ARCH00694 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00694.all ;
entity ENT00694_Test_Bench is
end ENT00694_Test_Bench ;
--
architecture ARCH00694_Test_Bench of ENT00694_Test_Bench is
begin
L1:
block
signal s_integer : integer := c_integer_1 ;
signal s2_integer : integer := c_integer_2 ;
signal toggle : boolean := false ;
component UUT
port (
signal s_st_bit_vector : in st_bit_vector ;
signal s2_integer : out integer
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00694 ( ARCH00694 )
port map (
s_st_arr3 =>
fst_bit_vectortost_arr3
( s_st_bit_vector ) ,
s2_integer =>
s2_integer
) ;
begin
toggle <= true ;
CIS1 : UUT
port map (
s_st_bit_vector =>
fintegertost_bit_vector
( s_integer ) ,
s2_integer =>
s2_integer
) ;
process ( s2_integer, s_integer, toggle)
variable correct : boolean := true ;
begin
if toggle then
correct := correct and s2_integer = c_integer_1 ;
test_report ( "ARCH00694" ,
"Type conversions in assoc. lists with in interface objects" ,
correct ) ;
end if ;
end process ;
end block L1 ;
end ARCH00694_Test_Bench ;
--
|
gpl-3.0
|
progranism/Open-Source-FPGA-Bitcoin-Miner
|
projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_extdepth.vhd
|
9
|
51718
|
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`protect end_protected
|
gpl-3.0
|
dcliche/mdsynth
|
rtl/src/sound/nco.vhd
|
1
|
2489
|
-- MDSynth Sound Chip
--
-- Copyright (c) 2012, Meldora Inc.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
-- following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this list of conditions and the
-- following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
-- following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
-- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Numerically-controlled oscillator
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- freq = (50E6 * (phase_delta * 2^octave)) / 2^32
entity nco is
port ( clk: in std_logic;
reset_phase: in std_logic;
ena: in std_logic;
phase_delta: in unsigned(11 downto 0);
octave: in unsigned(3 downto 0);
phase: out unsigned(7 downto 0));
end nco;
architecture nco_arch of nco is
signal phase_accumulator: unsigned(31 downto 0) := to_unsigned(0, 32);
signal toggle: std_logic := '0' ;
signal phase_delta_32: unsigned(31 downto 0) := to_unsigned(0, 32);
begin
process (clk)
begin
if (rising_edge(clk)) then
phase_delta_32(11 downto 0) <= phase_delta;
if (reset_phase = '1') then
phase_accumulator <= to_unsigned(0, 32);
elsif (ena = '1') then
phase_accumulator <= phase_accumulator + (phase_delta_32 sll (to_integer(octave)));
end if;
phase <= phase_accumulator(31 downto 24);
end if;
end process;
end nco_arch;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00637.vhd
|
1
|
65900
|
-- NEED RESULT: ARCH00637.P1: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P2: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P3: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P4: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P5: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P6: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P7: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P8: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P9: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P10: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P11: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P12: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P13: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P14: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P15: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P16: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637.P17: Multi transport transactions occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: One transport transaction occurred on signal asg with slice name on LHS passed
-- NEED RESULT: ARCH00637: Old transactions were removed on signal asg with slice name on LHS passed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00637
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (6)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00637)
-- ENT00637_Test_Bench(ARCH00637_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00637 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_boolean_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P1" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <= transport
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_boolean_vector (lowb+1),
s_st_boolean_vector (lowb+2),
s_st_boolean_vector (lowb+3)) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_bit_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_bit_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P2" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <= transport
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_bit_vector (lowb+1),
s_st_bit_vector (lowb+2),
s_st_bit_vector (lowb+3)) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_severity_level_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P3" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <= transport
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_severity_level_vector (lowb+1),
s_st_severity_level_vector (lowb+2),
s_st_severity_level_vector (lowb+3)) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_st_string )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P4" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <= transport
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_string (lowb+1),
s_st_string (lowb+2),
s_st_string (lowb+3)) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P5" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <= transport
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_enum1_vector (lowb+1),
s_st_enum1_vector (lowb+2),
s_st_enum1_vector (lowb+3)) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_st_integer_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P6" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <= transport
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_integer_vector (lowb+1),
s_st_integer_vector (lowb+2),
s_st_integer_vector (lowb+3)) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P7" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <= transport
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_int1_vector (lowb+1),
s_st_int1_vector (lowb+2),
s_st_int1_vector (lowb+3)) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_st_time_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P8" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <= transport
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_time_vector (lowb+1),
s_st_time_vector (lowb+2),
s_st_time_vector (lowb+3)) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P9" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <= transport
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_phys1_vector (lowb+1),
s_st_phys1_vector (lowb+2),
s_st_phys1_vector (lowb+3)) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_st_real_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P10" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <= transport
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real_vector (lowb+1),
s_st_real_vector (lowb+2),
s_st_real_vector (lowb+3)) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P11" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <= transport
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_real1_vector (lowb+1),
s_st_real1_vector (lowb+2),
s_st_real1_vector (lowb+3)) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P12" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <= transport
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec1_vector (lowb+1),
s_st_rec1_vector (lowb+2),
s_st_rec1_vector (lowb+3)) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P13" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <= transport
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec2_vector (lowb+1),
s_st_rec2_vector (lowb+2),
s_st_rec2_vector (lowb+3)) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P14" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <= transport
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_rec3_vector (lowb+1),
s_st_rec3_vector (lowb+2),
s_st_rec3_vector (lowb+3)) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P15" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <= transport
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr1_vector (lowb+1),
s_st_arr1_vector (lowb+2),
s_st_arr1_vector (lowb+3)) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P16" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <= transport
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr2_vector (lowb+1),
s_st_arr2_vector (lowb+2),
s_st_arr2_vector (lowb+3)) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3_vector )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> (s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00637.P17" ,
"Multi transport transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <= transport
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
(s_st_arr3_vector (lowb+1),
s_st_arr3_vector (lowb+2),
s_st_arr3_vector (lowb+3)) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00637" ,
"One transport transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00637" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P17 ;
--
--
end ARCH00637 ;
--
entity ENT00637_Test_Bench is
end ENT00637_Test_Bench ;
--
architecture ARCH00637_Test_Bench of ENT00637_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00637 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00637_Test_Bench ;
|
gpl-3.0
|
grwlf/vsim
|
vhdl_ct/ct00348.vhd
|
1
|
3078
|
-- NEED RESULT: ARCH00348: Attribute names passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00348
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 6.6 (1)
-- 6.6 (2)
-- 6.6 (3)
-- 6.6 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00348(ARCH00348)
-- ENT00348_Test_Bench(ARCH00348_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00348 is
generic ( g : integer := 5 ) ;
begin
end ENT00348 ;
architecture ARCH00348 of ENT00348 is
type array_array is array ( 1 to 4 ) of WORK.STANDARD_TYPES.st_arr1 ;
begin
P :
process
function f ( x : integer ) return WORK.STANDARD_TYPES.st_arr1 is
variable a : WORK.STANDARD_TYPES.st_arr1 ;
begin
return a ;
end f ;
function "+" ( a,b : WORK.STANDARD_TYPES.st_arr1 )
return WORK.STANDARD_TYPES.st_arr1 is
variable c : WORK.STANDARD_TYPES.st_arr1 ;
begin
for i in st_arr1'range loop
c(i) := a(i) + b(i) ;
end loop ;
return c ;
end "+" ;
variable i1,i2,i3,i4,i5,i6,i7,i8,i9,j : integer := 3 ;
variable b : boolean ;
variable a1 : WORK.STANDARD_TYPES.st_arr1 := c_st_arr1_2;
variable a2 : WORK.STANDARD_TYPES.st_arr2 := c_st_arr2_2;
variable a_a : array_array ;
begin
-- these test 6.6 (1)
i1 := st_arr1'left ; -- prefix is a simple name
i2 := WORK.STANDARD_TYPES.st_arr1'left ; -- prefix is a selected name
i3 := a2(1,b)'left ; -- prefix is an indexed name
i4 := a1(2 to 4)'left ; -- prefix is a slice name
-- i5 := f(j)'left ; -- prefix is a function call (not legal)
-- i6 := P."+"'left ; -- prefix is an operator symbol (not legal)
i7 := a_a(1)'right ; -- this tests 6.6 (2)
i8 := a_a(g-2)'right ; -- this tests 6.6 (3)
i9 := a_a(j+1)'right ; -- this tests 6.6 (4)
test_report ( "ARCH00348" ,
"Attribute names" ,
(i1 = lowb) and
(i2 = lowb) and
(i3 = lowb) and
(i4 = 2) and
-- (i5 = lowb) and -- taken out
-- (i6 = lowb) and -- taken out
(i7 = highb) and
(i8 = highb) and
(i9 = highb)
) ;
wait ;
end process P ;
end ARCH00348 ;
entity ENT00348_Test_Bench is
end ENT00348_Test_Bench ;
architecture ARCH00348_Test_Bench of ENT00348_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00348 ( ARCH00348 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00348_Test_Bench ;
|
gpl-3.0
|
rad-/65C816_SoftCore
|
65816_Interface_System.srcs/sources_1/ipshared/rad-/AXIinterfacefor65816_v5_0/680c2b9f/hdl/AXIinterfacefor65816_v1_0_S00_AXI.vhd
|
2
|
37571
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXIinterfacefor65816_v1_0_S00_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
clk : in std_logic;
tru_clk: in std_logic;
reset_65816_module : in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end AXIinterfacefor65816_v1_0_S00_AXI;
architecture arch_imp of AXIinterfacefor65816_v1_0_S00_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 4;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 32
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
--
--
-- CUSTOM INTERFACE PORTS AND SIGNALS
--
--
COMPONENT Soft_65C816
PORT(
clk : IN std_logic;
tru_clk : IN std_logic;
reset : IN std_logic;
Addr_Bus : OUT std_logic_vector(23 downto 0);
D_BUS : IN std_logic_vector(31 downto 0);
D_BUS_out : out std_logic_vector(23 downto 0);
EMULATION_SELECT : OUT std_logic;
RDY : out std_logic;
DATA_RDY: in std_logic;
REG_A : OUT std_logic_vector(15 downto 0);
REG_X : OUT std_logic_vector(15 downto 0);
REG_Y : OUT std_logic_vector(15 downto 0);
REG_SP : OUT std_logic_vector(15 downto 0);
REG_PC : OUT std_logic_vector(15 downto 0);
REG_Proc : OUT std_logic_vector(7 downto 0);
REG_DBR : OUT std_logic_vector(7 downto 0);
state_machine :out std_logic_vector(15 downto 0);
RW :out std_logic ; -- Read or write bit
VPB : OUT std_logic
);
END COMPONENT;
--Component Outputs
signal Addr_Bus : std_logic_vector(23 downto 0) := (others=> '0');-- Comes from slave register #0;
signal EMULATION_SELECT : std_logic; -- Comes from slave register #1
signal REG_A : std_logic_vector(15 downto 0); -- Comes from slave register #2
signal REG_X : std_logic_vector(15 downto 0); -- Comes from slave register #3
signal REG_Y : std_logic_vector(15 downto 0); -- Comes from slave register #4
signal REG_SP : std_logic_vector(15 downto 0); -- Comes from slave register #5
signal REG_PC : std_logic_vector(15 downto 0); -- Comes from slave register #6
signal REG_Proc : std_logic_vector(7 downto 0); -- Comes from slave register #7
signal REG_DBR : std_logic_vector(7 downto 0); -- Comes from slave register #8
signal state_machine : std_logic_vector(15 downto 0); -- Comes from slave register #9
signal VPB : std_logic;
signal RDY : std_logic; -- Comes from slave register #10
signal D_BUS_out:std_logic_vector(23 downto 0):=(others => '0'); -- Comes from slave register #13
signal RW : std_logic; -- Comes from slave register #10
--Component Inputs
--signal reset : std_logic := '0'; -- Comes from switch
signal D_BUS : std_logic_vector(31 downto 0) := (others => 'Z'); -- Goes to slave register #11
signal DATA_RDY: std_logic := '1'; -- Comes from slave register #12
--Internal Signals
begin
-- BEGIN User designated port maps
D_BUS <= slv_reg11;
DATA_RDY <= slv_reg12(0);
-- Instantiate the Soft 65816 Unit to be implemented
HEART: Soft_65C816 PORT MAP (
clk => clk,
tru_clk => tru_clk,
reset => reset_65816_module,
Addr_Bus => Addr_Bus,
D_BUS => D_BUS,
D_BUS_out => D_BUS_out,
EMULATION_SELECT => EMULATION_SELECT,
RDY => RDY,
RW => RW,
DATA_RDY => DATA_RDY,
REG_A => REG_A,
REG_X => REG_X,
REG_Y => REG_Y,
REG_SP => REG_SP,
REG_PC => REG_PC,
REG_Proc => REG_Proc,
REG_DBR => REG_DBR,
state_machine => state_machine,
VPB => VPB
);
-- END User designated port maps
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"00111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 13
slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 14
slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"01111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 15
slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 16
slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 17
slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 18
slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 19
slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 20
slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 21
slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 22
slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 23
slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 24
slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 25
slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 26
slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 27
slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 28
slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 29
slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 30
slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"11111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 31
slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00000" =>
reg_data_out <= X"00" & Addr_Bus;
when b"00001" =>
reg_data_out <= X"0000000" & b"000" & EMULATION_SELECT;
when b"00010" =>
reg_data_out <= X"0000" & REG_A;
when b"00011" =>
reg_data_out <= X"0000" & REG_X;
when b"00100" =>
reg_data_out <= X"0000" & REG_Y;
when b"00101" =>
reg_data_out <= X"0000" & REG_SP;
when b"00110" =>
reg_data_out <= X"0000" & REG_PC;
when b"00111" =>
reg_data_out <= X"000000" & REG_Proc;
when b"01000" =>
reg_data_out <= X"000000" & REG_DBR;
when b"01001" =>
reg_data_out <= X"0000" & state_machine;
when b"01010" =>
reg_data_out <= X"0000000" & b"00" & RW & RDY;
when b"01011" =>
reg_data_out <= D_BUS;
when b"01100" =>
reg_data_out <= X"0000000" & b"000" & DATA_RDY;
when b"01101" =>
reg_data_out <= X"00" & D_BUS_out;
when b"01110" =>
reg_data_out <= slv_reg14;
when b"01111" =>
reg_data_out <= slv_reg15;
when b"10000" =>
reg_data_out <= slv_reg16;
when b"10001" =>
reg_data_out <= slv_reg17;
when b"10010" =>
reg_data_out <= slv_reg18;
when b"10011" =>
reg_data_out <= slv_reg19;
when b"10100" =>
reg_data_out <= slv_reg20;
when b"10101" =>
reg_data_out <= slv_reg21;
when b"10110" =>
reg_data_out <= slv_reg22;
when b"10111" =>
reg_data_out <= slv_reg23;
when b"11000" =>
reg_data_out <= slv_reg24;
when b"11001" =>
reg_data_out <= slv_reg25;
when b"11010" =>
reg_data_out <= slv_reg26;
when b"11011" =>
reg_data_out <= slv_reg27;
when b"11100" =>
reg_data_out <= slv_reg28;
when b"11101" =>
reg_data_out <= slv_reg29;
when b"11110" =>
reg_data_out <= slv_reg30;
when b"11111" =>
reg_data_out <= X"0000AC32";
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
--PROC_for_65816_syncronization:
-- process (clk) is
-- begin
-- if rising_edge(clk) then
-- end if;
-- end process;
-- User logic ends
end arch_imp;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_reset.vhd
|
4
|
66988
|
-------------------------------------------------------------------------------
-- axi_vdma_reset
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
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-- CRITICAL APPLICATIONS
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-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_vdma_reset is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_INCLUDE_SG : integer range 0 to 1 := 0
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
);
port (
-- Clock Sources
s_axi_lite_aclk : in std_logic ; --
m_axi_sg_aclk : in std_logic ; --
prmry_axi_aclk : in std_logic ; --
prmry_axis_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
--
run_stop : in std_logic ; --
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
fsize_mismatch_err : in std_logic ; -- CR591965
hrd_axi_resetn : out std_logic ; --
--
-- MM2S or S2MM Main Primary Reset (Hard and Soft) --
prmry_resetn : out std_logic := '0' ; --
-- MM2S or S2MM Main Datamover Primary Reset (RAW) (Hard and Soft) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI Stream Reset (Hard and Soft) --
axis_resetn : out std_logic := '1' ; --
-- AXI Stream Reset Out (Hard and Soft) --
axis_reset_out_n : out std_logic ; --
-- AXI Scatter/Gather Reset (Hard and Soft) --
axi_sg_resetn : out std_logic ; --
-- AXI Scatter/Gather Reset (RAW) (Hard and Soft) --
axi_dm_sg_resetn : out std_logic --
);
end axi_vdma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
constant SEVEN_COUNT : std_logic_vector(2 downto 0) := (others => '1');
constant FIFTEEN_COUNT : std_logic_vector(3 downto 0) := (others => '1');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
--signal min_assert_sftrst_d1 : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Composite reset (hard and soft)
signal resetn_i : std_logic := '1';
-- Data Mover Halt
signal halt_i : std_logic := '0';
signal halt_reset : std_logic := '0';
signal run_stop_d1 : std_logic := '0'; -- CR581004
signal run_stop_fe : std_logic := '0'; -- CR581004
-- Reset outputs
signal axis_resetn_i : std_logic := '1';
signal prmry_resetn_i : std_logic := '1';
signal axi_sg_resetn_i : std_logic := '1';
signal hrd_axi_resetn_i : std_logic := '1';
signal sg_min_assert_sftrst : std_logic := '0';
signal sg_soft_reset_re : std_logic := '0';
signal sg_all_idle : std_logic := '0';
signal lite_min_assert_sftrst : std_logic := '0';
signal lite_soft_reset_re : std_logic := '0';
signal lite_all_idle : std_logic := '0';
signal axis_min_assert_sftrst : std_logic := '0';
signal axis_soft_reset_re : std_logic := '0';
signal axis_all_idle : std_logic := '0';
-- Soft reset support
signal prmry_min_assert_sftrst : std_logic := '0';
signal p_sg_min_assert_sftrst : std_logic := '0';
signal p_lite_min_assert_sftrst : std_logic := '0';
signal p_axis_min_assert_sftrst : std_logic := '0';
signal clear_sft_rst_hold : std_logic := '0';
signal sg_clear_sft_rst_hold : std_logic := '0';
signal lite_clear_sft_rst_hold : std_logic := '0';
signal axis_clear_sft_rst_hold : std_logic := '0';
signal prmry_min_count : std_logic_vector(3 downto 0) := (others => '0');
signal sg_min_count : std_logic_vector(3 downto 0) := (others => '0');
signal lite_min_count : std_logic_vector(3 downto 0) := (others => '0');
signal axis_min_count : std_logic_vector(3 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
hrd_axi_resetn <= hrd_axi_resetn_i;
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or hrd_axi_resetn_i = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- rising edge pulse on DMACR soft reset
soft_reset_re <= soft_reset and not soft_reset_d1;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not hrd_axi_resetn_i);
-------------------------------------------------------------------------------
-- Run Stop turned off by user (i.e. not an error and not a soft reset)
-------------------------------------------------------------------------------
-- CR581004 - When AXI VDMA in asynchronous mode does not come out of intial soft reset
-- Generate falling edge pulse for run_stop de-assertion
-- indicating run_stop turned off.
-- Only assert if not soft_reset and not stop (i.e. error)
REG_RUN_STOP_FE : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(resetn_i = '0' or soft_reset = '1' or stop = '1')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_STOP_FE;
run_stop_fe <= not run_stop and run_stop_d1;
---------------------------------------------------------------------------
-- Minimum soft reset in primary domain
---------------------------------------------------------------------------
GEN_MIN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
PRMRY_MIN_RESET_ASSERTION : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(clear_sft_rst_hold = '1')then
prmry_min_count <= (others => '0');
prmry_min_assert_sftrst <= '0';
elsif(s_soft_reset_i_re = '1')then
prmry_min_count <= (others => '0');
prmry_min_assert_sftrst <= '1';
elsif(prmry_min_assert_sftrst='1' and prmry_min_count = FIFTEEN_COUNT)then
prmry_min_count <= FIFTEEN_COUNT;
prmry_min_assert_sftrst <= '1';
elsif(prmry_min_assert_sftrst='1' and all_idle = '1')then
prmry_min_count <= std_logic_vector(unsigned(prmry_min_count) + 1);
prmry_min_assert_sftrst <= '1';
end if;
end if;
end process PRMRY_MIN_RESET_ASSERTION;
---------------------------------------------------------------------------
-- Minimum soft reset in lite domain
---------------------------------------------------------------------------
---- LITE_RESET_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => s_soft_reset_i_re ,
---- scndry_out => lite_soft_reset_re ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
LITE_RESET_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => s_soft_reset_i_re,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '1',
scndry_out => lite_soft_reset_re,
scndry_vect_out => open
);
---- LITE_IDLE_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => all_idle ,
---- scndry_out => lite_all_idle ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
LITE_IDLE_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '1',
scndry_out => lite_all_idle,
scndry_vect_out => open
);
LITE_MIN_RESET_ASSERTION : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(lite_clear_sft_rst_hold = '1')then
lite_min_count <= (others => '0');
lite_min_assert_sftrst <= '0';
elsif(lite_soft_reset_re = '1')then
lite_min_count <= (others => '0');
lite_min_assert_sftrst <= '1';
elsif(lite_min_assert_sftrst='1' and lite_min_count = FIFTEEN_COUNT)then
lite_min_count <= FIFTEEN_COUNT;
lite_min_assert_sftrst <= '1';
elsif(lite_min_assert_sftrst ='1' and lite_all_idle = '1')then
lite_min_count <= std_logic_vector(unsigned(lite_min_count) + 1);
lite_min_assert_sftrst <= '1';
end if;
end if;
end process LITE_MIN_RESET_ASSERTION;
-- Cross back to primary
---- LITE_MIN_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => lite_min_assert_sftrst ,
---- prmry_out => p_lite_min_assert_sftrst ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
LITE_MIN_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '1',
prmry_in => lite_min_assert_sftrst,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => p_lite_min_assert_sftrst,
scndry_vect_out => open
);
---- LITE_CLR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => clear_sft_rst_hold ,
---- scndry_out => lite_clear_sft_rst_hold ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
LITE_CLR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => clear_sft_rst_hold,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '1',
scndry_out => lite_clear_sft_rst_hold,
scndry_vect_out => open
);
---------------------------------------------------------------------------
-- Minimum soft reset in axis domain
---------------------------------------------------------------------------
---- AXIS_RESET_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => s_soft_reset_i_re ,
---- scndry_out => axis_soft_reset_re ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
AXIS_RESET_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => s_soft_reset_i_re,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_soft_reset_re,
scndry_vect_out => open
);
---- AXIS_IDLE_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => all_idle ,
---- scndry_out => axis_all_idle ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
AXIS_IDLE_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_all_idle,
scndry_vect_out => open
);
AXIS_MIN_RESET_ASSERTION : process(prmry_axis_aclk)
begin
if(prmry_axis_aclk'EVENT and prmry_axis_aclk = '1')then
if(axis_clear_sft_rst_hold = '1')then
axis_min_count <= (others => '0');
axis_min_assert_sftrst <= '0';
elsif(axis_soft_reset_re = '1')then
axis_min_count <= (others => '0');
axis_min_assert_sftrst <= '1';
elsif(axis_min_assert_sftrst='1' and axis_min_count = FIFTEEN_COUNT)then
axis_min_count <= FIFTEEN_COUNT;
axis_min_assert_sftrst <= '1';
elsif(axis_min_assert_sftrst ='1' and axis_all_idle = '1')then
axis_min_count <= std_logic_vector(unsigned(axis_min_count) + 1);
axis_min_assert_sftrst <= '1';
end if;
end if;
end process AXIS_MIN_RESET_ASSERTION;
-- Cross back to primary
---- AXIS_MIN_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => axis_min_assert_sftrst ,
---- prmry_out => p_axis_min_assert_sftrst ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
AXIS_MIN_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axis_aclk,
prmry_resetn => '1',
prmry_in => axis_min_assert_sftrst,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => p_axis_min_assert_sftrst,
scndry_vect_out => open
);
---- AXIS_CLR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => clear_sft_rst_hold ,
---- scndry_out => axis_clear_sft_rst_hold ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
AXIS_CLR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => clear_sft_rst_hold,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_clear_sft_rst_hold,
scndry_vect_out => open
);
---------------------------------------------------------------------------
-- Minimum soft reset in sg domain
---------------------------------------------------------------------------
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
---- SG_RESET_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => s_soft_reset_i_re ,
---- scndry_out => sg_soft_reset_re ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_RESET_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => s_soft_reset_i_re,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => sg_soft_reset_re,
scndry_vect_out => open
);
---- SG_IDLE_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => all_idle ,
---- scndry_out => sg_all_idle ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_IDLE_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => sg_all_idle,
scndry_vect_out => open
);
SG_MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_clear_sft_rst_hold = '1')then
sg_min_count <= (others => '0');
sg_min_assert_sftrst <= '0';
elsif(sg_soft_reset_re = '1')then
sg_min_count <= (others => '0');
sg_min_assert_sftrst <= '1';
elsif(sg_min_assert_sftrst='1' and sg_min_count = FIFTEEN_COUNT)then
sg_min_count <= FIFTEEN_COUNT;
sg_min_assert_sftrst <= '1';
elsif(sg_min_assert_sftrst ='1' and sg_all_idle = '1')then
sg_min_count <= std_logic_vector(unsigned(sg_min_count) + 1);
sg_min_assert_sftrst <= '1';
end if;
end if;
end process SG_MIN_RESET_ASSERTION;
-- Cross back to primary
---- SG_MIN_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => sg_min_assert_sftrst ,
---- prmry_out => p_sg_min_assert_sftrst ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_MIN_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axi_sg_aclk,
prmry_resetn => '1',
prmry_in => sg_min_assert_sftrst,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => p_sg_min_assert_sftrst,
scndry_vect_out => open
);
---- SG_CLR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => clear_sft_rst_hold ,
---- scndry_out => sg_clear_sft_rst_hold ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_CLR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => clear_sft_rst_hold,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => sg_clear_sft_rst_hold,
scndry_vect_out => open
);
clear_sft_rst_hold <= prmry_min_assert_sftrst
and p_sg_min_assert_sftrst
and p_lite_min_assert_sftrst
and p_axis_min_assert_sftrst;
-- Assert minimum soft reset.
REG_MIN_SFTRST : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re='1')then
min_assert_sftrst <= '1';
elsif(min_assert_sftrst = '1'
and prmry_min_assert_sftrst = '0'
and p_sg_min_assert_sftrst = '0'
and p_lite_min_assert_sftrst = '0'
and p_axis_min_assert_sftrst = '0')then
min_assert_sftrst <= '0';
end if;
end if;
end process REG_MIN_SFTRST;
end generate GEN_FOR_SG;
-- No SG so do not look at sg_min_assert signal
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
begin
clear_sft_rst_hold <= prmry_min_assert_sftrst
and p_lite_min_assert_sftrst
and p_axis_min_assert_sftrst;
-- Assert minimum soft reset.
REG_MIN_SFTRST : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re='1')then
min_assert_sftrst <= '1';
elsif(min_assert_sftrst = '1'
and prmry_min_assert_sftrst = '0'
and p_lite_min_assert_sftrst = '0'
and p_axis_min_assert_sftrst = '0')then
min_assert_sftrst <= '0';
end if;
end if;
end process REG_MIN_SFTRST;
end generate GEN_FOR_NO_SG;
end generate GEN_MIN_FOR_ASYNC;
GEN_MIN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 15 clock later. Used to set minimum 16clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 16 clocks.
PRMRY_MIN_RESET_ASSERTION : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly15 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process PRMRY_MIN_RESET_ASSERTION;
end generate GEN_MIN_FOR_SYNC;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and (halt_cmplt = '1' or halt_reset = '1'))then
s_soft_reset_i <= '1';
else
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
-- CR581004 - When AXI VDMA in asynchronous mode does not come out of intial soft reset
-- Soft reset or error or turned off therefore issue halt to datamover
--elsif(soft_reset_re = '1' or stop = '1' or run_stop = '0')then
--elsif(soft_reset_re = '1' or stop = '1' or run_stop_fe = '1')then
--
-- CR591965 need to halt and reset data mover on frame size mismatch inorder to correctly
-- flush out datamover and prep for starting up again on next frame sync. This is really
-- only needed for flush on frame sync mode. Signal is redundant in non-flush on frame sync mode
elsif(soft_reset_re = '1' or stop = '1' or run_stop_fe = '1' or fsize_mismatch_err = '1')then
halt_i <= '1';
-- If halt due to turn off then clear on halt reset else will
-- clear once resetn_i asserts for soft reset
--elsif(halt_reset = '1' and stop = '0' and run_stop = '1')then
elsif(halt_reset = '1' and stop = '0' and run_stop = '1')then
halt_i <= '0';
end if;
end if;
end process REG_DM_HALT;
-- Halt To DataMover
halt <= halt_i;
-- AXI Stream reset output
--REG_AXIS_RESET_OUT : process(prmry_axi_aclk)
-- begin
-- if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
-- axis_resetn_i <= resetn_i and not s_soft_reset_i;
-- end if;
-- end process REG_AXIS_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
prmry_resetn_i <= resetn_i;
end if;
end process REG_RESET_OUT;
-- Issue hard reset to DM on halt completed
-- specifically for when run_stop is cleared in DMACR
-- Note: If soft_reset then do not issue halt_reset because this will
-- terminate the halt_cmplt too soon and it will not get captured
-- by soft_reset process above. Reset to dm will occur
-- based on resetn_i for the soft_reset case.
HRDRST_DM : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
--CR574564 - on hard reset p_halt de-asserted before halt_cmplt thus
-- halt_reset never asserted causing a system hang
--if(halt_cmplt = '1' and run_stop = '0' and soft_reset = '0')then
-- CR581004 - When AXI VDMA in asynchronous mode does not come out of intial soft reset
--if(halt_cmplt = '1' and halt_i = '1' and soft_reset = '0')then
if(halt_cmplt = '1' and halt_i = '1' and soft_reset = '0' and stop = '0')then
halt_reset <= '1';
elsif(halt_reset = '1' and run_stop = '1')then
halt_reset <= '0';
end if;
end if;
end process HRDRST_DM;
-- System is asynchronous therefore use CDC module to cross
-- resets to appropriate clock domain
GEN_RESET_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Cross top level hard reset in from axi_lite to primary (mm2s or s2mm)
---- HARD_RESET_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => '1' ,
----
---- scndry_aclk => prmry_axi_aclk ,
---- scndry_resetn => '1' ,
----
---- -- Secondary to Primary Clock Crossing
---- scndry_in => '0' ,
---- prmry_out => open ,
----
---- -- Primary to Secondary Clock Crossing
---- prmry_in => axi_resetn ,
---- scndry_out => hrd_axi_resetn_i ,
----
---- -- Secondary Vector to Primary Vector Clock Crossing
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
----
---- -- Primary Vector to Secondary Vector Clock Crossing
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
----
---- );
----
HARD_RESET_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '1',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => hrd_axi_resetn_i,
scndry_vect_out => open
);
-- AXI DataMover Primary Reset (Raw) and primary logic reset
dm_prmry_resetn <= resetn_i and not halt_reset;
prmry_resetn <= prmry_resetn_i;
-- Scatter Gather Mode
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
-- AXI_SG_RESET_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
-- generic map(
-- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
-- C_VECTOR_WIDTH => 1
-- )
-- port map(
-- prmry_aclk => prmry_axi_aclk ,
-- prmry_resetn => '1' ,
--
-- scndry_aclk => m_axi_sg_aclk ,
-- scndry_resetn => '1' ,
--
-- -- Secondary to Primary Clock Crossing
-- scndry_in => '0' ,
-- prmry_out => open ,
--
-- -- Primary to Secondary Clock Crossing
-- prmry_in => resetn_i ,
-- scndry_out => axi_sg_resetn_i ,
--
-- -- Secondary Vector to Primary Vector Clock Crossing
-- scndry_vect_s_h => '0' ,
-- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
-- prmry_vect_out => open ,
--
-- -- Primary Vector to Secondary Vector Clock Crossing
-- prmry_vect_s_h => '0' ,
-- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
-- scndry_vect_out => open
--
-- );
--
AXI_SG_RESET_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => resetn_i,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => axi_sg_resetn_i,
scndry_vect_out => open
);
-- Scatter Gather Datamover and Logic Reset
axi_dm_sg_resetn <= axi_sg_resetn_i;
axi_sg_resetn <= axi_sg_resetn_i;
end generate GEN_FOR_SG;
-- Register Direct Mode
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
axi_dm_sg_resetn <= '1';
axi_sg_resetn <= '1';
end generate GEN_FOR_NO_SG;
---- AXIS_RESET_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
----
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
----
---- -- Secondary to Primary Clock Crossing
---- scndry_in => '0' ,
---- prmry_out => open ,
----
---- -- Primary to Secondary Clock Crossing
---- prmry_in => resetn_i ,
---- scndry_out => axis_resetn_i ,
----
---- -- Secondary Vector to Primary Vector Clock Crossing
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
----
---- -- Primary Vector to Secondary Vector Clock Crossing
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
----
---- );
AXIS_RESET_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => resetn_i,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_resetn_i,
scndry_vect_out => open
);
-- AXIS (MM2S or S2MM) logic reset and reset out
axis_resetn <= axis_resetn_i;
axis_reset_out_n <= axis_resetn_i;
end generate GEN_RESET_FOR_ASYNC;
-- System is synchronous therefore map internal resets to all
-- reset outputs
GEN_RESET_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- Hard reset in
hrd_axi_resetn_i <= axi_resetn;
-- AXI DataMover Primary Reset (Raw) and primary logic reset
prmry_resetn <= prmry_resetn_i;
dm_prmry_resetn <= resetn_i and not halt_reset;
-- Scatter Gather Mode
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
-- Scatter Gather Engine Reset
axi_sg_resetn <= prmry_resetn_i;
axi_dm_sg_resetn <= resetn_i;
end generate GEN_FOR_SG;
-- Register Direct Mode
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather Engine Reset
axi_sg_resetn <= '1';
axi_dm_sg_resetn <= '1';
end generate GEN_FOR_NO_SG;
-- AXIS (MM2S or S2MM) logic reset and reset out
axis_resetn <= prmry_resetn_i;
axis_reset_out_n <= prmry_resetn_i;
end generate GEN_RESET_FOR_SYNC;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_piano/zybo_petalinux_piano.srcs/sources_1/bd/block_design/ipshared/analogdeviceinc.com/axi_i2s_adi_v1_0/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd
|
7
|
1587
|
library ieee;
use ieee.std_logic_1164.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.dma_fifo;
entity axi_streaming_dma_tx_fifo is
generic (
RAM_ADDR_WIDTH : integer := 3;
FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
resetn : in std_logic;
fifo_reset : in std_logic;
-- Enable DMA interface
enable : in Boolean;
-- Write port
S_AXIS_ACLK : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
-- Read port
out_stb : out std_logic;
out_ack : in std_logic;
out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
);
end;
architecture imp of axi_streaming_dma_tx_fifo is
signal in_ack : std_logic;
signal drain_dma : Boolean;
begin
fifo: entity dma_fifo
generic map (
RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
FIFO_DWIDTH => FIFO_DWIDTH
)
port map (
clk => clk,
resetn => resetn,
fifo_reset => fifo_reset,
in_stb => S_AXIS_TVALID,
in_ack => in_ack,
in_data => S_AXIS_TDATA,
out_stb => out_stb,
out_ack => out_ack,
out_data => out_data
);
drain_process: process (S_AXIS_ACLK) is
variable enable_d1 : Boolean;
begin
if rising_edge(S_AXIS_ACLK) then
if resetn = '0' then
drain_dma <= False;
else
if S_AXIS_TLAST = '1' then
drain_dma <= False;
elsif enable_d1 and enable then
drain_dma <= True;
end if;
enable_d1 := enable;
end if;
end if;
end process;
S_AXIS_TREADY <= '1' when in_ack = '1' or drain_dma else '0';
end;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_intrpt.vhd
|
4
|
31463
|
-------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
gpl-3.0
|
mfrechtling/vhdl_fsm
|
src/mem_bank_tb.vhd
|
1
|
3381
|
library ieee;
use ieee.std_logic_1164.all;
entity mem_bank_tb is
end entity;
architecture test_bench of mem_bank_tb is
component mem_bank is
port(clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
rd_ack : out std_logic;
addr : in std_logic_vector(15 downto 0);
wr_data : in std_logic_vector(31 downto 0);
rd_data : out std_logic_vector(31 downto 0));
end component;
signal tb_clk : std_logic := '0';
signal tb_reset : std_logic := '0';
signal tb_wr_en : std_logic := '0';
signal tb_rd_en : std_logic := '0';
signal tb_rd_ack : std_logic := '0';
signal tb_addr : std_logic_vector(15 downto 0) := (others => '0');
signal tb_wr_data : std_logic_vector(31 downto 0) := (others => '0');
signal tb_rd_data : std_logic_vector(31 downto 0) := (others => '0');
begin
tb_clk <= not tb_clk after 10 ns;
mem_bank_0: mem_bank port map(clk => tb_clk,
reset => tb_reset,
wr_en => tb_wr_en,
rd_en => tb_rd_en,
rd_ack => tb_rd_ack,
addr => tb_addr,
wr_data => tb_wr_data,
rd_data => tb_rd_data);
process
type pattern_type is record
--inputs
reset : std_logic;
wr_en : std_logic;
rd_en : std_logic;
addr : std_logic_vector(15 downto 0);
wr_data : std_logic_vector(31 downto 0);
--outputs
rd_ack : std_logic;
rd_data : std_logic_vector(31 downto 0);
end record;
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(('0', '1', '0', x"0000", x"aaaaaaaa", '0', x"00000000"),
('0', '1', '0', x"0001", x"bbbbbbbb", '0', x"00000000"),
('0', '1', '0', x"0002", x"cccccccc", '0', x"00000000"),
('0', '1', '0', x"0003", x"dddddddd", '0', x"00000000"),
('0', '1', '0', x"00e7", x"eeeeeeee", '0', x"00000000"),
('0', '0', '0', x"0000", x"00000000", '0', x"00000000"),
('0', '0', '1', x"0000", x"00000000", '0', x"00000000"),
('0', '0', '1', x"0001", x"00000000", '1', x"aaaaaaaa"),
('0', '0', '1', x"0002", x"00000000", '1', x"bbbbbbbb"),
('0', '0', '1', x"0003", x"00000000", '1', x"cccccccc"),
('0', '0', '1', x"00e7", x"00000000", '1', x"dddddddd"),
('0', '0', '0', x"0000", x"00000000", '1', x"eeeeeeee"),
('0', '0', '0', x"0000", x"00000000", '0', x"00000000"),
('1', '0', '0', x"0000", x"00000000", '0', x"00000000"),
('0', '0', '1', x"0000", x"00000000", '0', x"00000000"),
('0', '0', '1', x"0001", x"00000000", '1', x"01234567"),
('0', '0', '1', x"0002", x"00000000", '1', x"89abcde7"),
('0', '0', '1', x"0003", x"00000000", '1', x"0a0b0c0d"),
('0', '0', '1', x"00e7", x"00000000", '1', x"10203040"),
('0', '0', '0', x"0000", x"00000000", '1', x"deadbeef"),
('0', '0', '0', x"0000", x"00000000", '0', x"00000000"));
begin
assert false report "Start of test." severity note;
for i in patterns'range loop
wait until rising_edge(tb_clk);
tb_reset <= patterns(i).reset;
tb_wr_en <= patterns(i).wr_en;
tb_rd_en <= patterns(i).rd_en;
tb_addr <= patterns(i).addr;
tb_wr_data <= patterns(i).wr_data;
wait for 1 ns;
assert tb_rd_ack = patterns(i).rd_ack
report "Bad rd_ack value." severity error;
assert tb_rd_data = patterns(i).rd_data
report "Bad rd_data value." severity error;
end loop;
assert false report "End of test." severity note;
wait;
end process;
end test_bench;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma.vhd
|
4
|
284148
|
-------------------------------------------------------------------------------
-- axi_vdma
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma.vhd
-- Description: This entity is the top level entity for the AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v5_1_11.axi_datamover.vhd (FULL)
-- |- axi_vdma_v6_2_8.axi_sg_v4_03.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
--library axi_sg_v4_03;
--use axi_sg_v4_03.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
--use proc_common_v4_0_2.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 1;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - all clocks may be asynchronous.
-----------------------------------------------------------------------
-- Video Specific Parameters
-----------------------------------------------------------------------
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads (Saves FPGA Resources)
-- 1 = Enable Video Parameter Reads
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_NUM_FSTORES : integer range 1 to 32 := 3;
-- Number of Frame Stores
C_USE_FSYNC : integer range 0 to 3 := 1;
-- 2013.1 : Spilt into C_USE_MM2S_FSYNC & C_USE_S2MM_FSYNC. C_USE_FSYNC is no longer used.
C_USE_MM2S_FSYNC : integer range 0 to 1 := 0; --2013.1
-- Specifies MM2S channel operation synchronized to frame sync input
-- 0 = channel is Free running
-- 1 = channel uses mm2s_fsync as a frame_sync
C_USE_S2MM_FSYNC : integer range 0 to 2 := 2; --2013.1
-- Specifies MM2S channel operation synchronized to frame sync input
-- 0 = channel is Free running
-- 1 = channel uses s2mm_fsync as a frame_sync
-- 2 = channel uses s2mm_tuser(0) as a frame_sync
C_FLUSH_ON_FSYNC : integer range 0 to 3 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Specifies VDMA will flush on frame sync
-- 0 = Disabled - both channel halts on error detection
-- 1 = Enabled - both channel does not halt and will flush on next fsync
-- 2 = Enabled - ONLY MM2S channel does not halt and will flush on next fsync
-- 3 = Enabled - ONLY S2MM channel does not halt and will flush on next fsync
C_INCLUDE_INTERNAL_GENLOCK : integer range 0 to 1 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Include or exclude the use of internal genlock bus.
-- 0 = Exclude internal genlock bus
-- 1 = Include internal genlock bus
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_MM2S_GENLOCK_MODE : integer range 0 to 3 := 3;
-- Specifies the Gen-Lock mode for the MM2S Channel
-- 0 = Master Mode
-- 1 = Slave Mode
C_MM2S_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1;
-- Specifies the number of Gen-Lock masters a Gen-Lock slave
-- can be synchronized with
C_MM2S_GENLOCK_REPEAT_EN : integer range 0 to 1 := 0;
-- In flush on frame sync mode specifies whether frame number
-- will increment on error'ed frame or repeat error'ed frame
-- 0 = increment frame
-- 1 = repeat frame
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Enable/Disable start of frame generation on tuser(0).
-- 0 = disable SOF
-- 1 = enable SOF
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_MM2S_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Depth of line buffer. Width of the line buffer is derived from Streaming width.
C_MM2S_LINEBUFFER_THRESH : integer range 1 to 65536 := 4; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Almost Empty Threshold. Threshold point at which MM2S line buffer
-- almost empty flag asserts high. Must be a resolution of
-- C_M_AXIS_MM2S_TDATA_WIDTH/8
-- Minimum valid value is C_M_AXIS_MM2S_TDATA_WIDTH/8
-- Maximum valid value is C_MM2S_LINEBUFFER_DEPTH
C_MM2S_MAX_BURST_LENGTH : integer range 2 to 256 := 8;
-- Maximum burst size in databeats per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 64;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_S2MM_GENLOCK_MODE : integer range 0 to 3 := 2;
-- Specifies the Gen-Lock mode for the S2MM Channel
-- 0 = Master Mode
-- 1 = Slave Mode
C_S2MM_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1;
-- Specifies the number of Gen-Lock masters a Gen-Lock slave
-- can be synchronized with
C_S2MM_GENLOCK_REPEAT_EN : integer range 0 to 1 := 1;
-- In flush on frame sync mode specifies whether frame number
-- will increment on error'ed frame or repeat error'ed frame
-- 0 = increment frame
-- 1 = repeat frame
C_S2MM_SOF_ENABLE : integer range 0 to 1 := 1; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Enable/Disable start of frame generation on tuser(0).
-- 0 = disable SOF
-- 1 = enable SOF
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_S2MM_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Depth of line buffer. Width of the line buffer is derived from Streaming width.
C_S2MM_LINEBUFFER_THRESH : integer range 1 to 65536 := 4; --Interally enabled i.e. user values are not passed to the core and this parameter is redundant (2013.1/14.5)
-- Almost Full Threshold. Threshold point at which S2MM line buffer
-- almost full flag asserts high. Must be a resolution of
-- C_M_AXIS_MM2S_TDATA_WIDTH/8
-- Minimum valid value is C_S_AXIS_S2MM_TDATA_WIDTH/8
-- Maximum valid value is C_S2MM_LINEBUFFER_DEPTH
C_S2MM_MAX_BURST_LENGTH : integer range 2 to 256 := 8;
-- Maximum burst size in data beats per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 64;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_S_AXIS_S2MM_TUSER_BITS : integer range 1 to 1 := 1;
-- Slave AXI Stream User Width for S2MM Channel
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '0');
-- Enable debug information
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 0;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 0;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 0;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 0;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 0;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 0;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 0;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 0;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 0;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 0;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 0;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 0;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 0;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_INSTANCE : string := "axi_vdma";
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Control Clocks
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
-- MM2S Clocks
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axis_mm2s_aclk : in std_logic := '0' ; --
-- S2MM Clocks
m_axi_s2mm_aclk : in std_logic := '0' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Video Interface --
----------------------------------------------------------------------- --
mm2s_fsync : in std_logic := '0' ; --
mm2s_frame_ptr_in : in std_logic_vector --
((C_MM2S_GENLOCK_NUM_MASTERS*6)-1 downto 0) := (others => '0'); --
mm2s_frame_ptr_out : out std_logic_vector(5 downto 0); --
s2mm_fsync : in std_logic := '0'; --
s2mm_frame_ptr_in : in std_logic_vector --
((C_S2MM_GENLOCK_NUM_MASTERS*6)-1 downto 0) := (others => '0'); --
s2mm_frame_ptr_out : out std_logic_vector(5 downto 0); --
mm2s_buffer_empty : out std_logic ; --
mm2s_buffer_almost_empty : out std_logic ; --
s2mm_buffer_full : out std_logic ; --
s2mm_buffer_almost_full : out std_logic ; --
--
mm2s_fsync_out : out std_logic ; --
s2mm_fsync_out : out std_logic ; --
mm2s_prmtr_update : out std_logic ; --
s2mm_prmtr_update : out std_logic ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := (others => '0') ; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := (others => '0'); --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; --
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := (others => '0'); --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; --
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); --
s_axis_s2mm_tuser : in std_logic_vector --
(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
--
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_vdma_tstvec : out std_logic_vector(63 downto 0) --
);
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
attribute IP_GROUP : string;
attribute IP_GROUP of axi_vdma : entity is "LOGICORE";
attribute IPTYPE : string;
attribute IPTYPE of axi_vdma : entity is "PERIPHERAL";
attribute RUN_NGCBUILD : string;
attribute RUN_NGCBUILD of axi_vdma : entity is "TRUE";
-----------------------------------------------------------------
-- End of PSFUtil MPD attributes
-----------------------------------------------------------------
end axi_vdma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_vdma,{"
--& "C_FAMILY= " & C_FAMILY
--& ",C_INSTANCE = " & C_INSTANCE
--& ",C_DLYTMR_RESOLUTION= " & integer'image(C_DLYTMR_RESOLUTION)
--& ",C_PRMRY_IS_ACLK_ASYNC= " & integer'image(C_PRMRY_IS_ACLK_ASYNC)
--& ",C_ENABLE_VIDPRMTR_READS= " & integer'image(C_ENABLE_VIDPRMTR_READS)
--& ",C_DYNAMIC_RESOLUTION= " & integer'image(C_DYNAMIC_RESOLUTION)
--& ",C_NUM_FSTORES= " & integer'image(C_NUM_FSTORES)
--& ",C_USE_MM2S_FSYNC= " & integer'image(C_USE_MM2S_FSYNC)
--& ",C_USE_S2MM_FSYNC= " & integer'image(C_USE_S2MM_FSYNC)
--& ",C_INCLUDE_SG= " & integer'image(C_INCLUDE_SG)
--& ",C_INCLUDE_MM2S= " & integer'image(C_INCLUDE_MM2S)
--& ",C_MM2S_GENLOCK_MODE= " & integer'image(C_MM2S_GENLOCK_MODE)
--& ",C_MM2S_GENLOCK_NUM_MASTERS= " & integer'image(C_MM2S_GENLOCK_NUM_MASTERS)
--& ",C_INCLUDE_MM2S_DRE= " & integer'image(C_INCLUDE_MM2S_DRE)
--& ",C_MM2S_LINEBUFFER_DEPTH= " & integer'image(C_MM2S_LINEBUFFER_DEPTH)
--& ",C_MM2S_MAX_BURST_LENGTH= " & integer'image(C_MM2S_MAX_BURST_LENGTH)
--& ",C_M_AXI_MM2S_DATA_WIDTH = " & integer'image(C_M_AXI_MM2S_DATA_WIDTH)
--& ",C_M_AXIS_MM2S_TDATA_WIDTH = " & integer'image(C_M_AXIS_MM2S_TDATA_WIDTH)
--& ",C_INCLUDE_S2MM= " & integer'image(C_INCLUDE_S2MM)
--& ",C_S2MM_GENLOCK_MODE= " & integer'image(C_S2MM_GENLOCK_MODE)
--& ",C_S2MM_GENLOCK_NUM_MASTERS= " & integer'image(C_S2MM_GENLOCK_NUM_MASTERS)
--& ",C_INCLUDE_S2MM_DRE= " & integer'image(C_INCLUDE_S2MM_DRE)
--& ",C_S2MM_LINEBUFFER_DEPTH= " & integer'image(C_S2MM_LINEBUFFER_DEPTH)
--& ",C_S2MM_MAX_BURST_LENGTH= " & integer'image(C_S2MM_MAX_BURST_LENGTH)
--& ",C_M_AXI_S2MM_DATA_WIDTH= " & integer'image(C_M_AXI_S2MM_DATA_WIDTH)
--& ",C_S_AXIS_S2MM_TDATA_WIDTH= " & integer'image(C_S_AXIS_S2MM_TDATA_WIDTH)
--& "}";
--attribute CORE_GENERATION_INFO : string;
--attribute CORE_GENERATION_INFO of implementation : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function width_calc (value_in : integer)
return integer is
variable addr_value : integer := 32;
begin
if (value_in > 32) then
addr_value := 64;
else
addr_value := 32;
end if;
return(addr_value);
end function width_calc;
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Major Version number 0, 1, 2, 3 etc.
constant VERSION_MAJOR : std_logic_vector (3 downto 0) := X"6" ;
-- Minor Version Number 00, 01, 02, etc.
constant VERSION_MINOR : std_logic_vector (7 downto 0) := X"20";
-- Version Revision character (EDK) a,b,c,etc
constant VERSION_REVISION : std_logic_vector (3 downto 0) := X"0" ;
-- Internal build number
constant REVISION_NUMBER : string := "Build Number: P80";
constant C_M_AXI_MM2S_ADDR_WIDTH_NEW : integer := width_calc (C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_NEW : integer := width_calc (C_M_AXI_S2MM_ADDR_WIDTH);
--*****************************************************************************
--** Scatter Gather Engine Configuration
--*****************************************************************************
constant SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
-- Number of Fetch Descriptors to Queue
constant SG_FTCH_DESC2QUEUE : integer := SG_INCLUDE_DESC_QUEUE * 4;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := SG_INCLUDE_DESC_QUEUE * 4;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 7;
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 7;
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- No Descriptor update for video
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1; -- No Descriptor update for video
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 0; -- No Descriptor update for video
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 0; -- No Descriptor update for video
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERR : integer := 0;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERR : integer := 0;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor pointer update bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor status update bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33;
-- Include SG Descriptor Updates
constant EXCLUDE_DESC_UPDATE : integer := 0; -- No Descriptor update for video
-- Include SG Interrupt Logic
constant EXCLUDE_INTRPT : integer := 0; -- Interrupt logic external to sg engine
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
constant EXCLUDE_DLYTMR : integer := 0;
--*****************************************************************************
--** General/Misc Constants
--*****************************************************************************
--constant C_USE_MM2S_FSYNC : integer :=find_mm2s_fsync(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM);
--constant C_USE_S2MM_FSYNC : integer :=find_s2mm_fsync(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM);
constant C_USE_S2MM_FSYNC_01 : integer :=find_s2mm_fsync_01(C_USE_S2MM_FSYNC);
--constant ENABLE_FLUSH_ON_MM2S_FSYNC : integer :=find_mm2s_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_FLUSH_ON_FSYNC);
--constant ENABLE_FLUSH_ON_S2MM_FSYNC : integer :=find_s2mm_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_FLUSH_ON_FSYNC);
--constant ENABLE_FLUSH_ON_MM2S_FSYNC : integer :=find_mm2s_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_USE_FSYNC);
--constant ENABLE_FLUSH_ON_S2MM_FSYNC : integer :=find_s2mm_flush(C_USE_FSYNC,C_INCLUDE_MM2S,C_INCLUDE_S2MM,C_USE_FSYNC);
constant ENABLE_FLUSH_ON_MM2S_FSYNC : integer := C_USE_MM2S_FSYNC;
constant ENABLE_FLUSH_ON_S2MM_FSYNC : integer := C_USE_S2MM_FSYNC_01;
--*****************************************************************************
--** AXI LITE Interface Constants
--*****************************************************************************
--constant TOTAL_NUM_REGISTER : integer := NUM_REG_TOTAL_REGDIR;
constant TOTAL_NUM_REGISTER : integer := get_num_registers(C_INCLUDE_SG,NUM_REG_TOTAL_SG,NUM_REG_TOTAL_REGDIR);
constant C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED : integer := calculated_mm2s_tdata_width(C_M_AXIS_MM2S_TDATA_WIDTH);
constant C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED : integer := calculated_s2mm_tdata_width(C_S_AXIS_S2MM_TDATA_WIDTH);
constant C_MM2S_ENABLE_TKEEP : integer := enable_tkeep_connectivity(C_M_AXIS_MM2S_TDATA_WIDTH,C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED,C_INCLUDE_MM2S_DRE);
constant C_S2MM_ENABLE_TKEEP : integer := enable_tkeep_connectivity(C_S_AXIS_S2MM_TDATA_WIDTH,C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED,C_INCLUDE_S2MM_DRE);
-- Specifies to register module which channel is which
constant CHANNEL_IS_MM2S : integer := 1;
constant CHANNEL_IS_S2MM : integer := 0;
--*****************************************************************************
--** DataMover General Constants
--*****************************************************************************
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
constant DM_CMDSTS_FIFO_DEPTH : integer := 4;
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 4;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- Datamover clock always synchronous
constant DM_CLOCK_SYNC : integer := 0;
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
constant ZERO_VALUE : std_logic_vector(1023 downto 0) := (others => '0');
--*****************************************************************************
--** S2MM DataMover Specific Constants
--*****************************************************************************
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := C_INCLUDE_S2MM * AXI_FULL_MODE;
-- CR591965 - Modified for flush on frame sync
-- Enable indeterminate BTT on datamover when S2MM Store And Forward Present
-- In this mode, the DataMovers S2MM store and forward buffer will be used
-- and underflow and overflow will be detected via receive byte compare
-- Enable indeterminate BTT on datamover when S2MM flush on frame sync is
-- enabled allowing S2MM AXIS stream absorption and prevent datamover
-- halt. Overflow and Underfow error detected external to datamover
-- in axi_vdma_cmdsts.vhd
constant DM_SUPPORT_INDET_BTT : integer := 1;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- DataMover status width is based on mode of operation
constant S2MM_DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- Never extend on S2MM
constant S2MM_DM_CMD_EXTENDED : integer := 0;
-- Minimum value required for length width based on burst size and stream dwidth
-- If hsize is too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant S2MM_DM_BTT_LENGTH_WIDTH : integer := required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED,
C_S2MM_MAX_BURST_LENGTH,
HSIZE_DWIDTH);
constant C_INCLUDE_S2MM_SF_INT : integer := 1;
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF_INT,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED);
--*****************************************************************************
--** MM2S DataMover Specific Constants
--*****************************************************************************
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := C_INCLUDE_MM2S * AXI_FULL_MODE;
-- Never extend on MM2S
constant MM2S_DM_CMD_NOT_EXTENDED : integer := 0;
-- DataMover status width - fixed to 8 for MM2S
constant MM2S_DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH;
-- Minimum value required for length width based on burst size and stream dwidth
-- If hsize is too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant MM2S_DM_BTT_LENGTH_WIDTH : integer := required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED,
C_MM2S_MAX_BURST_LENGTH,
HSIZE_DWIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
----constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
---- C_M_AXI_MM2S_DATA_WIDTH,
---- C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED);
----
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(0,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED);
--constant DM_MM2S_INCLUDE_SF : integer := 0;
--*****************************************************************************
--** Line Buffer Constants
--*****************************************************************************
-- For LineBuffer, track vertical lines to allow de-assertion of tready
-- when s2mm finished with frame. MM2S does not need to track lines
constant TRACK_NO_LINES : integer := 0;
constant TRACK_LINES : integer := 1;
-- zero vector of vsize width used to tie off mm2s line tracking ports
constant VSIZE_ZERO : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer default Almost Empty Threshold and Almost Full threshold
constant LINEBUFFER_AE_THRESH : integer := 1;
constant LINEBUFFER_AF_THRESH : integer := max2(1,C_MM2S_LINEBUFFER_DEPTH/2);
-- Include and Exclude settings for linebuffer skid buffers
constant INCLUDE_MSTR_SKID_BUFFER : integer := 1;
constant EXCLUDE_MSTR_SKID_BUFFER : integer := 0;
constant INCLUDE_SLV_SKID_BUFFER : integer := 1;
constant EXCLUDE_SLV_SKID_BUFFER : integer := 0;
-------- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode
-------- Also converts depth in bytes to depth in data beats
------constant MM2S_LINEBUFFER_DEPTH : integer := max2(128,(max2((C_MM2S_LINEBUFFER_DEPTH/(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8)),
------ (C_PRMRY_IS_ACLK_ASYNC*512))));
------
-------- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode
-------- Also converts depth in bytes to depth in data beats
------constant S2MM_LINEBUFFER_DEPTH : integer := max2(128,(max2((C_S2MM_LINEBUFFER_DEPTH/(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8)),
------ (C_PRMRY_IS_ACLK_ASYNC*512))));
------
--2013.1
--constant MM2S_LINEBUFFER_DEPTH : integer := C_MM2S_LINEBUFFER_DEPTH;
--constant S2MM_LINEBUFFER_DEPTH : integer := C_S2MM_LINEBUFFER_DEPTH;
-- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode
constant MM2S_LINEBUFFER_DEPTH : integer := max2(128,(max2(C_MM2S_LINEBUFFER_DEPTH,(C_PRMRY_IS_ACLK_ASYNC*512))));
-- Force a depth of 512 minimum if asynchronous clocks enabled and a 128 minimum for synchronous mode
constant S2MM_LINEBUFFER_DEPTH : integer := max2(128,(max2(C_S2MM_LINEBUFFER_DEPTH,(C_PRMRY_IS_ACLK_ASYNC*512))));
-- Enable SOF only for external frame sync and when SOF Enable parameter set
----constant MM2S_SOF_ENABLE : integer := C_USE_MM2S_FSYNC * C_MM2S_SOF_ENABLE;
--constant MM2S_SOF_ENABLE : integer := C_MM2S_SOF_ENABLE;
constant MM2S_SOF_ENABLE : integer := 1;
--constant S2MM_SOF_ENABLE : integer := C_USE_S2MM_FSYNC * C_S2MM_SOF_ENABLE;
--constant S2MM_SOF_ENABLE : integer := C_USE_S2MM_FSYNC ;
constant S2MM_SOF_ENABLE : integer := C_USE_S2MM_FSYNC_01 ;
--*****************************************************************************
--** GenLock Constants
--*****************************************************************************
-- GenLock Data Widths for Clock Domain Crossing Module
constant MM2S_GENLOCK_SLVE_PTR_DWIDTH : integer := (C_MM2S_GENLOCK_NUM_MASTERS*NUM_FRM_STORE_WIDTH);
constant S2MM_GENLOCK_SLVE_PTR_DWIDTH : integer := (C_S2MM_GENLOCK_NUM_MASTERS*NUM_FRM_STORE_WIDTH);
--constant INTERNAL_GENLOCK_ENABLE : integer := enable_internal_genloc(C_INCLUDE_MM2S, C_INCLUDE_S2MM, C_INCLUDE_INTERNAL_GENLOCK,
-- C_MM2S_GENLOCK_MODE,
-- C_S2MM_GENLOCK_MODE);
--
constant INTERNAL_GENLOCK_ENABLE : integer := enable_internal_genloc(C_INCLUDE_MM2S, C_INCLUDE_S2MM, 1,
C_MM2S_GENLOCK_MODE,
C_S2MM_GENLOCK_MODE);
constant C_MM2S_LINEBUFFER_THRESH_INT : integer := calculated_minimum_mm2s_linebuffer_thresh(C_INCLUDE_MM2S, C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED, C_MM2S_LINEBUFFER_DEPTH);
constant C_S2MM_LINEBUFFER_THRESH_INT : integer := calculated_minimum_s2mm_linebuffer_thresh(C_INCLUDE_S2MM, C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED, C_S2MM_LINEBUFFER_DEPTH);
Constant C_ROOT_FAMILY : string := C_FAMILY; -- function from family_support.vhd
constant C_NUM_FSTORES_64 : integer := C_NUM_FSTORES/(C_M_AXI_S2MM_ADDR_WIDTH_NEW/32);
constant CMD_WIDTH : integer := C_M_AXI_MM2S_ADDR_WIDTH_NEW+CMD_BASE_WIDTH;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
--type STARTADDR_ARRAY_TYPE_64 is array(natural range <>)
-- of std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH - 1 downto 0);
signal mm2s_prmry_resetn : std_logic := '1'; -- AXI MM2S Primary Reset
signal mm2s_dm_prmry_resetn : std_logic := '1'; -- AXI MM2S DataMover Primary Reset (Raw)
signal mm2s_axis_resetn : std_logic := '1'; -- AXIS MM2S Primary Reset
signal mm2s_axis_linebuf_reset_out : std_logic := '1'; -- AXIS MM2S Primary Reset
signal s2mm_axis_linebuf_reset_out : std_logic := '1'; -- AXIS MM2S Primary Reset
signal s2mm_axis_linebuf_reset_out_inv : std_logic := '1'; -- AXIS MM2S Primary Reset
signal s2mm_prmry_resetn : std_logic := '1'; -- AXI S2MM Primary Reset
signal s2mm_dm_prmry_resetn : std_logic := '1'; -- AXI S2MM DataMover Primary Reset (Raw)
signal s2mm_axis_resetn : std_logic := '1'; -- AXIS S2MM Primary Reset
signal s_axi_lite_resetn : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_resetn : std_logic := '1'; -- AXI Scatter Gather Interface Reset
signal m_axi_dm_sg_resetn : std_logic := '1'; -- AXI Scatter Gather Interface Reset (Raw)
signal mm2s_hrd_resetn : std_logic := '1'; -- AXI Hard Reset Only for MM2S
signal s2mm_hrd_resetn : std_logic := '1'; -- AXI Hard Reset Only for S2MM
-- MM2S Register Module Signals
signal mm2s_stop : std_logic := '0';
signal mm2s_stop_reg : std_logic := '0';
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_interr_set_minus_frame_errors : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_num_frame_store : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_linebuf_threshold : std_logic_vector(THRESH_MSB_BIT downto 0) := (others => '0');
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_cmdsts_idle : std_logic := '0';
signal mm2s_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_chnl_current_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_genlock_pair_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_crnt_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal mm2s_crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal mm2s_dlyirq_dsble : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0';
signal mm2s_valid_video_prmtrs : std_logic := '0';
signal mm2s_all_lines_xfred : std_logic := '0';
signal mm2s_all_lines_xfred_s : std_logic := '0';
signal mm2s_all_lines_xfred_s_dwidth : std_logic := '0';
signal mm2s_fsize_mismatch_err : std_logic := '0'; -- CR591965
signal mm2s_lsize_mismatch_err : std_logic := '0'; -- CR591965
signal mm2s_lsize_more_mismatch_err : std_logic := '0'; -- CR591965
signal mm2s_frame_ptr_out_i : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_to_s2mm_fsync : std_logic := '0';
-- MM2S Register Direct Support
signal mm2s_regdir_idle : std_logic := '0';
signal mm2s_prmtr_updt_complete : std_logic := '0';
signal mm2s_reg_module_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0);
signal mm2s_reg_module_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0);
signal mm2s_reg_module_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0);
signal mm2s_reg_module_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0);
signal mm2s_reg_module_strt_addr : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1);
signal mm2s_reg_module_strt_addr_64 : STARTADDR_ARRAY_TYPE_64(0 to C_NUM_FSTORES_64 - 1);
-- MM2S Register Interface Signals
signal mm2s_axi2ip_wrce : std_logic_vector(TOTAL_NUM_REGISTER-1 downto 0) := (others => '0');
signal mm2s_axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0') ;
signal mm2s_axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0') ;
--signal mm2s_axi2ip_rden : std_logic := '0';
signal mm2s_ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0') ;
--signal mm2s_ip2axi_rddata_valid : std_logic := '0';
signal mm2s_ip2axi_frame_ptr_ref : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_ip2axi_frame_store : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_ip2axi_introut : std_logic := '0';
-- MM2S Scatter Gather clock domain crossing signals
signal mm2s_cdc2sg_run_stop : std_logic := '0';
signal mm2s_cdc2sg_stop : std_logic := '0';
signal mm2s_cdc2sg_taildesc_wren : std_logic := '0';
signal mm2s_cdc2sg_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_cdc2sg_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sg2cdc_ftch_idle : std_logic := '0';
signal mm2s_sg2cdc_ftch_interr_set : std_logic := '0';
signal mm2s_sg2cdc_ftch_slverr_set : std_logic := '0';
signal mm2s_sg2cdc_ftch_decerr_set : std_logic := '0';
-- MM2S DMA Controller Signals
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_ftchcmdsts_idle : std_logic := '0';
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH_NEW+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(MM2S_DM_STATUS_WIDTH - 1 downto 0) := (others => '0'); -- CR608521
signal m_axis_mm2s_sts_tkeep : std_logic_vector((MM2S_DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0'); -- CR608521
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_reg : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- DataMover To Line Buffer AXI Stream Signals
signal dm2linebuf_mm2s_tdata : std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0);
signal dm2linebuf_mm2s_tkeep : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8)-1 downto 0);
signal dm2linebuf_mm2s_tlast : std_logic := '0';
signal dm2linebuf_mm2s_tvalid : std_logic := '0';
signal linebuf2dm_mm2s_tready : std_logic := '0';
-- MM2S Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
-- MM2S Soft Reset support
signal mm2s_soft_reset : std_logic := '0';
signal mm2s_soft_reset_clr : std_logic := '0';
-- MM2S SOF generation support
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal m_axis_mm2s_tvalid_i_axis_dw_conv : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_axis_dw_conv : std_logic := '0';
signal s_axis_s2mm_tdata_i : std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tkeep_i : std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8)-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tuser_i : std_logic_vector --
(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tvalid_i : std_logic ; --
signal s_axis_s2mm_tvalid_int : std_logic ; --
signal s_axis_s2mm_tlast_i : std_logic ;
signal m_axis_mm2s_tdata_i : std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) := (others => '0'); --
signal m_axis_mm2s_tkeep_i : std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8)-1 downto 0) := (others => '0'); --
signal m_axis_mm2s_tuser_i : std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0) := (others => '0'); --
signal m_axis_mm2s_tready_i : std_logic ; --
-- S2MM Register Module Signals
signal s2mm_stop : std_logic := '0';
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_interr_set_minus_frame_errors : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_num_frame_store : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal s2mm_linebuf_threshold : std_logic_vector(THRESH_MSB_BIT downto 0) := (others => '0');
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_cmdsts_idle : std_logic := '0';
signal s2mm_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_chnl_current_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_genlock_pair_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dlyirq_dsble : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0';
signal s2mm_valid_video_prmtrs : std_logic := '0';
signal s2mm_crnt_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');-- CR575884
signal s2mm_update_frmstore : std_logic := '0'; --CR582182
signal s2mm_frmstr_err_addr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); --CR582182
signal s2mm_all_lines_xfred : std_logic := '0'; -- CR591965
signal all_lasts_rcvd : std_logic := '0';
signal s2mm_capture_hsize_at_uf_err_sig : std_logic_vector(15 downto 0) ;
signal s2mm_capture_dm_done_vsize_counter_sig : std_logic_vector(12 downto 0) ;
signal s2mm_fsize_mismatch_err_flag : std_logic := '0'; -- CR591965
signal s2mm_fsize_mismatch_err : std_logic := '0'; -- CR591965
signal s2mm_lsize_mismatch_err : std_logic := '0'; -- CR591965
signal s2mm_lsize_more_mismatch_err : std_logic := '0'; -- CR591965
signal s2mm_tuser_fsync : std_logic := '0';
signal s2mm_frame_ptr_out_i : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal s2mm_to_mm2s_fsync : std_logic := '0';
-- S2MM Register Direct Support
signal s2mm_regdir_idle : std_logic := '0';
signal s2mm_prmtr_updt_complete : std_logic := '0';
signal s2mm_reg_module_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0);
signal s2mm_reg_module_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0);
signal s2mm_reg_module_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0);
signal s2mm_reg_module_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0);
signal s2mm_reg_module_strt_addr : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1);
signal s2mm_reg_module_strt_addr_64 : STARTADDR_ARRAY_TYPE_64(0 to C_NUM_FSTORES_64 - 1);
-- S2MM Register Interface Signals
signal s2mm_axi2ip_wrce : std_logic_vector(TOTAL_NUM_REGISTER-1 downto 0) := (others => '0');
signal s2mm_axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
--signal s2mm_axi2ip_rden : std_logic := '0';
signal s2mm_ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
--signal s2mm_ip2axi_rddata_valid : std_logic := '0';
signal s2mm_ip2axi_frame_ptr_ref : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_ip2axi_frame_store : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_ip2axi_introut : std_logic := '0';
-- S2MM Scatter Gather clock domain crossing signals
signal s2mm_cdc2sg_run_stop : std_logic := '0';
signal s2mm_cdc2sg_stop : std_logic := '0';
signal s2mm_cdc2sg_taildesc_wren : std_logic := '0';
signal s2mm_cdc2sg_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_cdc2sg_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_sg2cdc_ftch_idle : std_logic := '0';
signal s2mm_sg2cdc_ftch_interr_set : std_logic := '0';
signal s2mm_sg2cdc_ftch_slverr_set : std_logic := '0';
signal s2mm_sg2cdc_ftch_decerr_set : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_ftchcmdsts_idle : std_logic := '0';
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH_NEW+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(S2MM_DM_STATUS_WIDTH - 1 downto 0) := (others => '0'); -- CR608521
signal m_axis_s2mm_sts_tkeep : std_logic_vector((S2MM_DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0'); -- CR608521
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Line Buffer To DataMover AXI Stream Signals
signal linebuf2dm_s2mm_tdata : std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0);
signal linebuf2dm_s2mm_tkeep : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8)-1 downto 0);
signal linebuf2dm_s2mm_tlast : std_logic := '0';
signal linebuf2dm_s2mm_tvalid : std_logic := '0';
signal dm2linebuf_s2mm_tready : std_logic := '0';
-- S2MM Error Status Control
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
-- S2MM Soft Reset support
signal s2mm_soft_reset : std_logic := '0';
signal s2mm_soft_reset_clr : std_logic := '0';
-- S2MM SOF generation support
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_i_axis_dw_conv : std_logic := '0';
-- Video specific
signal s2mm_frame_sync : std_logic := '0';
signal mm2s_frame_sync : std_logic := '0';
signal mm2s_parameter_update : std_logic := '0';
signal s2mm_parameter_update : std_logic := '0';
-- Line Buffer Support
signal mm2s_allbuffer_empty : std_logic := '0';
signal mm2s_dwidth_fifo_pipe_empty : std_logic := '0';
signal mm2s_dwidth_fifo_pipe_empty_m : std_logic := '0';
-- Video CDC support
signal mm2s_cdc2dmac_fsync : std_logic := '0';
signal mm2s_dmac2cdc_fsync_out : std_logic := '0';
signal mm2s_dmac2cdc_prmtr_update : std_logic := '0';
signal mm2s_vid2cdc_packet_sof : std_logic := '0';
signal s2mm_cdc2dmac_fsync : std_logic := '0';
signal s2mm_dmac2cdc_fsync_out : std_logic := '0';
signal s2mm_dmac2cdc_prmtr_update : std_logic := '0';
signal s2mm_vid2cdc_packet_sof : std_logic := '0';
-- fsync qualified by valid parameters for frame count
-- decrement
signal mm2s_valid_frame_sync : std_logic := '0';
signal s2mm_valid_frame_sync : std_logic := '0';
signal mm2s_valid_frame_sync_cmb : std_logic := '0';
signal s2mm_valid_frame_sync_cmb : std_logic := '0';
--signal for test bench and for output
signal s2mm_tstvect_err : std_logic := '0';
signal mm2s_tstvect_err : std_logic := '0';
signal s2mm_tstvect_fsync : std_logic := '0';
signal mm2s_tstvect_fsync : std_logic := '0';
signal s2mm_tstvect_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tstvect_frame : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_fsync_out_i : std_logic := '0';
signal s2mm_fsync_out_m_i : std_logic := '0';
signal mm2s_fsync_out_i : std_logic := '0';
signal mm2s_mask_fsync_out : std_logic := '0';
signal s2mm_mask_fsync_out : std_logic := '0';
signal mm2s_mstrfrm_tstsync_out : std_logic := '0';
signal s2mm_mstrfrm_tstsync_out : std_logic := '0';
-- Genlock pointer signals
signal mm2s_mstrfrm_tstsync : std_logic := '0';
signal mm2s_s_frame_ptr_in : std_logic_vector(MM2S_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) := (others => '0');
signal mm2s_m_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal s2mm_mstrfrm_tstsync : std_logic := '0';
signal s2mm_s_frame_ptr_in : std_logic_vector(S2MM_GENLOCK_SLVE_PTR_DWIDTH-1 downto 0) := (others => '0');
signal s2mm_m_frame_ptr_out : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tstvect_frm_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tstvect_frm_ptr_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal sg2cdc_ftch_err_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sg2cdc_ftch_err : std_logic := '0';
signal mm2s_ftch_err_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_ftch_err : std_logic := '0';
signal s2mm_ftch_err_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_ftch_err : std_logic := '0';
-- Internal GenLock bus support
signal s2mm_to_mm2s_frame_ptr_in : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_to_s2mm_frame_ptr_in : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal mm2s_reg_index : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_reg_index : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal s2mm_fsync_src_select_s : std_logic_vector(1 downto 0) := (others => '0');
signal hold_dummy_tready_low : std_logic := '0';
signal hold_dummy_tready_low2 : std_logic := '0';
signal drop_fsync_d_pulse_gen_fsize_less_err : std_logic := '0';
signal s2mm_tuser_fsync_top : std_logic := '0';
signal s2mm_fsync_core : std_logic := '0';
signal s2mm_chnl_ready : std_logic := '0';
signal s2mm_strm_not_finished : std_logic := '0';
signal s2mm_strm_all_lines_rcvd : std_logic := '0';
signal s2mm_all_vount_rcvd : std_logic := '0';
signal s2mm_fsize_mismatch_err_s : std_logic := '0';
signal s2mm_fsize_less_err_internal_tvalid_gating : std_logic := '0';
signal s2mm_dummy_tready : std_logic := '0';
signal s2mm_fsize_more_or_sof_late_s : std_logic := '0';
signal s2mm_fsize_more_or_sof_late : std_logic := '0';
signal s_axis_s2mm_tdata_signal : std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tkeep_signal : std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tuser_signal : std_logic_vector --
(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_tvalid_signal : std_logic := '0'; --
signal s_axis_s2mm_tready_signal : std_logic := '0'; --
signal s_axis_s2mm_tlast_signal : std_logic := '0'; --
signal mm2s_fsync_core : std_logic := '0';
signal mm2s_fsize_mismatch_err_s : std_logic := '0';
signal mm2s_fsize_mismatch_err_m : std_logic := '0';
signal MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : std_logic := '0';
signal m_axis_mm2s_tready_i2 : std_logic ; --
signal m_axis_mm2s_tvalid_i2 : std_logic ; --
signal mm2s_fsync_out_m : std_logic := '0';
signal mm2s_fsize_mismatch_err_flag : std_logic := '0'; -- CR591965
signal mm2s_vsize_cntr_clr_flag : std_logic := '0'; -- CR591965
signal mm2s_fsync_d1 : std_logic := '0';
signal mm2s_fsync_d2 : std_logic := '0';
signal mm2s_fsync_fe : std_logic := '0';
signal s2mm_fsync_d1 : std_logic := '0';
signal s2mm_fsync_d2 : std_logic := '0';
signal s2mm_fsync_fe : std_logic := '0';
signal mm2s_buffer_empty_i : std_logic := '0';
signal s2mm_buffer_full_i : std_logic := '0';
signal mm2s_buffer_almost_empty_i : std_logic := '0';
signal s2mm_buffer_almost_full_i : std_logic := '0';
signal mm2s_prmtr_update_i : std_logic := '0';
signal s2mm_prmtr_update_i : std_logic := '0';
signal mm2s_fsync_out_sig : std_logic := '0';
signal s2mm_fsync_out_sig : std_logic := '0';
signal axi_vdma_tstvec_i : std_logic_vector(63 downto 0) := (others => '0');
signal mm2s_prmry_reset_out_n_i : std_logic := '1';
signal s2mm_prmry_reset_out_n_i : std_logic := '1';
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_NEW-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_NEW-1 downto 0) ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ENABLE_MM2S_PRMRY_RESET_OUT_N : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_0 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
mm2s_prmry_reset_out_n <= mm2s_prmry_reset_out_n_i;
end generate ENABLE_MM2S_PRMRY_RESET_OUT_N;
DISABLE_MM2S_PRMRY_RESET_OUT_N : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_0 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
mm2s_prmry_reset_out_n <= '1';
end generate DISABLE_MM2S_PRMRY_RESET_OUT_N;
ENABLE_MM2S_BUFFER_EMPTY : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
mm2s_buffer_empty <= mm2s_buffer_empty_i;
mm2s_buffer_almost_empty <= mm2s_buffer_almost_empty_i;
end generate ENABLE_MM2S_BUFFER_EMPTY;
DISABLE_MM2S_BUFFER_EMPTY : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
mm2s_buffer_empty <= '0';
mm2s_buffer_almost_empty <= '0';
end generate DISABLE_MM2S_BUFFER_EMPTY;
ENABLE_MM2S_PRMTR_UPDATE : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_2 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
mm2s_prmtr_update <= mm2s_prmtr_update_i;
end generate ENABLE_MM2S_PRMTR_UPDATE;
DISABLE_MM2S_PRMTR_UPDATE : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_2 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
mm2s_prmtr_update <= '0';
end generate DISABLE_MM2S_PRMTR_UPDATE;
ENABLE_MM2S_FSYNC_OUT : if (C_INCLUDE_MM2S = 1 and (C_ENABLE_DEBUG_INFO_3 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
mm2s_fsync_out <= mm2s_fsync_out_sig;
end generate ENABLE_MM2S_FSYNC_OUT;
DISABLE_MM2S_FSYNC_OUT : if (C_INCLUDE_MM2S = 0 or (C_ENABLE_DEBUG_INFO_3 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
mm2s_fsync_out <= '0';
end generate DISABLE_MM2S_FSYNC_OUT;
ENABLE_AXI_VDMA_TSTVEC : if (C_ENABLE_DEBUG_INFO_4 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
axi_vdma_tstvec <= axi_vdma_tstvec_i;
end generate ENABLE_AXI_VDMA_TSTVEC;
DISABLE_AXI_VDMA_TSTVEC : if (C_ENABLE_DEBUG_INFO_4 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
axi_vdma_tstvec <= (others => '0');
end generate DISABLE_AXI_VDMA_TSTVEC;
ENABLE_S2MM_PRMRY_RESET_OUT_N : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_8 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
s2mm_prmry_reset_out_n <= s2mm_prmry_reset_out_n_i;
end generate ENABLE_S2MM_PRMRY_RESET_OUT_N;
DISABLE_S2MM_PRMRY_RESET_OUT_N : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_8 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
s2mm_prmry_reset_out_n <= '1';
end generate DISABLE_S2MM_PRMRY_RESET_OUT_N;
ENABLE_S2MM_BUFFER_FULL : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_9 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
s2mm_buffer_full <= s2mm_buffer_full_i;
s2mm_buffer_almost_full <= s2mm_buffer_almost_full_i;
end generate ENABLE_S2MM_BUFFER_FULL;
DISABLE_S2MM_BUFFER_FULL : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_9 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
s2mm_buffer_full <= '0';
s2mm_buffer_almost_full <= '0';
end generate DISABLE_S2MM_BUFFER_FULL;
ENABLE_S2MM_PRMTR_UPDATE : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_10 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
s2mm_prmtr_update <= s2mm_prmtr_update_i;
end generate ENABLE_S2MM_PRMTR_UPDATE;
DISABLE_S2MM_PRMTR_UPDATE : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_10 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
s2mm_prmtr_update <= '0';
end generate DISABLE_S2MM_PRMTR_UPDATE;
ENABLE_S2MM_FSYNC_OUT : if (C_INCLUDE_S2MM = 1 and (C_ENABLE_DEBUG_INFO_11 = 1 or C_ENABLE_DEBUG_ALL = 1)) generate
begin
s2mm_fsync_out <= s2mm_fsync_out_sig;
end generate ENABLE_S2MM_FSYNC_OUT;
DISABLE_S2MM_FSYNC_OUT : if (C_INCLUDE_S2MM = 0 or (C_ENABLE_DEBUG_INFO_11 = 0 and C_ENABLE_DEBUG_ALL = 0)) generate
begin
s2mm_fsync_out <= '0';
end generate DISABLE_S2MM_FSYNC_OUT;
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_vdma_tstvec_i(63 downto 59) <= s2mm_tstvect_frm_ptr_out; ---
axi_vdma_tstvec_i(58 downto 54) <= mm2s_tstvect_frm_ptr_out; ---
axi_vdma_tstvec_i(53 downto 49) <= s2mm_tstvect_frame; ---
axi_vdma_tstvec_i(48 downto 44) <= mm2s_tstvect_frame; ---
axi_vdma_tstvec_i(43 downto 33) <= (others => '0');
axi_vdma_tstvec_i(32) <= s2mm_strm_all_lines_rcvd; --
axi_vdma_tstvec_i(31) <= s2mm_halt; -- DataMover halt tracking
axi_vdma_tstvec_i(30) <= mm2s_halt; -- DataMover halt tracking
axi_vdma_tstvec_i(29) <= s2mm_tstvect_err;
axi_vdma_tstvec_i(28) <= mm2s_tstvect_err;
axi_vdma_tstvec_i(27 downto 24) <= s2mm_tstvect_frm_ptr_out(3 downto 0); --
axi_vdma_tstvec_i(23 downto 20) <= mm2s_tstvect_frm_ptr_out(3 downto 0); --
axi_vdma_tstvec_i(19) <= s2mm_mstrfrm_tstsync_out;
axi_vdma_tstvec_i(18) <= mm2s_mstrfrm_tstsync_out;
axi_vdma_tstvec_i(17) <= s2mm_dmasr(DMASR_HALTED_BIT);
axi_vdma_tstvec_i(16) <= mm2s_dmasr(DMASR_HALTED_BIT);
axi_vdma_tstvec_i(15 downto 12) <= s2mm_tstvect_frame(3 downto 0); --
axi_vdma_tstvec_i(11 downto 8) <= mm2s_tstvect_frame(3 downto 0); --
axi_vdma_tstvec_i(7) <= s2mm_tstvect_fsync
and not s2mm_mask_fsync_out;
axi_vdma_tstvec_i(6) <= mm2s_tstvect_fsync
and not mm2s_mask_fsync_out;
axi_vdma_tstvec_i(5) <= s2mm_tstvect_fsync;
axi_vdma_tstvec_i(4) <= mm2s_tstvect_fsync;
axi_vdma_tstvec_i(3) <= s2mm_dummy_tready and s_axis_s2mm_tvalid_signal;
axi_vdma_tstvec_i(2) <= s2mm_packet_sof;
axi_vdma_tstvec_i(1) <= mm2s_all_lines_xfred;
axi_vdma_tstvec_i(0) <= mm2s_packet_sof;
GEN_MM2S_D1_REG : process(m_axis_mm2s_aclk)
begin
if(m_axis_mm2s_aclk'EVENT and m_axis_mm2s_aclk = '1')then
mm2s_fsync_d1 <= mm2s_fsync;
mm2s_fsync_d2 <= mm2s_fsync_d1;
end if;
end process GEN_MM2S_D1_REG;
mm2s_fsync_fe <= mm2s_fsync_d2 and not mm2s_fsync_d1;
GEN_S2MM_D1_REG : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
s2mm_fsync_d1 <= s2mm_fsync;
s2mm_fsync_d2 <= s2mm_fsync_d1;
end if;
end process GEN_S2MM_D1_REG;
s2mm_fsync_fe <= s2mm_fsync_d2 and not s2mm_fsync_d1;
s2mm_fsize_more_or_sof_late_s <= s2mm_dummy_tready and s_axis_s2mm_tvalid_signal and not s2mm_fsize_less_err_internal_tvalid_gating;
--s_axis_s2mm_tready <= s_axis_s2mm_tready_i_axis_dw_conv;
--m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i_axis_dw_conv;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i2;
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i_axis_dw_conv;
mm2s_frame_ptr_out <= mm2s_frame_ptr_out_i ;
s2mm_frame_ptr_out <= s2mm_frame_ptr_out_i ;
--*****************************************************************************
--** RESET MODULE **
--*****************************************************************************
I_RST_MODULE : entity axi_vdma_v6_2_8.axi_vdma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk => s_axi_lite_aclk ,
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axis_mm2s_aclk => m_axis_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
s_axis_s2mm_aclk => s_axis_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- MM2S Soft Reset Support
-----------------------------------------------------------------------
mm2s_soft_reset => mm2s_soft_reset ,
mm2s_soft_reset_clr => mm2s_soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_ftchcmdsts_idle ,
mm2s_fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
-----------------------------------------------------------------------
-- MM2S Soft Reset Support
-----------------------------------------------------------------------
s2mm_soft_reset => s2mm_soft_reset ,
s2mm_soft_reset_clr => s2mm_soft_reset_clr ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_ftchcmdsts_idle ,
s2mm_fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
-----------------------------------------------------------------------
-- SG Status
-----------------------------------------------------------------------
ftch_err => sg2cdc_ftch_err ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out
-----------------------------------------------------------------------
-- AXI Upsizer and Line Buffer
mm2s_prmry_resetn => mm2s_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
mm2s_dm_prmry_resetn => mm2s_dm_prmry_resetn ,
-- AXI Stream Logic Reset
mm2s_axis_resetn => mm2s_axis_resetn ,
-- AXI Stream Reset Outputs
mm2s_axis_reset_out_n => mm2s_prmry_reset_out_n_i ,
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out
-----------------------------------------------------------------------
s2mm_prmry_resetn => s2mm_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
s2mm_dm_prmry_resetn => s2mm_dm_prmry_resetn ,
-- AXI Stream Logic Reset
s2mm_axis_resetn => s2mm_axis_resetn ,
-- AXI Stream Reset Outputs
s2mm_axis_reset_out_n => s2mm_prmry_reset_out_n_i ,
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out
-----------------------------------------------------------------------
m_axi_sg_resetn => m_axi_sg_resetn ,
m_axi_dm_sg_resetn => m_axi_dm_sg_resetn ,
-----------------------------------------------------------------------
-- AXI Lite Interface Reset Out (Hard Only)
-----------------------------------------------------------------------
s_axi_lite_resetn => s_axi_lite_resetn ,
mm2s_hrd_resetn => mm2s_hrd_resetn ,
s2mm_hrd_resetn => s2mm_hrd_resetn
);
--*****************************************************************************
--** AXI LITE REGISTER INTERFACE **
--*****************************************************************************
-------------------------------------------------------------------------------
-- Provides the s_axi_lite inteface and clock domain crossing between
-- axi lite and mm2s/s2mm register modules
-------------------------------------------------------------------------------
AXI_LITE_REG_INTERFACE_I : entity axi_vdma_v6_2_8.axi_vdma_reg_if
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_VIDPRMTR_READS => C_ENABLE_VIDPRMTR_READS ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_TOTAL_NUM_REGISTER => TOTAL_NUM_REGISTER ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_VERSION_MAJOR => VERSION_MAJOR ,
C_VERSION_MINOR => VERSION_MINOR ,
C_VERSION_REVISION => VERSION_REVISION ,
C_REVISION_NUMBER => REVISION_NUMBER
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_reset_n => s_axi_lite_resetn ,
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S Register Interface
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_hrd_resetn => mm2s_hrd_resetn ,
mm2s_axi2ip_wrce => mm2s_axi2ip_wrce ,
mm2s_axi2ip_wrdata => mm2s_axi2ip_wrdata ,
mm2s_axi2ip_rdaddr => mm2s_axi2ip_rdaddr ,
--mm2s_axi2ip_rden => mm2s_axi2ip_rden ,
mm2s_ip2axi_rddata => mm2s_ip2axi_rddata ,
--mm2s_ip2axi_rddata_valid => mm2s_ip2axi_rddata_valid ,
mm2s_ip2axi_frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref ,
mm2s_ip2axi_frame_store => mm2s_ip2axi_frame_store ,
mm2s_chnl_current_frame => mm2s_chnl_current_frame ,
mm2s_genlock_pair_frame => mm2s_genlock_pair_frame ,
mm2s_ip2axi_introut => mm2s_ip2axi_introut ,
mm2s_introut => mm2s_introut ,
-- S2MM Register Interface
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_hrd_resetn => s2mm_hrd_resetn ,
s2mm_axi2ip_wrce => s2mm_axi2ip_wrce ,
s2mm_axi2ip_wrdata => s2mm_axi2ip_wrdata ,
--s2mm_axi2ip_rden => s2mm_axi2ip_rden ,
s2mm_axi2ip_rdaddr => s2mm_axi2ip_rdaddr ,
s2mm_ip2axi_rddata => s2mm_ip2axi_rddata ,
--s2mm_ip2axi_rddata_valid => s2mm_ip2axi_rddata_valid ,
s2mm_ip2axi_frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref ,
s2mm_ip2axi_frame_store => s2mm_ip2axi_frame_store ,
s2mm_capture_dm_done_vsize_counter => s2mm_capture_dm_done_vsize_counter_sig ,
s2mm_capture_hsize_at_uf_err => s2mm_capture_hsize_at_uf_err_sig ,
s2mm_chnl_current_frame => s2mm_chnl_current_frame ,
s2mm_genlock_pair_frame => s2mm_genlock_pair_frame ,
s2mm_ip2axi_introut => s2mm_ip2axi_introut ,
s2mm_introut => s2mm_introut
);
--*****************************************************************************
--** INTERRUPT CONTROLLER **
--*****************************************************************************
I_AXI_DMA_INTRPT : entity axi_vdma_v6_2_8.axi_vdma_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
m_axi_ch1_aclk => m_axi_mm2s_aclk ,
m_axi_ch1_aresetn => mm2s_prmry_resetn ,
m_axi_ch2_aclk => m_axi_s2mm_aclk ,
m_axi_ch2_aresetn => s2mm_prmry_resetn ,
ch1_irqthresh_decr => mm2s_tstvect_fsync ,
ch1_irqthresh_decr_mask => mm2s_fsize_mismatch_err_flag ,
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl ,
ch1_dlyirq_dsble => mm2s_dlyirq_dsble ,
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) ,
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) ,
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_tstvect_fsync ,
ch1_packet_eof_mask => mm2s_fsize_mismatch_err_flag ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
ch2_irqthresh_decr => s2mm_tstvect_fsync ,
ch2_irqthresh_decr_mask => s2mm_fsize_mismatch_err_flag ,
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl ,
ch2_dlyirq_dsble => s2mm_dlyirq_dsble ,
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) ,
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) ,
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_tstvect_fsync ,
ch2_packet_eof_mask => s2mm_fsize_mismatch_err_flag ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status
);
--*****************************************************************************
--** SCATTER GATHER ENGINE **
--*****************************************************************************
-- If Scatter Gather Engine is included the instantiate axi_sg
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
-------------------------------------------------------------------------------
-- Scatter Gather Engine
-------------------------------------------------------------------------------
I_SG_ENGINE : entity axi_vdma_v6_2_8.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERR ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => EXCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => EXCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => EXCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_AXIS_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_resetn ,
dm_resetn => m_axi_dm_sg_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => open ,
m_axi_sg_awlen => open ,
m_axi_sg_awsize => open ,
m_axi_sg_awburst => open ,
m_axi_sg_awprot => open ,
m_axi_sg_awcache => open ,
m_axi_sg_awvalid => open ,
m_axi_sg_awready => '0' ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => open ,
m_axi_sg_wstrb => open ,
m_axi_sg_wlast => open ,
m_axi_sg_wvalid => open ,
m_axi_sg_wready => '0' ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => "00" ,
m_axi_sg_bvalid => '0' ,
m_axi_sg_bready => open ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_cdc2sg_run_stop ,
ch1_desc_flush => mm2s_cdc2sg_stop ,
ch1_ftch_idle => mm2s_sg2cdc_ftch_idle ,
ch1_ftch_interr_set => mm2s_sg2cdc_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_sg2cdc_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_sg2cdc_ftch_decerr_set ,
ch1_ftch_err_early => open ,
ch1_ftch_stale_desc => open ,
ch1_updt_idle => open ,
ch1_updt_ioc_irq_set => open ,
ch1_updt_interr_set => open ,
ch1_updt_slverr_set => open ,
ch1_updt_decerr_set => open ,
ch1_dma_interr_set => open ,
ch1_dma_slverr_set => open ,
ch1_dma_decerr_set => open ,
ch1_tailpntr_enabled => '1' ,
ch1_taildesc_wren => mm2s_cdc2sg_taildesc_wren ,
ch1_taildesc => mm2s_cdc2sg_taildesc ,
ch1_curdesc => mm2s_cdc2sg_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
ch1_dlyirq_dsble => '0' ,
ch1_irqthresh_rstdsbl => '0' ,
ch1_irqdelay_wren => '0' ,
ch1_irqdelay => ZERO_VALUE(7 downto 0) ,
ch1_irqthresh_wren => '0' ,
ch1_irqthresh => ZERO_VALUE(7 downto 0) ,
ch1_packet_sof => '0' ,
ch1_packet_eof => '0' ,
ch1_ioc_irq_set => open ,
ch1_dly_irq_set => open ,
ch1_irqdelay_status => open ,
ch1_irqthresh_status => open ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axi_mm2s_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => '0' ,
s_axis_ch1_updtptr_tdata => ZERO_VALUE(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0),
s_axis_ch1_updtptr_tvalid => '0' ,
s_axis_ch1_updtptr_tready => open ,
s_axis_ch1_updtptr_tlast => '0' ,
s_axis_ch1_updtsts_tdata => ZERO_VALUE(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0),
s_axis_ch1_updtsts_tvalid => '0' ,
s_axis_ch1_updtsts_tready => open ,
s_axis_ch1_updtsts_tlast => '0' ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_cdc2sg_run_stop ,
ch2_desc_flush => s2mm_cdc2sg_stop ,
ch2_ftch_idle => s2mm_sg2cdc_ftch_idle ,
ch2_ftch_interr_set => s2mm_sg2cdc_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_sg2cdc_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_sg2cdc_ftch_decerr_set ,
ch2_ftch_err_early => open ,
ch2_ftch_stale_desc => open ,
ch2_updt_idle => open ,
ch2_updt_ioc_irq_set => open ,
ch2_updt_interr_set => open ,
ch2_updt_slverr_set => open ,
ch2_updt_decerr_set => open ,
ch2_dma_interr_set => open ,
ch2_dma_slverr_set => open ,
ch2_dma_decerr_set => open ,
ch2_tailpntr_enabled => '1' ,
ch2_taildesc_wren => s2mm_cdc2sg_taildesc_wren ,
ch2_taildesc => s2mm_cdc2sg_taildesc ,
ch2_curdesc => s2mm_cdc2sg_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
ch2_dlyirq_dsble => '0' ,
ch2_irqthresh_rstdsbl => '0' ,
ch2_irqdelay_wren => '0' ,
ch2_irqdelay => ZERO_VALUE(7 downto 0) ,
ch2_irqthresh_wren => '0' ,
ch2_irqthresh => ZERO_VALUE(7 downto 0) ,
ch2_packet_sof => '0' ,
ch2_packet_eof => '0' ,
ch2_ioc_irq_set => open ,
ch2_dly_irq_set => open ,
ch2_irqdelay_status => open ,
ch2_irqthresh_status => open ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axi_s2mm_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => '0' ,
s_axis_ch2_updtptr_tdata => ZERO_VALUE(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0),
s_axis_ch2_updtptr_tvalid => '0' ,
s_axis_ch2_updtptr_tready => open ,
s_axis_ch2_updtptr_tlast => '0' ,
s_axis_ch2_updtsts_tdata => ZERO_VALUE(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0),
s_axis_ch2_updtsts_tvalid => '0' ,
s_axis_ch2_updtsts_tready => open ,
s_axis_ch2_updtsts_tlast => '0' ,
-- Error addresses
ftch_error_addr => sg2cdc_ftch_err_addr ,
ftch_error => sg2cdc_ftch_err ,
updt_error => open ,
updt_error_addr => open
);
--*********************************************************************
--** MM2S Clock Domain To/From Scatter Gather Clock Domain **
--*********************************************************************
MM2S_SG_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_sg_cdc
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
scndry_aclk => m_axi_sg_aclk ,
scndry_resetn => m_axi_sg_resetn ,
-- From Register Module (Primary Clk Domain)
reg2cdc_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
reg2cdc_stop => mm2s_stop ,
reg2cdc_taildesc_wren => mm2s_tailpntr_updated ,
reg2cdc_taildesc => mm2s_taildesc ,
reg2cdc_curdesc => mm2s_curdesc ,
-- To Scatter Gather Engine (Secondary Clk Domain)
cdc2sg_run_stop => mm2s_cdc2sg_run_stop ,
cdc2sg_stop => mm2s_cdc2sg_stop ,
cdc2sg_taildesc_wren => mm2s_cdc2sg_taildesc_wren ,
cdc2sg_taildesc => mm2s_cdc2sg_taildesc ,
cdc2sg_curdesc => mm2s_cdc2sg_curdesc ,
-- From Scatter Gather Engine (Secondary Clk Domain)
sg2cdc_ftch_idle => mm2s_sg2cdc_ftch_idle ,
sg2cdc_ftch_interr_set => mm2s_sg2cdc_ftch_interr_set ,
sg2cdc_ftch_slverr_set => mm2s_sg2cdc_ftch_slverr_set ,
sg2cdc_ftch_decerr_set => mm2s_sg2cdc_ftch_decerr_set ,
sg2cdc_ftch_err_addr => sg2cdc_ftch_err_addr ,
sg2cdc_ftch_err => sg2cdc_ftch_err ,
-- To DMA Controller
cdc2dmac_ftch_idle => mm2s_ftch_idle ,
-- To Register Module
cdc2reg_ftch_interr_set => mm2s_ftch_interr_set ,
cdc2reg_ftch_slverr_set => mm2s_ftch_slverr_set ,
cdc2reg_ftch_decerr_set => mm2s_ftch_decerr_set ,
cdc2reg_ftch_err_addr => mm2s_ftch_err_addr ,
cdc2reg_ftch_err => mm2s_ftch_err
);
--*********************************************************************
--** S2MM Clock Domain To/From Scatter Gather Clock Domain **
--*********************************************************************
S2MM_SG_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_sg_cdc
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
scndry_aclk => m_axi_sg_aclk ,
scndry_resetn => m_axi_sg_resetn ,
-- From Register Module (Primary Clk Domain)
reg2cdc_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
reg2cdc_stop => s2mm_stop ,
reg2cdc_taildesc_wren => s2mm_tailpntr_updated ,
reg2cdc_taildesc => s2mm_taildesc ,
reg2cdc_curdesc => s2mm_curdesc ,
-- To Scatter Gather Engine (Secondary Clk Domain)
cdc2sg_run_stop => s2mm_cdc2sg_run_stop ,
cdc2sg_stop => s2mm_cdc2sg_stop ,
cdc2sg_taildesc_wren => s2mm_cdc2sg_taildesc_wren ,
cdc2sg_taildesc => s2mm_cdc2sg_taildesc ,
cdc2sg_curdesc => s2mm_cdc2sg_curdesc ,
-- From Scatter Gather Engine (Secondary Clk Domain)
sg2cdc_ftch_idle => s2mm_sg2cdc_ftch_idle ,
sg2cdc_ftch_interr_set => s2mm_sg2cdc_ftch_interr_set ,
sg2cdc_ftch_slverr_set => s2mm_sg2cdc_ftch_slverr_set ,
sg2cdc_ftch_decerr_set => s2mm_sg2cdc_ftch_decerr_set ,
sg2cdc_ftch_err_addr => sg2cdc_ftch_err_addr ,
sg2cdc_ftch_err => sg2cdc_ftch_err ,
-- To DMA Controller
cdc2dmac_ftch_idle => s2mm_ftch_idle ,
-- To Register Module
cdc2reg_ftch_interr_set => s2mm_ftch_interr_set ,
cdc2reg_ftch_slverr_set => s2mm_ftch_slverr_set ,
cdc2reg_ftch_decerr_set => s2mm_ftch_decerr_set ,
cdc2reg_ftch_err_addr => s2mm_ftch_err_addr ,
cdc2reg_ftch_err => s2mm_ftch_err
);
end generate GEN_SG_ENGINE;
-- No scatter gather engine therefore tie off unused signals
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
mm2s_ftch_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s2mm_ftch_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
mm2s_ftch_err_addr <= (others => '0');
mm2s_ftch_err <= '0';
s2mm_ftch_err_addr <= (others => '0');
s2mm_ftch_err <= '0';
sg2cdc_ftch_err <= '0';
end generate GEN_NO_SG_ENGINE;
--*****************************************************************************
--** MM2S CHANNEL **
--*****************************************************************************
-- Generate support logic for MM2S
GEN_SPRT_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
GEN_FLUSH_SOF_MM2S : if (ENABLE_FLUSH_ON_MM2S_FSYNC = 1 and MM2S_SOF_ENABLE = 1) generate
begin
--m_axis_mm2s_tvalid_i2 <= m_axis_mm2s_tvalid_i_axis_dw_conv when MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S = '0'
-- else '0';
m_axis_mm2s_tvalid_i2 <= '0' when MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S = '1' or mm2s_fsync_core = '1'
else m_axis_mm2s_tvalid_i_axis_dw_conv;
m_axis_mm2s_tready_i2 <= m_axis_mm2s_tready when MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S = '0'
else '1';
end generate GEN_FLUSH_SOF_MM2S;
GEN_NO_FLUSH_SOF_MM2S : if (ENABLE_FLUSH_ON_MM2S_FSYNC = 0 or MM2S_SOF_ENABLE = 0) generate
begin
m_axis_mm2s_tvalid_i2 <= m_axis_mm2s_tvalid_i_axis_dw_conv;
m_axis_mm2s_tready_i2 <= m_axis_mm2s_tready;
end generate GEN_NO_FLUSH_SOF_MM2S;
GEN_AXIS_MM2S_DWIDTH_CONV : if (C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
constant C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 : integer := C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8;
constant C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 : integer := C_M_AXIS_MM2S_TDATA_WIDTH/8;
signal m_axis_mm2s_dwidth_tuser_i : std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) := (others => '0'); --
signal m_axis_mm2s_dwidth_tuser : std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0) := (others => '0'); --
begin
m_axis_mm2s_dwidth_tuser_i(0) <= m_axis_mm2s_tuser_i(0);
MM2S_TUSER_CNCT : for i in 1 to C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 generate
begin
m_axis_mm2s_dwidth_tuser_i(i) <= '0';
end generate MM2S_TUSER_CNCT;
m_axis_mm2s_tuser(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0) <= m_axis_mm2s_dwidth_tuser(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0);
AXIS_MM2S_DWIDTH_CONVERTER_I: entity axi_vdma_v6_2_8.axi_vdma_mm2s_axis_dwidth_converter
generic map(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
--C_AXIS_SIGNAL_SET => 255 ,
C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 => C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8 ,
C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE ,
ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC,
C_AXIS_TID_WIDTH => 1 ,
C_AXIS_TDEST_WIDTH => 1 ,
C_FAMILY => C_ROOT_FAMILY )
port map(
ACLK => m_axis_mm2s_aclk ,
ARESETN => mm2s_axis_linebuf_reset_out ,
ACLKEN => '1' ,
dm_halt_reg => mm2s_halt_reg ,
stop_reg => mm2s_stop_reg ,
crnt_vsize_d2 => mm2s_crnt_vsize_d2 ,
fsync_out => mm2s_fsync_out_i ,
mm2s_vsize_cntr_clr_flag => mm2s_vsize_cntr_clr_flag ,
dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty ,
all_lines_xfred_s_dwidth => mm2s_all_lines_xfred_s_dwidth ,
S_AXIS_TVALID => m_axis_mm2s_tvalid_i ,
S_AXIS_TREADY => m_axis_mm2s_tready_i ,
S_AXIS_TDATA => m_axis_mm2s_tdata_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED-1 downto 0) ,
--S_AXIS_TSTRB => ZERO_VALUE(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TSTRB => m_axis_mm2s_tkeep_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TKEEP => m_axis_mm2s_tkeep_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
S_AXIS_TLAST => m_axis_mm2s_tlast_i ,
S_AXIS_TID => ZERO_VALUE(0 downto 0) ,
S_AXIS_TDEST => ZERO_VALUE(0 downto 0) ,
S_AXIS_TUSER => m_axis_mm2s_dwidth_tuser_i(C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) ,
M_AXIS_TVALID => m_axis_mm2s_tvalid_i_axis_dw_conv ,
M_AXIS_TREADY => m_axis_mm2s_tready_i2 ,
M_AXIS_TDATA => m_axis_mm2s_tdata(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0) ,
M_AXIS_TSTRB => open ,
M_AXIS_TKEEP => m_axis_mm2s_tkeep(C_M_AXIS_MM2S_TDATA_WIDTH/8-1 downto 0) ,
M_AXIS_TLAST => m_axis_mm2s_tlast_i_axis_dw_conv ,
M_AXIS_TID => open ,
M_AXIS_TDEST => open ,
M_AXIS_TUSER => m_axis_mm2s_dwidth_tuser(C_M_AXIS_MM2S_TDATA_WIDTH_div_by_8-1 downto 0)
) ;
end generate GEN_AXIS_MM2S_DWIDTH_CONV;
GEN_NO_AXIS_MM2S_DWIDTH_CONV : if (C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
m_axis_mm2s_tvalid_i_axis_dw_conv <= m_axis_mm2s_tvalid_i;
m_axis_mm2s_tdata <= m_axis_mm2s_tdata_i;
m_axis_mm2s_tkeep <= m_axis_mm2s_tkeep_i;
m_axis_mm2s_tlast_i_axis_dw_conv <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tuser <= m_axis_mm2s_tuser_i;
m_axis_mm2s_tready_i <= m_axis_mm2s_tready_i2;
mm2s_dwidth_fifo_pipe_empty <= '1';
mm2s_all_lines_xfred_s_dwidth <= '0';
end generate GEN_NO_AXIS_MM2S_DWIDTH_CONV;
--*************************************************************************
--** MM2S AXI4 Clock Domain - (m_axi_mm2s_aclk)
--*************************************************************************
---------------------------------------------------------------------------
-- MM2S Register Module
---------------------------------------------------------------------------
MM2S_REGISTER_MODULE_I : entity axi_vdma_v6_2_8.axi_vdma_reg_module
generic map(
C_TOTAL_NUM_REGISTER => TOTAL_NUM_REGISTER ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_CHANNEL_IS_MM2S => CHANNEL_IS_MM2S ,
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC , -- CR591965
C_ENABLE_VIDPRMTR_READS => C_ENABLE_VIDPRMTR_READS ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_LINEBUFFER_THRESH => C_MM2S_LINEBUFFER_THRESH_INT ,
C_NUM_FSTORES => C_NUM_FSTORES ,
C_NUM_FSTORES_64 => C_NUM_FSTORES_64 ,
C_GENLOCK_MODE => C_MM2S_GENLOCK_MODE ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH --C_M_AXI_MM2S_ADDR_WIDTH_NEW
)
port map(
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
-- Register to AXI Lite Interface
axi2ip_wrce => mm2s_axi2ip_wrce ,
axi2ip_wrdata => mm2s_axi2ip_wrdata ,
axi2ip_rdaddr => mm2s_axi2ip_rdaddr ,
--axi2ip_rden => mm2s_axi2ip_rden ,
axi2ip_rden => '0' ,
ip2axi_rddata => mm2s_ip2axi_rddata ,
--ip2axi_rddata_valid => mm2s_ip2axi_rddata_valid ,
ip2axi_rddata_valid => open ,
ip2axi_frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref ,
ip2axi_frame_store => mm2s_ip2axi_frame_store ,
ip2axi_introut => mm2s_ip2axi_introut ,
-- Soft Reset
soft_reset => mm2s_soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
-- DMA Control / Status Register Signals
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
frame_sync => mm2s_frame_sync ,
fsync_mask => mm2s_mask_fsync_out ,
new_curdesc_wren => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
update_frmstore => '1' , -- Always Update
new_frmstr => mm2s_frame_number ,
tstvect_fsync => mm2s_tstvect_fsync ,
valid_frame_sync => mm2s_valid_frame_sync ,
irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl ,
dlyirq_dsble => mm2s_dlyirq_dsble ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
tailpntr_updated => mm2s_tailpntr_updated ,
-- Error Detection Control
stop => mm2s_stop ,
dma_interr_set => mm2s_dma_interr_set ,
dma_interr_set_minus_frame_errors => mm2s_dma_interr_set_minus_frame_errors ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
fsize_mismatch_err => mm2s_fsize_mismatch_err ,
lsize_mismatch_err => mm2s_lsize_mismatch_err ,
lsize_more_mismatch_err => mm2s_lsize_more_mismatch_err ,
s2mm_fsize_more_or_sof_late => '0' ,
-- VDMA Base Registers
reg_index => mm2s_reg_index ,
dmacr => mm2s_dmacr ,
dmasr => mm2s_dmasr ,
curdesc => mm2s_curdesc ,
taildesc => mm2s_taildesc ,
num_frame_store => mm2s_num_frame_store ,
linebuf_threshold => mm2s_linebuf_threshold ,
-- Register Direct Support
regdir_idle => mm2s_regdir_idle ,
prmtr_updt_complete => mm2s_prmtr_updt_complete ,
reg_module_vsize => mm2s_reg_module_vsize ,
reg_module_hsize => mm2s_reg_module_hsize ,
reg_module_stride => mm2s_reg_module_stride ,
reg_module_frmdly => mm2s_reg_module_frmdly ,
reg_module_strt_addr => mm2s_reg_module_strt_addr ,
-- Fetch/Update error addresses
frmstr_err_addr => mm2s_frame_number ,
ftch_err_addr => mm2s_ftch_err_addr
);
ADDR32: if C_M_AXI_MM2S_ADDR_WIDTH_NEW = 32 generate
begin
---------------------------------------------------------------------------
-- MM2S DMA Controller
---------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_vdma_v6_2_8.axi_vdma_mngr
generic map(
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SF => DM_MM2S_INCLUDE_SF ,
C_USE_FSYNC => C_USE_MM2S_FSYNC , -- CR582182
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC , -- CR591965
C_NUM_FSTORES => C_NUM_FSTORES ,
C_GENLOCK_MODE => C_MM2S_GENLOCK_MODE ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
C_GENLOCK_NUM_MASTERS => C_MM2S_GENLOCK_NUM_MASTERS ,
--C_GENLOCK_REPEAT_EN => C_MM2S_GENLOCK_REPEAT_EN , -- CR591965
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_NEW ,
C_DM_STATUS_WIDTH => MM2S_DM_STATUS_WIDTH , -- CR608521
C_EXTEND_DM_COMMAND => MM2S_DM_CMD_NOT_EXTENDED ,
C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE ,
C_S2MM_SOF_ENABLE => 0 ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => 0 ,
C_SELECT_XPM => C_SELECT_XPM,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- Secondary Clock and Reset
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
soft_reset => mm2s_soft_reset ,
scndry_aclk => '0' ,
scndry_resetn => '1' ,
-- MM2S Control and Status
run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
dmacr_repeat_en => mm2s_dmacr(DMACR_REPEAT_EN_BIT) ,
dmasr_halt => mm2s_dmasr(DMASR_HALTED_BIT) ,
sync_enable => mm2s_dmacr(DMACR_SYNCEN_BIT) ,
regdir_idle => mm2s_regdir_idle ,
ftch_idle => mm2s_ftch_idle ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
stop => mm2s_stop ,
s2mm_dmasr_lsize_less_err => '0' ,
s2mm_fsize_more_or_sof_late => '0' ,
capture_hsize_at_uf_err => open ,
all_idle => mm2s_all_idle ,
cmdsts_idle => mm2s_cmdsts_idle ,
ftchcmdsts_idle => mm2s_ftchcmdsts_idle ,
s2mm_fsync_out_m => '0' ,
frame_sync => mm2s_frame_sync ,
mm2s_fsync_out_m => mm2s_fsync_out_m , -- CR616211
update_frmstore => open , -- Not Needed for MM2S channel
frmstr_err_addr => open , -- Not Needed for MM2S channel
frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref ,
frame_ptr_in => mm2s_s_frame_ptr_in ,
frame_ptr_out => mm2s_m_frame_ptr_out ,
internal_frame_ptr_in => s2mm_to_mm2s_frame_ptr_in ,
valid_frame_sync => mm2s_valid_frame_sync ,
valid_frame_sync_cmb => mm2s_valid_frame_sync_cmb ,
valid_video_prmtrs => mm2s_valid_video_prmtrs ,
parameter_update => mm2s_parameter_update ,
circular_prk_mode => mm2s_dmacr(DMACR_CRCLPRK_BIT) ,
mstr_pntr_ref => mm2s_dmacr(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) ,
genlock_select => mm2s_dmacr(DMACR_GENLOCK_SEL_BIT),
line_buffer_empty => mm2s_allbuffer_empty ,
dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty_m ,
crnt_vsize => mm2s_crnt_vsize , -- CR616211
num_frame_store => mm2s_num_frame_store ,
all_lines_xfred => mm2s_all_lines_xfred , -- CR616211
all_lasts_rcvd => all_lasts_rcvd , --
fsize_mismatch_err_flag => mm2s_fsize_mismatch_err_flag , -- CR591965
s2mm_fsize_mismatch_err_s => open , -- Not Needed for MM2S channel
drop_fsync_d_pulse_gen_fsize_less_err => '0' ,
s2mm_strm_all_lines_rcvd => '0' , -- : out std_logic;
s2mm_fsync_core => '0' ,
mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s , -- CR591965
mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m , -- CR591965
fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965
lsize_mismatch_err => mm2s_lsize_mismatch_err , -- CR591965
lsize_more_mismatch_err => mm2s_lsize_more_mismatch_err , -- CR591965
-- Register Direct Support
prmtr_updt_complete => mm2s_prmtr_updt_complete ,
reg_module_vsize => mm2s_reg_module_vsize ,
reg_module_hsize => mm2s_reg_module_hsize ,
reg_module_stride => mm2s_reg_module_stride ,
reg_module_frmdly => mm2s_reg_module_frmdly ,
reg_module_strt_addr => mm2s_reg_module_strt_addr ,
-- Fsync signals and Genlock for test vector
tstvect_err => mm2s_tstvect_err ,
tstvect_fsync => mm2s_tstvect_fsync ,
tstvect_frame => mm2s_tstvect_frame ,
tstvect_frm_ptr_out => mm2s_tstvect_frm_ptr_out ,
mstrfrm_tstsync_out => mm2s_mstrfrm_tstsync ,
-- AXI Stream Timing
packet_sof => '1' , -- NOT Used for MM2S
-- Primary DMA Errors
dma_interr_set => mm2s_dma_interr_set ,
dma_interr_set_minus_frame_errors => mm2s_dma_interr_set_minus_frame_errors ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ftch_tlast => m_axis_mm2s_ftch_tlast ,
-- Currently Being Processed Descriptor/Frame
frame_number => mm2s_frame_number ,
chnl_current_frame => mm2s_chnl_current_frame ,
genlock_pair_frame => mm2s_genlock_pair_frame ,
new_curdesc => mm2s_new_curdesc ,
new_curdesc_wren => mm2s_new_curdesc_wren ,
tailpntr_updated => mm2s_tailpntr_updated ,
-- User Command Interface Ports (AXI Stream)
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_sts_tkeep => m_axis_mm2s_sts_tkeep ,
err => mm2s_err ,
ftch_err => mm2s_ftch_err
);
end generate ADDR32;
ADDR64: if C_M_AXI_MM2S_ADDR_WIDTH_NEW > 32 generate
begin
FSTORES64 : for i in 0 to C_NUM_FSTORES_64-1 generate
mm2s_reg_module_strt_addr_64 (i) <= mm2s_reg_module_strt_addr (i*2+1) & mm2s_reg_module_strt_addr (i*2);
end generate FSTORES64;
---------------------------------------------------------------------------
-- MM2S DMA Controller
---------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_vdma_v6_2_8.axi_vdma_mngr_64
generic map(
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SF => DM_MM2S_INCLUDE_SF ,
C_USE_FSYNC => C_USE_MM2S_FSYNC , -- CR582182
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC , -- CR591965
C_NUM_FSTORES => C_NUM_FSTORES_64 ,
C_GENLOCK_MODE => C_MM2S_GENLOCK_MODE ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
C_GENLOCK_NUM_MASTERS => C_MM2S_GENLOCK_NUM_MASTERS ,
--C_GENLOCK_REPEAT_EN => C_MM2S_GENLOCK_REPEAT_EN , -- CR591965
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_NEW ,
C_DM_STATUS_WIDTH => MM2S_DM_STATUS_WIDTH , -- CR608521
C_EXTEND_DM_COMMAND => MM2S_DM_CMD_NOT_EXTENDED ,
C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE ,
C_S2MM_SOF_ENABLE => 0 ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => 0 ,
C_SELECT_XPM => C_SELECT_XPM,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- Secondary Clock and Reset
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
soft_reset => mm2s_soft_reset ,
scndry_aclk => '0' ,
scndry_resetn => '1' ,
-- MM2S Control and Status
run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
dmacr_repeat_en => mm2s_dmacr(DMACR_REPEAT_EN_BIT) ,
dmasr_halt => mm2s_dmasr(DMASR_HALTED_BIT) ,
sync_enable => mm2s_dmacr(DMACR_SYNCEN_BIT) ,
regdir_idle => mm2s_regdir_idle ,
ftch_idle => mm2s_ftch_idle ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
stop => mm2s_stop ,
s2mm_dmasr_lsize_less_err => '0' ,
s2mm_fsize_more_or_sof_late => '0' ,
capture_hsize_at_uf_err => open ,
all_idle => mm2s_all_idle ,
cmdsts_idle => mm2s_cmdsts_idle ,
ftchcmdsts_idle => mm2s_ftchcmdsts_idle ,
s2mm_fsync_out_m => '0' ,
frame_sync => mm2s_frame_sync ,
mm2s_fsync_out_m => mm2s_fsync_out_m , -- CR616211
update_frmstore => open , -- Not Needed for MM2S channel
frmstr_err_addr => open , -- Not Needed for MM2S channel
frame_ptr_ref => mm2s_ip2axi_frame_ptr_ref ,
frame_ptr_in => mm2s_s_frame_ptr_in ,
frame_ptr_out => mm2s_m_frame_ptr_out ,
internal_frame_ptr_in => s2mm_to_mm2s_frame_ptr_in ,
valid_frame_sync => mm2s_valid_frame_sync ,
valid_frame_sync_cmb => mm2s_valid_frame_sync_cmb ,
valid_video_prmtrs => mm2s_valid_video_prmtrs ,
parameter_update => mm2s_parameter_update ,
circular_prk_mode => mm2s_dmacr(DMACR_CRCLPRK_BIT) ,
mstr_pntr_ref => mm2s_dmacr(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) ,
genlock_select => mm2s_dmacr(DMACR_GENLOCK_SEL_BIT),
line_buffer_empty => mm2s_allbuffer_empty ,
dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty_m ,
crnt_vsize => mm2s_crnt_vsize , -- CR616211
num_frame_store => mm2s_num_frame_store ,
all_lines_xfred => mm2s_all_lines_xfred , -- CR616211
all_lasts_rcvd => all_lasts_rcvd , --
fsize_mismatch_err_flag => mm2s_fsize_mismatch_err_flag , -- CR591965
s2mm_fsize_mismatch_err_s => open , -- Not Needed for MM2S channel
drop_fsync_d_pulse_gen_fsize_less_err => '0' ,
s2mm_strm_all_lines_rcvd => '0' , -- : out std_logic;
s2mm_fsync_core => '0' ,
mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s , -- CR591965
mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m , -- CR591965
fsize_mismatch_err => mm2s_fsize_mismatch_err , -- CR591965
lsize_mismatch_err => mm2s_lsize_mismatch_err , -- CR591965
lsize_more_mismatch_err => mm2s_lsize_more_mismatch_err , -- CR591965
-- Register Direct Support
prmtr_updt_complete => mm2s_prmtr_updt_complete ,
reg_module_vsize => mm2s_reg_module_vsize ,
reg_module_hsize => mm2s_reg_module_hsize ,
reg_module_stride => mm2s_reg_module_stride ,
reg_module_frmdly => mm2s_reg_module_frmdly ,
reg_module_strt_addr => mm2s_reg_module_strt_addr_64 ,
-- Fsync signals and Genlock for test vector
tstvect_err => mm2s_tstvect_err ,
tstvect_fsync => mm2s_tstvect_fsync ,
tstvect_frame => mm2s_tstvect_frame ,
tstvect_frm_ptr_out => mm2s_tstvect_frm_ptr_out ,
mstrfrm_tstsync_out => mm2s_mstrfrm_tstsync ,
-- AXI Stream Timing
packet_sof => '1' , -- NOT Used for MM2S
-- Primary DMA Errors
dma_interr_set => mm2s_dma_interr_set ,
dma_interr_set_minus_frame_errors => mm2s_dma_interr_set_minus_frame_errors ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ftch_tlast => m_axis_mm2s_ftch_tlast ,
-- Currently Being Processed Descriptor/Frame
frame_number => mm2s_frame_number ,
chnl_current_frame => mm2s_chnl_current_frame ,
genlock_pair_frame => mm2s_genlock_pair_frame ,
new_curdesc => mm2s_new_curdesc ,
new_curdesc_wren => mm2s_new_curdesc_wren ,
tailpntr_updated => mm2s_tailpntr_updated ,
-- User Command Interface Ports (AXI Stream)
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_sts_tkeep => m_axis_mm2s_sts_tkeep ,
err => mm2s_err ,
ftch_err => mm2s_ftch_err
);
end generate ADDR64;
---------------------------------------------------------------------------
-- MM2S Frame sync generator
---------------------------------------------------------------------------
MM2S_FSYNC_I : entity axi_vdma_v6_2_8.axi_vdma_fsync_gen
generic map(
C_USE_FSYNC => C_USE_MM2S_FSYNC ,
ENABLE_FLUSH_ON_S2MM_FSYNC => 0 ,
ENABLE_FLUSH_ON_MM2S_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC ,
C_INCLUDE_S2MM => 0 ,
C_INCLUDE_MM2S => 1 ,
C_SOF_ENABLE => MM2S_SOF_ENABLE -- Always disabled
)
port map(
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
-- Frame Count Enable Support
valid_frame_sync_cmb => mm2s_valid_frame_sync_cmb ,
valid_video_prmtrs => mm2s_valid_video_prmtrs ,
frmcnt_ioc => mm2s_ioc_irq_set ,
dmacr_frmcnt_enbl => mm2s_dmacr(DMACR_FRMCNTEN_BIT) ,
dmasr_frmcnt_status => mm2s_irqthresh_status ,
mask_fsync_out => mm2s_mask_fsync_out ,
-- VDMA process status
run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
all_idle => mm2s_all_idle ,
parameter_update => mm2s_parameter_update ,
-- VDMA Frame Sync Sources
fsync => mm2s_cdc2dmac_fsync ,
tuser_fsync => '0' , -- Not used by MM2S
othrchnl_fsync => s2mm_to_mm2s_fsync ,
fsync_src_select => mm2s_dmacr(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) ,
-- VDMA frame sync output to core
frame_sync => mm2s_frame_sync ,
-- VDMA frame sync output to ports
frame_sync_out => mm2s_dmac2cdc_fsync_out ,
prmtr_update => mm2s_dmac2cdc_prmtr_update
);
-- Clock Domain Crossing between m_axi_mm2s_aclk and m_axis_mm2s_aclk
MM2S_VID_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_vid_cdc
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_GENLOCK_MSTR_PTR_DWIDTH => NUM_FRM_STORE_WIDTH ,
C_GENLOCK_SLVE_PTR_DWIDTH => MM2S_GENLOCK_SLVE_PTR_DWIDTH ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => m_axi_mm2s_aclk ,
prmry_resetn => mm2s_prmry_resetn ,
scndry_aclk => m_axis_mm2s_aclk ,
scndry_resetn => mm2s_axis_resetn ,
-- Genlock internal bus cdc
othrchnl_aclk => m_axi_s2mm_aclk ,
othrchnl_resetn => s2mm_prmry_resetn ,
othrchnl2cdc_frame_ptr_out => s2mm_frame_ptr_out_i ,
cdc2othrchnl_frame_ptr_in => s2mm_to_mm2s_frame_ptr_in ,
cdc2othrchnl_fsync => mm2s_to_s2mm_fsync ,
-- GenLock Clock Domain Crossing
dmac2cdc_frame_ptr_out => mm2s_m_frame_ptr_out ,
cdc2top_frame_ptr_out => mm2s_frame_ptr_out_i ,
top2cdc_frame_ptr_in => mm2s_frame_ptr_in ,
cdc2dmac_frame_ptr_in => mm2s_s_frame_ptr_in ,
dmac2cdc_mstrfrm_tstsync => mm2s_mstrfrm_tstsync ,
cdc2dmac_mstrfrm_tstsync => mm2s_mstrfrm_tstsync_out ,
-- SOF Detection Domain Crossing
vid2cdc_packet_sof => mm2s_vid2cdc_packet_sof ,
cdc2dmac_packet_sof => mm2s_packet_sof ,
-- Frame Sync Generation Domain Crossing
vid2cdc_fsync => mm2s_fsync_core ,
cdc2dmac_fsync => mm2s_cdc2dmac_fsync ,
dmac2cdc_fsync_out => mm2s_dmac2cdc_fsync_out ,
dmac2cdc_prmtr_update => mm2s_dmac2cdc_prmtr_update ,
cdc2vid_fsync_out => mm2s_fsync_out_i ,
cdc2vid_prmtr_update => mm2s_prmtr_update_i
);
mm2s_fsync_out_sig <= mm2s_fsync_out_i;
-- Start of Frame Detection - used for interrupt coalescing
MM2S_SOF_I : entity axi_vdma_v6_2_8.axi_vdma_sof_gen
port map(
scndry_aclk => m_axis_mm2s_aclk ,
scndry_resetn => mm2s_axis_resetn ,
axis_tready => m_axis_mm2s_tready_i2 ,
---axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tvalid => m_axis_mm2s_tvalid_i2 ,
fsync => mm2s_fsync_out_i , -- CR622884
packet_sof => mm2s_vid2cdc_packet_sof
);
---------------------------------------------------------------------------
-- Primary MM2S Line Buffer
---------------------------------------------------------------------------
MM2S_LINEBUFFER_I : entity axi_vdma_v6_2_8.axi_vdma_mm2s_linebuf
generic map(
C_DATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
--C_INCLUDE_MM2S_SF => C_INCLUDE_MM2S_SF ,
C_INCLUDE_MM2S_SF => 0 ,
C_INCLUDE_MM2S_DRE => C_MM2S_ENABLE_TKEEP ,
C_MM2S_SOF_ENABLE => MM2S_SOF_ENABLE ,
C_M_AXIS_MM2S_TUSER_BITS => C_M_AXIS_MM2S_TUSER_BITS ,
C_TOPLVL_LINEBUFFER_DEPTH => C_MM2S_LINEBUFFER_DEPTH , -- CR625142
ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_MM2S_FSYNC,
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_LINEBUFFER_DEPTH => MM2S_LINEBUFFER_DEPTH ,
C_LINEBUFFER_AE_THRESH => C_MM2S_LINEBUFFER_THRESH_INT ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-------------------------------------------------------------------
-- AXI Scatter Gather Interface
-------------------------------------------------------------------
-- MM2S AXIS Datamover side
s_axis_aclk => m_axi_mm2s_aclk ,
s_axis_resetn => mm2s_prmry_resetn ,
-- MM2S AXIS Out side
m_axis_aclk => m_axis_mm2s_aclk ,
m_axis_resetn => mm2s_axis_resetn ,
mm2s_axis_linebuf_reset_out => mm2s_axis_linebuf_reset_out ,
run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
s2mm_axis_resetn => s2mm_axis_resetn ,
s_axis_s2mm_aclk => s_axis_s2mm_aclk ,
mm2s_fsync => mm2s_fsync_fe ,
s2mm_fsync => s2mm_fsync_fe ,
mm2s_fsync_core => mm2s_fsync_core ,
mm2s_vsize_cntr_clr_flag => mm2s_vsize_cntr_clr_flag ,
mm2s_fsize_mismatch_err_flag => mm2s_fsize_mismatch_err_flag ,
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S => MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S ,
mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m ,
mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s ,
fsync_src_select => mm2s_dmacr(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) ,
-- Graceful shut down control
cmdsts_idle => mm2s_cmdsts_idle ,
dm_halt => mm2s_halt ,
dm_halt_reg_out => mm2s_halt_reg ,
stop => mm2s_stop , -- CR623291
stop_reg_out => mm2s_stop_reg , -- CR623291
-- Vertical Line Count control
crnt_vsize => mm2s_crnt_vsize , -- CR616211
crnt_vsize_d2_out => mm2s_crnt_vsize_d2 , -- CR616211
fsync_out => mm2s_fsync_out_i , -- CR616211
fsync_out_m => mm2s_fsync_out_m , -- CR616211
frame_sync => mm2s_frame_sync , -- CR616211
-- Threshold
linebuf_threshold => mm2s_linebuf_threshold ,
-- Stream In (Datamover to Linebuffer)
s_axis_tdata => dm2linebuf_mm2s_tdata ,
s_axis_tkeep => dm2linebuf_mm2s_tkeep ,
s_axis_tlast => dm2linebuf_mm2s_tlast ,
s_axis_tvalid => dm2linebuf_mm2s_tvalid ,
s_axis_tready => linebuf2dm_mm2s_tready ,
-- Stream Out (Linebuffer to AXIS Out)
m_axis_tdata => m_axis_mm2s_tdata_i ,
m_axis_tkeep => m_axis_mm2s_tkeep_i ,
m_axis_tlast => m_axis_mm2s_tlast_i ,
m_axis_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_tready => m_axis_mm2s_tready_i ,
m_axis_tuser => m_axis_mm2s_tuser_i ,
-- Fifo Status Flags
dwidth_fifo_pipe_empty => mm2s_dwidth_fifo_pipe_empty ,
dwidth_fifo_pipe_empty_m => mm2s_dwidth_fifo_pipe_empty_m ,
mm2s_fifo_pipe_empty => mm2s_allbuffer_empty ,
mm2s_fifo_empty => mm2s_buffer_empty_i ,
mm2s_fifo_almost_empty => mm2s_buffer_almost_empty_i ,
mm2s_all_lines_xfred_s_dwidth => mm2s_all_lines_xfred_s_dwidth ,
mm2s_all_lines_xfred_s => mm2s_all_lines_xfred_s ,
mm2s_all_lines_xfred => mm2s_all_lines_xfred -- CR616211
);
end generate GEN_SPRT_FOR_MM2S;
-- Do not generate support logic for MM2S
GEN_NO_SPRT_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
-- Register Module Tie-Offs
mm2s_ip2axi_rddata <= (others => '0');
--mm2s_ip2axi_rddata_valid <= '0';
mm2s_ip2axi_frame_ptr_ref <= (others => '0');
mm2s_ip2axi_frame_store <= (others => '0');
mm2s_ip2axi_introut <= '0';
mm2s_soft_reset <= '0';
mm2s_irqthresh_rstdsbl <= '0';
mm2s_dlyirq_dsble <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_dmacr <= (others => '0');
mm2s_dmasr <= (others => '0');
mm2s_curdesc <= (others => '0');
mm2s_taildesc <= (others => '0');
--internal to mm2s generate (dont really need to tie off)
mm2s_num_frame_store <= (others => '0');
mm2s_linebuf_threshold <= (others => '0');
mm2s_regdir_idle <= '0';
mm2s_prmtr_updt_complete <= '0';
mm2s_reg_module_vsize <= (others => '0');
mm2s_reg_module_hsize <= (others => '0');
mm2s_reg_module_stride <= (others => '0');
mm2s_reg_module_frmdly <= (others => '0');
-- Must zero each element of an array of vectors to zero
-- all vectors.
GEN_MM2S_ZERO_STRT : for i in 0 to C_NUM_FSTORES-1 generate
begin
mm2s_reg_module_strt_addr(i) <= (others => '0');
end generate GEN_MM2S_ZERO_STRT;
-- Line Buffer Tie-Offs
linebuf2dm_mm2s_tready <= '0';
m_axis_mm2s_tdata <= (others => '0');
m_axis_mm2s_tdata_i <= (others => '0');
m_axis_mm2s_tkeep <= (others => '0');
m_axis_mm2s_tkeep_i <= (others => '0');
m_axis_mm2s_tlast_i <= '0';
m_axis_mm2s_tlast_i_axis_dw_conv <= '0';
m_axis_mm2s_tuser <= (others => '0');
m_axis_mm2s_tuser_i <= (others => '0');
m_axis_mm2s_tvalid_i <= '0';
m_axis_mm2s_tvalid_i2 <= '0';
m_axis_mm2s_tvalid_i_axis_dw_conv <= '0';
mm2s_allbuffer_empty <= '0';
mm2s_dwidth_fifo_pipe_empty <= '0';
mm2s_buffer_empty_i <= '0';
mm2s_buffer_almost_empty_i <= '0';
mm2s_all_lines_xfred <= '0';
-- SOF generator
mm2s_packet_sof <= '0';
-- DMA Controller
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
mm2s_frame_number <= (others => '0');
mm2s_chnl_current_frame <= (others => '0');
mm2s_genlock_pair_frame <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_stop <= '0';
mm2s_stop_reg <= '0';
mm2s_all_idle <= '1';
mm2s_cmdsts_idle <= '1';
mm2s_ftchcmdsts_idle <= '1';
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
m_axis_mm2s_sts_tready <= '0';
mm2s_m_frame_ptr_out <= (others => '0');
mm2s_frame_ptr_out_i <= (others => '0');
s2mm_to_mm2s_frame_ptr_in <= (others => '0');
mm2s_valid_frame_sync <= '0';
mm2s_valid_frame_sync_cmb <= '0';
mm2s_valid_video_prmtrs <= '0';
mm2s_parameter_update <= '0';
mm2s_tstvect_err <= '0';
mm2s_tstvect_fsync <= '0';
mm2s_tstvect_frame <= (others => '0');
mm2s_dma_interr_set <= '0';
mm2s_dma_interr_set_minus_frame_errors <= '0';
mm2s_dma_slverr_set <= '0';
mm2s_dma_decerr_set <= '0';
mm2s_crnt_vsize <= (others => '0');
mm2s_crnt_vsize_d2 <= (others => '0');
mm2s_fsize_mismatch_err <= '0';
mm2s_lsize_mismatch_err <= '0';
mm2s_lsize_more_mismatch_err <= '0';
-- Frame Sync generator
mm2s_frame_sync <= '0';
mm2s_fsync_out_sig <= '0';
mm2s_prmtr_update_i <= '0';
mm2s_mask_fsync_out <= '0';
mm2s_mstrfrm_tstsync <= '0';
mm2s_mstrfrm_tstsync_out <= '0';
mm2s_tstvect_frm_ptr_out <= (others => '0');
mm2s_to_s2mm_fsync <= '0';
end generate GEN_NO_SPRT_FOR_MM2S;
--*****************************************************************************
--** S2MM CHANNEL **
--*****************************************************************************
-- Generate support logic for S2MM
GEN_SPRT_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
signal no_fsync_before_vsize_sel_00_01 : std_logic := '0';
begin
------------------------------------------------------------------------------------------------------------------------------------------------------
s2mm_axis_linebuf_reset_out_inv <= not s2mm_axis_linebuf_reset_out;
GEN_S2MM_DRE_ON_SKID : if C_S2MM_ENABLE_TKEEP = 1 generate
begin
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
I_S2MM_SKID_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
)
port map(
-- System Ports
ACLK => s_axis_s2mm_aclk ,
ARST => s2mm_axis_linebuf_reset_out_inv ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_tvalid ,
S_READY => s_axis_s2mm_tready ,
S_Data => s_axis_s2mm_tdata ,
S_STRB => s_axis_s2mm_tkeep ,
S_Last => s_axis_s2mm_tlast ,
S_User => s_axis_s2mm_tuser ,
-- Master Side (Stream Data Output)
M_VALID => s_axis_s2mm_tvalid_signal ,
M_READY => s_axis_s2mm_tready_signal ,
M_Data => s_axis_s2mm_tdata_signal ,
M_STRB => s_axis_s2mm_tkeep_signal ,
M_Last => s_axis_s2mm_tlast_signal ,
M_User => s_axis_s2mm_tuser_signal
);
end generate GEN_S2MM_DRE_ON_SKID;
GEN_S2MM_DRE_OFF_SKID : if C_S2MM_ENABLE_TKEEP = 0 generate
begin
--*********************************************************--
--** S2MM SLAVE SKID BUFFER **--
--*********************************************************--
I_S2MM_SKID_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_TUSER_WIDTH => C_S_AXIS_S2MM_TUSER_BITS
)
port map(
-- System Ports
ACLK => s_axis_s2mm_aclk ,
ARST => s2mm_axis_linebuf_reset_out_inv ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => s_axis_s2mm_tvalid ,
S_READY => s_axis_s2mm_tready ,
S_Data => s_axis_s2mm_tdata ,
--S_STRB => s_axis_s2mm_tkeep ,
S_STRB => (others => '1') ,
S_Last => s_axis_s2mm_tlast ,
S_User => s_axis_s2mm_tuser ,
-- Master Side (Stream Data Output)
M_VALID => s_axis_s2mm_tvalid_signal ,
M_READY => s_axis_s2mm_tready_signal ,
M_Data => s_axis_s2mm_tdata_signal ,
M_STRB => s_axis_s2mm_tkeep_signal ,
M_Last => s_axis_s2mm_tlast_signal ,
M_User => s_axis_s2mm_tuser_signal
);
end generate GEN_S2MM_DRE_OFF_SKID;
GEN_FLUSH_SOF_TREADY : if ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and S2MM_SOF_ENABLE = 1 generate
signal s2mm_fsize_less_err_flag_10 : std_logic := '0';
signal s2mm_fsize_less_err_flag_00_01 : std_logic := '0';
signal s_axis_s2mm_tuser_d1 : std_logic := '0';
signal s2mm_tuser_to_fsync_out : std_logic := '0';
signal d_tready_sof_late : std_logic := '0';
signal d_tready_sof_late_cmb : std_logic := '0';
signal s2mm_sof_late_err : std_logic := '0';
signal s2mm_prmtr_or_tail_ptr_updt_complete : std_logic := '0';
signal s2mm_prmtr_updt_complete_s : std_logic := '0';
signal s2mm_dmasr_halted_s : std_logic := '0';
signal d_tready_before_fsync_clr_flag1 : std_logic := '0';
signal d_tready_before_fsync : std_logic := '0';
signal d_tready_before_fsync_cmb : std_logic := '0';
signal d_tready_after_prmtr_updt : std_logic := '0';
signal d_tready_after_prmtr_updt_clrd_till_reset : std_logic := '0';
signal d_tready_after_prmtr_updt_clrd : std_logic := '0';
signal d_tready_sof_late_prmtr_updt : std_logic := '0';
signal d_tready_after_prmtr_updt_clrd_cmb : std_logic := '0';
signal s2mm_sof_late_err_prmtr_updt : std_logic := '0';
signal s2mm_fsync_src_select_s_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal s2mm_dummy_tready_fsync_src_sel_00_or_01 : std_logic := '0';
signal s2mm_dummy_tready_fsync_src_sel_10 : std_logic := '0';
signal d_tready_before_fsync_clr_flag1_sel_00_01 : std_logic := '0';
signal d_tready_before_fsync_clrd_sel_00_01 : std_logic := '0';
signal d_tready_before_fsync_clr_sel_00_01 : std_logic := '0';
signal d_tready_before_fsync_sel_00_01 : std_logic := '0';
signal d_tready_before_fsync_cmb_sel_00_01 : std_logic := '0';
signal d_tready_after_vcount_sel_00_01 : std_logic := '0';
signal after_vcount_flag_sel_00_01 : std_logic := '0';
signal d_tready_after_fsize_less_err_flag_00_01 : std_logic := '0';
signal d_tready_after_fsize_less_err_00_01 : std_logic := '0';
signal s2mm_fsize_less_err_internal_tvalid_gating_10 : std_logic := '0';
signal s2mm_fsize_less_err_internal_tvalid_gating_00_01 : std_logic := '0';
begin
no_fsync_before_vsize_sel_00_01 <= d_tready_before_fsync_clr_flag1_sel_00_01;
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid_signal and s2mm_chnl_ready ;
s_axis_s2mm_tready_signal <= (s_axis_s2mm_tready_i_axis_dw_conv and s2mm_chnl_ready) or s2mm_dummy_tready;
GEN_C_USE_S2MM_FSYNC_1 : if C_USE_S2MM_FSYNC = 1 generate
begin
s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_00_or_01;
s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_00_01;
end generate GEN_C_USE_S2MM_FSYNC_1;
GEN_C_USE_S2MM_FSYNC_2 : if C_USE_S2MM_FSYNC = 2 generate
begin
s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_10;
s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_10;
end generate GEN_C_USE_S2MM_FSYNC_2;
---- FSYNC_SEL_TREADY_S2MM_S : process(s2mm_fsync_src_select_s_d1,
---- s2mm_dummy_tready,
---- s2mm_dummy_tready_fsync_src_sel_00_or_01,
---- s2mm_fsize_less_err_internal_tvalid_gating_10,
---- s2mm_fsize_less_err_internal_tvalid_gating_00_01,
---- s2mm_fsize_less_err_internal_tvalid_gating,
---- s2mm_dummy_tready_fsync_src_sel_10)
---- begin
---- case s2mm_fsync_src_select_s_d1 is
----
---- when "00" => -- primary fsync (default)
---- s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_00_or_01;
---- s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_00_01;
---- when "01" => -- other channel fsync
---- s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_00_or_01;
---- s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_00_01;
---- when "10" => -- s2mm_tuser_fsync_top_d1 fsync
---- s2mm_dummy_tready <= s2mm_dummy_tready_fsync_src_sel_10;
---- s2mm_fsize_less_err_internal_tvalid_gating <= s2mm_fsize_less_err_internal_tvalid_gating_10;
---- when others =>
---- s2mm_dummy_tready <= '0';
---- s2mm_fsize_less_err_internal_tvalid_gating <= '0';
---- end case;
---- end process FSYNC_SEL_TREADY_S2MM_S;
----
----
----
---- D1_S2MM_FSYNC_SRC_SEL_STRM : process(s_axis_s2mm_aclk)
---- begin
---- if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
---- if(s2mm_axis_resetn = '0')then
---- s2mm_fsync_src_select_s_d1 <= (others => '0');
---- else
---- s2mm_fsync_src_select_s_d1 <= s2mm_fsync_src_select_s;
---- end if;
---- end if;
---- end process D1_S2MM_FSYNC_SRC_SEL_STRM;
----
--------------------------------------------------TUSER Start-------------------------------------------------------------------------------------------------------------------------
s2mm_dummy_tready_fsync_src_sel_10 <= d_tready_sof_late_cmb or d_tready_before_fsync_cmb ;
d_tready_sof_late_cmb <= d_tready_sof_late when s2mm_tuser_fsync_top = '0' and s2mm_tuser_to_fsync_out = '0' and s2mm_chnl_ready = '0' else '0';
TUSER_TO_FSYNC_OUT_FLAG : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_fsync_out_i = '1' )then
s2mm_tuser_to_fsync_out <= '0';
elsif(s2mm_tuser_fsync_top = '1' and d_tready_before_fsync_clr_flag1 = '0')then
s2mm_tuser_to_fsync_out <= '1';
end if;
end if;
end process TUSER_TO_FSYNC_OUT_FLAG;
s2mm_fsize_less_err_internal_tvalid_gating_10 <= '1' when s2mm_fsize_less_err_flag_10 = '1' and s2mm_tuser_fsync_top = '0'
else '0';
FSIZE_LESS_ERR_FLAG_10 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_tuser_fsync_top = '1')then
s2mm_fsize_less_err_flag_10 <= '0';
elsif(s2mm_fsize_mismatch_err_s = '1')then
s2mm_fsize_less_err_flag_10 <= '1';
end if;
end if;
end process FSIZE_LESS_ERR_FLAG_10;
TOP_TUSER_RE_PROCESS : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0')then
s_axis_s2mm_tuser_d1 <= '0';
else
s_axis_s2mm_tuser_d1 <= s_axis_s2mm_tuser_signal(0) and s_axis_s2mm_tvalid_signal;
end if;
end if;
end process TOP_TUSER_RE_PROCESS;
s2mm_tuser_fsync_top <= s_axis_s2mm_tuser_signal(0) and s_axis_s2mm_tvalid_signal and (not s_axis_s2mm_tuser_d1);
SOF_LATE_ERR_PULSE_PROCESS : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_sof_late_err = '1' or s2mm_chnl_ready = '1' or d_tready_before_fsync_clr_flag1 = '1')then
s2mm_sof_late_err <= '0';
d_tready_sof_late <= '0';
elsif((s2mm_chnl_ready = '0' or s2mm_fsize_less_err_internal_tvalid_gating_10 = '1') and s_axis_s2mm_tvalid_signal = '1' and s_axis_s2mm_tuser_signal(0) = '0' ) then
s2mm_sof_late_err <= '1';
d_tready_sof_late <= '1';
end if;
end if;
end process SOF_LATE_ERR_PULSE_PROCESS;
--------------------------------------------------------------------------------------------------------
d_tready_before_fsync_cmb <= d_tready_before_fsync and d_tready_before_fsync_clr_flag1;
GEN_D_TREADY_BEFORE_FSYNC : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(d_tready_before_fsync_clr_flag1 = '0')then
d_tready_before_fsync <= '0';
elsif(s2mm_axis_resetn = '1' or s2mm_dmasr_halted_s = '1')then
d_tready_before_fsync <= '1';
end if;
end if;
end process GEN_D_TREADY_BEFORE_FSYNC;
VALID_PRM_UPDT_FLAG_10 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_dmasr_halted_s = '1')then
d_tready_before_fsync_clr_flag1 <= '1';
elsif(s2mm_prmtr_updt_complete_s = '1')then
d_tready_before_fsync_clr_flag1 <= '0';
end if;
end if;
end process VALID_PRM_UPDT_FLAG_10;
--------------------------------------------------TUSER End-------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------External Fsync Start-----------------------------------------------------------------------------------------------------------------------
s2mm_dummy_tready_fsync_src_sel_00_or_01 <= d_tready_after_fsize_less_err_00_01 or d_tready_after_vcount_sel_00_01 or d_tready_before_fsync_cmb_sel_00_01;
--------------------------------------------------------------------------------------------------------------
d_tready_after_fsize_less_err_00_01 <= '1' when d_tready_after_fsize_less_err_flag_00_01 = '1' and s2mm_fsync_core = '0' and hold_dummy_tready_low2 = '0'
else '0';
TREADY_AFTER_FSIZE_LESS_ERR_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_fsync_core = '1' or hold_dummy_tready_low2 = '1')then
d_tready_after_fsize_less_err_flag_00_01 <= '0';
elsif(s2mm_fsize_mismatch_err_s = '1')then
d_tready_after_fsize_less_err_flag_00_01 <= '1';
end if;
end if;
end process TREADY_AFTER_FSIZE_LESS_ERR_FLAG_00_01;
--------------------------------------------------------------------------------------------------------------
d_tready_after_vcount_sel_00_01 <= '1' when s2mm_fsync_core = '0' and after_vcount_flag_sel_00_01 = '1' and hold_dummy_tready_low = '0'
else '0';
REG_S2MM_FSYNC_TO_FSYNC_OUT_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_fsync_core = '1' or hold_dummy_tready_low = '1')then
after_vcount_flag_sel_00_01 <= '0';
elsif(s2mm_all_vount_rcvd = '1')then
after_vcount_flag_sel_00_01 <= '1';
end if;
end if;
end process REG_S2MM_FSYNC_TO_FSYNC_OUT_FLAG_00_01;
--------------------------------------------------------------------------------------------------------------
d_tready_before_fsync_cmb_sel_00_01 <= d_tready_before_fsync_sel_00_01 and d_tready_before_fsync_clr_sel_00_01;
GEN_D_TREADY_BEFORE_FSYNC_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_fsync_core = '1'and d_tready_before_fsync_clr_flag1_sel_00_01 = '1')then
d_tready_before_fsync_sel_00_01 <= '0';
elsif(s2mm_axis_resetn = '1')then
d_tready_before_fsync_sel_00_01 <= '1';
end if;
end if;
end process GEN_D_TREADY_BEFORE_FSYNC_00_01;
d_tready_before_fsync_clr_sel_00_01 <= '0' when d_tready_before_fsync_clr_flag1_sel_00_01 = '1' and s2mm_fsync_core = '1'
else d_tready_before_fsync_clrd_sel_00_01;
REG_INITIAL_FRM_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_dmasr_halted_s = '1')then
d_tready_before_fsync_clrd_sel_00_01 <= '1';
elsif(s2mm_fsync_core = '1'and d_tready_before_fsync_clr_flag1_sel_00_01 = '1')then
d_tready_before_fsync_clrd_sel_00_01 <= '0';
end if;
end if;
end process REG_INITIAL_FRM_FLAG_00_01;
VALID_PRM_UPDT_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_dmasr_halted_s = '1')then
d_tready_before_fsync_clr_flag1_sel_00_01 <= '0';
elsif(s2mm_prmtr_updt_complete_s = '1')then
d_tready_before_fsync_clr_flag1_sel_00_01 <= '1';
end if;
end if;
end process VALID_PRM_UPDT_FLAG_00_01;
-----------------------------------------------------------------------------------
s2mm_fsize_less_err_internal_tvalid_gating_00_01 <= '1' when s2mm_fsize_less_err_flag_00_01 = '1' and s2mm_fsync_core = '0'
else '0';
FSIZE_LESS_ERR_FLAG_00_01 : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
if(s2mm_axis_resetn = '0' or s2mm_fsync_core = '1')then
s2mm_fsize_less_err_flag_00_01 <= '0';
elsif(s2mm_fsize_mismatch_err_s = '1')then
s2mm_fsize_less_err_flag_00_01 <= '1';
end if;
end if;
end process FSIZE_LESS_ERR_FLAG_00_01;
--------------------------------------------------External Fsync End-------------------------------------------------------------------------------------------------------------------------
SG_INCLUDED : if C_INCLUDE_SG = 1 generate
s2mm_prmtr_or_tail_ptr_updt_complete <= s2mm_tailpntr_updated;
end generate SG_INCLUDED;
SG_NOT_INCLUDED : if C_INCLUDE_SG = 0 generate
s2mm_prmtr_or_tail_ptr_updt_complete <= s2mm_prmtr_updt_complete;
end generate SG_NOT_INCLUDED;
GEN_FOR_ASYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
---- S2MM_PRM_UPDT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axi_s2mm_aclk ,
---- prmry_resetn => s2mm_prmry_resetn ,
---- scndry_aclk => s_axis_s2mm_aclk ,
---- scndry_resetn => s2mm_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_prmtr_or_tail_ptr_updt_complete ,
---- scndry_out => s2mm_prmtr_updt_complete_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
S2MM_PRM_UPDT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axi_s2mm_aclk,
prmry_resetn => s2mm_prmry_resetn,
prmry_in => s2mm_prmtr_or_tail_ptr_updt_complete,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_s2mm_aclk,
scndry_resetn => s2mm_axis_resetn,
scndry_out => s2mm_prmtr_updt_complete_s,
scndry_vect_out => open
);
---- S2MM_HALTED_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axi_s2mm_aclk ,
---- prmry_resetn => s2mm_prmry_resetn ,
---- scndry_aclk => s_axis_s2mm_aclk ,
---- scndry_resetn => s2mm_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_dmasr(DMASR_HALTED_BIT) ,
---- scndry_out => s2mm_dmasr_halted_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
S2MM_HALTED_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axi_s2mm_aclk,
prmry_resetn => s2mm_prmry_resetn,
prmry_in => s2mm_dmasr(DMASR_HALTED_BIT),
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_s2mm_aclk,
scndry_resetn => s2mm_axis_resetn,
scndry_out => s2mm_dmasr_halted_s,
scndry_vect_out => open
);
---- SOF_LATE_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axi_s2mm_aclk ,
---- prmry_resetn => s2mm_prmry_resetn ,
---- scndry_aclk => s_axis_s2mm_aclk ,
---- scndry_resetn => s2mm_axis_resetn ,
---- scndry_in => s2mm_fsize_more_or_sof_late_s , -- Not Used
---- prmry_out => s2mm_fsize_more_or_sof_late , -- Not Used
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
SOF_LATE_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsize_more_or_sof_late_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_s2mm_aclk,
scndry_resetn => s2mm_prmry_resetn,
scndry_out => s2mm_fsize_more_or_sof_late,
scndry_vect_out => open
);
end generate GEN_FOR_ASYNC_FLUSH_SOF;
GEN_FOR_SYNC_FLUSH_SOF : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
s2mm_dmasr_halted_s <= s2mm_dmasr(DMASR_HALTED_BIT);
s2mm_prmtr_updt_complete_s <= s2mm_prmtr_or_tail_ptr_updt_complete;
s2mm_fsize_more_or_sof_late <= s2mm_fsize_more_or_sof_late_s;
end generate GEN_FOR_SYNC_FLUSH_SOF;
---------------------------------------------------------------------------
end generate GEN_FLUSH_SOF_TREADY;
----------------------------------------------------------------------------------------------------------------------------------------------------------
GEN_FLUSH_NO_SOF_TREADY : if ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and S2MM_SOF_ENABLE = 0 generate
begin
--s_axis_s2mm_tdata_signal <= s_axis_s2mm_tdata;
--s_axis_s2mm_tkeep_signal <= s_axis_s2mm_tkeep;
--s_axis_s2mm_tuser_signal <= s_axis_s2mm_tuser;
--s_axis_s2mm_tlast_signal <= s_axis_s2mm_tlast;
--s_axis_s2mm_tvalid_signal <= s_axis_s2mm_tvalid;
--s_axis_s2mm_tready <= s_axis_s2mm_tready_signal;
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid_signal;
s_axis_s2mm_tready_signal <= s_axis_s2mm_tready_i_axis_dw_conv;
s2mm_dummy_tready <= '0';
end generate GEN_FLUSH_NO_SOF_TREADY;
GEN_NO_FLUSH_TREADY : if ENABLE_FLUSH_ON_S2MM_FSYNC = 0 generate
begin
--s_axis_s2mm_tdata_signal <= s_axis_s2mm_tdata;
--s_axis_s2mm_tkeep_signal <= s_axis_s2mm_tkeep;
--s_axis_s2mm_tuser_signal <= s_axis_s2mm_tuser;
--s_axis_s2mm_tlast_signal <= s_axis_s2mm_tlast;
--s_axis_s2mm_tvalid_signal <= s_axis_s2mm_tvalid;
--s_axis_s2mm_tready <= s_axis_s2mm_tready_signal;
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid_signal;
s_axis_s2mm_tready_signal <= s_axis_s2mm_tready_i_axis_dw_conv;
s2mm_dummy_tready <= '0';
end generate GEN_NO_FLUSH_TREADY;
GEN_AXIS_S2MM_DWIDTH_CONV : if C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED /= C_S_AXIS_S2MM_TDATA_WIDTH generate
constant C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 : integer := C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8;
constant C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 : integer := C_S_AXIS_S2MM_TDATA_WIDTH/8;
signal s_axis_s2mm_dwidth_tuser_i : std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0) := (others => '0'); --
signal s_axis_s2mm_dwidth_tuser : std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0) := (others => '0'); --
begin
S2MM_TUSER_CNCT : for i in 0 to C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 generate
begin
s_axis_s2mm_dwidth_tuser(i) <= s_axis_s2mm_tuser_signal(0);
end generate S2MM_TUSER_CNCT;
s_axis_s2mm_tuser_i(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0) <= s_axis_s2mm_dwidth_tuser_i(C_S_AXIS_S2MM_TUSER_BITS-1 downto 0);
AXIS_S2MM_DWIDTH_CONVERTER_I: entity axi_vdma_v6_2_8.axi_vdma_s2mm_axis_dwidth_converter
generic map(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED ,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
--C_AXIS_SIGNAL_SET => 255 ,
C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 => C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8 ,
C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8 ,
C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE ,
ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC,
C_AXIS_TID_WIDTH => 1 ,
C_AXIS_TDEST_WIDTH => 1 ,
C_FAMILY => C_ROOT_FAMILY )
port map(
ACLK => s_axis_s2mm_aclk ,
ARESETN => s2mm_axis_linebuf_reset_out ,
--ARESETN => s2mm_axis_resetn ,
ACLKEN => '1' ,
s2mm_fsize_less_err_internal_tvalid_gating => s2mm_fsize_less_err_internal_tvalid_gating , -- : in std_logic ;
fsync_out => s2mm_fsync_out_i , -- : in std_logic ;
crnt_vsize_d2 => s2mm_crnt_vsize_d2 , -- : in std_logic_vector(VSIZE_DWIDTH-1 downto 0) ;
chnl_ready_dwidth => s2mm_chnl_ready , -- : out std_logic;
strm_not_finished_dwidth => s2mm_strm_not_finished , -- : out std_logic;
strm_all_lines_rcvd_dwidth => s2mm_strm_all_lines_rcvd , -- : out std_logic;
all_vount_rcvd_dwidth => s2mm_all_vount_rcvd , -- : out std_logic;
S_AXIS_TVALID => s_axis_s2mm_tvalid_int ,
S_AXIS_TREADY => s_axis_s2mm_tready_i_axis_dw_conv ,
S_AXIS_TDATA => s_axis_s2mm_tdata_signal(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) ,
--S_AXIS_TSTRB => ZERO_VALUE(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TSTRB => s_axis_s2mm_tkeep_signal(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TKEEP => s_axis_s2mm_tkeep_signal(C_S_AXIS_S2MM_TDATA_WIDTH/8-1 downto 0) ,
S_AXIS_TLAST => s_axis_s2mm_tlast_signal ,
S_AXIS_TID => ZERO_VALUE(0 downto 0) ,
S_AXIS_TDEST => ZERO_VALUE(0 downto 0) ,
S_AXIS_TUSER => s_axis_s2mm_dwidth_tuser(C_S_AXIS_S2MM_TDATA_WIDTH_div_by_8-1 downto 0) ,
M_AXIS_TVALID => s_axis_s2mm_tvalid_i ,
M_AXIS_TREADY => s_axis_s2mm_tready_i ,
M_AXIS_TDATA => s_axis_s2mm_tdata_i(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED-1 downto 0) ,
M_AXIS_TSTRB => open ,
M_AXIS_TKEEP => s_axis_s2mm_tkeep_i(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED/8-1 downto 0) ,
M_AXIS_TLAST => s_axis_s2mm_tlast_i ,
M_AXIS_TID => open ,
M_AXIS_TDEST => open ,
M_AXIS_TUSER => s_axis_s2mm_dwidth_tuser_i(C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED_div_by_8-1 downto 0)
) ;
end generate GEN_AXIS_S2MM_DWIDTH_CONV;
GEN_NO_AXIS_S2MM_DWIDTH_CONV_NO_FLUSH_SOF : if ((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED = C_S_AXIS_S2MM_TDATA_WIDTH) and (ENABLE_FLUSH_ON_S2MM_FSYNC = 0 or S2MM_SOF_ENABLE = 0) )generate
begin
s_axis_s2mm_tvalid_i <= s_axis_s2mm_tvalid_int;
s_axis_s2mm_tdata_i <= s_axis_s2mm_tdata_signal;
s_axis_s2mm_tkeep_i <= s_axis_s2mm_tkeep_signal;
s_axis_s2mm_tlast_i <= s_axis_s2mm_tlast_signal;
s_axis_s2mm_tuser_i <= s_axis_s2mm_tuser_signal;
s_axis_s2mm_tready_i_axis_dw_conv <= s_axis_s2mm_tready_i;
s2mm_chnl_ready <= '0' ;
s2mm_strm_not_finished <= '0' ;
s2mm_strm_all_lines_rcvd <= '0' ;
s2mm_all_vount_rcvd <= '0' ;
end generate GEN_NO_AXIS_S2MM_DWIDTH_CONV_NO_FLUSH_SOF;
GEN_NO_AXIS_S2MM_DWIDTH_CONV : if ((C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED = C_S_AXIS_S2MM_TDATA_WIDTH) and (ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and S2MM_SOF_ENABLE = 1) ) generate
constant ZERO_VALUE : std_logic_vector(255 downto 0)
:= (others => '0');
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
signal chnl_ready_no_dwidth : std_logic := '0';
signal strm_not_finished_no_dwidth : std_logic := '0';
signal strm_all_lines_rcvd_no_dwidth : std_logic := '0';
signal decr_vcount_no_dwidth : std_logic := '0';
signal vsize_counter_no_dwidth : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal all_vount_rcvd_no_dwidth : std_logic := '0';
begin
s_axis_s2mm_tvalid_i <= s_axis_s2mm_tvalid_int;
s_axis_s2mm_tdata_i <= s_axis_s2mm_tdata_signal;
s_axis_s2mm_tkeep_i <= s_axis_s2mm_tkeep_signal;
s_axis_s2mm_tlast_i <= s_axis_s2mm_tlast_signal;
s_axis_s2mm_tuser_i <= s_axis_s2mm_tuser_signal;
s_axis_s2mm_tready_i_axis_dw_conv <= s_axis_s2mm_tready_i;
-- Decrement vertical count with each accept tlast
decr_vcount_no_dwidth <= '1' when s_axis_s2mm_tlast_signal = '1'
and s_axis_s2mm_tvalid_int = '1'
and s_axis_s2mm_tready_i_axis_dw_conv = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
NO_DWIDTH_VERT_COUNTER : process(s_axis_s2mm_aclk)
begin
if(s_axis_s2mm_aclk'EVENT and s_axis_s2mm_aclk = '1')then
--if(s2mm_axis_linebuf_reset_out = '0' and s2mm_fsync_out_i = '0')then
--if((s2mm_axis_linebuf_reset_out = '0' and s2mm_fsync_out_i = '0') or s2mm_fsize_less_err_flag = '1')then
if((s2mm_axis_linebuf_reset_out = '0' and s2mm_fsync_out_i = '0') or s2mm_fsize_less_err_internal_tvalid_gating = '1')then
vsize_counter_no_dwidth <= (others => '0');
chnl_ready_no_dwidth <= '0';
strm_not_finished_no_dwidth <= '0';
strm_all_lines_rcvd_no_dwidth <= '1';
all_vount_rcvd_no_dwidth <= '0';
elsif(s2mm_fsync_out_i = '1')then
vsize_counter_no_dwidth <= s2mm_crnt_vsize_d2;
chnl_ready_no_dwidth <= '1';
strm_not_finished_no_dwidth <= '1';
strm_all_lines_rcvd_no_dwidth <= '0';
all_vount_rcvd_no_dwidth <= '0';
elsif(decr_vcount_no_dwidth = '1' and vsize_counter_no_dwidth = VSIZE_ONE_VALUE)then
vsize_counter_no_dwidth <= (others => '0');
chnl_ready_no_dwidth <= '0';
strm_not_finished_no_dwidth <= '0';
strm_all_lines_rcvd_no_dwidth <= '1';
all_vount_rcvd_no_dwidth <= '1';
elsif(decr_vcount_no_dwidth = '1' and vsize_counter_no_dwidth /= VSIZE_ZERO_VALUE)then
vsize_counter_no_dwidth <= std_logic_vector(unsigned(vsize_counter_no_dwidth) - 1);
chnl_ready_no_dwidth <= '1';
strm_not_finished_no_dwidth <= '1';
strm_all_lines_rcvd_no_dwidth <= '0';
all_vount_rcvd_no_dwidth <= '0';
else
all_vount_rcvd_no_dwidth <= '0';
end if;
end if;
end process NO_DWIDTH_VERT_COUNTER;
s2mm_chnl_ready <= chnl_ready_no_dwidth;
s2mm_strm_not_finished <= strm_not_finished_no_dwidth;
s2mm_strm_all_lines_rcvd <= strm_all_lines_rcvd_no_dwidth;
s2mm_all_vount_rcvd <= all_vount_rcvd_no_dwidth;
end generate GEN_NO_AXIS_S2MM_DWIDTH_CONV;
---------------------------------------------------------------------------
-- S2MM Register Module
---------------------------------------------------------------------------
S2MM_REGISTER_MODULE_I : entity axi_vdma_v6_2_8.axi_vdma_reg_module
generic map(
C_TOTAL_NUM_REGISTER => TOTAL_NUM_REGISTER ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_CHANNEL_IS_MM2S => CHANNEL_IS_S2MM ,
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC , -- CR591965
C_ENABLE_VIDPRMTR_READS => C_ENABLE_VIDPRMTR_READS ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
C_NUM_FSTORES => C_NUM_FSTORES ,
C_NUM_FSTORES_64 => C_NUM_FSTORES_64 ,
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_LINEBUFFER_THRESH => C_S2MM_LINEBUFFER_THRESH_INT ,
C_GENLOCK_MODE => C_S2MM_GENLOCK_MODE ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH --C_M_AXI_S2MM_ADDR_WIDTH_NEW
)
port map(
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
-- Register to AXI Lite Interface
axi2ip_wrce => s2mm_axi2ip_wrce ,
axi2ip_wrdata => s2mm_axi2ip_wrdata ,
axi2ip_rdaddr => s2mm_axi2ip_rdaddr ,
--axi2ip_rden => s2mm_axi2ip_rden ,
axi2ip_rden => '0' ,
ip2axi_rddata => s2mm_ip2axi_rddata ,
--ip2axi_rddata_valid => s2mm_ip2axi_rddata_valid ,
ip2axi_rddata_valid => open ,
ip2axi_frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref ,
ip2axi_frame_store => s2mm_ip2axi_frame_store ,
ip2axi_introut => s2mm_ip2axi_introut ,
-- Soft Reset
soft_reset => s2mm_soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
-- DMA Control / Status Register Signals
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
frame_sync => s2mm_frame_sync ,
fsync_mask => s2mm_mask_fsync_out ,
new_curdesc_wren => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
update_frmstore => s2mm_update_frmstore ,
new_frmstr => s2mm_frame_number ,
tstvect_fsync => s2mm_tstvect_fsync ,
valid_frame_sync => s2mm_valid_frame_sync ,
irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl ,
dlyirq_dsble => s2mm_dlyirq_dsble ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
tailpntr_updated => s2mm_tailpntr_updated ,
-- Error Detection Control
stop => s2mm_stop ,
dma_interr_set => s2mm_dma_interr_set ,
dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
fsize_mismatch_err => s2mm_fsize_mismatch_err ,
lsize_mismatch_err => s2mm_lsize_mismatch_err ,
lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err ,
s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late ,
-- VDMA Base Registers
reg_index => s2mm_reg_index ,
dmacr => s2mm_dmacr ,
dmasr => s2mm_dmasr ,
curdesc => s2mm_curdesc ,
taildesc => s2mm_taildesc ,
num_frame_store => s2mm_num_frame_store ,
linebuf_threshold => s2mm_linebuf_threshold ,
-- Register Direct Support
regdir_idle => s2mm_regdir_idle ,
prmtr_updt_complete => s2mm_prmtr_updt_complete ,
reg_module_vsize => s2mm_reg_module_vsize ,
reg_module_hsize => s2mm_reg_module_hsize ,
reg_module_stride => s2mm_reg_module_stride ,
reg_module_frmdly => s2mm_reg_module_frmdly ,
reg_module_strt_addr => s2mm_reg_module_strt_addr ,
-- Fetch/Update error addresses
frmstr_err_addr => s2mm_frmstr_err_addr ,
ftch_err_addr => s2mm_ftch_err_addr
);
S2MMADDR32: if C_M_AXI_S2MM_ADDR_WIDTH_NEW = 32 generate
begin
---------------------------------------------------------------------------
-- S2MM DMA Controller
---------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_vdma_v6_2_8.axi_vdma_mngr
generic map(
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_SF => DM_S2MM_INCLUDE_SF ,
C_USE_FSYNC => C_USE_S2MM_FSYNC_01 , -- CR582182
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC , -- CR591965
C_NUM_FSTORES => C_NUM_FSTORES ,
C_GENLOCK_MODE => C_S2MM_GENLOCK_MODE ,
C_GENLOCK_NUM_MASTERS => C_S2MM_GENLOCK_NUM_MASTERS ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
--C_GENLOCK_REPEAT_EN => C_S2MM_GENLOCK_REPEAT_EN , -- CR591965
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800
C_SELECT_XPM => C_SELECT_XPM,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_NEW ,
C_DM_STATUS_WIDTH => S2MM_DM_STATUS_WIDTH , -- CR608521
C_EXTEND_DM_COMMAND => S2MM_DM_CMD_EXTENDED ,
C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE,
C_MM2S_SOF_ENABLE => 0 ,
C_INCLUDE_MM2S => 0 ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- Secondary Clock and Reset
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
soft_reset => s2mm_soft_reset ,
scndry_aclk => s_axis_s2mm_aclk ,
scndry_resetn => s2mm_axis_resetn ,
-- MM2S Control and Status
run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
dmacr_repeat_en => s2mm_dmacr(DMACR_REPEAT_EN_BIT) ,
dmasr_halt => s2mm_dmasr(DMASR_HALTED_BIT) ,
sync_enable => s2mm_dmacr(DMACR_SYNCEN_BIT) ,
regdir_idle => s2mm_regdir_idle ,
ftch_idle => s2mm_ftch_idle ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
stop => s2mm_stop ,
s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late ,
s2mm_dmasr_lsize_less_err => s2mm_dmasr(DMASR_LSIZEERR_BIT) ,
all_idle => s2mm_all_idle ,
cmdsts_idle => s2mm_cmdsts_idle ,
ftchcmdsts_idle => s2mm_ftchcmdsts_idle ,
s2mm_fsync_out_m => s2mm_fsync_out_m_i ,
mm2s_fsync_out_m => '0' , -- CR616211
frame_sync => s2mm_frame_sync ,
update_frmstore => s2mm_update_frmstore , -- CR582182
frmstr_err_addr => s2mm_frmstr_err_addr , -- CR582182
frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref ,
frame_ptr_in => s2mm_s_frame_ptr_in ,
frame_ptr_out => s2mm_m_frame_ptr_out ,
internal_frame_ptr_in => mm2s_to_s2mm_frame_ptr_in ,
valid_frame_sync => s2mm_valid_frame_sync ,
valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb ,
valid_video_prmtrs => s2mm_valid_video_prmtrs ,
parameter_update => s2mm_parameter_update ,
circular_prk_mode => s2mm_dmacr(DMACR_CRCLPRK_BIT) ,
mstr_pntr_ref => s2mm_dmacr(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) ,
genlock_select => s2mm_dmacr(DMACR_GENLOCK_SEL_BIT),
line_buffer_empty => '1' , -- NOT Used by S2MM therefore tie off
dwidth_fifo_pipe_empty => '1' , -- NOT Used by S2MM therefore tie off
crnt_vsize => s2mm_crnt_vsize , -- CR575884
num_frame_store => s2mm_num_frame_store ,
all_lines_xfred => s2mm_all_lines_xfred , -- CR591965
all_lasts_rcvd => all_lasts_rcvd ,
mm2s_fsize_mismatch_err_m => '0' , -- Not Needed for MM2S channel
mm2s_fsize_mismatch_err_s => '0' , -- Not Needed for MM2S channel
s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s , -- Not Needed for MM2S channel
drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err ,
s2mm_strm_all_lines_rcvd => s2mm_strm_all_lines_rcvd , -- : out std_logic;
s2mm_fsync_core => s2mm_fsync_core ,
fsize_mismatch_err_flag => s2mm_fsize_mismatch_err_flag , -- CR591965
fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965
lsize_mismatch_err => s2mm_lsize_mismatch_err , -- CR591965
lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err , -- CR591965
capture_hsize_at_uf_err => s2mm_capture_hsize_at_uf_err_sig ,
-- Register Direct Support
prmtr_updt_complete => s2mm_prmtr_updt_complete ,
reg_module_vsize => s2mm_reg_module_vsize ,
reg_module_hsize => s2mm_reg_module_hsize ,
reg_module_stride => s2mm_reg_module_stride ,
reg_module_frmdly => s2mm_reg_module_frmdly ,
reg_module_strt_addr => s2mm_reg_module_strt_addr ,
-- Test vector signals
tstvect_err => s2mm_tstvect_err ,
tstvect_fsync => s2mm_tstvect_fsync ,
tstvect_frame => s2mm_tstvect_frame ,
tstvect_frm_ptr_out => s2mm_tstvect_frm_ptr_out ,
mstrfrm_tstsync_out => s2mm_mstrfrm_tstsync ,
-- AXI Stream Timing
packet_sof => s2mm_packet_sof ,
-- Primary DMA Errors
dma_interr_set => s2mm_dma_interr_set ,
dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ftch_tlast => m_axis_s2mm_ftch_tlast ,
-- Currently Being Processed Descriptor/Frame
frame_number => s2mm_frame_number ,
chnl_current_frame => s2mm_chnl_current_frame ,
genlock_pair_frame => s2mm_genlock_pair_frame ,
new_curdesc => s2mm_new_curdesc ,
new_curdesc_wren => s2mm_new_curdesc_wren ,
tailpntr_updated => s2mm_tailpntr_updated ,
-- User Command Interface Ports (AXI Stream)
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_sts_tkeep => m_axis_s2mm_sts_tkeep ,
err => s2mm_err ,
ftch_err => s2mm_ftch_err
);
end generate S2MMADDR32;
S2MMADDR64: if C_M_AXI_S2MM_ADDR_WIDTH_NEW > 32 generate
begin
S2MM_FSTORES64 : for i in 0 to C_NUM_FSTORES_64-1 generate
s2mm_reg_module_strt_addr_64 (i) <= s2mm_reg_module_strt_addr (i*2+1) & s2mm_reg_module_strt_addr (i*2);
end generate S2MM_FSTORES64;
---------------------------------------------------------------------------
-- S2MM DMA Controller
---------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_vdma_v6_2_8.axi_vdma_mngr_64
generic map(
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_SF => DM_S2MM_INCLUDE_SF ,
C_USE_FSYNC => C_USE_S2MM_FSYNC_01 , -- CR582182
C_ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC , -- CR591965
C_NUM_FSTORES => C_NUM_FSTORES_64 ,
C_GENLOCK_MODE => C_S2MM_GENLOCK_MODE ,
C_GENLOCK_NUM_MASTERS => C_S2MM_GENLOCK_NUM_MASTERS ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
--C_GENLOCK_REPEAT_EN => C_S2MM_GENLOCK_REPEAT_EN , -- CR591965
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG , -- CR581800
C_SELECT_XPM => C_SELECT_XPM,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_NEW ,
C_DM_STATUS_WIDTH => S2MM_DM_STATUS_WIDTH , -- CR608521
C_EXTEND_DM_COMMAND => S2MM_DM_CMD_EXTENDED ,
C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE,
C_MM2S_SOF_ENABLE => 0 ,
C_INCLUDE_MM2S => 0 ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- Secondary Clock and Reset
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
soft_reset => s2mm_soft_reset ,
scndry_aclk => s_axis_s2mm_aclk ,
scndry_resetn => s2mm_axis_resetn ,
-- MM2S Control and Status
run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
dmacr_repeat_en => s2mm_dmacr(DMACR_REPEAT_EN_BIT) ,
dmasr_halt => s2mm_dmasr(DMASR_HALTED_BIT) ,
sync_enable => s2mm_dmacr(DMACR_SYNCEN_BIT) ,
regdir_idle => s2mm_regdir_idle ,
ftch_idle => s2mm_ftch_idle ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
stop => s2mm_stop ,
s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late ,
s2mm_dmasr_lsize_less_err => s2mm_dmasr(DMASR_LSIZEERR_BIT) ,
all_idle => s2mm_all_idle ,
cmdsts_idle => s2mm_cmdsts_idle ,
ftchcmdsts_idle => s2mm_ftchcmdsts_idle ,
s2mm_fsync_out_m => s2mm_fsync_out_m_i ,
mm2s_fsync_out_m => '0' , -- CR616211
frame_sync => s2mm_frame_sync ,
update_frmstore => s2mm_update_frmstore , -- CR582182
frmstr_err_addr => s2mm_frmstr_err_addr , -- CR582182
frame_ptr_ref => s2mm_ip2axi_frame_ptr_ref ,
frame_ptr_in => s2mm_s_frame_ptr_in ,
frame_ptr_out => s2mm_m_frame_ptr_out ,
internal_frame_ptr_in => mm2s_to_s2mm_frame_ptr_in ,
valid_frame_sync => s2mm_valid_frame_sync ,
valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb ,
valid_video_prmtrs => s2mm_valid_video_prmtrs ,
parameter_update => s2mm_parameter_update ,
circular_prk_mode => s2mm_dmacr(DMACR_CRCLPRK_BIT) ,
mstr_pntr_ref => s2mm_dmacr(DMACR_PNTR_NUM_MSB
downto DMACR_PNTR_NUM_LSB) ,
genlock_select => s2mm_dmacr(DMACR_GENLOCK_SEL_BIT),
line_buffer_empty => '1' , -- NOT Used by S2MM therefore tie off
dwidth_fifo_pipe_empty => '1' , -- NOT Used by S2MM therefore tie off
crnt_vsize => s2mm_crnt_vsize , -- CR575884
num_frame_store => s2mm_num_frame_store ,
all_lines_xfred => s2mm_all_lines_xfred , -- CR591965
all_lasts_rcvd => all_lasts_rcvd ,
mm2s_fsize_mismatch_err_m => '0' , -- Not Needed for MM2S channel
mm2s_fsize_mismatch_err_s => '0' , -- Not Needed for MM2S channel
s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s , -- Not Needed for MM2S channel
drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err ,
s2mm_strm_all_lines_rcvd => s2mm_strm_all_lines_rcvd , -- : out std_logic;
s2mm_fsync_core => s2mm_fsync_core ,
fsize_mismatch_err_flag => s2mm_fsize_mismatch_err_flag , -- CR591965
fsize_mismatch_err => s2mm_fsize_mismatch_err , -- CR591965
lsize_mismatch_err => s2mm_lsize_mismatch_err , -- CR591965
lsize_more_mismatch_err => s2mm_lsize_more_mismatch_err , -- CR591965
capture_hsize_at_uf_err => s2mm_capture_hsize_at_uf_err_sig ,
-- Register Direct Support
prmtr_updt_complete => s2mm_prmtr_updt_complete ,
reg_module_vsize => s2mm_reg_module_vsize ,
reg_module_hsize => s2mm_reg_module_hsize ,
reg_module_stride => s2mm_reg_module_stride ,
reg_module_frmdly => s2mm_reg_module_frmdly ,
reg_module_strt_addr => s2mm_reg_module_strt_addr_64 ,
-- Test vector signals
tstvect_err => s2mm_tstvect_err ,
tstvect_fsync => s2mm_tstvect_fsync ,
tstvect_frame => s2mm_tstvect_frame ,
tstvect_frm_ptr_out => s2mm_tstvect_frm_ptr_out ,
mstrfrm_tstsync_out => s2mm_mstrfrm_tstsync ,
-- AXI Stream Timing
packet_sof => s2mm_packet_sof ,
-- Primary DMA Errors
dma_interr_set => s2mm_dma_interr_set ,
dma_interr_set_minus_frame_errors => s2mm_dma_interr_set_minus_frame_errors ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ftch_tlast => m_axis_s2mm_ftch_tlast ,
-- Currently Being Processed Descriptor/Frame
frame_number => s2mm_frame_number ,
chnl_current_frame => s2mm_chnl_current_frame ,
genlock_pair_frame => s2mm_genlock_pair_frame ,
new_curdesc => s2mm_new_curdesc ,
new_curdesc_wren => s2mm_new_curdesc_wren ,
tailpntr_updated => s2mm_tailpntr_updated ,
-- User Command Interface Ports (AXI Stream)
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_sts_tkeep => m_axis_s2mm_sts_tkeep ,
err => s2mm_err ,
ftch_err => s2mm_ftch_err
);
end generate S2MMADDR64;
---------------------------------------------------------------------------
-- MM2S Frame sync generator
---------------------------------------------------------------------------
S2MM_FSYNC_I : entity axi_vdma_v6_2_8.axi_vdma_fsync_gen
generic map(
C_USE_FSYNC => C_USE_S2MM_FSYNC_01 ,
ENABLE_FLUSH_ON_S2MM_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC ,
ENABLE_FLUSH_ON_MM2S_FSYNC => 0 ,
C_INCLUDE_S2MM => 1 ,
C_INCLUDE_MM2S => 0 ,
C_SOF_ENABLE => S2MM_SOF_ENABLE
)
port map(
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
-- Frame Count Enable Support
valid_frame_sync_cmb => s2mm_valid_frame_sync_cmb ,
valid_video_prmtrs => s2mm_valid_video_prmtrs ,
frmcnt_ioc => s2mm_ioc_irq_set ,
dmacr_frmcnt_enbl => s2mm_dmacr(DMACR_FRMCNTEN_BIT) ,
dmasr_frmcnt_status => s2mm_irqthresh_status ,
mask_fsync_out => s2mm_mask_fsync_out ,
-- VDMA process status
run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
all_idle => s2mm_all_idle ,
parameter_update => s2mm_parameter_update ,
-- VDMA Frame Sync sources
fsync => s2mm_cdc2dmac_fsync ,
tuser_fsync => s2mm_tuser_fsync ,
othrchnl_fsync => mm2s_to_s2mm_fsync ,
fsync_src_select => s2mm_dmacr(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) ,
-- VDMA frame sync output to core
frame_sync => s2mm_frame_sync ,
-- VDMA Frame Sync Output to ports
frame_sync_out => s2mm_dmac2cdc_fsync_out ,
prmtr_update => s2mm_dmac2cdc_prmtr_update
);
-- Clock Domain Crossing between m_axi_s2mm_aclk and s_axis_s2mm_aclk
S2MM_VID_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_vid_cdc
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_GENLOCK_MSTR_PTR_DWIDTH => NUM_FRM_STORE_WIDTH ,
C_GENLOCK_SLVE_PTR_DWIDTH => S2MM_GENLOCK_SLVE_PTR_DWIDTH ,
C_INTERNAL_GENLOCK_ENABLE => INTERNAL_GENLOCK_ENABLE
)
port map(
prmry_aclk => m_axi_s2mm_aclk ,
prmry_resetn => s2mm_prmry_resetn ,
scndry_aclk => s_axis_s2mm_aclk ,
scndry_resetn => s2mm_axis_resetn ,
-- Genlock internal bus cdc
othrchnl_aclk => m_axi_mm2s_aclk ,
othrchnl_resetn => mm2s_prmry_resetn ,
othrchnl2cdc_frame_ptr_out => mm2s_frame_ptr_out_i ,
cdc2othrchnl_frame_ptr_in => mm2s_to_s2mm_frame_ptr_in ,
cdc2othrchnl_fsync => s2mm_to_mm2s_fsync ,
-- GenLock Clock Domain Crossing
dmac2cdc_frame_ptr_out => s2mm_m_frame_ptr_out ,
cdc2top_frame_ptr_out => s2mm_frame_ptr_out_i ,
top2cdc_frame_ptr_in => s2mm_frame_ptr_in ,
cdc2dmac_frame_ptr_in => s2mm_s_frame_ptr_in ,
dmac2cdc_mstrfrm_tstsync => s2mm_mstrfrm_tstsync ,
cdc2dmac_mstrfrm_tstsync => s2mm_mstrfrm_tstsync_out ,
-- SOF Detection Domain Crossing
vid2cdc_packet_sof => s2mm_vid2cdc_packet_sof ,
cdc2dmac_packet_sof => s2mm_packet_sof ,
-- Frame Sync Generation Domain Crossing
vid2cdc_fsync => s2mm_fsync_core ,
cdc2dmac_fsync => s2mm_cdc2dmac_fsync ,
dmac2cdc_fsync_out => s2mm_dmac2cdc_fsync_out ,
dmac2cdc_prmtr_update => s2mm_dmac2cdc_prmtr_update ,
cdc2vid_fsync_out => s2mm_fsync_out_i ,
cdc2vid_prmtr_update => s2mm_prmtr_update_i
);
s2mm_fsync_out_sig <= s2mm_fsync_out_i;
-- Start of Frame Detection - used for interrupt coalescing
S2MM_SOF_I : entity axi_vdma_v6_2_8.axi_vdma_sof_gen
port map(
scndry_aclk => s_axis_s2mm_aclk ,
scndry_resetn => s2mm_axis_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid_i ,
fsync => s2mm_fsync_out_i , -- CR622884
packet_sof => s2mm_vid2cdc_packet_sof
);
-------------------------------------------------------------------------------
-- Primary S2MM Line Buffer
-------------------------------------------------------------------------------
S2MM_LINEBUFFER_I : entity axi_vdma_v6_2_8.axi_vdma_s2mm_linebuf
generic map(
C_DATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED ,
C_S2MM_SOF_ENABLE => S2MM_SOF_ENABLE ,
C_USE_FSYNC => C_USE_S2MM_FSYNC_01 ,
C_USE_S2MM_FSYNC => C_USE_S2MM_FSYNC ,
C_S_AXIS_S2MM_TUSER_BITS => C_S_AXIS_S2MM_TUSER_BITS ,
C_INCLUDE_S2MM_DRE => C_S2MM_ENABLE_TKEEP ,
C_TOPLVL_LINEBUFFER_DEPTH => C_S2MM_LINEBUFFER_DEPTH , -- CR625142
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_LINEBUFFER_DEPTH => S2MM_LINEBUFFER_DEPTH ,
C_LINEBUFFER_AF_THRESH => C_S2MM_LINEBUFFER_THRESH_INT ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
ENABLE_FLUSH_ON_FSYNC => ENABLE_FLUSH_ON_S2MM_FSYNC,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
s_axis_aclk => s_axis_s2mm_aclk ,
s_axis_resetn => s2mm_axis_resetn ,
m_axis_aclk => m_axi_s2mm_aclk ,
m_axis_resetn => s2mm_prmry_resetn ,
s2mm_axis_linebuf_reset_out => s2mm_axis_linebuf_reset_out ,
-- Graceful shut down control
run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
dm_halt => s2mm_halt , -- CR591965
dm_halt_cmplt => s2mm_halt_cmplt , -- CR591965
capture_dm_done_vsize_counter => s2mm_capture_dm_done_vsize_counter_sig ,
s2mm_fsize_mismatch_err_flag => s2mm_fsize_mismatch_err_flag ,
s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s ,
s2mm_fsize_mismatch_err => s2mm_fsize_mismatch_err ,
drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err ,
no_fsync_before_vsize_sel_00_01 => no_fsync_before_vsize_sel_00_01 ,
hold_dummy_tready_low => hold_dummy_tready_low ,
hold_dummy_tready_low2 => hold_dummy_tready_low2 ,
mm2s_fsync => mm2s_fsync_fe ,
m_axis_mm2s_aclk => m_axis_mm2s_aclk ,
mm2s_axis_resetn => mm2s_axis_resetn ,
s2mm_fsync_core => s2mm_fsync_core ,
s2mm_fsync => s2mm_fsync_fe ,
s2mm_tuser_fsync_top => s2mm_tuser_fsync_top ,
s2mm_dmasr_fsize_less_err => s2mm_dmasr(DMASR_FSIZEERR_BIT) ,
fsync_src_select => s2mm_dmacr(DMACR_FSYNCSEL_MSB
downto DMACR_FSYNCSEL_LSB) ,
fsync_src_select_s => s2mm_fsync_src_select_s ,
chnl_ready_external => s2mm_chnl_ready ,
strm_not_finished => s2mm_strm_not_finished ,
crnt_vsize_d2_s => s2mm_crnt_vsize_d2 ,
-- Line Tracking Control
crnt_vsize => s2mm_crnt_vsize ,
fsync_out_m => s2mm_fsync_out_m_i ,
fsync_out => s2mm_fsync_out_i ,
frame_sync => s2mm_frame_sync ,
-- Threshold
linebuf_threshold => s2mm_linebuf_threshold ,
-- Stream In
s_axis_tdata => s_axis_s2mm_tdata_i ,
s_axis_tkeep => s_axis_s2mm_tkeep_i ,
s_axis_tlast => s_axis_s2mm_tlast_i ,
s_axis_tvalid => s_axis_s2mm_tvalid_i ,
s_axis_tready => s_axis_s2mm_tready_i ,
s_axis_tuser => s_axis_s2mm_tuser_i ,
-- Stream Out
m_axis_tdata => linebuf2dm_s2mm_tdata ,
m_axis_tkeep => linebuf2dm_s2mm_tkeep ,
m_axis_tlast => linebuf2dm_s2mm_tlast ,
m_axis_tvalid => linebuf2dm_s2mm_tvalid ,
m_axis_tready => dm2linebuf_s2mm_tready ,
-- Fifo Status Flags
s2mm_fifo_full => s2mm_buffer_full_i ,
s2mm_fifo_almost_full => s2mm_buffer_almost_full_i ,
s2mm_all_lines_xfred => s2mm_all_lines_xfred , -- CR591965
all_lasts_rcvd => all_lasts_rcvd ,
s2mm_tuser_fsync => s2mm_tuser_fsync
);
end generate GEN_SPRT_FOR_S2MM;
-- Do not generate support logic for S2MM
GEN_NO_SPRT_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
-- Register Module Tie-Offs
s2mm_ip2axi_rddata <= (others => '0');
--s2mm_ip2axi_rddata_valid <= '0';
s2mm_ip2axi_frame_ptr_ref <= (others => '0');
s2mm_ip2axi_frame_store <= (others => '0');
s2mm_ip2axi_introut <= '0';
s2mm_soft_reset <= '0';
s2mm_irqthresh_rstdsbl <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dmacr <= (others => '0');
s2mm_dmasr <= (others => '0');
s2mm_curdesc <= (others => '0');
s2mm_taildesc <= (others => '0');
s2mm_num_frame_store <= (others => '0');
s2mm_linebuf_threshold <= (others => '0');
s2mm_regdir_idle <= '0';
s2mm_prmtr_updt_complete <= '0';
s2mm_reg_module_vsize <= (others => '0');
s2mm_reg_module_hsize <= (others => '0');
s2mm_reg_module_stride <= (others => '0');
s2mm_reg_module_frmdly <= (others => '0');
s2mm_dummy_tready <= '0';
-- Must zero each element of an array of vectors to zero
-- all vectors.
GEN_S2MM_ZERO_STRT : for i in 0 to C_NUM_FSTORES-1 generate
begin
s2mm_reg_module_strt_addr(i) <= (others => '0');
end generate GEN_S2MM_ZERO_STRT;
-- Line buffer Tie-Offs
s_axis_s2mm_tready_i_axis_dw_conv <= '0';
s_axis_s2mm_tready_i <= '0';
s_axis_s2mm_tready <= '0';
s2mm_capture_dm_done_vsize_counter_sig <= (others => '0');
s2mm_capture_hsize_at_uf_err_sig <= (others => '0');
linebuf2dm_s2mm_tdata <= (others => '0');
linebuf2dm_s2mm_tkeep <= (others => '0');
linebuf2dm_s2mm_tlast <= '0';
linebuf2dm_s2mm_tvalid <= '0';
s2mm_buffer_full_i <= '0';
s2mm_buffer_almost_full_i <= '0';
s2mm_all_lines_xfred <= '0'; -- CR591965
s2mm_tuser_fsync <= '0';
-- Frame sync generator
s2mm_frame_sync <= '0';
-- SOF/EOF generator
s2mm_packet_sof <= '0';
-- DMA Controller
s2mm_halted_clr <= '0';
s2mm_halted_set <= '1';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s2mm_frame_number <= (others => '0');
s2mm_chnl_current_frame <= (others => '0');
s2mm_genlock_pair_frame <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_stop <= '0';
s2mm_all_idle <= '1';
s2mm_cmdsts_idle <= '1';
s2mm_ftchcmdsts_idle <= '1';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others => '0');
m_axis_s2mm_sts_tready <= '0';
s2mm_frame_ptr_out_i <= (others => '0');
s2mm_m_frame_ptr_out <= (others => '0');
mm2s_to_s2mm_frame_ptr_in <= (others => '0');
s2mm_valid_frame_sync <= '0';
s2mm_valid_frame_sync_cmb <= '0';
s2mm_valid_video_prmtrs <= '0';
s2mm_parameter_update <= '0';
s2mm_tstvect_err <= '0';
s2mm_tstvect_fsync <= '0';
s2mm_tstvect_frame <= (others => '0');
s2mm_dma_interr_set <= '0';
s2mm_dma_interr_set_minus_frame_errors <= '0';
s2mm_dma_slverr_set <= '0';
s2mm_dma_decerr_set <= '0';
s2mm_fsize_mismatch_err <= '0';
s2mm_lsize_mismatch_err <= '0';
s2mm_lsize_more_mismatch_err <= '0';
-- Frame Sync generator
s2mm_fsync_out_sig <= '0';
s2mm_prmtr_update_i <= '0';
s2mm_crnt_vsize <= (others => '0'); -- CR575884
s2mm_mask_fsync_out <= '0';
s2mm_mstrfrm_tstsync <= '0';
s2mm_mstrfrm_tstsync_out <= '0';
s2mm_tstvect_frm_ptr_out <= (others => '0');
s2mm_frmstr_err_addr <= (others => '0');
s2mm_to_mm2s_fsync <= '0';
end generate GEN_NO_SPRT_FOR_S2MM;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1_11.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_NEW ,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED ,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => DM_CLOCK_SYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_ENABLE_MM2S_TKEEP => C_MM2S_ENABLE_TKEEP ,
C_MM2S_BURST_SIZE => C_MM2S_MAX_BURST_LENGTH ,
C_MM2S_BTT_USED => MM2S_DM_BTT_LENGTH_WIDTH ,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH ,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF ,
C_ENABLE_SKID_BUF => "11100" ,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_NEW ,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH_CALCULATED ,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => DM_CLOCK_SYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_ENABLE_S2MM_TKEEP => C_S2MM_ENABLE_TKEEP ,
C_S2MM_BURST_SIZE => C_S2MM_MAX_BURST_LENGTH ,
C_S2MM_BTT_USED => S2MM_DM_BTT_LENGTH_WIDTH ,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH ,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF ,
C_CMD_WIDTH => CMD_WIDTH ,
C_FAMILY => C_ROOT_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => mm2s_dm_prmry_resetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_mm2s_aclk ,
m_axis_mm2s_cmdsts_aresetn => mm2s_dm_prmry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr_int ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => dm2linebuf_mm2s_tdata ,
m_axis_mm2s_tkeep => dm2linebuf_mm2s_tkeep ,
m_axis_mm2s_tlast => dm2linebuf_mm2s_tlast ,
m_axis_mm2s_tvalid => dm2linebuf_mm2s_tvalid ,
m_axis_mm2s_tready => linebuf2dm_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- Datamover v4_02_a addional signals not needed for VDMA
--sg_ctl => (others => '0') ,
m_axi_mm2s_aruser => open ,
m_axi_s2mm_awuser => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => s2mm_dm_prmry_resetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_s2mm_aclk ,
m_axis_s2mm_cmdsts_aresetn => s2mm_dm_prmry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr_int ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => linebuf2dm_s2mm_tdata ,
s_axis_s2mm_tkeep => linebuf2dm_s2mm_tkeep ,
s_axis_s2mm_tlast => linebuf2dm_s2mm_tlast ,
s_axis_s2mm_tvalid => linebuf2dm_s2mm_tvalid ,
s_axis_s2mm_tready => dm2linebuf_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_full_wrap.vhd
|
5
|
70871
|
-------------------------------------------------------------------------------
-- axi_datamover_mm2s_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_reset;
use axi_datamover_v5_1_11.axi_datamover_cmd_status;
use axi_datamover_v5_1_11.axi_datamover_pcc;
use axi_datamover_v5_1_11.axi_datamover_addr_cntl;
use axi_datamover_v5_1_11.axi_datamover_rddata_cntl;
use axi_datamover_v5_1_11.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1_11.axi_datamover_mm2s_dre;
Use axi_datamover_v5_1_11.axi_datamover_rd_sf;
use axi_datamover_v5_1_11.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_full_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 1;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the incllusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit Store and Forward
-- 1 = Include Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ---------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- MM2S Halt request input control --------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Error discrete output ------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ---------
-- Used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
-------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
---------------------------------------------------------------
-- Address Posting contols ------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
---------------------------------------------------------------
-- MM2S AXI Address Channel I/O ---------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals ------------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
------------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O -----------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
---------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
----------------------------------------------------------------------------------------
-- Testing Support I/O -------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------
);
end entity axi_datamover_mm2s_full_wrap;
architecture implementation of axi_datamover_mm2s_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else -- no DRE
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others => -- 128 ratio
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for MM2S
-- modules upstream from the downsizing Store and Forward. If
-- Store and Forward is present, then the effective native width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Native Data width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled = 1) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-- Constant Declarations ----------------------------------------
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH,
C_MM2S_SDATA_WIDTH,
C_INCLUDE_MM2S_GP_SF);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S;
Constant IS_MM2S : integer range 0 to 1 := 1;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH;
Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE;
Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED;
Constant NO_INDET_BTT : integer range 0 to 1 := 0;
Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE,
C_MM2S_SDATA_WIDTH);
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE,
C_MM2S_SDATA_WIDTH);
-- Calculates the minimum needed depth of the Store and Forward FIFO
-- based on the MM2S pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * MM2S_BURST_SIZE;
-- Assigns the depth of the optional Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH,
MM2S_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2rdc_wready : std_logic := '0';
signal sig_rdc2sf_wvalid : std_logic := '0';
signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2sf_wlast : std_logic := '0';
signal sig_skid2dre_wready : std_logic := '0';
signal sig_dre2skid_wvalid : std_logic := '0';
signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2skid_wlast : std_logic := '0';
signal sig_dre2sf_wready : std_logic := '0';
signal sig_sf2dre_wvalid : std_logic := '0';
signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2dre_wlast : std_logic := '0';
signal sig_rdc2dre_new_align : std_logic := '0';
signal sig_rdc2dre_use_autodest : std_logic := '0';
signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_flush : std_logic := '0';
signal sig_sf2dre_new_align : std_logic := '0';
signal sig_sf2dre_use_autodest : std_logic := '0';
signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_flush : std_logic := '0';
signal sig_dre_new_align : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_sf_allow_addr_req : std_logic := '0';
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_sf2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2sf_cmd_valid : std_logic := '0';
signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2sf_drr : std_logic := '0';
signal sig_mstr2sf_eof : std_logic := '0';
signal sig_mstr2sf_calc_error : std_logic := '0';
signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_data2sf_cmd_cmplt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
signal mm2s_aruser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug vector output
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc
mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc
-- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
sig_cache_data <= mm2s_cmd_wdata(79+(C_MM2S_ADDR_WIDTH-32) downto 72+(C_MM2S_ADDR_WIDTH-32)); -- This is the xUser and xCache values
end generate GEN_CACHE2;
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_11.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_11.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1_11.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1_11.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_MM2S ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_BTT_USED => MM2S_BTT_USED ,
C_SUPPORT_INDET_BTT => NO_INDET_BTT ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_btt => sig_mstr2sf_btt ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_11.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => mm2s_arcache_int ,
addr2axi_auser => mm2s_aruser_int ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_mm2s_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1_11.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => sig_rdc2dre_new_align ,
mm2s_dre_use_autodest => sig_rdc2dre_use_autodest ,
mm2s_dre_src_align => sig_rdc2dre_src_align ,
mm2s_dre_dest_align => sig_rdc2dre_dest_align ,
mm2s_dre_flush => sig_rdc2dre_flush ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2sf_wvalid ,
mm2s_strm_wready => sig_sf2rdc_wready ,
mm2s_strm_wdata => sig_rdc2sf_wdata ,
mm2s_strm_wstrb => sig_rdc2sf_wstrb ,
mm2s_strm_wlast => sig_rdc2sf_wlast ,
-- MM2S Store and Forward Supplimental Control ----------
mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_SF
--
-- If Generate Description:
-- Include the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate
begin
-- Merge external address posting control with the
-- Store and Forward address posting control
sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and
mm2s_allow_addr_req;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
sig_dre_new_align <= sig_sf2dre_new_align ;
sig_dre_use_autodest <= sig_sf2dre_use_autodest ;
sig_dre_src_align <= sig_sf2dre_src_align ;
sig_dre_dest_align <= sig_sf2dre_dest_align ;
sig_dre_flush <= sig_sf2dre_flush ;
------------------------------------------------------------
-- Instance: I_RD_SF
--
-- Description:
-- Instance for the MM2S Store and Forward module with
-- downsizer support.
--
------------------------------------------------------------
I_RD_SF : entity axi_datamover_v5_1_11.axi_datamover_rd_sf
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_DRE_IS_USED => INCLUDE_DRE ,
C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -------------------------------
aclk => mm2s_aclk ,
reset => sig_mmap_rst ,
-- DataMover Read Side Address Pipelining Control Interface
ok_to_post_rd_addr => sig_sf_allow_addr_req ,
rd_addr_posted => sig_addr_req_posted ,
rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S Read Data Controller -----
sf2sin_tready => sig_sf2rdc_wready ,
sin2sf_tvalid => sig_rdc2sf_wvalid ,
sin2sf_tdata => sig_rdc2sf_wdata ,
sin2sf_tkeep => sig_rdc2sf_wstrb ,
sin2sf_tlast => sig_rdc2sf_wlast ,
-- RDC Store and Forward Supplimental Controls ----------
data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
data2sf_dre_flush => sig_rdc2dre_flush ,
-- DRE Control Interface from the Command Calculator -----------------------------
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset ,
-- MM2S DRE Control -------------------------------------------------------------
sf2dre_new_align => sig_sf2dre_new_align ,
sf2dre_use_autodest => sig_sf2dre_use_autodest ,
sf2dre_src_align => sig_sf2dre_src_align ,
sf2dre_dest_align => sig_sf2dre_dest_align ,
sf2dre_flush => sig_sf2dre_flush ,
-- Stream Out ----------------------------------
sout2sf_tready => sig_dre2sf_wready ,
sf2sout_tvalid => sig_sf2dre_wvalid ,
sf2sout_tdata => sig_sf2dre_wdata ,
sf2sout_tkeep => sig_sf2dre_wstrb ,
sf2sout_tlast => sig_sf2dre_wlast
);
-- ------------------------------------------------------------
-- -- Instance: I_RD_SF
-- --
-- -- Description:
-- -- Instance for the MM2S Store and Forward module.
-- --
-- ------------------------------------------------------------
-- I_RD_SF : entity axi_datamover_v5_1_11.axi_datamover_rd_sf
-- generic map (
--
-- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
-- C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
-- C_DRE_IS_USED => INCLUDE_DRE ,
-- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
--
-- -- Clock and Reset inputs -------------------------------
-- aclk => mm2s_aclk ,
-- reset => sig_mmap_rst ,
--
--
-- -- DataMover Read Side Address Pipelining Control Interface
-- ok_to_post_rd_addr => sig_sf_allow_addr_req ,
-- rd_addr_posted => sig_addr_req_posted ,
-- rd_xfer_cmplt => sig_rd_xfer_cmplt ,
--
--
--
-- -- Read Side Stream In from DataMover MM2S -----
-- sf2sin_tready => sig_sf2dre_wready ,
-- sin2sf_tvalid => sig_dre2sf_wvalid ,
-- sin2sf_tdata => sig_dre2sf_wdata ,
-- sin2sf_tkeep => sig_dre2sf_wstrb ,
-- sin2sf_tlast => sig_dre2sf_wlast ,
--
--
--
-- -- Stream Out ----------------------------------
-- sout2sf_tready => sig_skid2sf_wready ,
-- sf2sout_tvalid => sig_sf2skid_wvalid ,
-- sf2sout_tdata => sig_sf2skid_wdata ,
-- sf2sout_tkeep => sig_sf2skid_wstrb ,
-- sf2sout_tlast => sig_sf2skid_wlast
--
-- );
end generate GEN_INCLUDE_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_SF
--
-- If Generate Description:
-- Omit the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate
begin
-- Allow external address posting control
-- Ignore Store and Forward Control
sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ;
sig_sf_allow_addr_req <= '0' ;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
-- DRE Control Bus (Connect to the Read data Controller)
sig_dre_new_align <= sig_rdc2dre_new_align ;
sig_dre_use_autodest <= sig_rdc2dre_use_autodest ;
sig_dre_src_align <= sig_rdc2dre_src_align ;
sig_dre_dest_align <= sig_rdc2dre_dest_align ;
sig_dre_flush <= sig_rdc2dre_flush ;
-- Just pass stream signals through
sig_sf2rdc_wready <= sig_dre2sf_wready ;
sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ;
sig_sf2dre_wdata <= sig_rdc2sf_wdata ;
sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ;
sig_sf2dre_wlast <= sig_rdc2sf_wlast ;
-- Always enable the DRE Cmd bus for loading to keep from
-- stalling the PCC module
sig_sf2mstr_cmd_ready <= LOGIC_HIGH;
end generate GEN_NO_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_DRE
--
-- If Generate Description:
-- Include the MM2S DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate
begin
------------------------------------------------------------
-- Instance: I_DRE64
--
-- Description:
-- Instance for the MM2S DRE whach can support widths of
-- 16 bits to 64 bits.
--
------------------------------------------------------------
I_DRE_16_to_64 : entity axi_datamover_v5_1_11.axi_datamover_mm2s_dre
generic map (
C_DWIDTH => MM2S_SDATA_WIDTH ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH
)
port map (
-- Control inputs
dre_clk => mm2s_aclk ,
dre_rst => sig_stream_rst ,
dre_new_align => sig_dre_new_align ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
dre_flush => sig_dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_sf2dre_wstrb ,
dre_in_tdata => sig_sf2dre_wdata ,
dre_in_tlast => sig_sf2dre_wlast ,
dre_in_tvalid => sig_sf2dre_wvalid ,
dre_in_tready => sig_dre2sf_wready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2skid_wstrb ,
dre_out_tdata => sig_dre2skid_wdata ,
dre_out_tlast => sig_dre2skid_wlast ,
dre_out_tvalid => sig_dre2skid_wvalid ,
dre_out_tready => sig_skid2dre_wready
);
end generate GEN_INCLUDE_MM2S_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_DRE
--
-- If Generate Description:
-- Omit the MM2S DRE and housekeep the signals that it
-- needs to output.
--
------------------------------------------------------------
GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate
begin
-- Just pass stream signals through from the Store
-- and Forward module
sig_dre2sf_wready <= sig_skid2dre_wready ;
sig_dre2skid_wvalid <= sig_sf2dre_wvalid ;
sig_dre2skid_wdata <= sig_sf2dre_wdata ;
sig_dre2skid_wstrb <= sig_sf2dre_wstrb ;
sig_dre2skid_wlast <= sig_sf2dre_wlast ;
end generate GEN_NO_MM2S_DRE;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_dre2skid_wvalid ,
s_ready => sig_skid2dre_wready ,
s_data => sig_dre2skid_wdata ,
s_strb => sig_dre2skid_wstrb ,
s_last => sig_dre2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_dre2skid_wvalid;
sig_skid2dre_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_dre2skid_wdata;
mm2s_strm_wstrb <= sig_dre2skid_wstrb;
mm2s_strm_wlast <= sig_dre2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_pkg.vhd
|
4
|
71734
|
-------------------------------------------------------------------------------
-- axi_vdma_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI VDMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
package axi_vdma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
function enable_tkeep_connectivity (tdata_dwidth : integer; tdata_width_calculated : integer; DRE_ON : integer)
return integer;
-- CALCULATE mm2s_tdata_width for axi_vdma
function calculated_mm2s_tdata_width (mm2s_tdata_dwidth : integer)
return integer;
function calculated_s2mm_tdata_width (s2mm_tdata_dwidth : integer)
return integer;
function calculated_minimum_mm2s_linebuffer_thresh (mm2s_included : integer; mm2s_tdata_dwidth : integer; mm2s_linebuffer_depth: integer)
return integer;
function calculated_minimum_s2mm_linebuffer_thresh (s2mm_included : integer; s2mm_tdata_dwidth : integer; s2mm_linebuffer_depth: integer)
return integer;
function find_mm2s_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer;
function find_s2mm_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer;
function find_s2mm_fsync_01 (use_s2mm_fsync : integer)
return integer;
function find_mm2s_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer;
function find_s2mm_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer;
-- Find minimum required btt width
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer;
-- Converts string to interger
function string2int(strngbuf: string)
return integer;
-- Return number of registers
function get_num_registers(mode : integer;
sg_num : integer;
regdir_num : integer)
return integer;
-- Return correct hertz paramter value
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer;
-- Return SnF enable or disable
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer;
-- Return mm2s index or converted s2mm index
function convert_base_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer;
-- Return mm2s index or converted s2mm index
function convert_regdir_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer;
-- Return enable genlock bus
function enable_internal_genloc(mm2s_enabled : integer;
s2mm_enabled : integer;
internal_genlock : integer;
mm2s_genlock_mode : integer;
s2mm_genlock_mode : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
constant NUM_REG_TOTAL_SG : integer := 62;
constant NUM_REG_TOTAL_REGDIR : integer := 62;
----constant NUM_REG_TOTAL_SG : integer := 20;
----constant NUM_REG_TOTAL_REGDIR : integer := 59;
--constant NUM_REG_TOTAL_REGDIR : integer := 156;
--constant NUM_REG_TOTAL_REGDIR : integer := 123;
constant NUM_REG_PER_CHANNEL : integer := 8;
constant NUM_DIRECT_REG_PER_CHANNEL : integer := 19;
--constant NUM_DIRECT_REG_PER_CHANNEL : integer := 67;
--constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
constant CMD_BASE_WIDTH : integer := 40;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Clock Domain Crossing Constants
constant CDC_TYPE_PULSE_P_S : integer := 0;
constant CDC_TYPE_LEVEL_P_S : integer := 1;
constant CDC_TYPE_PULSE_S_P : integer := 2;
constant CDC_TYPE_LEVEL_S_P : integer := 3;
constant CDC_TYPE_VECTR_P_S : integer := 4;
constant CDC_TYPE_VECTR_S_P : integer := 5;
constant CDC_TYPE_PULSE_P_S_NO_RST : integer := 6;
constant CDC_TYPE_LEVEL_P_S_NO_RST : integer := 7;
constant CDC_TYPE_PULSE_S_P_NO_RST : integer := 8;
constant CDC_TYPE_LEVEL_S_P_NO_RST : integer := 9;
constant CDC_TYPE_PULSE_P_S_LL : integer := 10;
constant CDC_TYPE_PULSE_S_P_LL : integer := 11;
constant CDC_TYPE_PULSE_P_S_OPEN_ENDED : integer := 12;
constant CDC_TYPE_PULSE_S_P_OPEN_ENDED : integer := 13;
constant CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST : integer := 14;
constant CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST : integer := 15;
constant MTBF_STAGES : integer := 4;
constant MTBF_STAGES_LITE : integer := 3;
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-- Frame Store
constant NUM_FRM_STORE_WIDTH : integer := 6;
constant FRAME_NUMBER_WIDTH : integer := NUM_FRM_STORE_WIDTH - 1;
constant ZERO_FRAMESTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
constant ONE_FRAMESTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,NUM_FRM_STORE_WIDTH));
constant MAX_FSTORES : integer := 32;
-- Line Buffer
constant LINEBUFFER_THRESH_WIDTH : integer := 17;
-- Video parameter constants
constant VSIZE_DWIDTH : integer := 13;
constant HSIZE_DWIDTH : integer := 16;
constant STRIDE_DWIDTH : integer := 16;
constant FRMDLY_DWIDTH : integer := FRAME_NUMBER_WIDTH;
constant FRMDLY_MSB : integer := 28;
constant FRMDLY_LSB : integer := 24;
constant RSVD_BITS_31TO29 : std_logic_vector(2 downto 0) := (others => '0');
constant RSVD_BITS_23TO16 : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Lite AXI DMA Register Offsets
-------------------------------------------------------------------------------
constant MM2S_DMACR_INDEX : integer := 0;
constant MM2S_DMASR_INDEX : integer := 1;
constant MM2S_CURDESC_LSB_INDEX : integer := 2;
constant MM2S_CURDESC_MSB_INDEX : integer := 3;
constant MM2S_TAILDESC_LSB_INDEX : integer := 4;
constant MM2S_TAILDESC_MSB_INDEX : integer := 5;
constant MM2S_REG_IND : integer := 5;
constant MM2S_FRAME_STORE_INDEX : integer := 6;
constant MM2S_THRESHOLD_INDEX : integer := 7;
constant RESERVED_20_INDEX : integer := 8;
constant VDMA_GLPTR_INDEX : integer := 9;
constant VDMA_PARKPTR_INDEX : integer := 10;
constant VDMA_VERISON_INDEX : integer := 11;
constant S2MM_DMACR_INDEX : integer := 12;
constant S2MM_DMASR_INDEX : integer := 13;
constant S2MM_CURDESC_LSB_INDEX : integer := 14;
constant S2MM_CURDESC_MSB_INDEX : integer := 15;
constant S2MM_DMA_IRQ_MASK : integer := 15;
constant S2MM_TAILDESC_LSB_INDEX : integer := 16;
constant S2MM_TAILDESC_MSB_INDEX : integer := 17;
constant S2MM_REG_IND : integer := 17;
constant S2MM_FRAME_STORE_INDEX : integer := 18;
constant S2MM_THRESHOLD_INDEX : integer := 19;
-- Register direct
constant MM2S_VSIZE_INDEX : integer := 20;
constant MM2S_HSIZE_INDEX : integer := 21;
constant MM2S_DLYSTRD_INDEX : integer := 22;
constant MM2S_STARTADDR1_INDEX : integer := 23;
constant MM2S_STARTADDR2_INDEX : integer := 24;
constant MM2S_STARTADDR3_INDEX : integer := 25;
constant MM2S_STARTADDR4_INDEX : integer := 26;
constant MM2S_STARTADDR5_INDEX : integer := 27;
constant MM2S_STARTADDR6_INDEX : integer := 28;
constant MM2S_STARTADDR7_INDEX : integer := 29;
constant MM2S_STARTADDR8_INDEX : integer := 30;
constant MM2S_STARTADDR9_INDEX : integer := 31;
constant MM2S_STARTADDR10_INDEX : integer := 32;
constant MM2S_STARTADDR11_INDEX : integer := 33;
constant MM2S_STARTADDR12_INDEX : integer := 34;
constant MM2S_STARTADDR13_INDEX : integer := 35;
constant MM2S_STARTADDR14_INDEX : integer := 36;
constant MM2S_STARTADDR15_INDEX : integer := 37;
constant MM2S_STARTADDR16_INDEX : integer := 38;
constant RESERVED_9C_INDEX : integer := 39;
constant S2MM_VSIZE_INDEX : integer := 40;
constant S2MM_HSIZE_INDEX : integer := 41;
constant S2MM_DLYSTRD_INDEX : integer := 42;
constant S2MM_STARTADDR1_INDEX : integer := 43;
constant S2MM_STARTADDR2_INDEX : integer := 44;
constant S2MM_STARTADDR3_INDEX : integer := 45;
constant S2MM_STARTADDR4_INDEX : integer := 46;
constant S2MM_STARTADDR5_INDEX : integer := 47;
constant S2MM_STARTADDR6_INDEX : integer := 48;
constant S2MM_STARTADDR7_INDEX : integer := 49;
constant S2MM_STARTADDR8_INDEX : integer := 50;
constant S2MM_STARTADDR9_INDEX : integer := 51;
constant S2MM_STARTADDR10_INDEX : integer := 52;
constant S2MM_STARTADDR11_INDEX : integer := 53;
constant S2MM_STARTADDR12_INDEX : integer := 54;
constant S2MM_STARTADDR13_INDEX : integer := 55;
constant S2MM_STARTADDR14_INDEX : integer := 56;
constant S2MM_STARTADDR15_INDEX : integer := 57;
constant S2MM_STARTADDR16_INDEX : integer := 58;
constant RESERVED_EC_INDEX : integer := 59;
--constant RESERVED_F0_INDEX : integer := 60;
constant HSIZE_AT_LLESS_ERR_F0_INDEX : integer := 60;
--constant RESERVED_F4_INDEX : integer := 61;
constant VSIZE_AT_FLESS_ERR_F4_INDEX : integer := 61;
constant RESERVED_F8_INDEX : integer := 62;
constant RESERVED_FC_INDEX : integer := 63;
constant RESERVED_100_INDEX : integer := 64;
constant RESERVED_104_INDEX : integer := 65;
constant RESERVED_108_INDEX : integer := 66;
constant RESERVED_10C_INDEX : integer := 67;
constant RESERVED_110_INDEX : integer := 68;
constant RESERVED_114_INDEX : integer := 69;
constant RESERVED_118_INDEX : integer := 70;
constant RESERVED_11C_INDEX : integer := 71;
constant RESERVED_120_INDEX : integer := 72;
constant RESERVED_124_INDEX : integer := 73;
constant RESERVED_128_INDEX : integer := 74;
constant RESERVED_12C_INDEX : integer := 75;
constant RESERVED_130_INDEX : integer := 76;
constant RESERVED_134_INDEX : integer := 77;
constant RESERVED_138_INDEX : integer := 78;
constant RESERVED_13C_INDEX : integer := 79;
constant RESERVED_140_INDEX : integer := 80;
constant RESERVED_144_INDEX : integer := 81;
constant RESERVED_148_INDEX : integer := 82;
constant RESERVED_14C_INDEX : integer := 83;
constant RESERVED_150_INDEX : integer := 84;
constant RESERVED_154_INDEX : integer := 85;
constant RESERVED_158_INDEX : integer := 86;
constant MM2S_STARTADDR17_INDEX : integer := 87;
constant MM2S_STARTADDR18_INDEX : integer := 88;
constant MM2S_STARTADDR19_INDEX : integer := 89;
constant MM2S_STARTADDR20_INDEX : integer := 90;
constant MM2S_STARTADDR21_INDEX : integer := 91;
constant MM2S_STARTADDR22_INDEX : integer := 92;
constant MM2S_STARTADDR23_INDEX : integer := 93;
constant MM2S_STARTADDR24_INDEX : integer := 94;
constant MM2S_STARTADDR25_INDEX : integer := 95;
constant MM2S_STARTADDR26_INDEX : integer := 96;
constant MM2S_STARTADDR27_INDEX : integer := 97;
constant MM2S_STARTADDR28_INDEX : integer := 98;
constant MM2S_STARTADDR29_INDEX : integer := 99;
constant MM2S_STARTADDR30_INDEX : integer := 100;
constant MM2S_STARTADDR31_INDEX : integer := 101;
constant MM2S_STARTADDR32_INDEX : integer := 102;
constant RESERVED_19C_INDEX : integer := 103;
constant RESERVED_1A0_INDEX : integer := 104;
constant RESERVED_1A4_INDEX : integer := 105;
constant RESERVED_1A8_INDEX : integer := 106;
constant S2MM_STARTADDR17_INDEX : integer := 107;
constant S2MM_STARTADDR18_INDEX : integer := 108;
constant S2MM_STARTADDR19_INDEX : integer := 109;
constant S2MM_STARTADDR20_INDEX : integer := 110;
constant S2MM_STARTADDR21_INDEX : integer := 111;
constant S2MM_STARTADDR22_INDEX : integer := 112;
constant S2MM_STARTADDR23_INDEX : integer := 113;
constant S2MM_STARTADDR24_INDEX : integer := 114;
constant S2MM_STARTADDR25_INDEX : integer := 115;
constant S2MM_STARTADDR26_INDEX : integer := 116;
constant S2MM_STARTADDR27_INDEX : integer := 117;
constant S2MM_STARTADDR28_INDEX : integer := 118;
constant S2MM_STARTADDR29_INDEX : integer := 119;
constant S2MM_STARTADDR30_INDEX : integer := 120;
constant S2MM_STARTADDR31_INDEX : integer := 121;
constant S2MM_STARTADDR32_INDEX : integer := 122;
-- READ MUX Offsets
constant MM2S_REG_INDEX_OFFSET_90 : std_logic_vector(8 downto 0) := "000010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_90 : std_logic_vector(8 downto 0) := "001000100"; -- 44
constant MM2S_REG_INDEX_OFFSET_91 : std_logic_vector(8 downto 0) := "100010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_91 : std_logic_vector(8 downto 0) := "101000100"; -- 44
constant MM2S_REG_INDEX_OFFSET_8 : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant S2MM_REG_INDEX_OFFSET_8 : std_logic_vector(7 downto 0) := "01000100"; -- 44
-- }
constant MM2S_DMACR_OFFSET_SG : std_logic_vector(7 downto 0) := "00000000"; -- 00
constant MM2S_DMASR_OFFSET_SG : std_logic_vector(7 downto 0) := "00000100"; -- 04
constant MM2S_CURDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00001000"; -- 08
constant MM2S_CURDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00001100"; -- 0C
constant MM2S_TAILDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00010000"; -- 10
constant MM2S_TAILDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant MM2S_FRAME_STORE_OFFSET_SG : std_logic_vector(7 downto 0) := "00011000"; -- 18
constant MM2S_THRESHOLD_OFFSET_SG : std_logic_vector(7 downto 0) := "00011100"; -- 1C
constant RESERVED_20_OFFSET_SG : std_logic_vector(7 downto 0) := "00100000"; -- 20
constant RESERVED_24_OFFSET_SG : std_logic_vector(7 downto 0) := "00100100"; -- 24
constant VDMA_PARK_PTRREF_OFFSET : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant VDMA_PARK_PTRREF_OFFSET_SG : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET_SG : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant S2MM_DMACR_OFFSET_SG : std_logic_vector(7 downto 0) := "00110000"; -- 30
constant S2MM_DMASR_OFFSET_SG : std_logic_vector(7 downto 0) := "00110100"; -- 34
constant S2MM_CURDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00111000"; -- 38
constant S2MM_CURDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_DMA_IRQ_MASK_SG : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_TAILDESC_LSB_OFFSET_SG : std_logic_vector(7 downto 0) := "01000000"; -- 40
constant S2MM_TAILDESC_MSB_OFFSET_SG : std_logic_vector(7 downto 0) := "01000100"; -- 44
constant S2MM_FRAME_STORE_OFFSET_SG : std_logic_vector(7 downto 0) := "01001000"; -- 48
constant S2MM_THRESHOLD_OFFSET_SG : std_logic_vector(7 downto 0) := "01001100"; -- 4C
------
constant MM2S_DMACR_OFFSET_8 : std_logic_vector(7 downto 0) := "00000000"; -- 00
constant MM2S_DMASR_OFFSET_8 : std_logic_vector(7 downto 0) := "00000100"; -- 04
constant MM2S_CURDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00001000"; -- 08
constant MM2S_CURDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00001100"; -- 0C
constant MM2S_TAILDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00010000"; -- 10
constant MM2S_TAILDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00010100"; -- 14
constant MM2S_FRAME_STORE_OFFSET_8 : std_logic_vector(7 downto 0) := "00011000"; -- 18
constant MM2S_THRESHOLD_OFFSET_8 : std_logic_vector(7 downto 0) := "00011100"; -- 1C
constant RESERVED_20_OFFSET_8 : std_logic_vector(7 downto 0) := "00100000"; -- 20
constant RESERVED_24_OFFSET_8 : std_logic_vector(7 downto 0) := "00100100"; -- 24
constant VDMA_PARK_PTRREF_OFFSET_8 : std_logic_vector(7 downto 0) := "00101000"; -- 28
constant VDMA_VERSION_OFFSET_8 : std_logic_vector(7 downto 0) := "00101100"; -- 2C
constant S2MM_DMACR_OFFSET_8 : std_logic_vector(7 downto 0) := "00110000"; -- 30
constant S2MM_DMASR_OFFSET_8 : std_logic_vector(7 downto 0) := "00110100"; -- 34
constant S2MM_CURDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00111000"; -- 38
constant S2MM_CURDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_DMA_IRQ_MASK_8 : std_logic_vector(7 downto 0) := "00111100"; -- 3C
constant S2MM_TAILDESC_LSB_OFFSET_8 : std_logic_vector(7 downto 0) := "01000000"; -- 40
constant S2MM_TAILDESC_MSB_OFFSET_8 : std_logic_vector(7 downto 0) := "01000100"; -- 44
constant S2MM_FRAME_STORE_OFFSET_8 : std_logic_vector(7 downto 0) := "01001000"; -- 48
constant S2MM_THRESHOLD_OFFSET_8 : std_logic_vector(7 downto 0) := "01001100"; -- 4C
------
constant MM2S_DMACR_OFFSET_90 : std_logic_vector(8 downto 0) := "000000000"; -- 000
constant MM2S_DMASR_OFFSET_90 : std_logic_vector(8 downto 0) := "000000100"; -- 004
constant MM2S_CURDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000001000"; -- 008
constant MM2S_CURDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000001100"; -- 00C
constant MM2S_TAILDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000010000"; -- 010
constant MM2S_TAILDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000010100"; -- 014
constant MM2S_FRAME_STORE_OFFSET_90 : std_logic_vector(8 downto 0) := "000011000"; -- 018
constant MM2S_THRESHOLD_OFFSET_90 : std_logic_vector(8 downto 0) := "000011100"; -- 01C
constant RESERVED_20_OFFSET_90 : std_logic_vector(8 downto 0) := "000100000"; -- 020
constant RESERVED_24_OFFSET_90 : std_logic_vector(8 downto 0) := "000100100"; -- 024
constant VDMA_PARK_PTRREF_OFFSET_90 : std_logic_vector(8 downto 0) := "000101000"; -- 028
constant VDMA_VERSION_OFFSET_90 : std_logic_vector(8 downto 0) := "000101100"; -- 02C
constant S2MM_DMACR_OFFSET_90 : std_logic_vector(8 downto 0) := "000110000"; -- 030
constant S2MM_DMASR_OFFSET_90 : std_logic_vector(8 downto 0) := "000110100"; -- 034
constant S2MM_CURDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000111000"; -- 038
constant S2MM_CURDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "000111100"; -- 03C
constant S2MM_DMA_IRQ_MASK_OFFSET_90 : std_logic_vector(8 downto 0) := "000111100"; -- 03C
constant S2MM_TAILDESC_LSB_OFFSET_90 : std_logic_vector(8 downto 0) := "001000000"; -- 040
constant S2MM_TAILDESC_MSB_OFFSET_90 : std_logic_vector(8 downto 0) := "001000100"; -- 044
constant S2MM_FRAME_STORE_OFFSET_90 : std_logic_vector(8 downto 0) := "001001000"; -- 048
constant S2MM_THRESHOLD_OFFSET_90 : std_logic_vector(8 downto 0) := "001001100"; -- 04C
------
constant MM2S_DMACR_OFFSET_91 : std_logic_vector(8 downto 0) := "100000000"; -- 100
constant MM2S_DMASR_OFFSET_91 : std_logic_vector(8 downto 0) := "100000100"; -- 104
constant MM2S_CURDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100001000"; -- 108
constant MM2S_CURDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100001100"; -- 10C
constant MM2S_TAILDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100010000"; -- 110
constant MM2S_TAILDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100010100"; -- 114
constant MM2S_FRAME_STORE_OFFSET_91 : std_logic_vector(8 downto 0) := "100011000"; -- 118
constant MM2S_THRESHOLD_OFFSET_91 : std_logic_vector(8 downto 0) := "100011100"; -- 11C
constant RESERVED_20_OFFSET_91 : std_logic_vector(8 downto 0) := "100100000"; -- 120
constant RESERVED_24_OFFSET_91 : std_logic_vector(8 downto 0) := "100100100"; -- 124
constant VDMA_PARK_PTRREF_OFFSET_91 : std_logic_vector(8 downto 0) := "100101000"; -- 128
constant VDMA_VERSION_OFFSET_91 : std_logic_vector(8 downto 0) := "100101100"; -- 12C
constant S2MM_DMACR_OFFSET_91 : std_logic_vector(8 downto 0) := "100110000"; -- 130
constant S2MM_DMASR_OFFSET_91 : std_logic_vector(8 downto 0) := "100110100"; -- 134
constant S2MM_CURDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100111000"; -- 138
constant S2MM_CURDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant S2MM_DMA_IRQ_MASK_OFFSET_91 : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant S2MM_TAILDESC_LSB_OFFSET_91 : std_logic_vector(8 downto 0) := "101000000"; -- 140
constant S2MM_TAILDESC_MSB_OFFSET_91 : std_logic_vector(8 downto 0) := "101000100"; -- 144
constant S2MM_FRAME_STORE_OFFSET_91 : std_logic_vector(8 downto 0) := "101001000"; -- 148
constant S2MM_THRESHOLD_OFFSET_91 : std_logic_vector(8 downto 0) := "101001100"; -- 14C
------
-------- Register direct READ MUX Offsets
constant MM2S_VSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "01010000"; -- 50
constant MM2S_HSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "01010100"; -- 54
constant MM2S_DLYSTRD_OFFSET_8 : std_logic_vector(7 downto 0) := "01011000"; -- 58
constant MM2S_VSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "001010000"; -- 050
constant MM2S_HSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "001010100"; -- 054
constant MM2S_DLYSTRD_OFFSET_90 : std_logic_vector(8 downto 0) := "001011000"; -- 058
constant MM2S_VSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "101010000"; -- 050
constant MM2S_HSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "101010100"; -- 054
constant MM2S_DLYSTRD_OFFSET_91 : std_logic_vector(8 downto 0) := "101011000"; -- 058
constant MM2S_STARTADDR1_OFFSET_8 : std_logic_vector(7 downto 0) := "01011100"; -- 5C
constant MM2S_STARTADDR2_OFFSET_8 : std_logic_vector(7 downto 0) := "01100000"; -- 60
constant MM2S_STARTADDR3_OFFSET_8 : std_logic_vector(7 downto 0) := "01100100"; -- 64
constant MM2S_STARTADDR4_OFFSET_8 : std_logic_vector(7 downto 0) := "01101000"; -- 68
constant MM2S_STARTADDR5_OFFSET_8 : std_logic_vector(7 downto 0) := "01101100"; -- 6C
constant MM2S_STARTADDR6_OFFSET_8 : std_logic_vector(7 downto 0) := "01110000"; -- 70
constant MM2S_STARTADDR7_OFFSET_8 : std_logic_vector(7 downto 0) := "01110100"; -- 74
constant MM2S_STARTADDR8_OFFSET_8 : std_logic_vector(7 downto 0) := "01111000"; -- 78
constant MM2S_STARTADDR9_OFFSET_8 : std_logic_vector(7 downto 0) := "01111100"; -- 7C
constant MM2S_STARTADDR10_OFFSET_8 : std_logic_vector(7 downto 0) := "10000000"; -- 80
constant MM2S_STARTADDR11_OFFSET_8 : std_logic_vector(7 downto 0) := "10000100"; -- 84
constant MM2S_STARTADDR12_OFFSET_8 : std_logic_vector(7 downto 0) := "10001000"; -- 88
constant MM2S_STARTADDR13_OFFSET_8 : std_logic_vector(7 downto 0) := "10001100"; -- 8C
constant MM2S_STARTADDR14_OFFSET_8 : std_logic_vector(7 downto 0) := "10010000"; -- 90
constant MM2S_STARTADDR15_OFFSET_8 : std_logic_vector(7 downto 0) := "10010100"; -- 94
constant MM2S_STARTADDR16_OFFSET_8 : std_logic_vector(7 downto 0) := "10011000"; -- 98
constant MM2S_STARTADDR1_OFFSET_90 : std_logic_vector(8 downto 0) := "001011100"; -- 05C
constant MM2S_STARTADDR2_OFFSET_90 : std_logic_vector(8 downto 0) := "001100000"; -- 060
constant MM2S_STARTADDR3_OFFSET_90 : std_logic_vector(8 downto 0) := "001100100"; -- 064
constant MM2S_STARTADDR4_OFFSET_90 : std_logic_vector(8 downto 0) := "001101000"; -- 068
constant MM2S_STARTADDR5_OFFSET_90 : std_logic_vector(8 downto 0) := "001101100"; -- 06C
constant MM2S_STARTADDR6_OFFSET_90 : std_logic_vector(8 downto 0) := "001110000"; -- 070
constant MM2S_STARTADDR7_OFFSET_90 : std_logic_vector(8 downto 0) := "001110100"; -- 074
constant MM2S_STARTADDR8_OFFSET_90 : std_logic_vector(8 downto 0) := "001111000"; -- 078
constant MM2S_STARTADDR9_OFFSET_90 : std_logic_vector(8 downto 0) := "001111100"; -- 07C
constant MM2S_STARTADDR10_OFFSET_90 : std_logic_vector(8 downto 0) := "010000000"; -- 080
constant MM2S_STARTADDR11_OFFSET_90 : std_logic_vector(8 downto 0) := "010000100"; -- 084
constant MM2S_STARTADDR12_OFFSET_90 : std_logic_vector(8 downto 0) := "010001000"; -- 088
constant MM2S_STARTADDR13_OFFSET_90 : std_logic_vector(8 downto 0) := "010001100"; -- 08C
constant MM2S_STARTADDR14_OFFSET_90 : std_logic_vector(8 downto 0) := "010010000"; -- 090
constant MM2S_STARTADDR15_OFFSET_90 : std_logic_vector(8 downto 0) := "010010100"; -- 094
constant MM2S_STARTADDR16_OFFSET_90 : std_logic_vector(8 downto 0) := "010011000"; -- 098
constant MM2S_STARTADDR1_OFFSET_91 : std_logic_vector(8 downto 0) := "101011100"; -- 15C
constant MM2S_STARTADDR2_OFFSET_91 : std_logic_vector(8 downto 0) := "101100000"; -- 160
constant MM2S_STARTADDR3_OFFSET_91 : std_logic_vector(8 downto 0) := "101100100"; -- 164
constant MM2S_STARTADDR4_OFFSET_91 : std_logic_vector(8 downto 0) := "101101000"; -- 168
constant MM2S_STARTADDR5_OFFSET_91 : std_logic_vector(8 downto 0) := "101101100"; -- 16C
constant MM2S_STARTADDR6_OFFSET_91 : std_logic_vector(8 downto 0) := "101110000"; -- 170
constant MM2S_STARTADDR7_OFFSET_91 : std_logic_vector(8 downto 0) := "101110100"; -- 174
constant MM2S_STARTADDR8_OFFSET_91 : std_logic_vector(8 downto 0) := "101111000"; -- 178
constant MM2S_STARTADDR9_OFFSET_91 : std_logic_vector(8 downto 0) := "101111100"; -- 17C
constant MM2S_STARTADDR10_OFFSET_91 : std_logic_vector(8 downto 0) := "110000000"; -- 180
constant MM2S_STARTADDR11_OFFSET_91 : std_logic_vector(8 downto 0) := "110000100"; -- 184
constant MM2S_STARTADDR12_OFFSET_91 : std_logic_vector(8 downto 0) := "110001000"; -- 188
constant MM2S_STARTADDR13_OFFSET_91 : std_logic_vector(8 downto 0) := "110001100"; -- 18C
constant MM2S_STARTADDR14_OFFSET_91 : std_logic_vector(8 downto 0) := "110010000"; -- 190
constant MM2S_STARTADDR15_OFFSET_91 : std_logic_vector(8 downto 0) := "110010100"; -- 194
constant MM2S_STARTADDR16_OFFSET_91 : std_logic_vector(8 downto 0) := "110011000"; -- 198
constant RESERVED_9C_OFFSET_90 : std_logic_vector(8 downto 0) := "010011100"; -- 9C
constant S2MM_VSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "10100000"; -- A0
constant S2MM_HSIZE_OFFSET_8 : std_logic_vector(7 downto 0) := "10100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_8 : std_logic_vector(7 downto 0) := "10101000"; -- A8
constant S2MM_VSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "010100000"; -- A0
constant S2MM_HSIZE_OFFSET_90 : std_logic_vector(8 downto 0) := "010100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_90 : std_logic_vector(8 downto 0) := "010101000"; -- A8
constant S2MM_VSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "110100000"; -- A0
constant S2MM_HSIZE_OFFSET_91 : std_logic_vector(8 downto 0) := "110100100"; -- A4
constant S2MM_DLYSTRD_OFFSET_91 : std_logic_vector(8 downto 0) := "110101000"; -- A8
constant S2MM_STARTADDR1_OFFSET_8 : std_logic_vector(7 downto 0) := "10101100"; -- AC
constant S2MM_STARTADDR2_OFFSET_8 : std_logic_vector(7 downto 0) := "10110000"; -- B0
constant S2MM_STARTADDR3_OFFSET_8 : std_logic_vector(7 downto 0) := "10110100"; -- B4
constant S2MM_STARTADDR4_OFFSET_8 : std_logic_vector(7 downto 0) := "10111000"; -- B8
constant S2MM_STARTADDR5_OFFSET_8 : std_logic_vector(7 downto 0) := "10111100"; -- BC
constant S2MM_STARTADDR6_OFFSET_8 : std_logic_vector(7 downto 0) := "11000000"; -- C0
constant S2MM_STARTADDR7_OFFSET_8 : std_logic_vector(7 downto 0) := "11000100"; -- C4
constant S2MM_STARTADDR8_OFFSET_8 : std_logic_vector(7 downto 0) := "11001000"; -- C8
constant S2MM_STARTADDR9_OFFSET_8 : std_logic_vector(7 downto 0) := "11001100"; -- CC
constant S2MM_STARTADDR10_OFFSET_8 : std_logic_vector(7 downto 0) := "11010000"; -- D0
constant S2MM_STARTADDR11_OFFSET_8 : std_logic_vector(7 downto 0) := "11010100"; -- D4
constant S2MM_STARTADDR12_OFFSET_8 : std_logic_vector(7 downto 0) := "11011000"; -- D8
constant S2MM_STARTADDR13_OFFSET_8 : std_logic_vector(7 downto 0) := "11011100"; -- DC
constant S2MM_STARTADDR14_OFFSET_8 : std_logic_vector(7 downto 0) := "11100000"; -- E0
constant S2MM_STARTADDR15_OFFSET_8 : std_logic_vector(7 downto 0) := "11100100"; -- E4
constant S2MM_STARTADDR16_OFFSET_8 : std_logic_vector(7 downto 0) := "11101000"; -- E8
constant S2MM_STARTADDR1_OFFSET_90 : std_logic_vector(8 downto 0) := "010101100"; -- 0AC
constant S2MM_STARTADDR2_OFFSET_90 : std_logic_vector(8 downto 0) := "010110000"; -- 0B0
constant S2MM_STARTADDR3_OFFSET_90 : std_logic_vector(8 downto 0) := "010110100"; -- 0B4
constant S2MM_STARTADDR4_OFFSET_90 : std_logic_vector(8 downto 0) := "010111000"; -- 0B8
constant S2MM_STARTADDR5_OFFSET_90 : std_logic_vector(8 downto 0) := "010111100"; -- 0BC
constant S2MM_STARTADDR6_OFFSET_90 : std_logic_vector(8 downto 0) := "011000000"; -- 0C0
constant S2MM_STARTADDR7_OFFSET_90 : std_logic_vector(8 downto 0) := "011000100"; -- 0C4
constant S2MM_STARTADDR8_OFFSET_90 : std_logic_vector(8 downto 0) := "011001000"; -- 0C8
constant S2MM_STARTADDR9_OFFSET_90 : std_logic_vector(8 downto 0) := "011001100"; -- 0CC
constant S2MM_STARTADDR10_OFFSET_90 : std_logic_vector(8 downto 0) := "011010000"; -- 0D0
constant S2MM_STARTADDR11_OFFSET_90 : std_logic_vector(8 downto 0) := "011010100"; -- 0D4
constant S2MM_STARTADDR12_OFFSET_90 : std_logic_vector(8 downto 0) := "011011000"; -- 0D8
constant S2MM_STARTADDR13_OFFSET_90 : std_logic_vector(8 downto 0) := "011011100"; -- 0DC
constant S2MM_STARTADDR14_OFFSET_90 : std_logic_vector(8 downto 0) := "011100000"; -- 0E0
constant S2MM_STARTADDR15_OFFSET_90 : std_logic_vector(8 downto 0) := "011100100"; -- 0E4
constant S2MM_STARTADDR16_OFFSET_90 : std_logic_vector(8 downto 0) := "011101000"; -- 0E8
constant RESERVED_EC_OFFSET : std_logic_vector(8 downto 0) := "011101100"; -- 0EC
constant RESERVED_F0_OFFSET : std_logic_vector(8 downto 0) := "011110000"; -- 0F0
constant RESERVED_F4_OFFSET : std_logic_vector(8 downto 0) := "011110100"; -- 0F4
constant RESERVED_F8_OFFSET : std_logic_vector(8 downto 0) := "011111000"; -- 0F8
constant RESERVED_FC_OFFSET : std_logic_vector(8 downto 0) := "011111100"; -- 0FC
constant RESERVED_100_OFFSET : std_logic_vector(8 downto 0) := "100000000"; -- 100
constant RESERVED_104_OFFSET : std_logic_vector(8 downto 0) := "100000100"; -- 104
constant RESERVED_108_OFFSET : std_logic_vector(8 downto 0) := "100001000"; -- 108
constant RESERVED_10C_OFFSET : std_logic_vector(8 downto 0) := "100001100"; -- 10C
constant RESERVED_110_OFFSET : std_logic_vector(8 downto 0) := "100010000"; -- 110
constant RESERVED_114_OFFSET : std_logic_vector(8 downto 0) := "100010100"; -- 114
constant RESERVED_118_OFFSET : std_logic_vector(8 downto 0) := "100011000"; -- 118
constant RESERVED_11C_OFFSET : std_logic_vector(8 downto 0) := "100011100"; -- 11C
constant RESERVED_120_OFFSET : std_logic_vector(8 downto 0) := "100100000"; -- 120
constant RESERVED_124_OFFSET : std_logic_vector(8 downto 0) := "100100100"; -- 124
constant RESERVED_128_OFFSET : std_logic_vector(8 downto 0) := "100101000"; -- 128
constant RESERVED_12C_OFFSET : std_logic_vector(8 downto 0) := "100101100"; -- 12C
constant RESERVED_130_OFFSET : std_logic_vector(8 downto 0) := "100110000"; -- 130
constant RESERVED_134_OFFSET : std_logic_vector(8 downto 0) := "100110100"; -- 134
constant RESERVED_138_OFFSET : std_logic_vector(8 downto 0) := "100111000"; -- 138
constant RESERVED_13C_OFFSET : std_logic_vector(8 downto 0) := "100111100"; -- 13C
constant RESERVED_140_OFFSET : std_logic_vector(8 downto 0) := "101000000"; -- 140
constant RESERVED_144_OFFSET : std_logic_vector(8 downto 0) := "101000100"; -- 144
constant RESERVED_148_OFFSET : std_logic_vector(8 downto 0) := "101001000"; -- 148
constant RESERVED_14C_OFFSET : std_logic_vector(8 downto 0) := "101001100"; -- 14C
constant RESERVED_150_OFFSET : std_logic_vector(8 downto 0) := "101010000"; -- 150
constant RESERVED_154_OFFSET : std_logic_vector(8 downto 0) := "101010100"; -- 154
constant RESERVED_158_OFFSET : std_logic_vector(8 downto 0) := "101011000"; -- 158
constant MM2S_STARTADDR17_OFFSET_91 : std_logic_vector(8 downto 0) := "101011100"; -- 15C
constant MM2S_STARTADDR18_OFFSET_91 : std_logic_vector(8 downto 0) := "101100000"; -- 160
constant MM2S_STARTADDR19_OFFSET_91 : std_logic_vector(8 downto 0) := "101100100"; -- 164
constant MM2S_STARTADDR20_OFFSET_91 : std_logic_vector(8 downto 0) := "101101000"; -- 168
constant MM2S_STARTADDR21_OFFSET_91 : std_logic_vector(8 downto 0) := "101101100"; -- 16C
constant MM2S_STARTADDR22_OFFSET_91 : std_logic_vector(8 downto 0) := "101110000"; -- 170
constant MM2S_STARTADDR23_OFFSET_91 : std_logic_vector(8 downto 0) := "101110100"; -- 174
constant MM2S_STARTADDR24_OFFSET_91 : std_logic_vector(8 downto 0) := "101111000"; -- 178
constant MM2S_STARTADDR25_OFFSET_91 : std_logic_vector(8 downto 0) := "101111100"; -- 17C
constant MM2S_STARTADDR26_OFFSET_91 : std_logic_vector(8 downto 0) := "110000000"; -- 180
constant MM2S_STARTADDR27_OFFSET_91 : std_logic_vector(8 downto 0) := "110000100"; -- 184
constant MM2S_STARTADDR28_OFFSET_91 : std_logic_vector(8 downto 0) := "110001000"; -- 188
constant MM2S_STARTADDR29_OFFSET_91 : std_logic_vector(8 downto 0) := "110001100"; -- 18C
constant MM2S_STARTADDR30_OFFSET_91 : std_logic_vector(8 downto 0) := "110010000"; -- 190
constant MM2S_STARTADDR31_OFFSET_91 : std_logic_vector(8 downto 0) := "110010100"; -- 194
constant MM2S_STARTADDR32_OFFSET_91 : std_logic_vector(8 downto 0) := "110011000"; -- 198
constant RESERVED_19C_OFFSET : std_logic_vector(8 downto 0) := "110011100"; -- 19C
constant RESERVED_1A0_OFFSET : std_logic_vector(8 downto 0) := "110100000"; -- 1A0
constant RESERVED_1A4_OFFSET : std_logic_vector(8 downto 0) := "110100100"; -- 1A4
constant RESERVED_1A8_OFFSET : std_logic_vector(8 downto 0) := "110101000"; -- 1A8
constant S2MM_STARTADDR17_OFFSET_91 : std_logic_vector(8 downto 0) := "110101100"; -- 1AC
constant S2MM_STARTADDR18_OFFSET_91 : std_logic_vector(8 downto 0) := "110110000"; -- 1B0
constant S2MM_STARTADDR19_OFFSET_91 : std_logic_vector(8 downto 0) := "110110100"; -- 1B4
constant S2MM_STARTADDR20_OFFSET_91 : std_logic_vector(8 downto 0) := "110111000"; -- 1B8
constant S2MM_STARTADDR21_OFFSET_91 : std_logic_vector(8 downto 0) := "110111100"; -- 1BC
constant S2MM_STARTADDR22_OFFSET_91 : std_logic_vector(8 downto 0) := "111000000"; -- 1C0
constant S2MM_STARTADDR23_OFFSET_91 : std_logic_vector(8 downto 0) := "111000100"; -- 1C4
constant S2MM_STARTADDR24_OFFSET_91 : std_logic_vector(8 downto 0) := "111001000"; -- 1C8
constant S2MM_STARTADDR25_OFFSET_91 : std_logic_vector(8 downto 0) := "111001100"; -- 1CC
constant S2MM_STARTADDR26_OFFSET_91 : std_logic_vector(8 downto 0) := "111010000"; -- 1D0
constant S2MM_STARTADDR27_OFFSET_91 : std_logic_vector(8 downto 0) := "111010100"; -- 1D4
constant S2MM_STARTADDR28_OFFSET_91 : std_logic_vector(8 downto 0) := "111011000"; -- 1D8
constant S2MM_STARTADDR29_OFFSET_91 : std_logic_vector(8 downto 0) := "111011100"; -- 1DC
constant S2MM_STARTADDR30_OFFSET_91 : std_logic_vector(8 downto 0) := "111100000"; -- 1E0
constant S2MM_STARTADDR31_OFFSET_91 : std_logic_vector(8 downto 0) := "111100100"; -- 1E4
constant S2MM_STARTADDR32_OFFSET_91 : std_logic_vector(8 downto 0) := "111101000"; -- 1E8
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RS_BIT : integer := 0;
constant DMACR_CRCLPRK_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_SYNCEN_BIT : integer := 3;
constant DMACR_FRMCNTEN_BIT : integer := 4;
constant DMACR_FSYNCSEL_LSB : integer := 5;
constant DMACR_FSYNCSEL_MSB : integer := 6;
constant DMACR_GENLOCK_SEL_BIT : integer := 7;
constant DMACR_PNTR_NUM_LSB : integer := 8;
constant DMACR_PNTR_NUM_MSB : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
--constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_REPEAT_EN_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_RESERVED2_BIT : integer := 2;
constant DMASR_ERR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_FSIZEERR_BIT : integer := 7;
constant DMASR_LSIZEERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
--constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_FSIZE_MORE_OR_SOF_LATE_ERR_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_LSIZE_MORE_ERR_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
constant PARKPTR_FRMSTR_RSVD_BIT31 : integer := 31;
constant PARKPTR_FRMSTR_S2MM_MSB_BIT : integer := 28;
constant PARKPTR_FRMSTR_S2MM_LSB_BIT : integer := 24;
constant PARKPTR_FRMSTR_MM2S_MSB_BIT : integer := 20;
constant PARKPTR_FRMSTR_MM2S_LSB_BIT : integer := 16;
constant PARKPTR_FRMSTR_RSVD_BIT15 : integer := 15;
constant PARKPTR_FRMPTR_S2MM_MSB_BIT : integer := 12;
constant PARKPTR_FRMPTR_S2MM_LSB_BIT : integer := 8;
constant PARKPTR_FRMPTR_MM2S_MSB_BIT : integer := 4;
constant PARKPTR_FRMPTR_MM2S_LSB_BIT : integer := 0;
-- FRAMESTORE
constant FRMSTORE_LSB_BIT : integer := 0;
constant FRMSTORE_MSB_BIT : integer := NUM_FRM_STORE_WIDTH-1;
-- LineBuffer Threshold
constant THRESH_LSB_BIT : integer := 0;
constant THRESH_MSB_BIT : integer := LINEBUFFER_THRESH_WIDTH-1;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Word 0 : NXTDESC PTR LS-WORD
-- Descriptor Word 1 : NXTDESC PTR MS-WORD
-- Descriptor Word 2 : STARTADDR PTR LS-WORD
-- Descriptor Word 3 : STARTADDR PTR MS-WORD
-- Descriptor Word 4
constant DESC_WRD4_VSIZE_LSB_BIT : integer := 0;
constant DESC_WRD4_VSIZE_MSB_BIT : integer := 12;
-- Descriptor Word 5
constant DESC_WRD5_HSIZE_LSB_BIT : integer := 0;
constant DESC_WRD5_HSIZE_MSB_BIT : integer := 15;
-- Descriptor Word 6
constant DESC_WRD6_STRIDE_LSB_BIT : integer := 0;
constant DESC_WRD6_STRIDE_MSB_BIT : integer := 15;
constant DESC_WRD6_FRMDLY_LSB_BIT : integer := 24;
constant DESC_WRD6_FRMDLY_MSB_BIT : integer := 28;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
-- Gen-Lock constants
constant MSTR0 : std_logic_vector(3 downto 0) := "0000";
constant MSTR1 : std_logic_vector(3 downto 0) := "0001";
constant MSTR2 : std_logic_vector(3 downto 0) := "0010";
constant MSTR3 : std_logic_vector(3 downto 0) := "0011";
constant MSTR4 : std_logic_vector(3 downto 0) := "0100";
constant MSTR5 : std_logic_vector(3 downto 0) := "0101";
constant MSTR6 : std_logic_vector(3 downto 0) := "0110";
constant MSTR7 : std_logic_vector(3 downto 0) := "0111";
constant MSTR8 : std_logic_vector(3 downto 0) := "1000";
constant MSTR9 : std_logic_vector(3 downto 0) := "1001";
constant MSTR10 : std_logic_vector(3 downto 0) := "1010";
constant MSTR11 : std_logic_vector(3 downto 0) := "1011";
constant MSTR12 : std_logic_vector(3 downto 0) := "1100";
constant MSTR13 : std_logic_vector(3 downto 0) := "1101";
constant MSTR14 : std_logic_vector(3 downto 0) := "1110";
constant MSTR15 : std_logic_vector(3 downto 0) := "1111";
constant MSTR0_LO_INDEX : integer := 0;
constant MSTR0_HI_INDEX : integer := 5;
constant MSTR1_LO_INDEX : integer := 6;
constant MSTR1_HI_INDEX : integer := 11;
constant MSTR2_LO_INDEX : integer := 12;
constant MSTR2_HI_INDEX : integer := 17;
constant MSTR3_LO_INDEX : integer := 18;
constant MSTR3_HI_INDEX : integer := 23;
constant MSTR4_LO_INDEX : integer := 24;
constant MSTR4_HI_INDEX : integer := 29;
constant MSTR5_LO_INDEX : integer := 30;
constant MSTR5_HI_INDEX : integer := 35;
constant MSTR6_LO_INDEX : integer := 36;
constant MSTR6_HI_INDEX : integer := 41;
constant MSTR7_LO_INDEX : integer := 42;
constant MSTR7_HI_INDEX : integer := 47;
constant MSTR8_LO_INDEX : integer := 48;
constant MSTR8_HI_INDEX : integer := 53;
constant MSTR9_LO_INDEX : integer := 54;
constant MSTR9_HI_INDEX : integer := 59;
constant MSTR10_LO_INDEX : integer := 60;
constant MSTR10_HI_INDEX : integer := 65;
constant MSTR11_LO_INDEX : integer := 66;
constant MSTR11_HI_INDEX : integer := 71;
constant MSTR12_LO_INDEX : integer := 72;
constant MSTR12_HI_INDEX : integer := 77;
constant MSTR13_LO_INDEX : integer := 78;
constant MSTR13_HI_INDEX : integer := 83;
constant MSTR14_LO_INDEX : integer := 84;
constant MSTR14_HI_INDEX : integer := 89;
constant MSTR15_LO_INDEX : integer := 90;
constant MSTR15_HI_INDEX : integer := 95;
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
constant BITS_PER_REG : integer := 32;
constant BITS_PER_REG_64 : integer := 64;
type STARTADDR_ARRAY_TYPE is array(natural range <>)
of std_logic_vector(BITS_PER_REG - 1 downto 0);
type STARTADDR_ARRAY_TYPE_64 is array(natural range <>)
of std_logic_vector(BITS_PER_REG_64 - 1 downto 0);
end axi_vdma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_vdma_pkg is
-- coverage off
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width (dwidth : integer;
burst_size : integer;
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width;
-------------------------------------------------------------------------------
-- String to Integer Function
-------------------------------------------------------------------------------
function string2int(strngbuf: string)
return integer is
variable result : integer := 0;
begin
for i in 1 to strngbuf'length loop
case strngbuf(i) is
when '0' => result := result*10;
when '1' => result := result*10 + 1;
when '2' => result := result*10 + 2;
when '3' => result := result*10 + 3;
when '4' => result := result*10 + 4;
when '5' => result := result*10 + 5;
when '6' => result := result*10 + 6;
when '7' => result := result*10 + 7;
when '8' => result := result*10 + 8;
when '9' => result := result*10 + 9;
-- coverage off
when others => null;
-- coverage on
end case;
end loop;
return result;
end;
--------------------------------------------------------------------------------
--Channel Fsync & Flush decoding
--------------------------------------------------------------------------------
function find_mm2s_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 0 or use_fsync = 1)then
return use_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 or use_fsync = 2) then
return 1;
-- coverage off
else
return 0;
-- coverage on
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_mm2s_fsync;
function find_s2mm_fsync_01 (use_s2mm_fsync : integer)
return integer is
begin
if (use_s2mm_fsync = 1 or use_s2mm_fsync = 2)then
return 1;
else
return 0;
end if;
end function find_s2mm_fsync_01;
function find_s2mm_fsync (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 0 or use_fsync = 1)then
return use_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 or use_fsync = 3) then
return 1;
-- coverage off
else
return 0;
-- coverage on
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_s2mm_fsync;
function find_mm2s_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 1 and (flush_on_fsync = 0 or flush_on_fsync = 1)) then
return flush_on_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 and ( flush_on_fsync = 1 or flush_on_fsync = 2))then
return 1;
elsif (use_fsync = 2 and flush_on_fsync = 2)then
return 1;
else
return 0;
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_mm2s_flush;
function find_s2mm_flush (use_fsync : integer;
mm2s_included : integer;
s2mm_included : integer;
flush_on_fsync : integer)
return integer is
begin
if ((mm2s_included = 0 and s2mm_included = 1) or (mm2s_included = 1 and s2mm_included = 0)) then
if (use_fsync = 1 and (flush_on_fsync = 0 or flush_on_fsync = 1)) then
return flush_on_fsync;
else
return 0;
end if;
elsif(mm2s_included = 1 and s2mm_included = 1) then
if (use_fsync = 1 and ( flush_on_fsync = 1 or flush_on_fsync = 3))then
return 1;
elsif (use_fsync = 3 and flush_on_fsync = 3)then
return 1;
else
return 0;
end if;
elsif(mm2s_included = 0 and s2mm_included = 0) then
return 0;
-- coverage off
else
return 0;
-- coverage on
end if;
end function find_s2mm_flush;
-- coverage on
----------------------------------------------------------------------------------------------------------
-- Function to calculate minimum threshold value for MM2S Line buffer based on TDATA, and LineBuffer Depth
----------------------------------------------------------------------------------------------------------
function calculated_minimum_mm2s_linebuffer_thresh (mm2s_included : integer; mm2s_tdata_dwidth : integer; mm2s_linebuffer_depth : integer)
return integer is
begin
if(mm2s_included = 0 or mm2s_linebuffer_depth = 0)then
return 4;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 8) then
return 1;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 16) then
return 2;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 32) then
return 4;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 64) then
return 8;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 128) then
return 16;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 256) then
return 32;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 512) then
return 64;
elsif(mm2s_included = 1 and mm2s_linebuffer_depth > 0 and mm2s_tdata_dwidth = 1024) then
return 128;
-- coverage off
else
return 128 ;
-- coverage on
end if;
end function calculated_minimum_mm2s_linebuffer_thresh;
function calculated_minimum_s2mm_linebuffer_thresh (s2mm_included : integer; s2mm_tdata_dwidth : integer; s2mm_linebuffer_depth : integer)
return integer is
begin
if(s2mm_included = 0 or s2mm_linebuffer_depth = 0)then
return 4;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 8) then
return 1;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 16) then
return 2;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 32) then
return 4;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 64) then
return 8;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 128) then
return 16;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 256) then
return 32;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 512) then
return 64;
elsif(s2mm_included = 1 and s2mm_linebuffer_depth > 0 and s2mm_tdata_dwidth = 1024) then
return 128;
-- coverage off
else
return 128 ;
-- coverage on
end if;
end function calculated_minimum_s2mm_linebuffer_thresh;
-------------------------------------------------------------------------------
-- Function to calculate C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED from C_M_AXIS_MM2S_TDATA_WIDTH
-------------------------------------------------------------------------------
function calculated_mm2s_tdata_width (mm2s_tdata_dwidth : integer)
return integer is
begin
if(mm2s_tdata_dwidth <= 16)then
return mm2s_tdata_dwidth;
elsif(mm2s_tdata_dwidth > 16 and mm2s_tdata_dwidth <= 32) then
return 32;
elsif(mm2s_tdata_dwidth > 32 and mm2s_tdata_dwidth <= 64) then
return 64;
elsif(mm2s_tdata_dwidth > 64 and mm2s_tdata_dwidth <= 128) then
return 128;
elsif(mm2s_tdata_dwidth > 128 and mm2s_tdata_dwidth <= 256) then
return 256;
elsif(mm2s_tdata_dwidth > 256 and mm2s_tdata_dwidth <= 512) then
return 512;
elsif(mm2s_tdata_dwidth > 512 and mm2s_tdata_dwidth <= 1024) then
return 1024;
-- coverage off
else
return 32 ;
-- coverage on
end if;
end function calculated_mm2s_tdata_width;
function calculated_s2mm_tdata_width (s2mm_tdata_dwidth : integer)
return integer is
begin
if(s2mm_tdata_dwidth <= 16)then
return s2mm_tdata_dwidth;
elsif(s2mm_tdata_dwidth > 16 and s2mm_tdata_dwidth <= 32) then
return 32;
elsif(s2mm_tdata_dwidth > 32 and s2mm_tdata_dwidth <= 64) then
return 64;
elsif(s2mm_tdata_dwidth > 64 and s2mm_tdata_dwidth <= 128) then
return 128;
elsif(s2mm_tdata_dwidth > 128 and s2mm_tdata_dwidth <= 256) then
return 256;
elsif(s2mm_tdata_dwidth > 256 and s2mm_tdata_dwidth <= 512) then
return 512;
elsif(s2mm_tdata_dwidth > 512 and s2mm_tdata_dwidth <= 1024) then
return 1024;
-- coverage off
else
return 32 ;
-- coverage on
end if;
end function calculated_s2mm_tdata_width;
function enable_tkeep_connectivity (tdata_dwidth : integer; tdata_width_calculated : integer; DRE_ON : integer)
return integer is
begin
if(DRE_ON = 1 or ( tdata_width_calculated /= tdata_dwidth))then
return 1;
else
return 0 ;
end if;
end function enable_tkeep_connectivity;
-------------------------------------------------------------------------------
-- function to return number of registers depending on mode of operation
-------------------------------------------------------------------------------
function get_num_registers(mode : integer;
sg_num : integer;
regdir_num : integer)
return integer is
begin
-- 1 = Scatter Gather Mode
-- 0 = Register Direct Mode
if(mode = 1)then
return sg_num;
else
return regdir_num;
end if;
end;
-- coverage off
-------------------------------------------------------------------------------
-- function to return Frequency Hertz parameter based on inclusion of sg engine
-------------------------------------------------------------------------------
function hertz_prmtr_select(included : integer;
lite_frequency : integer;
sg_frequency : integer)
return integer is
begin
-- 1 = Scatter Gather Included
-- 0 = Scatter Gather Excluded
if(included = 1)then
return sg_frequency;
else
return lite_frequency;
end if;
end;
-- coverage on
-------------------------------------------------------------------------------
-- function to enable store and forward based on data width mismatch
-- or directly enabled
-------------------------------------------------------------------------------
function enable_snf (sf_enabled : integer;
axi_data_width : integer;
axis_tdata_width : integer)
return integer is
begin
-- If store and forward enable or data widths do not
-- match then return 1 to enable snf
if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then
return 1;
else
return 0;
end if;
end;
-------------------------------------------------------------------------------
-- Convert mm2s index to an s2mm index for the base registers
-------------------------------------------------------------------------------
function convert_base_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer is
variable new_index : integer := 0;
begin
if(channel_is_mm2s = 1)then
return mm2s_index;
else
new_index := mm2s_index + 12;
return new_index;
end if;
end;
-------------------------------------------------------------------------------
-- Convert mm2s index to an s2mm index for the regdir registers
-------------------------------------------------------------------------------
function convert_regdir_index(channel_is_mm2s : integer;
mm2s_index : integer)
return integer is
variable new_index : integer := 0;
begin
if(channel_is_mm2s = 1)then
return mm2s_index;
else
--new_index := mm2s_index + 68;
new_index := mm2s_index + 20;
return new_index;
end if;
end;
-------------------------------------------------------------------------------
-- enable internal genlock bus based on genlock modes and internal genlock
-- parameters.
-------------------------------------------------------------------------------
function enable_internal_genloc(mm2s_enabled : integer;
s2mm_enabled : integer;
internal_genlock : integer;
mm2s_genlock_mode : integer;
s2mm_genlock_mode : integer)
return integer is
begin
-- internal genlock turned OFF at parameter or if NOT both channel enabled.
if(internal_genlock = 0 or mm2s_enabled = 0 or s2mm_enabled = 0)then
return 0;
-- at least one channel must be a master and one be a slave
-- before turning ON the internal genlock bus
elsif( (mm2s_genlock_mode = 0 and s2mm_genlock_mode = 1)
or (mm2s_genlock_mode = 1 and s2mm_genlock_mode = 0))then
return 1;
elsif( (mm2s_genlock_mode = 2 and s2mm_genlock_mode = 3)
or (mm2s_genlock_mode = 3 and s2mm_genlock_mode = 2))then
return 1;
-- either both are maters or both are slaves therefore
-- turn OFF internal genlock bus
else
return 0;
end if;
end;
end package body axi_vdma_pkg;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_demux.vhd
|
18
|
75691
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_demux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_demux.vhd
--
-- Description:
-- This file implements the DataMover Master Write Strobe De-Multiplexer.
-- This is needed when the native data width of the DataMover is narrower
-- than the AXI4 Write Data Channel.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Write Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the native data width of the DataMover S2MM. If
-- S2MM Store and Forward with upsizer is enabled, the width is
-- the AXi4 Write Data Channel, else it is the S2MM Stream data width.
);
port (
-- AXI MMap Data Channel Input --------------------------------------------
--
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- data input --
----------------------------------------------------------------------------
-- AXI Master Stream ------------------------------------------------------
--
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
--De-Mux strb output --
----------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------
--
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
----------------------------------------------------------------------------
);
end entity axi_datamover_wr_demux;
architecture implementation of axi_datamover_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
--when 2 =>
-- var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 1;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- assume 1024 bit width
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH);
Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX);
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when others => -- 1 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when others => -- 3 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when others => -- 7 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when others => -- 15 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when others => -- 31 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel demux case
--
--
------------------------------------------------------------
GEN_64XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_64XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when others => -- 63 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
end case;
end process DO_64XN_DEMUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel demux case
--
--
------------------------------------------------------------
GEN_128XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_128XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when 63 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
when 64 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*65)-1 downto STREAM_WSTB_WIDTH*64) <= wstrb_in;
when 65 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*66)-1 downto STREAM_WSTB_WIDTH*65) <= wstrb_in;
when 66 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*67)-1 downto STREAM_WSTB_WIDTH*66) <= wstrb_in;
when 67 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*68)-1 downto STREAM_WSTB_WIDTH*67) <= wstrb_in;
when 68 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*69)-1 downto STREAM_WSTB_WIDTH*68) <= wstrb_in;
when 69 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*70)-1 downto STREAM_WSTB_WIDTH*69) <= wstrb_in;
when 70 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*71)-1 downto STREAM_WSTB_WIDTH*70) <= wstrb_in;
when 71 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*72)-1 downto STREAM_WSTB_WIDTH*71) <= wstrb_in;
when 72 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*73)-1 downto STREAM_WSTB_WIDTH*72) <= wstrb_in;
when 73 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*74)-1 downto STREAM_WSTB_WIDTH*73) <= wstrb_in;
when 74 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*75)-1 downto STREAM_WSTB_WIDTH*74) <= wstrb_in;
when 75 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*76)-1 downto STREAM_WSTB_WIDTH*75) <= wstrb_in;
when 76 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*77)-1 downto STREAM_WSTB_WIDTH*76) <= wstrb_in;
when 77 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*78)-1 downto STREAM_WSTB_WIDTH*77) <= wstrb_in;
when 78 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*79)-1 downto STREAM_WSTB_WIDTH*78) <= wstrb_in;
when 79 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*80)-1 downto STREAM_WSTB_WIDTH*79) <= wstrb_in;
when 80 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*81)-1 downto STREAM_WSTB_WIDTH*80) <= wstrb_in;
when 81 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*82)-1 downto STREAM_WSTB_WIDTH*81) <= wstrb_in;
when 82 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*83)-1 downto STREAM_WSTB_WIDTH*82) <= wstrb_in;
when 83 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*84)-1 downto STREAM_WSTB_WIDTH*83) <= wstrb_in;
when 84 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*85)-1 downto STREAM_WSTB_WIDTH*84) <= wstrb_in;
when 85 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*86)-1 downto STREAM_WSTB_WIDTH*85) <= wstrb_in;
when 86 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*87)-1 downto STREAM_WSTB_WIDTH*86) <= wstrb_in;
when 87 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*88)-1 downto STREAM_WSTB_WIDTH*87) <= wstrb_in;
when 88 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*89)-1 downto STREAM_WSTB_WIDTH*88) <= wstrb_in;
when 89 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*90)-1 downto STREAM_WSTB_WIDTH*89) <= wstrb_in;
when 90 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*91)-1 downto STREAM_WSTB_WIDTH*90) <= wstrb_in;
when 91 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*92)-1 downto STREAM_WSTB_WIDTH*91) <= wstrb_in;
when 92 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*93)-1 downto STREAM_WSTB_WIDTH*92) <= wstrb_in;
when 93 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*94)-1 downto STREAM_WSTB_WIDTH*93) <= wstrb_in;
when 94 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*95)-1 downto STREAM_WSTB_WIDTH*94) <= wstrb_in;
when 95 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*96)-1 downto STREAM_WSTB_WIDTH*95) <= wstrb_in;
when 96 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*97 )-1 downto STREAM_WSTB_WIDTH*96 ) <= wstrb_in;
when 97 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*98 )-1 downto STREAM_WSTB_WIDTH*97 ) <= wstrb_in;
when 98 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*99 )-1 downto STREAM_WSTB_WIDTH*98 ) <= wstrb_in;
when 99 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*100)-1 downto STREAM_WSTB_WIDTH*99 ) <= wstrb_in;
when 100 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*101)-1 downto STREAM_WSTB_WIDTH*100) <= wstrb_in;
when 101 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*102)-1 downto STREAM_WSTB_WIDTH*101) <= wstrb_in;
when 102 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*103)-1 downto STREAM_WSTB_WIDTH*102) <= wstrb_in;
when 103 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*104)-1 downto STREAM_WSTB_WIDTH*103) <= wstrb_in;
when 104 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*105)-1 downto STREAM_WSTB_WIDTH*104) <= wstrb_in;
when 105 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*106)-1 downto STREAM_WSTB_WIDTH*105) <= wstrb_in;
when 106 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*107)-1 downto STREAM_WSTB_WIDTH*106) <= wstrb_in;
when 107 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*108)-1 downto STREAM_WSTB_WIDTH*107) <= wstrb_in;
when 108 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*109)-1 downto STREAM_WSTB_WIDTH*108) <= wstrb_in;
when 109 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*110)-1 downto STREAM_WSTB_WIDTH*109) <= wstrb_in;
when 110 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*111)-1 downto STREAM_WSTB_WIDTH*110) <= wstrb_in;
when 111 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*112)-1 downto STREAM_WSTB_WIDTH*111) <= wstrb_in;
when 112 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*113)-1 downto STREAM_WSTB_WIDTH*112) <= wstrb_in;
when 113 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*114)-1 downto STREAM_WSTB_WIDTH*113) <= wstrb_in;
when 114 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*115)-1 downto STREAM_WSTB_WIDTH*114) <= wstrb_in;
when 115 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*116)-1 downto STREAM_WSTB_WIDTH*115) <= wstrb_in;
when 116 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*117)-1 downto STREAM_WSTB_WIDTH*116) <= wstrb_in;
when 117 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*118)-1 downto STREAM_WSTB_WIDTH*117) <= wstrb_in;
when 118 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*119)-1 downto STREAM_WSTB_WIDTH*118) <= wstrb_in;
when 119 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*120)-1 downto STREAM_WSTB_WIDTH*119) <= wstrb_in;
when 120 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*121)-1 downto STREAM_WSTB_WIDTH*120) <= wstrb_in;
when 121 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*122)-1 downto STREAM_WSTB_WIDTH*121) <= wstrb_in;
when 122 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*123)-1 downto STREAM_WSTB_WIDTH*122) <= wstrb_in;
when 123 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*124)-1 downto STREAM_WSTB_WIDTH*123) <= wstrb_in;
when 124 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*125)-1 downto STREAM_WSTB_WIDTH*124) <= wstrb_in;
when 125 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*126)-1 downto STREAM_WSTB_WIDTH*125) <= wstrb_in;
when 126 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*127)-1 downto STREAM_WSTB_WIDTH*126) <= wstrb_in;
when others => -- 127 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*128)-1 downto STREAM_WSTB_WIDTH*127) <= wstrb_in;
end case;
end process DO_128XN_DEMUX;
end generate GEN_128XN;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_demux.vhd
|
18
|
75691
|
-------------------------------------------------------------------------------
-- axi_datamover_wr_demux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wr_demux.vhd
--
-- Description:
-- This file implements the DataMover Master Write Strobe De-Multiplexer.
-- This is needed when the native data width of the DataMover is narrower
-- than the AXI4 Write Data Channel.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_wr_demux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Write Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the native data width of the DataMover S2MM. If
-- S2MM Store and Forward with upsizer is enabled, the width is
-- the AXi4 Write Data Channel, else it is the S2MM Stream data width.
);
port (
-- AXI MMap Data Channel Input --------------------------------------------
--
wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- data input --
----------------------------------------------------------------------------
-- AXI Master Stream ------------------------------------------------------
--
demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
--De-Mux strb output --
----------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------
--
debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
----------------------------------------------------------------------------
);
end entity axi_datamover_wr_demux;
architecture implementation of axi_datamover_wr_demux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
--when 2 =>
-- var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 1;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (stream_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case stream_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- assume 1024 bit width
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH);
Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX);
Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8;
Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
demux_wstrb_out <= sig_demux_wstrb_out;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memeory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate
begin
sig_demux_wstrb_out <= wstrb_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel demux case
--
--
------------------------------------------------------------
GEN_2XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_DEMUX
--
-- Process Description:
-- Implement the 2XN DeMux
--
-------------------------------------------------------------
DO_2XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when others => -- 1 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
end case;
end process DO_2XN_DEMUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel demux case
--
--
------------------------------------------------------------
GEN_4XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_DEMUX
--
-- Process Description:
-- Implement the 4XN DeMux
--
-------------------------------------------------------------
DO_4XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when others => -- 3 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
end case;
end process DO_4XN_DEMUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel demux case
--
--
------------------------------------------------------------
GEN_8XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_DEMUX
--
-- Process Description:
-- Implement the 8XN DeMux
--
-------------------------------------------------------------
DO_8XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when others => -- 7 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
end case;
end process DO_8XN_DEMUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel demux case
--
--
------------------------------------------------------------
GEN_16XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_DEMUX
--
-- Process Description:
-- Implement the 16XN DeMux
--
-------------------------------------------------------------
DO_16XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when others => -- 15 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
end case;
end process DO_16XN_DEMUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel demux case
--
--
------------------------------------------------------------
GEN_32XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_32XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when others => -- 31 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
end case;
end process DO_32XN_DEMUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel demux case
--
--
------------------------------------------------------------
GEN_64XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_64XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when others => -- 63 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
end case;
end process DO_64XN_DEMUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel demux case
--
--
------------------------------------------------------------
GEN_128XN : if (INCLUDE_DEMUX and
NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_demux_sel_int : integer := 0;
signal lsig_demux_sel_int_local : integer := 0;
signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned
sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
lsig_demux_sel_int_local <= sig_demux_sel_int;
sig_demux_wstrb_out <= lsig_demux_wstrb_out;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_DEMUX
--
-- Process Description:
-- Implement the 32XN DeMux
--
-------------------------------------------------------------
DO_128XN_DEMUX : process (lsig_demux_sel_int_local,
wstrb_in)
begin
-- Set default value
lsig_demux_wstrb_out <= (others => '0');
case lsig_demux_sel_int_local is
when 0 =>
lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in;
when 1 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in;
when 2 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in;
when 3 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in;
when 4 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in;
when 5 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in;
when 6 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in;
when 7 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in;
when 8 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in;
when 9 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in;
when 10 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in;
when 11 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in;
when 12 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in;
when 13 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in;
when 14 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in;
when 15 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in;
when 16 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in;
when 17 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in;
when 18 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in;
when 19 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in;
when 20 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in;
when 21 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in;
when 22 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in;
when 23 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in;
when 24 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in;
when 25 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in;
when 26 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in;
when 27 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in;
when 28 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in;
when 29 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in;
when 30 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in;
when 31 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in;
when 32 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in;
when 33 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in;
when 34 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in;
when 35 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in;
when 36 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in;
when 37 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in;
when 38 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in;
when 39 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in;
when 40 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in;
when 41 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in;
when 42 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in;
when 43 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in;
when 44 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in;
when 45 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in;
when 46 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in;
when 47 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in;
when 48 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in;
when 49 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in;
when 50 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in;
when 51 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in;
when 52 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in;
when 53 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in;
when 54 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in;
when 55 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in;
when 56 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in;
when 57 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in;
when 58 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in;
when 59 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in;
when 60 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in;
when 61 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in;
when 62 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in;
when 63 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in;
when 64 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*65)-1 downto STREAM_WSTB_WIDTH*64) <= wstrb_in;
when 65 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*66)-1 downto STREAM_WSTB_WIDTH*65) <= wstrb_in;
when 66 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*67)-1 downto STREAM_WSTB_WIDTH*66) <= wstrb_in;
when 67 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*68)-1 downto STREAM_WSTB_WIDTH*67) <= wstrb_in;
when 68 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*69)-1 downto STREAM_WSTB_WIDTH*68) <= wstrb_in;
when 69 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*70)-1 downto STREAM_WSTB_WIDTH*69) <= wstrb_in;
when 70 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*71)-1 downto STREAM_WSTB_WIDTH*70) <= wstrb_in;
when 71 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*72)-1 downto STREAM_WSTB_WIDTH*71) <= wstrb_in;
when 72 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*73)-1 downto STREAM_WSTB_WIDTH*72) <= wstrb_in;
when 73 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*74)-1 downto STREAM_WSTB_WIDTH*73) <= wstrb_in;
when 74 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*75)-1 downto STREAM_WSTB_WIDTH*74) <= wstrb_in;
when 75 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*76)-1 downto STREAM_WSTB_WIDTH*75) <= wstrb_in;
when 76 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*77)-1 downto STREAM_WSTB_WIDTH*76) <= wstrb_in;
when 77 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*78)-1 downto STREAM_WSTB_WIDTH*77) <= wstrb_in;
when 78 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*79)-1 downto STREAM_WSTB_WIDTH*78) <= wstrb_in;
when 79 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*80)-1 downto STREAM_WSTB_WIDTH*79) <= wstrb_in;
when 80 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*81)-1 downto STREAM_WSTB_WIDTH*80) <= wstrb_in;
when 81 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*82)-1 downto STREAM_WSTB_WIDTH*81) <= wstrb_in;
when 82 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*83)-1 downto STREAM_WSTB_WIDTH*82) <= wstrb_in;
when 83 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*84)-1 downto STREAM_WSTB_WIDTH*83) <= wstrb_in;
when 84 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*85)-1 downto STREAM_WSTB_WIDTH*84) <= wstrb_in;
when 85 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*86)-1 downto STREAM_WSTB_WIDTH*85) <= wstrb_in;
when 86 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*87)-1 downto STREAM_WSTB_WIDTH*86) <= wstrb_in;
when 87 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*88)-1 downto STREAM_WSTB_WIDTH*87) <= wstrb_in;
when 88 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*89)-1 downto STREAM_WSTB_WIDTH*88) <= wstrb_in;
when 89 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*90)-1 downto STREAM_WSTB_WIDTH*89) <= wstrb_in;
when 90 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*91)-1 downto STREAM_WSTB_WIDTH*90) <= wstrb_in;
when 91 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*92)-1 downto STREAM_WSTB_WIDTH*91) <= wstrb_in;
when 92 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*93)-1 downto STREAM_WSTB_WIDTH*92) <= wstrb_in;
when 93 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*94)-1 downto STREAM_WSTB_WIDTH*93) <= wstrb_in;
when 94 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*95)-1 downto STREAM_WSTB_WIDTH*94) <= wstrb_in;
when 95 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*96)-1 downto STREAM_WSTB_WIDTH*95) <= wstrb_in;
when 96 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*97 )-1 downto STREAM_WSTB_WIDTH*96 ) <= wstrb_in;
when 97 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*98 )-1 downto STREAM_WSTB_WIDTH*97 ) <= wstrb_in;
when 98 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*99 )-1 downto STREAM_WSTB_WIDTH*98 ) <= wstrb_in;
when 99 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*100)-1 downto STREAM_WSTB_WIDTH*99 ) <= wstrb_in;
when 100 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*101)-1 downto STREAM_WSTB_WIDTH*100) <= wstrb_in;
when 101 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*102)-1 downto STREAM_WSTB_WIDTH*101) <= wstrb_in;
when 102 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*103)-1 downto STREAM_WSTB_WIDTH*102) <= wstrb_in;
when 103 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*104)-1 downto STREAM_WSTB_WIDTH*103) <= wstrb_in;
when 104 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*105)-1 downto STREAM_WSTB_WIDTH*104) <= wstrb_in;
when 105 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*106)-1 downto STREAM_WSTB_WIDTH*105) <= wstrb_in;
when 106 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*107)-1 downto STREAM_WSTB_WIDTH*106) <= wstrb_in;
when 107 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*108)-1 downto STREAM_WSTB_WIDTH*107) <= wstrb_in;
when 108 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*109)-1 downto STREAM_WSTB_WIDTH*108) <= wstrb_in;
when 109 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*110)-1 downto STREAM_WSTB_WIDTH*109) <= wstrb_in;
when 110 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*111)-1 downto STREAM_WSTB_WIDTH*110) <= wstrb_in;
when 111 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*112)-1 downto STREAM_WSTB_WIDTH*111) <= wstrb_in;
when 112 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*113)-1 downto STREAM_WSTB_WIDTH*112) <= wstrb_in;
when 113 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*114)-1 downto STREAM_WSTB_WIDTH*113) <= wstrb_in;
when 114 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*115)-1 downto STREAM_WSTB_WIDTH*114) <= wstrb_in;
when 115 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*116)-1 downto STREAM_WSTB_WIDTH*115) <= wstrb_in;
when 116 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*117)-1 downto STREAM_WSTB_WIDTH*116) <= wstrb_in;
when 117 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*118)-1 downto STREAM_WSTB_WIDTH*117) <= wstrb_in;
when 118 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*119)-1 downto STREAM_WSTB_WIDTH*118) <= wstrb_in;
when 119 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*120)-1 downto STREAM_WSTB_WIDTH*119) <= wstrb_in;
when 120 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*121)-1 downto STREAM_WSTB_WIDTH*120) <= wstrb_in;
when 121 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*122)-1 downto STREAM_WSTB_WIDTH*121) <= wstrb_in;
when 122 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*123)-1 downto STREAM_WSTB_WIDTH*122) <= wstrb_in;
when 123 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*124)-1 downto STREAM_WSTB_WIDTH*123) <= wstrb_in;
when 124 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*125)-1 downto STREAM_WSTB_WIDTH*124) <= wstrb_in;
when 125 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*126)-1 downto STREAM_WSTB_WIDTH*125) <= wstrb_in;
when 126 =>
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*127)-1 downto STREAM_WSTB_WIDTH*126) <= wstrb_in;
when others => -- 127 case
lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*128)-1 downto STREAM_WSTB_WIDTH*127) <= wstrb_in;
end case;
end process DO_128XN_DEMUX;
end generate GEN_128XN;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux8_1_x_n.vhd
|
18
|
6145
|
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_dre_mux8_1_x_n.vhd
--
-- Description:
--
-- This VHDL file provides a 8 to 1 xn bit wide mux for the AXI Data Realignment
-- Engine (DRE).
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Start 8 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Entity axi_datamover_dre_mux8_1_x_n is
generic (
C_WIDTH : Integer := 8
-- Sets the bit width of the 8x Mux slice
);
port (
Sel : In std_logic_vector(2 downto 0);
-- Mux select control
I0 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 0 input
I1 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 1 input
I2 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 2 input
I3 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 3 input
I4 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 4 input
I5 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 5 input
I6 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 6 input
I7 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 7 input
Y : Out std_logic_vector(C_WIDTH-1 downto 0)
-- Mux output value
);
end entity axi_datamover_dre_mux8_1_x_n; --
Architecture implementation of axi_datamover_dre_mux8_1_x_n is
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SELECT8_1
--
-- Process Description:
-- This process implements an 8 to 1 mux.
--
-------------------------------------------------------------
SELECT8_1 : process (Sel, I0, I1, I2, I3,
I4, I5, I6, I7)
begin
case Sel is
when "000" =>
Y <= I0;
when "001" =>
Y <= I1;
when "010" =>
Y <= I2;
when "011" =>
Y <= I3;
when "100" =>
Y <= I4;
when "101" =>
Y <= I5;
when "110" =>
Y <= I6;
when "111" =>
Y <= I7;
when others =>
Y <= I0;
end case;
end process SELECT8_1;
end implementation; -- axi_datamover_dre_mux8_1_x_n
-------------------------------------------------------------------------------
-- End 8 to 1 xN Mux
-------------------------------------------------------------------------------
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_vregister.vhd
|
4
|
13338
|
-------------------------------------------------------------------------------
-- axi_vdma_vregister
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vregister.vhd
--
-- Description: Top level for video register block. These registers provide
-- the video parameters to the DMA controllers.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vregister is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 32 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Video Register Update control --
video_reg_update : in std_logic ; --
--
dmasr_halt : in std_logic ; --
-- Scatter Gather register Bank --
vsize_sg : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
hsize_sg : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
stride_sg : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
frmdly_sg : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
start_address_sg : in STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
-- Video Register Bank --
vsize_vid : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
hsize_vid : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
stride_vid : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
frmdly_vid : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
start_address_vid : out STARTADDR_ARRAY_TYPE
(0 to C_NUM_FSTORES - 1) --
);
end axi_vdma_vregister;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vregister is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- No Signals Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Vertical Size - Video Side
REG_VSIZE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
vsize_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
vsize_vid <= vsize_sg;
end if;
end if;
end process REG_VSIZE;
-- Horizontal Size - Video Side
REG_HSIZE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
hsize_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
hsize_vid <= hsize_sg;
end if;
end if;
end process REG_HSIZE;
-- Stride - Video Side
REG_STRIDE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
stride_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
stride_vid <= stride_sg;
end if;
end if;
end process REG_STRIDE;
-- Frame Delay - Video Side
REG_FRMDLY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
frmdly_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
frmdly_vid <= frmdly_sg;
end if;
end if;
end process REG_FRMDLY;
-- Generate C_NUM_FSTORE start address registeres
GEN_START_ADDR_REG : for i in 0 to C_NUM_FSTORES-1 generate
begin
-- Start Address Registers
REG_START_ADDR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
start_address_vid(i) <= (others => '0');
elsif(video_reg_update = '1')then
start_address_vid(i) <= start_address_sg(i);
end if;
end if;
end process REG_START_ADDR;
end generate GEN_START_ADDR_REG;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ip/block_design_xlconstant_0_0/sim/block_design_xlconstant_0_0.vhd
|
4
|
1337
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/14/2014 12:18:30 PM
-- Design Name:
-- Module Name: tb_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconstant;
ENTITY block_design_xlconstant_0_0 IS
PORT (
dout : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0)
);
END block_design_xlconstant_0_0;
ARCHITECTURE block_design_xlconstant_0_0_arch OF block_design_xlconstant_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_xlconstant_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconstant IS
GENERIC (
CONST_VAL : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
CONST_WIDTH : INTEGER
);
PORT (
dout : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0)
);
END COMPONENT xlconstant;
BEGIN
U0 : xlconstant
GENERIC MAP (
CONST_VAL => "000000",
CONST_WIDTH => 6
)
PORT MAP (
dout => dout
);
END block_design_xlconstant_0_0_arch;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/bd/block_design/ip/block_design_xlconstant_0_0/sim/block_design_xlconstant_0_0.vhd
|
4
|
1337
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/14/2014 12:18:30 PM
-- Design Name:
-- Module Name: tb_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconstant;
ENTITY block_design_xlconstant_0_0 IS
PORT (
dout : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0)
);
END block_design_xlconstant_0_0;
ARCHITECTURE block_design_xlconstant_0_0_arch OF block_design_xlconstant_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_xlconstant_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconstant IS
GENERIC (
CONST_VAL : STD_LOGIC_VECTOR(6-1 DOWNTO 0);
CONST_WIDTH : INTEGER
);
PORT (
dout : OUT STD_LOGIC_VECTOR(6-1 DOWNTO 0)
);
END COMPONENT xlconstant;
BEGIN
U0 : xlconstant
GENERIC MAP (
CONST_VAL => "000000",
CONST_WIDTH => 6
)
PORT MAP (
dout => dout
);
END block_design_xlconstant_0_0_arch;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_gpio_sysfs/zybo_petalinux_1.ip_user_files/ipstatic/proc_sys_reset_v5_0/hdl/src/vhdl/sequence_psr.vhd
|
15
|
22231
|
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_9;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_9.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_mm2s_linebuf.vhd
|
4
|
130236
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_linebuf
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_linebuf.vhd
-- Description: This entity encompases the mm2s line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_mm2s_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AE_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost empty threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-- MM2S AXIS Input Side (i.e. Datamover side)
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
-- MM2S AXIS Output Side --
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
mm2s_axis_linebuf_reset_out : out std_logic ; --
s2mm_axis_resetn : in std_logic := '1' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
s2mm_fsync : in std_logic ; --
mm2s_fsync_core : out std_logic ; --
mm2s_fsize_mismatch_err_s : out std_logic ; --
mm2s_fsize_mismatch_err_m : out std_logic ; --
mm2s_vsize_cntr_clr_flag : out std_logic ; --
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : out std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
run_stop : in std_logic ; --
-- Graceful shut down control --
dm_halt : in std_logic ; --
dm_halt_reg_out : out std_logic ; --
cmdsts_idle : in std_logic ; --
stop : in std_logic ; -- CR623291
stop_reg_out : out std_logic ; -- CR623291
--
-- Vertical Line Count control --
fsync_out : in std_logic ; -- CR616211
fsync_out_m : out std_logic ; -- CR616211
mm2s_fsize_mismatch_err_flag: in std_logic ; -- CR616211
frame_sync : in std_logic ; -- CR616211
crnt_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
crnt_vsize_d2_out : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
--
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
--
-- Stream In (Datamover To Line Buffer) --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
--
--
-- Stream Out (Line Buffer To MM2S AXIS) --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
m_axis_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
--
-- Fifo Status Flags --
dwidth_fifo_pipe_empty : in std_logic ; --
dwidth_fifo_pipe_empty_m : out std_logic ; --
mm2s_fifo_pipe_empty : out std_logic ; --
mm2s_fifo_empty : out std_logic ; --
mm2s_fifo_almost_empty : out std_logic ; --
mm2s_all_lines_xfred_s_dwidth : in std_logic ; --
mm2s_all_lines_xfred_s : out std_logic ; --
mm2s_all_lines_xfred : out std_logic -- CR616211
);
end axi_vdma_mm2s_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
-- Increase data width by 1 when tuser support included.
--constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8) + 1;
constant BUFFER_WIDTH : integer := C_DATA_WIDTH -- tdata
+ (C_DATA_WIDTH/8)*C_INCLUDE_MM2S_DRE -- tkeep
+ 1 -- tlast
+ (C_MM2S_SOF_ENABLE -- tuser
*C_M_AXIS_MM2S_TUSER_BITS);
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant DATA_COUNT_ZERO : std_logic_vector(DATACOUNT_WIDTH-1 downto 0)
:= (others => '0');
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
constant THRESHOLD_PAD : std_logic_vector(THRESHOLD_LSB_INDEX-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_rdcount : std_logic_vector(DATACOUNT_WIDTH -1 downto 0) := (others => '0');
signal s_axis_tready_i : std_logic := '0'; -- CR619293
signal m_axis_tready_i : std_logic := '0';
signal m_axis_tvalid_i : std_logic := '0';
signal m_axis_tlast_i : std_logic := '0';
signal m_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal m_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tuser_i : std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS - 1 downto 0) := (others => '0');
signal m_axis_tready_d1 : std_logic := '0';
signal m_axis_tlast_d1 : std_logic := '0';
signal m_axis_tvalid_d1 : std_logic := '0';
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal decr_vcount : std_logic := '0'; -- CR575884
signal all_lines_xfred : std_logic := '0'; -- CR616211
signal all_lines_xfred_no_dwidth : std_logic := '0'; -- CR616211
signal mm2s_all_lines_xfred_s_sig : std_logic := '0'; -- CR616211
signal m_axis_tvalid_out : std_logic := '0'; -- CR576993
signal m_axis_tlast_out : std_logic := '0'; -- CR616211
signal slv2skid_s_axis_tvalid : std_logic := '0'; -- CR576993
signal fifo_empty_d1 : std_logic := '0'; -- CR576993
-- FIFO Pipe empty signals
signal fifo_pipe_empty : std_logic := '0';
signal fifo_wren_d1 : std_logic := '0'; -- CR579191
signal pot_empty : std_logic := '0'; -- CR579191
signal fifo_almost_empty_i : std_logic := '1'; -- CR604273/CR604272
signal fifo_almost_empty_d1 : std_logic := '1';
signal fifo_almost_empty_fe : std_logic := '0'; -- CR604273/CR604272
signal fifo_almost_empty_reg : std_logic := '1';
signal data_count_ae_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal m_data_count_ae_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal sf_threshold_met : std_logic := '0';
signal cmdsts_idle_d1 : std_logic := '0';
signal cmdsts_idle_fe : std_logic := '0';
signal stop_reg : std_logic := '0'; --CR623291
signal s_axis_fifo_ainit : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal s_axis_fifo_ainit_nosync_reg : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal dm_decr_vcount : std_logic := '0'; -- CR619293
signal dm_xfred_all_lines : std_logic := '0'; -- CR619293
signal dm_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR619293
signal dm_xfred_all_lines_reg : std_logic := '0'; -- CR619293
signal sof_flag : std_logic := '0';
signal mm2s_fifo_pipe_empty_i : std_logic := '0';
signal frame_sync_d1 : std_logic := '0';
signal m_skid_reset : std_logic := '0';
signal dm_halt_reg : std_logic := '0';
signal mm2s_axis_linebuf_reset_out_inv : std_logic := '0' ; --
signal sof_reset : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_fifo_pipe_empty <= mm2s_fifo_pipe_empty_i;
dm_halt_reg_out <= dm_halt_reg;
stop_reg_out <= stop_reg;
crnt_vsize_d2_out <= crnt_vsize_d2;
GEN_MM2S_DRE_ON : if C_INCLUDE_MM2S_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_MM2S_DRE_ON;
GEN_MM2S_DRE_OFF : if C_INCLUDE_MM2S_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_MM2S_DRE_OFF;
GEN_LINEBUF_NO_SOF : if (ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0) generate
begin
mm2s_fsync_core <= mm2s_fsync;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= '0';
mm2s_fsize_mismatch_err_s <= '0';
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
GEN_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 and C_MM2S_SOF_ENABLE = 1 generate
--signal sof_reset : std_logic := '0';
begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_SOF;
-- SOF turned off therefore do not generate SOF on tuser
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
-------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
-------- or (sf_threshold_met = '0' -- Or Threshold not met
-------- and stop_reg = '1' -- Commanded to stop
-------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
-------- else '0';
--------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
end generate GEN_SOF;
-- Do not generate sof on tuser(0)
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
sof_flag <= '0';
m_axis_tuser <= (others => '0');
end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_all_lines_xfred_s <= '0';
fsync_out_m <= '0';
mm2s_vsize_cntr_clr_flag <= '0';
mm2s_fsize_mismatch_err_m <= '0';
end generate GEN_LINEBUF_NO_SOF;
GEN_LINEBUF_FLUSH_SOF : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1) generate
signal s2mm_fsync_mm2s_s : std_logic := '0';
signal run_stop_reg : std_logic := '0';
signal fsync_out_d1 : std_logic := '0';
signal mm2s_fsync_int : std_logic := '0';
signal fsize_mismatch_err_int_s : std_logic := '0';
signal fsize_mismatch_err_int_m : std_logic := '0';
signal fsize_mismatch_err_flag_s : std_logic := '0';
signal fsize_mismatch_err_flag_vsize_cntr_clr : std_logic := '0';
signal fsize_mismatch_err_flag_cmb_s : std_logic := '0';
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
------ GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
------ signal sof_reset : std_logic := '0';
------ begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
------ end generate GEN_SOF;
------
------
-- SOF turned off therefore do not generate SOF on tuser
---------- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
---------- begin
----------
---------- sof_flag <= '0';
----------
---------- -- AXI Slave Side of FIFO
---------- fifo_din <= s_axis_tlast & s_axis_tkeep & s_axis_tdata;
---------- fifo_wren <= s_axis_tvalid and not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready_i <= not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready <= s_axis_tready_i; -- CR619293
----------
---------- -- AXI Master Side of FIFO
---------- fifo_rden <= m_axis_tready_i and not fifo_empty_i and sf_threshold_met;
---------- m_axis_tvalid_i <= not fifo_empty_i and sf_threshold_met;
---------- m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
---------- m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
---------- m_axis_tlast_i <= not fifo_empty_i and fifo_dout(BUFFER_WIDTH-1);
---------- m_axis_tuser_i <= (others => '0');
----------
---------- end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
---------------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
---------------- or (sf_threshold_met = '0' -- Or Threshold not met
---------------- and stop_reg = '1' -- Commanded to stop
---------------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
---------------- else '0';
----------------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
---- GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
--- begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
--- end generate GEN_SOF;
-- Do not generate sof on tuser(0)
----- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
----- begin
----- sof_flag <= '0';
----- m_axis_tuser <= (others => '0');
----- end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
---- MM2S_RUN_STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => run_stop ,
---- prmry_out => run_stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
MM2S_RUN_STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
---- MM2S_FSIZE_ERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fsize_mismatch_err_int_s ,
---- scndry_out => fsize_mismatch_err_int_m ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
MM2S_FSIZE_ERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsize_mismatch_err_int_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsize_mismatch_err_int_m,
scndry_vect_out => open
);
---- MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => fsync_out ,
---- scndry_out => fsync_out_m ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsync_out_m,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
GEN_ASYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axis_s2mm_aclk ,
---- prmry_resetn => s2mm_axis_resetn ,
---- scndry_aclk => m_axis_aclk ,
---- scndry_resetn => m_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_fsync ,
---- scndry_out => s2mm_fsync_mm2s_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_fsync_mm2s_s,
scndry_vect_out => open
);
end generate GEN_ASYNC_CROSS_FSYNC;
GEN_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
run_stop_reg <= run_stop; -- CR623291
fsync_out_m <= fsync_out; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
fsync_src_select_s_int <= fsync_src_select;
fsize_mismatch_err_int_m <= fsize_mismatch_err_int_s;
GEN_SYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
s2mm_fsync_mm2s_s <= s2mm_fsync;
end generate GEN_SYNC_CROSS_FSYNC;
GEN_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC;
NO_DWIDTH_VERT_COUNTER : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and fsync_out = '0') or fsize_mismatch_err_flag_vsize_cntr_clr = '1' )then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred_no_dwidth <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred_no_dwidth <= '0';
end if;
end if;
end process VERT_COUNTER;
end generate NO_DWIDTH_VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
all_lines_xfred <= mm2s_all_lines_xfred_s_sig;
mm2s_all_lines_xfred_s <= mm2s_all_lines_xfred_s_sig;
--C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= mm2s_all_lines_xfred_s_dwidth;
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= all_lines_xfred_no_dwidth;
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
-- Frame sync cross bar
---- FSYNC_CROSSBAR_MM2S_S : process(fsync_src_select_s_int,
---- run_stop_reg,
---- mm2s_fsync,
---- s2mm_fsync_mm2s_s)
---- begin
---- case fsync_src_select_s_int is
----
---- when "00" => -- primary fsync (default)
---- mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
---- when "01" => -- other channel fsync
---- mm2s_fsync_int <= s2mm_fsync_mm2s_s and run_stop_reg;
---- when others =>
---- mm2s_fsync_int <= '0';
---- end case;
---- end process FSYNC_CROSSBAR_MM2S_S;
FSIZE_MISMATCH_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsize_mismatch_err_int_s <= '0';
-- fsync occurred when not all lines transferred
elsif(mm2s_fsync_int = '1' and mm2s_all_lines_xfred_s_sig = '0')then
fsize_mismatch_err_int_s <= '1';
else
fsize_mismatch_err_int_s <= '0';
end if;
end if;
end process FSIZE_MISMATCH_MM2S_FLUSH_SOF_s;
FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or mm2s_fsync_int = '1')then
fsize_mismatch_err_flag_s <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_s <= '1';
end if;
end if;
end process FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s;
fsize_mismatch_err_flag_cmb_s <= fsize_mismatch_err_int_s or fsize_mismatch_err_flag_s;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= fsize_mismatch_err_flag_cmb_s;
mm2s_fsize_mismatch_err_s <= fsize_mismatch_err_int_s;
mm2s_fsize_mismatch_err_m <= fsize_mismatch_err_int_m;
mm2s_vsize_cntr_clr_flag <= fsize_mismatch_err_flag_vsize_cntr_clr or fsize_mismatch_err_int_s;
D1_FSYNC_OUT : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsync_out_d1 <= '0';
else
fsync_out_d1 <= fsync_out;
end if;
end if;
end process D1_FSYNC_OUT;
FLAG_VSIZE_CNTR_CLR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or fsync_out_d1 = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '1';
end if;
end if;
end process FLAG_VSIZE_CNTR_CLR;
MM2S_FSIZE_ERR_TO_DM_HALT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process MM2S_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= fsize_mismatch_err_int_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and mm2s_fsync_int = '1'
else '0';
MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG;
MM2S_REG_D_FSYNC : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process MM2S_REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
mm2s_fsync_core <= (mm2s_fsync_int and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or d_fsync_halt_cmplt_s;
--mm2s_fsync_core <= mm2s_fsync_int;
end generate GEN_LINEBUF_FLUSH_SOF;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_mm2s_linebuf.vhd
|
4
|
130236
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_linebuf
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
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--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_linebuf.vhd
-- Description: This entity encompases the mm2s line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_mm2s_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AE_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost empty threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-- MM2S AXIS Input Side (i.e. Datamover side)
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
-- MM2S AXIS Output Side --
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
mm2s_axis_linebuf_reset_out : out std_logic ; --
s2mm_axis_resetn : in std_logic := '1' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
s2mm_fsync : in std_logic ; --
mm2s_fsync_core : out std_logic ; --
mm2s_fsize_mismatch_err_s : out std_logic ; --
mm2s_fsize_mismatch_err_m : out std_logic ; --
mm2s_vsize_cntr_clr_flag : out std_logic ; --
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : out std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
run_stop : in std_logic ; --
-- Graceful shut down control --
dm_halt : in std_logic ; --
dm_halt_reg_out : out std_logic ; --
cmdsts_idle : in std_logic ; --
stop : in std_logic ; -- CR623291
stop_reg_out : out std_logic ; -- CR623291
--
-- Vertical Line Count control --
fsync_out : in std_logic ; -- CR616211
fsync_out_m : out std_logic ; -- CR616211
mm2s_fsize_mismatch_err_flag: in std_logic ; -- CR616211
frame_sync : in std_logic ; -- CR616211
crnt_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
crnt_vsize_d2_out : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
--
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
--
-- Stream In (Datamover To Line Buffer) --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
--
--
-- Stream Out (Line Buffer To MM2S AXIS) --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
m_axis_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
--
-- Fifo Status Flags --
dwidth_fifo_pipe_empty : in std_logic ; --
dwidth_fifo_pipe_empty_m : out std_logic ; --
mm2s_fifo_pipe_empty : out std_logic ; --
mm2s_fifo_empty : out std_logic ; --
mm2s_fifo_almost_empty : out std_logic ; --
mm2s_all_lines_xfred_s_dwidth : in std_logic ; --
mm2s_all_lines_xfred_s : out std_logic ; --
mm2s_all_lines_xfred : out std_logic -- CR616211
);
end axi_vdma_mm2s_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
-- Increase data width by 1 when tuser support included.
--constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8) + 1;
constant BUFFER_WIDTH : integer := C_DATA_WIDTH -- tdata
+ (C_DATA_WIDTH/8)*C_INCLUDE_MM2S_DRE -- tkeep
+ 1 -- tlast
+ (C_MM2S_SOF_ENABLE -- tuser
*C_M_AXIS_MM2S_TUSER_BITS);
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant DATA_COUNT_ZERO : std_logic_vector(DATACOUNT_WIDTH-1 downto 0)
:= (others => '0');
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
constant THRESHOLD_PAD : std_logic_vector(THRESHOLD_LSB_INDEX-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_rdcount : std_logic_vector(DATACOUNT_WIDTH -1 downto 0) := (others => '0');
signal s_axis_tready_i : std_logic := '0'; -- CR619293
signal m_axis_tready_i : std_logic := '0';
signal m_axis_tvalid_i : std_logic := '0';
signal m_axis_tlast_i : std_logic := '0';
signal m_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal m_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tuser_i : std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS - 1 downto 0) := (others => '0');
signal m_axis_tready_d1 : std_logic := '0';
signal m_axis_tlast_d1 : std_logic := '0';
signal m_axis_tvalid_d1 : std_logic := '0';
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal decr_vcount : std_logic := '0'; -- CR575884
signal all_lines_xfred : std_logic := '0'; -- CR616211
signal all_lines_xfred_no_dwidth : std_logic := '0'; -- CR616211
signal mm2s_all_lines_xfred_s_sig : std_logic := '0'; -- CR616211
signal m_axis_tvalid_out : std_logic := '0'; -- CR576993
signal m_axis_tlast_out : std_logic := '0'; -- CR616211
signal slv2skid_s_axis_tvalid : std_logic := '0'; -- CR576993
signal fifo_empty_d1 : std_logic := '0'; -- CR576993
-- FIFO Pipe empty signals
signal fifo_pipe_empty : std_logic := '0';
signal fifo_wren_d1 : std_logic := '0'; -- CR579191
signal pot_empty : std_logic := '0'; -- CR579191
signal fifo_almost_empty_i : std_logic := '1'; -- CR604273/CR604272
signal fifo_almost_empty_d1 : std_logic := '1';
signal fifo_almost_empty_fe : std_logic := '0'; -- CR604273/CR604272
signal fifo_almost_empty_reg : std_logic := '1';
signal data_count_ae_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal m_data_count_ae_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal sf_threshold_met : std_logic := '0';
signal cmdsts_idle_d1 : std_logic := '0';
signal cmdsts_idle_fe : std_logic := '0';
signal stop_reg : std_logic := '0'; --CR623291
signal s_axis_fifo_ainit : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal s_axis_fifo_ainit_nosync_reg : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal dm_decr_vcount : std_logic := '0'; -- CR619293
signal dm_xfred_all_lines : std_logic := '0'; -- CR619293
signal dm_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR619293
signal dm_xfred_all_lines_reg : std_logic := '0'; -- CR619293
signal sof_flag : std_logic := '0';
signal mm2s_fifo_pipe_empty_i : std_logic := '0';
signal frame_sync_d1 : std_logic := '0';
signal m_skid_reset : std_logic := '0';
signal dm_halt_reg : std_logic := '0';
signal mm2s_axis_linebuf_reset_out_inv : std_logic := '0' ; --
signal sof_reset : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_fifo_pipe_empty <= mm2s_fifo_pipe_empty_i;
dm_halt_reg_out <= dm_halt_reg;
stop_reg_out <= stop_reg;
crnt_vsize_d2_out <= crnt_vsize_d2;
GEN_MM2S_DRE_ON : if C_INCLUDE_MM2S_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_MM2S_DRE_ON;
GEN_MM2S_DRE_OFF : if C_INCLUDE_MM2S_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_MM2S_DRE_OFF;
GEN_LINEBUF_NO_SOF : if (ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0) generate
begin
mm2s_fsync_core <= mm2s_fsync;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= '0';
mm2s_fsize_mismatch_err_s <= '0';
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
GEN_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 and C_MM2S_SOF_ENABLE = 1 generate
--signal sof_reset : std_logic := '0';
begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_SOF;
-- SOF turned off therefore do not generate SOF on tuser
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
-------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
-------- or (sf_threshold_met = '0' -- Or Threshold not met
-------- and stop_reg = '1' -- Commanded to stop
-------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
-------- else '0';
--------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
end generate GEN_SOF;
-- Do not generate sof on tuser(0)
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
sof_flag <= '0';
m_axis_tuser <= (others => '0');
end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_all_lines_xfred_s <= '0';
fsync_out_m <= '0';
mm2s_vsize_cntr_clr_flag <= '0';
mm2s_fsize_mismatch_err_m <= '0';
end generate GEN_LINEBUF_NO_SOF;
GEN_LINEBUF_FLUSH_SOF : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1) generate
signal s2mm_fsync_mm2s_s : std_logic := '0';
signal run_stop_reg : std_logic := '0';
signal fsync_out_d1 : std_logic := '0';
signal mm2s_fsync_int : std_logic := '0';
signal fsize_mismatch_err_int_s : std_logic := '0';
signal fsize_mismatch_err_int_m : std_logic := '0';
signal fsize_mismatch_err_flag_s : std_logic := '0';
signal fsize_mismatch_err_flag_vsize_cntr_clr : std_logic := '0';
signal fsize_mismatch_err_flag_cmb_s : std_logic := '0';
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
------ GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
------ signal sof_reset : std_logic := '0';
------ begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
------ end generate GEN_SOF;
------
------
-- SOF turned off therefore do not generate SOF on tuser
---------- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
---------- begin
----------
---------- sof_flag <= '0';
----------
---------- -- AXI Slave Side of FIFO
---------- fifo_din <= s_axis_tlast & s_axis_tkeep & s_axis_tdata;
---------- fifo_wren <= s_axis_tvalid and not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready_i <= not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready <= s_axis_tready_i; -- CR619293
----------
---------- -- AXI Master Side of FIFO
---------- fifo_rden <= m_axis_tready_i and not fifo_empty_i and sf_threshold_met;
---------- m_axis_tvalid_i <= not fifo_empty_i and sf_threshold_met;
---------- m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
---------- m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
---------- m_axis_tlast_i <= not fifo_empty_i and fifo_dout(BUFFER_WIDTH-1);
---------- m_axis_tuser_i <= (others => '0');
----------
---------- end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
---------------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
---------------- or (sf_threshold_met = '0' -- Or Threshold not met
---------------- and stop_reg = '1' -- Commanded to stop
---------------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
---------------- else '0';
----------------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
---- GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
--- begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
--- end generate GEN_SOF;
-- Do not generate sof on tuser(0)
----- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
----- begin
----- sof_flag <= '0';
----- m_axis_tuser <= (others => '0');
----- end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
---- MM2S_RUN_STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => run_stop ,
---- prmry_out => run_stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
MM2S_RUN_STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
---- MM2S_FSIZE_ERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fsize_mismatch_err_int_s ,
---- scndry_out => fsize_mismatch_err_int_m ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
MM2S_FSIZE_ERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsize_mismatch_err_int_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsize_mismatch_err_int_m,
scndry_vect_out => open
);
---- MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => fsync_out ,
---- scndry_out => fsync_out_m ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsync_out_m,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
GEN_ASYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axis_s2mm_aclk ,
---- prmry_resetn => s2mm_axis_resetn ,
---- scndry_aclk => m_axis_aclk ,
---- scndry_resetn => m_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_fsync ,
---- scndry_out => s2mm_fsync_mm2s_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_fsync_mm2s_s,
scndry_vect_out => open
);
end generate GEN_ASYNC_CROSS_FSYNC;
GEN_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
run_stop_reg <= run_stop; -- CR623291
fsync_out_m <= fsync_out; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
fsync_src_select_s_int <= fsync_src_select;
fsize_mismatch_err_int_m <= fsize_mismatch_err_int_s;
GEN_SYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
s2mm_fsync_mm2s_s <= s2mm_fsync;
end generate GEN_SYNC_CROSS_FSYNC;
GEN_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC;
NO_DWIDTH_VERT_COUNTER : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and fsync_out = '0') or fsize_mismatch_err_flag_vsize_cntr_clr = '1' )then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred_no_dwidth <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred_no_dwidth <= '0';
end if;
end if;
end process VERT_COUNTER;
end generate NO_DWIDTH_VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
all_lines_xfred <= mm2s_all_lines_xfred_s_sig;
mm2s_all_lines_xfred_s <= mm2s_all_lines_xfred_s_sig;
--C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= mm2s_all_lines_xfred_s_dwidth;
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= all_lines_xfred_no_dwidth;
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
-- Frame sync cross bar
---- FSYNC_CROSSBAR_MM2S_S : process(fsync_src_select_s_int,
---- run_stop_reg,
---- mm2s_fsync,
---- s2mm_fsync_mm2s_s)
---- begin
---- case fsync_src_select_s_int is
----
---- when "00" => -- primary fsync (default)
---- mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
---- when "01" => -- other channel fsync
---- mm2s_fsync_int <= s2mm_fsync_mm2s_s and run_stop_reg;
---- when others =>
---- mm2s_fsync_int <= '0';
---- end case;
---- end process FSYNC_CROSSBAR_MM2S_S;
FSIZE_MISMATCH_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsize_mismatch_err_int_s <= '0';
-- fsync occurred when not all lines transferred
elsif(mm2s_fsync_int = '1' and mm2s_all_lines_xfred_s_sig = '0')then
fsize_mismatch_err_int_s <= '1';
else
fsize_mismatch_err_int_s <= '0';
end if;
end if;
end process FSIZE_MISMATCH_MM2S_FLUSH_SOF_s;
FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or mm2s_fsync_int = '1')then
fsize_mismatch_err_flag_s <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_s <= '1';
end if;
end if;
end process FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s;
fsize_mismatch_err_flag_cmb_s <= fsize_mismatch_err_int_s or fsize_mismatch_err_flag_s;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= fsize_mismatch_err_flag_cmb_s;
mm2s_fsize_mismatch_err_s <= fsize_mismatch_err_int_s;
mm2s_fsize_mismatch_err_m <= fsize_mismatch_err_int_m;
mm2s_vsize_cntr_clr_flag <= fsize_mismatch_err_flag_vsize_cntr_clr or fsize_mismatch_err_int_s;
D1_FSYNC_OUT : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsync_out_d1 <= '0';
else
fsync_out_d1 <= fsync_out;
end if;
end if;
end process D1_FSYNC_OUT;
FLAG_VSIZE_CNTR_CLR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or fsync_out_d1 = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '1';
end if;
end if;
end process FLAG_VSIZE_CNTR_CLR;
MM2S_FSIZE_ERR_TO_DM_HALT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process MM2S_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= fsize_mismatch_err_int_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and mm2s_fsync_int = '1'
else '0';
MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG;
MM2S_REG_D_FSYNC : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process MM2S_REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
mm2s_fsync_core <= (mm2s_fsync_int and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or d_fsync_halt_cmplt_s;
--mm2s_fsync_core <= mm2s_fsync_int;
end generate GEN_LINEBUF_FLUSH_SOF;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_gpio_sysfs/zybo_petalinux_1.srcs/sources_1/bd/block_design/ipshared/xilinx.com/interrupt_control_v3_1/hdl/src/vhdl/interrupt_control.vhd
|
4
|
57397
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0_2 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0_2 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0_2
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_fsync_gen.vhd
|
4
|
36967
|
-------------------------------------------------------------------------------
-- axi_vdma_fsync_gen
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_fsync_gen.vhd
-- Description: This entity generates the frame sync for vdma operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_fsync_gen is
generic (
C_USE_FSYNC : integer range 0 to 1 := 0;
-- Specifies DMA oeration synchronized to frame sync input
-- 0 = Free running
-- 1 = Fsync synchronous
ENABLE_FLUSH_ON_MM2S_FSYNC : integer range 0 to 1 := 0 ;
ENABLE_FLUSH_ON_S2MM_FSYNC : integer range 0 to 1 := 0 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 0 ;
C_INCLUDE_MM2S : integer range 0 to 1 := 0 ;
C_SOF_ENABLE : integer range 0 to 1 := 0
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Frame Count Enable Support --
valid_video_prmtrs : in std_logic ; --
valid_frame_sync_cmb : in std_logic ; --
frmcnt_ioc : in std_logic ; --
dmacr_frmcnt_enbl : in std_logic ; --
dmasr_frmcnt_status : in std_logic_vector(7 downto 0) ; --
mask_fsync_out : out std_logic ; --
--
-- VDMA status for free run (C_USE_FSYNC = 0) --
run_stop : in std_logic ; --
all_idle : in std_logic ; --
parameter_update : in std_logic ; --
--
-- Frame Sync Sources (C_USE_FSYNC = 1) --
fsync : in std_logic ; --
tuser_fsync : in std_logic ; --
othrchnl_fsync : in std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
-- Sync out for VDMA logic --
frame_sync : out std_logic ; --
--
-- Sync / Update out top level for Video IP --
frame_sync_out : out std_logic ; --
prmtr_update : out std_logic --
);
end axi_vdma_fsync_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_fsync_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant FRAME_COUNT_ONE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(1,8));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- No Signals Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Generate Free Run Mode (Internal Frame Sync)
-------------------------------------------------------------------------------
GEN_FREE_RUN_MODE : if C_USE_FSYNC = 0 generate
-- For internal fsync generation
signal all_idle_d1 : std_logic := '0';
signal all_idle_d2 : std_logic := '0';
signal all_idle_re : std_logic := '0';
-- For internal fsync and fsync out
signal frame_sync_aligned : std_logic := '0';
signal frame_sync_i : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Register all idle for use in creating rising edge pulse
REG_IDLE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
-- On reset clear flag
if(prmry_resetn = '0')then
all_idle_d1 <= '0';
all_idle_d2 <= '0';
-- Otherwise pass idle state through to gen re pulse
else
all_idle_d1 <= all_idle;
all_idle_d2 <= all_idle_d1;
end if;
end if;
end process REG_IDLE;
all_idle_re <= all_idle_d1 and not all_idle_d2;
-- Register frame sync source to shift all processes started
-- by fsync 1 clock later in time. This allows initial FrameDelay
-- and resulting calculation to be registered before
-- being latched by frame_sync.
REG_FSYNC_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_i <= '0';
else
frame_sync_i <= all_idle_re and run_stop;
end if;
end if;
end process REG_FSYNC_PROCESS;
-- Pass out for internal use (secondary clock domain)
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FREE_RUN_MODE;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_MM2S_NO_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_MM2S = 1 and (ENABLE_FLUSH_ON_MM2S_FSYNC = 0 or C_SOF_ENABLE = 0)) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
---- end generate GEN_FSYNC_NO_SOF;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_MM2S_NO_SOF;
GEN_FSYNC_MODE_MM2S_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_MM2S = 1 and ENABLE_FLUSH_ON_MM2S_FSYNC = 1 and C_SOF_ENABLE = 1) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
frame_sync_i <= fsync;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_MM2S_SOF;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_NON_FLUSH : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 0) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- generate fsync from tuser
GEN_FSYNC_FOR_SOF : if C_SOF_ENABLE = 1 generate
begin
-- frame_sync_i <= tuser_fsync and run_stop;
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync,
tuser_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when "10" => -- tuser fsync (used only by s2mm)
frame_sync_i <= tuser_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
end generate GEN_FSYNC_FOR_SOF;
-- generate fsync from fsync
GEN_FSYNC_NO_SOF : if C_SOF_ENABLE = 0 generate
begin
-- Internal fsync on fe for vdma if running
--frame_sync_i <= fsync and run_stop;
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
end generate GEN_FSYNC_NO_SOF;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_NON_FLUSH;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_FLUSH_NON_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and C_SOF_ENABLE = 0) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
-- Frame sync cross bar
FSYNC_CROSSBAR : process(fsync_src_select,
run_stop,
fsync,
othrchnl_fsync)
begin
case fsync_src_select is
when "00" => -- primary fsync (default)
frame_sync_i <= fsync and run_stop;
when "01" => -- other channel fsync
frame_sync_i <= othrchnl_fsync and run_stop;
when others =>
frame_sync_i <= '0';
end case;
end process FSYNC_CROSSBAR;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_FLUSH_NON_SOF;
-------------------------------------------------------------------------------
-- Generate Frame Sync Mode (External frame sync)
-------------------------------------------------------------------------------
-- Note: Treated async and sync clock modes as async so fsync out behavior is
-- identical regardless of mode.
GEN_FSYNC_MODE_S2MM_FLUSH_SOF : if (C_USE_FSYNC = 1 and C_INCLUDE_S2MM = 1 and ENABLE_FLUSH_ON_S2MM_FSYNC = 1 and C_SOF_ENABLE = 1) generate
-- Frame sync for VDMA and for core output
signal frame_sync_i : std_logic := '0';
signal frame_sync_aligned : std_logic := '0';
signal mask_fsync_out_i : std_logic := '0';
begin
frame_sync_i <= fsync;
-- Pass out for VDMA use
frame_sync <= frame_sync_i;
-- For frame count enable, mask fsync out at end of frame.
FRAME_SYNC_MASK : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
mask_fsync_out_i <= '0';
-- If masked and ioc occurs then clear mask
elsif(mask_fsync_out_i = '1' and frmcnt_ioc = '1')then
mask_fsync_out_i <= '0';
-- On frame count enable at end of last frame mask off last fsync out
elsif(dmacr_frmcnt_enbl = '1' and dmasr_frmcnt_status = FRAME_COUNT_ONE and valid_frame_sync_cmb = '1')then
mask_fsync_out_i <= '1';
end if;
end if;
end process FRAME_SYNC_MASK;
mask_fsync_out <= mask_fsync_out_i or not valid_video_prmtrs;
-------------------------------------------------------------------
-- GENERATE FSYNC OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Align internal fsync with parameter update. Parameter update
-- asserts on next clock after frame_sync therefor by adding 1
-- pipe of delay we align parameter_update input with frame_sync
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
-- clear on reset or s_h clear
if(prmry_resetn = '0')then
frame_sync_aligned <= '0';
else
frame_sync_aligned <= frame_sync_i;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Provide output of frame sync to target Video IP.
REG_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
frame_sync_out <= '0';
else
frame_sync_out <= frame_sync_aligned and not mask_fsync_out_i and valid_video_prmtrs;
end if;
end if;
end process REG_FSYNC_OUT;
-------------------------------------------------------------------
-- GENERATE PARAMETER UPDATE OUT FOR VIDEO IP
-------------------------------------------------------------------
-- Provide output of video parameter update to target Video IP.
REG_PRMTRUPDT_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk='1')then
if(prmry_resetn = '0')then
prmtr_update <= '0';
else
prmtr_update <= parameter_update and not mask_fsync_out_i;
end if;
end if;
end process REG_PRMTRUPDT_OUT;
end generate GEN_FSYNC_MODE_S2MM_FLUSH_SOF;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rddata_cntl.vhd
|
5
|
75297
|
-------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_rdmux;
-------------------------------------------------------------------------------
entity axi_datamover_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_rddata_cntl;
architecture implementation of axi_datamover_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast ;
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
GEN_MM2S_TKEEP_ENABLE5 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
end generate GEN_MM2S_TKEEP_ENABLE5;
GEN_MM2S_TKEEP_DISABLE5 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE5;
-- MM2S Supplimental Controls
mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
sig_next_cmd_cmplt_reg) or
(sig_halt_reg and
sig_dqual_reg_full and
not(sig_no_posted_cmds) and
not(sig_calc_error_reg));
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_datamover_v5_1_11.axi_datamover_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH
)
port map (
mmap_read_data_in => mm2s_rdata ,
mux_data_out => mm2s_strm_wdata ,
mstr2data_saddr_lsb => sig_addr_lsb_reg
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When (mm2s_rresp = DECERR and mm2s_rvalid = '1')
Else '0';
sig_slverr <= '1'
When (mm2s_rresp = SLVERR and mm2s_rvalid = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/lib_srl_fifo_v1_0/hdl/src/vhdl/srl_fifo_rbu_f.vhd
|
15
|
15824
|
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed lib library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_srl_fifo_v1_0_2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity lib_srl_fifo_v1_0_2.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity lib_srl_fifo_v1_0_2.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_pkg.vhd
|
4
|
8426
|
-------------------------------------------------------------------------------
-- axi_sg_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI SG Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v4_03.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package axi_sg_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Convert boolean to a std_logic
function bo2int (value : boolean)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- AXI Response Values
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-- Misc Constants
constant CMD_BASE_WIDTH : integer := 40;
constant SG_BTT_WIDTH : integer := 7;
constant SG_ADDR_LSB : integer := 6;
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST : integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
-- Descriptor field bits
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_CMPLTD_BIT : integer := 31;
-- IOC Bit on descriptor update
-- Stored in LSB of TAG field then catinated on status word from primary
-- datamover (i.e. DESCTYPE & IOC & STATUS & Bytes Transferred).
constant DESC_IOC_TAG_BIT : integer := 32;
end axi_sg_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_sg_pkg is
-------------------------------------------------------------------------------
-- Boolean to Integer
-------------------------------------------------------------------------------
function bo2int ( value : boolean)
return integer is
variable value_int : integer;
begin
if(value)then
value_int := 1;
else
value_int := 0;
end if;
return value_int;
end function bo2int;
end package body axi_sg_pkg;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/lib_srl_fifo_v1_0/hdl/src/vhdl/dynshreg_f.vhd
|
15
|
11276
|
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
-- constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
-- constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
-- (C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
-- constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
constant W32 : boolean := (C_DEPTH > 16);
constant W16 : boolean := (not W32);
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
-- constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
-- and ( (W16 and C_DEPTH >= 16)
-- or (W32 and C_DEPTH >= 32)
-- )
-- )
-- or (not W32 and not W16);
constant USE_INFERRED : boolean := true;
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_addr_cntl.vhd
|
5
|
41585
|
----------------------------------------------------------------------------
-- axi_datamover_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_datamover Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
Use axi_datamover_v5_1_11.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_datamover_addr_cntl;
architecture implementation of axi_datamover_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
begin
-- Format the input FIFO data word
sig_aq_fifo_data_in <= mstr2addr_cache &
mstr2addr_user &
mstr2addr_calc_error &
mstr2addr_cmd_cmplt &
mstr2addr_burst &
mstr2addr_size &
mstr2addr_len &
mstr2addr_addr &
mstr2addr_tag ;
-- Rip fields from FIFO output data word
sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 7)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 4)
);
sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 3)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)
);
sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)-1);
sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH)-1);
sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH) ;
sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH) ;
sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH) ;
sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH)-1
downto
C_TAG_WIDTH) ;
sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_ADDR_QUAL_FIFO
--
-- Description:
-- Instance for the Address/Qualifier FIFO
--
------------------------------------------------------------
I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => ADDR_QUAL_WIDTH ,
C_DEPTH => C_ADDR_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_aq_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_aq_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_mngr_64.vhd
|
4
|
110894
|
-------------------------------------------------------------------------------
-- axi_vdma_mngr_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mngr_64.vhd
-- Description: This entity is the top level entity for the AXI VDMA Controller
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr_64.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr_64.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_mngr_64 is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_INCLUDE_SF : integer range 0 to 1 := 0;
-- Include or exclude store and forward module
-- 0 = excluded
-- 1 = included
C_USE_FSYNC : integer range 0 to 1 := 0;
-- Specifies DMA oeration synchronized to frame sync input
-- 0 = Free running
-- 1 = Fsync synchronous
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
C_ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0; -- CR591965
-- Specifies VDMA Flush on Frame sync enabled
-- 0 = Disabled
-- 1 = Enabled
C_NUM_FSTORES : integer range 1 to 32 := 1;
-- Number of Frame Stores
C_GENLOCK_MODE : integer range 0 to 3 := 0;
-- Specifies Gen-Lock Mode of operation
-- 0 = Master - Channel configured to be Gen-Lock Master
-- 1 = Slave - Channel configured to be Gen-Lock Slave
C_GENLOCK_NUM_MASTERS : integer range 1 to 16 := 1;
-- Number of Gen-Lock masters capable of controlling Gen-Lock Slave
--C_GENLOCK_REPEAT_EN : integer range 0 to 1 := 0; -- CR591965
-- In flush on frame sync mode specifies whether frame number
-- will increment on error'ed frame or repeat error'ed frame
-- 0 = increment frame
-- 1 = repeat frame
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_INTERNAL_GENLOCK_ENABLE : integer range 0 to 1 := 0;
-- Enable internal genlock bus
-- 0 = disable internal genlock bus
-- 1 = enable internal genlock bus
C_EXTEND_DM_COMMAND : integer range 0 to 1 := 0;
-- Extend datamover command by padding BTT with 1's for
-- indeterminate BTT mode
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
-----------------------------------------------------------------------
-- Memory Map Parameters
-----------------------------------------------------------------------
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Read Port
C_DM_STATUS_WIDTH : integer := 8 ;
-- CR608521
-- DataMover status width - is based on mode of operation
C_S2MM_SOF_ENABLE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
soft_reset : in std_logic ; --
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
--
-- Control and Status --
run_stop : in std_logic ; --
dmasr_halt : in std_logic ; --
dmacr_repeat_en : in std_logic ; --
sync_enable : in std_logic ; --
regdir_idle : in std_logic ; --
ftch_idle : in std_logic ; --
halt : in std_logic ; --
halt_cmplt : in std_logic ; --
halted_clr : out std_logic ; --
halted_set : out std_logic ; --
idle_set : out std_logic ; --
idle_clr : out std_logic ; --
chnl_current_frame : out std_logic_vector
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
genlock_pair_frame : out std_logic_vector
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
frame_number : out std_logic_vector
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
new_curdesc_wren : out std_logic ; --
stop : out std_logic ; --
all_idle : out std_logic ; --
cmdsts_idle : out std_logic ; --
ftchcmdsts_idle : out std_logic ; --
fsize_mismatch_err_flag : out std_logic ; -- CR591965
fsize_mismatch_err : out std_logic ; -- CR591965
lsize_mismatch_err : out std_logic ; -- CR591965
lsize_more_mismatch_err : out std_logic ; -- CR591965
s2mm_fsize_mismatch_err_s : out std_logic ; -- CR591965
mm2s_fsize_mismatch_err_s : in std_logic ; -- CR591965
mm2s_fsize_mismatch_err_m : in std_logic ; -- CR591965
--
-- Register direct support --
prmtr_updt_complete : in std_logic ; --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_strt_addr : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
mstr_pntr_ref : in std_logic_vector(3 downto 0) ; -- (master in control)
genlock_select : in std_logic ; --
frame_ptr_ref : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
frame_ptr_in : in std_logic_vector --
((C_GENLOCK_NUM_MASTERS --
*NUM_FRM_STORE_WIDTH)-1 downto 0) ; --
frame_ptr_out : out std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
internal_frame_ptr_in : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
--
update_frmstore : out std_logic ; -- CR582182
frmstr_err_addr : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; -- CR582182
valid_frame_sync : out std_logic ; --
valid_frame_sync_cmb : out std_logic ; --
valid_video_prmtrs : out std_logic ; --
parameter_update : out std_logic ; --
tailpntr_updated : in std_logic ; --
frame_sync : in std_logic ; --
circular_prk_mode : in std_logic ; --
line_buffer_empty : in std_logic ; --
dwidth_fifo_pipe_empty : in std_logic ; --
crnt_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR575884
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
all_lines_xfred : in std_logic ; -- CR616211
all_lasts_rcvd : in std_logic ; --
s2mm_strm_all_lines_rcvd : in std_logic ; --
drop_fsync_d_pulse_gen_fsize_less_err : in std_logic ; --
s2mm_fsize_more_or_sof_late : in std_logic ; --
s2mm_dmasr_lsize_less_err : in std_logic ; --
s2mm_fsync_core : in std_logic ;
s2mm_fsync_out_m : in std_logic ;
mm2s_fsync_out_m : in std_logic ;
capture_hsize_at_uf_err : out std_logic_vector(15 downto 0) ;
-- Test Vector signals --
tstvect_err : out std_logic ; --
tstvect_fsync : out std_logic ; --
tstvect_frame : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
tstvect_frm_ptr_out : out std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
mstrfrm_tstsync_out : out std_logic ; --
--
-- AXI Stream Signals --
packet_sof : in std_logic ; --
--
-- Primary DMA Errors --
dma_interr_set_minus_frame_errors : out std_logic ; --
dma_interr_set : out std_logic ; --
dma_slverr_set : out std_logic ; --
dma_decerr_set : out std_logic ; --
--
-- SG Descriptor Fetch AXI Stream In --
m_axis_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : in std_logic ; --
m_axis_ftch_tready : out std_logic ; --
m_axis_ftch_tlast : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_cmd_tvalid : out std_logic ; --
s_axis_cmd_tready : in std_logic ; --
s_axis_cmd_tdata : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_sts_tvalid : in std_logic ; --
m_axis_sts_tready : out std_logic ; --
m_axis_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH-1 downto 0); -- CR608521
m_axis_sts_tkeep : in std_logic_vector --
((C_DM_STATUS_WIDTH/8)-1 downto 0) ; -- CR608521
err : in std_logic ; --
--
ftch_err : in std_logic --
);
end axi_vdma_mngr_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mngr_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Zero vector for tying off unused inputs
constant ZERO_VALUE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal cmnd_wr : std_logic := '0';
signal cmnd_data : std_logic_vector
((C_M_AXI_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal cmnd_pending : std_logic := '0';
signal sts_received : std_logic := '0';
-- Primary DataMover Status signals
signal done : std_logic := '0';
signal stop_i : std_logic := '0';
signal interr : std_logic := '0';
signal interr_minus_frame_errors : std_logic := '0';
signal slverr : std_logic := '0';
signal decerr : std_logic := '0';
signal tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_err : std_logic := '0';
--signal error : std_logic := '0';
signal zero_size_err : std_logic := '0';
signal fsize_mismatch_err_i : std_logic := '0'; -- CR591965
signal lsize_mismatch_err_i : std_logic := '0'; -- CR591965
signal lsize_more_mismatch_err_i : std_logic := '0'; -- CR591965
signal cmnd_idle : std_logic := '0';
signal sts_idle : std_logic := '0';
signal ftch_complete : std_logic := '0';
signal ftch_complete_clr : std_logic := '0';
signal video_prmtrs_valid : std_logic := '0';
signal prmtr_update_complete : std_logic := '0'; -- CR605424
--Descriptor video xfer parameters
signal desc_data_wren : std_logic := '0';
signal desc_strtaddress : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal desc_vsize : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
signal desc_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0');
signal desc_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0');
signal desc_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0');
-- Scatter Gather register Bank
signal crnt_vsize_i : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_hsize : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0');
signal crnt_stride : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0');
signal crnt_frmdly : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0');
signal crnt_start_address : std_logic_vector(C_M_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal frame_number_i : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal mstr_frame_ref_in : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal slv_frame_ref_out : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal valid_frame_sync_i : std_logic := '0';
signal valid_frame_sync_d2 : std_logic := '0';
signal initial_frame : std_logic := '0';
signal tstvect_fsync_d1 : std_logic := '0';
signal tstvect_fsync_d2 : std_logic := '0';
signal repeat_frame : std_logic := '0'; -- CR591965
signal repeat_frame_nmbr : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); -- CR591965
signal s_h_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); -- CR582182
signal dm_prev_frame_number : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0'); -- CR582182
signal all_idle_d1 : std_logic := '0'; -- CR582182
signal all_idle_re : std_logic := '0'; -- CR582182
signal all_idle_i : std_logic := '0'; -- CR582182
signal late_idle : std_logic := '0'; -- CR582182
signal frame_sync_d1 : std_logic := '0';
signal frame_sync_d2 : std_logic := '0';
signal err_d1 : std_logic := '0';
-- Dynamic frame store support
signal num_fstore_minus1_cmb : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0) := (others => '0');
signal num_fstore_minus1 : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal num_fstore_equal_one : std_logic := '0';
signal fsize_mismatch_err_flag_i : std_logic := '0';
signal flag_to_repeat_after_fsize_less_err : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
fsize_mismatch_err_flag <= fsize_mismatch_err_flag_i ;
-- Number of fstore value set in register is 0x01.
num_fstore_equal_one <= '1' when num_fstore_minus1 = ZERO_VALUE(FRAME_NUMBER_WIDTH-1 downto 0)
else '0';
-- Pass errors to register module
dma_interr_set <= interr ;
dma_interr_set_minus_frame_errors <= interr_minus_frame_errors ;
dma_slverr_set <= slverr ;
dma_decerr_set <= decerr ;
-- Route out to map to reset module for halt/recover of datamover
fsize_mismatch_err <= fsize_mismatch_err_i; -- CR591965
lsize_mismatch_err <= lsize_mismatch_err_i; -- CR591965
lsize_more_mismatch_err <= lsize_more_mismatch_err_i; -- CR591965
-- Pass current vertical size out for line tracking in linebuffers
crnt_vsize <= crnt_vsize_i; -- CR575884
-- Pass out to allow masking of fsync_out when parameters are not valid.
valid_video_prmtrs <= video_prmtrs_valid;
all_idle <= all_idle_i; -- CR582182
--*****************************************************************************
-- Frame sync for incrementing frame_number. This sync is qualified with
-- video parameter valid to prevent incrementing frame_number on first frame.
-- So valid_frame_sync will assert after first frame and then every frame
-- after that.
--*****************************************************************************
-- Qualify frame sync with valid parameters to allow for
-- clean video startup
valid_frame_sync_i <= frame_sync and video_prmtrs_valid;
--*****************************************************************************
-- Frame Sync For Masking FSync OUT when shutting down channel for
-- FrmCntEn Mode and frame count reached. (cannot move in time)
--*****************************************************************************
-- Pass combinatorial version for frame_count enable masking in axi_vdma_fsync_gen.
valid_frame_sync_cmb <= valid_frame_sync_i;
--*****************************************************************************
-- INTIAL Frame Flag
-- Used to keep frame_number at Zero for intial frame
--*****************************************************************************
-- Flag used for intializing frame number to 0. Will
-- hold frame number at 0 until a valid frame sync
-- occurs.
REG_INITIAL_FRAME_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
initial_frame <= '0';
elsif(frame_sync = '1')then
initial_frame <= '1';
end if;
end if;
end process REG_INITIAL_FRAME_FLAG;
--*****************************************************************************
-- Frame Store Error Address (CR582182)
-- Frame number currently being operated on from a memory map perspective.
-- Needed because axi stream can complete significanly prior to memory map
-- completion on S2MM writes allowing for an external fsync to be seen before
-- all status is returned from datamover. This memory mapped based frame
-- number allows the correct frame store pointer to be updated to the
-- PARK_PTR_REF register during error events.
--*****************************************************************************
GEN_FRMSTORE_EXTFSYNC : if C_USE_FSYNC = 1 generate
begin
-- Register all idle to generate re pulse for error frame store process
REG_IDLE_RE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' )then
all_idle_d1 <= '0';
else
all_idle_d1 <= all_idle_i;
end if;
end if;
end process REG_IDLE_RE;
all_idle_re <= all_idle_i and not all_idle_d1;
-- Case 2: Fsync asserts before Idle
-- If this case and not case 3 (below) then do not sample
-- frame_number but use s_h_frame_number.
LATE_IDLE_CASE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or all_idle_re = '1' or video_prmtrs_valid = '0')then
late_idle <= '0';
elsif(frame_sync = '1' and all_idle_i = '0')then
late_idle <= '1';
end if;
end if;
end process LATE_IDLE_CASE;
-- Sample and hold frame number for special "late idle" case
-- i.e. when memory map write does not complete before external
-- fsync in asserts
S_H_FRAME : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
s_h_frame_number <= (others => '0');
elsif(frame_sync = '1')then
s_h_frame_number <= frame_number_i;
end if;
end if;
end process S_H_FRAME;
-- Sample current frame. If normal fsync to idle relationship
-- then pass frame_number. If idle occurs after fsync then
-- pass sample-n-held frame number.
---- REG_FRMSTORE_FRAME : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- -- Reset on reset and also on error delayed 1 to prevent re-assertion on transient
---- -- conditions causing wrong error frame to be logged.
---- --if(prmry_resetn = '0' or zero_size_err_d1 = '1')then
---- if(prmry_resetn = '0')then
---- frmstr_err_addr <= (others => '0');
---- update_frmstore <= '0';
----
---- -- On frame size mismatch, late idle will be asserted and need
---- -- to latch in last frame (i.e. sample and held frame) into
---- -- the frame store register.
---- elsif(late_idle = '1' and fsize_mismatch_err_i = '1')then
---- frmstr_err_addr <= s_h_frame_number;
---- update_frmstore <= '1';
----
---- -- CR591965 capture error frame for zero size and frm mismatch
---- -- needed because these two errors are detected at the completion
---- -- of a frame
---- --elsif(zero_size_err_re = '1')then
---- elsif(zero_size_err = '1' or fsize_mismatch_err_i = '1')then
---- frmstr_err_addr <= frame_number_i;
---- update_frmstore <= '1';
----
---- -- Not in Park mode and Idle occurs after fsync therefore
---- -- pass sample-n-held frm number
---- -- CR583667
---- --elsif(late_idle = '1' and all_idle_re = '1')then
---- elsif(late_idle = '1' and all_idle_re = '1' and circular_prk_mode = '1')then
---- frmstr_err_addr <= s_h_frame_number;
---- update_frmstore <= '1';
----
---- -- On idle assertion latch current frame number
---- -- CR583667
---- --elsif(all_idle_re = '1')then
---- elsif(all_idle_re = '1' or circular_prk_mode = '0')then
---- frmstr_err_addr <= frame_number_i;
---- update_frmstore <= '1';
---- --else
---- -- update_frmstore <= '0';
---- end if;
---- end if;
---- end process REG_FRMSTORE_FRAME;
frmstr_err_addr <= frame_number_i;
update_frmstore <= '1';
end generate GEN_FRMSTORE_EXTFSYNC;
-- If configured for internal fsync then can simply pass
-- frame number to framestore value.
GEN_FRMSTORE_INTFSYNC : if C_USE_FSYNC = 0 generate
begin
frmstr_err_addr <= frame_number_i;
update_frmstore <= '1';
end generate GEN_FRMSTORE_INTFSYNC;
--*****************************************************************************
-- Dynamic Frame Store Support
--*****************************************************************************
-- One less than setting of number of frame stores. Use for reverse
-- flag toggle
num_fstore_minus1_cmb <= std_logic_vector(unsigned(num_frame_store) - 1);
REG_NUM_FSTR_MINUS1 : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
num_fstore_minus1 <= (others =>'0');
else
num_fstore_minus1 <= num_fstore_minus1_cmb(FRAME_NUMBER_WIDTH-1 downto 0);
end if;
end if;
end process REG_NUM_FSTR_MINUS1;
--*****************************************************************************
-- Dynamic GenLock Slave Mode
--*****************************************************************************
-- Frame counter for Dynamic GenLock Slave Mode
DYNAMIC_SLAVE_MODE_FRAME_CNT : if C_GENLOCK_MODE = 3 generate
signal reg_frame_number_ds : std_logic_vector(FRAME_NUMBER_WIDTH-1 downto 0) := (others => '0');
signal rst_to_frame_zero : std_logic := '0';
signal valid_frame_sync_d1 : std_logic := '0';
--signal valid_frame_sync_d2 : std_logic := '0';
begin
-- Register qualified frame sync (i.e. valid parameters and frame_sync)
-- for use in IOC Threshold count wr to hold counter at intial
-- value until after first frame. This is done in axi_vdma_reg_module.vhd
DS_REG_VALID_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
valid_frame_sync <= '0';
valid_frame_sync_d1 <= '0';
valid_frame_sync_d2 <= '0';
else
valid_frame_sync_d1 <= valid_frame_sync_i;
valid_frame_sync_d2 <= valid_frame_sync_d1;
valid_frame_sync <= valid_frame_sync_d2;
end if;
end if;
end process DS_REG_VALID_FSYNC_OUT;
-- Frame sync for test vector, delay counter, and threshold counter
-- Register test vector signals out. Also used for
-- delay timer and threshold counter.
-- Mask with valid video parameters to prevent delay counter
-- from counting at start up for external fsyncs that can
-- be coming in long before starting.
-- Note: tstvect_fsync output needs to be aligned exactly
-- with valid_frame_sync output for use in register module to
-- reset threshold counter on first frame but not on subsequent
-- frames.
-- coverage off
DS_PROCESS_TSTVECTOR_REG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_fsync_d1 <= '0';
tstvect_fsync_d2 <= '0';
tstvect_fsync <= '0';
else
tstvect_fsync_d1 <= frame_sync;
tstvect_fsync_d2 <= tstvect_fsync_d1;
tstvect_fsync <= tstvect_fsync_d2
and video_prmtrs_valid;
end if;
end if;
end process DS_PROCESS_TSTVECTOR_REG;
-- coverage on
-- Pass frame number out for test vector
-- used in verification only
--tstvect_frame <= frame_number_i;
-- coverage off
DS_TSTVECT_FRM_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_frame <= (others => '0');
elsif (dmasr_halt = '0') then
tstvect_frame <= frame_number_i;
--else
-- tstvect_frame <= tstvect_frame;
end if;
end if;
end process DS_TSTVECT_FRM_OUT;
-- coverage on
-- Calculate frame to work on based on frame delay
DS_GEN_FSTORE_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
-- Register to break long timing paths
DS_REG_EXT_FRM_NUMBER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_frame_number_ds <= (others => '0');
else
reg_frame_number_ds <= slv_frame_ref_out;
end if;
end if;
end process DS_REG_EXT_FRM_NUMBER;
end generate DS_GEN_FSTORE_GRTR_ONE;
DS_GEN_FSTORE_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
reg_frame_number_ds <= slv_frame_ref_out;
end generate DS_GEN_FSTORE_EQL_ONE;
--*************************************************************************
--** VERIFICATION ONLY RTL
--*************************************************************************
-- coverage off
-- TSTVECT_FTPTR_OUT : process(reg_frame_number_ds)
DS_TSTVECT_FTPTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_frm_ptr_out <= (others => '0');
elsif (dmasr_halt = '0') then
tstvect_frm_ptr_out <= reg_frame_number_ds(FRAME_NUMBER_WIDTH-1 downto 0);
--else
--tstvect_frm_ptr_out <= tstvect_frm_ptr_out;
end if;
end if;
end process DS_TSTVECT_FTPTR_OUT;
-- coverage on
--*************************************************************************
--** END VERIFICATION ONLY RTL
--*************************************************************************
-------------------------------------------------------------------------------
-- Include State Machine and support logic
-------------------------------------------------------------------------------
rst_to_frame_zero <= '1' when (dmasr_halt = '1')
or (initial_frame = '0' and sync_enable = '0' and circular_prk_mode = '1')
else '0';
-- CR582183 incorrect frame delay on first frame
-- Delay fsync 2 pipeline stages to allow crnt_frmdly to propogate to
-- the correct value for frame_number_i sampling for genlock slave mode
DS_REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_sync_d1 <= '0';
frame_sync_d2 <= '0';
else
frame_sync_d1 <= frame_sync;
frame_sync_d2 <= frame_sync_d1;
end if;
end if;
end process DS_REG_DELAY_FSYNC;
-- Frame Number generation
DS_REG_FRAME_COUNT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear at reset or stopped or first valid fsync not occured
if(prmry_resetn = '0' or rst_to_frame_zero = '1')then
frame_number_i <= (others => '0');
-- GenLock Mode and Not in Park Mode (i.e. in tail ptr mode)
-- elsif(valid_frame_sync_i = '1' and sync_enable = '1' and circular_prk_mode = '1')then
-- latch with frame_sync when doing gen lock to proper capture initial frame ptr in.
-- CR582183 incorrect frame delay on first frame
--elsif(frame_sync = '1' and sync_enable = '1' and circular_prk_mode = '1')then
--elsif(frame_sync_d2 = '1' and sync_enable = '1' and circular_prk_mode = '1')then
--elsif(fsize_mismatch_err_flag_i= '1')then
elsif(flag_to_repeat_after_fsize_less_err= '1')then
frame_number_i <= frame_number_i;
elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and circular_prk_mode = '1')then
frame_number_i <= reg_frame_number_ds(FRAME_NUMBER_WIDTH-1 downto 0);
-- Otherwise all other changes are on frame sync boudnary.
elsif(valid_frame_sync_d2 = '1')then
-- If Park is enabled
if(circular_prk_mode = '0')then
frame_number_i <= frame_ptr_ref;
-- Frame count reached terminal count therefore roll count over
--elsif(frame_number_i = FRAME_NUMBER_TC)then
elsif(frame_number_i = num_fstore_minus1)then
frame_number_i <= (others => '0');
-- Increment frame count with each sync if valid prmtr values
-- stored.
else
frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1);
end if;
end if;
end if;
end process DS_REG_FRAME_COUNT;
frame_number <= frame_number_i;
--pass Dynamic Genlock Slave's current working frame number for grey encoding and then output
mstr_frame_ref_in <= frame_number_i;
REG_CURR_FRM_NUMBER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
chnl_current_frame <= (others => '0');
else
chnl_current_frame <= frame_number_i;
end if;
end if;
end process REG_CURR_FRM_NUMBER;
----chnl_current_frame <= frame_number_i;
----genlock_pair_frame <= slv_frame_ref_out;
REG_PAIR_FRM_NUMBER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
genlock_pair_frame <= (others => '0');
else
genlock_pair_frame <= slv_frame_ref_out;
end if;
end if;
end process REG_PAIR_FRM_NUMBER;
end generate DYNAMIC_SLAVE_MODE_FRAME_CNT;
--*****************************************************************************
-- GEN-LOCK Slave Mode
--*****************************************************************************
-- Frame counter for Gen-Lock Slave Mode
SLAVE_MODE_FRAME_CNT : if C_GENLOCK_MODE = 1 generate
constant ONE_FSTORE : std_logic_vector(NUM_FRM_STORE_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,NUM_FRM_STORE_WIDTH));
signal ext_frame_number_grtr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0');
signal ext_frame_number_lesr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0');
signal reg_frame_number_grtr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0');
signal reg_frame_number_lesr : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0');
signal ext_slv_frmref : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0');
signal ext_crnt_frmdly : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0');
signal ext_num_fstore : std_logic_vector(NUM_FRM_STORE_WIDTH downto 0) := (others => '0');
signal rst_to_frame_zero : std_logic := '0';
signal valid_frame_sync_d1 : std_logic := '0';
--signal valid_frame_sync_d2 : std_logic := '0';
begin
-- Register qualified frame sync (i.e. valid parameters and frame_sync)
-- for use in IOC Threshold count wr to hold counter at intial
-- value until after first frame. This is done in axi_vdma_reg_module.vhd
S_REG_VALID_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
valid_frame_sync <= '0';
valid_frame_sync_d1 <= '0';
valid_frame_sync_d2 <= '0';
else
valid_frame_sync_d1 <= valid_frame_sync_i;
valid_frame_sync_d2 <= valid_frame_sync_d1;
valid_frame_sync <= valid_frame_sync_d2;
end if;
end if;
end process S_REG_VALID_FSYNC_OUT;
-- Frame sync for test vector, delay counter, and threshold counter
-- Register test vector signals out. Also used for
-- delay timer and threshold counter.
-- Mask with valid video parameters to prevent delay counter
-- from counting at start up for external fsyncs that can
-- be coming in long before starting.
-- Note: tstvect_fsync output needs to be aligned exactly
-- with valid_frame_sync output for use in register module to
-- reset threshold counter on first frame but not on subsequent
-- frames.
S_PROCESS_TSTVECTOR_REG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_fsync_d1 <= '0';
tstvect_fsync_d2 <= '0';
tstvect_fsync <= '0';
else
tstvect_fsync_d1 <= frame_sync;
tstvect_fsync_d2 <= tstvect_fsync_d1;
tstvect_fsync <= tstvect_fsync_d2
and video_prmtrs_valid;
end if;
end if;
end process S_PROCESS_TSTVECTOR_REG;
-- Pass frame number out for test vector
-- used in verification only
--tstvect_frame <= frame_number_i;
-- coverage off
S_TSTVECT_FRM_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_frame <= (others => '0');
elsif (dmasr_halt = '0') then
tstvect_frame <= frame_number_i;
--else
-- tstvect_frame <= tstvect_frame;
end if;
end if;
end process S_TSTVECT_FRM_OUT;
-- coverage on
-- Calculate frame to work on based on frame delay
GEN_FSTORE_GRTR_ONE : if C_NUM_FSTORES > 1 generate
begin
-- Extend unsigned vectors by 1 bit to allow for
-- carry out during addition.
--ext_slv_frmref <= '0' & slv_frame_ref_out;
--ext_crnt_frmdly <= '0' & crnt_frmdly;
ext_slv_frmref <= "00" & slv_frame_ref_out;
ext_crnt_frmdly <= "00" & crnt_frmdly;
ext_num_fstore <= '0' & num_frame_store;
-- Calculate for when frame delay less than or equal to slave frame ref. This is
-- normal operation where a simple subtraction of frame delay from slave frame ref
-- will work.
ext_frame_number_lesr <= std_logic_vector(unsigned(ext_slv_frmref)
- unsigned(ext_crnt_frmdly));
-- Calculate for when frame delay greater than slave frame ref. This is roll-over
-- point, i.e. if slave frame ref = 0 then you want frame number to be C_NUM_FSTORES-1
-- This can be calculated with (C_NUM_FSTORES + Slave Frame Ref) - Frame Delay
--ext_frame_number_grtr <= std_logic_vector( (C_NUM_FSTORES + unsigned(ext_slv_frmref))
-- - unsigned(ext_crnt_frmdly));
ext_frame_number_grtr <= std_logic_vector( (unsigned(ext_num_fstore) + unsigned(ext_slv_frmref))
- unsigned(ext_crnt_frmdly));
-- Register to break long timing paths
REG_EXT_FRM_NUMBER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
reg_frame_number_grtr <= (others => '0');
reg_frame_number_lesr <= (others => '0');
-- If frame stores set to 1 then simply pass unmodified version
-- through
elsif(num_frame_store = ONE_FSTORE)then
reg_frame_number_grtr <= ext_slv_frmref;
reg_frame_number_lesr <= ext_slv_frmref;
else
reg_frame_number_grtr <= ext_frame_number_grtr;
reg_frame_number_lesr <= ext_frame_number_lesr;
end if;
end if;
end process REG_EXT_FRM_NUMBER;
end generate GEN_FSTORE_GRTR_ONE;
-- For frame stores = 1 then frame delay has no meaning.
GEN_FSTORE_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
reg_frame_number_grtr <= ext_slv_frmref;
reg_frame_number_lesr <= ext_slv_frmref;
end generate GEN_FSTORE_EQL_ONE;
--*************************************************************************
--** VERIFICATION ONLY RTL
--*************************************************************************
-- coverage off
---- TSTVECT_FTPTR_OUT : process(crnt_frmdly,
---- slv_frame_ref_out,
---- reg_frame_number_lesr,
---- reg_frame_number_grtr)
---- begin
---- if(crnt_frmdly <= slv_frame_ref_out)then
---- tstvect_frm_ptr_out <= reg_frame_number_lesr(FRAME_NUMBER_WIDTH-1 downto 0);
---- else
---- tstvect_frm_ptr_out <= reg_frame_number_grtr(FRAME_NUMBER_WIDTH-1 downto 0);
---- end if;
---- end process TSTVECT_FTPTR_OUT;
S_TSTVECT_FTPTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_frm_ptr_out <= (others => '0');
elsif (dmasr_halt = '0') then
if(crnt_frmdly <= slv_frame_ref_out)then
tstvect_frm_ptr_out <= reg_frame_number_lesr(FRAME_NUMBER_WIDTH-1 downto 0);
else
tstvect_frm_ptr_out <= reg_frame_number_grtr(FRAME_NUMBER_WIDTH-1 downto 0);
end if;
--else
--tstvect_frm_ptr_out <= tstvect_frm_ptr_out;
end if;
end if;
end process S_TSTVECT_FTPTR_OUT;
-- coverage on
--*************************************************************************
--** END VERIFICATION ONLY RTL
--*************************************************************************
-------------------------------------------------------------------------------
-- Include State Machine and support logic
-------------------------------------------------------------------------------
rst_to_frame_zero <= '1' when (dmasr_halt = '1')
or (initial_frame = '0' and sync_enable = '0' and circular_prk_mode = '1')
else '0';
-- CR582183 incorrect frame delay on first frame
-- Delay fsync 2 pipeline stages to allow crnt_frmdly to propogate to
-- the correct value for frame_number_i sampling for genlock slave mode
REG_DELAY_FSYNC : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
frame_sync_d1 <= '0';
frame_sync_d2 <= '0';
else
frame_sync_d1 <= frame_sync;
frame_sync_d2 <= frame_sync_d1;
end if;
end if;
end process REG_DELAY_FSYNC;
-- Frame Number generation
REG_FRAME_COUNT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear at reset or stopped or first valid fsync not occured
if(prmry_resetn = '0' or rst_to_frame_zero = '1')then
frame_number_i <= (others => '0');
-- GenLock Mode and Not in Park Mode (i.e. in tail ptr mode)
-- elsif(valid_frame_sync_i = '1' and sync_enable = '1' and circular_prk_mode = '1')then
-- latch with frame_sync when doing gen lock to proper capture initial frame ptr in.
-- CR582183 incorrect frame delay on first frame
--elsif(frame_sync = '1' and sync_enable = '1' and circular_prk_mode = '1')then
--elsif(fsize_mismatch_err_flag_i= '1')then
elsif(flag_to_repeat_after_fsize_less_err= '1')then
frame_number_i <= frame_number_i;
elsif(frame_sync_d2 = '1' and sync_enable = '1' and circular_prk_mode = '1')then
-- If frame delay less than or equal slave frame reference
-- then simply subtract
if(crnt_frmdly <= slv_frame_ref_out)then
frame_number_i <= reg_frame_number_lesr(FRAME_NUMBER_WIDTH-1 downto 0);
else
frame_number_i <= reg_frame_number_grtr(FRAME_NUMBER_WIDTH-1 downto 0);
end if;
-- Otherwise all other changes are on frame sync boudnary.
elsif(valid_frame_sync_d2 = '1')then
-- If Park is enabled
if(circular_prk_mode = '0')then
frame_number_i <= frame_ptr_ref;
-- Frame count reached terminal count therefore roll count over
--elsif(frame_number_i = FRAME_NUMBER_TC)then
elsif(frame_number_i = num_fstore_minus1)then
frame_number_i <= (others => '0');
-- Increment frame count with each sync if valid prmtr values
-- stored.
else
frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1);
end if;
end if;
end if;
end process REG_FRAME_COUNT;
frame_number <= frame_number_i;
--pass Genlock Slave's current working frame number for grey encoding and then output -- CR 703788
--mstr_frame_ref_in <= (others => '0'); -- Not Used in Slave Mode
mstr_frame_ref_in <= frame_number_i; -- CR 703788
REG_CURR_FRM_NUMBER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
chnl_current_frame <= (others => '0');
else
chnl_current_frame <= frame_number_i;
end if;
end if;
end process REG_CURR_FRM_NUMBER;
----chnl_current_frame <= frame_number_i;
----genlock_pair_frame <= slv_frame_ref_out;
REG_PAIR_FRM_NUMBER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
genlock_pair_frame <= (others => '0');
else
genlock_pair_frame <= slv_frame_ref_out;
end if;
end if;
end process REG_PAIR_FRM_NUMBER;
end generate SLAVE_MODE_FRAME_CNT;
--*****************************************************************************
-- Dynamic GenLock Master Mode
--*****************************************************************************
-- Frame counter for Gen-Lock Master Mode
DYNAMIC_MASTER_MODE_FRAME_CNT : if C_GENLOCK_MODE = 2 generate
signal valid_frame_sync_d1 : std_logic := '0';
--signal flag_to_repeat_after_fsize_less_err : std_logic := '0';
--signal valid_frame_sync_d2 : std_logic := '0';
begin
-- Register qualified frame sync (i.e. valid parameters and frame_sync)
-- for use in IOC Threshold count wr to hold counter at intial
-- value until after first frame. This is done in axi_vdma_reg_module.vhd
DM_REG_VALID_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
valid_frame_sync <= '0';
valid_frame_sync_d1 <= '0';
valid_frame_sync_d2 <= '0';
else
valid_frame_sync_d1 <= valid_frame_sync_i;
valid_frame_sync_d2 <= valid_frame_sync_d1;
valid_frame_sync <= valid_frame_sync_d2;
end if;
end if;
end process DM_REG_VALID_FSYNC_OUT;
-- Frame sync for test vector, delay counter, and threshold counter
-- Register test vector signals out. Also used for
-- delay timer and threshold counter.
---- DM_PROCESS_TSTVECTOR_REG : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- tstvect_fsync_d1<= '0';
---- tstvect_fsync_d2<= '0';
---- tstvect_frame <= (others => '0');
---- else
---- tstvect_fsync_d1<= frame_sync;
---- tstvect_fsync_d2<= tstvect_fsync_d1;
---- tstvect_frame <= frame_number_i;
---- end if;
---- end if;
---- end process DM_PROCESS_TSTVECTOR_REG;
-- coverage off
DM_PROCESS_TSTVECTOR_REG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_fsync_d1 <= '0';
tstvect_fsync_d2 <= '0';
tstvect_fsync <= '0';
else
tstvect_fsync_d1 <= frame_sync;
tstvect_fsync_d2 <= tstvect_fsync_d1;
tstvect_fsync <= tstvect_fsync_d2
and video_prmtrs_valid;
end if;
end if;
end process DM_PROCESS_TSTVECTOR_REG;
DM_TSTVECT_FRM_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_frame <= (others => '0');
elsif (dmasr_halt = '0') then
tstvect_frame <= frame_number_i;
--else
-- tstvect_frame <= tstvect_frame;
end if;
end if;
end process DM_TSTVECT_FRM_OUT;
-- coverage on
-- Mask with valid video parameters to prevent delay counter
-- from counting at start up for external fsyncs that can
-- be coming in long before starting.
-- video_prmtrs_valid asserts on clock cycle following assertion
-- of frame_sync, thus pipeline delay to create tstvect_fsync_d1
-- is required to assert first fsync for first valid frame
-- Note: tstvect_fsync output needs to be aligned exactly
-- with valid_frame_sync output for use in register module to
-- reset threshold counter on first frame but not on subsequent
-- frames.
--tstvect_fsync <= tstvect_fsync_d1 and video_prmtrs_valid;
--tstvect_fsync <= tstvect_fsync_d2 and video_prmtrs_valid;
DM_GEN_FSTORE_GRTR_TWO : if C_NUM_FSTORES > 2 generate
begin
-------------------------------------------------------------------------------
-- Include State Machine and support logic
-------------------------------------------------------------------------------
-- Frame Number generation
DM_REG_FRAME_COUNT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear at reset or stopped or first valid fsync not occured
if(prmry_resetn = '0' or dmasr_halt = '1'
or (circular_prk_mode = '1' and initial_frame = '0') or num_fstore_equal_one = '1')then
frame_number_i <= (others => '0');
-- If Park is enabled then on frame sync transision to
-- frame pointer reference.
--elsif(fsize_mismatch_err_flag_i= '1')then
elsif(flag_to_repeat_after_fsize_less_err= '1')then
frame_number_i <= frame_number_i;
elsif(valid_frame_sync_d2 = '1' and circular_prk_mode = '0')then
frame_number_i <= frame_ptr_ref;
------------------------------------------------------------------------------------------------------------
-- On Repeat Frame simply hold current frame number (CR591965)
--elsif(repeat_frame = '1')then
elsif(repeat_frame = '1' and dmacr_repeat_en = '1')then
frame_number_i <= repeat_frame_nmbr;
------------------------------------------------------------------------------------------------------------
-- Frame count reached terminal count therefore roll count over
--elsif(valid_frame_sync_i = '1' and frame_number_i = FRAME_NUMBER_TC)then
elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and frame_number_i = num_fstore_minus1 and (slv_frame_ref_out /= "00000"))then
frame_number_i <= (others => '0');
elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and frame_number_i = num_fstore_minus1 and (slv_frame_ref_out = "00000"))then
frame_number_i <= "00001";
elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and slv_frame_ref_out = num_fstore_minus1 and (frame_number_i = std_logic_vector(unsigned(slv_frame_ref_out) - 1)))then
frame_number_i <= (others => '0');
elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (slv_frame_ref_out /= num_fstore_minus1) and (slv_frame_ref_out /= "00000") and (frame_number_i = std_logic_vector(unsigned(slv_frame_ref_out) - 1)))then
frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 2);
-- Increment frame count with each sync if valid prmtr values
-- stored.
elsif(valid_frame_sync_d2 = '1' and frame_number_i = num_fstore_minus1)then
frame_number_i <= (others => '0');
elsif(valid_frame_sync_d2 = '1')then
frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1);
end if;
end if;
end process DM_REG_FRAME_COUNT;
end generate DM_GEN_FSTORE_GRTR_TWO;
DM_GEN_FSTORES_EQL_TWO : if C_NUM_FSTORES = 2 generate
begin
-------------------------------------------------------------------------------
-- Include State Machine and support logic
-------------------------------------------------------------------------------
-- Frame Number generation
DM_REG_FRAME_COUNT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear at reset or stopped or first valid fsync not occured
if(prmry_resetn = '0' or dmasr_halt = '1'
or (circular_prk_mode = '1' and initial_frame = '0') or num_fstore_equal_one = '1')then
frame_number_i <= (others => '0');
-- If Park is enabled then on frame sync transision to
-- frame pointer reference.
--elsif(fsize_mismatch_err_flag_i= '1')then
elsif(flag_to_repeat_after_fsize_less_err= '1')then
frame_number_i <= frame_number_i;
elsif(valid_frame_sync_d2 = '1' and circular_prk_mode = '0')then
frame_number_i <= frame_ptr_ref;
------------------------------------------------------------------------------------------------------------
-- On Repeat Frame simply hold current frame number (CR591965)
--elsif(repeat_frame = '1')then
elsif(repeat_frame = '1' and dmacr_repeat_en = '1')then
frame_number_i <= repeat_frame_nmbr;
------------------------------------------------------------------------------------------------------------
-- Frame count reached terminal count therefore roll count over
--elsif(valid_frame_sync_i = '1' and frame_number_i = FRAME_NUMBER_TC)then
elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00001") and (slv_frame_ref_out = "00001"))then
frame_number_i <= (others => '0');
elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00001") and (slv_frame_ref_out = "00000"))then
frame_number_i <= "00001";
elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00000") and (slv_frame_ref_out = "00001"))then
frame_number_i <= (others => '0');
elsif(valid_frame_sync_d2 = '1' and sync_enable = '1' and (frame_number_i = "00000") and (slv_frame_ref_out = "00000"))then
frame_number_i <="00001" ;
elsif(valid_frame_sync_d2 = '1' and frame_number_i = "00001")then
frame_number_i <= (others => '0');
elsif(valid_frame_sync_d2 = '1' and frame_number_i = "00000")then
frame_number_i <="00001" ;
end if;
end if;
end process DM_REG_FRAME_COUNT;
end generate DM_GEN_FSTORES_EQL_TWO;
DM_GEN_FSTORES_EQL_ONE : if C_NUM_FSTORES = 1 generate
begin
frame_number_i <= (others => '0');
end generate DM_GEN_FSTORES_EQL_ONE;
DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF : if C_MM2S_SOF_ENABLE = 1 or C_S2MM_SOF_ENABLE = 1 generate
begin
DM_REPEAT_EN_FSIZE_LESS_ERR_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then
flag_to_repeat_after_fsize_less_err <= '0';
elsif(fsize_mismatch_err_i = '1')then
flag_to_repeat_after_fsize_less_err <= '1';
end if;
end if;
end process DM_REPEAT_EN_FSIZE_LESS_ERR_FLAG;
end generate DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF;
DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF : if C_MM2S_SOF_ENABLE = 0 and C_S2MM_SOF_ENABLE = 0 generate
begin
flag_to_repeat_after_fsize_less_err <= '0';
end generate DM_GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF;
-- If flush on frame sync enabled and genlock repeat frame enabled
-- then repeat errored frame on next frame sync. (CR591965)
-- DM_GEN_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 1 and C_ENABLE_FLUSH_ON_FSYNC = 1 generate
-- begin
DM_REPEAT_FRAME_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
----if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then
if(prmry_resetn = '0' or (valid_frame_sync_d2 = '1' and flag_to_repeat_after_fsize_less_err = '0'))then
repeat_frame_nmbr <= (others => '0');
repeat_frame <= '0';
-- Frame size mismatch
elsif(fsize_mismatch_err_i='1' or flag_to_repeat_after_fsize_less_err = '1')then
repeat_frame_nmbr <= s_h_frame_number;
repeat_frame <= '1';
-- Line size mismatch
elsif(lsize_mismatch_err_i='1' or lsize_more_mismatch_err_i ='1')then
repeat_frame_nmbr <= frame_number_i;
repeat_frame <= '1';
end if;
end if;
end process DM_REPEAT_FRAME_PROCESS;
-- end generate DM_GEN_REPEAT_FRM_LOGIC;
---- -- Not in flush on frame sync mode or repeat frame not enabled (CR591965)
---- DM_GEN_NO_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 0 or C_ENABLE_FLUSH_ON_FSYNC = 0 generate
---- begin
---- -- never repeat frame
---- repeat_frame <= '0';
---- repeat_frame_nmbr <= (others => '0');
----
---- end generate DM_GEN_NO_REPEAT_FRM_LOGIC;
-- Pass Frame sync to video
mstr_frame_ref_in <= dm_prev_frame_number;
-- Pass frame number out to register module
frame_number <= frame_number_i;
-- Drive test vector to zero for GenLock master mode
--tstvect_frm_ptr_out <= (others => '0');
-- Drive test vector for Dynamic GenLock master mode
--tstvect_frm_ptr_out <= slv_frame_ref_out;
-- coverage off
-- TSTVECT_FTPTR_OUT : process(reg_frame_number_ds)
DM_TSTVECT_FTPTR_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_frm_ptr_out <= (others => '0');
elsif (dmasr_halt = '0') then
tstvect_frm_ptr_out <= slv_frame_ref_out;
--else
--tstvect_frm_ptr_out <= tstvect_frm_ptr_out;
end if;
end if;
end process DM_TSTVECT_FTPTR_OUT;
-- coverage on
DM_PREV_FRAME : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
dm_prev_frame_number <= (others => '0');
--elsif(valid_frame_sync_d2 = '1'and repeat_frame = '0' and fsize_mismatch_err_flag_i = '0')then
----elsif(valid_frame_sync_d2 = '1'and repeat_frame = '0' and flag_to_repeat_after_fsize_less_err = '0')then
elsif(valid_frame_sync_d2 = '1'and (dmacr_repeat_en = '0' or repeat_frame = '0') and flag_to_repeat_after_fsize_less_err = '0')then
dm_prev_frame_number <= frame_number_i;
end if;
end if;
end process DM_PREV_FRAME;
REG_CURR_FRM_NUMBER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
chnl_current_frame <= (others => '0');
else
chnl_current_frame <= frame_number_i;
end if;
end if;
end process REG_CURR_FRM_NUMBER;
----chnl_current_frame <= frame_number_i;
----genlock_pair_frame <= slv_frame_ref_out;
REG_PAIR_FRM_NUMBER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
genlock_pair_frame <= (others => '0');
else
genlock_pair_frame <= slv_frame_ref_out;
end if;
end if;
end process REG_PAIR_FRM_NUMBER;
end generate DYNAMIC_MASTER_MODE_FRAME_CNT;
--*****************************************************************************
-- GEN-LOCK MASTER Mode
--*****************************************************************************
-- Frame counter for Gen-Lock Master Mode
MASTER_MODE_FRAME_CNT : if C_GENLOCK_MODE = 0 generate
signal valid_frame_sync_d1 : std_logic := '0';
--signal flag_to_repeat_after_fsize_less_err : std_logic := '0';
--signal valid_frame_sync_d2 : std_logic := '0';
begin
-- Register qualified frame sync (i.e. valid parameters and frame_sync)
-- for use in IOC Threshold count wr to hold counter at intial
-- value until after first frame. This is done in axi_vdma_reg_module.vhd
M_REG_VALID_FSYNC_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
valid_frame_sync <= '0';
valid_frame_sync_d1 <= '0';
valid_frame_sync_d2 <= '0';
else
valid_frame_sync_d1 <= valid_frame_sync_i;
valid_frame_sync_d2 <= valid_frame_sync_d1;
valid_frame_sync <= valid_frame_sync_d2;
end if;
end if;
end process M_REG_VALID_FSYNC_OUT;
---- REG_VALID_FSYNC_OUT : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- valid_frame_sync <= '0';
---- else
---- valid_frame_sync <= valid_frame_sync_i;
---- end if;
---- end if;
---- end process REG_VALID_FSYNC_OUT;
-- Frame sync for test vector, delay counter, and threshold counter
-- Register test vector signals out. Also used for
-- delay timer and threshold counter.
---- PROCESS_TSTVECTOR_REG : process(prmry_aclk)
---- begin
---- if(prmry_aclk'EVENT and prmry_aclk = '1')then
---- if(prmry_resetn = '0')then
---- tstvect_fsync_d1<= '0';
---- tstvect_frame <= (others => '0');
---- else
---- tstvect_fsync_d1<= frame_sync;
---- tstvect_frame <= frame_number_i;
---- end if;
---- end if;
---- end process PROCESS_TSTVECTOR_REG;
-- coverage off
M_TSTVECT_FRM_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_frame <= (others => '0');
elsif (dmasr_halt = '0') then
tstvect_frame <= frame_number_i;
--else
-- tstvect_frame <= tstvect_frame;
end if;
end if;
end process M_TSTVECT_FRM_OUT;
M_PROCESS_TSTVECTOR_REG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
tstvect_fsync_d1 <= '0';
tstvect_fsync_d2 <= '0';
tstvect_fsync <= '0';
else
tstvect_fsync_d1 <= frame_sync;
tstvect_fsync_d2 <= tstvect_fsync_d1;
tstvect_fsync <= tstvect_fsync_d2
and video_prmtrs_valid;
end if;
end if;
end process M_PROCESS_TSTVECTOR_REG;
-- coverage on
-- Mask with valid video parameters to prevent delay counter
-- from counting at start up for external fsyncs that can
-- be coming in long before starting.
-- video_prmtrs_valid asserts on clock cycle following assertion
-- of frame_sync, thus pipeline delay to create tstvect_fsync_d1
-- is required to assert first fsync for first valid frame
-- Note: tstvect_fsync output needs to be aligned exactly
-- with valid_frame_sync output for use in register module to
-- reset threshold counter on first frame but not on subsequent
-- frames.
--tstvect_fsync <= tstvect_fsync_d1 and video_prmtrs_valid;
-------------------------------------------------------------------------------
-- Include State Machine and support logic
-------------------------------------------------------------------------------
-- Frame Number generation
REG_FRAME_COUNT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear at reset or stopped or first valid fsync not occured
if(prmry_resetn = '0' or dmasr_halt = '1'
or (circular_prk_mode = '1' and initial_frame = '0'))then
frame_number_i <= (others => '0');
-- If Park is enabled then on frame sync transision to
-- frame pointer reference.
--elsif(fsize_mismatch_err_flag_i= '1')then
elsif(flag_to_repeat_after_fsize_less_err= '1')then
frame_number_i <= frame_number_i;
elsif(valid_frame_sync_d2 = '1' and circular_prk_mode = '0')then
frame_number_i <= frame_ptr_ref;
-- On Repeat Frame simply hold current frame number (CR591965)
--elsif(repeat_frame = '1')then
elsif(repeat_frame = '1' and dmacr_repeat_en = '1')then
frame_number_i <= repeat_frame_nmbr;
-- Frame count reached terminal count therefore roll count over
--elsif(valid_frame_sync_i = '1' and frame_number_i = FRAME_NUMBER_TC)then
elsif(valid_frame_sync_d2 = '1' and frame_number_i = num_fstore_minus1)then
frame_number_i <= (others => '0');
-- Increment frame count with each sync if valid prmtr values
-- stored.
elsif(valid_frame_sync_d2 = '1' and video_prmtrs_valid = '1')then
frame_number_i <= std_logic_vector(unsigned(frame_number_i) + 1);
end if;
end if;
end process REG_FRAME_COUNT;
GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF : if C_MM2S_SOF_ENABLE = 1 or C_S2MM_SOF_ENABLE = 1 generate
begin
REPEAT_EN_FSIZE_LESS_ERR_FLAG : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then
flag_to_repeat_after_fsize_less_err <= '0';
elsif(fsize_mismatch_err_i = '1')then
flag_to_repeat_after_fsize_less_err <= '1';
end if;
end if;
end process REPEAT_EN_FSIZE_LESS_ERR_FLAG;
end generate GEN_REPEAT_FRM_FSIZE_LESS_ERR_SOF;
GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF : if C_MM2S_SOF_ENABLE = 0 and C_S2MM_SOF_ENABLE = 0 generate
begin
flag_to_repeat_after_fsize_less_err <= '0';
end generate GEN_REPEAT_FRM_FSIZE_LESS_ERR_NO_SOF;
-- If flush on frame sync enabled and genlock repeat frame enabled
-- then repeat errored frame on next frame sync. (CR591965)
-- GEN_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 1 and C_ENABLE_FLUSH_ON_FSYNC = 1 generate
-- begin
REPEAT_FRAME_PROCESS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
----if(prmry_resetn = '0' or valid_frame_sync_d2 = '1')then
if(prmry_resetn = '0' or (valid_frame_sync_d2 = '1' and flag_to_repeat_after_fsize_less_err = '0'))then
repeat_frame_nmbr <= (others => '0');
repeat_frame <= '0';
-- Frame size mismatch
--elsif(fsize_mismatch_err_i='1')then
elsif(fsize_mismatch_err_i='1' or flag_to_repeat_after_fsize_less_err='1')then
repeat_frame_nmbr <= s_h_frame_number;
repeat_frame <= '1';
-- Line size mismatch
elsif(lsize_mismatch_err_i='1' or lsize_more_mismatch_err_i ='1')then
repeat_frame_nmbr <= frame_number_i;
repeat_frame <= '1';
end if;
end if;
end process REPEAT_FRAME_PROCESS;
--end generate GEN_REPEAT_FRM_LOGIC;
---- -- Not in flush on frame sync mode or repeat frame not enabled (CR591965)
---- GEN_NO_REPEAT_FRM_LOGIC : if C_GENLOCK_REPEAT_EN = 0 or C_ENABLE_FLUSH_ON_FSYNC = 0 generate
---- begin
---- -- never repeat frame
---- repeat_frame <= '0';
---- repeat_frame_nmbr <= (others => '0');
----
---- end generate GEN_NO_REPEAT_FRM_LOGIC;
-- Pass Frame sync to video
mstr_frame_ref_in <= frame_number_i;
-- Pass frame number out to register module
frame_number <= frame_number_i;
-- Drive test vector to zero for master mode
tstvect_frm_ptr_out <= (others => '0');
----chnl_current_frame <= frame_number_i;
REG_CURR_FRM_NUMBER : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
chnl_current_frame <= (others => '0');
else
chnl_current_frame <= frame_number_i;
end if;
end if;
end process REG_CURR_FRM_NUMBER;
----chnl_current_frame <= frame_number_i;
genlock_pair_frame <= (others => '0');
end generate MASTER_MODE_FRAME_CNT;
--*****************************************************************************
-- Error Handling
-- For graceful shut down logic
--*****************************************************************************
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg fetch error
-- SG fetch error included because need to shut down because data maybe corrupt
-- therefor do not want to issue the xfer command to primary datamover
-- Added run_stop to assertion for when run_stop is de-asserted in middle of video
-- frame need to halt datamover to clear out potential pending commands.
stop_i <= dma_err -- DMAIntErr, DMADecErr, DMASlvErr, ZeroSize, possibly Frame/Line Mismatch
or ftch_err -- SGDecErr, SGSlvErr
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
stop <= '0';
else
stop <= stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- For verification only - drive error detection
-- out to test vector port, will be stripped during build
-- (Broke up in order to capture all errors regardless of
-- flush on frame sync mode)
-- coverage off
REG_DELAY_ERR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
err_d1 <= '0';
tstvect_err <= '0';
else
err_d1 <= slverr -- DMASlvErr
or decerr -- DMADecErr
or interr -- DMAIntErr, ZeroSize, Frame
or lsize_mismatch_err_i -- Line Mismatch
or lsize_more_mismatch_err_i -- Line Mismatch
or ftch_err; -- SGSlvErr, SGDecErr
tstvect_err <= err_d1;
end if;
end if;
end process REG_DELAY_ERR;
-- coverage on
--*****************************************************************************
-- DMA Control
--*****************************************************************************
---------------------------------------------------------------------------
-- Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_SM : entity axi_vdma_v6_2_8.axi_vdma_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_INCLUDE_SF => C_INCLUDE_SF ,
C_USE_FSYNC => C_USE_FSYNC , -- CR591965
C_ENABLE_FLUSH_ON_FSYNC => C_ENABLE_FLUSH_ON_FSYNC , -- CR591965
C_EXTEND_DM_COMMAND => C_EXTEND_DM_COMMAND ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_MM2S_SOF_ENABLE => C_MM2S_SOF_ENABLE ,
C_S2MM_SOF_ENABLE => C_S2MM_SOF_ENABLE ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
scndry_aclk => scndry_aclk ,
scndry_resetn => scndry_resetn ,
-- AXI Stream Qualifiers
packet_sof => packet_sof ,
-- Raw fsync (must use unqualified frame sync for proper sm operation)
frame_sync => frame_sync ,
-- Valid video parameter available
video_prmtrs_valid => video_prmtrs_valid ,
-- Control and Status
run_stop => run_stop ,
cmnd_idle => cmnd_idle ,
sts_idle => sts_idle ,
stop => stop_i ,
halt => halt ,
zero_size_err => zero_size_err ,
mm2s_fsync_out_m => mm2s_fsync_out_m ,
s2mm_fsync_out_m => s2mm_fsync_out_m ,
mm2s_fsize_mismatch_err_s => mm2s_fsize_mismatch_err_s ,
mm2s_fsize_mismatch_err_m => mm2s_fsize_mismatch_err_m ,
s2mm_fsize_mismatch_err_s => s2mm_fsize_mismatch_err_s ,
fsize_mismatch_err_flag => fsize_mismatch_err_flag_i ,
fsize_mismatch_err => fsize_mismatch_err_i , -- CR591965
all_lines_xfred => all_lines_xfred , -- CR616211
all_lasts_rcvd => all_lasts_rcvd ,
drop_fsync_d_pulse_gen_fsize_less_err => drop_fsync_d_pulse_gen_fsize_less_err ,
s2mm_strm_all_lines_rcvd => s2mm_strm_all_lines_rcvd , -- : out std_logic;
s2mm_fsync_core => s2mm_fsync_core , -- : out std_logic;
-- DataMover Command/Status
cmnd_wr => cmnd_wr ,
cmnd_data => cmnd_data ,
cmnd_pending => cmnd_pending ,
sts_received => sts_received ,
-- Descriptor Fields
crnt_start_address => crnt_start_address ,
crnt_vsize => crnt_vsize_i , -- CR575884
crnt_hsize => crnt_hsize ,
crnt_stride => crnt_stride
);
-- If Scatter Gather engine is included then instantiate scatter gather
-- interface
GEN_SG_INTERFACE : if C_INCLUDE_SG = 1 generate
begin
---------------------------------------------------------------------------
-- Scatter Gather State Machine
---------------------------------------------------------------------------
I_SG_IF : entity axi_vdma_v6_2_8.axi_vdma_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
dmasr_halt => dmasr_halt ,
ftch_idle => ftch_idle ,
ftch_complete => ftch_complete ,
ftch_complete_clr => ftch_complete_clr ,
-- SG Descriptor Fetch AXI Stream In
m_axis_ftch_tdata => m_axis_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ftch_tready ,
m_axis_ftch_tlast => m_axis_ftch_tlast ,
-- Descriptor Field Output
new_curdesc => new_curdesc ,
new_curdesc_wren => new_curdesc_wren ,
desc_data_wren => desc_data_wren ,
desc_strtaddress => desc_strtaddress ,
desc_vsize => desc_vsize ,
desc_hsize => desc_hsize ,
desc_stride => desc_stride ,
desc_frmdly => desc_frmdly
);
end generate GEN_SG_INTERFACE;
-- If Scatter Gather engine is excluded then tie off unused signals
GEN_NO_SG_INTERFACE : if C_INCLUDE_SG = 0 generate
begin
-- Map update complete to ftch_complete signal for proper
-- video paramter transfer from axi_lite registers to video registers
ftch_complete <= prmtr_updt_complete;
-- Signals not need for register direct mode
m_axis_ftch_tready <= '0';
new_curdesc <= (others => '0');
new_curdesc_wren <= '0';
desc_data_wren <= '0';
desc_strtaddress <= (others => '0');
desc_vsize <= (others => '0');
desc_hsize <= (others => '0');
desc_stride <= (others => '0');
desc_frmdly <= (others => '0');
end generate GEN_NO_SG_INTERFACE;
-------------------------------------------------------------------------------
-- Primary DataMover command status interface
-------------------------------------------------------------------------------
I_CMDSTS : entity axi_vdma_v6_2_8.axi_vdma_cmdsts_if
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
--C_ENABLE_DEBUG_INFO => C_ENABLE_DEBUG_INFO ,
C_ENABLE_DEBUG_ALL => C_ENABLE_DEBUG_ALL ,
C_ENABLE_DEBUG_INFO_0 => C_ENABLE_DEBUG_INFO_0 ,
C_ENABLE_DEBUG_INFO_1 => C_ENABLE_DEBUG_INFO_1 ,
C_ENABLE_DEBUG_INFO_2 => C_ENABLE_DEBUG_INFO_2 ,
C_ENABLE_DEBUG_INFO_3 => C_ENABLE_DEBUG_INFO_3 ,
C_ENABLE_DEBUG_INFO_4 => C_ENABLE_DEBUG_INFO_4 ,
C_ENABLE_DEBUG_INFO_5 => C_ENABLE_DEBUG_INFO_5 ,
C_ENABLE_DEBUG_INFO_6 => C_ENABLE_DEBUG_INFO_6 ,
C_ENABLE_DEBUG_INFO_7 => C_ENABLE_DEBUG_INFO_7 ,
C_ENABLE_DEBUG_INFO_8 => C_ENABLE_DEBUG_INFO_8 ,
C_ENABLE_DEBUG_INFO_9 => C_ENABLE_DEBUG_INFO_9 ,
C_ENABLE_DEBUG_INFO_10 => C_ENABLE_DEBUG_INFO_10 ,
C_ENABLE_DEBUG_INFO_11 => C_ENABLE_DEBUG_INFO_11 ,
C_ENABLE_DEBUG_INFO_12 => C_ENABLE_DEBUG_INFO_12 ,
C_ENABLE_DEBUG_INFO_13 => C_ENABLE_DEBUG_INFO_13 ,
C_ENABLE_DEBUG_INFO_14 => C_ENABLE_DEBUG_INFO_14 ,
C_ENABLE_DEBUG_INFO_15 => C_ENABLE_DEBUG_INFO_15 ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM,
C_ENABLE_FLUSH_ON_FSYNC => C_ENABLE_FLUSH_ON_FSYNC
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Fetch command write interface from sm
cmnd_wr => cmnd_wr ,
cmnd_data => cmnd_data ,
cmnd_pending => cmnd_pending ,
sts_received => sts_received ,
crnt_hsize => crnt_hsize ,
stop => stop_i ,
halt => halt , -- CR613214
dmasr_halt => dmasr_halt ,
-- User Command Interface Ports (AXI Stream)
s_axis_cmd_tvalid => s_axis_cmd_tvalid ,
s_axis_cmd_tready => s_axis_cmd_tready ,
s_axis_cmd_tdata => s_axis_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_sts_tvalid => m_axis_sts_tvalid ,
m_axis_sts_tready => m_axis_sts_tready ,
m_axis_sts_tdata => m_axis_sts_tdata ,
m_axis_sts_tkeep => m_axis_sts_tkeep ,
s2mm_fsize_more_or_sof_late => s2mm_fsize_more_or_sof_late ,
s2mm_dmasr_lsize_less_err => s2mm_dmasr_lsize_less_err ,
-- Zero Hsize and/or Vsize. mapped here to combine with interr
zero_size_err => zero_size_err ,
-- Frame Mismatch. mapped here to combine with interr
fsize_mismatch_err => fsize_mismatch_err_i , -- CR591965
lsize_mismatch_err => lsize_mismatch_err_i , -- CR591965
lsize_more_mismatch_err => lsize_more_mismatch_err_i , -- CR591965
capture_hsize_at_uf_err => capture_hsize_at_uf_err ,
-- Primary DataMover Status
err => err ,
done => done ,
err_o => dma_err ,
interr_minus_frame_errors => interr_minus_frame_errors ,
interr => interr ,
slverr => slverr ,
decerr => decerr ,
tag => tag -- Not used
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_STS_MNGR : entity axi_vdma_v6_2_8.axi_vdma_sts_mngr
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- dma control and sg engine status signals
run_stop => run_stop ,
regdir_idle => regdir_idle ,
ftch_idle => ftch_idle ,
cmnd_idle => cmnd_idle ,
sts_idle => sts_idle ,
line_buffer_empty => line_buffer_empty ,
dwidth_fifo_pipe_empty => dwidth_fifo_pipe_empty ,
video_prmtrs_valid => video_prmtrs_valid ,
prmtr_update_complete => prmtr_update_complete , -- CR605424
-- stop and halt control/status
stop => stop_i ,
halt => halt , -- CR 625278
halt_cmplt => halt_cmplt ,
-- system state and control
all_idle => all_idle_i ,
ftchcmdsts_idle => ftchcmdsts_idle ,
cmdsts_idle => cmdsts_idle ,
halted_clr => halted_clr ,
halted_set => halted_set ,
idle_set => idle_set ,
idle_clr => idle_clr
);
---------------------------------------------------------------------------
-- Video Register Bank
---------------------------------------------------------------------------
VIDEO_REG_I : entity axi_vdma_v6_2_8.axi_vdma_vidreg_module_64
generic map(
C_INCLUDE_SG => C_INCLUDE_SG ,
C_NUM_FSTORES => C_NUM_FSTORES ,
C_DYNAMIC_RESOLUTION => C_DYNAMIC_RESOLUTION ,
C_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_SELECT_XPM => C_SELECT_XPM ,
C_FAMILY => C_FAMILY
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Register update control
ftch_complete => ftch_complete ,
ftch_complete_clr => ftch_complete_clr ,
parameter_update => parameter_update ,
video_prmtrs_valid => video_prmtrs_valid ,
prmtr_update_complete => prmtr_update_complete , -- CR605424
num_fstore_minus1 => num_fstore_minus1 , -- CR607089
-- Register swap control/status
frame_sync => frame_sync ,
run_stop => run_stop ,
dmasr_halt => dmasr_halt ,
ftch_idle => ftch_idle ,
tailpntr_updated => tailpntr_updated ,
frame_number => frame_number_i ,
-- Register Direct Mode Video Parameter In
reg_module_vsize => reg_module_vsize ,
reg_module_hsize => reg_module_hsize ,
reg_module_stride => reg_module_stride ,
reg_module_frmdly => reg_module_frmdly ,
reg_module_strt_addr => reg_module_strt_addr ,
-- Descriptor data/control from sg interface
desc_data_wren => desc_data_wren ,
desc_strtaddress => desc_strtaddress ,
desc_vsize => desc_vsize ,
desc_hsize => desc_hsize ,
desc_stride => desc_stride ,
desc_frmdly => desc_frmdly ,
-- Scatter Gather register Bank
--crnt_vsize => crnt_vsize , -- CR575884
crnt_vsize => crnt_vsize_i , -- CR575884
crnt_hsize => crnt_hsize ,
crnt_stride => crnt_stride ,
crnt_frmdly => crnt_frmdly ,
crnt_start_address => crnt_start_address
);
---------------------------------------------------------------------------
-- Gen Lock
---------------------------------------------------------------------------
VIDEO_GENLOCK_I : entity axi_vdma_v6_2_8.axi_vdma_genlock_mngr
generic map(
C_GENLOCK_MODE => C_GENLOCK_MODE ,
C_GENLOCK_NUM_MASTERS => C_GENLOCK_NUM_MASTERS ,
C_INTERNAL_GENLOCK_ENABLE => C_INTERNAL_GENLOCK_ENABLE ,
C_NUM_FSTORES => C_NUM_FSTORES
)
port map(
-- Secondary Clock Domain
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Dynamic Frame Store Support
num_frame_store => num_frame_store ,
num_fstore_minus1 => num_fstore_minus1 ,
-- Gen-Lock Slave Signals
mstr_in_control => mstr_pntr_ref ,
genlock_select => genlock_select ,
frame_ptr_in => frame_ptr_in ,
internal_frame_ptr_in => internal_frame_ptr_in ,
slv_frame_ref_out => slv_frame_ref_out ,
-- Gen-Lock Master Signals
dmasr_halt => dmasr_halt ,
circular_prk_mode => circular_prk_mode ,
fsize_mismatch_err_flag => fsize_mismatch_err_flag_i ,
mstr_frame_update => valid_frame_sync_d2 ,
mstr_frame_ref_in => mstr_frame_ref_in ,
mstrfrm_tstsync_out => mstrfrm_tstsync_out ,
frame_ptr_out => frame_ptr_out
);
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_blkmem.vhd
|
4
|
20086
|
-------------------------------------------------------------------------------
--axi_vdma_blkmem.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_blkmem.vhd
--
-- Description: This file is the top level wrapper for properly configuring
-- and calling blk_mem_gen_wrapper
--
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_bmg_v1_0_5;
use lib_bmg_v1_0_5.blk_mem_gen_wrapper;
--use proc_common_v4_0_2.family_support.all;
-------------------------------------------------------------------------------
entity axi_vdma_blkmem is
generic (
C_DATA_WIDTH : integer := 32;
C_ADDR_WIDTH : integer := 9;
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
);
port(
Clk : in std_logic ;--
Rst : in std_logic ;--
--
--
-- Write Port signals --
Wr_Enable : in std_logic ;--
Wr_Req : in std_logic ;--
Wr_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Wr_Data : in std_logic_vector(0 to C_DATA_WIDTH-1) ;--
--
-- Read Port Signals --
Rd_Enable : in std_logic ;--
Rd_Address : in std_logic_vector(0 to C_ADDR_WIDTH-1) ;--
Rd_Data : out std_logic_vector(0 to C_DATA_WIDTH-1) --
);
end axi_vdma_blkmem ;
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_blkmem is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
component xpm_memory_tdpram
generic (
MEMORY_SIZE : integer := 4096;
MEMORY_PRIMITIVE : string := "blockram";
CLOCKING_MODE : string := "common_clock";
ECC_MODE : string := "no_ecc";
MEMORY_INIT_FILE : string := "none";
WAKEUP_TIME : string := "disable_sleep";
MESSAGE_CONTROL : integer := 0;
WRITE_DATA_WIDTH_A : integer := 32;
READ_DATA_WIDTH_A : integer := 32;
BYTE_WRITE_WIDTH_A : integer := 32;
ADDR_WIDTH_A : integer := 12;
READ_RESET_VALUE_A : string := "0";
READ_LATENCY_A : integer := 1;
WRITE_MODE_A : string := "write_first";
WRITE_DATA_WIDTH_B : integer := 32;
READ_DATA_WIDTH_B : integer := 32;
BYTE_WRITE_WIDTH_B : integer := 32;
ADDR_WIDTH_B : integer := 12;
READ_RESET_VALUE_B : string := "0";
READ_LATENCY_B : integer := 1;
WRITE_MODE_B : string := "write_first"
);
port (
-- Common module ports
sleep : in std_logic;
-- Port A module ports
clka : in std_logic;
rsta : in std_logic;
ena : in std_logic;
regcea : in std_logic;
wea : in std_logic_vector (0 downto 0);
addra : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dina : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterra : in std_logic;
injectdbiterra : in std_logic;
douta : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterra : out std_logic;
dbiterra : out std_logic;
-- Port B module ports
clkb : in std_logic;
rstb : in std_logic;
enb : in std_logic;
regceb : in std_logic;
web : in std_logic_vector (0 downto 0);
addrb : in std_logic_vector (0 to C_ADDR_WIDTH-1);
dinb : in std_logic_vector (0 to C_DATA_WIDTH-1);
injectsbiterrb : in std_logic;
injectdbiterrb : in std_logic;
doutb : out std_logic_vector(0 to C_DATA_WIDTH-1);
sbiterrb : out std_logic;
dbiterrb : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
function get_bram_primitive (target_width: integer)
return integer is
variable primitive_blk_mem : integer;
constant prim_type_1bit : integer := 0; -- ( 1-bit wide)
constant prim_type_2bit : integer := 1; -- ( 2-bit wide)
constant prim_type_4bit : integer := 2; -- ( 4-bit wide)
constant prim_type_9bit : integer := 3; -- ( 9-bit wide)
constant prim_type_18bit : integer := 4; -- (18-bit wide)
constant prim_type_36bit : integer := 5; -- (36-bit wide)
constant prim_type_72bit : integer := 6; -- (72-bit wide, single port only)
begin
case target_width Is
when 1 =>
primitive_blk_mem := prim_type_1bit;
when 2 =>
primitive_blk_mem := prim_type_2bit;
when 3 | 4 =>
primitive_blk_mem := prim_type_4bit;
when 5 | 6 | 7 | 8 | 9 =>
primitive_blk_mem := prim_type_9bit;
when 10 | 11 | 12 | 13 | 14 |
15 | 16 | 17 | 18 =>
primitive_blk_mem := prim_type_18bit;
when others =>
primitive_blk_mem := prim_type_36bit;
end case;
return primitive_blk_mem;
end function get_bram_primitive;
----------------------------------------------------------------------------
-- Constants Declarations
----------------------------------------------------------------------------
constant PRIM_TYPE : integer := get_bram_primitive(C_DATA_WIDTH);
constant MEM_TYPE : integer := 2; -- True dual port RAM
-- Determine the number of BRAM storage locations needed
constant FIFO_DEPTH : integer := 2**C_ADDR_WIDTH;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal port_a_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_a_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_a_enable : std_logic;
signal port_a_wr_enable : std_logic_vector(0 downto 0);
signal port_b_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0);
signal port_b_data_in : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_data_out : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal port_b_enable : std_logic;
signal port_b_wr_enable : std_logic_vector(0 downto 0);
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- translate big-endian and little_endian indexes of the
-- data buses
TRANSLATE_DATA : process (Wr_Data, port_b_data_out)
begin
port_a_data_in <= (others => '0');
for i in C_DATA_WIDTH-1 downto 0 loop
port_a_data_in(i) <= Wr_Data(C_DATA_WIDTH-1-i);
Rd_Data(C_DATA_WIDTH-1-i) <= port_b_data_out(i);
end loop;
end process TRANSLATE_DATA;
-- translate big-endian and little_endian indexes of the
-- address buses (makes simulation easier)
TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address)
begin
port_a_addr <= (others => '0');
port_b_addr <= (others => '0');
for i in C_ADDR_WIDTH-1 downto 0 loop
port_a_addr(i) <= Wr_Address(C_ADDR_WIDTH-1-i);
port_b_addr(i) <= Rd_Address(C_ADDR_WIDTH-1-i);
end loop;
end process TRANSLATE_ADDRESS;
port_a_enable <= Wr_Enable;
port_a_wr_enable(0) <= Wr_Req;
port_b_enable <= Rd_Enable;
port_b_data_in <= (others => '0');
port_b_wr_enable <= (others => '0');
xpm_mem_gen : if (C_SELECT_XPM = 1) generate
xpm_memory_inst: xpm_memory_tdpram
generic map (
MEMORY_SIZE => FIFO_DEPTH*C_DATA_WIDTH,
MEMORY_PRIMITIVE => "blockram",
CLOCKING_MODE => "common_clock",
ECC_MODE => "no_ecc",
MEMORY_INIT_FILE => "none",
WAKEUP_TIME => "disable_sleep",
MESSAGE_CONTROL => 1,
WRITE_DATA_WIDTH_A => C_DATA_WIDTH,
READ_DATA_WIDTH_A => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_A => C_DATA_WIDTH,
ADDR_WIDTH_A => C_ADDR_WIDTH,
READ_RESET_VALUE_A => "0",
READ_LATENCY_A => 1,
WRITE_MODE_A => "write_first",
WRITE_DATA_WIDTH_B => C_DATA_WIDTH,
READ_DATA_WIDTH_B => C_DATA_WIDTH,
BYTE_WRITE_WIDTH_B => C_DATA_WIDTH,
ADDR_WIDTH_B => C_ADDR_WIDTH,
READ_RESET_VALUE_B => "0",
READ_LATENCY_B => 1,
WRITE_MODE_B => "write_first"
)
port map (
-- Common module ports
sleep => '0',
-- Port A module ports
clka => Clk,
rsta => Rst,
ena => port_a_enable,
regcea => '0',
wea => port_a_wr_enable,
addra => port_a_addr,
dina => port_a_data_in,
injectsbiterra => '0',
injectdbiterra => '0',
douta => open,
sbiterra => open,
dbiterra => open,
-- Port B module ports
clkb => Clk,
rstb => Rst,
enb => port_b_enable,
regceb => '0',
web => port_b_wr_enable,
addrb => port_b_addr,
dinb => port_b_data_in,
injectsbiterrb => '0',
injectdbiterrb => '0',
doutb => port_b_data_out,
sbiterrb => open,
dbiterrb => open
);
end generate;
blk_mem_gen : if (C_SELECT_XPM = 0) generate
-- For V6 and S6 use block memory generator to
-- generate BRAM
I_BLK_MEM : entity lib_bmg_v1_0_5.blk_mem_gen_wrapper
generic map (
c_family => C_FAMILY,
c_xdevicefamily => C_FAMILY,
c_mem_type => MEM_TYPE,
c_algorithm => 1,
c_prim_type => PRIM_TYPE,
c_byte_size => 8,
c_sim_collision_check => "All",
c_common_clk => 1,
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_load_init_file => 0,
c_init_file_name => "no_coe_file_loaded",
c_use_default_data => 0,
c_default_data => "0",
-- Port A Settings
c_has_mem_output_regs_a => 0,
c_has_mux_output_regs_a => 0,
c_write_width_a => C_DATA_WIDTH,
c_read_width_a => C_DATA_WIDTH,
c_write_depth_a => FIFO_DEPTH,
c_read_depth_a => FIFO_DEPTH,
c_addra_width => C_ADDR_WIDTH,
c_write_mode_a => "WRITE_FIRST",
c_has_ena => 1,
c_has_regcea => 0,
c_has_ssra => 0,
c_sinita_val => "0",
c_use_byte_wea => 0,
c_wea_width => 1,
-- Port B Settings
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_b => 0,
c_write_width_b => C_DATA_WIDTH,
c_read_width_b => C_DATA_WIDTH,
c_write_depth_b => FIFO_DEPTH,
c_read_depth_b => FIFO_DEPTH,
c_addrb_width => C_ADDR_WIDTH,
c_write_mode_b => "WRITE_FIRST",
c_has_enb => 1,
c_has_regceb => 0,
c_has_ssrb => 0,
c_sinitb_val => "0",
c_use_byte_web => 0,
c_web_width => 1,
-- Misc Settings
c_mux_pipeline_stages => 0,
c_use_ecc => 0,
c_use_ramb16bwer_rst_bhv => 0 -- No use of S3A DSP embedded RAM primitives
)
port map (
clka => Clk ,
ssra => Rst ,
dina => port_a_data_in ,
addra => port_a_addr ,
ena => port_a_enable ,
regcea => '0' ,
wea => port_a_wr_enable ,
douta => open ,
clkb => Clk ,
ssrb => Rst ,
dinb => port_b_data_in ,
addrb => port_b_addr ,
enb => port_b_enable ,
regceb => '0' ,
web => port_b_wr_enable ,
doutb => port_b_data_out ,
dbiterr => open , -- No ECC
sbiterr => open -- No ECC
);
end generate;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_gpio_sysfs/zybo_petalinux_1.ip_user_files/ipstatic/axi_lite_ipif_v3_0/hdl/src/vhdl/ipif_pkg.vhd
|
4
|
55295
|
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default_i : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function log2(x : natural) return integer;
function clog2(x : positive) return natural;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default_i : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default_i;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_ftch_pntr.vhd
|
4
|
21872
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_pntr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch1_fetch_address <= ch1_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0')then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch2_fetch_address <= ch2_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
ch2_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_omit_wrap.vhd
|
18
|
17501
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_updt_mngr.vhd
|
4
|
21166
|
-------------------------------------------------------------------------------
-- axi_sg_updt_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_mngr.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
ch2_updt_curdesc_wren : in std_logic ; --
ch2_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
s2mm_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_cmnd_wr : std_logic := '0';
signal updt_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH
+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal updt_done : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal updt_interr : std_logic := '0';
signal updt_slverr : std_logic := '0';
signal updt_decerr : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_UPDT_SG : entity axi_vdma_v6_2_8.axi_sg_updt_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ftch_error => ftch_error ,
-- Channel 1 Control and Status
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set ,
ch1_dma_slverr_set => ch1_dma_slverr_set ,
ch1_dma_decerr_set => ch1_dma_decerr_set ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set ,
ch2_dma_slverr_set => ch2_dma_slverr_set ,
ch2_dma_decerr_set => ch2_dma_decerr_set ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- DataMover Command
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- DataMover Status
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_UPDT_CMDSTS_IF : entity axi_vdma_v6_2_8.axi_sg_updt_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
-- Scatter Gather Fetch Status
s2mm_err => s2mm_err ,
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr
);
end implementation;
|
gpl-3.0
|
rad-/65C816_SoftCore
|
65C816_Repo/65C816 (Prometheus's conflicted copy 2016-03-18).vhd
|
1
|
61332
|
----------------------------------------------------------------------------------
-- Company: Open Source
-- Engineer: Steven T. Seppala ( rad- )
--
-- Create Date: 01/26/2016 03:26:56 PM
-- Design Name:
-- Module Name: 65C816 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
-- This is a soft-core implementation of a 65C816. There will be initally 92
--of the 256 OpCodes useable. Please refer to DOC 1A for reference.
--
-- Dependencies:
-- For testing purposes there will be an AXI interface into this module.
--This should be provided with all the source HDL.
--If this module is being used in conjunction with another module and there is no need
--to access or view the inner workings of this module, no other dependancies occour.
--
-- Revision: V .1 -- 26 Jan 2016 STS
--
-- Revision 0.01 - File Created
-- Additional Comments:
-- The SNES CPU (65c816) uses little endian.
-- Revision 0.5 - Decode Table and Addressing Modes
-- The decode process and addressing mode assigning table
-- processes have been crated.
-- NOTE : Memory accesses will be passed from this
-- module to a C_FLAG program for reading/writing.
-- Revision 1.0 - 18 Feb 2016
-- Main Modules finished.
-- Revision 1.1 - 3 March 2016
-- Tests passed. Main is now implemented.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.SNES65816func.all;
entity Soft_65C816 is
Port ( clk : in STD_LOGIC; -- Main CLK for system
tru_clk : in std_logic; -- True clk for system
reset : in std_logic; -- Reset Signal
Addr_Bus : out STD_LOGIC_VECTOR (23 downto 0);-- Address Bus
D_BUS : in STD_LOGIC_VECTOR (31 downto 0); -- Data Bus
EMULATION_SELECT : out STD_LOGIC; -- Emulation Bit
RDY : out STD_LOGIC;
DATA_RDY: in STD_LOGIC;
REG_A :out std_logic_vector(15 downto 0);
REG_X :out std_logic_vector(15 downto 0);
REG_Y :out std_logic_vector(15 downto 0);
REG_SP :out std_logic_vector(15 downto 0);
REG_PC :out std_logic_vector(15 downto 0);
REG_Proc :out std_logic_vector(7 downto 0);
REG_DBR :out std_logic_vector(7 downto 0);
VPB : out STD_LOGIC);
end Soft_65C816;
architecture Behavioral of Soft_65C816 is
--state machine states
type state_machine_states is (s0, s1, s2, s3, s4, s5 , sc, sa, sm, sp, sf, ss, sn, se, si, calculate_memory_pointer, s6);
signal state : state_machine_states;
--One hot sounter for state machine location/control
signal state_machine_onehot : std_logic_vector (15 downto 0);
--chunk pull vector
signal chunk_pull : std_logic_vector (31 downto 0);
--vector with info about the opcode
signal instruction_info : std_logic_vector (11 downto 0);
signal op_code : std_logic_vector (7 downto 0);
-- This will have the instructions arguments assigned to it.
signal instrction_args : std_logic_vector (31 downto 0);
-- This signal must be run with a 3.58 MHz CLK.
-- It is just a counter, but it must count at 3.58 MHz.
signal tru_cpu : std_logic_vector (3 downto 0);
-- This is essentially a latch enable,
-- it will count for as many cycles as the
-- operation would take on a true 65816
signal tru_clk_cntr : std_logic_vector(3 downto 0);
-- This will hold the instruction size, so the PC can correctly
-- be incrimented.
signal instruction_size : std_logic_vector (3 downto 0);
-- Memory pointer for pulling and pushing values
signal memory_pointer : std_logic_vector ( 23 downto 0);
-- This signal holds the values from the memory locations
-- requested.
signal requested_values : std_logic_vector (31 downto 0);
-- This will hold type info so the correct
-- execution state can be determined.
signal type_info : std_logic_vector (3 downto 0);
--
-- Process Control Signals
--
signal addressing_done, addressing_on, decode_on, decode_done, memory_calculate_done, memory_calculate_on : STD_LOGIC;
signal memory_done:std_logic;
signal math_done : std_logic;
signal pc_done : std_logic;
signal flag_done : std_logic;
signal store_back: std_logic;
signal push_to_stack : std_logic;
signal ready_up : std_logic;
signal stack_done: std_logic;
signal exchange_done: std_logic;
signal data_enable : std_logic;
--
-- REGISTER DECLARATIONS
--
-- Program Counter : PC
-- PC Bank Register : PBR
signal PC : std_logic_vector (23 downto 0);
alias PBR : std_logic_vector (7 downto 0) is PC (23 downto 16);
alias ProgramCntr : std_logic_vector (15 downto 0) is PC (15 downto 0);
-- Accumulator : A_REG
-- Direct Page Register: DP
-- Stack Pointer : SP
-- X & Y_REG Are Index Registers
signal A_REG, DP, StackPointer, X_REG, Y_REG : std_logic_vector ( 15 downto 0);
-- StackPointer is vaid from 00:0000 to 00:FFFF
-- Processor Status : P
-- Data Bank Register : DBR
signal P : std_logic_vector ( 7 downto 0);
signal DBR : std_logic_vector ( 7 downto 0);
alias N : STD_LOGIC is P(7); -- Negative Flag
alias V : STD_LOGIC is P(6); -- Overflow Flag
alias M : STD_LOGIC is P(5); -- Memory Select
alias X_FLAG : STD_LOGIC is P(4); -- Index Register
alias D_FLAG : STD_LOGIC is P(3); -- Decimal Mode
alias I : STD_LOGIC is P(2); -- IRQ Disable
alias Z : STD_LOGIC is P(1); -- Zero Result
alias C_FLAG : STD_LOGIC is P(0); -- Carry Flag / Emulation Mode
--
-- END REGISTER DECLARATIONS
--
--
-- Memory signals
--
signal effective_memory_pointer : std_logic_vector (23 downto 0);
signal write_back_location : std_logic_vector (23 downto 0);
signal write_back_value : std_logic_vector(15 downto 0);
signal write_back_bank : std_logic_vector(7 downto 0);
signal adr_type : integer range 0 to 25;
signal push_val : std_logic_vector(23 downto 0);
signal read_out : std_logic_vector(15 downto 0);
signal read_out_bank : std_logic_vector(7 downto 0);
signal address_out : std_logic_vector(23 downto 0);
--
--
-- Constant Signals
--
--
constant zeros : std_logic_vector (15 downto 1) := ( B"0000_0000_0000_000");
begin
Addr_Bus<= address_out;
REG_A <= A_REG;
REG_X <= X_REG;
REG_Y <= Y_REG;
REG_SP <= StackPointer;
REG_PC <= ProgramCntr;
REG_Proc <= P;
REG_DBR <= DBR;
--
-- This is the true CPU clock for the processor
-- It runs at 3.58 MHz and allows s6 to continue
-- to s1.
slow_clock:
process(tru_clk, clk) is
begin
if reset = '1' then
tru_clk_cntr <= (others => '0');
ready_up <= '0';
end if;
if rising_edge(clk) then
if (tru_clk_cntr = tru_cpu) and rising_edge(tru_clk) then
ready_up <= '1' ;
else
ready_up <= '0';
end if;
elsif falling_edge(clk) then
if ready_up ='1' then
tru_clk_cntr <= (others => '0');
end if;
end if;
if rising_edge(tru_clk) then
tru_clk_cntr <= std_logic_vector(unsigned(tru_clk_cntr) + 1);
end if;
end process;
--
-- This is a 16 bit microprocessor with variable length instructions, the PC will
-- depend on the current instruction size.
-- Thus the PC will get
--
--
state_machine:
process (clk, reset) is
variable effective_memeory_pointer_temp : std_logic_vector (23 downto 0);
variable pointer_calculation_done : std_logic;
variable math_temp : std_logic_vector (16 downto 0);
variable stack_temp : std_logic_vector (16 downto 0);
variable xfr_temp : std_logic_vector (16 downto 0);
variable mem_temp : std_logic_vector (16 downto 0);
variable flag_temp : std_logic_vector (16 downto 0);
begin
if reset = '1' then
--TODO: RESET
state <= s0; -- reset to s0
chunk_pull <= (others => 'Z'); -- clear chunk pull
op_code <= (others => 'Z'); -- set opcode hi-Z
StackPointer <= X"0100"; -- Initialize Stack pointer
A_REG <= (others => '0');
X_REG <= (others => '0');
Y_REG <= (others => '0');
PC <= (others => '0');
DBR <= X"00";
DP <= X"0000";
N <= '0';
V <= '0';
M <= '1';
X_FLAG <= '1';
D_FLAG <= '0';
I <= '1';
Z <= '0';
C_FLAG <= '1'; -- This is the emulation flag on reset.
elsif rising_edge(clk) then
case state is
when s0 =>
if state_machine_onehot = "0000000000000001" then
state <= s1;
else
state <= s0;
end if;
state_machine_onehot <= "0000000000000001";
write_back_value <=X"0000";
write_back_bank <=X"00";
address_out <=PC;
rdy <= '1';
when s1 =>
if state_machine_onehot = "0000000000000010" then
state <= s2;
else
state <= s1;
end if;
rdy <= '0';
data_enable <= '1';
if data_rdy ='0' and chunk_pull /= "ZZZZZZZZZZZZZZZZZ" then
chunk_pull <= D_BUS;
state_machine_onehot <= "0000000000000010";
end if;
when s2 =>
if ((addressing_done = '1') and (decode_done = '1') and (state_machine_onehot = "0000000000000100")) then
state <= s3;
else
state <= s2;
end if;
addressing_on <= '1';
decode_on <= '1';
-- This should send the OPCode from chunkpull
-- to the opcode_info process, which inturn
-- will give us everything we need to know about how
-- to execute the instruction.
if data_enable = '1' then
op_code <= chunk_pull(31 downto 24);
state_machine_onehot <= "0000000000000100";
data_enable <= '0';
end if;
when s3 =>
if state_machine_onehot = "0000000000001000" then
state <= s4;
else
state <= s3;
end if;
data_enable <= '1';
addressing_on <= '0';
decode_on <= '0';
instruction_size <= instruction_info(11 downto 8);
tru_cpu <= instruction_info(7 downto 4);
type_info <= instruction_info( 3 downto 0);
state_machine_onehot <= "0000000000001000";
when s4 =>
if ((state_machine_onehot = "0000000000010000") and (memory_calculate_done = '1'))then
state <= calculate_memory_pointer;
else
state <= s4;
end if;
PC <= std_logic_vector(unsigned(PC) + unsigned(instruction_size));
state_machine_onehot <= "0000000000010000";
memory_calculate_on <= '1';
when calculate_memory_pointer =>
if pointer_calculation_done = '1' then
state <= s5;
end if;
memory_calculate_on <= '0';
case adr_type is
when 0 =>
if ((op_code = X"20") or (op_code = X"4c")) then
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
else
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
end if;
pointer_calculation_done := '1';
when 1 =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 2 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(X_REG));
pointer_calculation_done := '1';
when 3 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(Y_REG));
pointer_calculation_done := '1';
when 4 =>
effective_memory_pointer <= memory_pointer;
pointer_calculation_done := '1';
when 5 =>
effective_memory_pointer <= std_logic_vector(unsigned(memory_pointer) + unsigned(X_REG));
pointer_calculation_done := '1';
when 6 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
pointer_calculation_done := '1';
when 7 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0) + X_REG;
pointer_calculation_done := '1';
when 8 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 9 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 10=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + X_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 11=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + Y_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 12=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 13=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 14=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 15=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= X_REG + DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 16=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 17=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 18=>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 19=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 20=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 21=>
-- Stack Operations are handled in the stack state or where neccicary
effective_memory_pointer <= X"00" & StackPointer;
pointer_calculation_done := '1';
when 22=>
-- Block operations are not implemented yet
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 23 =>
requested_values <= X"00" & memory_pointer;
pointer_calculation_done := '1';
when others =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
end case;
when s5 =>
pointer_calculation_done := '0';
state_machine_onehot <= "0000000000100000";
if state_machine_onehot = "0000000000100000" then
-- Go to fan out based on type info,
-- if type info is not 0 - 8, then count it
-- as a NOP
--
if type_info = X"0" then
state <= sa;
elsif type_info = X"1" then
state <= sp;
elsif type_info = X"2" then
state <= sm;
elsif type_info = X"3" then
state <= sc;
elsif type_info = X"4" then
state <= sf;
elsif type_info = X"5" then
state <= ss;
elsif type_info = X"6" then
state <= sn;
elsif type_info = X"7" then
state <= se;
elsif type_info = X"8" then
state <= si;
-- if state can not be defined treat it as a NOP
else
state <= sn;
end if;
end if;
when sc =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sc;
end if;
state_machine_onehot <= "0000000001000000";
--
-- Arithmatic State Start
--
when sa =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sa;
end if;
-- ADC
if op_code = X"6D" or
op_code = X"7D" or
op_code = X"79" or
op_code = X"6F" or
op_code = X"7F" or
op_code = X"17" or
op_code = X"65" or
op_code = X"63" or
op_code = X"75" or
op_code = X"72" or
op_code = X"67" or
op_code = X"73" or
op_code = X"61" or
op_code = X"71" or
op_code = X"77" or
op_code = X"69" then
math_temp := ('0' & requested_values(15 downto 0)) + A_REG + ( zeros & C_FLAG);
if ((math_temp = "00000000000000000" ) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
elsif math_temp /= "ZZZZZZZZZZZZZZZZZ" then
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
-- AND
elsif op_code = X"2D" or
op_code = X"3E" or
op_code = X"39" or
op_code = X"2F" or
op_code = X"3F" or
op_code = X"25" or
op_code = X"23" or
op_code = X"36" or
op_code = X"32" or
op_code = X"27" or
op_code = X"33" or
op_code = X"91" or
op_code = X"31" or
op_code = X"37" or
op_code = X"29" then
math_temp := '0' & ( A_REG and requested_values(15 downto 0));
if math_temp = "00000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0 );
math_done <= '1';
-- ASL
elsif
op_code = X"0E" or
op_code = X"1E" or
op_code = X"06" or
op_code = X"16" then
math_temp := requested_values(15 downto 0) & '0';
C_FLAG <= requested_values(15);
store_back <= '1';
if math_temp(15 downto 0) = "0000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
elsif op_code = X"0A" then
math_temp := A_REG( 15 downto 0) & '0';
C_FLAG <= A_REG(15);
if math_temp(15 downto 0) = ("0000000000000000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
-- CMP
elsif
op_code = X"CD" or
op_code = X"DD" or
op_code = X"D9" or
op_code = X"CF" or
op_code = X"DF" or
op_code = X"C5" or
op_code = X"C3" or
op_code = X"D5" or
op_code = X"D2" or
op_code = X"C7" or
op_code = X"D3" or
op_code = X"C1" or
op_code = X"D1" or
op_code = X"D7" or
op_code = X"C9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0));
if (A_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPX
elsif
op_code = X"EC" or
op_code = X"E4" or
op_code = X"E0" then
math_temp := X_REG - ('0' & requested_values(15 downto 0));
if (X_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPY
elsif
op_code = X"CC" or
op_code = X"C4" or
op_code = X"C0" then
math_temp := Y_REG - ('0' & requested_values(15 downto 0));
if (Y_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- DEX
elsif
op_code = X"CA" then
math_temp := '0' & X_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- DEY
elsif
op_code = X"88" then
math_temp := '0' & Y_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- EOR
elsif
op_code = X"4D" or
op_code = X"5D" or
op_code = X"59" or
op_code = X"4F" or
op_code = X"5F" or
op_code = X"5D" or
op_code = X"45" or
op_code = X"43" or
op_code = X"55" or
op_code = X"52" or
op_code = X"47" or
op_code = X"53" or
op_code = X"41" or
op_code = X"51" or
op_code = X"57" or
op_code = X"49" then
math_temp := '0' & (requested_values(15 downto 0) xor A_REG);
if math_temp = ('0'&(X"0000")) then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- INX
elsif
op_code = X"E8" then
math_temp := '0' & X_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- INY
elsif
op_code = X"C8" then
math_temp := '0' & Y_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- LSR
elsif
op_code = X"4A" then
math_temp := '0' & A_REG;
N <= '0';
C_FLAG <= A_REG(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"4E" or
op_code = X"5E" or
op_code = X"46" or
op_code = X"56" then
math_temp := '0' & requested_values(15 downto 0);
store_back <= '1';
N <= '0';
C_FLAG <= requested_values(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
math_done <= '1';
-- ORA
elsif
op_code = X"0D" or
op_code = X"1D" or
op_code = X"19" or
op_code = X"0F" or
op_code = X"1F" or
op_code = X"05" or
op_code = X"03" or
op_code = X"15" or
op_code = X"12" or
op_code = X"07" or
op_code = X"13" or
op_code = X"01" or
op_code = X"11" or
op_code = X"17" or
op_code = X"09" then
math_temp := '0' & (requested_values(15 downto 0) or A_REG);
A_REG <= math_temp;
if math_temp = ('0' & X"0000") then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- ROL
elsif
op_code = X"2A" then
math_temp := A_REG & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
if math_temp(16 downto 1) = X"0000" then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (15 downto 0);
math_done <= '1';
elsif
op_code = X"2E" or
op_code = X"3E" or
op_code = X"26" or
op_code = X"36" then
math_temp := requested_values(15 downto 0) & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- ROR
elsif
op_code = X"6A" then
math_temp := C_FLAG & A_REG;
C_FLAG <= A_REG (0);
N <= math_temp(15);
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"6E" or
op_code = X"7E" or
op_code = X"66" or
op_code = X"76" then
math_temp := C_FLAG & requested_values(15 downto 0) ;
C_FLAG <= requested_values (0);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- SBC
elsif
op_code = X"ED" or
op_code = X"FD" or
op_code = X"F9" or
op_code = X"FF" or
op_code = X"E5" or
op_code = X"E3" or
op_code = X"F5" or
op_code = X"F2" or
op_code = X"E7" or
op_code = X"F3" or
op_code = X"E1" or
op_code = X"F1" or
op_code = X"F7" or
op_code = X"E9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0)) - ( ('0' & zeros) & C_FLAG);
if ((math_temp = ('0' & X"0000")) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
else
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
if (store_back = '1') and (math_done = '1') then
write_back_value <= math_temp (15 downto 0);
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif math_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END OF ARITHMATIC STATE
--
--
-- START MEMORY MANIPULATION STATE
--
when sm =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sm;
end if;
-- DEC
if op_code = X"CE" or
op_code= X"DE" or
op_code= X"C6" or
op_code= X"D6" then
mem_temp := '0' & requested_values(15 downto 0) - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
elsif op_code = X"3A" then
mem_temp := '0' & A_REG - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- INC
elsif op_code= X"1A" then
mem_temp := '0' & A_REG + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"EE" or
op_code= X"FE" or
op_code= X"E6" or
op_code= X"F6" then
mem_temp := '0' & requested_values(15 downto 0) + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
-- LDA
elsif op_code = X"AD" or
op_code= X"BD" or
op_code = X"B9" or
op_code = X"AF" or
op_code = X"BF" or
op_code = X"A5" or
op_code = X"A3" or
op_code = X"B5" or
op_code = X"B2" or
op_code = X"A7" or
op_code = X"B3" or
op_code = X"A1" or
op_code = X"B1" or
op_code = X"B7" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"A9" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDX
elsif op_code = X"AE" or
op_code= X"BE" or
op_code= X"A6" or
op_code= X"B6" or
op_code= X"A2" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
X_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDY
elsif op_code = X"AC" or
op_code= X"BC" or
op_code= X"A4" or
op_code= X"B4" or
op_code= X"A0" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
Y_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- STA
elsif op_code = X"8D" or
op_code= X"9D" or
op_code= X"8F" or
op_code= X"9F" or
op_code= X"85" or
op_code= X"83" or
op_code= X"95" or
op_code= X"92" or
op_code= X"87" or
op_code= X"93" or
op_code= X"81" or
op_code= X"91" or
op_code= X"97" then
mem_temp := '0' & A_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STX
elsif op_code = X"8E" or
op_code= X"86" or
op_code= X"96" then
mem_temp := '0' & X_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STY
elsif op_code = X"8C" or
op_code= X"84" or
op_code= X"94" then
mem_temp :='0' & Y_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
end if;
if (memory_done = '1') and (store_back = '1') then
state_machine_onehot <= "0000000001000000";
write_back_location <= effective_memory_pointer;
elsif (memory_done = '1') then
state_machine_onehot <= "0000000001000000";
store_back <= '0';
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END MEMORY MANIPULATION STATE
--
--
-- START PC MANIPULATION STATE
--
when sp =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sp;
end if;
-- BCC
if op_code = X"90" then
if C_FLAG = '0' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BEQ
elsif op_code = X"F0" then
if Z = '1' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BMI
elsif op_code = X"30" then
if N = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BNE
elsif op_code = X"D0" then
if Z = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BPL
elsif op_code = X"10" then
if N = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVC
elsif op_code = X"50" then
if V = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVS
elsif op_code = X"70" then
if V = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- JMP
elsif
op_code = X"4C" then
PC <= effective_memory_pointer;
pc_done <= '1';
elsif
op_code = X"5C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
elsif
op_code = X"6C" or
op_code = X"7C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
-- JSR
elsif op_code = X"20" or
op_code = X"FC" then
write_back_value <= ProgramCntr;
write_back_bank <= PBR;
PC <= requested_values(23 downto 0);
push_to_stack <= '1';
pc_done <= '1';
-- RTS
elsif op_code = X"60" then
ProgramCntr <= requested_values(15 downto 0);
StackPointer <= StackPointer - 2;
pc_done <= '1';
end if;
if (pc_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END PC MANIPULATION STATE
--
--
-- START FLAGC MANIPULATION STATE
--
when sf =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sf;
end if;
-- BIT
if op_code = X"2C" or
op_code = X"3C" or
op_code = X"24" or
op_code = X"34" then
flag_temp := '0' & (A_REG and requested_values(15 downto 0));
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= flag_temp(15);
V <= flag_temp(14);
else
V <= flag_temp(14);
N <= flag_temp(15);
Z <= '0';
end if;
flag_done <= '1';
elsif op_code = X"89" then
flag_temp := '0' & A_REG and requested_values(15 downto 0);
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
flag_done <= '1';
-- CLC
elsif op_code = X"18" then
C_FLAG <= '0';
flag_done <= '1';
-- CLD
elsif op_code = X"D8" then
D_FLAG <= '0';
flag_done <= '1';
-- CLI
elsif op_code = X"58" then
I <= '0';
flag_done <= '1';
-- CLV
elsif op_code = X"B8" then
V <= '0';
flag_done <= '1';
-- SEC
elsif op_code = X"38" then
C_FLAG <= '1';
flag_done <= '1';
-- SED
elsif op_code = X"F8" then
D_FLAG <= '0';
flag_done <= '1';
-- SEI
elsif op_code = X"78" then
I <= '1';
flag_done <= '1';
end if;
if flag_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END FLAG MANIPULATION STATE
--
--
-- STACK MANIPULATION STATE
--
when ss =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= ss;
end if;
-- PHA
if op_code = X"48" then
StackPointer <= StackPointer + 2;
push_to_stack <= '1';
write_back_value <= A_REG;
stack_done <= '1';
-- PHP
elsif op_code = X"08" then
StackPointer <= StackPointer + 1;
push_to_stack <= '1';
write_back_value <= X"00" & P;
stack_done <= '1';
-- PLA
elsif op_code = X"68" then
StackPointer <= StackPointer - 2;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
A_REG <= stack_temp(15 downto 0);
stack_done <= '1';
-- PLP
elsif op_code = X"28" then
StackPointer <= StackPointer - 1;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
P <= stack_temp(7 downto 0);
stack_done <= '1';
end if;
if (stack_done = '1') and (store_back = '1') then
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif (stack_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END STACK MANIPULATION STATE
--
--
-- START NOP STATE
--
when sn =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sn;
end if;
state_machine_onehot <= "0000000001000000";
--
-- END NOP STATE
--
--
-- START EXCHANGE STATE
--
when se =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= se;
end if;
-- TAX
if op_code = X"AA" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TAY
elsif op_code = X"AB" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
Y_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TYA
elsif op_code = X"98" then
xfr_temp := '0' & Y_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TSX
elsif op_code = X"BA" then
xfr_temp := '0' & StackPointer;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXA
elsif
op_code = X"8A" then
xfr_temp := '0' & X_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXS
elsif
op_code = X"9A" then
xfr_temp := '0' & X_REG;
StackPointer <= xfr_temp(15 downto 0);
exchange_done <= '1';
end if;
if (exchange_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END EXCHANGE STATE
--
--
-- START INTERUPT STATE
--
when si =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= si;
end if;
-- RTI
if op_code = X"40" then
ProgramCntr <= requested_values(23 downto 8);
P <= requested_values(7 downto 0);
end if;
state_machine_onehot <= "0000000001000000";
--
-- END INTRRUPT STATE
--
when s6 =>
if (state_machine_onehot = "0000000010000000") and (ready_up = '1') then
state <= s0;
else
state <= state;
end if;
math_done <= '0';
memory_done <= '0';
pc_done <= '0';
flag_done <= '0';
stack_done <= '0';
exchange_done <= '0';
if (store_back = '1') then
READ_OUT <= write_back_value;
ADDRESS_OUT <= write_back_location;
store_back <= '0';
state_machine_onehot <= "0000000010000000";
elsif (push_to_stack = '1') then
read_out <= write_back_value;
read_out_bank <= write_back_bank;
address_out <= X"00" & StackPointer;
push_to_stack <= '0';
state_machine_onehot <= "0000000010000000";
else
state_machine_onehot <= "0000000010000000";
end if;
when others =>
state_machine_onehot <= "0000000000000010";
end case;
end if;
end process;
--
-- This process will look at the opcode
-- and determine the addressing mode of
-- the specific instruction being requested
-- and then pass it onto the adr_type vector.
--
Addressing_Mode:
process (addressing_on) is
begin
addressing_done <= '0';
if (addressing_on = '1') then
-- Refer to 65000 Programmers Manual for explanation
-- of addressing modes.
--
-- Symbol Addressing Mode Symbol Addressing Mode
-- 0 -> a absolute
-- 1 -> A_REG accumulator
-- 2 -> a,x absolute indexed with X
-- 3 -> a,y absolute indexed with Y_REG
-- 4 -> al absolute long
-- 5 -> al,x absolute long indexed
-- 6 -> (a) absolute indirect
-- 7 -> (a,x) absolute indexed indirect
-- 8 -> d direct
-- 9 -> d,s stack relative
-- 10 -> d,x direct indexed with x
-- 11 -> d,y direct indexed with y
-- 12 -> (d) direct indirect
-- 13 -> [d] direct indirect long
-- 14 -> (d,s),y stack relative indirect indexed
-- 15 -> (d,x) direct indexed indirect
-- 16 -> (d),y direct indirect indexed
-- 17 -> [d].y direct indirect long indexed
-- 18 -> i implied
-- 19 -> r program counter relative
-- 20 -> rl program counter relative long
-- 21 -> s stack
-- 22 -> xyc block move
-- 23 -> # immediate
--
--
case op_code is
when X"6d" | X"2d" | X"0e" | X"2c" | X"cd" | X"ec" | X"cc" | X"ce" | X"4d" | X"ee" | X"4c" | X"20" | X"ad" | X"ae" | X"ac" | X"4e" | X"0d" | X"2e" | X"6e" | X"ed" | X"8d" | X"8e" | X"8c" | X"9c" | X"1c" | X"0c" =>
adr_type <= 0;
when X"0a" | X"3A" | X"1a" | X"4a" | X"2a" | X"6a" | X"3b" | X"ba" | X"8a" | X"9a" | X"9b" | X"98" | X"bb" | X"cb" | X"42" | X"eb" | X"fb" =>
adr_type <= 1;
when X"7d" | X"3e" | X"1e" | X"3c" | X"dd" | X"de" | X"5d" | X"fe" | X"bd" | X"bc" | X"5e" | X"1d" | X"7e" | X"fd" | X"9d" | X"9e" =>
adr_type <= 2;
when X"6f" | X"2f" | X"cf" | X"4f" | X"5c" | X"22" | X"af" | X"0f" | X"8f" =>
adr_type <= 3;
when X"79" | X"39" | X"d9" | X"59" | X"b9" | X"be" | X"19" | X"f9" =>
adr_type <= 4;
when X"7f" | X"3f" | X"df" | X"5f" | X"bf" | X"1f" | X"ff" | X"9f" =>
adr_type <= 5;
when X"dc" | X"6c" =>
adr_type <= 6;
when X"7c" | X"fc" =>
adr_type <= 7;
when X"65" | X"25" | X"06" | X"24" | X"c5" | X"e4" | X"c4" | X"c6" | X"45" | X"e6" | X"a5" | X"a6" | X"a4" | X"46" | X"05" | X"26" | X"66" | X"e5" | X"85" | X"86" | X"84" | X"64" | X"14" | X"04" =>
adr_type <= 8;
when X"63" | X"23" | X"c3" | X"43" | X"a3" | X"03" | X"e3" | X"83" =>
adr_type <= 9;
when X"75" | X"36" | X"16" | X"34" | X"d5" | X"d6" | X"55" | X"f6" | X"b5" | X"b4" | X"56" | X"15" | X"76" | X"f5" | X"95" | X"94" | X"74" =>
adr_type <= 10;
when X"b6" | X"96" =>
adr_type <= 11;
when X"72" | X"32" | X"d2" | X"52" | X"b2" | X"12" | X"f2" | X"92" =>
adr_type <= 12;
when X"67" | X"27" | X"c7" | X"47" | X"a7" | X"07" | X"e7" | X"87" =>
adr_type <= 13;
when X"73" | X"33" | X"d3" | X"53" | X"b3" | X"13" | X"f3" | X"93" =>
adr_type <= 14;
when X"61" | X"c1" | X"41" | X"a1" | X"01" | X"e1" | X"81" =>
adr_type <= 15;
when X"71" | X"31" | X"d1" | X"51" | X"b1" | X"11" | X"f1" | X"91" =>
adr_type <= 16;
when X"77" | X"37" | X"d7" | X"57" | X"b7" | X"17" | X"f7" | X"97" =>
adr_type <= 17;
when X"18" | X"d8" | X"58" | X"b8" | X"ca" | X"88" | X"e8" | X"c8" | X"ea" | X"38" | X"f8" | X"78" | X"db" | X"aa" | X"5b" | X"1b" | X"7b" =>
adr_type <= 18;
when X"b0" | X"f0" | X"90" | X"d0" | X"10" | X"80" | X"50" | X"70" =>
adr_type <= 19;
when X"82" =>
adr_type <= 20;
when X"00" | X"02" | X"f4" | X"d4" | X"62" | X"48" | X"8b" | X"0b" | X"4b" | X"08" | X"da" | X"5a" | X"68" | X"ab" | X"2b" | X"28" | X"fa" | X"7a" | X"40" | X"6b" | X"60" =>
adr_type <= 21;
when X"54" | X"44" =>
adr_type <= 22;
when X"69" | X"29" | X"89" | X"c9" | X"e0" | X"c0" | X"49" | X"a9" | X"a2" | X"a0" | X"09" | X"c2" | X"e9" | X"e2" =>
adr_type <= 23;
when others =>
adr_type <= 0;
end case;
addressing_done <= '1';
end if;
end process;
--
-- This process reverses the byte order
-- of instruction arguments so that
-- a memory pointer or argument can
-- be precisely used
--
memory_pointer_calculation:
process (memory_calculate_on) is
begin
memory_calculate_done <= '0';
if memory_calculate_on = '1' then
case instruction_size is
when X"2" =>
memory_pointer <= X"0000" & chunk_pull (23 downto 16);
when X"3" =>
memory_pointer <= X"00" & chunk_pull(15 downto 8) & chunk_pull (23 downto 16);
when X"4" =>
memory_pointer <= chunk_pull (7 downto 0) & chunk_pull(15 downto 8) & chunk_pull (23 downto 16);
when others =>
memory_pointer <= (others => '0');
end case;
memory_calculate_done <= '1';
end if;
end process;
--
-- This process will decode the OPcode byte.
-- It will then assign instruction_info all relevent data.
--
opcode_info:
process (decode_on) is
begin
decode_done <= '0';
if reset = '1' then
instruction_info <= (others => '0');-- clear instruction info
elsif (decode_on = '1') then
--
--
-- intstruction_info syntax is
-- bytes + cycles + type
--
-- Flags (on reset) :
-- N V M X D I Z C_FLAG/E
-- P = * * 1 1 0 1 * */1
-- * = Not Initialized
-- STP and WAI instructions are cleared.
-- Type Table:
-- 0 -> Arithmatic
-- 1 -> PC
-- 2 -> Memory
-- 3 -> Coprocessor
-- 4 -> Flag
-- 5 -> Stack
-- 6 -> NOP (and non used)
-- 7 -> Exchange
-- 8 -> Interrupt
--
--
--
--
case op_code is
--
-- BRK (break)
-- pc+2 onto stack, processor status onto stack
-- Also set I flag = 1
--
-- !!!!!!!!!!!!! TODO: Implemented as a NOP for now due to issues with interrupts
-- !!!!!!!!!!!!!!!!!!!!!!!!!!! X"270" is now X"126"
when X"00" =>
instruction_info <= X"126";
-- ADC
-- The following are Add memory to accumulator with cary
-- A_REG + M + C_FLAG -> A_REG, C_FLAG
--
when X"69" =>
instruction_info <= X"220";
when X"65" =>
instruction_info <= X"230";
when X"75" =>
instruction_info <= X"240";
when X"6D" =>
instruction_info <= X"340";
when X"7D" =>
instruction_info <= X"340";
when X"79" =>
instruction_info <= X"340";
when X"61" =>
instruction_info <= X"260";
when X"71" =>
instruction_info <= X"250";
-- AND
-- The follwing are logical AND's with accumulator
-- A_REG and M -> A_REG
--
--
when X"29" =>
instruction_info <= X"220";
when X"25" =>
instruction_info <= X"230";
when X"35" =>
instruction_info <= X"240";
when X"2D" =>
instruction_info <= X"340";
when X"3D" =>
instruction_info <= X"340";
when X"39" =>
instruction_info <= X"340";
when X"21" =>
instruction_info <= X"260";
when X"31" =>
instruction_info <= X"250";
--
-- The following are ASL
-- left shift by one
-- memory or accumulator
--
when X"0A" =>
instruction_info <= X"120";
when X"06" =>
instruction_info <= X"250";
when X"16" =>
instruction_info <= X"260";
when X"0E" =>
instruction_info <= X"360";
when X"1E" =>
instruction_info <= X"370";
-- BCC
-- Branch on carry clear
-- when carry flag = 0, branch
-- * + 1 cycle if branch happens
when X"90" =>
instruction_info <= X"221";
-- BEQ
-- branch on zero flag set
-- * + 1 cycle if branch happens
when X"F0" =>
instruction_info <= X"221";
-- BIT
-- Accumulator AND'd with memory,
-- bit 7 of memory goes to Negative flag
-- bit 6 of memoyr goes to overflow flag
-- If A_REG and M = 0 then Z = 1 , else 0
when X"24" =>
instruction_info <= X"234";
when X"2C" =>
instruction_info <= X"344";
-- BMI
-- Branch On Negative Flag Set
-- * + 1 Cycle If Can Branch
when X"30" =>
instruction_info <= X"221";
-- BNE
-- Branch on zero flag not set
-- * + 1 cycle if can do
--
when X"D0" =>
instruction_info <= X"221";
-- BPL
-- Brnach when N flag not set.
-- * + 1 cycle if can do
--
when X"10" =>
instruction_info <= X"221";
-- BVC
-- Branch on V flag = 0
-- * +1 cycle if can do
when X"50" =>
instruction_info <= X"221";
-- BVS
-- Branch when V flag set
-- * + 1 cycle if can do
when X"70" =>
instruction_info <= X"221";
-- CLC
-- Clear the carry flag
--
when X"18" =>
instruction_info <= X"124";
-- CLD
-- Clear the decimal flag
--
when X"D8" =>
instruction_info <= X"124";
-- CLI
-- Clear interupt bit
--
when X"58" =>
instruction_info <= X"124";
-- CLV
-- Clear the overflow flag
--
when X"B8" =>
instruction_info <= X"124";
-- CMP
-- Compar memory and accumulator
-- Set N, Z, or C_FLAG flag accordingly
-- A_REG - M
--
when X"c9" =>
instruction_info <= X"220";
when X"c5" =>
instruction_info <= X"230";
when X"D5" =>
instruction_info <= X"240";
when X"DD" =>
instruction_info <= X"340";
when X"d9" =>
instruction_info <= X"340";
when X"c1" =>
instruction_info <= X"260";
when X"d1" =>
instruction_info <= X"250";
-- CPX
-- Compary memory and X reg
-- X - M and set N, Z, C_FLAG flags as needed
--
when X"E0" =>
instruction_info <= X"220";
when X"E4" =>
instruction_info <= X"230";
when X"EC" =>
instruction_info <= X"340";
-- CPY
-- Compary memory and Y_REG reg
-- Y_REG - M
-- Set N, Z, and C_FLAG flags as needed.
--
when X"C0" =>
instruction_info <= X"220";
when X"C4" =>
instruction_info <= X"230";
when X"cc" =>
instruction_info <= X"340";
-- DEC
-- Decrimeent memory by 1
-- M - 1 -> M
-- Use N & Z flags
when X"C6" =>
instruction_info <= X"252";
when X"D6" =>
instruction_info <= X"262";
when X"ce" =>
instruction_info <= X"362";
when X"de" =>
instruction_info <= X"372";
-- DEX
-- Decriment X reg by 1
-- X - 1 -> X
-- use N & Z flags
when X"CA" =>
instruction_info <= X"120";
-- DEY
-- Decriment Y_REG reg by 1
-- Y_REG - 1 -> Y_REG
-- N & Z flags
--
when X"88" =>
instruction_info <= X"120";
-- EOR
-- Acc XOR Mem -> Acc
-- N and Z flags
--
when X"49" =>
instruction_info <= X"220";
when X"45" =>
instruction_info <= X"230";
when X"55" =>
instruction_info <= X"240";
when X"4d" =>
instruction_info <= X"340";
when X"5d" =>
instruction_info <= X"340";
when X"59" =>
instruction_info <= X"340";
when X"41" =>
instruction_info <= X"260";
when X"51" =>
instruction_info <= X"250";
-- INC
-- Incriment memory by one
-- M + 1 -> M
-- N & Z flags
--
when X"E6" =>
instruction_info <= X"252";
when X"F6" =>
instruction_info <= X"262";
when X"ee" =>
instruction_info <= X"362";
when X"fe" =>
instruction_info <= X"372";
-- INX
-- Incriment X by one
-- X + 1 -> X
-- N & Z flags
--
when X"e8" =>
instruction_info <= X"120";
-- INY
-- Incriment Y_REG by one
-- Y_REG + 1 -> Y_REG
-- N & Z flags
--
when X"c8" =>
instruction_info <= X"120";
--
--
-- JMP
-- JUMP INSTRUCTIONS
--=======================================================================
-- JMP
-- Jump to location
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--JMP absolute
--take contents of memory location
--1 byte from opcode and store into
--PC LOW, then take the very next byte
--and store into PC HIGH
-- REVERSE BYTE ORDER AND MAKE NEW PC
when X"4c" =>
instruction_info <= X"331";
--JMP indirect
-- starts out the same as above, but
-- instead of getting the opcode at the new PC,
-- a new PC is again fetched in the same way.
-- making this a jump to a jump.
when X"6c" =>
instruction_info <= X"351";
--=======================================================================
--
--
--
--
-- JSR
-- Jump to subroutine
-- PC + 2 -> stack
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--
when X"20" =>
instruction_info <= X"361";
-- LDA
-- Load accumulator with memory
-- M -> A_REG
-- N & Z flags
when X"a9" =>
instruction_info <= X"222";
when X"a5" =>
instruction_info <= X"232";
when X"b5" =>
instruction_info <= X"242";
when X"ad" =>
instruction_info <= X"342";
when X"bd" =>
instruction_info <= X"342";
when X"b9" =>
instruction_info <= X"342";
when X"a1" =>
instruction_info <= X"262";
when X"b1" =>
instruction_info <= X"252";
-- LDX
-- Load X with memory
-- M -> X
-- N & Z flags
--
when X"a2" =>
instruction_info <= X"222";
when X"a6" =>
instruction_info <= X"232";
when X"b6" =>
instruction_info <= X"242";
when X"ae" =>
instruction_info <= X"342";
when X"be" =>
instruction_info <= X"342";
-- LDY
-- Load Y_REG with memory
-- M -> Y_REG
-- N & Z Flags
--
when X"a0" =>
instruction_info <= X"222";
when X"a4" =>
instruction_info <= X"232";
when X"b4" =>
instruction_info <= X"242";
when X"ac" =>
instruction_info <= X"342";
when X"bc" =>
instruction_info <= X"342";
-- LSR
-- Right shift one bit
-- 0 -> [bits] -> C_FLAG
-- C_FLAG & Z flag, N flag zerod
--
when X"4a" =>
instruction_info <= X"120";
when X"46" =>
instruction_info <= X"250";
when X"56" =>
instruction_info <= X"260";
when X"4e" =>
instruction_info <= X"360";
when X"5e" =>
instruction_info <= X"370";
-- NOP
-- No operation
--
when X"ea" =>
instruction_info <= X"126";
-- ORA
-- Or with accumulator
-- A_REG (or) M -> A_REG
-- N & Z flags
--
when X"09" =>
instruction_info <= X"220";
when X"05" =>
instruction_info <= X"230";
when X"15" =>
instruction_info <= X"240";
when X"0d" =>
instruction_info <= X"340";
when X"1d" =>
instruction_info <= X"340";
when X"19" =>
instruction_info <= X"340";
when X"01" =>
instruction_info <= X"260";
when X"11" =>
instruction_info <= X"250";
-- PHA
-- Push accumuator to stack
-- A_REG -> STACK
-- NO FLAGS
when X"48" =>
instruction_info <= X"135";
-- PHP
-- Push processor status on stack
-- P -> STACK
when X"08" =>
instruction_info <= X"135";
-- PLA
-- Pull accumulator from stack
-- STACK -> A_REG
-- N & Z flags
--
when X"68" =>
instruction_info <= X"145";
-- PLP
-- Pull processor status from stack
-- STACK -> P
-- ALL FLAGS CAN CHANGE
when X"28" =>
instruction_info <= X"145";
-- ROL
-- Rotate one bit left
-- [bit 7] -> C_FLAG FLAG
-- [ <- bits 6 - 0] [C_FLAG FLAG (becomes 0 bit)]
-- N & Z & C_FLAG FLAGS
--
when X"2a" =>
instruction_info <= X"120";
when X"26" =>
instruction_info <= X"250";
when X"36" =>
instruction_info <= X"260";
when X"2e" =>
instruction_info <= X"360";
when X"3e" =>
instruction_info <= X"270";
-- ROR
-- Rotate right one
-- [C_FLAG FLAG -> bit 7] [bits 7 - 1 ] [bit 0 becomes C_FLAG flag]
-- N & Z & C_FLAG
--
when X"6a" =>
instruction_info <= X"120";
when X"66" =>
instruction_info <= X"250";
when X"76" =>
instruction_info <= X"260";
when X"6e" =>
instruction_info <= X"360";
when X"7e" =>
instruction_info <= X"370";
-- RTI
-- Return from Interrupt
-- STACK -> P
-- STACK -> PC
-- FLAGS FROM STACK
--
when X"40" =>
instruction_info <= X"168";
-- RTS
-- Reutrn from subroutine
-- STACK -> PC
-- PC + 1 -> PC
-- NO FLAGS
--
when X"60" =>
instruction_info <= X"161";
-- SBC
-- Subtract memory from accumulator w/ borrow
-- A_REG - M - (not) C_FLAG -> Accumulator
-- N & Z & C_FLAG & V Flags
--
when X"e9" =>
instruction_info <= X"220";
when X"e5" =>
instruction_info <= X"230";
when X"f5" =>
instruction_info <= X"240";
when X"ed" =>
instruction_info <= X"340";
when X"fd" =>
instruction_info <= X"340";
when X"f9" =>
instruction_info <= X"340";
when X"e1" =>
instruction_info <= X"260";
when X"f1" =>
instruction_info <= X"250";
-- SEC
-- Set carry flag
-- 1 -> C_FLAG
-- C_FLAG Flag
--
when X"38" =>
instruction_info <= X"124";
-- SED
-- Set decimal flag
-- 1 -> D
-- D flag
--
when X"f8" =>
instruction_info <= X"124";
-- SEI
-- Set interrupt disable flag
-- 1 -> I
-- I FLAG
when X"78" =>
instruction_info <= X"124";
-- STA
-- Store accumulator in memory
-- A_REG -> M
-- no flags
--
when X"85" =>
instruction_info <= X"232";
when X"95" =>
instruction_info <= X"242";
when X"8d" =>
instruction_info <= X"342";
when X"9d" =>
instruction_info <= X"352";
when X"99" =>
instruction_info <= X"352";
when X"81" =>
instruction_info <= X"262";
when X"91" =>
instruction_info <= X"262";
-- STX
-- Store X in memory
-- X -> M
--
when X"86" =>
instruction_info <= X"232";
when X"96" =>
instruction_info <= X"242";
when X"8e" =>
instruction_info <= X"342";
-- STY
-- Store y in memory
-- Y_REG -> M
--
when X"84" =>
instruction_info <= X"232";
when X"94" =>
instruction_info <= X"242";
when X"8c" =>
instruction_info <= X"342";
-- TAX
-- Transfer A_REG to X
-- A_REG -> X
-- N & Z
--
when X"AA" =>
instruction_info <= X"127";
-- TAY
-- X-fer A_REG to Y_REG
-- A_REG -> Y_REG
-- N & Z
--
when X"a8" =>
instruction_info <= X"127";
-- TYA
-- X-fer Y_REG to A_REG
-- Y_REG -> A_REG
-- N & Z
--
when X"98" =>
instruction_info <= X"127";
-- TSX
-- X-fer stack pointer to X
-- S -> X
-- N & Z
--
when X"ba" =>
instruction_info <= X"127";
-- TXA
-- X-fer X to Accumulator
-- X -> A_REG
-- N & Z
--
when X"8A" =>
instruction_info <= X"127";
-- TXS
-- X-fer X to stack pointer
-- X -> S
--
when X"9a" =>
instruction_info <= X"127";
-- XBA
-- Exchange B & A_REG Accumulators
-- A_REG <-> B
-- Remeber that A_REG is the lower 8 bits of C_FLAG
-- and that B is the upper 8 bits of C_FLAG
--
when X"EB" =>
instruction_info <= X"137";
-- XCE
-- Exchange Carry and Emulation flags
-- E Flag <-> C_FLAG Flag
-- Even though this manipulates
-- flag bits, note that it is
-- EXCHANGE type instruction for
-- this implementation.
--
when X"FB" =>
instruction_info <= X"127";
--
-- All other instructions are NOP's
--
when others =>
instruction_info <= X"126";
end case;
decode_done <= '1';
end if;
end process;
end architecture;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set.vhd
|
18
|
30582
|
-------------------------------------------------------------------------------
-- axi_datamover_stbs_set.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_stbs_set.vhd
--
-- Description:
-- This file implements a module to count the number of strobe bits that
-- are asserted active high on the input strobe bus. This module does not
-- support sparse strobe assertions.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_stbs_set is
generic (
C_STROBE_WIDTH : Integer range 1 to 128 := 8
-- Specifies the width (in bits) of the input strobe bus.
);
port (
-- Input Strobe bus ----------------------------------------------------
--
tstrb_in : in std_logic_vector(C_STROBE_WIDTH-1 downto 0); --
------------------------------------------------------------------------
-- Asserted Strobes count output ---------------------------------------
--
num_stbs_asserted : Out std_logic_vector(7 downto 0) --
-- Indicates the number of asserted tstrb_in bits --
------------------------------------------------------------------------
);
end entity axi_datamover_stbs_set;
architecture implementation of axi_datamover_stbs_set is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_8bit_stbs_set
--
-- Function Description:
-- Implements an 8-bit lookup table for calculating the number
-- of asserted bits within an 8-bit strobe vector.
--
-- Note that this function assumes that asserted strobes are
-- contiguous with each other (no sparse strobe assertions).
--
-------------------------------------------------------------------
function funct_8bit_stbs_set (strb_8 : std_logic_vector(7 downto 0)) return unsigned is
Constant ASSERTED_VALUE_WIDTH : integer := 4;-- 4 bits needed
Variable lvar_num_set : Integer range 0 to 8 := 0;
begin
case strb_8 is
------- 1 bit --------------------------
when "00000001" | "00000010" | "00000100" | "00001000" |
"00010000" | "00100000" | "01000000" | "10000000" =>
lvar_num_set := 1;
------- 2 bit --------------------------
when "00000011" | "00000110" | "00001100" | "00011000" |
"00110000" | "01100000" | "11000000" =>
lvar_num_set := 2;
------- 3 bit --------------------------
when "00000111" | "00001110" | "00011100" | "00111000" |
"01110000" | "11100000" =>
lvar_num_set := 3;
------- 4 bit --------------------------
when "00001111" | "00011110" | "00111100" | "01111000" |
"11110000" =>
lvar_num_set := 4;
------- 5 bit --------------------------
when "00011111" | "00111110" | "01111100" | "11111000" =>
lvar_num_set := 5;
------- 6 bit --------------------------
when "00111111" | "01111110" | "11111100" =>
lvar_num_set := 6;
------- 7 bit --------------------------
when "01111111" | "11111110" =>
lvar_num_set := 7;
------- 8 bit --------------------------
when "11111111" =>
lvar_num_set := 8;
------- all zeros or sparse strobes ------
When others =>
lvar_num_set := 0;
end case;
Return (TO_UNSIGNED(lvar_num_set, ASSERTED_VALUE_WIDTH));
end function funct_8bit_stbs_set;
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_FOR_STBS_ASSERTED : integer := 8; -- increments of 8 bits
Constant NUM_ZEROS_WIDTH : integer := BITS_FOR_STBS_ASSERTED;
-- Signals
signal sig_strb_input : std_logic_vector(C_STROBE_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs_asserted : std_logic_vector(BITS_FOR_STBS_ASSERTED-1 downto 0) := (others => '0');
begin --(architecture implementation)
num_stbs_asserted <= sig_stbs_asserted;
sig_strb_input <= tstrb_in ;
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1_STRB
--
-- If Generate Description:
-- 1-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_1_STRB : if (C_STROBE_WIDTH = 1) generate
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_1BIT_STRB
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_1BIT_STRB : process (sig_strb_input)
begin
-- Concatonate the strobe to the ls bit of
-- the asserted value
sig_stbs_asserted <= "0000000" &
sig_strb_input(0);
end process IMP_1BIT_STRB;
end generate GEN_1_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2_STRB
--
-- If Generate Description:
-- 2-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_2_STRB : if (C_STROBE_WIDTH = 2) generate
signal lsig_num_set : integer range 0 to 2 := 0;
signal lsig_strb_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_2BIT_STRB
--
-- Process Description:
-- Calculates the number of strobes set fo the 2-bit
-- strobe case
--
-------------------------------------------------------------
IMP_2BIT_STRB : process (lsig_strb_vect)
begin
case lsig_strb_vect is
when "01" | "10" =>
lsig_num_set <= 1;
when "11" =>
lsig_num_set <= 2;
when others =>
lsig_num_set <= 0;
end case;
end process IMP_2BIT_STRB;
sig_stbs_asserted <= STD_LOGIC_VECTOR(TO_UNSIGNED(lsig_num_set,
BITS_FOR_STBS_ASSERTED));
end generate GEN_2_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4_STRB
--
-- If Generate Description:
-- 4-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_4_STRB : if (C_STROBE_WIDTH = 4) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= "0000" & sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_4_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8_STRB
--
-- If Generate Description:
-- 8-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_8_STRB : if (C_STROBE_WIDTH = 8) generate
signal lsig_strb_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_strb_vect <= sig_strb_input; -- make and 8-bit vector
-- for the function call
sig_stbs_asserted <= STD_LOGIC_VECTOR(RESIZE(funct_8bit_stbs_set(lsig_strb_vect),
BITS_FOR_STBS_ASSERTED));
end generate GEN_8_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16_STRB
--
-- If Generate Description:
-- 16-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_16_STRB : if (C_STROBE_WIDTH = 16) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_16_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32_STRB
--
-- If Generate Description:
-- 32-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_32_STRB : if (C_STROBE_WIDTH = 32) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_32_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64_STRB
--
-- If Generate Description:
-- 64-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_64_STRB : if (C_STROBE_WIDTH = 64) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_64_STRB;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128_STRB
--
-- If Generate Description:
-- 128-bit strobe bus width case
--
--
------------------------------------------------------------
GEN_128_STRB : if (C_STROBE_WIDTH = 128) generate
Constant RESULT_BIT_WIDTH : integer := 8;
signal lsig_strb_vect1 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect2 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect3 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect4 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect5 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect6 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect7 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect8 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect9 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect10 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect11 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect12 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect13 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect14 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect15 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_strb_vect16 : std_logic_vector(7 downto 0) := (others => '0');
signal lsig_num_in_stbs1 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs2 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs3 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs4 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs5 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs6 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs7 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs8 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs9 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs10 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs11 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs12 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs13 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs14 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs15 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_in_stbs16 : unsigned(3 downto 0) := (others => '0');
signal lsig_num_total : unsigned(RESULT_BIT_WIDTH-1 downto 0) := (others => '0');
begin
lsig_strb_vect1 <= sig_strb_input(7 downto 0); -- make and 8-bit vector
-- for the function call
lsig_strb_vect2 <= sig_strb_input(15 downto 8); -- make and 8-bit vector
-- for the function call
lsig_strb_vect3 <= sig_strb_input(23 downto 16); -- make and 8-bit vector
-- for the function call
lsig_strb_vect4 <= sig_strb_input(31 downto 24); -- make and 8-bit vector
-- for the function call
lsig_strb_vect5 <= sig_strb_input(39 downto 32); -- make and 8-bit vector
-- for the function call
lsig_strb_vect6 <= sig_strb_input(47 downto 40); -- make and 8-bit vector
-- for the function call
lsig_strb_vect7 <= sig_strb_input(55 downto 48); -- make and 8-bit vector
-- for the function call
lsig_strb_vect8 <= sig_strb_input(63 downto 56); -- make and 8-bit vector
-- for the function call
lsig_strb_vect9 <= sig_strb_input(71 downto 64); -- make and 8-bit vector
-- for the function call
lsig_strb_vect10 <= sig_strb_input(79 downto 72); -- make and 8-bit vector
-- for the function call
lsig_strb_vect11 <= sig_strb_input(87 downto 80); -- make and 8-bit vector
-- for the function call
lsig_strb_vect12 <= sig_strb_input(95 downto 88); -- make and 8-bit vector
-- for the function call
lsig_strb_vect13 <= sig_strb_input(103 downto 96); -- make and 8-bit vector
-- for the function call
lsig_strb_vect14 <= sig_strb_input(111 downto 104); -- make and 8-bit vector
-- for the function call
lsig_strb_vect15 <= sig_strb_input(119 downto 112); -- make and 8-bit vector
-- for the function call
lsig_strb_vect16 <= sig_strb_input(127 downto 120); -- make and 8-bit vector
-- for the function call
lsig_num_in_stbs1 <= funct_8bit_stbs_set(lsig_strb_vect1) ;
lsig_num_in_stbs2 <= funct_8bit_stbs_set(lsig_strb_vect2) ;
lsig_num_in_stbs3 <= funct_8bit_stbs_set(lsig_strb_vect3) ;
lsig_num_in_stbs4 <= funct_8bit_stbs_set(lsig_strb_vect4) ;
lsig_num_in_stbs5 <= funct_8bit_stbs_set(lsig_strb_vect5) ;
lsig_num_in_stbs6 <= funct_8bit_stbs_set(lsig_strb_vect6) ;
lsig_num_in_stbs7 <= funct_8bit_stbs_set(lsig_strb_vect7) ;
lsig_num_in_stbs8 <= funct_8bit_stbs_set(lsig_strb_vect8) ;
lsig_num_in_stbs9 <= funct_8bit_stbs_set(lsig_strb_vect9) ;
lsig_num_in_stbs10 <= funct_8bit_stbs_set(lsig_strb_vect10) ;
lsig_num_in_stbs11 <= funct_8bit_stbs_set(lsig_strb_vect11) ;
lsig_num_in_stbs12 <= funct_8bit_stbs_set(lsig_strb_vect12) ;
lsig_num_in_stbs13 <= funct_8bit_stbs_set(lsig_strb_vect13) ;
lsig_num_in_stbs14 <= funct_8bit_stbs_set(lsig_strb_vect14) ;
lsig_num_in_stbs15 <= funct_8bit_stbs_set(lsig_strb_vect15) ;
lsig_num_in_stbs16 <= funct_8bit_stbs_set(lsig_strb_vect16) ;
lsig_num_total <= RESIZE(lsig_num_in_stbs1 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs2 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs3 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs4 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs5 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs6 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs7 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs8 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs9 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs10 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs11 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs12 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs13 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs14 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs15 , RESULT_BIT_WIDTH) +
RESIZE(lsig_num_in_stbs16 , RESULT_BIT_WIDTH);
sig_stbs_asserted <= STD_LOGIC_VECTOR(lsig_num_total);
end generate GEN_128_STRB;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/bd/block_design/hdl/block_design.vhd
|
2
|
140430
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Wed Aug 17 18:50:03 2016
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target block_design.bd
--Design : block_design
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1X21ZCV is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1X21ZCV;
architecture STRUCTURE of m00_couplers_imp_1X21ZCV is
component block_design_m00_regslice_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_m00_regslice_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_regslice_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_regslice_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_regslice_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_regslice_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_regslice_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_regslice_WVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_regslice_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_regslice_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_regslice_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_regslice_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_regslice_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_regslice_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_regslice_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_regslice_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_regslice_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1(0) <= M_ARESETN(0);
M_AXI_araddr(5 downto 0) <= m00_regslice_to_m00_couplers_ARADDR(5 downto 0);
M_AXI_arprot(2 downto 0) <= m00_regslice_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m00_regslice_to_m00_couplers_ARVALID;
M_AXI_awaddr(5 downto 0) <= m00_regslice_to_m00_couplers_AWADDR(5 downto 0);
M_AXI_awprot(2 downto 0) <= m00_regslice_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m00_regslice_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_regslice_to_m00_couplers_BREADY;
M_AXI_rready <= m00_regslice_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_regslice_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_regslice_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_regslice_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_regslice_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_regslice_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_regslice_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_regslice_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_regslice_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_regslice_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_regslice_RVALID;
S_AXI_wready <= m00_couplers_to_m00_regslice_WREADY;
m00_couplers_to_m00_regslice_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_regslice_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_regslice_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_regslice_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_regslice_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_regslice_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_regslice_BREADY <= S_AXI_bready;
m00_couplers_to_m00_regslice_RREADY <= S_AXI_rready;
m00_couplers_to_m00_regslice_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_regslice_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_regslice_WVALID <= S_AXI_wvalid;
m00_regslice_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_regslice_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_regslice_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_regslice_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_regslice_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_regslice_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_regslice_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_regslice_to_m00_couplers_WREADY <= M_AXI_wready;
m00_regslice: component block_design_m00_regslice_0
port map (
aclk => M_ACLK_1,
aresetn => M_ARESETN_1(0),
m_axi_araddr(5 downto 0) => m00_regslice_to_m00_couplers_ARADDR(5 downto 0),
m_axi_arprot(2 downto 0) => m00_regslice_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready => m00_regslice_to_m00_couplers_ARREADY,
m_axi_arvalid => m00_regslice_to_m00_couplers_ARVALID,
m_axi_awaddr(5 downto 0) => m00_regslice_to_m00_couplers_AWADDR(5 downto 0),
m_axi_awprot(2 downto 0) => m00_regslice_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready => m00_regslice_to_m00_couplers_AWREADY,
m_axi_awvalid => m00_regslice_to_m00_couplers_AWVALID,
m_axi_bready => m00_regslice_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => m00_regslice_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => m00_regslice_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => m00_regslice_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready => m00_regslice_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => m00_regslice_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => m00_regslice_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => m00_regslice_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready => m00_regslice_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => m00_regslice_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => m00_regslice_to_m00_couplers_WVALID,
s_axi_araddr(5 downto 0) => m00_couplers_to_m00_regslice_ARADDR(5 downto 0),
s_axi_arprot(2 downto 0) => m00_couplers_to_m00_regslice_ARPROT(2 downto 0),
s_axi_arready => m00_couplers_to_m00_regslice_ARREADY,
s_axi_arvalid => m00_couplers_to_m00_regslice_ARVALID,
s_axi_awaddr(5 downto 0) => m00_couplers_to_m00_regslice_AWADDR(5 downto 0),
s_axi_awprot(2 downto 0) => m00_couplers_to_m00_regslice_AWPROT(2 downto 0),
s_axi_awready => m00_couplers_to_m00_regslice_AWREADY,
s_axi_awvalid => m00_couplers_to_m00_regslice_AWVALID,
s_axi_bready => m00_couplers_to_m00_regslice_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_m00_regslice_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_m00_regslice_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_m00_regslice_RDATA(31 downto 0),
s_axi_rready => m00_couplers_to_m00_regslice_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_m00_regslice_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_m00_regslice_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_m00_regslice_WDATA(31 downto 0),
s_axi_wready => m00_couplers_to_m00_regslice_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_m00_regslice_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_m00_regslice_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1UJ7QBJ is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1UJ7QBJ;
architecture STRUCTURE of m01_couplers_imp_1UJ7QBJ is
component block_design_m01_regslice_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_m01_regslice_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_regslice_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_regslice_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_regslice_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_regslice_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_regslice_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_regslice_WVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_regslice_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_regslice_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_regslice_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_regslice_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_regslice_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_regslice_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_WVALID : STD_LOGIC;
signal NLW_m01_regslice_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_m01_regslice_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_m01_regslice_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1(0) <= M_ARESETN(0);
M_AXI_araddr(8 downto 0) <= m01_regslice_to_m01_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= m01_regslice_to_m01_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= m01_regslice_to_m01_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= m01_regslice_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_regslice_to_m01_couplers_BREADY;
M_AXI_rready <= m01_regslice_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_regslice_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m01_regslice_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_regslice_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_regslice_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_regslice_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_regslice_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_regslice_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_regslice_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_regslice_RVALID;
S_AXI_wready <= m01_couplers_to_m01_regslice_WREADY;
m01_couplers_to_m01_regslice_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_regslice_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_regslice_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_regslice_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_regslice_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_regslice_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_regslice_BREADY <= S_AXI_bready;
m01_couplers_to_m01_regslice_RREADY <= S_AXI_rready;
m01_couplers_to_m01_regslice_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_regslice_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_regslice_WVALID <= S_AXI_wvalid;
m01_regslice_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_regslice_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_regslice_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_regslice_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_regslice_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_regslice_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_regslice_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_regslice_to_m01_couplers_WREADY <= M_AXI_wready;
m01_regslice: component block_design_m01_regslice_0
port map (
aclk => M_ACLK_1,
aresetn => M_ARESETN_1(0),
m_axi_araddr(8 downto 0) => m01_regslice_to_m01_couplers_ARADDR(8 downto 0),
m_axi_arprot(2 downto 0) => NLW_m01_regslice_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => m01_regslice_to_m01_couplers_ARREADY,
m_axi_arvalid => m01_regslice_to_m01_couplers_ARVALID,
m_axi_awaddr(8 downto 0) => m01_regslice_to_m01_couplers_AWADDR(8 downto 0),
m_axi_awprot(2 downto 0) => NLW_m01_regslice_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => m01_regslice_to_m01_couplers_AWREADY,
m_axi_awvalid => m01_regslice_to_m01_couplers_AWVALID,
m_axi_bready => m01_regslice_to_m01_couplers_BREADY,
m_axi_bresp(1 downto 0) => m01_regslice_to_m01_couplers_BRESP(1 downto 0),
m_axi_bvalid => m01_regslice_to_m01_couplers_BVALID,
m_axi_rdata(31 downto 0) => m01_regslice_to_m01_couplers_RDATA(31 downto 0),
m_axi_rready => m01_regslice_to_m01_couplers_RREADY,
m_axi_rresp(1 downto 0) => m01_regslice_to_m01_couplers_RRESP(1 downto 0),
m_axi_rvalid => m01_regslice_to_m01_couplers_RVALID,
m_axi_wdata(31 downto 0) => m01_regslice_to_m01_couplers_WDATA(31 downto 0),
m_axi_wready => m01_regslice_to_m01_couplers_WREADY,
m_axi_wstrb(3 downto 0) => NLW_m01_regslice_m_axi_wstrb_UNCONNECTED(3 downto 0),
m_axi_wvalid => m01_regslice_to_m01_couplers_WVALID,
s_axi_araddr(8 downto 0) => m01_couplers_to_m01_regslice_ARADDR(8 downto 0),
s_axi_arprot(2 downto 0) => m01_couplers_to_m01_regslice_ARPROT(2 downto 0),
s_axi_arready => m01_couplers_to_m01_regslice_ARREADY,
s_axi_arvalid => m01_couplers_to_m01_regslice_ARVALID,
s_axi_awaddr(8 downto 0) => m01_couplers_to_m01_regslice_AWADDR(8 downto 0),
s_axi_awprot(2 downto 0) => m01_couplers_to_m01_regslice_AWPROT(2 downto 0),
s_axi_awready => m01_couplers_to_m01_regslice_AWREADY,
s_axi_awvalid => m01_couplers_to_m01_regslice_AWVALID,
s_axi_bready => m01_couplers_to_m01_regslice_BREADY,
s_axi_bresp(1 downto 0) => m01_couplers_to_m01_regslice_BRESP(1 downto 0),
s_axi_bvalid => m01_couplers_to_m01_regslice_BVALID,
s_axi_rdata(31 downto 0) => m01_couplers_to_m01_regslice_RDATA(31 downto 0),
s_axi_rready => m01_couplers_to_m01_regslice_RREADY,
s_axi_rresp(1 downto 0) => m01_couplers_to_m01_regslice_RRESP(1 downto 0),
s_axi_rvalid => m01_couplers_to_m01_regslice_RVALID,
s_axi_wdata(31 downto 0) => m01_couplers_to_m01_regslice_WDATA(31 downto 0),
s_axi_wready => m01_couplers_to_m01_regslice_WREADY,
s_axi_wstrb(3 downto 0) => m01_couplers_to_m01_regslice_WSTRB(3 downto 0),
s_axi_wvalid => m01_couplers_to_m01_regslice_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1RQO0KS is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1RQO0KS;
architecture STRUCTURE of s00_couplers_imp_1RQO0KS is
component block_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component block_design_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_QE4JF is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s00_couplers_imp_QE4JF;
architecture STRUCTURE of s00_couplers_imp_QE4JF is
component block_design_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_s00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_s00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_rdata(63 downto 0) <= s00_couplers_to_auto_pc_RDATA(63 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_pc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
auto_pc: component block_design_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(3 downto 0) => auto_pc_to_s00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_s00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_pc_to_s00_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_pc_to_s00_couplers_RLAST,
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_rdata(63 downto 0) => s00_couplers_to_auto_pc_RDATA(63 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end block_design_axi_interconnect_0_0;
architecture STRUCTURE of block_design_axi_interconnect_0_0 is
component block_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component block_design_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(5 downto 0) <= m00_couplers_to_axi_interconnect_0_ARADDR(5 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(5 downto 0) <= m00_couplers_to_axi_interconnect_0_AWADDR(5 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_interconnect_0_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(8 downto 0) <= m01_couplers_to_axi_interconnect_0_ARADDR(8 downto 0);
M01_AXI_arvalid <= m01_couplers_to_axi_interconnect_0_ARVALID;
M01_AXI_awaddr(8 downto 0) <= m01_couplers_to_axi_interconnect_0_AWADDR(8 downto 0);
M01_AXI_awvalid <= m01_couplers_to_axi_interconnect_0_AWVALID;
M01_AXI_bready <= m01_couplers_to_axi_interconnect_0_BREADY;
M01_AXI_rready <= m01_couplers_to_axi_interconnect_0_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M01_AXI_wvalid <= m01_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY;
axi_interconnect_0_ACLK_net <= ACLK;
axi_interconnect_0_ARESETN_net(0) <= ARESETN(0);
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
m01_couplers_to_axi_interconnect_0_ARREADY <= M01_AXI_arready;
m01_couplers_to_axi_interconnect_0_AWREADY <= M01_AXI_awready;
m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_BVALID <= M01_AXI_bvalid;
m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_RVALID <= M01_AXI_rvalid;
m01_couplers_to_axi_interconnect_0_WREADY <= M01_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1X21ZCV
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(5 downto 0) => m00_couplers_to_axi_interconnect_0_ARADDR(5 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0),
M_AXI_arready => m00_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(5 downto 0) => m00_couplers_to_axi_interconnect_0_AWADDR(5 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0),
M_AXI_awready => m00_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1UJ7QBJ
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m01_couplers_to_axi_interconnect_0_ARADDR(8 downto 0),
M_AXI_arready => m01_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m01_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(8 downto 0) => m01_couplers_to_axi_interconnect_0_AWADDR(8 downto 0),
M_AXI_awready => m01_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m01_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m01_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wvalid => m01_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
s00_couplers: entity work.s00_couplers_imp_1RQO0KS
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => axi_interconnect_0_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => axi_interconnect_0_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => axi_interconnect_0_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => axi_interconnect_0_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => axi_interconnect_0_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST,
S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID
);
xbar: component block_design_xbar_0
port map (
aclk => axi_interconnect_0_ACLK_net,
aresetn => axi_interconnect_0_ARESETN_net(0),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_axi_interconnect_1_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC
);
end block_design_axi_interconnect_1_0;
architecture STRUCTURE of block_design_axi_interconnect_1_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_1_ACLK_net : STD_LOGIC;
signal axi_interconnect_1_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_1_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_interconnect_1_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_axi_interconnect_1_RLAST : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_1_RVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_1_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_interconnect_1_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_interconnect_1_ARCACHE(3 downto 0);
M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_interconnect_1_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= s00_couplers_to_axi_interconnect_1_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_interconnect_1_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_interconnect_1_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_interconnect_1_ARSIZE(2 downto 0);
M00_AXI_arvalid <= s00_couplers_to_axi_interconnect_1_ARVALID;
M00_AXI_rready <= s00_couplers_to_axi_interconnect_1_RREADY;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_interconnect_1_to_s00_couplers_ARREADY;
S00_AXI_rdata(63 downto 0) <= axi_interconnect_1_to_s00_couplers_RDATA(63 downto 0);
S00_AXI_rlast <= axi_interconnect_1_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_1_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_1_to_s00_couplers_RVALID;
axi_interconnect_1_ACLK_net <= M00_ACLK;
axi_interconnect_1_ARESETN_net(0) <= M00_ARESETN(0);
axi_interconnect_1_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_1_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_1_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_1_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_interconnect_1_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_1_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_1_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_1_to_s00_couplers_RREADY <= S00_AXI_rready;
s00_couplers_to_axi_interconnect_1_ARREADY <= M00_AXI_arready;
s00_couplers_to_axi_interconnect_1_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0);
s00_couplers_to_axi_interconnect_1_RLAST <= M00_AXI_rlast;
s00_couplers_to_axi_interconnect_1_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_interconnect_1_RVALID <= M00_AXI_rvalid;
s00_couplers: entity work.s00_couplers_imp_QE4JF
port map (
M_ACLK => axi_interconnect_1_ACLK_net,
M_ARESETN(0) => axi_interconnect_1_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_1_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_interconnect_1_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_interconnect_1_ARCACHE(3 downto 0),
M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_interconnect_1_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => s00_couplers_to_axi_interconnect_1_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_interconnect_1_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_interconnect_1_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_axi_interconnect_1_ARREADY,
M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_interconnect_1_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_axi_interconnect_1_ARVALID,
M_AXI_rdata(63 downto 0) => s00_couplers_to_axi_interconnect_1_RDATA(63 downto 0),
M_AXI_rlast => s00_couplers_to_axi_interconnect_1_RLAST,
M_AXI_rready => s00_couplers_to_axi_interconnect_1_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_1_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_interconnect_1_RVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_interconnect_1_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_1_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_1_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_interconnect_1_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_1_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_interconnect_1_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_interconnect_1_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_1_to_s00_couplers_ARVALID,
S_AXI_rdata(63 downto 0) => axi_interconnect_1_to_s00_couplers_RDATA(63 downto 0),
S_AXI_rlast => axi_interconnect_1_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_1_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_1_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_1_to_s00_couplers_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 5 downto 0 );
vga_hs : out STD_LOGIC;
vga_r : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_vs : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of block_design : entity is "block_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=block_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=17,numReposBlks=11,numNonXlnxBlks=1,numHierBlks=6,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of block_design : entity is "block_design.hwdef";
end block_design;
architecture STRUCTURE of block_design is
component block_design_processing_system7_0_0 is
port (
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component block_design_processing_system7_0_0;
component block_design_axi_dispctrl_0_0 is
port (
REF_CLK_I : in STD_LOGIC;
PXL_CLK_O : out STD_LOGIC;
PXL_CLK_5X_O : out STD_LOGIC;
LOCKED_O : out STD_LOGIC;
FSYNC_O : out STD_LOGIC;
HSYNC_O : out STD_LOGIC;
VSYNC_O : out STD_LOGIC;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR ( 4 downto 0 );
GREEN_O : out STD_LOGIC_VECTOR ( 5 downto 0 );
BLUE_O : out STD_LOGIC_VECTOR ( 4 downto 0 );
DEBUG_O : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axis_mm2s_aclk : in STD_LOGIC;
s_axis_mm2s_aresetn : in STD_LOGIC;
s_axis_mm2s_tready : out STD_LOGIC;
s_axis_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_mm2s_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_mm2s_tlast : in STD_LOGIC;
s_axis_mm2s_tvalid : in STD_LOGIC
);
end component block_design_axi_dispctrl_0_0;
component block_design_axi_vdma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axis_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
mm2s_fsync : in STD_LOGIC;
mm2s_frame_ptr_in : in STD_LOGIC_VECTOR ( 5 downto 0 );
mm2s_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component block_design_axi_vdma_0_0;
component block_design_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component block_design_proc_sys_reset_0_0;
component block_design_proc_sys_reset_1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component block_design_proc_sys_reset_1_0;
component block_design_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component block_design_xlconstant_0_0;
signal S00_AXI_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_ARREADY : STD_LOGIC;
signal S00_AXI_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_ARVALID : STD_LOGIC;
signal S00_AXI_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_AWREADY : STD_LOGIC;
signal S00_AXI_1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_1_AWVALID : STD_LOGIC;
signal S00_AXI_1_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_BREADY : STD_LOGIC;
signal S00_AXI_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_BVALID : STD_LOGIC;
signal S00_AXI_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_RLAST : STD_LOGIC;
signal S00_AXI_1_RREADY : STD_LOGIC;
signal S00_AXI_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_1_RVALID : STD_LOGIC;
signal S00_AXI_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_1_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal S00_AXI_1_WLAST : STD_LOGIC;
signal S00_AXI_1_WREADY : STD_LOGIC;
signal S00_AXI_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_1_WVALID : STD_LOGIC;
signal S00_AXI_2_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S00_AXI_2_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_2_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S00_AXI_2_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal S00_AXI_2_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_2_ARREADY : STD_LOGIC;
signal S00_AXI_2_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S00_AXI_2_ARVALID : STD_LOGIC;
signal S00_AXI_2_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal S00_AXI_2_RLAST : STD_LOGIC;
signal S00_AXI_2_RREADY : STD_LOGIC;
signal S00_AXI_2_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S00_AXI_2_RVALID : STD_LOGIC;
signal axi_dispctrl_0_BLUE_O : STD_LOGIC_VECTOR ( 4 downto 0 );
signal axi_dispctrl_0_FSYNC_O : STD_LOGIC;
signal axi_dispctrl_0_GREEN_O : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_dispctrl_0_HSYNC_O : STD_LOGIC;
signal axi_dispctrl_0_PXL_CLK_O : STD_LOGIC;
signal axi_dispctrl_0_RED_O : STD_LOGIC_VECTOR ( 4 downto 0 );
signal axi_dispctrl_0_VSYNC_O : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_1_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_interconnect_1_M00_AXI_RLAST : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_M00_AXI_RVALID : STD_LOGIC;
signal axi_vdma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_vdma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_vdma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_vdma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_vdma_0_m_axis_mm2s_tkeep : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_vdma_0_mm2s_introut : STD_LOGIC;
signal proc_sys_reset_0_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_1_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_axi_dispctrl_0_DE_O_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dispctrl_0_LOCKED_O_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dispctrl_0_PXL_CLK_5X_O_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dispctrl_0_DEBUG_O_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axi_vdma_0_m_axis_mm2s_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_vdma_0_mm2s_frame_ptr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_proc_sys_reset_0_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
vga_b(4 downto 0) <= axi_dispctrl_0_BLUE_O(4 downto 0);
vga_g(5 downto 0) <= axi_dispctrl_0_GREEN_O(5 downto 0);
vga_hs <= axi_dispctrl_0_HSYNC_O;
vga_r(4 downto 0) <= axi_dispctrl_0_RED_O(4 downto 0);
vga_vs <= axi_dispctrl_0_VSYNC_O;
axi_dispctrl_0: component block_design_axi_dispctrl_0_0
port map (
BLUE_O(4 downto 0) => axi_dispctrl_0_BLUE_O(4 downto 0),
DEBUG_O(31 downto 0) => NLW_axi_dispctrl_0_DEBUG_O_UNCONNECTED(31 downto 0),
DE_O => NLW_axi_dispctrl_0_DE_O_UNCONNECTED,
FSYNC_O => axi_dispctrl_0_FSYNC_O,
GREEN_O(5 downto 0) => axi_dispctrl_0_GREEN_O(5 downto 0),
HSYNC_O => axi_dispctrl_0_HSYNC_O,
LOCKED_O => NLW_axi_dispctrl_0_LOCKED_O_UNCONNECTED,
PXL_CLK_5X_O => NLW_axi_dispctrl_0_PXL_CLK_5X_O_UNCONNECTED,
PXL_CLK_O => axi_dispctrl_0_PXL_CLK_O,
RED_O(4 downto 0) => axi_dispctrl_0_RED_O(4 downto 0),
REF_CLK_I => processing_system7_0_FCLK_CLK0,
VSYNC_O => axi_dispctrl_0_VSYNC_O,
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(5 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(5 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s_axi_awaddr(5 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(5 downto 0),
s_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID,
s_axis_mm2s_aclk => axi_dispctrl_0_PXL_CLK_O,
s_axis_mm2s_aresetn => proc_sys_reset_1_peripheral_aresetn(0),
s_axis_mm2s_tdata(31 downto 0) => axi_vdma_0_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_TLAST,
s_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_TREADY,
s_axis_mm2s_tstrb(3 downto 0) => axi_vdma_0_m_axis_mm2s_tkeep(3 downto 0),
s_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_TVALID
);
axi_interconnect_0: entity work.block_design_axi_interconnect_0_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => proc_sys_reset_0_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(5 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(5 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(5 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(5 downto 0),
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M01_AXI_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
M01_AXI_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_1_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_1_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => S00_AXI_1_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => S00_AXI_1_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => S00_AXI_1_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_1_ARQOS(3 downto 0),
S00_AXI_arready => S00_AXI_1_ARREADY,
S00_AXI_arsize(2 downto 0) => S00_AXI_1_ARSIZE(2 downto 0),
S00_AXI_arvalid => S00_AXI_1_ARVALID,
S00_AXI_awaddr(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_1_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_1_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => S00_AXI_1_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => S00_AXI_1_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => S00_AXI_1_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_1_AWQOS(3 downto 0),
S00_AXI_awready => S00_AXI_1_AWREADY,
S00_AXI_awsize(2 downto 0) => S00_AXI_1_AWSIZE(2 downto 0),
S00_AXI_awvalid => S00_AXI_1_AWVALID,
S00_AXI_bid(11 downto 0) => S00_AXI_1_BID(11 downto 0),
S00_AXI_bready => S00_AXI_1_BREADY,
S00_AXI_bresp(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
S00_AXI_bvalid => S00_AXI_1_BVALID,
S00_AXI_rdata(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => S00_AXI_1_RID(11 downto 0),
S00_AXI_rlast => S00_AXI_1_RLAST,
S00_AXI_rready => S00_AXI_1_RREADY,
S00_AXI_rresp(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
S00_AXI_rvalid => S00_AXI_1_RVALID,
S00_AXI_wdata(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => S00_AXI_1_WID(11 downto 0),
S00_AXI_wlast => S00_AXI_1_WLAST,
S00_AXI_wready => S00_AXI_1_WREADY,
S00_AXI_wstrb(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
S00_AXI_wvalid => S00_AXI_1_WVALID
);
axi_interconnect_1: entity work.block_design_axi_interconnect_1_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => proc_sys_reset_0_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_1_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_interconnect_1_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_interconnect_1_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arlen(3 downto 0) => axi_interconnect_1_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_interconnect_1_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_1_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_interconnect_1_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_interconnect_1_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_interconnect_1_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_interconnect_1_M00_AXI_ARVALID,
M00_AXI_rdata(63 downto 0) => axi_interconnect_1_M00_AXI_RDATA(63 downto 0),
M00_AXI_rlast => axi_interconnect_1_M00_AXI_RLAST,
M00_AXI_rready => axi_interconnect_1_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_1_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_1_M00_AXI_RVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => S00_AXI_2_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_2_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_2_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => S00_AXI_2_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => S00_AXI_2_ARPROT(2 downto 0),
S00_AXI_arready => S00_AXI_2_ARREADY,
S00_AXI_arsize(2 downto 0) => S00_AXI_2_ARSIZE(2 downto 0),
S00_AXI_arvalid => S00_AXI_2_ARVALID,
S00_AXI_rdata(63 downto 0) => S00_AXI_2_RDATA(63 downto 0),
S00_AXI_rlast => S00_AXI_2_RLAST,
S00_AXI_rready => S00_AXI_2_RREADY,
S00_AXI_rresp(1 downto 0) => S00_AXI_2_RRESP(1 downto 0),
S00_AXI_rvalid => S00_AXI_2_RVALID
);
axi_vdma_0: component block_design_axi_vdma_0_0
port map (
axi_resetn => proc_sys_reset_0_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => S00_AXI_2_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => S00_AXI_2_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => S00_AXI_2_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => S00_AXI_2_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => S00_AXI_2_ARPROT(2 downto 0),
m_axi_mm2s_arready => S00_AXI_2_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => S00_AXI_2_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => S00_AXI_2_ARVALID,
m_axi_mm2s_rdata(63 downto 0) => S00_AXI_2_RDATA(63 downto 0),
m_axi_mm2s_rlast => S00_AXI_2_RLAST,
m_axi_mm2s_rready => S00_AXI_2_RREADY,
m_axi_mm2s_rresp(1 downto 0) => S00_AXI_2_RRESP(1 downto 0),
m_axi_mm2s_rvalid => S00_AXI_2_RVALID,
m_axis_mm2s_aclk => axi_dispctrl_0_PXL_CLK_O,
m_axis_mm2s_tdata(31 downto 0) => axi_vdma_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_vdma_0_m_axis_mm2s_tkeep(3 downto 0),
m_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tuser(0) => NLW_axi_vdma_0_m_axis_mm2s_tuser_UNCONNECTED(0),
m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_TVALID,
mm2s_frame_ptr_in(5 downto 0) => xlconstant_0_dout(5 downto 0),
mm2s_frame_ptr_out(5 downto 0) => NLW_axi_vdma_0_mm2s_frame_ptr_out_UNCONNECTED(5 downto 0),
mm2s_fsync => axi_dispctrl_0_FSYNC_O,
mm2s_introut => axi_vdma_0_mm2s_introut,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
s_axi_lite_arready => axi_interconnect_0_M01_AXI_ARREADY,
s_axi_lite_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
s_axi_lite_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
s_axi_lite_awready => axi_interconnect_0_M01_AXI_AWREADY,
s_axi_lite_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
s_axi_lite_bready => axi_interconnect_0_M01_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => axi_interconnect_0_M01_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
s_axi_lite_rready => axi_interconnect_0_M01_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => axi_interconnect_0_M01_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
s_axi_lite_wready => axi_interconnect_0_M01_AXI_WREADY,
s_axi_lite_wvalid => axi_interconnect_0_M01_AXI_WVALID
);
proc_sys_reset_0: component block_design_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => proc_sys_reset_0_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_0_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
proc_sys_reset_1: component block_design_proc_sys_reset_1_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => NLW_proc_sys_reset_1_interconnect_aresetn_UNCONNECTED(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_1_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_1_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => axi_dispctrl_0_PXL_CLK_O
);
processing_system7_0: component block_design_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(0) => axi_vdma_0_mm2s_introut,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => S00_AXI_1_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => S00_AXI_1_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => S00_AXI_1_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => S00_AXI_1_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => S00_AXI_1_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => S00_AXI_1_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => S00_AXI_1_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => S00_AXI_1_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => S00_AXI_1_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => S00_AXI_1_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => S00_AXI_1_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => S00_AXI_1_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => S00_AXI_1_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => S00_AXI_1_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => S00_AXI_1_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => S00_AXI_1_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => S00_AXI_1_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => S00_AXI_1_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => S00_AXI_1_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => S00_AXI_1_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => S00_AXI_1_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => S00_AXI_1_AWVALID,
M_AXI_GP0_BID(11 downto 0) => S00_AXI_1_BID(11 downto 0),
M_AXI_GP0_BREADY => S00_AXI_1_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => S00_AXI_1_BRESP(1 downto 0),
M_AXI_GP0_BVALID => S00_AXI_1_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => S00_AXI_1_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => S00_AXI_1_RID(11 downto 0),
M_AXI_GP0_RLAST => S00_AXI_1_RLAST,
M_AXI_GP0_RREADY => S00_AXI_1_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => S00_AXI_1_RRESP(1 downto 0),
M_AXI_GP0_RVALID => S00_AXI_1_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => S00_AXI_1_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => S00_AXI_1_WID(11 downto 0),
M_AXI_GP0_WLAST => S00_AXI_1_WLAST,
M_AXI_GP0_WREADY => S00_AXI_1_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => S00_AXI_1_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => S00_AXI_1_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_interconnect_1_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_interconnect_1_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_interconnect_1_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => axi_interconnect_1_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_interconnect_1_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_interconnect_1_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_interconnect_1_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_interconnect_1_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_interconnect_1_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_interconnect_1_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_processing_system7_0_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_processing_system7_0_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => axi_interconnect_1_M00_AXI_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => axi_interconnect_1_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_interconnect_1_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_interconnect_1_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_interconnect_1_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_processing_system7_0_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
xlconstant_0: component block_design_xlconstant_0_0
port map (
dout(5 downto 0) => xlconstant_0_dout(5 downto 0)
);
end STRUCTURE;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/ip_repo/axi_dispctrl_1.0/hdl/axi_dispctrl_v1_0_S_AXI.vhd
|
7
|
23770
|
--------------------------------------------------------------------------------
--
-- File:
-- axi_dispctrl_v1_0_S_AXI.vhd
--
-- Module:
-- AXIS Display Controller AXI Slave Interface
--
-- Author:
-- Tinghui Wang (Steve)
--
-- Description:
-- AXI-Lite Register Interface for AXI Display Controller
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- Licence:
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity axi_dispctrl_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
CTRL_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
STAT_REG :in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
FRAME_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
HPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM1_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
VPARAM2_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_O_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FB_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FRAC_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_DIV_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_LOCK_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
CLK_FLTR_REG :out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end axi_dispctrl_v1_0_S_AXI;
architecture arch_imp of axi_dispctrl_v1_0_S_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 13
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
-- slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"0000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when b"0001" =>
-- for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
-- if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- -- Respective byte enables are asserted as per write strobes
-- -- slave registor 1
-- slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when b"0010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0110" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"0111" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 8
slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 9
slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 10
slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 11
slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"1100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 12
slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
-- slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '1');
else
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"0000" =>
reg_data_out <= slv_reg0;
when b"0001" =>
reg_data_out <= slv_reg1;
when b"0010" =>
reg_data_out <= slv_reg2;
when b"0011" =>
reg_data_out <= slv_reg3;
when b"0100" =>
reg_data_out <= slv_reg4;
when b"0101" =>
reg_data_out <= slv_reg5;
when b"0110" =>
reg_data_out <= slv_reg6;
when b"0111" =>
reg_data_out <= slv_reg7;
when b"1000" =>
reg_data_out <= slv_reg8;
when b"1001" =>
reg_data_out <= slv_reg9;
when b"1010" =>
reg_data_out <= slv_reg10;
when b"1011" =>
reg_data_out <= slv_reg11;
when b"1100" =>
reg_data_out <= slv_reg12;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
CTRL_REG <= slv_reg0;
FRAME_REG <= slv_reg2;
HPARAM1_REG <= slv_reg3;
HPARAM2_REG <= slv_reg4;
VPARAM1_REG <= slv_reg5;
VPARAM2_REG <= slv_reg6;
CLK_O_REG <= slv_reg7;
CLK_FB_REG <= slv_reg8;
CLK_FRAC_REG <= slv_reg9;
CLK_DIV_REG <= slv_reg10;
CLK_LOCK_REG <= slv_reg11;
CLK_FLTR_REG <= slv_reg12;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg1 <= (others => '0');
else
slv_reg1 <= STAT_REG;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_updt_queue.vhd
|
4
|
39132
|
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty,
m_axis_updt_tready,
updt_tvalid,
updt_tlast)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty = '0')then
write_curdesc_lsb <= '1';
dataq_rden <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(ptr_queue_empty = '0')then
dataq_rden <= '1';
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid = '1' and m_axis_updt_tready = '1'
and updt_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
-- Channel Pointer Queue (Generate Synchronous FIFO)
I_UPDT_DATA_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => UPD_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_WRITE_DEPTH => UPDATE_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_READ_DEPTH => UPDATE_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => ptr_queue_din ,
Wr_en => ptr_queue_wren ,
Rd_en => ptr_queue_rden ,
Dout => ptr_queue_dout ,
Full => ptr_queue_full ,
Empty => ptr_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- Channel Status Queue (Generate Synchronous FIFO)
I_UPDT_STS_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => STS_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_WRITE_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_READ_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0 ,
C_HAS_DCOUNT => 1 , --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_HAS_ALMOST_FULL => 0 ,
C_HAS_RD_ACK => 0 ,
C_HAS_RD_ERR => 0 ,
C_HAS_WR_ACK => 0 ,
C_HAS_WR_ERR => 0 ,
C_RD_ACK_LOW => 0 ,
C_RD_ERR_LOW => 0 ,
C_WR_ACK_LOW => 0 ,
C_WR_ERR_LOW => 0 ,
C_PRELOAD_REGS => 1 ,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => sts_queue_din ,
Wr_en => sts_queue_wren ,
Rd_en => sts_queue_rden ,
Dout => sts_queue_dout ,
Full => sts_queue_full ,
Empty => sts_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
end generate GEN_Q_FOR_SYNC;
GEN_Q_FOR_ASYNC : if C_AXIS_IS_ASYNC = 1 generate
begin
-- Generate Asynchronous FIFO
I_UPDT_DATA_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_DEPTH => UPDATE_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => UPD_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => ptr_queue_wren ,
AFIFO_Din => ptr_queue_din ,
AFIFO_Rd_clk => s_axis_updt_aclk ,
AFIFO_Rd_en => ptr_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => ptr_queue_dout ,
AFIFO_Full => ptr_queue_full ,
AFIFO_Empty => ptr_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-- Generate Asynchronous FIFO
I_UPDT_STS_FIFO : entity axi_vdma_v6_2_8.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 ,
C_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => STS_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => s_axis_updt_aclk ,
AFIFO_Wr_en => sts_queue_wren ,
AFIFO_Din => sts_queue_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => sts_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => sts_queue_dout ,
AFIFO_Full => sts_queue_full ,
AFIFO_Empty => sts_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate GEN_Q_FOR_ASYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt_queue_empty <= ptr_queue_empty
or sts_queue_empty;
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
updt_tvalid <= not sts_queue_empty
and writing_status;
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
updt_tlast <= not sts_queue_empty
and writing_status
and sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-----------------------------------------------------------------------
-- TDATA - drive data to datamover from status queue
-----------------------------------------------------------------------
m_axis_updt_tdata <= sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= updt_tvalid;
m_axis_updt_tlast <= updt_tlast;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_sg_ftch_mngr.vhd
|
4
|
27463
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_vdma_v6_2_8.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_vdma_v6_2_8.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_vdma_v6_2_8.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_vdma_v6_2/hdl/src/vhdl/axi_vdma_vidreg_module_64.vhd
|
4
|
33128
|
-------------------------------------------------------------------------------
-- axi_vdma_vidreg_module_64
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vidreg_module_64.vhd
--
-- Description: This entity is the top level for the dual register blocks,
-- i.e. video register set and sg register set and provides
-- indication of valid parameters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module_64.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module_64.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vidreg_module_64 is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
-----------------------------------------------------------------------
C_DYNAMIC_RESOLUTION : integer range 0 to 1 := 1 ;
-- Run time configuration of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 0 = Halt VDMA before writing new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE
-- 1 = Run time register configuration for new set of HSIZE, STRIDE, FRM_DLY, StartAddress & VSIZE.
-----------------------------------------------------------------------
C_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Start Address Width
C_SELECT_XPM : integer := 1;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
--
-- Register update control --
run_stop : in std_logic ; --
dmasr_halt : in std_logic ; --
ftch_idle : in std_logic ; --
tailpntr_updated : in std_logic ; --
frame_number : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
num_fstore_minus1 : in std_logic_vector --
(FRAME_NUMBER_WIDTH-1 downto 0) ; --
--
-- Register swap control/status --
frame_sync : in std_logic ; --
ftch_complete : in std_logic ; --
ftch_complete_clr : out std_logic ; --
parameter_update : out std_logic ; --
video_prmtrs_valid : out std_logic ; --
prmtr_update_complete : out std_logic ; -- CR605424
--
-- Register Direct Mode Video Parameter In --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_strt_addr : in STARTADDR_ARRAY_TYPE_64 --
(0 to C_NUM_FSTORES - 1) ; --
--
-- Descriptor data/control from sg interface --
desc_data_wren : in std_logic ; --
--
desc_strtaddress : in std_logic_vector --
(C_ADDR_WIDTH-1 downto 0) ; --
desc_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
desc_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
desc_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
desc_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
--
-- Scatter Gather register Bank --
crnt_vsize : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
crnt_hsize : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
crnt_stride : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
crnt_frmdly : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
crnt_start_address : out std_logic_vector --
(C_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_vidreg_module_64;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vidreg_module_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Control
signal video_parameter_updt : std_logic := '0';
signal video_prmtrs_valid_i : std_logic := '0';
signal ftch_complete_clr_i : std_logic := '0';
signal run_stop_re : std_logic := '0';
signal run_stop_d1 : std_logic := '0';
signal video_reg_updated : std_logic := '0';
signal video_reg_update : std_logic := '0';
signal update_complete : std_logic := '0';
-- Scatter Gather Side Video Register Bank
--signal vsize_sg : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal hsize_sg : std_logic_vector(HSIZE_DWIDTH-1 downto 0) := (others => '0');
--signal stride_sg : std_logic_vector(STRIDE_DWIDTH-1 downto 0) := (others => '0');
--signal frmdly_sg : std_logic_vector(FRMDLY_DWIDTH-1 downto 0) := (others => '0');
signal start_address_vid : STARTADDR_ARRAY_TYPE_64(0 to C_NUM_FSTORES - 1);
--signal start_address_sg : STARTADDR_ARRAY_TYPE(0 to C_NUM_FSTORES - 1);
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- If Scatter Gather engine is included then instantiate SG register block
GEN_SG_REGISTER : if C_INCLUDE_SG = 1 generate
begin
-- Flag for updating video parameters on descriptor fetch
-- Used to enable vsize, hsize, stride, frmdly update on first desc
-- fetchted
REG_UPDATE_VIDEO_PRMTRS : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_parameter_updt <= '0';
-- if new tailpointer and sg fetch engine idle or if new start then
-- set flag to capture video parameters
elsif((tailpntr_updated = '1' and ftch_idle = '1') or run_stop_re = '1')then
video_parameter_updt <= '1';
-- clear flag when parameters written to video_register module.
elsif(desc_data_wren = '1')then
video_parameter_updt <= '0';
end if;
end if;
end process REG_UPDATE_VIDEO_PRMTRS;
-- Register run stop to generate rising edge pulse
-- Used to force start address counter reset on shutdown
REG_RUN_STOP : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_STOP;
run_stop_re <= run_stop and not run_stop_d1;
-- Scatter Gather Start Address Register Block (LUTRAM)
SG_ADDREG_I : entity axi_vdma_v6_2_8.axi_vdma_sgregister
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH ,
C_SELECT_XPM => C_SELECT_XPM ,
C_FAMILY => C_FAMILY
)
port map (
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Update Control
video_reg_update => video_reg_update ,
video_parameter_updt => video_parameter_updt ,
video_parameter_valid => video_prmtrs_valid_i ,
dmasr_halt => dmasr_halt ,
strt_addr_clr => run_stop_re ,
desc_data_wren => desc_data_wren ,
frame_number => frame_number ,
ftch_complete => ftch_complete ,
ftch_complete_clr => ftch_complete_clr_i ,
update_complete => update_complete ,
num_fstore_minus1 => num_fstore_minus1 , -- CR607089
-- Video Start Address / Parameters In from Scatter Gather Engine
desc_vsize => desc_vsize ,
desc_hsize => desc_hsize ,
desc_stride => desc_stride ,
desc_frmdly => desc_frmdly ,
desc_strtaddress => desc_strtaddress ,
-- Video Start Address / Parameters Out to DMA Controller
crnt_vsize => crnt_vsize ,
crnt_hsize => crnt_hsize ,
crnt_stride => crnt_stride ,
crnt_frmdly => crnt_frmdly ,
crnt_start_address => crnt_start_address
);
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
--video_reg_update <= '1' when (frame_sync = '1' and ftch_complete = '1')
-- or (video_prmtrs_valid_i = '0' and ftch_complete = '1')
-- else '0';
video_reg_update <= '1' when (frame_sync = '1' and update_complete = '1')
or (video_prmtrs_valid_i = '0' and update_complete = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= update_complete;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
ftch_complete_clr_i <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
--elsif(frame_sync = '1' and ftch_complete = '1')then
elsif(frame_sync = '1' and update_complete = '1')then
video_prmtrs_valid_i <= '1';
ftch_complete_clr_i <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
ftch_complete_clr_i <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- When video register block update drive out parameter update flag
-- for generation of ****_prmtr_update output
parameter_update <= ftch_complete_clr_i;
-- Clear fetch flag in sg interface
ftch_complete_clr <= ftch_complete_clr_i;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
end generate GEN_SG_REGISTER;
-- If Scatter Gather engine is excluded then instantiate register direct block
GEN_REGISTER_DIRECT : if C_INCLUDE_SG = 0 generate
begin
GEN_REGDIRECT_DRES : if C_DYNAMIC_RESOLUTION = 1 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Register Direct Mode - Video Register Block
------- REGDIR_REGBLOCK_I : entity axi_vdma_v6_2_8.axi_vdma_vregister
------- generic map(
------- C_NUM_FSTORES => C_NUM_FSTORES ,
------- C_ADDR_WIDTH => C_ADDR_WIDTH
-------
------- )
------- port map(
------- prmry_aclk => prmry_aclk ,
------- prmry_resetn => prmry_resetn ,
-------
------- -- Video Register Update control
------- video_reg_update => ftch_complete ,
-------
------- dmasr_halt => dmasr_halt ,
-------
------- -- Scatter Gather register Bank
------- vsize_sg => reg_module_vsize ,
------- hsize_sg => reg_module_hsize ,
------- stride_sg => reg_module_stride ,
------- frmdly_sg => reg_module_frmdly ,
------- start_address_sg => reg_module_strt_addr ,
-------
------- -- Video Register Bank
------- vsize_vid => vsize_sg ,
------- hsize_vid => hsize_sg ,
------- stride_vid => stride_sg ,
------- frmdly_vid => frmdly_sg ,
------- start_address_vid => start_address_sg
------- );
-------
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- Generate logic to transfer sg bank to vid bank of registers
-- transfer on frame sync if sg engine fetch is complete
video_reg_update <= '1' when (frame_sync = '1' and video_reg_updated = '1')
or (video_prmtrs_valid_i = '0' and video_reg_updated = '1')
else '0';
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
-- Video Register Block
VIDREGISTER_I : entity axi_vdma_v6_2_8.axi_vdma_vregister_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Video Register Update control
video_reg_update => video_reg_update ,
dmasr_halt => dmasr_halt ,
-- Scatter Gather register Bank
-- vsize_sg => vsize_sg ,
-- hsize_sg => hsize_sg ,
-- stride_sg => stride_sg ,
-- frmdly_sg => frmdly_sg ,
-- start_address_sg => start_address_sg ,
vsize_sg => reg_module_vsize ,
hsize_sg => reg_module_hsize ,
stride_sg => reg_module_stride ,
frmdly_sg => reg_module_frmdly ,
start_address_sg => reg_module_strt_addr ,
-- Video Register Bank
vsize_vid => crnt_vsize ,
hsize_vid => crnt_hsize ,
stride_vid => crnt_stride ,
frmdly_vid => crnt_frmdly ,
start_address_vid => start_address_vid
);
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_DRES;
GEN_REGDIRECT_NO_DRES : if C_DYNAMIC_RESOLUTION = 0 generate
begin
ftch_complete_clr <= '0'; -- Not Used in Register Direct Mode
-- Flag when video parameters/start address have been updated.
-- Assert on sg engine fetch or register update is complete
REG_PRE_VIDREG_UPDT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- Clear flag on reset, or halt
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_reg_updated <= '0';
elsif(video_reg_updated = '1' and frame_sync = '1')then
video_reg_updated <= '0';
-- video parameter from register module updated to
-- pre-video register block
elsif(ftch_complete = '1')then -- in RegDirect mode ftch_complete = writing VSIZE register.
video_reg_updated <= '1';
end if;
end if;
end process REG_PRE_VIDREG_UPDT;
-- CR605424
-- Pass up to sts_mngr when update is finally complete
-- This is used for initial fsync generation for Free Run mode
prmtr_update_complete <= video_reg_updated;
-- Indicate valid parameters on fsync and video registers updated.
REG_VIDPRMTR_VALID : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
-- reset or channel halt will clear video parameters
if(prmry_resetn = '0' or dmasr_halt = '1')then
video_prmtrs_valid_i <= '0';
parameter_update <= '0';
-- Frame sync and video parameter have been updated,then flag video parameters
-- valid
-- CR583673 - Fixes wrong hsize and frmdly values being registered on first frame
--elsif(frame_sync = '1' and (ftch_complete = '1' or video_reg_updated = '1'))then
elsif(frame_sync = '1' and video_reg_updated = '1')then
video_prmtrs_valid_i <= '1';
parameter_update <= '1';
else
video_prmtrs_valid_i <= video_prmtrs_valid_i;
parameter_update <= '0';
end if;
end if;
end process REG_VIDPRMTR_VALID;
-- Drive out flag to sm and frame counter that valid video
-- parameters have been loaded.
video_prmtrs_valid <= video_prmtrs_valid_i;
crnt_vsize <= reg_module_vsize;
crnt_hsize <= reg_module_hsize;
crnt_stride <= reg_module_stride;
crnt_frmdly <= reg_module_frmdly;
-- Generate C_NUM_FSTORE start address registeres
GEN_START_ADDR_REG : for i in 0 to C_NUM_FSTORES-1 generate
begin
start_address_vid(i) <= reg_module_strt_addr(i);
end generate GEN_START_ADDR_REG;
-- Video Start Address MUX
VIDADDR_MUX_I : entity axi_vdma_v6_2_8.axi_vdma_vaddrreg_mux_64
generic map(
C_NUM_FSTORES => C_NUM_FSTORES ,
C_ADDR_WIDTH => C_ADDR_WIDTH
)
port map(
prmry_aclk => prmry_aclk ,
prmry_resetn => prmry_resetn ,
-- Current Frame Number
frame_number => frame_number ,
start_address_vid => start_address_vid ,
crnt_start_address => crnt_start_address
);
end generate GEN_REGDIRECT_NO_DRES;
end generate GEN_REGISTER_DIRECT;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_piano/ip_repo/axi_i2s_adi_1.0/hdl/i2s_controller.vhd
|
7
|
8371
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.fifo_synchronizer;
use axi_i2s_adi_v1_00_a.i2s_clkgen;
use axi_i2s_adi_v1_00_a.i2s_tx;
use axi_i2s_adi_v1_00_a.i2s_rx;
entity i2s_controller is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1
);
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
data_clk : in std_logic; -- Data clock should be less than clk / 4
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input
tx_enable : in Boolean; -- Enable TX
tx_ack : out std_logic; -- Request new Slot Data
tx_stb : in std_logic; -- Request new Slot Data
tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
rx_enable : in Boolean; -- Enable RX
rx_ack : in std_logic;
rx_stb : out std_logic; -- Valid Slot Data
rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
-- Runtime parameter
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255
);
end i2s_controller;
architecture Behavioral of i2s_controller is
constant NUM_TX : integer := C_HAS_TX * C_NUM_CH;
constant NUM_RX : integer := C_HAS_RX * C_NUM_CH;
signal enable : Boolean;
signal tick : std_logic;
signal tick_d1 : std_logic;
signal tick_d2 : std_logic;
signal BCLK_O_int : std_logic;
signal LRCLK_O_int : std_logic;
signal tx_bclk : std_logic;
signal tx_lrclk : std_logic;
signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0);
signal tx_tick : std_logic;
signal tx_channel_sync : std_logic;
signal tx_frame_sync : std_logic;
signal bclk_tick : std_logic;
signal rx_bclk : std_logic;
signal rx_lrclk : std_logic;
signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0);
signal rx_channel_sync : std_logic;
signal rx_frame_sync : std_logic;
signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0);
signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0);
signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0);
signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0);
begin
enable <= rx_enable or tx_enable;
-- Generate tick signal in the DATA_CLK_I domain
process (data_clk)
begin
if rising_edge(data_clk) then
if resetn = '0' then
tick <= '0';
else
tick <= not tick;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if resetn = '0' then
tick_d1 <= '0';
tick_d2 <= '0';
else
tick_d1 <= tick;
tick_d2 <= tick_d1;
end if;
end if;
end process;
tx_tick <= tick_d2 xor tick_d1;
tx_sync_fifo_in(0) <= tx_channel_sync;
tx_sync_fifo_in(1) <= tx_frame_sync;
tx_sync_fifo_in(2) <= tx_bclk;
tx_sync_fifo_in(3) <= tx_lrclk;
tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata;
process (data_clk)
begin
if rising_edge(data_clk) then
if resetn = '0' then
BCLK_O <= (others => '1');
LRCLK_O <= (others => '1');
SDATA_O <= (others => '0');
else
if C_BCLK_POL = 0 then
BCLK_O <= (others => tx_sync_fifo_out(2));
else
BCLK_O <= (others => not tx_sync_fifo_out(2));
end if;
if C_LRCLK_POL = 0 then
LRCLK_O <= (others => tx_sync_fifo_out(3));
else
LRCLK_O <= (others => not tx_sync_fifo_out(3));
end if;
if C_HAS_TX = 1 then
SDATA_O <= tx_sync_fifo_out(3 + NUM_TX downto 4);
end if;
if C_HAS_RX = 1 then
rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0);
rx_sync_fifo_in(3 + NUM_RX downto 4) <= SDATA_I;
end if;
end if;
end if;
end process;
tx_sync: entity fifo_synchronizer
generic map (
DEPTH => 4,
WIDTH => NUM_TX + 4
)
port map (
resetn => resetn,
in_clk => clk,
in_data => tx_sync_fifo_in,
in_tick => tx_tick,
out_clk => data_clk,
out_data => tx_sync_fifo_out
);
clkgen: entity i2s_clkgen
port map(
clk => clk,
resetn => resetn,
enable => enable,
tick => tx_tick,
bclk_div_rate => bclk_div_rate,
lrclk_div_rate => lrclk_div_rate,
channel_sync => tx_channel_sync,
frame_sync => tx_frame_sync,
bclk => tx_bclk,
lrclk => tx_lrclk
);
tx_gen: if C_HAS_TX = 1 generate
tx: entity i2s_tx
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_NUM => NUM_TX
)
port map (
clk => clk,
resetn => resetn,
enable => tx_enable,
channel_sync => tx_channel_sync,
frame_sync => tx_frame_sync,
bclk => tx_bclk,
sdata => tx_sdata,
ack => tx_ack,
stb => tx_stb,
data => tx_data
);
end generate;
rx_gen: if C_HAS_RX = 1 generate
rx: entity i2s_rx
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_NUM => NUM_RX
)
port map (
clk => clk,
resetn => resetn,
enable => rx_enable,
channel_sync => rx_channel_sync,
frame_sync => rx_frame_sync,
bclk => rx_bclk,
sdata => rx_sdata,
ack => rx_ack,
stb => rx_stb,
data => rx_data
);
rx_channel_sync <= rx_sync_fifo_out(0);
rx_frame_sync <= rx_sync_fifo_out(1);
rx_bclk <= rx_sync_fifo_out(2);
rx_lrclk <= rx_sync_fifo_out(3);
rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4);
rx_sync: entity fifo_synchronizer
generic map (
DEPTH => 4,
WIDTH => NUM_RX + 4
)
port map (
resetn => resetn,
in_clk => data_clk,
in_data => rx_sync_fifo_in,
in_tick => '1',
out_clk => clk,
out_data => rx_sync_fifo_out
);
end generate;
end Behavioral;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ip/block_design_axi_vdma_0_0/synth/block_design_axi_vdma_0_0.vhd
|
2
|
23873
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2_8;
USE axi_vdma_v6_2_8.axi_vdma;
ENTITY block_design_axi_vdma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC
);
END block_design_axi_vdma_0_0;
ARCHITECTURE block_design_axi_vdma_0_0_arch OF block_design_axi_vdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_SELECT_XPM : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "axi_vdma,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF block_design_axi_vdma_0_0_arch : ARCHITECTURE IS "block_design_axi_vdma_0_0,axi_vdma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF block_design_axi_vdma_0_0_arch: ARCHITECTURE IS "block_design_axi_vdma_0_0,axi_vdma,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_vdma,x_ipVersion=6.2,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=9,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=1,C_ENABLE_VIDPRMTR_READS=1,C_DYNAMIC_RESOLUTION=1,C_NUM_FSTORES=3,C_USE_FSYNC=1,C_USE_MM2S_FSYNC=1,C_USE_S2MM_FSYNC=2,C_FLUSH_ON_FSYNC=1,C_INCLUDE_INTERNAL_GENLOCK=1,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_" &
"M_AXI_SG_DATA_WIDTH=32,C_INCLUDE_MM2S=1,C_MM2S_GENLOCK_MODE=1,C_MM2S_GENLOCK_NUM_MASTERS=1,C_MM2S_GENLOCK_REPEAT_EN=0,C_MM2S_SOF_ENABLE=1,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_MM2S_SF=0,C_MM2S_LINEBUFFER_DEPTH=2048,C_MM2S_LINEBUFFER_THRESH=4,C_MM2S_MAX_BURST_LENGTH=8,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=64,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_M_AXIS_MM2S_TUSER_BITS=1,C_INCLUDE_S2MM=0,C_S2MM_GENLOCK_MODE=0,C_S2MM_GENLOCK_NUM_MASTERS=1,C_S2MM_GENLOCK_REPEAT_EN=1,C_S2MM_SOF_ENABLE=1,C_INCLUDE_S2MM" &
"_DRE=0,C_INCLUDE_S2MM_SF=1,C_S2MM_LINEBUFFER_DEPTH=512,C_S2MM_LINEBUFFER_THRESH=4,C_S2MM_MAX_BURST_LENGTH=8,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=64,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_S_AXIS_S2MM_TUSER_BITS=1,C_ENABLE_DEBUG_ALL=0,C_ENABLE_DEBUG_INFO_0=0,C_ENABLE_DEBUG_INFO_1=0,C_ENABLE_DEBUG_INFO_2=0,C_ENABLE_DEBUG_INFO_3=0,C_ENABLE_DEBUG_INFO_4=0,C_ENABLE_DEBUG_INFO_5=0,C_ENABLE_DEBUG_INFO_6=1,C_ENABLE_DEBUG_INFO_7=1,C_ENABLE_DEBUG_INFO_8=0,C_ENABLE_DEBUG_INFO_9=0,C_ENABLE_DEBUG_INFO_1" &
"0=0,C_ENABLE_DEBUG_INFO_11=0,C_ENABLE_DEBUG_INFO_12=0,C_ENABLE_DEBUG_INFO_13=0,C_ENABLE_DEBUG_INFO_14=1,C_ENABLE_DEBUG_INFO_15=1,C_INSTANCE=axi_vdma,C_SELECT_XPM=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_fsync: SIGNAL IS "xilinx.com:signal:video_frame_sync:1.0 MM2S_FSYNC FRAME_SYNC";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_in: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_IN_0 FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 1,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 1,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 2048,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 1,
C_ENABLE_DEBUG_INFO_7 => 1,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 1,
C_ENABLE_DEBUG_INFO_15 => 1,
C_INSTANCE => "axi_vdma",
C_SELECT_XPM => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => '0',
s_axis_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => mm2s_fsync,
mm2s_frame_ptr_in => mm2s_frame_ptr_in,
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
mm2s_introut => mm2s_introut
);
END block_design_axi_vdma_0_0_arch;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/ipstatic/lib_bmg_v1_0/hdl/src/vhdl/blk_mem_gen_wrapper.vhd
|
4
|
30883
|
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library blk_mem_gen_v8_3_3;
use blk_mem_gen_v8_3_3.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex7";
c_xdevicefamily : string := "virtex7";
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
-- directly passing C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
signal RSTA_BUSY : STD_LOGIC;
signal RSTB_BUSY : STD_LOGIC;
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until clka = '1';
-- wait until clka = '0';
-- Wait until clka = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
-- douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
-- doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr <= '0' ; -- : out std_logic;
-- sbiterr <= '0' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_3_3.blk_mem_gen_v8_3_3
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- New features in 2015.1
C_EN_DEEPSLEEP_PIN => 0 ,
C_EN_SHUTDOWN_PIN => 0 ,
C_EN_SAFETY_CKT => 0 ,
C_USE_URAM => 0 ,
C_EN_RDADDRA_CHG => 0 ,
C_EN_RDADDRB_CHG => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
SHUTDOWN => '0' ,
DEEPSLEEP => '0' ,
RSTA_BUSY => RSTA_BUSY ,
RSTB_BUSY => RSTB_BUSY ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ipshared/xilinx.com/lib_bmg_v1_0/hdl/src/vhdl/blk_mem_gen_wrapper.vhd
|
4
|
30883
|
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library blk_mem_gen_v8_3_3;
use blk_mem_gen_v8_3_3.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex7";
c_xdevicefamily : string := "virtex7";
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
-- directly passing C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
signal RSTA_BUSY : STD_LOGIC;
signal RSTB_BUSY : STD_LOGIC;
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until clka = '1';
-- wait until clka = '0';
-- Wait until clka = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
-- douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
-- doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr <= '0' ; -- : out std_logic;
-- sbiterr <= '0' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_3_3.blk_mem_gen_v8_3_3
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- New features in 2015.1
C_EN_DEEPSLEEP_PIN => 0 ,
C_EN_SHUTDOWN_PIN => 0 ,
C_EN_SAFETY_CKT => 0 ,
C_USE_URAM => 0 ,
C_EN_RDADDRA_CHG => 0 ,
C_EN_RDADDRB_CHG => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
SHUTDOWN => '0' ,
DEEPSLEEP => '0' ,
RSTA_BUSY => RSTA_BUSY ,
RSTB_BUSY => RSTB_BUSY ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_gpio_sysfs/zybo_petalinux_1.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_gpio_v2_0/hdl/src/vhdl/axi_gpio.vhd
|
4
|
33322
|
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_11 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_11 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_4;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_11 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_11;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_11.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
|
gpl-3.0
|
andrewandrepowell/zybo_petalinux
|
zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ip/block_design_proc_sys_reset_0_0/synth/block_design_proc_sys_reset_0_0.vhd
|
3
|
6658
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY block_design_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END block_design_proc_sys_reset_0_0;
ARCHITECTURE block_design_proc_sys_reset_0_0_arch OF block_design_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF block_design_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF block_design_proc_sys_reset_0_0_arch : ARCHITECTURE IS "block_design_proc_sys_reset_0_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF block_design_proc_sys_reset_0_0_arch: ARCHITECTURE IS "block_design_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END block_design_proc_sys_reset_0_0_arch;
|
gpl-3.0
|
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