repo_name
stringlengths 6
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stringlengths 5
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stringclasses 54
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stringlengths 1
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stringlengths 0
1.04M
⌀ | license
stringclasses 15
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|---|---|---|---|---|---|
KANGKANGABC/ArmRobot
|
MotorCtl.vhd
|
1
|
17432
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: ZhaoKang
--
-- Create Date: 2017/05/31 21:54:01
-- Design Name:
-- Module Name: MotorCtl - beh
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functns with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MotorCtl is
Port (
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
UART_TX : out STD_LOGIC;
M1_degree : in STD_LOGIC_VECTOR (15 downto 0);
M2_degree : in STD_LOGIC_VECTOR (15 downto 0);
M3_degree : in STD_LOGIC_VECTOR (15 downto 0);
M4_degree : in STD_LOGIC_VECTOR (15 downto 0);
M5_degree : in STD_LOGIC_VECTOR (15 downto 0);
M6_degree : in STD_LOGIC_VECTOR (15 downto 0)
--TMP : buffer STD_LOGIC_VECTOR (15 downto 0)
);
end entity;
architecture beh of MotorCtl is
component crc is
port (
clk: in std_logic;
data_in: in std_logic_vector(7 downto 0);
crc_in: in std_logic_vector(15 downto 0);
crc_out: out std_logic_vector(15 downto 0)
);
end component;
component UART_TX_CTRL is
port (
SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC
);
end component;
--component InstructionRam is
--PORT (
-- clka : IN STD_LOGIC;
-- wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
-- dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-- clkb : IN STD_LOGIC;
-- web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-- addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
-- dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-- );
--end component;
SIGNAL clk_1 : std_logic;
SIGNAL crc_ret : std_logic_vector (15 downto 0);
SIGNAL crc_int : std_logic_vector (15 downto 0);
SIGNAL crc_data : std_logic_vector (7 downto 0);
--SIGNAL wea : std_logic_vector (0 downto 0);
--SIGNAL addra : std_logic_vector (6 downto 0);
--SIGNAL addrb : std_logic_vector (6 downto 0);
--SIGNAL dina : std_logic_vector (7 downto 0);
--SIGNAL douta : std_logic_vector (7 downto 0);
--SIGNAL dinb : std_logic_vector (7 downto 0);
--SIGNAL doutb : std_logic_vector (7 downto 0);
TYPE matrix_index is array (13 downto 0) of std_logic_vector(7 downto 0);
TYPE StateType is (S000,S00, S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14,
S15, S16, S17, S18, S19, S20, S21, S22, S23);
SIGNAL m1, m2, m3, m4, m5, m6 : matrix_index;
SIGNAL m1a, m2a, m3a, m4a, m5a, m6a : matrix_index;
signal UartBusy : std_logic;
signal UartCtl : std_logic;
signal UartData : std_logic_vector(7 DOWNTO 0);
begin
crc_ins : crc
port map(
clk => clk_1,
data_in => crc_data,
crc_in => crc_int,
crc_out => crc_ret
);
UART_TX_CTRL_ins : UART_TX_CTRL
port map(
READY => UartBusy,
UART_TX => UART_TX,
CLK => clk_1,
DATA => UartData,
SEND => UartCtl
);
-- InstructionRam_ins : InstructionRam
-- port map(
-- clka => clk_1,
-- clkb => clk_1,
-- wea => wea,
-- web => wea,
-- addra => addra,
-- addrb => addrb,
-- dina => dina,
-- douta => douta,
-- dinb => dinb,
-- doutb => doutb
-- );
process(CLK)
variable state : StateType := S000;
variable count1 : integer range 0 to 13;
variable TMP : std_logic_vector (15 downto 0);
begin
-- m1(12) <= x"FF";m2(12) <= x"FF";m3(12) <= x"FF";m4(12) <= x"FF";m5(12) <= x"FF";m6(12) <= x"FF";
-- m1(13) <= x"FF";m2(13) <= x"FF";m3(13) <= x"FF";m4(13) <= x"FF";m5(13) <= x"FF";m6(13) <= x"FF";
clk_1 <= CLK;
if RESET = '0' then
count1 := 0;
state := S000;
elsif falling_edge(CLK) then
case state is
when S000 =>
m1(0) <= x"FF";m2(0) <= x"FF";m3(0) <= x"FF";m4(0) <= x"FF";m5(0) <= x"FF";m6(0) <= x"FF";
m1(1) <= x"FF";m2(1) <= x"FF";m3(1) <= x"FF";m4(1) <= x"FF";m5(1) <= x"FF";m6(1) <= x"FF";
m1(2) <= x"FD";m2(2) <= x"FD";m3(2) <= x"FD";m4(2) <= x"FD";m5(2) <= x"FD";m6(2) <= x"FD";
m1(3) <= x"00";m2(3) <= x"00";m3(3) <= x"00";m4(3) <= x"00";m5(3) <= x"00";m6(3) <= x"00";
m1(4) <= x"01";m2(4) <= x"02";m3(4) <= x"03";m4(4) <= x"04";m5(4) <= x"05";m6(4) <= x"06";
m1(5) <= x"07";m2(5) <= x"07";m3(5) <= x"07";m4(5) <= x"07";m5(5) <= x"07";m6(5) <= x"07";
m1(6) <= x"00";m2(6) <= x"00";m3(6) <= x"00";m4(6) <= x"00";m5(6) <= x"00";m6(6) <= x"00";
m1(7) <= x"03";m2(7) <= x"03";m3(7) <= x"03";m4(7) <= x"03";m5(7) <= x"03";m6(7) <= x"03";
m1(8) <= x"1E";m2(8) <= x"1E";m3(8) <= x"1E";m4(8) <= x"1E";m5(8) <= x"1E";m6(8) <= x"1E";
m1(9) <= x"00";m2(9) <= x"00";m3(9) <= x"00";m4(9) <= x"00";m5(9) <= x"00";m6(9) <= x"00";
m1(10) <= M1_degree(7 DOWNTO 0);m2(10) <= M2_degree(7 DOWNTO 0);m3(10) <= M3_degree(7 DOWNTO 0);
m4(10) <= M4_degree(7 DOWNTO 0);m5(10) <= M5_degree(7 DOWNTO 0);m6(10) <= M6_degree(7 DOWNTO 0);
m1(11) <= M1_degree(15 DOWNTO 8);m2(11) <= M2_degree(15 DOWNTO 8);m3(11) <= M3_degree(15 DOWNTO 8);
m4(11) <= M4_degree(15 DOWNTO 8);m5(11) <= M5_degree(15 DOWNTO 8);m6(11) <= M6_degree(15 DOWNTO 8);
state := S00;
when S00 =>
crc_int <= x"0000";
crc_data <= m1(count1);
state := S0;
when S0 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m1(count1);
state := S1;
when S1 =>
if count1 < 11 then
state := S0;
else
state := S2;
count1 := 0;
TMP := crc_ret;
end if;
when S2 =>
m1(12) <= crc_ret(7 downto 0);
m1(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m2(count1);
state := S3;
when S3 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m2(count1);
state := S4;
when S4 =>
if count1 < 11 then
state := S3;
else
state := S5;
count1 := 0;
TMP := crc_ret;
end if;
when S5 =>
m2(12) <= crc_ret(7 downto 0);
m2(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m3(count1);
state := S6;
when S6 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m3(count1);
state := S7;
when S7 =>
if count1 < 11 then
state := S6;
else
state := S8;
count1 := 0;
TMP := crc_ret;
end if;
when S8 =>
m3(12) <= crc_ret(7 downto 0);
m3(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m4(count1);
state := S9;
when S9 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m4(count1);
state := S10;
when S10 =>
if count1 < 11 then
state := S9;
else
state := S11;
count1 := 0;
TMP := crc_ret;
end if;
when S11 =>
m4(12) <= crc_ret(7 downto 0);
m4(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m5(count1);
state := S12;
when S12 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m5(count1);
state := S13;
when S13 =>
if count1 < 11 then
state := S12;
else
state := S14;
count1 := 0;
TMP := crc_ret;
end if;
when S14 =>
m5(12) <= crc_ret(7 downto 0);
m5(13) <= crc_ret(15 downto 8);
crc_int <= x"0000";
crc_data <= m6(count1);
state := S15;
when S15 =>
crc_int <= crc_ret;
count1 := count1 + 1;
crc_data<= m6(count1);
state := S16;
when S16 =>
if count1 < 11 then
state := S15;
else
state := S17;
count1 := 0;
TMP := crc_ret;
end if;
when S17 =>
m6(12) <= crc_ret(7 downto 0);
m6(13) <= crc_ret(15 downto 8);
m1a <= m1;
m2a <= m2;
m3a <= m3;
m4a <= m4;
m5a <= m5;
m6a <= m6;
state := S000;
when others =>
state := S000;
end case;
end if;
end process;
process(CLK)
variable state1 : StateType := S000;
variable count2 : integer range 0 to 14;
begin
if RESET = '0' then
state1 := S000;
count2 := 0;
elsif falling_edge(CLK) then
case state1 is
when S000 =>
UartCtl <= '0';
UartData <= x"00";
state1 := S00;
count2 := 0;
---------------------------motor1--------------------------------
when S00 =>
UartData <= m1a(count2);
state1 := S0;
when S0 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S1;
when S1 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S2;
end if;
when S2 =>
if count2 < 14 then
state1 := S00;
else
state1 := S3;
count2 := 0;
end if;
---------------------------motor2--------------------------------
when S3 =>
UartData <= m2a(count2);
state1 := S4;
when S4 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S5;
when S5 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S6;
end if;
when S6 =>
if count2 < 14 then
state1 := S3;
else
state1 := S7;
count2 := 0;
end if;
---------------------------motor3--------------------------------
when S7 =>
UartData <= m3a(count2);
state1 := S8;
when S8 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S9;
when S9 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S10;
end if;
when S10 =>
if count2 < 14 then
state1 := S7;
else
state1 := S11;
count2 := 0;
end if;
---------------------------motor4--------------------------------
when S11 =>
UartData <= m4a(count2);
state1 := S12;
when S12 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S13;
when S13 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S14;
end if;
when S14 =>
if count2 < 14 then
state1 := S11;
else
state1 := S15;
count2 := 0;
end if;
---------------------------motor5--------------------------------
when S15 =>
UartData <= m5a(count2);
state1 := S16;
when S16 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S17;
when S17 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S18;
end if;
when S18 =>
if count2 < 14 then
state1 := S15;
else
state1 := S19;
count2 := 0;
end if;
---------------------------motor6--------------------------------
when S19 =>
UartData <= m6a(count2);
state1 := S20;
when S20 =>
UartCtl <= '1';
count2 := count2 + 1;
state1 := S21;
when S21 =>
if UartBusy = '1' then
UartCtl <= '0';
state1 := S22;
end if;
when S22 =>
if count2 < 14 then
state1 := S19;
else
state1 := S23;
count2 := 0;
end if;
when S23 =>
state1 := S000;
when others =>
state1 := S000;
end case;
end if;
end process;
end architecture;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/14-MESA-IA/asap-alap-random/mesaia_asap.vhd
|
1
|
8428
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:53:38)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 3);
output1, output2, output3, output4: OUT unsigned(0 TO 4));
END mesaia_asap_entity;
ARCHITECTURE mesaia_asap_description OF mesaia_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register12: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register13: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register14: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register15: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register16: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register17: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register18: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register19: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register20: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register21: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register22: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register23: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register24: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register25: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register26: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register27: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register28: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register29: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register30: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register31: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register32: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register33: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register34: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register35: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register36: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register37: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register38: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register39: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register40: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register41: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register42: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register43: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register44: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register45: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register46: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register47: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register48: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 + 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 * 9;
register10 := input10 * 10;
register11 := input11 + 11;
register12 := input12 * 12;
register13 := input13 * 13;
register14 := input14 * 14;
register15 := input15 + 15;
register16 := input16 * 16;
register17 := input17 * 17;
register18 := input18 + 18;
register19 := input19 * 19;
register20 := input20 * 20;
register21 := input21 * 21;
register22 := input22 * 22;
register23 := input23 + 23;
register24 := input24 * 24;
register25 := input25 * 25;
register26 := input26 * 26;
register27 := input27 * 27;
register28 := input28 * 28;
register29 := input29 + 29;
register30 := input30 * 30;
register31 := input31 * 31;
register32 := input32 + 32;
register33 := input33 * 33;
register34 := input34 * 34;
register35 := input35 * 35;
register36 := input36 + 36;
register37 := input37 * 37;
register38 := input38 * 38;
register39 := input39 + 39;
register40 := input40 * 40;
register41 := input41 * 41;
register42 := input42 * 42;
register43 := input43 + 43;
register44 := input44 * 44;
register45 := input45 + 45;
register46 := input46 + 46;
register47 := input47 * 47;
register48 := input48 + 48;
WHEN "00000010" =>
register1 := register24 + register1;
register2 := register2 + register32;
register3 := register3 + register39;
register5 := register38 + register5;
register6 := register10 + register6;
register7 := register40 + register7;
register9 := register9 + register48;
register10 := register22 + register11;
register11 := register12 + register45;
register12 := register14 + register36;
register14 := register27 + register15;
register15 := register17 + register43;
register17 := register28 + register18;
register18 := register19 + register23;
register19 := register34 + register29;
register22 := register44 + register46;
WHEN "00000011" =>
register1 := register25 + register1;
register2 := register33 + register2;
register3 := register4 + register3;
register4 := register37 + register5;
register5 := register30 + register6;
register6 := register41 + register7;
register7 := register8 + register9;
register8 := register21 + register10;
register9 := register31 + register11;
register10 := register13 + register12;
register11 := register26 + register14;
register12 := register16 + register15;
register13 := register42 + register17;
register14 := register20 + register18;
register15 := register35 + register19;
register16 := register47 + register22;
WHEN "00000100" =>
register1 := ((NOT register1) + 1) XOR register1;
register3 := ((NOT register3) + 1) XOR register3;
register4 := ((NOT register4) + 1) XOR register4;
register6 := ((NOT register6) + 1) XOR register6;
register7 := ((NOT register7) + 1) XOR register7;
register8 := ((NOT register8) + 1) XOR register8;
register11 := ((NOT register11) + 1) XOR register11;
register12 := ((NOT register12) + 1) XOR register12;
register13 := ((NOT register13) + 1) XOR register13;
register14 := ((NOT register14) + 1) XOR register14;
register15 := ((NOT register15) + 1) XOR register15;
register16 := ((NOT register16) + 1) XOR register16;
WHEN "00000101" =>
register1 := register6 - register1;
register4 := register16 - register4;
register6 := register7 - register12;
register7 := register13 - register14;
WHEN "00000110" =>
register1 := register1 * 74;
register4 := register4 * 76;
register6 := register6 * 78;
register7 := register7 * 80;
WHEN "00000111" =>
register1 := register15 + register1;
register3 := register3 + register4;
register4 := register11 + register6;
register6 := register8 + register7;
WHEN "00001000" =>
output1 <= register1(0 TO 1) & register9(0 TO 2);
output2 <= register3(0 TO 1) & register5(0 TO 2);
output3 <= register4(0 TO 1) & register2(0 TO 2);
output4 <= register6(0 TO 1) & register10(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_asap_description;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/1-HAL/asap-alap-random/hal_asap.vhd
|
1
|
1668
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.08:57:10)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_asap_entity;
ARCHITECTURE hal_asap_description OF hal_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
WHEN "00000010" =>
IF (register1 < 6) THEN
output1 <= register1;
ELSE
output1 <= "00110";
END IF;
register1 := register2 * register3;
register2 := register4 * 8;
output2 <= register5 + 9;
WHEN "00000011" =>
register1 := register1 - 11;
WHEN "00000100" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_asap_description;
|
gpl-3.0
|
jouyang3/FMCW
|
DSP/Radar_DSP/FPGA/Individual Modules/Working_FFT/Working_FFT/FFT_Mag/simulation/modelsim/work/dft_testbench/_primary.vhd
|
2
|
86
|
library verilog;
use verilog.vl_types.all;
entity dft_testbench is
end dft_testbench;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/3-ARF/metaheurísticas/arf_hype.vhd
|
1
|
2433
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:34:57)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 3);
output1, output2: OUT unsigned(0 TO 4));
END arf_hype_entity;
ARCHITECTURE arf_hype_description OF arf_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register1 + register2;
register2 := input3 * 3;
register3 := input4 * 4;
WHEN "00000011" =>
register4 := input5 * 5;
register1 := register1 + 7;
register5 := input6 * 8;
register2 := register3 + register2;
WHEN "00000100" =>
register3 := input7 * 9;
register6 := input8 * 10;
register4 := register5 + register4;
WHEN "00000101" =>
register5 := register1 * 12;
register1 := register1 * 14;
register3 := register3 + register6;
register4 := register4 + 16;
WHEN "00000110" =>
register6 := register4 * 18;
register4 := register4 * 20;
WHEN "00000111" =>
register1 := register1 + register4;
register4 := register5 + register6;
WHEN "00001000" =>
register5 := register4 * 22;
register6 := register1 * 24;
WHEN "00001001" =>
register1 := register1 * 26;
register4 := register4 * 28;
register5 := register5 + register6;
WHEN "00001010" =>
register1 := register4 + register1;
output1 <= register3 + register5;
WHEN "00001011" =>
output2 <= register2 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_hype_description;
|
gpl-3.0
|
rcls/sdr
|
vhdl/downconvert.vhd
|
1
|
16150
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
-- This does one half of the downconverter, either real or imaginary.
entity dc1 is
generic(minus_sin : boolean; gen_product : boolean := false);
port (data : in signed14;
gain : in unsigned(3 downto 0);
product : out signed36;
q : out mf_signed;
phase : in unsigned(13 downto 0);
clk : in std_logic;
index : out unsigned(9 downto 0);
packed : in unsigned18);
end dc1;
architecture dc1 of dc1 is
constant width1 : integer := 48;
constant width2 : integer := minimum(mf_width + 10, width1);
--signal index : unsigned(9 downto 0);
signal low, low_2 : unsigned(1 downto 0);
signal minus : std_logic_vector(1 to 5);
signal main, offset : unsigned18;
signal data_3 : signed14;
signal main_4, main_5, offset_4, offset_5, trig : signed18;
signal data_4, data_5, data_6 : signed18;
signal prod : signed36;
signal buf : signed(width1 - 1 downto 0);
signal buf_9, acc : signed(width2 - 1 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of acc : signal is "no";
begin
process
begin
wait until rising_edge(clk);
-- Unpack the accumulator to the indexes and signs.
-- Maybe we should have separate tables for
-- sines and cosines...
if minus_sin then
if phase(12) = '1' then
index <= not phase(11 downto 2);
low <= not phase(1 downto 0);
else
index <= phase(11 downto 2);
low <= phase(1 downto 0);
end if;
-- We are down-converting not up converting, so we want to use -sin.
minus(1) <= not phase(13);
else
if phase(12) = '1' then
index <= phase(11 downto 2);
low <= phase(1 downto 0);
else
index <= not phase(11 downto 2);
low <= not phase(1 downto 0);
end if;
minus(1) <= phase(13) xor phase(12);
end if;
minus(2 to 5) <= minus(1 to 4);
-- Lookup the sin and cos tables. - done a level up.
--packed <= sintable(to_integer(index));
low_2 <= low;
-- Prepare the sin and cos.
main <= packed and "00" & x"3fff";
offset <= resize(sinoffset(packed, low_2), 18);
data_3 <= data;
-- Apply gain(1,0) to sin & cos, & gain(2) to data.
if gain(2) = '0' then
data_4 <= resize(data_3, 18);
else
data_4 <= data_3 & "0000";
end if;
main_4 <= signed(main) sll to_integer(gain(1 downto 0));
if minus(4) = '1' then
offset_4 <= -signed(offset) sll to_integer(gain(1 downto 0));
else
offset_4 <= signed(offset) sll to_integer(gain(1 downto 0));
end if;
-- Buffer.
main_5 <= main_4;
offset_5 <= offset_4;
data_5 <= data_4;
-- Pre-add.
if minus(5) = '1' then
trig <= offset_5 - main_5;
else
trig <= offset_5 + main_5;
end if;
data_6 <= data_5;
-- Multiply
prod <= data_6 * trig;
-- Post add (8).
buf <= buf + prod;
if gen_product then
product <= prod;
end if;
-- Buffer.
buf_9 <= buf(width1 - 1 downto width1 - width2);
-- Second order accumulate, applying gain(3).
if gain(3) = '0' then
acc <= acc + buf_9;
else
acc <= acc + (buf_9 sll 8);
end if;
q <= acc(width2 - 1 downto width2 - mf_width);
end process;
end dc1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
entity downconvert is
port (data : in signed14;
gain : in unsigned8;
xx, yy : out mf_signed;
freq : in unsigned24;
clk : in std_logic);
end downconvert;
architecture downconvert of downconvert is
-- For the cosine/sine lookup, we take a 14 bit quantity. The first two bits
-- determine the quadrant, the middle ten the table index, and the bottom
-- two determine the fine adjustment. For cosine, the quadrant processing is:
-- quadrant 00 : invert bottom 12 bits (rom index & fine adjust index).
-- quadrant 01 : cosine is negative.
-- quadrant 10 : invert bottom 12 bits, cosine is negative.
-- quadrant 11 : as looked up.
-- Sine is identical, except that the quadrant is processed differently:
-- quadrant 00 : as looked up.
-- quadrant 01 : invert bottom 12 bits.
-- quadrant 10 : sin is negative.
-- quadrant 11 : invert bottom 12 bits, sin is negative.
-- The (co)sines are scaled to range from 0 to 2^14/pi (and sign bit).
-- The average abs(sin) is 2/pi, after scaling 2^15/pi^2
-- Data sample is 13 bits plus sign, so worst case average multiplier
-- output is signed 2^28/pi^2, [just under] 25 bits plus sign. (Before taking
-- the shift due to 'gain' into account.)
-- e.g., accumulating over 1024 samples needs 35 bits plus sign.
-- second order accumulation needs 45 bits plus sign. Use all 48 bits...
signal phase : unsigned24 := x"000000";
signal sin_index, cos_index : unsigned(9 downto 0);
signal sin_packed, cos_packed : unsigned18;
signal sintable : sinrom_t := sinrom;
begin
cos : entity work.dc1 generic map(false)
port map(data, gain(3 downto 0), open, xx, phase(23 downto 10), clk,
cos_index, cos_packed);
sin : entity work.dc1 generic map(true)
port map(data, gain(3 downto 0), open, yy, phase(23 downto 10), clk,
sin_index, sin_packed);
process
begin
wait until rising_edge(clk);
phase <= phase + freq;
cos_packed <= sintable(to_integer(cos_index));
sin_packed <= sintable(to_integer(sin_index));
end process;
end downconvert;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
use work.sincos.all;
entity downconvertpll is
port (data : in signed14;
freq_in : in unsigned24;
gain : in unsigned8;
decay : in unsigned(3 downto 0);
freq_in_strobe : in std_logic;
xx, yy : out mf_signed;
phasor : out unsigned18;
freq_out : out unsigned(31 downto 0);
error_out : out unsigned(31 downto 0);
level_out : out unsigned(31 downto 0);
out_strobe : in std_logic;
clk : in std_logic);
end downconvertpll;
architecture downconvertpll of downconvertpll is
-- Our control loop looks like:
--
-- d/dt phase = freq + alpha error,
-- d/dt freq = error
-- d/dt error = -beta error - gamma phase
--
-- (counting t in clk cycles).
-- Eigenpolynomial is
-- lambda**3 + beta lambda**2 + alpha gamma lambda + gamma.
-- We are aiming for (lambda + beta/3)**3,
-- i.e., alpha gamma = beta**2 / 3, gamma = beta**3 / 27,
-- alpha = 9 / beta.
-- For convenience, take alpha = 8/beta so we can use bit shifts.
-- beta is 1/2 ** (beta_base + decay),
-- alpha is 2 ** (alpha_base + decay).
-- alpha_base = 14 = 3 + beta_base, beta_base = 11.
-- [so beta is in range 1/2048 to 1/262144, might want to allow lower
-- bandwidth]
-- and we want gamma around 1/27 * 1/2 ** (3*beta_base + 3*decay)
-- gamma is given by shifting and the multiplier scaling.
-- We phase to number of cycles, and t to be discrete number of clock cycles,
-- so that phase, freq and error can all be taken (mod 1).
-- Around phase=0 [and gain=0], the normalisation of our "sin" function is
-- d/dphase "sin"(phase) is 1/2 ** (-13), i.e, a step at
-- bit (-14) produces a step of 2 LSB of the "sin".
-- The overall mean multiplier of the trig multiply is halved and takes the
-- gain signal into account giving a mean multiplier of
-- 2 ** (gain + 12).
-- gamma is then composed of that, the signal strength [in units of LSB],
-- and a shift, i.e., we want
-- 1/27 * 1/2 ** (3*beta_base + 3*decay) = strength * 2 ** (gain + 12) * shift
-- 1 = 27 * strength * shift * 2 ** (gain + 12 + 3*beta_base + 3 * decay)
-- Design for gain to be set so that strength * 2**gain = 2**10
-- = 2**target_width.
-- Approximate 27 by 32, this gives
-- 1 = shift * 2 ** (3*beta_base + 3 * decay + target_width + 17)
-- shift = 1/2 ** (17 + 3*beta_base + target_width + 3 * decay), or
-- The design above gives a shift going into error.
-- It makes more sense to apply this coming out of error, than going in.
-- Fixed point, range [0,1). MSB has weight 0.5.
constant phase_width : integer := 32;
signal phase : signed(phase_width - 1 downto 0) := (others => '0');
constant beta_base : integer := 8;
constant alpha_base : integer := beta_base + 3;
constant level_base : integer := beta_base + 3;
-- Fixed point, MSB has weight 0.5.
constant freq_width : integer := 56;
constant freq_in_pad : signed(freq_width - 25 downto 0) := (others => '0');
signal freq : signed(freq_width - 1 downto 0) := x"642576" & freq_in_pad;
-- Target signal strength. The signal level should be about target_width
-- bits, after left shifting by the gain.
constant target_width : integer := 10;
-- Error (and level) are fix point with the LSB at position
-- (- 60 - 3*decay + error_drop).
constant error_width : integer := 32;
constant level_width : integer := 40;
constant error_drop : integer := 12;
constant level_drop : integer := 12;
signal error : signed(error_width - 1 downto 0);
signal level : signed(level_width - 1 downto 0);
-- These include an extra low bit for use in rounding.
signal error_1 : signed(error_width - beta_base downto 0);
signal level_1 : signed(level_width - level_base downto 0);
-- For the error scaling we need to right shift by
-- 17 + 3*beta_base + target_width + 3*decay - error_drop.
-- For the alignment with freq, left shift by freq_width.
-- We actually left shift by 33 by padding, right shift by 3*decay,
-- and right shift by 50+3*beta_base+target_width-freq_width
-- -error_drop by selecting.
constant error_f_w : integer := error_width + 33;
constant error_f_base : integer := 50 + 3 * beta_base + target_width
- freq_width - error_drop;
signal error_f1 : signed(error_f_w - 1 downto 0);
signal sin_index, cos_index : unsigned(9 downto 0);
signal sin_packed, cos_packed : unsigned18;
signal sintable : sinrom_t := sinrom;
alias cgain : unsigned(3 downto 0) is gain(3 downto 0);
alias sgain : unsigned(3 downto 0) is gain(7 downto 4);
signal sproduct, cproduct : signed36;
signal sproduct_1, sdelta : signed(error_width - 1 downto 0);
signal cproduct_1, cdelta : signed(level_width - 1 downto 0);
signal sproduct_r, cproduct_r, sproduct_r2, cproduct_r2 : std_logic;
-- For the error scaling we need to right shift by
-- 17 + 3*beta_base + target_width + 3*decay - error_drop.
-- For beta we need to left shift by alpha_base + decay.
-- For the alignment with phase, left shift by phase_width.
-- We actually pad by 22, and then right shift by 2*decay, and then
-- right shift (by selection) by
-- 39 + 3*beta_base + target_width - error_drop - alpha_base - phase_width.
constant error_p_w : integer := error_width + 22;
constant error_p_base : integer := 39 + 3*beta_base + target_width
- error_drop - alpha_base - phase_width;
constant error_p_max : integer := minimum(error_p_w,
error_p_base + phase_width);
signal error_p1 : signed(error_p_w - 1 downto 0);
signal phase_a : signed(phase_width - 1 downto 0);
signal base_phase : unsigned24;
-- For some bloody stupid reason, the sra operator doesn't work.
function ssra(val : signed; a : unsigned; m : integer := 1) return signed is
variable v : signed(val'length + 11 * m - 1 downto 0);
variable result : signed(val'length - 1 downto 0);
variable aa : unsigned(3 downto 0);
begin
v := (others => val(val'left));
v(val'length - 1 downto 0) := val;
result := (others => '0');
for i in 0 to 11 loop
if to_integer(a) = i then
result := v(val'length - 1 + i * m downto i * m);
end if;
end loop;
return result;
end ssra;
function top(val : signed; n : integer) return signed is
variable result : signed(n - 1 downto 0);
begin
result := val(val'left downto val'left + 1 - n);
return result;
end top;
function topd(val : signed; n : integer) return std_logic is
begin
return val(val'left - n);
end topd;
begin
cos : entity work.dc1 generic map(false, true)
port map(data, cgain, cproduct, xx,
unsigned(phase(phase_width - 1 downto phase_width - 14)),
clk, cos_index, cos_packed);
sin : entity work.dc1 generic map(true, true)
port map(data, sgain, sproduct, yy,
unsigned(phase(phase_width - 1 downto phase_width - 14)),
clk, sin_index, sin_packed);
process
variable error_1b : signed(error_width - beta_base downto 0);
variable level_1b : signed(level_width - level_base downto 0);
variable error_f0, error_f2 : signed(error_f_w - 1 downto 0);
variable error_p0, error_p2 : signed(error_p_w - 1 downto 0);
begin
wait until rising_edge(clk);
cos_packed <= sintable(to_integer(cos_index));
sin_packed <= sintable(to_integer(sin_index));
sproduct_1 <= top(resize(sproduct, error_width + error_drop)
sll to_integer(sgain and "1000"),
error_width);
sproduct_r <= topd(resize(sproduct, error_width + error_drop)
sll to_integer(sgain and "1000"),
error_width);
cproduct_1 <= top(resize(cproduct, level_width + level_drop)
sll to_integer(cgain and "1000"),
level_width);
cproduct_r <= topd(resize(cproduct, level_width + level_drop)
sll to_integer(cgain and "1000"),
level_width);
error_1 <= ssra(error(error_width - 1 downto beta_base - 1),
decay and "0011");
level_1 <= ssra(level(level_width - 1 downto level_base - 1),
decay and "0011");
error_1b := ssra(error_1, decay and "1100");
level_1b := ssra(level_1, decay and "1100");
sdelta <= sproduct_1 - error_1b(error_width - beta_base downto 1)
- ("0" & error_1b(0));
cdelta <= cproduct_1 - level_1b(level_width - level_base downto 1)
- ("0" & level_1b(0));
sproduct_r2 <= sproduct_r;
cproduct_r2 <= cproduct_r;
error <= error + sdelta + ("0" & sproduct_r2);
level <= level + cdelta + ("0" & cproduct_r2);
error_f0 := (others => '0');
error_f0(error_f_w - 1 downto error_f_w - error_width) := error;
error_f1 <= ssra(error_f0, decay and "0011", 3);
error_f2 := ssra(error_f1, decay and "1100", 3);
freq <= freq + error_f2(error_f_w - 1 downto error_f_base)
+ ("0" & error_f2(error_f_base - 1));
error_p0 := (others => '0');
error_p0(error_p_w - 1 downto error_p_w - error_width) := error;
error_p1 <= ssra(error_p0, decay and "0011", 2);
error_p2 := ssra(error_p1, decay and "1100", 2);
phase_a <= freq(freq_width - 1 downto freq_width - phase_width)
+ error_p2(error_p_max - 1 downto error_p_base)
+ ("0" & error_p2(error_p_base - 1));
phase <= phase + phase_a;
if freq_in_strobe = '1' then
freq <= (signed(freq_in) & freq_in_pad)
+ error_f2(error_f_w - 1 downto error_f_base)
+ ("0" & error_f2(error_f_base - 1));
error <= (others => '0');
level <= (others => '0');
error_1 <= (others => '0');
level_1 <= (others => '0');
sdelta <= (others => '0');
cdelta <= (others => '0');
error_f1 <= (others => '0');
end if;
if out_strobe = '1' then
freq_out <= unsigned(freq(freq'left downto freq'left - 31));
error_out <= unsigned(error(error'left downto error'left - 31));
level_out <= unsigned(level(level'left downto level'left - 31));
end if;
base_phase <= base_phase + freq_in;
phasor <= unsigned(phase(phase_width - 1 downto phase_width - 18))
- base_phase(23 downto 6);
end process;
end downconvertpll;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/14-MESA-IA/asap-alap-random/mesaia_asap.vhd
|
1
|
9734
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:53:38)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 30);
output1, output2, output3, output4: OUT unsigned(0 TO 31));
END mesaia_asap_entity;
ARCHITECTURE mesaia_asap_description OF mesaia_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register10: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register11: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register12: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register13: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register14: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register15: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register16: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register17: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register18: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register19: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register20: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register21: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register22: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register23: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register24: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register25: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register26: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register27: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register28: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register29: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register30: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register31: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register32: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register33: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register34: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register35: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register36: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register37: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register38: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register39: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register40: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register41: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register42: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register43: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register44: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register45: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register46: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register47: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register48: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 + 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 * 9;
register10 := input10 * 10;
register11 := input11 + 11;
register12 := input12 * 12;
register13 := input13 * 13;
register14 := input14 * 14;
register15 := input15 + 15;
register16 := input16 * 16;
register17 := input17 * 17;
register18 := input18 + 18;
register19 := input19 * 19;
register20 := input20 * 20;
register21 := input21 * 21;
register22 := input22 * 22;
register23 := input23 + 23;
register24 := input24 * 24;
register25 := input25 * 25;
register26 := input26 * 26;
register27 := input27 * 27;
register28 := input28 * 28;
register29 := input29 + 29;
register30 := input30 * 30;
register31 := input31 * 31;
register32 := input32 + 32;
register33 := input33 * 33;
register34 := input34 * 34;
register35 := input35 * 35;
register36 := input36 + 36;
register37 := input37 * 37;
register38 := input38 * 38;
register39 := input39 + 39;
register40 := input40 * 40;
register41 := input41 * 41;
register42 := input42 * 42;
register43 := input43 + 43;
register44 := input44 * 44;
register45 := input45 + 45;
register46 := input46 + 46;
register47 := input47 * 47;
register48 := input48 + 48;
WHEN "00000010" =>
register1 := register24 + register1;
register2 := register2 + register32;
register3 := register3 + register39;
register5 := register38 + register5;
register6 := register10 + register6;
register7 := register40 + register7;
register9 := register9 + register48;
register10 := register22 + register11;
register11 := register12 + register45;
register12 := register14 + register36;
register14 := register27 + register15;
register15 := register17 + register43;
register17 := register28 + register18;
register18 := register19 + register23;
register19 := register34 + register29;
register22 := register44 + register46;
WHEN "00000011" =>
register1 := register25 + register1;
register2 := register33 + register2;
register3 := register4 + register3;
register4 := register37 + register5;
register5 := register30 + register6;
register6 := register41 + register7;
register7 := register8 + register9;
register8 := register21 + register10;
register9 := register31 + register11;
register10 := register13 + register12;
register11 := register26 + register14;
register12 := register16 + register15;
register13 := register42 + register17;
register14 := register20 + register18;
register15 := register35 + register19;
register16 := register47 + register22;
WHEN "00000100" =>
register1 := ((NOT register1) + 1) XOR register1;
register3 := ((NOT register3) + 1) XOR register3;
register4 := ((NOT register4) + 1) XOR register4;
register6 := ((NOT register6) + 1) XOR register6;
register7 := ((NOT register7) + 1) XOR register7;
register8 := ((NOT register8) + 1) XOR register8;
register11 := ((NOT register11) + 1) XOR register11;
register12 := ((NOT register12) + 1) XOR register12;
register13 := ((NOT register13) + 1) XOR register13;
register14 := ((NOT register14) + 1) XOR register14;
register15 := ((NOT register15) + 1) XOR register15;
register16 := ((NOT register16) + 1) XOR register16;
WHEN "00000101" =>
register1 := register6 - register1;
register4 := register16 - register4;
register6 := register7 - register12;
register7 := register13 - register14;
WHEN "00000110" =>
register1 := register1 * 74;
register4 := register4 * 76;
register6 := register6 * 78;
register7 := register7 * 80;
WHEN "00000111" =>
register1 := register15 + register1;
register3 := register3 + register4;
register4 := register11 + register6;
register6 := register8 + register7;
WHEN "00001000" =>
output1 <= register1(0 TO 14) & register9(0 TO 15);
output2 <= register3(0 TO 14) & register5(0 TO 15);
output3 <= register4(0 TO 14) & register2(0 TO 15);
output4 <= register6(0 TO 14) & register10(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_asap_description;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/7-FIR1/metaheurísticas/fir1_wsga.vhd
|
1
|
3673
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-26.15:30:58)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY fir1_wsga_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22: IN unsigned(0 TO 3);
output1: OUT unsigned(0 TO 4));
END fir1_wsga_entity;
ARCHITECTURE fir1_wsga_description OF fir1_wsga_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register9: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register10: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register11: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 and input1;
register2 := input2 and input2;
register3 := input3 and input3;
register4 := input4 and input4;
WHEN "00000010" =>
register5 := input5 and input5;
register6 := input6 and input6;
register7 := input7 and input7;
register1 := register1 * register4;
register4 := input8 and input8;
register2 := register3 * register2;
WHEN "00000011" =>
register3 := register6 * register4;
register4 := input9 and input9;
register6 := input10 and input10;
register5 := register7 * register5;
register7 := input11 and input11;
WHEN "00000100" =>
register6 := register6 * register7;
register7 := input12 and input12;
WHEN "00000101" =>
register4 := register4 * register7;
register3 := register6 + register3;
WHEN "00000110" =>
register2 := register3 + register2;
register3 := input13 and input13;
register6 := input14 and input14;
register7 := input15 and input15;
register8 := input16 and input16;
WHEN "00000111" =>
register3 := register8 * register3;
register8 := input17 and input17;
register9 := input18 and input18;
register10 := input19 and input19;
register11 := input20 and input20;
register1 := register1 + register2;
WHEN "00001000" =>
register2 := input21 and input21;
register6 := register10 * register6;
register9 := register11 * register9;
register7 := register8 * register7;
WHEN "00001001" =>
register5 := register5 + register9;
register8 := input22 and input22;
register6 := register7 + register6;
WHEN "00001010" =>
register1 := register6 + register1;
WHEN "00001011" =>
register1 := register1 + register4;
register2 := register2 * register8;
WHEN "00001100" =>
register1 := register5 + register1;
WHEN "00001101" =>
register1 := register1 + register2;
WHEN "00001110" =>
register1 := register3 + register1;
WHEN "00001111" =>
output1 <= register1 and register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END fir1_wsga_description;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/3-ARF/metaheurísticas/arf_nsga2.vhd
|
1
|
2608
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:34:32)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END arf_nsga2_entity;
ARCHITECTURE arf_nsga2_description OF arf_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := input3 * 3;
register3 := input4 * 4;
WHEN "00000011" =>
register2 := register3 + register2;
register3 := input5 * 5;
register4 := input6 * 6;
WHEN "00000100" =>
register3 := register3 + register4;
register2 := register2 + 8;
register4 := input7 * 9;
register1 := register1 + 11;
register5 := input8 * 12;
WHEN "00000101" =>
register4 := register4 + register5;
register5 := register1 * 14;
register6 := register2 * 16;
WHEN "00000110" =>
register1 := register1 * 18;
register2 := register2 * 20;
register5 := register6 + register5;
WHEN "00000111" =>
register1 := register2 + register1;
WHEN "00001000" =>
register2 := register1 * 22;
register6 := register5 * 24;
WHEN "00001001" =>
register1 := register1 * 26;
register5 := register5 * 28;
register2 := register6 + register2;
WHEN "00001010" =>
register1 := register5 + register1;
output1 <= register3 + register2;
WHEN "00001011" =>
output2 <= register4 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_nsga2_description;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/1-HAL/asap-alap-random/hal_random.vhd
|
1
|
1688
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.08:58:13)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_random_entity;
ARCHITECTURE hal_random_description OF hal_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := input3 * 3;
WHEN "00000011" =>
register4 := input4 * 4;
output1 <= register1 + 5;
WHEN "00000100" =>
register1 := input5 * 6;
WHEN "00000101" =>
register1 := register4 * register1;
WHEN "00000110" =>
register1 := register1 - 8;
register3 := register3 * 10;
IF (register2 < 11) THEN
output2 <= register2;
ELSE
output2 <= "01011";
END IF;
WHEN "00000111" =>
output3 <= register1 - register3;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_random_description;
|
gpl-3.0
|
rhexsel/xinu-cMIPS
|
vhdl/units.vhd
|
2
|
21553
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Altera's design for a dual-port RAM that can be synthesized
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
entity ram_dual is
generic (N_WORDS : integer := 64;
WIDTH : integer := 8);
port (data : in std_logic_vector(WIDTH - 1 downto 0);
raddr : in natural range 0 to N_WORDS - 1;
waddr : in natural range 0 to N_WORDS - 1;
we : in std_logic;
rclk : in std_logic;
wclk : in std_logic;
q : out std_logic_vector(WIDTH - 1 downto 0));
end ram_dual;
architecture rtl of ram_dual is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector(WIDTH - 1 downto 0);
type memory_t is array(N_WORDS - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t; -- := (others => (others => '0'));
begin
process(wclk)
begin
if(rising_edge(wclk)) then
if(we = '1') then
ram(waddr) <= data;
end if;
end if;
end process;
process(rclk)
begin
if(rising_edge(rclk)) then
q <= ram(raddr);
end if;
end process;
end rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- register bank, reg(0) always 0, write-enable=0
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_Logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity reg_bank is
port(wrclk, rdclk, wren : in std_logic;
a_rs, a_rt, a_rd : in reg5;
C : in reg32;
A, B : out reg32);
end reg_bank;
-- -----------------------------------------------------------------------
-- RTL with implicit memory
-- -----------------------------------------------------------------------
architecture rtl of reg_bank is
type reg_file is array(0 to 31) of reg32;
signal reg_file_A : reg_file;
signal reg_file_B : reg_file;
signal int_rs, int_rt, int_rd : integer range 0 to 31;
signal pre_A, pre_B : reg32;
begin
int_rs <= to_integer(unsigned(a_rs));
int_rt <= to_integer(unsigned(a_rt));
int_rd <= to_integer(unsigned(a_rd));
-- forwarding WB -> RF, external to RAM
A <= C when (a_rd = a_rs) and (wren = '0') and (a_rs /= b"00000")
else pre_A when a_rs /= b"00000"
else x"00000000"; -- reg0 always zero
B <= C when (a_rd = a_rt) and (wren = '0') and (a_rt /= b"00000")
else pre_B when a_rt /= b"00000"
else x"00000000";
WRITE_REG_BANKS: process(wrclk, rdclk)
begin
if rising_edge(rdclk) then -- read early
pre_A <= reg_file_A( int_rs );
pre_B <= reg_file_B( int_rt );
end if;
-- write to enforce setup (forwarding is external to RAM)
if rising_edge(wrclk) then
if wren = '0' and int_rd /= 0 then
reg_file_A( int_rd ) <= C;
reg_file_B( int_rd ) <= C;
end if;
end if;
end process WRITE_REG_BANKS;
end rtl;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- RTL with explicitly declared dual-port RAMs (FPGA friendly)
-- -----------------------------------------------------------------------
architecture dual_port_ram of reg_bank is
component ram_dual is
generic (N_WORDS : integer;
WIDTH : integer);
port (data : in std_logic_vector;
raddr : in natural range 0 to N_WORDS-1;
waddr : in natural range 0 to N_WORDS-1;
we : in std_logic;
rclk : in std_logic;
wclk : in std_logic;
q : out std_logic_vector);
end component ram_dual;
signal int_rs, int_rt, int_rd : integer range 0 to 31;
signal pre_A, pre_B : reg32;
signal update : std_logic;
begin
int_rs <= to_integer(unsigned(a_rs));
int_rt <= to_integer(unsigned(a_rt));
int_rd <= to_integer(unsigned(a_rd));
update <= '1' when wren = '0' and int_rd /= 0 else '0';
PORT_A: ram_dual generic map (32, 32)
port map (C, int_rs, int_rd, update, rdclk, wrclk, pre_A);
PORT_B: ram_dual generic map (32, 32)
port map (C, int_rt, int_rd, update, rdclk, wrclk, pre_B);
-- internal forwarding WB -> RF
A <= C when (a_rd = a_rs) and (wren = '0') and (a_rs /= b"00000") else
pre_A when a_rs /= b"00000"
else x"00000000"; -- reg0 always zero
B <= C when (a_rd = a_rt) and (wren = '0') and (a_rt /= b"00000") else
pre_B when a_rt /= b"00000"
else x"00000000";
end architecture dual_port_ram;
-- -----------------------------------------------------------------------
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ALU
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity alu is
port(clk,rst: in std_logic;
A, B: in reg32;
C: out reg32;
LO: out reg32;
HI: out reg32;
wr_hilo: in std_logic; -- write to HI & LO, active high
move_ok: out std_logic;
fun: in t_alu_fun;
postn: in reg5;
shamt: in reg5;
ovfl: out std_logic);
end alu;
architecture functional of alu is
component register32 is
generic (INITIAL_VALUE: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component register32;
component mf_alt_add_sub is
port(add_sub : IN STD_LOGIC; -- add=1, sub=0
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component mf_alt_add_sub;
component mf_alt_add_sub_u is
port(add_sub : IN STD_LOGIC; -- add=1, sub=0
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component mf_alt_add_sub_u;
component mask_off_bits is
port(B : in std_logic_vector;
X : out std_logic_vector);
end component mask_off_bits;
component shift_left32 is
port(inp : in reg32;
shamt : in reg5;
otp : out reg32);
end component shift_left32;
component shift_right32 is
port(inp : in reg32;
arith: in std_logic;
shamt : in reg5;
otp : out reg32);
end component shift_right32;
signal operation : integer;
signal s_HI,s_LO, loc_HI,loc_LO, inp_HI,inp_LO, mask,mask_and : reg32;
signal sh_left, sh_right, sh_inp, sh_lft_ins, summ_diff, summ_diff_u : reg32;
signal addition, overflow, overflow_u, shift_arith, wr_hi,wr_lo : std_logic;
signal size,index, shift_amnt : reg5;
begin
assert fun /= invalid_op
report "INVALID ALU OPERATION: " & integer'image(operation)
severity failure;
operation <= t_alu_fun'pos(fun); -- for debugging only
U_alu: process (A,B, fun, sh_left,sh_right,sh_lft_ins,
mask, loc_HI,loc_LO, summ_diff, summ_diff_u, overflow)
variable i_C, i_and, i_or: reg32;
variable i_prod : reg64;
variable i_move_ok, B_is_zero : std_logic := 'L';
begin
ovfl <= '0';
addition <= '0';
i_move_ok := '0';
if (B = x"00000000") then B_is_zero := '1'; else B_is_zero := '0'; end if;
i_C := (others => '0');
case fun is
when opSLL | opSLLV => i_C := sh_left;
when opSRL | opSRA | opSRLV | opSRAV => i_C := sh_right;
when opMOVZ => -- reg_update handled at EX_stage
if (B_is_zero = '1') then
i_C := A;
i_move_ok := '1';
end if;
when opMOVN => -- reg_update handled at EX_stage
if (B_is_zero /= '1') then
i_C := A;
i_move_ok := '1';
end if;
when opMFHI => i_C := loc_HI;
when opMFLO => i_C := loc_LO;
when opADD => addition <= '1';
i_C := summ_diff;
ovfl <= overflow;
when opADDU => addition <= '1';
i_C := summ_diff_u;
ovfl <= '0';
when opSUB => addition <= '0';
i_C := summ_diff;
ovfl <= overflow;
when opSUBU => addition <= '0';
i_C := summ_diff_u;
ovfl <= '0';
when opAND => i_C := A and B;
when opOR => i_C := A or B;
when opXOR => i_C := A xor B;
when opNOR => i_C := A nor B;
when opSLT => addition <= '0';
if ( overflow = '1' ) then -- ovfl
i_C := x"0000000" & b"000" & not(summ_diff(31));
else
i_C := x"0000000" & b"000" & summ_diff(31);
end if;
-- this instr cannot cause an exception
when opSLTU => addition <= '0'; -- ignore overflow/signal
i_C := x"0000000" & b"000" & summ_diff_u(31);
ovfl <= '0';
when opLUI => i_C := B(15 downto 0) & x"0000";
when opSWAP => -- word swap bytes within halfwords
i_C := B(23 downto 16)&B(31 downto 24)&B(7 downto 0) &B(15 downto 8);
when opEXT => -- extract bit field
i_C := sh_right and mask;
when opINS => -- insert bit field
i_and := B and not(sh_left);
i_or := sh_lft_ins;
i_C := i_and or i_or;
when opSEB => -- sign-extend byte
if B(7) = '0' then
i_C := x"000000" & B(7 downto 0);
else
i_C := x"FFFFFF" & B(7 downto 0);
end if;
when opSEH => -- sign-extend halfword
if B(15) = '0' then
i_C := x"0000" & B(15 downto 0);
else
i_C := x"FFFF" & B(15 downto 0);
end if;
when opMUL =>
i_prod := std_logic_vector(signed(A) * signed(B));
i_C := i_prod(31 downto 0);
when others =>
i_C := (others => 'X');
end case;
--assert false report "alu: " &
-- "A="& SLV32HEX(A) &" ["& natural'image(operation) &"] B="&
-- SLV32HEX(B) &" ="& SLV32HEX( i_C ); -- DEBUG
move_ok <= i_move_ok;
C <= i_C;
end process U_alu; -- -------------------------------------------
U_ADD_SUB: mf_alt_add_sub -- signed add/subtract
port map (add_sub => addition, overflow => overflow,
dataa => A, datab => B, result => summ_diff);
U_ADD_SUB_U: mf_alt_add_sub_u -- UNsigned add/subtract, no overflow
port map (add_sub => addition,
dataa => A, datab => B, result => summ_diff_u);
U_HILO: process (A,B, fun, loc_HI,loc_LO)
variable i_hi,i_lo, i_quoc,i_rem: reg32;
variable i_prod : reg64;
variable s_quoc, s_rem : unsigned(31 downto 0);
begin
i_LO := (others => '0');
i_HI := (others => '0');
s_quoc := (others => '0');
s_rem := (others => '0');
case fun is
when opMULT | opMULTU =>
i_prod := std_logic_vector(signed(A) * signed(B));
i_LO := i_prod(31 downto 0);
i_HI := i_prod(63 downto 32);
when opDIV | opDIVU =>
if ( B = x"00000000" ) then -- NO exceptions caused by division
assert true report
"div by zero A="& SLV32HEX(A) &"["& integer'image(operation)&"]"
& SLV32HEX(B); -- DEBUG
i_quoc := x"FFFFFFFF";
i_rem := x"FFFFFFFF";
else
-- divmod(unsigned(A),unsigned(B),s_quoc,s_rem);
s_quoc := unsigned(A) / unsigned(B);
s_rem := unsigned(A) rem unsigned(B);
end if;
i_quoc := std_logic_vector(s_quoc);
i_rem := std_logic_vector(s_rem);
i_LO := i_quoc;
i_HI := i_rem;
when others =>
i_hi := (others => 'X'); -- to help synthesis
i_lo := (others => 'X'); -- to help synthesis
s_quoc := (others => 'X'); -- to help synthesis
s_rem := (others => 'X'); -- to help synthesis
end case;
s_HI <= i_hi;
s_LO <= i_lo;
end process U_HILO; -- -------------------------------------------
U_hilo_inp: process (A, fun, s_HI, s_LO, wr_hilo)
begin
wr_lo <= '1';
wr_hi <= '1';
case fun is
when opMULT | opMULTU | opDIV | opDIVU =>
wr_lo <= wr_hilo;
wr_hi <= wr_hilo;
inp_HI <= s_HI;
inp_LO <= s_LO;
when opMTLO =>
wr_lo <= wr_hilo;
inp_LO <= A;
wr_hi <= '1';
inp_HI <= (others => 'X');
when opMTHI =>
wr_hi <= wr_hilo;
inp_HI <= A;
wr_lo <= '1';
inp_LO <= (others => 'X');
when others =>
wr_lo <= '1';
wr_hi <= '1';
inp_LO <= (others => 'X');
inp_HI <= (others => 'X');
end case;
end process U_hilo_inp; -- -------------------------------------------
U_HI: register32 generic map (x"00000000")
port map(clk, rst, wr_hi, inp_HI, loc_HI);
U_LO: register32 generic map (x"00000000")
port map(clk, rst, wr_lo, inp_LO, loc_LO);
HI <= loc_HI;
LO <= loc_LO;
U_shifts: process (A,B, fun, shamt, mask)
begin
case fun is
when opSLL | opSRL =>
sh_inp <= B;
shift_arith <= '0';
shift_amnt <= shamt;
when opSRA =>
sh_inp <= B;
shift_arith <= '1';
shift_amnt <= shamt;
when opSLLV | opSRLV => -- operators RS and RT exchanged!!
sh_inp <= B;
shift_arith <= '0';
shift_amnt <= A(4 downto 0);
when opSRAV => -- operators RS and RT exchanged!!
sh_inp <= B;
shift_arith <= '1';
shift_amnt <= A(4 downto 0);
when opEXT =>
sh_inp <= A;
shift_arith <= '0';
shift_amnt <= shamt;
when opINS =>
sh_inp <= mask;
shift_arith <= '0';
shift_amnt <= shamt;
when others =>
-- sh_inp <= B;
-- shift_arith <= '0';
-- shift_amnt <= b"00000";
sh_inp <= (others => 'X');
shift_arith <= '0';
shift_amnt <= (others => 'X');
end case;
end process U_shifts; -- -------------------------------------------
U_sh_left: shift_left32 port map (sh_inp,shift_amnt, sh_left);
U_sh_right: shift_right32 port map (sh_inp,shift_arith,shift_amnt, sh_right);
U_sh_left_ins: shift_left32 port map (mask_and,shift_amnt, sh_lft_ins);
size <= std_logic_vector(unsigned(postn) - unsigned(shamt));
index <= size when (fun = opINS) else postn;
U_mask: mask_off_bits port map (index, mask);
mask_and <= A and mask;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- sel32: select bit field (right aligned)
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;
use work.p_wires.all;
entity mask_off_bits is
port(B : in reg5;
X : out reg32);
end mask_off_bits;
architecture table of mask_off_bits is
type sel_vector is array (0 to 31) of reg32;
constant sel_array : sel_vector := (
x"00000001",--0
x"00000003",
x"00000007",
x"0000000f",
x"0000001f",--4
x"0000003f",
x"0000007f",
x"000000ff",
x"000001ff",--8
x"000003ff",
x"000007ff",
x"00000fff",
x"00001fff",--12
x"00003fff",
x"00007fff",
x"0000ffff",
x"0001ffff",--16
x"0003ffff",
x"0007ffff",
x"000fffff",
x"001fffff",--20
x"003fffff",
x"007fffff",
x"00ffffff",
x"01ffffff",--24
x"03ffffff",
x"07ffffff",
x"0fffffff",
x"1fffffff",--28
x"3fffffff",
x"7fffffff",
x"ffffffff");
begin
X <= sel_array(to_integer(unsigned(B)));
end table;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- shift-left32: shift left a specified number of bits
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity shift_left32 is
port(inp : in reg32;
shamt : in reg5;
otp : out reg32);
end shift_left32;
architecture functional of shift_left32 is
begin
U_shift_left: process (inp, shamt)
variable i_1, i_2, i_4, i_8, i_16 : reg32;
begin
if shamt(0) = '1' then i_1 := inp(30 downto 0) & b"0";
else i_1 := inp;
end if;
if shamt(1) = '1' then i_2 := i_1(29 downto 0) & b"00";
else i_2 := i_1;
end if;
if shamt(2) = '1' then i_4 := i_2(27 downto 0) & b"0000";
else i_4 := i_2;
end if;
if shamt(3) = '1' then i_8 := i_4(23 downto 0) & b"00000000";
else i_8 := i_4;
end if;
if shamt(4) = '1' then i_16 := i_8(15 downto 0) & b"0000000000000000";
else i_16 := i_8;
end if;
otp <= i_16;
end process U_shift_left;
end functional;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- shift-right32: shift right a specified number of bits
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity shift_right32 is
port(inp : in reg32;
arith: in std_logic;
shamt : in reg5;
otp : out reg32);
end shift_right32;
architecture functional of shift_right32 is
begin
U_shift_right: process (inp, arith, shamt)
variable i_1, i_2, i_4, i_8, i_16, sign_ext : reg32;
begin -- process U_shift_right
if arith = '1' then sign_ext := (others => inp(31));
else sign_ext := (others => '0');
end if;
if shamt(0) = '1' then i_1 := sign_ext(31) & inp(31 downto 1);
else i_1 := inp;
end if;
if shamt(1) = '1' then i_2 := sign_ext(31 downto 30) & i_1(31 downto 2);
else i_2 := i_1;
end if;
if shamt(2) = '1' then i_4 := sign_ext(31 downto 28) & i_2(31 downto 4);
else i_4 := i_2;
end if;
if shamt(3) = '1' then i_8 := sign_ext(31 downto 24) & i_4(31 downto 8);
else i_8 := i_4;
end if;
if shamt(4) = '1' then i_16 := sign_ext(31 downto 16) & i_8(31 downto 16);
else i_16 := i_8;
end if;
otp <= i_16;
end process U_shift_right;
end functional;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- bus interface: generates ONE wait-state request
-- peripheral/mem must generate additional waits, if needed
-- "waiting" is active only for the first clock cycle of reference
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end wait_states;
architecture structural of wait_states is
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component FFT is
port(clk, rst, T : in std_logic; Q : out std_logic);
end component FFT;
signal will_wait, w, w_d, n_sel, cycle, this : std_logic;
begin
n_sel <= not(sel);
will_wait <= '0' when NUM_WAIT_STATES = 0 else '1';
-- modulo 2 reference counter, changes at every reference
U_DO_WAIT: FFT port map
(clk => clk, rst => rst, T => n_sel, Q => cycle);
-- ref counter delayed, so will deactivate "waiting" at end of 1st clock
U_OLD_CYCLE: FFD port map
(clk => clk, rst => rst, set => '1', D => cycle, Q => this);
-- w_d <= this xor cycle; -- active for ONE cycle only
waiting <= not(this xor cycle) and n_sel and will_wait;
end;
-- ++ wait_states +++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-30bits_outputs31bits/3-ARF/metaheurísticas/arf_ibea.vhd
|
1
|
2625
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:35:07)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY arf_ibea_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END arf_ibea_entity;
ARCHITECTURE arf_ibea_description OF arf_ibea_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
WHEN "00000010" =>
register3 := input3 * 3;
register1 := register2 + register1;
register2 := input4 * 4;
WHEN "00000011" =>
register2 := register3 + register2;
register3 := input5 * 5;
register4 := input6 * 6;
WHEN "00000100" =>
register3 := register4 + register3;
register4 := input7 * 7;
register5 := input8 * 8;
WHEN "00000101" =>
register4 := register5 + register4;
register2 := register2 + 10;
register3 := register3 + 12;
WHEN "00000110" =>
register5 := register2 * 14;
register6 := register3 * 16;
WHEN "00000111" =>
register5 := register6 + register5;
register2 := register2 * 18;
register3 := register3 * 20;
WHEN "00001000" =>
register6 := register5 * 22;
register2 := register3 + register2;
WHEN "00001001" =>
register3 := register2 * 24;
WHEN "00001010" =>
register3 := register6 + register3;
register5 := register5 * 26;
register2 := register2 * 28;
WHEN "00001011" =>
output1 <= register1 + register3;
register1 := register5 + register2;
WHEN "00001100" =>
output2 <= register4 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END arf_ibea_description;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/LEKO_LEKU/leku/LEKU-CD'/25_3.vhd
|
1
|
193760
|
Library IEEE;
use IEEE.std_logic_1164.all;
entity x25_3x is
Port (
A302,A301,A300,A299,A298,A269,A268,A267,A266,A265,A236,A235,A234,A233,A232,A203,A202,A201,A200,A199,A166,A167,A168,A169,A170: in std_logic;
A140: buffer std_logic
);
end x25_3x;
architecture x25_3x_behav of x25_3x is
signal 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7647a,a7648a,a7649a,a7653a,a7654a,a7658a,a7659a,a7660a,a7663a,a7667a,a7668a,a7669a,a7673a,a7674a,a7678a,a7679a,a7680a,a7683a,a7687a,a7688a,a7689a,a7693a,a7694a,a7698a,a7699a,a7700a,a7703a,a7707a,a7708a,a7709a,a7713a,a7714a,a7718a,a7719a,a7720a,a7723a,a7727a,a7728a,a7729a,a7733a,a7734a,a7738a,a7739a,a7740a,a7743a,a7747a,a7748a,a7749a,a7753a,a7754a,a7758a,a7759a,a7760a,a7763a,a7767a,a7768a,a7769a,a7773a,a7774a,a7778a,a7779a,a7780a,a7783a,a7787a,a7788a,a7789a,a7793a,a7794a,a7798a,a7799a,a7800a,a7803a,a7807a,a7808a,a7809a,a7813a,a7814a,a7818a,a7819a,a7820a,a7823a,a7827a,a7828a,a7829a,a7833a,a7834a,a7838a,a7839a,a7840a,a7843a,a7847a,a7848a,a7849a,a7853a,a7854a,a7858a,a7859a,a7860a,a7863a,a7867a,a7868a,a7869a,a7873a,a7874a,a7878a,a7879a,a7880a,a7883a,a7887a,a7888a,a7889a,a7893a,a7894a,a7898a,a7899a,a7900a,a7903a,a7907a,a7908a,a7909a,a7913a,a7914a,a7918a,a7919a,a7920a,a7923a,a7927a,a7928a,a7929a,a7933a,a7934a,a7938a,a7939a,a7940a,a7943a,a7947a,a7948a,a7949a,a7953a,a7954a,a7958a,a7959a,a7960a,a7964a,a7965a,a7969a,a7970a,a7971a,a7975a,a7976a,a7980a,a7981a,a7982a,a7986a,a7987a,a7991a,a7992a,a7993a,a7997a,a7998a,a8002a,a8003a,a8004a,a8008a,a8009a,a8013a,a8014a,a8015a,a8019a,a8020a,a8024a,a8025a,a8026a,a8030a,a8031a,a8035a,a8036a,a8037a,a8041a,a8042a,a8046a,a8047a,a8048a,a8052a,a8053a,a8057a,a8058a,a8059a,a8063a,a8064a,a8068a,a8069a,a8070a,a8074a,a8075a,a8079a,a8080a,a8081a,a8085a,a8086a,a8090a,a8091a,a8092a,a8096a,a8097a,a8101a,a8102a,a8103a,a8107a,a8108a,a8112a,a8113a,a8114a,a8118a,a8119a,a8123a,a8124a,a8125a,a8129a,a8130a,a8134a,a8135a,a8136a,a8140a,a8141a,a8145a,a8146a,a8147a,a8151a,a8152a,a8156a,a8157a,a8158a,a8162a,a8163a,a8167a,a8168a,a8169a,a8173a,a8174a,a8178a,a8179a,a8180a,a8184a,a8185a,a8189a,a8190a,a8191a,a8195a,a8196a,a8200a,a8201a,a8202a,a8206a,a8207a,a8211a,a8212a,a8213a,a8217a,a8218a,a8222a,a8223a,a8224a,a8228a,a8229a,a8233a,a8234a,a8235a,a8239a,a8240a,a8244a,a8245a,a8246a,a8250a,a8251a,a8255a,a8256a,a8257a,a8261a,a8262a,a8266a,a8267a,a8268a,a8272a,a8273a,a8277a,a8278a,a8279a,a8283a,a8284a,a8288a,a8289a,a8290a,a8294a,a8295a,a8299a,a8300a,a8301a,a8305a,a8306a,a8310a,a8311a,a8312a,a8316a,a8317a,a8321a,a8322a,a8323a,a8327a,a8328a,a8332a,a8333a,a8334a,a8338a,a8339a,a8343a,a8344a,a8345a,a8349a,a8350a,a8354a,a8355a,a8356a,a8360a,a8361a,a8365a,a8366a,a8367a,a8371a,a8372a,a8376a,a8377a,a8378a,a8382a,a8383a,a8387a,a8388a,a8389a,a8393a,a8394a,a8398a,a8399a,a8400a,a8404a,a8405a,a8409a,a8410a,a8411a,a8415a,a8416a,a8420a,a8421a,a8422a,a8426a,a8427a,a8431a,a8432a,a8433a,a8437a,a8438a,a8442a,a8443a,a8444a,a8448a,a8449a,a8453a,a8454a,a8455a,a8459a,a8460a,a8464a,a8465a,a8466a,a8470a,a8471a,a8475a,a8476a,a8477a,a8481a,a8482a,a8486a,a8487a,a8488a,a8492a,a8493a,a8497a,a8498a,a8499a,a8503a,a8504a,a8508a,a8509a,a8510a,a8514a,a8515a,a8519a,a8520a,a8521a,a8525a,a8526a,a8530a,a8531a,a8532a,a8536a,a8537a,a8541a,a8542a,a8543a,a8547a,a8548a,a8552a,a8553a,a8554a,a8558a,a8559a,a8563a,a8564a,a8565a,a8569a,a8570a,a8574a,a8575a,a8576a,a8580a,a8581a,a8585a,a8586a,a8587a,a8591a,a8592a,a8596a,a8597a,a8598a,a8602a,a8603a,a8607a,a8608a,a8609a,a8613a,a8614a,a8618a,a8619a,a8620a,a8624a,a8625a,a8629a,a8630a,a8631a,a8635a,a8636a,a8640a,a8641a,a8642a,a8646a,a8647a,a8651a,a8652a,a8653a,a8657a,a8658a,a8662a,a8663a,a8664a,a8668a,a8669a,a8673a,a8674a,a8675a,a8679a,a8680a,a8684a,a8685a,a8686a,a8690a,a8691a,a8695a,a8696a,a8697a,a8701a,a8702a,a8706a,a8707a,a8708a,a8712a,a8713a,a8717a,a8718a,a8719a,a8723a,a8724a,a8728a,a8729a,a8730a,a8734a,a8735a,a8739a,a8740a,a8741a,a8745a,a8746a,a8750a,a8751a,a8752a,a8756a,a8757a,a8761a,a8762a,a8763a,a8767a,a8768a,a8772a,a8773a,a8774a,a8778a,a8779a,a8783a,a8784a,a8785a,a8789a,a8790a,a8794a,a8795a,a8796a,a8800a,a8801a,a8805a,a8806a,a8807a,a8811a,a8812a,a8816a,a8817a,a8818a,a8822a,a8823a,a8827a,a8828a,a8829a,a8833a,a8834a,a8838a,a8839a,a8840a,a8844a,a8845a,a8849a,a8850a,a8851a,a8855a,a8856a,a8860a,a8861a,a8862a,a8866a,a8867a,a8871a,a8872a,a8873a,a8877a,a8878a,a8882a,a8883a,a8884a,a8888a,a8889a,a8893a,a8894a,a8895a,a8899a,a8900a,a8904a,a8905a,a8906a,a8910a,a8911a,a8915a,a8916a,a8917a,a8921a,a8922a,a8926a,a8927a,a8928a,a8932a,a8933a,a8937a,a8938a,a8939a,a8943a,a8944a,a8948a,a8949a,a8950a,a8954a,a8955a,a8959a,a8960a,a8961a,a8965a,a8966a,a8970a,a8971a,a8972a,a8976a,a8977a,a8981a,a8982a,a8983a,a8987a,a8988a,a8992a,a8993a,a8994a,a8998a,a8999a,a9003a,a9004a,a9005a,a9009a,a9010a,a9014a,a9015a,a9016a,a9020a,a9021a,a9025a,a9026a,a9027a,a9031a,a9032a,a9036a,a9037a,a9038a,a9042a,a9043a,a9047a,a9048a,a9049a,a9053a,a9054a,a9058a,a9059a,a9060a,a9064a,a9065a,a9069a,a9070a,a9071a,a9075a,a9076a,a9080a,a9081a,a9082a,a9086a,a9087a,a9091a,a9092a,a9093a,a9097a,a9098a,a9102a,a9103a,a9104a,a9108a,a9109a,a9113a,a9114a,a9115a,a9119a,a9120a,a9124a,a9125a,a9126a,a9130a,a9131a,a9135a,a9136a,a9137a,a9141a,a9142a,a9146a,a9147a,a9148a,a9152a,a9153a,a9157a,a9158a,a9159a,a9163a,a9164a,a9168a,a9169a,a9170a,a9174a,a9175a,a9179a,a9180a,a9181a,a9185a,a9186a,a9190a,a9191a,a9192a,a9196a,a9197a,a9201a,a9202a,a9203a,a9207a,a9208a,a9212a,a9213a,a9214a,a9218a,a9219a,a9223a,a9224a,a9225a,a9229a,a9230a,a9234a,a9235a,a9236a,a9240a,a9241a,a9245a,a9246a,a9247a,a9251a,a9252a,a9256a,a9257a,a9258a,a9262a,a9263a,a9267a,a9268a,a9269a,a9273a,a9274a,a9278a,a9279a,a9280a,a9284a,a9285a,a9289a,a9290a,a9291a,a9295a,a9296a,a9300a,a9301a,a9302a,a9306a,a9307a,a9311a,a9312a,a9313a,a9317a,a9318a,a9322a,a9323a,a9324a,a9328a,a9329a,a9333a,a9334a,a9335a,a9339a,a9340a,a9344a,a9345a,a9346a,a9350a,a9351a,a9355a,a9356a,a9357a,a9361a,a9362a,a9366a,a9367a,a9368a,a9372a,a9373a,a9377a,a9378a,a9379a,a9383a,a9384a,a9387a,a9390a,a9391a,a9392a,a9396a,a9397a,a9401a,a9402a,a9403a,a9407a,a9408a,a9411a,a9414a,a9415a,a9416a,a9420a,a9421a,a9425a,a9426a,a9427a,a9431a,a9432a,a9435a,a9438a,a9439a,a9440a,a9444a,a9445a,a9449a,a9450a,a9451a,a9455a,a9456a,a9459a,a9462a,a9463a,a9464a,a9468a,a9469a,a9473a,a9474a,a9475a,a9479a,a9480a,a9483a,a9486a,a9487a,a9488a,a9492a,a9493a,a9497a,a9498a,a9499a,a9503a,a9504a,a9507a,a9510a,a9511a,a9512a,a9516a,a9517a,a9521a,a9522a,a9523a,a9527a,a9528a,a9531a,a9534a,a9535a,a9536a,a9540a,a9541a,a9545a,a9546a,a9547a,a9551a,a9552a,a9555a,a9558a,a9559a,a9560a: std_logic;
begin
A140 <=( a1312a ) or ( a875a );
a1a <=( a9560a and a9547a );
a2a <=( a9536a and a9523a );
a3a <=( a9512a and a9499a );
a4a <=( a9488a and a9475a );
a5a <=( a9464a and a9451a );
a6a <=( a9440a and a9427a );
a7a <=( a9416a and a9403a );
a8a <=( a9392a and a9379a );
a9a <=( a9368a and a9357a );
a10a <=( a9346a and a9335a );
a11a <=( a9324a and a9313a );
a12a <=( a9302a and a9291a );
a13a <=( a9280a and a9269a );
a14a <=( a9258a and a9247a );
a15a <=( a9236a and a9225a );
a16a <=( a9214a and a9203a );
a17a <=( a9192a and a9181a );
a18a <=( a9170a and a9159a );
a19a <=( a9148a and a9137a );
a20a <=( a9126a and a9115a );
a21a <=( a9104a and a9093a );
a22a <=( a9082a and a9071a );
a23a <=( a9060a and a9049a );
a24a <=( a9038a and a9027a );
a25a <=( a9016a and a9005a );
a26a <=( a8994a and a8983a );
a27a <=( a8972a and a8961a );
a28a <=( a8950a and a8939a );
a29a <=( a8928a and a8917a );
a30a <=( a8906a and a8895a );
a31a <=( a8884a and a8873a );
a32a <=( a8862a and a8851a );
a33a <=( a8840a and a8829a );
a34a <=( a8818a and a8807a );
a35a <=( a8796a and a8785a );
a36a <=( a8774a and a8763a );
a37a <=( a8752a and a8741a );
a38a <=( a8730a and a8719a );
a39a <=( a8708a and a8697a );
a40a <=( a8686a and a8675a );
a41a <=( a8664a and a8653a );
a42a <=( a8642a and a8631a );
a43a <=( a8620a and a8609a );
a44a <=( a8598a and a8587a );
a45a <=( a8576a and a8565a );
a46a <=( a8554a and a8543a );
a47a <=( a8532a and a8521a );
a48a <=( a8510a and a8499a );
a49a <=( a8488a and a8477a );
a50a <=( a8466a and a8455a );
a51a <=( a8444a and a8433a );
a52a <=( a8422a and a8411a );
a53a <=( a8400a and a8389a );
a54a <=( a8378a and a8367a );
a55a <=( a8356a and a8345a );
a56a <=( a8334a and a8323a );
a57a <=( a8312a and a8301a );
a58a <=( a8290a and a8279a );
a59a <=( a8268a and a8257a );
a60a <=( a8246a and a8235a );
a61a <=( a8224a and a8213a );
a62a <=( a8202a and a8191a );
a63a <=( a8180a and a8169a );
a64a <=( a8158a and a8147a );
a65a <=( a8136a and a8125a );
a66a <=( a8114a and a8103a );
a67a <=( a8092a and a8081a );
a68a <=( a8070a and a8059a );
a69a <=( a8048a and a8037a );
a70a <=( a8026a and a8015a );
a71a <=( a8004a and a7993a );
a72a <=( a7982a and a7971a );
a73a <=( a7960a and a7949a );
a74a <=( a7940a and a7929a );
a75a <=( a7920a and a7909a );
a76a <=( a7900a and a7889a );
a77a <=( a7880a and a7869a );
a78a <=( a7860a and a7849a );
a79a <=( a7840a and a7829a );
a80a <=( a7820a and a7809a );
a81a <=( a7800a and a7789a );
a82a <=( a7780a and a7769a );
a83a <=( a7760a and a7749a );
a84a <=( a7740a and a7729a );
a85a <=( a7720a and a7709a );
a86a <=( a7700a and a7689a );
a87a <=( a7680a and a7669a );
a88a <=( a7660a and a7649a );
a89a <=( a7640a and a7629a );
a90a <=( a7620a and a7609a );
a91a <=( a7600a and a7589a );
a92a <=( a7580a and a7569a );
a93a <=( a7560a and a7549a );
a94a <=( a7540a and a7529a );
a95a <=( a7520a and a7509a );
a96a <=( a7500a and a7489a );
a97a <=( a7480a and a7469a );
a98a <=( a7460a and a7449a );
a99a <=( a7440a and a7429a );
a100a <=( a7420a and a7409a );
a101a <=( a7400a and a7389a );
a102a <=( a7380a and a7369a );
a103a <=( a7360a and a7349a );
a104a <=( a7340a and a7329a );
a105a <=( a7320a and a7309a );
a106a <=( a7300a and a7289a );
a107a <=( a7280a and a7269a );
a108a <=( a7260a and a7249a );
a109a <=( a7240a and a7229a );
a110a <=( a7220a and a7209a );
a111a <=( a7200a and a7189a );
a112a <=( a7180a and a7169a );
a113a <=( a7160a and a7149a );
a114a <=( a7140a and a7129a );
a115a <=( a7120a and a7109a );
a116a <=( a7100a and a7089a );
a117a <=( a7080a and a7069a );
a118a <=( a7060a and a7049a );
a119a <=( a7040a and a7029a );
a120a <=( a7020a and a7009a );
a121a <=( a7000a and a6989a );
a122a <=( a6980a and a6969a );
a123a <=( a6960a and a6949a );
a124a <=( a6940a and a6929a );
a125a <=( a6920a and a6909a );
a126a <=( a6900a and a6889a );
a127a <=( a6880a and a6869a );
a128a <=( a6860a and a6849a );
a129a <=( a6840a and a6829a );
a130a <=( a6820a and a6809a );
a131a <=( a6800a and a6789a );
a132a <=( a6780a and a6769a );
a133a <=( a6760a and a6749a );
a134a <=( a6740a and a6729a );
a135a <=( a6720a and a6709a );
a136a <=( a6700a and a6689a );
a137a <=( a6680a and a6669a );
a138a <=( a6660a and a6649a );
a139a <=( a6640a and a6629a );
a140a <=( a6620a and a6609a );
a141a <=( a6600a and a6589a );
a142a <=( a6580a and a6569a );
a143a <=( a6560a and a6549a );
a144a <=( a6540a and a6529a );
a145a <=( a6520a and a6509a );
a146a <=( a6500a and a6489a );
a147a <=( a6480a and a6469a );
a148a <=( a6460a and a6449a );
a149a <=( a6440a and a6429a );
a150a <=( a6420a and a6409a );
a151a <=( a6400a and a6389a );
a152a <=( a6380a and a6369a );
a153a <=( a6360a and a6349a );
a154a <=( a6340a and a6329a );
a155a <=( a6320a and a6309a );
a156a <=( a6300a and a6289a );
a157a <=( a6280a and a6269a );
a158a <=( a6260a and a6249a );
a159a <=( a6240a and a6229a );
a160a <=( a6220a and a6209a );
a161a <=( a6200a and a6189a );
a162a <=( a6180a and a6169a );
a163a <=( a6160a and a6149a );
a164a <=( a6140a and a6129a );
a165a <=( a6120a and a6109a );
a166a <=( a6100a and a6089a );
a167a <=( a6080a and a6069a );
a168a <=( a6060a and a6049a );
a169a <=( a6040a and a6029a );
a170a <=( a6020a and a6009a );
a171a <=( a6000a and a5989a );
a172a <=( a5980a and a5969a );
a173a <=( a5960a and a5949a );
a174a <=( a5940a and a5929a );
a175a <=( a5920a and a5909a );
a176a <=( a5900a and a5889a );
a177a <=( a5880a and a5869a );
a178a <=( a5860a and a5849a );
a179a <=( a5840a and a5829a );
a180a <=( a5820a and a5809a );
a181a <=( a5800a and a5789a );
a182a <=( a5780a and a5769a );
a183a <=( a5760a and a5749a );
a184a <=( a5740a and a5729a );
a185a <=( a5720a and a5709a );
a186a <=( a5700a and a5689a );
a187a <=( a5680a and a5669a );
a188a <=( a5660a and a5649a );
a189a <=( a5640a and a5629a );
a190a <=( a5620a and a5609a );
a191a <=( a5600a and a5589a );
a192a <=( a5580a and a5569a );
a193a <=( a5560a and a5549a );
a194a <=( a5540a and a5529a );
a195a <=( a5520a and a5509a );
a196a <=( a5500a and a5489a );
a197a <=( a5480a and a5469a );
a198a <=( a5460a and a5449a );
a199a <=( a5440a and a5429a );
a200a <=( a5420a and a5409a );
a201a <=( a5400a and a5389a );
a202a <=( a5380a and a5369a );
a203a <=( a5360a and a5349a );
a204a <=( a5340a and a5329a );
a205a <=( a5320a and a5309a );
a206a <=( a5300a and a5289a );
a207a <=( a5280a and a5269a );
a208a <=( a5260a and a5249a );
a209a <=( a5240a and a5229a );
a210a <=( a5220a and a5209a );
a211a <=( a5200a and a5189a );
a212a <=( a5180a and a5169a );
a213a <=( a5160a and a5149a );
a214a <=( a5140a and a5129a );
a215a <=( a5120a and a5109a );
a216a <=( a5100a and a5089a );
a217a <=( a5080a and a5069a );
a218a <=( a5060a and a5049a );
a219a <=( a5040a and a5029a );
a220a <=( a5020a and a5009a );
a221a <=( a5000a and a4989a );
a222a <=( a4980a and a4969a );
a223a <=( a4960a and a4949a );
a224a <=( a4940a and a4929a );
a225a <=( a4920a and a4909a );
a226a <=( a4900a and a4889a );
a227a <=( a4880a and a4869a );
a228a <=( a4860a and a4849a );
a229a <=( a4840a and a4829a );
a230a <=( a4820a and a4809a );
a231a <=( a4800a and a4789a );
a232a <=( a4780a and a4769a );
a233a <=( a4760a and a4751a );
a234a <=( a4742a and a4733a );
a235a <=( a4724a and a4715a );
a236a <=( a4706a and a4697a );
a237a <=( a4688a and a4679a );
a238a <=( a4670a and a4661a );
a239a <=( a4652a and a4643a );
a240a <=( a4634a and a4625a );
a241a <=( a4616a and a4607a );
a242a <=( a4598a and a4589a );
a243a <=( a4580a and a4571a );
a244a <=( a4562a and a4553a );
a245a <=( a4544a and a4535a );
a246a <=( a4526a and a4517a );
a247a <=( a4508a and a4499a );
a248a <=( a4490a and a4481a );
a249a <=( a4472a and a4463a );
a250a <=( a4454a and a4445a );
a251a <=( a4436a and a4427a );
a252a <=( a4418a and a4409a );
a253a <=( a4400a and a4391a );
a254a <=( a4382a and a4373a );
a255a <=( a4364a and a4355a );
a256a <=( a4346a and a4337a );
a257a <=( a4328a and a4319a );
a258a <=( a4310a and a4301a );
a259a <=( a4292a and a4283a );
a260a <=( a4274a and a4265a );
a261a <=( a4256a and a4247a );
a262a <=( a4238a and a4229a );
a263a <=( a4220a and a4211a );
a264a <=( a4202a and a4193a );
a265a <=( a4184a and a4175a );
a266a <=( a4166a and a4157a );
a267a <=( a4148a and a4139a );
a268a <=( a4130a and a4121a );
a269a <=( a4112a and a4103a );
a270a <=( a4094a and a4085a );
a271a <=( a4076a and a4067a );
a272a <=( a4058a and a4049a );
a273a <=( a4040a and a4031a );
a274a <=( a4022a and a4013a );
a275a <=( a4004a and a3995a );
a276a <=( a3986a and a3977a );
a277a <=( a3968a and a3959a );
a278a <=( a3950a and a3941a );
a279a <=( a3932a and a3923a );
a280a <=( a3914a and a3905a );
a281a <=( a3896a and a3887a );
a282a <=( a3878a and a3869a );
a283a <=( a3860a and a3851a );
a284a <=( a3842a and a3833a );
a285a <=( a3824a and a3815a );
a286a <=( a3806a and a3797a );
a287a <=( a3788a and a3779a );
a288a <=( a3770a and a3761a );
a289a <=( a3752a and a3743a );
a290a <=( a3734a and a3725a );
a291a <=( a3716a and a3707a );
a292a <=( a3698a and a3689a );
a293a <=( a3680a and a3671a );
a294a <=( a3662a and a3653a );
a295a <=( a3644a and a3635a );
a296a <=( a3626a and a3617a );
a297a <=( a3608a and a3599a );
a298a <=( a3590a and a3581a );
a299a <=( a3572a and a3563a );
a300a <=( a3554a and a3545a );
a301a <=( a3536a and a3527a );
a302a <=( a3518a and a3509a );
a303a <=( a3500a and a3491a );
a304a <=( a3482a and a3473a );
a305a <=( a3464a and a3455a );
a306a <=( a3446a and a3437a );
a307a <=( a3428a and a3419a );
a308a <=( a3410a and a3401a );
a309a <=( a3392a and a3383a );
a310a <=( a3374a and a3365a );
a311a <=( a3356a and a3347a );
a312a <=( a3338a and a3329a );
a313a <=( a3320a and a3311a );
a314a <=( a3302a and a3293a );
a315a <=( a3284a and a3275a );
a316a <=( a3266a and a3257a );
a317a <=( a3248a and a3239a );
a318a <=( a3230a and a3221a );
a319a <=( a3212a and a3203a );
a320a <=( a3194a and a3185a );
a321a <=( a3176a and a3167a );
a322a <=( a3158a and a3149a );
a323a <=( a3140a and a3131a );
a324a <=( a3122a and a3113a );
a325a <=( a3104a and a3095a );
a326a <=( a3086a and a3077a );
a327a <=( a3068a and a3059a );
a328a <=( a3050a and a3041a );
a329a <=( a3032a and a3023a );
a330a <=( a3014a and a3005a );
a331a <=( a2996a and a2987a );
a332a <=( a2978a and a2969a );
a333a <=( a2960a and a2951a );
a334a <=( a2942a and a2933a );
a335a <=( a2924a and a2915a );
a336a <=( a2906a and a2897a );
a337a <=( a2888a and a2879a );
a338a <=( a2870a and a2861a );
a339a <=( a2852a and a2843a );
a340a <=( a2834a and a2825a );
a341a <=( a2816a and a2807a );
a342a <=( a2798a and a2789a );
a343a <=( a2780a and a2771a );
a344a <=( a2762a and a2753a );
a345a <=( a2744a and a2735a );
a346a <=( a2726a and a2717a );
a347a <=( a2708a and a2699a );
a348a <=( a2690a and a2681a );
a349a <=( a2672a and a2663a );
a350a <=( a2654a and a2645a );
a351a <=( a2636a and a2627a );
a352a <=( a2618a and a2609a );
a353a <=( a2600a and a2591a );
a354a <=( a2582a and a2573a );
a355a <=( a2564a and a2555a );
a356a <=( a2546a and a2537a );
a357a <=( a2528a and a2519a );
a358a <=( a2510a and a2501a );
a359a <=( a2492a and a2483a );
a360a <=( a2474a and a2465a );
a361a <=( a2456a and a2447a );
a362a <=( a2438a and a2429a );
a363a <=( a2420a and a2411a );
a364a <=( a2402a and a2393a );
a365a <=( a2384a and a2375a );
a366a <=( a2366a and a2357a );
a367a <=( a2348a and a2339a );
a368a <=( a2330a and a2321a );
a369a <=( a2312a and a2303a );
a370a <=( a2296a and a2287a );
a371a <=( a2280a and a2271a );
a372a <=( a2264a and a2255a );
a373a <=( a2248a and a2239a );
a374a <=( a2232a and a2223a );
a375a <=( a2216a and a2207a );
a376a <=( a2200a and a2191a );
a377a <=( a2184a and a2175a );
a378a <=( a2168a and a2159a );
a379a <=( a2152a and a2143a );
a380a <=( a2136a and a2127a );
a381a <=( a2120a and a2111a );
a382a <=( a2104a and a2095a );
a383a <=( a2088a and a2079a );
a384a <=( a2072a and a2063a );
a385a <=( a2056a and a2047a );
a386a <=( a2040a and a2031a );
a387a <=( a2024a and a2015a );
a388a <=( a2008a and a1999a );
a389a <=( a1992a and a1983a );
a390a <=( a1976a and a1967a );
a391a <=( a1960a and a1951a );
a392a <=( a1944a and a1935a );
a393a <=( a1928a and a1919a );
a394a <=( a1912a and a1903a );
a395a <=( a1896a and a1887a );
a396a <=( a1880a and a1871a );
a397a <=( a1864a and a1855a );
a398a <=( a1848a and a1839a );
a399a <=( a1832a and a1823a );
a400a <=( a1816a and a1807a );
a401a <=( a1800a and a1793a );
a402a <=( a1786a and a1779a );
a403a <=( a1772a and a1765a );
a404a <=( a1758a and a1751a );
a405a <=( a1744a and a1737a );
a406a <=( a1730a and a1723a );
a407a <=( a1716a and a1709a );
a408a <=( a1702a and a1695a );
a409a <=( a1688a and a1681a );
a410a <=( a1674a and a1667a );
a411a <=( a1660a and a1653a );
a412a <=( a1646a and a1639a );
a413a <=( a1632a and a1625a );
a414a <=( a1618a and a1611a );
a415a <=( a1604a and a1597a );
a416a <=( a1590a and a1583a );
a417a <=( a1576a and a1569a );
a418a <=( a1562a and a1555a );
a419a <=( a1548a and a1541a );
a420a <=( a1534a and a1527a );
a421a <=( a1520a and a1513a );
a422a <=( a1506a and a1499a );
a423a <=( a1492a and a1485a );
a424a <=( a1478a and a1471a );
a425a <=( a1464a and a1457a );
a426a <=( a1450a and a1443a );
a427a <=( a1436a and a1429a );
a428a <=( a1422a and a1415a );
a429a <=( a1408a and a1401a );
a430a <=( a1394a and a1387a );
a431a <=( a1380a and a1373a );
a432a <=( a1366a and a1359a );
a433a <=( a1352a and a1347a );
a434a <=( a1344a and a1339a );
a435a <=( a1336a and a1333a );
a436a <=( a1330a and a1327a );
a437a <=( a1324a and a1321a );
a438a <=( a1318a and a1315a );
a442a <=( a436a ) or ( a437a );
a443a <=( a438a ) or ( a442a );
a447a <=( a433a ) or ( a434a );
a448a <=( a435a ) or ( a447a );
a449a <=( a448a ) or ( a443a );
a453a <=( a430a ) or ( a431a );
a454a <=( a432a ) or ( a453a );
a457a <=( a428a ) or ( a429a );
a460a <=( a426a ) or ( a427a );
a461a <=( a460a ) or ( a457a );
a462a <=( a461a ) or ( a454a );
a463a <=( a462a ) or ( a449a );
a467a <=( a423a ) or ( a424a );
a468a <=( a425a ) or ( a467a );
a471a <=( a421a ) or ( a422a );
a474a <=( a419a ) or ( a420a );
a475a <=( a474a ) or ( a471a );
a476a <=( a475a ) or ( a468a );
a480a <=( a416a ) or ( a417a );
a481a <=( a418a ) or ( a480a );
a484a <=( a414a ) or ( a415a );
a487a <=( a412a ) or ( a413a );
a488a <=( a487a ) or ( a484a );
a489a <=( a488a ) or ( a481a );
a490a <=( a489a ) or ( a476a );
a491a <=( a490a ) or ( a463a );
a495a <=( a409a ) or ( a410a );
a496a <=( a411a ) or ( a495a );
a500a <=( a406a ) or ( a407a );
a501a <=( a408a ) or ( a500a );
a502a <=( a501a ) or ( a496a );
a506a <=( a403a ) or ( a404a );
a507a <=( a405a ) or ( a506a );
a510a <=( a401a ) or ( a402a );
a513a <=( a399a ) or ( a400a );
a514a <=( a513a ) or ( a510a );
a515a <=( a514a ) or ( a507a );
a516a <=( a515a ) or ( a502a );
a520a <=( a396a ) or ( a397a );
a521a <=( a398a ) or ( a520a );
a524a <=( a394a ) or ( a395a );
a527a <=( a392a ) or ( a393a );
a528a <=( a527a ) or ( a524a );
a529a <=( a528a ) or ( a521a );
a533a <=( a389a ) or ( a390a );
a534a <=( a391a ) or ( a533a );
a537a <=( a387a ) or ( a388a );
a540a <=( a385a ) or ( a386a );
a541a <=( a540a ) or ( a537a );
a542a <=( a541a ) or ( a534a );
a543a <=( a542a ) or ( a529a );
a544a <=( a543a ) or ( a516a );
a545a <=( a544a ) or ( a491a );
a549a <=( a382a ) or ( a383a );
a550a <=( a384a ) or ( a549a );
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a555a <=( a381a ) or ( a554a );
a556a <=( a555a ) or ( a550a );
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a564a <=( a374a ) or ( a375a );
a567a <=( a372a ) or ( a373a );
a568a <=( a567a ) or ( a564a );
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a575a <=( a371a ) or ( a574a );
a578a <=( a367a ) or ( a368a );
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a582a <=( a581a ) or ( a578a );
a583a <=( a582a ) or ( a575a );
a587a <=( a362a ) or ( a363a );
a588a <=( a364a ) or ( a587a );
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a594a <=( a358a ) or ( a359a );
a595a <=( a594a ) or ( a591a );
a596a <=( a595a ) or ( a588a );
a597a <=( a596a ) or ( a583a );
a598a <=( a597a ) or ( a570a );
a602a <=( a355a ) or ( a356a );
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a610a <=( a609a ) or ( a606a );
a611a <=( a610a ) or ( a603a );
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a616a <=( a350a ) or ( a615a );
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a624a <=( a623a ) or ( a616a );
a625a <=( a624a ) or ( a611a );
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a630a <=( a343a ) or ( a629a );
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a636a <=( a337a ) or ( a338a );
a637a <=( a636a ) or ( a633a );
a638a <=( a637a ) or ( a630a );
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a643a <=( a336a ) or ( a642a );
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a650a <=( a649a ) or ( a646a );
a651a <=( a650a ) or ( a643a );
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a653a <=( a652a ) or ( a625a );
a654a <=( a653a ) or ( a598a );
a655a <=( a654a ) or ( a545a );
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a660a <=( a329a ) or ( a659a );
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a665a <=( a326a ) or ( a664a );
a666a <=( a665a ) or ( a660a );
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a671a <=( a323a ) or ( a670a );
a674a <=( a319a ) or ( a320a );
a677a <=( a317a ) or ( a318a );
a678a <=( a677a ) or ( a674a );
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a680a <=( a679a ) or ( a666a );
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a685a <=( a316a ) or ( a684a );
a688a <=( a312a ) or ( a313a );
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a692a <=( a691a ) or ( a688a );
a693a <=( a692a ) or ( a685a );
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a698a <=( a309a ) or ( a697a );
a701a <=( a305a ) or ( a306a );
a704a <=( a303a ) or ( a304a );
a705a <=( a704a ) or ( a701a );
a706a <=( a705a ) or ( a698a );
a707a <=( a706a ) or ( a693a );
a708a <=( a707a ) or ( a680a );
a712a <=( a300a ) or ( a301a );
a713a <=( a302a ) or ( a712a );
a716a <=( a298a ) or ( a299a );
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a720a <=( a719a ) or ( a716a );
a721a <=( a720a ) or ( a713a );
a725a <=( a293a ) or ( a294a );
a726a <=( a295a ) or ( a725a );
a729a <=( a291a ) or ( a292a );
a732a <=( a289a ) or ( a290a );
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a734a <=( a733a ) or ( a726a );
a735a <=( a734a ) or ( a721a );
a739a <=( a286a ) or ( a287a );
a740a <=( a288a ) or ( a739a );
a743a <=( a284a ) or ( a285a );
a746a <=( a282a ) or ( a283a );
a747a <=( a746a ) or ( a743a );
a748a <=( a747a ) or ( a740a );
a752a <=( a279a ) or ( a280a );
a753a <=( a281a ) or ( a752a );
a756a <=( a277a ) or ( a278a );
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a760a <=( a759a ) or ( a756a );
a761a <=( a760a ) or ( a753a );
a762a <=( a761a ) or ( a748a );
a763a <=( a762a ) or ( a735a );
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a768a <=( a272a ) or ( a273a );
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a773a <=( a269a ) or ( a270a );
a774a <=( a271a ) or ( a773a );
a775a <=( a774a ) or ( a769a );
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a780a <=( a268a ) or ( a779a );
a783a <=( a264a ) or ( a265a );
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a787a <=( a786a ) or ( a783a );
a788a <=( a787a ) or ( a780a );
a789a <=( a788a ) or ( a775a );
a793a <=( a259a ) or ( a260a );
a794a <=( a261a ) or ( a793a );
a797a <=( a257a ) or ( a258a );
a800a <=( a255a ) or ( a256a );
a801a <=( a800a ) or ( a797a );
a802a <=( a801a ) or ( a794a );
a806a <=( a252a ) or ( a253a );
a807a <=( a254a ) or ( a806a );
a810a <=( a250a ) or ( a251a );
a813a <=( a248a ) or ( a249a );
a814a <=( a813a ) or ( a810a );
a815a <=( a814a ) or ( a807a );
a816a <=( a815a ) or ( a802a );
a817a <=( a816a ) or ( a789a );
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a822a <=( a247a ) or ( a821a );
a825a <=( a243a ) or ( a244a );
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a829a <=( a828a ) or ( a825a );
a830a <=( a829a ) or ( a822a );
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a835a <=( a240a ) or ( a834a );
a838a <=( a236a ) or ( a237a );
a841a <=( a234a ) or ( a235a );
a842a <=( a841a ) or ( a838a );
a843a <=( a842a ) or ( a835a );
a844a <=( a843a ) or ( a830a );
a848a <=( a231a ) or ( a232a );
a849a <=( a233a ) or ( a848a );
a852a <=( a229a ) or ( a230a );
a855a <=( a227a ) or ( a228a );
a856a <=( a855a ) or ( a852a );
a857a <=( a856a ) or ( a849a );
a861a <=( a224a ) or ( a225a );
a862a <=( a226a ) or ( a861a );
a865a <=( a222a ) or ( a223a );
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a869a <=( a868a ) or ( a865a );
a870a <=( a869a ) or ( a862a );
a871a <=( a870a ) or ( a857a );
a872a <=( a871a ) or ( a844a );
a873a <=( a872a ) or ( a817a );
a874a <=( a873a ) or ( a764a );
a875a <=( a874a ) or ( a655a );
a879a <=( a217a ) or ( a218a );
a880a <=( a219a ) or ( a879a );
a884a <=( a214a ) or ( a215a );
a885a <=( a216a ) or ( a884a );
a886a <=( a885a ) or ( a880a );
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a891a <=( a213a ) or ( a890a );
a894a <=( a209a ) or ( a210a );
a897a <=( a207a ) or ( a208a );
a898a <=( a897a ) or ( a894a );
a899a <=( a898a ) or ( a891a );
a900a <=( a899a ) or ( a886a );
a904a <=( a204a ) or ( a205a );
a905a <=( a206a ) or ( a904a );
a908a <=( a202a ) or ( a203a );
a911a <=( a200a ) or ( a201a );
a912a <=( a911a ) or ( a908a );
a913a <=( a912a ) or ( a905a );
a917a <=( a197a ) or ( a198a );
a918a <=( a199a ) or ( a917a );
a921a <=( a195a ) or ( a196a );
a924a <=( a193a ) or ( a194a );
a925a <=( a924a ) or ( a921a );
a926a <=( a925a ) or ( a918a );
a927a <=( a926a ) or ( a913a );
a928a <=( a927a ) or ( a900a );
a932a <=( a190a ) or ( a191a );
a933a <=( a192a ) or ( a932a );
a937a <=( a187a ) or ( a188a );
a938a <=( a189a ) or ( a937a );
a939a <=( a938a ) or ( a933a );
a943a <=( a184a ) or ( a185a );
a944a <=( a186a ) or ( a943a );
a947a <=( a182a ) or ( a183a );
a950a <=( a180a ) or ( a181a );
a951a <=( a950a ) or ( a947a );
a952a <=( a951a ) or ( a944a );
a953a <=( a952a ) or ( a939a );
a957a <=( a177a ) or ( a178a );
a958a <=( a179a ) or ( a957a );
a961a <=( a175a ) or ( a176a );
a964a <=( a173a ) or ( a174a );
a965a <=( a964a ) or ( a961a );
a966a <=( a965a ) or ( a958a );
a970a <=( a170a ) or ( a171a );
a971a <=( a172a ) or ( a970a );
a974a <=( a168a ) or ( a169a );
a977a <=( a166a ) or ( a167a );
a978a <=( a977a ) or ( a974a );
a979a <=( a978a ) or ( a971a );
a980a <=( a979a ) or ( a966a );
a981a <=( a980a ) or ( a953a );
a982a <=( a981a ) or ( a928a );
a986a <=( a163a ) or ( a164a );
a987a <=( a165a ) or ( a986a );
a991a <=( a160a ) or ( a161a );
a992a <=( a162a ) or ( a991a );
a993a <=( a992a ) or ( a987a );
a997a <=( a157a ) or ( a158a );
a998a <=( a159a ) or ( a997a );
a1001a <=( a155a ) or ( a156a );
a1004a <=( a153a ) or ( a154a );
a1005a <=( a1004a ) or ( a1001a );
a1006a <=( a1005a ) or ( a998a );
a1007a <=( a1006a ) or ( a993a );
a1011a <=( a150a ) or ( a151a );
a1012a <=( a152a ) or ( a1011a );
a1015a <=( a148a ) or ( a149a );
a1018a <=( a146a ) or ( a147a );
a1019a <=( a1018a ) or ( a1015a );
a1020a <=( a1019a ) or ( a1012a );
a1024a <=( a143a ) or ( a144a );
a1025a <=( a145a ) or ( a1024a );
a1028a <=( a141a ) or ( a142a );
a1031a <=( a139a ) or ( a140a );
a1032a <=( a1031a ) or ( a1028a );
a1033a <=( a1032a ) or ( a1025a );
a1034a <=( a1033a ) or ( a1020a );
a1035a <=( a1034a ) or ( a1007a );
a1039a <=( a136a ) or ( a137a );
a1040a <=( a138a ) or ( a1039a );
a1043a <=( a134a ) or ( a135a );
a1046a <=( a132a ) or ( a133a );
a1047a <=( a1046a ) or ( a1043a );
a1048a <=( a1047a ) or ( a1040a );
a1052a <=( a129a ) or ( a130a );
a1053a <=( a131a ) or ( a1052a );
a1056a <=( a127a ) or ( a128a );
a1059a <=( a125a ) or ( a126a );
a1060a <=( a1059a ) or ( a1056a );
a1061a <=( a1060a ) or ( a1053a );
a1062a <=( a1061a ) or ( a1048a );
a1066a <=( a122a ) or ( a123a );
a1067a <=( a124a ) or ( a1066a );
a1070a <=( a120a ) or ( a121a );
a1073a <=( a118a ) or ( a119a );
a1074a <=( a1073a ) or ( a1070a );
a1075a <=( a1074a ) or ( a1067a );
a1079a <=( a115a ) or ( a116a );
a1080a <=( a117a ) or ( a1079a );
a1083a <=( a113a ) or ( a114a );
a1086a <=( a111a ) or ( a112a );
a1087a <=( a1086a ) or ( a1083a );
a1088a <=( a1087a ) or ( a1080a );
a1089a <=( a1088a ) or ( a1075a );
a1090a <=( a1089a ) or ( a1062a );
a1091a <=( a1090a ) or ( a1035a );
a1092a <=( a1091a ) or ( a982a );
a1096a <=( a108a ) or ( a109a );
a1097a <=( a110a ) or ( a1096a );
a1101a <=( a105a ) or ( a106a );
a1102a <=( a107a ) or ( a1101a );
a1103a <=( a1102a ) or ( a1097a );
a1107a <=( a102a ) or ( a103a );
a1108a <=( a104a ) or ( a1107a );
a1111a <=( a100a ) or ( a101a );
a1114a <=( a98a ) or ( a99a );
a1115a <=( a1114a ) or ( a1111a );
a1116a <=( a1115a ) or ( a1108a );
a1117a <=( a1116a ) or ( a1103a );
a1121a <=( a95a ) or ( a96a );
a1122a <=( a97a ) or ( a1121a );
a1125a <=( a93a ) or ( a94a );
a1128a <=( a91a ) or ( a92a );
a1129a <=( a1128a ) or ( a1125a );
a1130a <=( a1129a ) or ( a1122a );
a1134a <=( a88a ) or ( a89a );
a1135a <=( a90a ) or ( a1134a );
a1138a <=( a86a ) or ( a87a );
a1141a <=( a84a ) or ( a85a );
a1142a <=( a1141a ) or ( a1138a );
a1143a <=( a1142a ) or ( a1135a );
a1144a <=( a1143a ) or ( a1130a );
a1145a <=( a1144a ) or ( a1117a );
a1149a <=( a81a ) or ( a82a );
a1150a <=( a83a ) or ( a1149a );
a1153a <=( a79a ) or ( a80a );
a1156a <=( a77a ) or ( a78a );
a1157a <=( a1156a ) or ( a1153a );
a1158a <=( a1157a ) or ( a1150a );
a1162a <=( a74a ) or ( a75a );
a1163a <=( a76a ) or ( a1162a );
a1166a <=( a72a ) or ( a73a );
a1169a <=( a70a ) or ( a71a );
a1170a <=( a1169a ) or ( a1166a );
a1171a <=( a1170a ) or ( a1163a );
a1172a <=( a1171a ) or ( a1158a );
a1176a <=( a67a ) or ( a68a );
a1177a <=( a69a ) or ( a1176a );
a1180a <=( a65a ) or ( a66a );
a1183a <=( a63a ) or ( a64a );
a1184a <=( a1183a ) or ( a1180a );
a1185a <=( a1184a ) or ( a1177a );
a1189a <=( a60a ) or ( a61a );
a1190a <=( a62a ) or ( a1189a );
a1193a <=( a58a ) or ( a59a );
a1196a <=( a56a ) or ( a57a );
a1197a <=( a1196a ) or ( a1193a );
a1198a <=( a1197a ) or ( a1190a );
a1199a <=( a1198a ) or ( a1185a );
a1200a <=( a1199a ) or ( a1172a );
a1201a <=( a1200a ) or ( a1145a );
a1205a <=( a53a ) or ( a54a );
a1206a <=( a55a ) or ( a1205a );
a1210a <=( a50a ) or ( a51a );
a1211a <=( a52a ) or ( a1210a );
a1212a <=( a1211a ) or ( a1206a );
a1216a <=( a47a ) or ( a48a );
a1217a <=( a49a ) or ( a1216a );
a1220a <=( a45a ) or ( a46a );
a1223a <=( a43a ) or ( a44a );
a1224a <=( a1223a ) or ( a1220a );
a1225a <=( a1224a ) or ( a1217a );
a1226a <=( a1225a ) or ( a1212a );
a1230a <=( a40a ) or ( a41a );
a1231a <=( a42a ) or ( a1230a );
a1234a <=( a38a ) or ( a39a );
a1237a <=( a36a ) or ( a37a );
a1238a <=( a1237a ) or ( a1234a );
a1239a <=( a1238a ) or ( a1231a );
a1243a <=( a33a ) or ( a34a );
a1244a <=( a35a ) or ( a1243a );
a1247a <=( a31a ) or ( a32a );
a1250a <=( a29a ) or ( a30a );
a1251a <=( a1250a ) or ( a1247a );
a1252a <=( a1251a ) or ( a1244a );
a1253a <=( a1252a ) or ( a1239a );
a1254a <=( a1253a ) or ( a1226a );
a1258a <=( a26a ) or ( a27a );
a1259a <=( a28a ) or ( a1258a );
a1262a <=( a24a ) or ( a25a );
a1265a <=( a22a ) or ( a23a );
a1266a <=( a1265a ) or ( a1262a );
a1267a <=( a1266a ) or ( a1259a );
a1271a <=( a19a ) or ( a20a );
a1272a <=( a21a ) or ( a1271a );
a1275a <=( a17a ) or ( a18a );
a1278a <=( a15a ) or ( a16a );
a1279a <=( a1278a ) or ( a1275a );
a1280a <=( a1279a ) or ( a1272a );
a1281a <=( a1280a ) or ( a1267a );
a1285a <=( a12a ) or ( a13a );
a1286a <=( a14a ) or ( a1285a );
a1289a <=( a10a ) or ( a11a );
a1292a <=( a8a ) or ( a9a );
a1293a <=( a1292a ) or ( a1289a );
a1294a <=( a1293a ) or ( a1286a );
a1298a <=( a5a ) or ( a6a );
a1299a <=( a7a ) or ( a1298a );
a1302a <=( a3a ) or ( a4a );
a1305a <=( a1a ) or ( a2a );
a1306a <=( a1305a ) or ( a1302a );
a1307a <=( a1306a ) or ( a1299a );
a1308a <=( a1307a ) or ( a1294a );
a1309a <=( a1308a ) or ( a1281a );
a1310a <=( a1309a ) or ( a1254a );
a1311a <=( a1310a ) or ( a1201a );
a1312a <=( a1311a ) or ( a1092a );
a1315a <=( A266 and (not A265) );
a1318a <=( A268 and A267 );
a1321a <=( A266 and (not A265) );
a1324a <=( A269 and A267 );
a1327a <=( (not A266) and A265 );
a1330a <=( A268 and A267 );
a1333a <=( (not A266) and A265 );
a1336a <=( A269 and A267 );
a1339a <=( A266 and (not A265) );
a1343a <=( (not A269) and (not A268) );
a1344a <=( (not A267) and a1343a );
a1347a <=( (not A266) and A265 );
a1351a <=( (not A269) and (not A268) );
a1352a <=( (not A267) and a1351a );
a1355a <=( A200 and (not A199) );
a1358a <=( A202 and A201 );
a1359a <=( a1358a and a1355a );
a1362a <=( A233 and (not A232) );
a1365a <=( A235 and A234 );
a1366a <=( a1365a and a1362a );
a1369a <=( A200 and (not A199) );
a1372a <=( A202 and A201 );
a1373a <=( a1372a and a1369a );
a1376a <=( A233 and (not A232) );
a1379a <=( A236 and A234 );
a1380a <=( a1379a and a1376a );
a1383a <=( A200 and (not A199) );
a1386a <=( A202 and A201 );
a1387a <=( a1386a and a1383a );
a1390a <=( (not A233) and A232 );
a1393a <=( A235 and A234 );
a1394a <=( a1393a and a1390a );
a1397a <=( A200 and (not A199) );
a1400a <=( A202 and A201 );
a1401a <=( a1400a and a1397a );
a1404a <=( (not A233) and A232 );
a1407a <=( A236 and A234 );
a1408a <=( a1407a and a1404a );
a1411a <=( A200 and (not A199) );
a1414a <=( A203 and A201 );
a1415a <=( a1414a and a1411a );
a1418a <=( A233 and (not A232) );
a1421a <=( A235 and A234 );
a1422a <=( a1421a and a1418a );
a1425a <=( A200 and (not A199) );
a1428a <=( A203 and A201 );
a1429a <=( a1428a and a1425a );
a1432a <=( A233 and (not A232) );
a1435a <=( A236 and A234 );
a1436a <=( a1435a and a1432a );
a1439a <=( A200 and (not A199) );
a1442a <=( A203 and A201 );
a1443a <=( a1442a and a1439a );
a1446a <=( (not A233) and A232 );
a1449a <=( A235 and A234 );
a1450a <=( a1449a and a1446a );
a1453a <=( A200 and (not A199) );
a1456a <=( A203 and A201 );
a1457a <=( a1456a and a1453a );
a1460a <=( (not A233) and A232 );
a1463a <=( A236 and A234 );
a1464a <=( a1463a and a1460a );
a1467a <=( (not A200) and A199 );
a1470a <=( A202 and A201 );
a1471a <=( a1470a and a1467a );
a1474a <=( A233 and (not A232) );
a1477a <=( A235 and A234 );
a1478a <=( a1477a and a1474a );
a1481a <=( (not A200) and A199 );
a1484a <=( A202 and A201 );
a1485a <=( a1484a and a1481a );
a1488a <=( A233 and (not A232) );
a1491a <=( A236 and A234 );
a1492a <=( a1491a and a1488a );
a1495a <=( (not A200) and A199 );
a1498a <=( A202 and A201 );
a1499a <=( a1498a and a1495a );
a1502a <=( (not A233) and A232 );
a1505a <=( A235 and A234 );
a1506a <=( a1505a and a1502a );
a1509a <=( (not A200) and A199 );
a1512a <=( A202 and A201 );
a1513a <=( a1512a and a1509a );
a1516a <=( (not A233) and A232 );
a1519a <=( A236 and A234 );
a1520a <=( a1519a and a1516a );
a1523a <=( (not A200) and A199 );
a1526a <=( A203 and A201 );
a1527a <=( a1526a and a1523a );
a1530a <=( A233 and (not A232) );
a1533a <=( A235 and A234 );
a1534a <=( a1533a and a1530a );
a1537a <=( (not A200) and A199 );
a1540a <=( A203 and A201 );
a1541a <=( a1540a and a1537a );
a1544a <=( A233 and (not A232) );
a1547a <=( A236 and A234 );
a1548a <=( a1547a and a1544a );
a1551a <=( (not A200) and A199 );
a1554a <=( A203 and A201 );
a1555a <=( a1554a and a1551a );
a1558a <=( (not A233) and A232 );
a1561a <=( A235 and A234 );
a1562a <=( a1561a and a1558a );
a1565a <=( (not A200) and A199 );
a1568a <=( A203 and A201 );
a1569a <=( a1568a and a1565a );
a1572a <=( (not A233) and A232 );
a1575a <=( A236 and A234 );
a1576a <=( a1575a and a1572a );
a1579a <=( A168 and (not A170) );
a1582a <=( (not A166) and A167 );
a1583a <=( a1582a and a1579a );
a1586a <=( A233 and (not A232) );
a1589a <=( A235 and A234 );
a1590a <=( a1589a and a1586a );
a1593a <=( A168 and (not A170) );
a1596a <=( (not A166) and A167 );
a1597a <=( a1596a and a1593a );
a1600a <=( A233 and (not A232) );
a1603a <=( A236 and A234 );
a1604a <=( a1603a and a1600a );
a1607a <=( A168 and (not A170) );
a1610a <=( (not A166) and A167 );
a1611a <=( a1610a and a1607a );
a1614a <=( (not A233) and A232 );
a1617a <=( A235 and A234 );
a1618a <=( a1617a and a1614a );
a1621a <=( A168 and (not A170) );
a1624a <=( (not A166) and A167 );
a1625a <=( a1624a and a1621a );
a1628a <=( (not A233) and A232 );
a1631a <=( A236 and A234 );
a1632a <=( a1631a and a1628a );
a1635a <=( A168 and (not A170) );
a1638a <=( A166 and (not A167) );
a1639a <=( a1638a and a1635a );
a1642a <=( A233 and (not A232) );
a1645a <=( A235 and A234 );
a1646a <=( a1645a and a1642a );
a1649a <=( A168 and (not A170) );
a1652a <=( A166 and (not A167) );
a1653a <=( a1652a and a1649a );
a1656a <=( A233 and (not A232) );
a1659a <=( A236 and A234 );
a1660a <=( a1659a and a1656a );
a1663a <=( A168 and (not A170) );
a1666a <=( A166 and (not A167) );
a1667a <=( a1666a and a1663a );
a1670a <=( (not A233) and A232 );
a1673a <=( A235 and A234 );
a1674a <=( a1673a and a1670a );
a1677a <=( A168 and (not A170) );
a1680a <=( A166 and (not A167) );
a1681a <=( a1680a and a1677a );
a1684a <=( (not A233) and A232 );
a1687a <=( A236 and A234 );
a1688a <=( a1687a and a1684a );
a1691a <=( A168 and A169 );
a1694a <=( (not A166) and A167 );
a1695a <=( a1694a and a1691a );
a1698a <=( A233 and (not A232) );
a1701a <=( A235 and A234 );
a1702a <=( a1701a and a1698a );
a1705a <=( A168 and A169 );
a1708a <=( (not A166) and A167 );
a1709a <=( a1708a and a1705a );
a1712a <=( A233 and (not A232) );
a1715a <=( A236 and A234 );
a1716a <=( a1715a and a1712a );
a1719a <=( A168 and A169 );
a1722a <=( (not A166) and A167 );
a1723a <=( a1722a and a1719a );
a1726a <=( (not A233) and A232 );
a1729a <=( A235 and A234 );
a1730a <=( a1729a and a1726a );
a1733a <=( A168 and A169 );
a1736a <=( (not A166) and A167 );
a1737a <=( a1736a and a1733a );
a1740a <=( (not A233) and A232 );
a1743a <=( A236 and A234 );
a1744a <=( a1743a and a1740a );
a1747a <=( A168 and A169 );
a1750a <=( A166 and (not A167) );
a1751a <=( a1750a and a1747a );
a1754a <=( A233 and (not A232) );
a1757a <=( A235 and A234 );
a1758a <=( a1757a and a1754a );
a1761a <=( A168 and A169 );
a1764a <=( A166 and (not A167) );
a1765a <=( a1764a and a1761a );
a1768a <=( A233 and (not A232) );
a1771a <=( A236 and A234 );
a1772a <=( a1771a and a1768a );
a1775a <=( A168 and A169 );
a1778a <=( A166 and (not A167) );
a1779a <=( a1778a and a1775a );
a1782a <=( (not A233) and A232 );
a1785a <=( A235 and A234 );
a1786a <=( a1785a and a1782a );
a1789a <=( A168 and A169 );
a1792a <=( A166 and (not A167) );
a1793a <=( a1792a and a1789a );
a1796a <=( (not A233) and A232 );
a1799a <=( A236 and A234 );
a1800a <=( a1799a and a1796a );
a1803a <=( A200 and (not A199) );
a1806a <=( A202 and A201 );
a1807a <=( a1806a and a1803a );
a1810a <=( A233 and (not A232) );
a1814a <=( (not A236) and (not A235) );
a1815a <=( (not A234) and a1814a );
a1816a <=( a1815a and a1810a );
a1819a <=( A200 and (not A199) );
a1822a <=( A202 and A201 );
a1823a <=( a1822a and a1819a );
a1826a <=( (not A233) and A232 );
a1830a <=( (not A236) and (not A235) );
a1831a <=( (not A234) and a1830a );
a1832a <=( a1831a and a1826a );
a1835a <=( A200 and (not A199) );
a1838a <=( A203 and A201 );
a1839a <=( a1838a and a1835a );
a1842a <=( A233 and (not A232) );
a1846a <=( (not A236) and (not A235) );
a1847a <=( (not A234) and a1846a );
a1848a <=( a1847a and a1842a );
a1851a <=( A200 and (not A199) );
a1854a <=( A203 and A201 );
a1855a <=( a1854a and a1851a );
a1858a <=( (not A233) and A232 );
a1862a <=( (not A236) and (not A235) );
a1863a <=( (not A234) and a1862a );
a1864a <=( a1863a and a1858a );
a1867a <=( A200 and (not A199) );
a1870a <=( (not A202) and (not A201) );
a1871a <=( a1870a and a1867a );
a1874a <=( (not A232) and (not A203) );
a1878a <=( A235 and A234 );
a1879a <=( A233 and a1878a );
a1880a <=( a1879a and a1874a );
a1883a <=( A200 and (not A199) );
a1886a <=( (not A202) and (not A201) );
a1887a <=( a1886a and a1883a );
a1890a <=( (not A232) and (not A203) );
a1894a <=( A236 and A234 );
a1895a <=( A233 and a1894a );
a1896a <=( a1895a and a1890a );
a1899a <=( A200 and (not A199) );
a1902a <=( (not A202) and (not A201) );
a1903a <=( a1902a and a1899a );
a1906a <=( A232 and (not A203) );
a1910a <=( A235 and A234 );
a1911a <=( (not A233) and a1910a );
a1912a <=( a1911a and a1906a );
a1915a <=( A200 and (not A199) );
a1918a <=( (not A202) and (not A201) );
a1919a <=( a1918a and a1915a );
a1922a <=( A232 and (not A203) );
a1926a <=( A236 and A234 );
a1927a <=( (not A233) and a1926a );
a1928a <=( a1927a and a1922a );
a1931a <=( (not A200) and A199 );
a1934a <=( A202 and A201 );
a1935a <=( a1934a and a1931a );
a1938a <=( A233 and (not A232) );
a1942a <=( (not A236) and (not A235) );
a1943a <=( (not A234) and a1942a );
a1944a <=( a1943a and a1938a );
a1947a <=( (not A200) and A199 );
a1950a <=( A202 and A201 );
a1951a <=( a1950a and a1947a );
a1954a <=( (not A233) and A232 );
a1958a <=( (not A236) and (not A235) );
a1959a <=( (not A234) and a1958a );
a1960a <=( a1959a and a1954a );
a1963a <=( (not A200) and A199 );
a1966a <=( A203 and A201 );
a1967a <=( a1966a and a1963a );
a1970a <=( A233 and (not A232) );
a1974a <=( (not A236) and (not A235) );
a1975a <=( (not A234) and a1974a );
a1976a <=( a1975a and a1970a );
a1979a <=( (not A200) and A199 );
a1982a <=( A203 and A201 );
a1983a <=( a1982a and a1979a );
a1986a <=( (not A233) and A232 );
a1990a <=( (not A236) and (not A235) );
a1991a <=( (not A234) and a1990a );
a1992a <=( a1991a and a1986a );
a1995a <=( (not A200) and A199 );
a1998a <=( (not A202) and (not A201) );
a1999a <=( a1998a and a1995a );
a2002a <=( (not A232) and (not A203) );
a2006a <=( A235 and A234 );
a2007a <=( A233 and a2006a );
a2008a <=( a2007a and a2002a );
a2011a <=( (not A200) and A199 );
a2014a <=( (not A202) and (not A201) );
a2015a <=( a2014a and a2011a );
a2018a <=( (not A232) and (not A203) );
a2022a <=( A236 and A234 );
a2023a <=( A233 and a2022a );
a2024a <=( a2023a and a2018a );
a2027a <=( (not A200) and A199 );
a2030a <=( (not A202) and (not A201) );
a2031a <=( a2030a and a2027a );
a2034a <=( A232 and (not A203) );
a2038a <=( A235 and A234 );
a2039a <=( (not A233) and a2038a );
a2040a <=( a2039a and a2034a );
a2043a <=( (not A200) and A199 );
a2046a <=( (not A202) and (not A201) );
a2047a <=( a2046a and a2043a );
a2050a <=( A232 and (not A203) );
a2054a <=( A236 and A234 );
a2055a <=( (not A233) and a2054a );
a2056a <=( a2055a and a2050a );
a2059a <=( A168 and (not A170) );
a2062a <=( (not A166) and A167 );
a2063a <=( a2062a and a2059a );
a2066a <=( A233 and (not A232) );
a2070a <=( (not A236) and (not A235) );
a2071a <=( (not A234) and a2070a );
a2072a <=( a2071a and a2066a );
a2075a <=( A168 and (not A170) );
a2078a <=( (not A166) and A167 );
a2079a <=( a2078a and a2075a );
a2082a <=( (not A233) and A232 );
a2086a <=( (not A236) and (not A235) );
a2087a <=( (not A234) and a2086a );
a2088a <=( a2087a and a2082a );
a2091a <=( A168 and (not A170) );
a2094a <=( A166 and (not A167) );
a2095a <=( a2094a and a2091a );
a2098a <=( A233 and (not A232) );
a2102a <=( (not A236) and (not A235) );
a2103a <=( (not A234) and a2102a );
a2104a <=( a2103a and a2098a );
a2107a <=( A168 and (not A170) );
a2110a <=( A166 and (not A167) );
a2111a <=( a2110a and a2107a );
a2114a <=( (not A233) and A232 );
a2118a <=( (not A236) and (not A235) );
a2119a <=( (not A234) and a2118a );
a2120a <=( a2119a and a2114a );
a2123a <=( A168 and A169 );
a2126a <=( (not A166) and A167 );
a2127a <=( a2126a and a2123a );
a2130a <=( A233 and (not A232) );
a2134a <=( (not A236) and (not A235) );
a2135a <=( (not A234) and a2134a );
a2136a <=( a2135a and a2130a );
a2139a <=( A168 and A169 );
a2142a <=( (not A166) and A167 );
a2143a <=( a2142a and a2139a );
a2146a <=( (not A233) and A232 );
a2150a <=( (not A236) and (not A235) );
a2151a <=( (not A234) and a2150a );
a2152a <=( a2151a and a2146a );
a2155a <=( A168 and A169 );
a2158a <=( A166 and (not A167) );
a2159a <=( a2158a and a2155a );
a2162a <=( A233 and (not A232) );
a2166a <=( (not A236) and (not A235) );
a2167a <=( (not A234) and a2166a );
a2168a <=( a2167a and a2162a );
a2171a <=( A168 and A169 );
a2174a <=( A166 and (not A167) );
a2175a <=( a2174a and a2171a );
a2178a <=( (not A233) and A232 );
a2182a <=( (not A236) and (not A235) );
a2183a <=( (not A234) and a2182a );
a2184a <=( a2183a and a2178a );
a2187a <=( (not A169) and A170 );
a2190a <=( A167 and (not A168) );
a2191a <=( a2190a and a2187a );
a2194a <=( (not A232) and (not A166) );
a2198a <=( A235 and A234 );
a2199a <=( A233 and a2198a );
a2200a <=( a2199a and a2194a );
a2203a <=( (not A169) and A170 );
a2206a <=( A167 and (not A168) );
a2207a <=( a2206a and a2203a );
a2210a <=( (not A232) and (not A166) );
a2214a <=( A236 and A234 );
a2215a <=( A233 and a2214a );
a2216a <=( a2215a and a2210a );
a2219a <=( (not A169) and A170 );
a2222a <=( A167 and (not A168) );
a2223a <=( a2222a and a2219a );
a2226a <=( A232 and (not A166) );
a2230a <=( A235 and A234 );
a2231a <=( (not A233) and a2230a );
a2232a <=( a2231a and a2226a );
a2235a <=( (not A169) and A170 );
a2238a <=( A167 and (not A168) );
a2239a <=( a2238a and a2235a );
a2242a <=( A232 and (not A166) );
a2246a <=( A236 and A234 );
a2247a <=( (not A233) and a2246a );
a2248a <=( a2247a and a2242a );
a2251a <=( (not A169) and A170 );
a2254a <=( (not A167) and (not A168) );
a2255a <=( a2254a and a2251a );
a2258a <=( (not A232) and A166 );
a2262a <=( A235 and A234 );
a2263a <=( A233 and a2262a );
a2264a <=( a2263a and a2258a );
a2267a <=( (not A169) and A170 );
a2270a <=( (not A167) and (not A168) );
a2271a <=( a2270a and a2267a );
a2274a <=( (not A232) and A166 );
a2278a <=( A236 and A234 );
a2279a <=( A233 and a2278a );
a2280a <=( a2279a and a2274a );
a2283a <=( (not A169) and A170 );
a2286a <=( (not A167) and (not A168) );
a2287a <=( a2286a and a2283a );
a2290a <=( A232 and A166 );
a2294a <=( A235 and A234 );
a2295a <=( (not A233) and a2294a );
a2296a <=( a2295a and a2290a );
a2299a <=( (not A169) and A170 );
a2302a <=( (not A167) and (not A168) );
a2303a <=( a2302a and a2299a );
a2306a <=( A232 and A166 );
a2310a <=( A236 and A234 );
a2311a <=( (not A233) and a2310a );
a2312a <=( a2311a and a2306a );
a2315a <=( A200 and (not A199) );
a2319a <=( (not A203) and (not A202) );
a2320a <=( (not A201) and a2319a );
a2321a <=( a2320a and a2315a );
a2324a <=( A233 and (not A232) );
a2328a <=( (not A236) and (not A235) );
a2329a <=( (not A234) and a2328a );
a2330a <=( a2329a and a2324a );
a2333a <=( A200 and (not A199) );
a2337a <=( (not A203) and (not A202) );
a2338a <=( (not A201) and a2337a );
a2339a <=( a2338a and a2333a );
a2342a <=( (not A233) and A232 );
a2346a <=( (not A236) and (not A235) );
a2347a <=( (not A234) and a2346a );
a2348a <=( a2347a and a2342a );
a2351a <=( (not A200) and A199 );
a2355a <=( (not A203) and (not A202) );
a2356a <=( (not A201) and a2355a );
a2357a <=( a2356a and a2351a );
a2360a <=( A233 and (not A232) );
a2364a <=( (not A236) and (not A235) );
a2365a <=( (not A234) and a2364a );
a2366a <=( a2365a and a2360a );
a2369a <=( (not A200) and A199 );
a2373a <=( (not A203) and (not A202) );
a2374a <=( (not A201) and a2373a );
a2375a <=( a2374a and a2369a );
a2378a <=( (not A233) and A232 );
a2382a <=( (not A236) and (not A235) );
a2383a <=( (not A234) and a2382a );
a2384a <=( a2383a and a2378a );
a2387a <=( A166 and A167 );
a2391a <=( A201 and A200 );
a2392a <=( (not A199) and a2391a );
a2393a <=( a2392a and a2387a );
a2396a <=( A298 and A202 );
a2400a <=( A301 and A300 );
a2401a <=( (not A299) and a2400a );
a2402a <=( a2401a and a2396a );
a2405a <=( A166 and A167 );
a2409a <=( A201 and A200 );
a2410a <=( (not A199) and a2409a );
a2411a <=( a2410a and a2405a );
a2414a <=( A298 and A202 );
a2418a <=( A302 and A300 );
a2419a <=( (not A299) and a2418a );
a2420a <=( a2419a and a2414a );
a2423a <=( A166 and A167 );
a2427a <=( A201 and A200 );
a2428a <=( (not A199) and a2427a );
a2429a <=( a2428a and a2423a );
a2432a <=( (not A298) and A202 );
a2436a <=( A301 and A300 );
a2437a <=( A299 and a2436a );
a2438a <=( a2437a and a2432a );
a2441a <=( A166 and A167 );
a2445a <=( A201 and A200 );
a2446a <=( (not A199) and a2445a );
a2447a <=( a2446a and a2441a );
a2450a <=( (not A298) and A202 );
a2454a <=( A302 and A300 );
a2455a <=( A299 and a2454a );
a2456a <=( a2455a and a2450a );
a2459a <=( A166 and A167 );
a2463a <=( A201 and A200 );
a2464a <=( (not A199) and a2463a );
a2465a <=( a2464a and a2459a );
a2468a <=( A298 and A203 );
a2472a <=( A301 and A300 );
a2473a <=( (not A299) and a2472a );
a2474a <=( a2473a and a2468a );
a2477a <=( A166 and A167 );
a2481a <=( A201 and A200 );
a2482a <=( (not A199) and a2481a );
a2483a <=( a2482a and a2477a );
a2486a <=( A298 and A203 );
a2490a <=( A302 and A300 );
a2491a <=( (not A299) and a2490a );
a2492a <=( a2491a and a2486a );
a2495a <=( A166 and A167 );
a2499a <=( A201 and A200 );
a2500a <=( (not A199) and a2499a );
a2501a <=( a2500a and a2495a );
a2504a <=( (not A298) and A203 );
a2508a <=( A301 and A300 );
a2509a <=( A299 and a2508a );
a2510a <=( a2509a and a2504a );
a2513a <=( A166 and A167 );
a2517a <=( A201 and A200 );
a2518a <=( (not A199) and a2517a );
a2519a <=( a2518a and a2513a );
a2522a <=( (not A298) and A203 );
a2526a <=( A302 and A300 );
a2527a <=( A299 and a2526a );
a2528a <=( a2527a and a2522a );
a2531a <=( A166 and A167 );
a2535a <=( A201 and (not A200) );
a2536a <=( A199 and a2535a );
a2537a <=( a2536a and a2531a );
a2540a <=( A298 and A202 );
a2544a <=( A301 and A300 );
a2545a <=( (not A299) and a2544a );
a2546a <=( a2545a and a2540a );
a2549a <=( A166 and A167 );
a2553a <=( A201 and (not A200) );
a2554a <=( A199 and a2553a );
a2555a <=( a2554a and a2549a );
a2558a <=( A298 and A202 );
a2562a <=( A302 and A300 );
a2563a <=( (not A299) and a2562a );
a2564a <=( a2563a and a2558a );
a2567a <=( A166 and A167 );
a2571a <=( A201 and (not A200) );
a2572a <=( A199 and a2571a );
a2573a <=( a2572a and a2567a );
a2576a <=( (not A298) and A202 );
a2580a <=( A301 and A300 );
a2581a <=( A299 and a2580a );
a2582a <=( a2581a and a2576a );
a2585a <=( A166 and A167 );
a2589a <=( A201 and (not A200) );
a2590a <=( A199 and a2589a );
a2591a <=( a2590a and a2585a );
a2594a <=( (not A298) and A202 );
a2598a <=( A302 and A300 );
a2599a <=( A299 and a2598a );
a2600a <=( a2599a and a2594a );
a2603a <=( A166 and A167 );
a2607a <=( A201 and (not A200) );
a2608a <=( A199 and a2607a );
a2609a <=( a2608a and a2603a );
a2612a <=( A298 and A203 );
a2616a <=( A301 and A300 );
a2617a <=( (not A299) and a2616a );
a2618a <=( a2617a and a2612a );
a2621a <=( A166 and A167 );
a2625a <=( A201 and (not A200) );
a2626a <=( A199 and a2625a );
a2627a <=( a2626a and a2621a );
a2630a <=( A298 and A203 );
a2634a <=( A302 and A300 );
a2635a <=( (not A299) and a2634a );
a2636a <=( a2635a and a2630a );
a2639a <=( A166 and A167 );
a2643a <=( A201 and (not A200) );
a2644a <=( A199 and a2643a );
a2645a <=( a2644a and a2639a );
a2648a <=( (not A298) and A203 );
a2652a <=( A301 and A300 );
a2653a <=( A299 and a2652a );
a2654a <=( a2653a and a2648a );
a2657a <=( A166 and A167 );
a2661a <=( A201 and (not A200) );
a2662a <=( A199 and a2661a );
a2663a <=( a2662a and a2657a );
a2666a <=( (not A298) and A203 );
a2670a <=( A302 and A300 );
a2671a <=( A299 and a2670a );
a2672a <=( a2671a and a2666a );
a2675a <=( (not A166) and (not A167) );
a2679a <=( A201 and A200 );
a2680a <=( (not A199) and a2679a );
a2681a <=( a2680a and a2675a );
a2684a <=( A298 and A202 );
a2688a <=( A301 and A300 );
a2689a <=( (not A299) and a2688a );
a2690a <=( a2689a and a2684a );
a2693a <=( (not A166) and (not A167) );
a2697a <=( A201 and A200 );
a2698a <=( (not A199) and a2697a );
a2699a <=( a2698a and a2693a );
a2702a <=( A298 and A202 );
a2706a <=( A302 and A300 );
a2707a <=( (not A299) and a2706a );
a2708a <=( a2707a and a2702a );
a2711a <=( (not A166) and (not A167) );
a2715a <=( A201 and A200 );
a2716a <=( (not A199) and a2715a );
a2717a <=( a2716a and a2711a );
a2720a <=( (not A298) and A202 );
a2724a <=( A301 and A300 );
a2725a <=( A299 and a2724a );
a2726a <=( a2725a and a2720a );
a2729a <=( (not A166) and (not A167) );
a2733a <=( A201 and A200 );
a2734a <=( (not A199) and a2733a );
a2735a <=( a2734a and a2729a );
a2738a <=( (not A298) and A202 );
a2742a <=( A302 and A300 );
a2743a <=( A299 and a2742a );
a2744a <=( a2743a and a2738a );
a2747a <=( (not A166) and (not A167) );
a2751a <=( A201 and A200 );
a2752a <=( (not A199) and a2751a );
a2753a <=( a2752a and a2747a );
a2756a <=( A298 and A203 );
a2760a <=( A301 and A300 );
a2761a <=( (not A299) and a2760a );
a2762a <=( a2761a and a2756a );
a2765a <=( (not A166) and (not A167) );
a2769a <=( A201 and A200 );
a2770a <=( (not A199) and a2769a );
a2771a <=( a2770a and a2765a );
a2774a <=( A298 and A203 );
a2778a <=( A302 and A300 );
a2779a <=( (not A299) and a2778a );
a2780a <=( a2779a and a2774a );
a2783a <=( (not A166) and (not A167) );
a2787a <=( A201 and A200 );
a2788a <=( (not A199) and a2787a );
a2789a <=( a2788a and a2783a );
a2792a <=( (not A298) and A203 );
a2796a <=( A301 and A300 );
a2797a <=( A299 and a2796a );
a2798a <=( a2797a and a2792a );
a2801a <=( (not A166) and (not A167) );
a2805a <=( A201 and A200 );
a2806a <=( (not A199) and a2805a );
a2807a <=( a2806a and a2801a );
a2810a <=( (not A298) and A203 );
a2814a <=( A302 and A300 );
a2815a <=( A299 and a2814a );
a2816a <=( a2815a and a2810a );
a2819a <=( (not A166) and (not A167) );
a2823a <=( A201 and (not A200) );
a2824a <=( A199 and a2823a );
a2825a <=( a2824a and a2819a );
a2828a <=( A298 and A202 );
a2832a <=( A301 and A300 );
a2833a <=( (not A299) and a2832a );
a2834a <=( a2833a and a2828a );
a2837a <=( (not A166) and (not A167) );
a2841a <=( A201 and (not A200) );
a2842a <=( A199 and a2841a );
a2843a <=( a2842a and a2837a );
a2846a <=( A298 and A202 );
a2850a <=( A302 and A300 );
a2851a <=( (not A299) and a2850a );
a2852a <=( a2851a and a2846a );
a2855a <=( (not A166) and (not A167) );
a2859a <=( A201 and (not A200) );
a2860a <=( A199 and a2859a );
a2861a <=( a2860a and a2855a );
a2864a <=( (not A298) and A202 );
a2868a <=( A301 and A300 );
a2869a <=( A299 and a2868a );
a2870a <=( a2869a and a2864a );
a2873a <=( (not A166) and (not A167) );
a2877a <=( A201 and (not A200) );
a2878a <=( A199 and a2877a );
a2879a <=( a2878a and a2873a );
a2882a <=( (not A298) and A202 );
a2886a <=( A302 and A300 );
a2887a <=( A299 and a2886a );
a2888a <=( a2887a and a2882a );
a2891a <=( (not A166) and (not A167) );
a2895a <=( A201 and (not A200) );
a2896a <=( A199 and a2895a );
a2897a <=( a2896a and a2891a );
a2900a <=( A298 and A203 );
a2904a <=( A301 and A300 );
a2905a <=( (not A299) and a2904a );
a2906a <=( a2905a and a2900a );
a2909a <=( (not A166) and (not A167) );
a2913a <=( A201 and (not A200) );
a2914a <=( A199 and a2913a );
a2915a <=( a2914a and a2909a );
a2918a <=( A298 and A203 );
a2922a <=( A302 and A300 );
a2923a <=( (not A299) and a2922a );
a2924a <=( a2923a and a2918a );
a2927a <=( (not A166) and (not A167) );
a2931a <=( A201 and (not A200) );
a2932a <=( A199 and a2931a );
a2933a <=( a2932a and a2927a );
a2936a <=( (not A298) and A203 );
a2940a <=( A301 and A300 );
a2941a <=( A299 and a2940a );
a2942a <=( a2941a and a2936a );
a2945a <=( (not A166) and (not A167) );
a2949a <=( A201 and (not A200) );
a2950a <=( A199 and a2949a );
a2951a <=( a2950a and a2945a );
a2954a <=( (not A298) and A203 );
a2958a <=( A302 and A300 );
a2959a <=( A299 and a2958a );
a2960a <=( a2959a and a2954a );
a2963a <=( A168 and (not A170) );
a2967a <=( (not A201) and (not A166) );
a2968a <=( A167 and a2967a );
a2969a <=( a2968a and a2963a );
a2972a <=( A298 and A202 );
a2976a <=( A301 and A300 );
a2977a <=( (not A299) and a2976a );
a2978a <=( a2977a and a2972a );
a2981a <=( A168 and (not A170) );
a2985a <=( (not A201) and (not A166) );
a2986a <=( A167 and a2985a );
a2987a <=( a2986a and a2981a );
a2990a <=( A298 and A202 );
a2994a <=( A302 and A300 );
a2995a <=( (not A299) and a2994a );
a2996a <=( a2995a and a2990a );
a2999a <=( A168 and (not A170) );
a3003a <=( (not A201) and (not A166) );
a3004a <=( A167 and a3003a );
a3005a <=( a3004a and a2999a );
a3008a <=( (not A298) and A202 );
a3012a <=( A301 and A300 );
a3013a <=( A299 and a3012a );
a3014a <=( a3013a and a3008a );
a3017a <=( A168 and (not A170) );
a3021a <=( (not A201) and (not A166) );
a3022a <=( A167 and a3021a );
a3023a <=( a3022a and a3017a );
a3026a <=( (not A298) and A202 );
a3030a <=( A302 and A300 );
a3031a <=( A299 and a3030a );
a3032a <=( a3031a and a3026a );
a3035a <=( A168 and (not A170) );
a3039a <=( (not A201) and (not A166) );
a3040a <=( A167 and a3039a );
a3041a <=( a3040a and a3035a );
a3044a <=( A298 and A203 );
a3048a <=( A301 and A300 );
a3049a <=( (not A299) and a3048a );
a3050a <=( a3049a and a3044a );
a3053a <=( A168 and (not A170) );
a3057a <=( (not A201) and (not A166) );
a3058a <=( A167 and a3057a );
a3059a <=( a3058a and a3053a );
a3062a <=( A298 and A203 );
a3066a <=( A302 and A300 );
a3067a <=( (not A299) and a3066a );
a3068a <=( a3067a and a3062a );
a3071a <=( A168 and (not A170) );
a3075a <=( (not A201) and (not A166) );
a3076a <=( A167 and a3075a );
a3077a <=( a3076a and a3071a );
a3080a <=( (not A298) and A203 );
a3084a <=( A301 and A300 );
a3085a <=( A299 and a3084a );
a3086a <=( a3085a and a3080a );
a3089a <=( A168 and (not A170) );
a3093a <=( (not A201) and (not A166) );
a3094a <=( A167 and a3093a );
a3095a <=( a3094a and a3089a );
a3098a <=( (not A298) and A203 );
a3102a <=( A302 and A300 );
a3103a <=( A299 and a3102a );
a3104a <=( a3103a and a3098a );
a3107a <=( A168 and (not A170) );
a3111a <=( A199 and (not A166) );
a3112a <=( A167 and a3111a );
a3113a <=( a3112a and a3107a );
a3116a <=( A298 and A200 );
a3120a <=( A301 and A300 );
a3121a <=( (not A299) and a3120a );
a3122a <=( a3121a and a3116a );
a3125a <=( A168 and (not A170) );
a3129a <=( A199 and (not A166) );
a3130a <=( A167 and a3129a );
a3131a <=( a3130a and a3125a );
a3134a <=( A298 and A200 );
a3138a <=( A302 and A300 );
a3139a <=( (not A299) and a3138a );
a3140a <=( a3139a and a3134a );
a3143a <=( A168 and (not A170) );
a3147a <=( A199 and (not A166) );
a3148a <=( A167 and a3147a );
a3149a <=( a3148a and a3143a );
a3152a <=( (not A298) and A200 );
a3156a <=( A301 and A300 );
a3157a <=( A299 and a3156a );
a3158a <=( a3157a and a3152a );
a3161a <=( A168 and (not A170) );
a3165a <=( A199 and (not A166) );
a3166a <=( A167 and a3165a );
a3167a <=( a3166a and a3161a );
a3170a <=( (not A298) and A200 );
a3174a <=( A302 and A300 );
a3175a <=( A299 and a3174a );
a3176a <=( a3175a and a3170a );
a3179a <=( A168 and (not A170) );
a3183a <=( (not A199) and (not A166) );
a3184a <=( A167 and a3183a );
a3185a <=( a3184a and a3179a );
a3188a <=( A298 and (not A200) );
a3192a <=( A301 and A300 );
a3193a <=( (not A299) and a3192a );
a3194a <=( a3193a and a3188a );
a3197a <=( A168 and (not A170) );
a3201a <=( (not A199) and (not A166) );
a3202a <=( A167 and a3201a );
a3203a <=( a3202a and a3197a );
a3206a <=( A298 and (not A200) );
a3210a <=( A302 and A300 );
a3211a <=( (not A299) and a3210a );
a3212a <=( a3211a and a3206a );
a3215a <=( A168 and (not A170) );
a3219a <=( (not A199) and (not A166) );
a3220a <=( A167 and a3219a );
a3221a <=( a3220a and a3215a );
a3224a <=( (not A298) and (not A200) );
a3228a <=( A301 and A300 );
a3229a <=( A299 and a3228a );
a3230a <=( a3229a and a3224a );
a3233a <=( A168 and (not A170) );
a3237a <=( (not A199) and (not A166) );
a3238a <=( A167 and a3237a );
a3239a <=( a3238a and a3233a );
a3242a <=( (not A298) and (not A200) );
a3246a <=( A302 and A300 );
a3247a <=( A299 and a3246a );
a3248a <=( a3247a and a3242a );
a3251a <=( A168 and (not A170) );
a3255a <=( (not A201) and A166 );
a3256a <=( (not A167) and a3255a );
a3257a <=( a3256a and a3251a );
a3260a <=( A298 and A202 );
a3264a <=( A301 and A300 );
a3265a <=( (not A299) and a3264a );
a3266a <=( a3265a and a3260a );
a3269a <=( A168 and (not A170) );
a3273a <=( (not A201) and A166 );
a3274a <=( (not A167) and a3273a );
a3275a <=( a3274a and a3269a );
a3278a <=( A298 and A202 );
a3282a <=( A302 and A300 );
a3283a <=( (not A299) and a3282a );
a3284a <=( a3283a and a3278a );
a3287a <=( A168 and (not A170) );
a3291a <=( (not A201) and A166 );
a3292a <=( (not A167) and a3291a );
a3293a <=( a3292a and a3287a );
a3296a <=( (not A298) and A202 );
a3300a <=( A301 and A300 );
a3301a <=( A299 and a3300a );
a3302a <=( a3301a and a3296a );
a3305a <=( A168 and (not A170) );
a3309a <=( (not A201) and A166 );
a3310a <=( (not A167) and a3309a );
a3311a <=( a3310a and a3305a );
a3314a <=( (not A298) and A202 );
a3318a <=( A302 and A300 );
a3319a <=( A299 and a3318a );
a3320a <=( a3319a and a3314a );
a3323a <=( A168 and (not A170) );
a3327a <=( (not A201) and A166 );
a3328a <=( (not A167) and a3327a );
a3329a <=( a3328a and a3323a );
a3332a <=( A298 and A203 );
a3336a <=( A301 and A300 );
a3337a <=( (not A299) and a3336a );
a3338a <=( a3337a and a3332a );
a3341a <=( A168 and (not A170) );
a3345a <=( (not A201) and A166 );
a3346a <=( (not A167) and a3345a );
a3347a <=( a3346a and a3341a );
a3350a <=( A298 and A203 );
a3354a <=( A302 and A300 );
a3355a <=( (not A299) and a3354a );
a3356a <=( a3355a and a3350a );
a3359a <=( A168 and (not A170) );
a3363a <=( (not A201) and A166 );
a3364a <=( (not A167) and a3363a );
a3365a <=( a3364a and a3359a );
a3368a <=( (not A298) and A203 );
a3372a <=( A301 and A300 );
a3373a <=( A299 and a3372a );
a3374a <=( a3373a and a3368a );
a3377a <=( A168 and (not A170) );
a3381a <=( (not A201) and A166 );
a3382a <=( (not A167) and a3381a );
a3383a <=( a3382a and a3377a );
a3386a <=( (not A298) and A203 );
a3390a <=( A302 and A300 );
a3391a <=( A299 and a3390a );
a3392a <=( a3391a and a3386a );
a3395a <=( A168 and (not A170) );
a3399a <=( A199 and A166 );
a3400a <=( (not A167) and a3399a );
a3401a <=( a3400a and a3395a );
a3404a <=( A298 and A200 );
a3408a <=( A301 and A300 );
a3409a <=( (not A299) and a3408a );
a3410a <=( a3409a and a3404a );
a3413a <=( A168 and (not A170) );
a3417a <=( A199 and A166 );
a3418a <=( (not A167) and a3417a );
a3419a <=( a3418a and a3413a );
a3422a <=( A298 and A200 );
a3426a <=( A302 and A300 );
a3427a <=( (not A299) and a3426a );
a3428a <=( a3427a and a3422a );
a3431a <=( A168 and (not A170) );
a3435a <=( A199 and A166 );
a3436a <=( (not A167) and a3435a );
a3437a <=( a3436a and a3431a );
a3440a <=( (not A298) and A200 );
a3444a <=( A301 and A300 );
a3445a <=( A299 and a3444a );
a3446a <=( a3445a and a3440a );
a3449a <=( A168 and (not A170) );
a3453a <=( A199 and A166 );
a3454a <=( (not A167) and a3453a );
a3455a <=( a3454a and a3449a );
a3458a <=( (not A298) and A200 );
a3462a <=( A302 and A300 );
a3463a <=( A299 and a3462a );
a3464a <=( a3463a and a3458a );
a3467a <=( A168 and (not A170) );
a3471a <=( (not A199) and A166 );
a3472a <=( (not A167) and a3471a );
a3473a <=( a3472a and a3467a );
a3476a <=( A298 and (not A200) );
a3480a <=( A301 and A300 );
a3481a <=( (not A299) and a3480a );
a3482a <=( a3481a and a3476a );
a3485a <=( A168 and (not A170) );
a3489a <=( (not A199) and A166 );
a3490a <=( (not A167) and a3489a );
a3491a <=( a3490a and a3485a );
a3494a <=( A298 and (not A200) );
a3498a <=( A302 and A300 );
a3499a <=( (not A299) and a3498a );
a3500a <=( a3499a and a3494a );
a3503a <=( A168 and (not A170) );
a3507a <=( (not A199) and A166 );
a3508a <=( (not A167) and a3507a );
a3509a <=( a3508a and a3503a );
a3512a <=( (not A298) and (not A200) );
a3516a <=( A301 and A300 );
a3517a <=( A299 and a3516a );
a3518a <=( a3517a and a3512a );
a3521a <=( A168 and (not A170) );
a3525a <=( (not A199) and A166 );
a3526a <=( (not A167) and a3525a );
a3527a <=( a3526a and a3521a );
a3530a <=( (not A298) and (not A200) );
a3534a <=( A302 and A300 );
a3535a <=( A299 and a3534a );
a3536a <=( a3535a and a3530a );
a3539a <=( (not A168) and (not A170) );
a3543a <=( A201 and A200 );
a3544a <=( (not A199) and a3543a );
a3545a <=( a3544a and a3539a );
a3548a <=( A298 and A202 );
a3552a <=( A301 and A300 );
a3553a <=( (not A299) and a3552a );
a3554a <=( a3553a and a3548a );
a3557a <=( (not A168) and (not A170) );
a3561a <=( A201 and A200 );
a3562a <=( (not A199) and a3561a );
a3563a <=( a3562a and a3557a );
a3566a <=( A298 and A202 );
a3570a <=( A302 and A300 );
a3571a <=( (not A299) and a3570a );
a3572a <=( a3571a and a3566a );
a3575a <=( (not A168) and (not A170) );
a3579a <=( A201 and A200 );
a3580a <=( (not A199) and a3579a );
a3581a <=( a3580a and a3575a );
a3584a <=( (not A298) and A202 );
a3588a <=( A301 and A300 );
a3589a <=( A299 and a3588a );
a3590a <=( a3589a and a3584a );
a3593a <=( (not A168) and (not A170) );
a3597a <=( A201 and A200 );
a3598a <=( (not A199) and a3597a );
a3599a <=( a3598a and a3593a );
a3602a <=( (not A298) and A202 );
a3606a <=( A302 and A300 );
a3607a <=( A299 and a3606a );
a3608a <=( a3607a and a3602a );
a3611a <=( (not A168) and (not A170) );
a3615a <=( A201 and A200 );
a3616a <=( (not A199) and a3615a );
a3617a <=( a3616a and a3611a );
a3620a <=( A298 and A203 );
a3624a <=( A301 and A300 );
a3625a <=( (not A299) and a3624a );
a3626a <=( a3625a and a3620a );
a3629a <=( (not A168) and (not A170) );
a3633a <=( A201 and A200 );
a3634a <=( (not A199) and a3633a );
a3635a <=( a3634a and a3629a );
a3638a <=( A298 and A203 );
a3642a <=( A302 and A300 );
a3643a <=( (not A299) and a3642a );
a3644a <=( a3643a and a3638a );
a3647a <=( (not A168) and (not A170) );
a3651a <=( A201 and A200 );
a3652a <=( (not A199) and a3651a );
a3653a <=( a3652a and a3647a );
a3656a <=( (not A298) and A203 );
a3660a <=( A301 and A300 );
a3661a <=( A299 and a3660a );
a3662a <=( a3661a and a3656a );
a3665a <=( (not A168) and (not A170) );
a3669a <=( A201 and A200 );
a3670a <=( (not A199) and a3669a );
a3671a <=( a3670a and a3665a );
a3674a <=( (not A298) and A203 );
a3678a <=( A302 and A300 );
a3679a <=( A299 and a3678a );
a3680a <=( a3679a and a3674a );
a3683a <=( (not A168) and (not A170) );
a3687a <=( A201 and (not A200) );
a3688a <=( A199 and a3687a );
a3689a <=( a3688a and a3683a );
a3692a <=( A298 and A202 );
a3696a <=( A301 and A300 );
a3697a <=( (not A299) and a3696a );
a3698a <=( a3697a and a3692a );
a3701a <=( (not A168) and (not A170) );
a3705a <=( A201 and (not A200) );
a3706a <=( A199 and a3705a );
a3707a <=( a3706a and a3701a );
a3710a <=( A298 and A202 );
a3714a <=( A302 and A300 );
a3715a <=( (not A299) and a3714a );
a3716a <=( a3715a and a3710a );
a3719a <=( (not A168) and (not A170) );
a3723a <=( A201 and (not A200) );
a3724a <=( A199 and a3723a );
a3725a <=( a3724a and a3719a );
a3728a <=( (not A298) and A202 );
a3732a <=( A301 and A300 );
a3733a <=( A299 and a3732a );
a3734a <=( a3733a and a3728a );
a3737a <=( (not A168) and (not A170) );
a3741a <=( A201 and (not A200) );
a3742a <=( A199 and a3741a );
a3743a <=( a3742a and a3737a );
a3746a <=( (not A298) and A202 );
a3750a <=( A302 and A300 );
a3751a <=( A299 and a3750a );
a3752a <=( a3751a and a3746a );
a3755a <=( (not A168) and (not A170) );
a3759a <=( A201 and (not A200) );
a3760a <=( A199 and a3759a );
a3761a <=( a3760a and a3755a );
a3764a <=( A298 and A203 );
a3768a <=( A301 and A300 );
a3769a <=( (not A299) and a3768a );
a3770a <=( a3769a and a3764a );
a3773a <=( (not A168) and (not A170) );
a3777a <=( A201 and (not A200) );
a3778a <=( A199 and a3777a );
a3779a <=( a3778a and a3773a );
a3782a <=( A298 and A203 );
a3786a <=( A302 and A300 );
a3787a <=( (not A299) and a3786a );
a3788a <=( a3787a and a3782a );
a3791a <=( (not A168) and (not A170) );
a3795a <=( A201 and (not A200) );
a3796a <=( A199 and a3795a );
a3797a <=( a3796a and a3791a );
a3800a <=( (not A298) and A203 );
a3804a <=( A301 and A300 );
a3805a <=( A299 and a3804a );
a3806a <=( a3805a and a3800a );
a3809a <=( (not A168) and (not A170) );
a3813a <=( A201 and (not A200) );
a3814a <=( A199 and a3813a );
a3815a <=( a3814a and a3809a );
a3818a <=( (not A298) and A203 );
a3822a <=( A302 and A300 );
a3823a <=( A299 and a3822a );
a3824a <=( a3823a and a3818a );
a3827a <=( A168 and A169 );
a3831a <=( (not A201) and (not A166) );
a3832a <=( A167 and a3831a );
a3833a <=( a3832a and a3827a );
a3836a <=( A298 and A202 );
a3840a <=( A301 and A300 );
a3841a <=( (not A299) and a3840a );
a3842a <=( a3841a and a3836a );
a3845a <=( A168 and A169 );
a3849a <=( (not A201) and (not A166) );
a3850a <=( A167 and a3849a );
a3851a <=( a3850a and a3845a );
a3854a <=( A298 and A202 );
a3858a <=( A302 and A300 );
a3859a <=( (not A299) and a3858a );
a3860a <=( a3859a and a3854a );
a3863a <=( A168 and A169 );
a3867a <=( (not A201) and (not A166) );
a3868a <=( A167 and a3867a );
a3869a <=( a3868a and a3863a );
a3872a <=( (not A298) and A202 );
a3876a <=( A301 and A300 );
a3877a <=( A299 and a3876a );
a3878a <=( a3877a and a3872a );
a3881a <=( A168 and A169 );
a3885a <=( (not A201) and (not A166) );
a3886a <=( A167 and a3885a );
a3887a <=( a3886a and a3881a );
a3890a <=( (not A298) and A202 );
a3894a <=( A302 and A300 );
a3895a <=( A299 and a3894a );
a3896a <=( a3895a and a3890a );
a3899a <=( A168 and A169 );
a3903a <=( (not A201) and (not A166) );
a3904a <=( A167 and a3903a );
a3905a <=( a3904a and a3899a );
a3908a <=( A298 and A203 );
a3912a <=( A301 and A300 );
a3913a <=( (not A299) and a3912a );
a3914a <=( a3913a and a3908a );
a3917a <=( A168 and A169 );
a3921a <=( (not A201) and (not A166) );
a3922a <=( A167 and a3921a );
a3923a <=( a3922a and a3917a );
a3926a <=( A298 and A203 );
a3930a <=( A302 and A300 );
a3931a <=( (not A299) and a3930a );
a3932a <=( a3931a and a3926a );
a3935a <=( A168 and A169 );
a3939a <=( (not A201) and (not A166) );
a3940a <=( A167 and a3939a );
a3941a <=( a3940a and a3935a );
a3944a <=( (not A298) and A203 );
a3948a <=( A301 and A300 );
a3949a <=( A299 and a3948a );
a3950a <=( a3949a and a3944a );
a3953a <=( A168 and A169 );
a3957a <=( (not A201) and (not A166) );
a3958a <=( A167 and a3957a );
a3959a <=( a3958a and a3953a );
a3962a <=( (not A298) and A203 );
a3966a <=( A302 and A300 );
a3967a <=( A299 and a3966a );
a3968a <=( a3967a and a3962a );
a3971a <=( A168 and A169 );
a3975a <=( A199 and (not A166) );
a3976a <=( A167 and a3975a );
a3977a <=( a3976a and a3971a );
a3980a <=( A298 and A200 );
a3984a <=( A301 and A300 );
a3985a <=( (not A299) and a3984a );
a3986a <=( a3985a and a3980a );
a3989a <=( A168 and A169 );
a3993a <=( A199 and (not A166) );
a3994a <=( A167 and a3993a );
a3995a <=( a3994a and a3989a );
a3998a <=( A298 and A200 );
a4002a <=( A302 and A300 );
a4003a <=( (not A299) and a4002a );
a4004a <=( a4003a and a3998a );
a4007a <=( A168 and A169 );
a4011a <=( A199 and (not A166) );
a4012a <=( A167 and a4011a );
a4013a <=( a4012a and a4007a );
a4016a <=( (not A298) and A200 );
a4020a <=( A301 and A300 );
a4021a <=( A299 and a4020a );
a4022a <=( a4021a and a4016a );
a4025a <=( A168 and A169 );
a4029a <=( A199 and (not A166) );
a4030a <=( A167 and a4029a );
a4031a <=( a4030a and a4025a );
a4034a <=( (not A298) and A200 );
a4038a <=( A302 and A300 );
a4039a <=( A299 and a4038a );
a4040a <=( a4039a and a4034a );
a4043a <=( A168 and A169 );
a4047a <=( (not A199) and (not A166) );
a4048a <=( A167 and a4047a );
a4049a <=( a4048a and a4043a );
a4052a <=( A298 and (not A200) );
a4056a <=( A301 and A300 );
a4057a <=( (not A299) and a4056a );
a4058a <=( a4057a and a4052a );
a4061a <=( A168 and A169 );
a4065a <=( (not A199) and (not A166) );
a4066a <=( A167 and a4065a );
a4067a <=( a4066a and a4061a );
a4070a <=( A298 and (not A200) );
a4074a <=( A302 and A300 );
a4075a <=( (not A299) and a4074a );
a4076a <=( a4075a and a4070a );
a4079a <=( A168 and A169 );
a4083a <=( (not A199) and (not A166) );
a4084a <=( A167 and a4083a );
a4085a <=( a4084a and a4079a );
a4088a <=( (not A298) and (not A200) );
a4092a <=( A301 and A300 );
a4093a <=( A299 and a4092a );
a4094a <=( a4093a and a4088a );
a4097a <=( A168 and A169 );
a4101a <=( (not A199) and (not A166) );
a4102a <=( A167 and a4101a );
a4103a <=( a4102a and a4097a );
a4106a <=( (not A298) and (not A200) );
a4110a <=( A302 and A300 );
a4111a <=( A299 and a4110a );
a4112a <=( a4111a and a4106a );
a4115a <=( A168 and A169 );
a4119a <=( (not A201) and A166 );
a4120a <=( (not A167) and a4119a );
a4121a <=( a4120a and a4115a );
a4124a <=( A298 and A202 );
a4128a <=( A301 and A300 );
a4129a <=( (not A299) and a4128a );
a4130a <=( a4129a and a4124a );
a4133a <=( A168 and A169 );
a4137a <=( (not A201) and A166 );
a4138a <=( (not A167) and a4137a );
a4139a <=( a4138a and a4133a );
a4142a <=( A298 and A202 );
a4146a <=( A302 and A300 );
a4147a <=( (not A299) and a4146a );
a4148a <=( a4147a and a4142a );
a4151a <=( A168 and A169 );
a4155a <=( (not A201) and A166 );
a4156a <=( (not A167) and a4155a );
a4157a <=( a4156a and a4151a );
a4160a <=( (not A298) and A202 );
a4164a <=( A301 and A300 );
a4165a <=( A299 and a4164a );
a4166a <=( a4165a and a4160a );
a4169a <=( A168 and A169 );
a4173a <=( (not A201) and A166 );
a4174a <=( (not A167) and a4173a );
a4175a <=( a4174a and a4169a );
a4178a <=( (not A298) and A202 );
a4182a <=( A302 and A300 );
a4183a <=( A299 and a4182a );
a4184a <=( a4183a and a4178a );
a4187a <=( A168 and A169 );
a4191a <=( (not A201) and A166 );
a4192a <=( (not A167) and a4191a );
a4193a <=( a4192a and a4187a );
a4196a <=( A298 and A203 );
a4200a <=( A301 and A300 );
a4201a <=( (not A299) and a4200a );
a4202a <=( a4201a and a4196a );
a4205a <=( A168 and A169 );
a4209a <=( (not A201) and A166 );
a4210a <=( (not A167) and a4209a );
a4211a <=( a4210a and a4205a );
a4214a <=( A298 and A203 );
a4218a <=( A302 and A300 );
a4219a <=( (not A299) and a4218a );
a4220a <=( a4219a and a4214a );
a4223a <=( A168 and A169 );
a4227a <=( (not A201) and A166 );
a4228a <=( (not A167) and a4227a );
a4229a <=( a4228a and a4223a );
a4232a <=( (not A298) and A203 );
a4236a <=( A301 and A300 );
a4237a <=( A299 and a4236a );
a4238a <=( a4237a and a4232a );
a4241a <=( A168 and A169 );
a4245a <=( (not A201) and A166 );
a4246a <=( (not A167) and a4245a );
a4247a <=( a4246a and a4241a );
a4250a <=( (not A298) and A203 );
a4254a <=( A302 and A300 );
a4255a <=( A299 and a4254a );
a4256a <=( a4255a and a4250a );
a4259a <=( A168 and A169 );
a4263a <=( A199 and A166 );
a4264a <=( (not A167) and a4263a );
a4265a <=( a4264a and a4259a );
a4268a <=( A298 and A200 );
a4272a <=( A301 and A300 );
a4273a <=( (not A299) and a4272a );
a4274a <=( a4273a and a4268a );
a4277a <=( A168 and A169 );
a4281a <=( A199 and A166 );
a4282a <=( (not A167) and a4281a );
a4283a <=( a4282a and a4277a );
a4286a <=( A298 and A200 );
a4290a <=( A302 and A300 );
a4291a <=( (not A299) and a4290a );
a4292a <=( a4291a and a4286a );
a4295a <=( A168 and A169 );
a4299a <=( A199 and A166 );
a4300a <=( (not A167) and a4299a );
a4301a <=( a4300a and a4295a );
a4304a <=( (not A298) and A200 );
a4308a <=( A301 and A300 );
a4309a <=( A299 and a4308a );
a4310a <=( a4309a and a4304a );
a4313a <=( A168 and A169 );
a4317a <=( A199 and A166 );
a4318a <=( (not A167) and a4317a );
a4319a <=( a4318a and a4313a );
a4322a <=( (not A298) and A200 );
a4326a <=( A302 and A300 );
a4327a <=( A299 and a4326a );
a4328a <=( a4327a and a4322a );
a4331a <=( A168 and A169 );
a4335a <=( (not A199) and A166 );
a4336a <=( (not A167) and a4335a );
a4337a <=( a4336a and a4331a );
a4340a <=( A298 and (not A200) );
a4344a <=( A301 and A300 );
a4345a <=( (not A299) and a4344a );
a4346a <=( a4345a and a4340a );
a4349a <=( A168 and A169 );
a4353a <=( (not A199) and A166 );
a4354a <=( (not A167) and a4353a );
a4355a <=( a4354a and a4349a );
a4358a <=( A298 and (not A200) );
a4362a <=( A302 and A300 );
a4363a <=( (not A299) and a4362a );
a4364a <=( a4363a and a4358a );
a4367a <=( A168 and A169 );
a4371a <=( (not A199) and A166 );
a4372a <=( (not A167) and a4371a );
a4373a <=( a4372a and a4367a );
a4376a <=( (not A298) and (not A200) );
a4380a <=( A301 and A300 );
a4381a <=( A299 and a4380a );
a4382a <=( a4381a and a4376a );
a4385a <=( A168 and A169 );
a4389a <=( (not A199) and A166 );
a4390a <=( (not A167) and a4389a );
a4391a <=( a4390a and a4385a );
a4394a <=( (not A298) and (not A200) );
a4398a <=( A302 and A300 );
a4399a <=( A299 and a4398a );
a4400a <=( a4399a and a4394a );
a4403a <=( (not A168) and A169 );
a4407a <=( A201 and A200 );
a4408a <=( (not A199) and a4407a );
a4409a <=( a4408a and a4403a );
a4412a <=( A298 and A202 );
a4416a <=( A301 and A300 );
a4417a <=( (not A299) and a4416a );
a4418a <=( a4417a and a4412a );
a4421a <=( (not A168) and A169 );
a4425a <=( A201 and A200 );
a4426a <=( (not A199) and a4425a );
a4427a <=( a4426a and a4421a );
a4430a <=( A298 and A202 );
a4434a <=( A302 and A300 );
a4435a <=( (not A299) and a4434a );
a4436a <=( a4435a and a4430a );
a4439a <=( (not A168) and A169 );
a4443a <=( A201 and A200 );
a4444a <=( (not A199) and a4443a );
a4445a <=( a4444a and a4439a );
a4448a <=( (not A298) and A202 );
a4452a <=( A301 and A300 );
a4453a <=( A299 and a4452a );
a4454a <=( a4453a and a4448a );
a4457a <=( (not A168) and A169 );
a4461a <=( A201 and A200 );
a4462a <=( (not A199) and a4461a );
a4463a <=( a4462a and a4457a );
a4466a <=( (not A298) and A202 );
a4470a <=( A302 and A300 );
a4471a <=( A299 and a4470a );
a4472a <=( a4471a and a4466a );
a4475a <=( (not A168) and A169 );
a4479a <=( A201 and A200 );
a4480a <=( (not A199) and a4479a );
a4481a <=( a4480a and a4475a );
a4484a <=( A298 and A203 );
a4488a <=( A301 and A300 );
a4489a <=( (not A299) and a4488a );
a4490a <=( a4489a and a4484a );
a4493a <=( (not A168) and A169 );
a4497a <=( A201 and A200 );
a4498a <=( (not A199) and a4497a );
a4499a <=( a4498a and a4493a );
a4502a <=( A298 and A203 );
a4506a <=( A302 and A300 );
a4507a <=( (not A299) and a4506a );
a4508a <=( a4507a and a4502a );
a4511a <=( (not A168) and A169 );
a4515a <=( A201 and A200 );
a4516a <=( (not A199) and a4515a );
a4517a <=( a4516a and a4511a );
a4520a <=( (not A298) and A203 );
a4524a <=( A301 and A300 );
a4525a <=( A299 and a4524a );
a4526a <=( a4525a and a4520a );
a4529a <=( (not A168) and A169 );
a4533a <=( A201 and A200 );
a4534a <=( (not A199) and a4533a );
a4535a <=( a4534a and a4529a );
a4538a <=( (not A298) and A203 );
a4542a <=( A302 and A300 );
a4543a <=( A299 and a4542a );
a4544a <=( a4543a and a4538a );
a4547a <=( (not A168) and A169 );
a4551a <=( A201 and (not A200) );
a4552a <=( A199 and a4551a );
a4553a <=( a4552a and a4547a );
a4556a <=( A298 and A202 );
a4560a <=( A301 and A300 );
a4561a <=( (not A299) and a4560a );
a4562a <=( a4561a and a4556a );
a4565a <=( (not A168) and A169 );
a4569a <=( A201 and (not A200) );
a4570a <=( A199 and a4569a );
a4571a <=( a4570a and a4565a );
a4574a <=( A298 and A202 );
a4578a <=( A302 and A300 );
a4579a <=( (not A299) and a4578a );
a4580a <=( a4579a and a4574a );
a4583a <=( (not A168) and A169 );
a4587a <=( A201 and (not A200) );
a4588a <=( A199 and a4587a );
a4589a <=( a4588a and a4583a );
a4592a <=( (not A298) and A202 );
a4596a <=( A301 and A300 );
a4597a <=( A299 and a4596a );
a4598a <=( a4597a and a4592a );
a4601a <=( (not A168) and A169 );
a4605a <=( A201 and (not A200) );
a4606a <=( A199 and a4605a );
a4607a <=( a4606a and a4601a );
a4610a <=( (not A298) and A202 );
a4614a <=( A302 and A300 );
a4615a <=( A299 and a4614a );
a4616a <=( a4615a and a4610a );
a4619a <=( (not A168) and A169 );
a4623a <=( A201 and (not A200) );
a4624a <=( A199 and a4623a );
a4625a <=( a4624a and a4619a );
a4628a <=( A298 and A203 );
a4632a <=( A301 and A300 );
a4633a <=( (not A299) and a4632a );
a4634a <=( a4633a and a4628a );
a4637a <=( (not A168) and A169 );
a4641a <=( A201 and (not A200) );
a4642a <=( A199 and a4641a );
a4643a <=( a4642a and a4637a );
a4646a <=( A298 and A203 );
a4650a <=( A302 and A300 );
a4651a <=( (not A299) and a4650a );
a4652a <=( a4651a and a4646a );
a4655a <=( (not A168) and A169 );
a4659a <=( A201 and (not A200) );
a4660a <=( A199 and a4659a );
a4661a <=( a4660a and a4655a );
a4664a <=( (not A298) and A203 );
a4668a <=( A301 and A300 );
a4669a <=( A299 and a4668a );
a4670a <=( a4669a and a4664a );
a4673a <=( (not A168) and A169 );
a4677a <=( A201 and (not A200) );
a4678a <=( A199 and a4677a );
a4679a <=( a4678a and a4673a );
a4682a <=( (not A298) and A203 );
a4686a <=( A302 and A300 );
a4687a <=( A299 and a4686a );
a4688a <=( a4687a and a4682a );
a4691a <=( (not A169) and A170 );
a4695a <=( (not A166) and A167 );
a4696a <=( (not A168) and a4695a );
a4697a <=( a4696a and a4691a );
a4700a <=( A233 and (not A232) );
a4704a <=( (not A236) and (not A235) );
a4705a <=( (not A234) and a4704a );
a4706a <=( a4705a and a4700a );
a4709a <=( (not A169) and A170 );
a4713a <=( (not A166) and A167 );
a4714a <=( (not A168) and a4713a );
a4715a <=( a4714a and a4709a );
a4718a <=( (not A233) and A232 );
a4722a <=( (not A236) and (not A235) );
a4723a <=( (not A234) and a4722a );
a4724a <=( a4723a and a4718a );
a4727a <=( (not A169) and A170 );
a4731a <=( A166 and (not A167) );
a4732a <=( (not A168) and a4731a );
a4733a <=( a4732a and a4727a );
a4736a <=( A233 and (not A232) );
a4740a <=( (not A236) and (not A235) );
a4741a <=( (not A234) and a4740a );
a4742a <=( a4741a and a4736a );
a4745a <=( (not A169) and A170 );
a4749a <=( A166 and (not A167) );
a4750a <=( (not A168) and a4749a );
a4751a <=( a4750a and a4745a );
a4754a <=( (not A233) and A232 );
a4758a <=( (not A236) and (not A235) );
a4759a <=( (not A234) and a4758a );
a4760a <=( a4759a and a4754a );
a4763a <=( A166 and A167 );
a4767a <=( A201 and A200 );
a4768a <=( (not A199) and a4767a );
a4769a <=( a4768a and a4763a );
a4773a <=( (not A299) and A298 );
a4774a <=( A202 and a4773a );
a4778a <=( (not A302) and (not A301) );
a4779a <=( (not A300) and a4778a );
a4780a <=( a4779a and a4774a );
a4783a <=( A166 and A167 );
a4787a <=( A201 and A200 );
a4788a <=( (not A199) and a4787a );
a4789a <=( a4788a and a4783a );
a4793a <=( A299 and (not A298) );
a4794a <=( A202 and a4793a );
a4798a <=( (not A302) and (not A301) );
a4799a <=( (not A300) and a4798a );
a4800a <=( a4799a and a4794a );
a4803a <=( A166 and A167 );
a4807a <=( A201 and A200 );
a4808a <=( (not A199) and a4807a );
a4809a <=( a4808a and a4803a );
a4813a <=( (not A299) and A298 );
a4814a <=( A203 and a4813a );
a4818a <=( (not A302) and (not A301) );
a4819a <=( (not A300) and a4818a );
a4820a <=( a4819a and a4814a );
a4823a <=( A166 and A167 );
a4827a <=( A201 and A200 );
a4828a <=( (not A199) and a4827a );
a4829a <=( a4828a and a4823a );
a4833a <=( A299 and (not A298) );
a4834a <=( A203 and a4833a );
a4838a <=( (not A302) and (not A301) );
a4839a <=( (not A300) and a4838a );
a4840a <=( a4839a and a4834a );
a4843a <=( A166 and A167 );
a4847a <=( (not A201) and A200 );
a4848a <=( (not A199) and a4847a );
a4849a <=( a4848a and a4843a );
a4853a <=( A298 and (not A203) );
a4854a <=( (not A202) and a4853a );
a4858a <=( A301 and A300 );
a4859a <=( (not A299) and a4858a );
a4860a <=( a4859a and a4854a );
a4863a <=( A166 and A167 );
a4867a <=( (not A201) and A200 );
a4868a <=( (not A199) and a4867a );
a4869a <=( a4868a and a4863a );
a4873a <=( A298 and (not A203) );
a4874a <=( (not A202) and a4873a );
a4878a <=( A302 and A300 );
a4879a <=( (not A299) and a4878a );
a4880a <=( a4879a and a4874a );
a4883a <=( A166 and A167 );
a4887a <=( (not A201) and A200 );
a4888a <=( (not A199) and a4887a );
a4889a <=( a4888a and a4883a );
a4893a <=( (not A298) and (not A203) );
a4894a <=( (not A202) and a4893a );
a4898a <=( A301 and A300 );
a4899a <=( A299 and a4898a );
a4900a <=( a4899a and a4894a );
a4903a <=( A166 and A167 );
a4907a <=( (not A201) and A200 );
a4908a <=( (not A199) and a4907a );
a4909a <=( a4908a and a4903a );
a4913a <=( (not A298) and (not A203) );
a4914a <=( (not A202) and a4913a );
a4918a <=( A302 and A300 );
a4919a <=( A299 and a4918a );
a4920a <=( a4919a and a4914a );
a4923a <=( A166 and A167 );
a4927a <=( A201 and (not A200) );
a4928a <=( A199 and a4927a );
a4929a <=( a4928a and a4923a );
a4933a <=( (not A299) and A298 );
a4934a <=( A202 and a4933a );
a4938a <=( (not A302) and (not A301) );
a4939a <=( (not A300) and a4938a );
a4940a <=( a4939a and a4934a );
a4943a <=( A166 and A167 );
a4947a <=( A201 and (not A200) );
a4948a <=( A199 and a4947a );
a4949a <=( a4948a and a4943a );
a4953a <=( A299 and (not A298) );
a4954a <=( A202 and a4953a );
a4958a <=( (not A302) and (not A301) );
a4959a <=( (not A300) and a4958a );
a4960a <=( a4959a and a4954a );
a4963a <=( A166 and A167 );
a4967a <=( A201 and (not A200) );
a4968a <=( A199 and a4967a );
a4969a <=( a4968a and a4963a );
a4973a <=( (not A299) and A298 );
a4974a <=( A203 and a4973a );
a4978a <=( (not A302) and (not A301) );
a4979a <=( (not A300) and a4978a );
a4980a <=( a4979a and a4974a );
a4983a <=( A166 and A167 );
a4987a <=( A201 and (not A200) );
a4988a <=( A199 and a4987a );
a4989a <=( a4988a and a4983a );
a4993a <=( A299 and (not A298) );
a4994a <=( A203 and a4993a );
a4998a <=( (not A302) and (not A301) );
a4999a <=( (not A300) and a4998a );
a5000a <=( a4999a and a4994a );
a5003a <=( A166 and A167 );
a5007a <=( (not A201) and (not A200) );
a5008a <=( A199 and a5007a );
a5009a <=( a5008a and a5003a );
a5013a <=( A298 and (not A203) );
a5014a <=( (not A202) and a5013a );
a5018a <=( A301 and A300 );
a5019a <=( (not A299) and a5018a );
a5020a <=( a5019a and a5014a );
a5023a <=( A166 and A167 );
a5027a <=( (not A201) and (not A200) );
a5028a <=( A199 and a5027a );
a5029a <=( a5028a and a5023a );
a5033a <=( A298 and (not A203) );
a5034a <=( (not A202) and a5033a );
a5038a <=( A302 and A300 );
a5039a <=( (not A299) and a5038a );
a5040a <=( a5039a and a5034a );
a5043a <=( A166 and A167 );
a5047a <=( (not A201) and (not A200) );
a5048a <=( A199 and a5047a );
a5049a <=( a5048a and a5043a );
a5053a <=( (not A298) and (not A203) );
a5054a <=( (not A202) and a5053a );
a5058a <=( A301 and A300 );
a5059a <=( A299 and a5058a );
a5060a <=( a5059a and a5054a );
a5063a <=( A166 and A167 );
a5067a <=( (not A201) and (not A200) );
a5068a <=( A199 and a5067a );
a5069a <=( a5068a and a5063a );
a5073a <=( (not A298) and (not A203) );
a5074a <=( (not A202) and a5073a );
a5078a <=( A302 and A300 );
a5079a <=( A299 and a5078a );
a5080a <=( a5079a and a5074a );
a5083a <=( (not A166) and (not A167) );
a5087a <=( A201 and A200 );
a5088a <=( (not A199) and a5087a );
a5089a <=( a5088a and a5083a );
a5093a <=( (not A299) and A298 );
a5094a <=( A202 and a5093a );
a5098a <=( (not A302) and (not A301) );
a5099a <=( (not A300) and a5098a );
a5100a <=( a5099a and a5094a );
a5103a <=( (not A166) and (not A167) );
a5107a <=( A201 and A200 );
a5108a <=( (not A199) and a5107a );
a5109a <=( a5108a and a5103a );
a5113a <=( A299 and (not A298) );
a5114a <=( A202 and a5113a );
a5118a <=( (not A302) and (not A301) );
a5119a <=( (not A300) and a5118a );
a5120a <=( a5119a and a5114a );
a5123a <=( (not A166) and (not A167) );
a5127a <=( A201 and A200 );
a5128a <=( (not A199) and a5127a );
a5129a <=( a5128a and a5123a );
a5133a <=( (not A299) and A298 );
a5134a <=( A203 and a5133a );
a5138a <=( (not A302) and (not A301) );
a5139a <=( (not A300) and a5138a );
a5140a <=( a5139a and a5134a );
a5143a <=( (not A166) and (not A167) );
a5147a <=( A201 and A200 );
a5148a <=( (not A199) and a5147a );
a5149a <=( a5148a and a5143a );
a5153a <=( A299 and (not A298) );
a5154a <=( A203 and a5153a );
a5158a <=( (not A302) and (not A301) );
a5159a <=( (not A300) and a5158a );
a5160a <=( a5159a and a5154a );
a5163a <=( (not A166) and (not A167) );
a5167a <=( (not A201) and A200 );
a5168a <=( (not A199) and a5167a );
a5169a <=( a5168a and a5163a );
a5173a <=( A298 and (not A203) );
a5174a <=( (not A202) and a5173a );
a5178a <=( A301 and A300 );
a5179a <=( (not A299) and a5178a );
a5180a <=( a5179a and a5174a );
a5183a <=( (not A166) and (not A167) );
a5187a <=( (not A201) and A200 );
a5188a <=( (not A199) and a5187a );
a5189a <=( a5188a and a5183a );
a5193a <=( A298 and (not A203) );
a5194a <=( (not A202) and a5193a );
a5198a <=( A302 and A300 );
a5199a <=( (not A299) and a5198a );
a5200a <=( a5199a and a5194a );
a5203a <=( (not A166) and (not A167) );
a5207a <=( (not A201) and A200 );
a5208a <=( (not A199) and a5207a );
a5209a <=( a5208a and a5203a );
a5213a <=( (not A298) and (not A203) );
a5214a <=( (not A202) and a5213a );
a5218a <=( A301 and A300 );
a5219a <=( A299 and a5218a );
a5220a <=( a5219a and a5214a );
a5223a <=( (not A166) and (not A167) );
a5227a <=( (not A201) and A200 );
a5228a <=( (not A199) and a5227a );
a5229a <=( a5228a and a5223a );
a5233a <=( (not A298) and (not A203) );
a5234a <=( (not A202) and a5233a );
a5238a <=( A302 and A300 );
a5239a <=( A299 and a5238a );
a5240a <=( a5239a and a5234a );
a5243a <=( (not A166) and (not A167) );
a5247a <=( A201 and (not A200) );
a5248a <=( A199 and a5247a );
a5249a <=( a5248a and a5243a );
a5253a <=( (not A299) and A298 );
a5254a <=( A202 and a5253a );
a5258a <=( (not A302) and (not A301) );
a5259a <=( (not A300) and a5258a );
a5260a <=( a5259a and a5254a );
a5263a <=( (not A166) and (not A167) );
a5267a <=( A201 and (not A200) );
a5268a <=( A199 and a5267a );
a5269a <=( a5268a and a5263a );
a5273a <=( A299 and (not A298) );
a5274a <=( A202 and a5273a );
a5278a <=( (not A302) and (not A301) );
a5279a <=( (not A300) and a5278a );
a5280a <=( a5279a and a5274a );
a5283a <=( (not A166) and (not A167) );
a5287a <=( A201 and (not A200) );
a5288a <=( A199 and a5287a );
a5289a <=( a5288a and a5283a );
a5293a <=( (not A299) and A298 );
a5294a <=( A203 and a5293a );
a5298a <=( (not A302) and (not A301) );
a5299a <=( (not A300) and a5298a );
a5300a <=( a5299a and a5294a );
a5303a <=( (not A166) and (not A167) );
a5307a <=( A201 and (not A200) );
a5308a <=( A199 and a5307a );
a5309a <=( a5308a and a5303a );
a5313a <=( A299 and (not A298) );
a5314a <=( A203 and a5313a );
a5318a <=( (not A302) and (not A301) );
a5319a <=( (not A300) and a5318a );
a5320a <=( a5319a and a5314a );
a5323a <=( (not A166) and (not A167) );
a5327a <=( (not A201) and (not A200) );
a5328a <=( A199 and a5327a );
a5329a <=( a5328a and a5323a );
a5333a <=( A298 and (not A203) );
a5334a <=( (not A202) and a5333a );
a5338a <=( A301 and A300 );
a5339a <=( (not A299) and a5338a );
a5340a <=( a5339a and a5334a );
a5343a <=( (not A166) and (not A167) );
a5347a <=( (not A201) and (not A200) );
a5348a <=( A199 and a5347a );
a5349a <=( a5348a and a5343a );
a5353a <=( A298 and (not A203) );
a5354a <=( (not A202) and a5353a );
a5358a <=( A302 and A300 );
a5359a <=( (not A299) and a5358a );
a5360a <=( a5359a and a5354a );
a5363a <=( (not A166) and (not A167) );
a5367a <=( (not A201) and (not A200) );
a5368a <=( A199 and a5367a );
a5369a <=( a5368a and a5363a );
a5373a <=( (not A298) and (not A203) );
a5374a <=( (not A202) and a5373a );
a5378a <=( A301 and A300 );
a5379a <=( A299 and a5378a );
a5380a <=( a5379a and a5374a );
a5383a <=( (not A166) and (not A167) );
a5387a <=( (not A201) and (not A200) );
a5388a <=( A199 and a5387a );
a5389a <=( a5388a and a5383a );
a5393a <=( (not A298) and (not A203) );
a5394a <=( (not A202) and a5393a );
a5398a <=( A302 and A300 );
a5399a <=( A299 and a5398a );
a5400a <=( a5399a and a5394a );
a5403a <=( A168 and (not A170) );
a5407a <=( A201 and (not A166) );
a5408a <=( A167 and a5407a );
a5409a <=( a5408a and a5403a );
a5413a <=( A298 and (not A203) );
a5414a <=( (not A202) and a5413a );
a5418a <=( A301 and A300 );
a5419a <=( (not A299) and a5418a );
a5420a <=( a5419a and a5414a );
a5423a <=( A168 and (not A170) );
a5427a <=( A201 and (not A166) );
a5428a <=( A167 and a5427a );
a5429a <=( a5428a and a5423a );
a5433a <=( A298 and (not A203) );
a5434a <=( (not A202) and a5433a );
a5438a <=( A302 and A300 );
a5439a <=( (not A299) and a5438a );
a5440a <=( a5439a and a5434a );
a5443a <=( A168 and (not A170) );
a5447a <=( A201 and (not A166) );
a5448a <=( A167 and a5447a );
a5449a <=( a5448a and a5443a );
a5453a <=( (not A298) and (not A203) );
a5454a <=( (not A202) and a5453a );
a5458a <=( A301 and A300 );
a5459a <=( A299 and a5458a );
a5460a <=( a5459a and a5454a );
a5463a <=( A168 and (not A170) );
a5467a <=( A201 and (not A166) );
a5468a <=( A167 and a5467a );
a5469a <=( a5468a and a5463a );
a5473a <=( (not A298) and (not A203) );
a5474a <=( (not A202) and a5473a );
a5478a <=( A302 and A300 );
a5479a <=( A299 and a5478a );
a5480a <=( a5479a and a5474a );
a5483a <=( A168 and (not A170) );
a5487a <=( (not A201) and (not A166) );
a5488a <=( A167 and a5487a );
a5489a <=( a5488a and a5483a );
a5493a <=( (not A299) and A298 );
a5494a <=( A202 and a5493a );
a5498a <=( (not A302) and (not A301) );
a5499a <=( (not A300) and a5498a );
a5500a <=( a5499a and a5494a );
a5503a <=( A168 and (not A170) );
a5507a <=( (not A201) and (not A166) );
a5508a <=( A167 and a5507a );
a5509a <=( a5508a and a5503a );
a5513a <=( A299 and (not A298) );
a5514a <=( A202 and a5513a );
a5518a <=( (not A302) and (not A301) );
a5519a <=( (not A300) and a5518a );
a5520a <=( a5519a and a5514a );
a5523a <=( A168 and (not A170) );
a5527a <=( (not A201) and (not A166) );
a5528a <=( A167 and a5527a );
a5529a <=( a5528a and a5523a );
a5533a <=( (not A299) and A298 );
a5534a <=( A203 and a5533a );
a5538a <=( (not A302) and (not A301) );
a5539a <=( (not A300) and a5538a );
a5540a <=( a5539a and a5534a );
a5543a <=( A168 and (not A170) );
a5547a <=( (not A201) and (not A166) );
a5548a <=( A167 and a5547a );
a5549a <=( a5548a and a5543a );
a5553a <=( A299 and (not A298) );
a5554a <=( A203 and a5553a );
a5558a <=( (not A302) and (not A301) );
a5559a <=( (not A300) and a5558a );
a5560a <=( a5559a and a5554a );
a5563a <=( A168 and (not A170) );
a5567a <=( A199 and (not A166) );
a5568a <=( A167 and a5567a );
a5569a <=( a5568a and a5563a );
a5573a <=( (not A299) and A298 );
a5574a <=( A200 and a5573a );
a5578a <=( (not A302) and (not A301) );
a5579a <=( (not A300) and a5578a );
a5580a <=( a5579a and a5574a );
a5583a <=( A168 and (not A170) );
a5587a <=( A199 and (not A166) );
a5588a <=( A167 and a5587a );
a5589a <=( a5588a and a5583a );
a5593a <=( A299 and (not A298) );
a5594a <=( A200 and a5593a );
a5598a <=( (not A302) and (not A301) );
a5599a <=( (not A300) and a5598a );
a5600a <=( a5599a and a5594a );
a5603a <=( A168 and (not A170) );
a5607a <=( (not A199) and (not A166) );
a5608a <=( A167 and a5607a );
a5609a <=( a5608a and a5603a );
a5613a <=( (not A299) and A298 );
a5614a <=( (not A200) and a5613a );
a5618a <=( (not A302) and (not A301) );
a5619a <=( (not A300) and a5618a );
a5620a <=( a5619a and a5614a );
a5623a <=( A168 and (not A170) );
a5627a <=( (not A199) and (not A166) );
a5628a <=( A167 and a5627a );
a5629a <=( a5628a and a5623a );
a5633a <=( A299 and (not A298) );
a5634a <=( (not A200) and a5633a );
a5638a <=( (not A302) and (not A301) );
a5639a <=( (not A300) and a5638a );
a5640a <=( a5639a and a5634a );
a5643a <=( A168 and (not A170) );
a5647a <=( A201 and A166 );
a5648a <=( (not A167) and a5647a );
a5649a <=( a5648a and a5643a );
a5653a <=( A298 and (not A203) );
a5654a <=( (not A202) and a5653a );
a5658a <=( A301 and A300 );
a5659a <=( (not A299) and a5658a );
a5660a <=( a5659a and a5654a );
a5663a <=( A168 and (not A170) );
a5667a <=( A201 and A166 );
a5668a <=( (not A167) and a5667a );
a5669a <=( a5668a and a5663a );
a5673a <=( A298 and (not A203) );
a5674a <=( (not A202) and a5673a );
a5678a <=( A302 and A300 );
a5679a <=( (not A299) and a5678a );
a5680a <=( a5679a and a5674a );
a5683a <=( A168 and (not A170) );
a5687a <=( A201 and A166 );
a5688a <=( (not A167) and a5687a );
a5689a <=( a5688a and a5683a );
a5693a <=( (not A298) and (not A203) );
a5694a <=( (not A202) and a5693a );
a5698a <=( A301 and A300 );
a5699a <=( A299 and a5698a );
a5700a <=( a5699a and a5694a );
a5703a <=( A168 and (not A170) );
a5707a <=( A201 and A166 );
a5708a <=( (not A167) and a5707a );
a5709a <=( a5708a and a5703a );
a5713a <=( (not A298) and (not A203) );
a5714a <=( (not A202) and a5713a );
a5718a <=( A302 and A300 );
a5719a <=( A299 and a5718a );
a5720a <=( a5719a and a5714a );
a5723a <=( A168 and (not A170) );
a5727a <=( (not A201) and A166 );
a5728a <=( (not A167) and a5727a );
a5729a <=( a5728a and a5723a );
a5733a <=( (not A299) and A298 );
a5734a <=( A202 and a5733a );
a5738a <=( (not A302) and (not A301) );
a5739a <=( (not A300) and a5738a );
a5740a <=( a5739a and a5734a );
a5743a <=( A168 and (not A170) );
a5747a <=( (not A201) and A166 );
a5748a <=( (not A167) and a5747a );
a5749a <=( a5748a and a5743a );
a5753a <=( A299 and (not A298) );
a5754a <=( A202 and a5753a );
a5758a <=( (not A302) and (not A301) );
a5759a <=( (not A300) and a5758a );
a5760a <=( a5759a and a5754a );
a5763a <=( A168 and (not A170) );
a5767a <=( (not A201) and A166 );
a5768a <=( (not A167) and a5767a );
a5769a <=( a5768a and a5763a );
a5773a <=( (not A299) and A298 );
a5774a <=( A203 and a5773a );
a5778a <=( (not A302) and (not A301) );
a5779a <=( (not A300) and a5778a );
a5780a <=( a5779a and a5774a );
a5783a <=( A168 and (not A170) );
a5787a <=( (not A201) and A166 );
a5788a <=( (not A167) and a5787a );
a5789a <=( a5788a and a5783a );
a5793a <=( A299 and (not A298) );
a5794a <=( A203 and a5793a );
a5798a <=( (not A302) and (not A301) );
a5799a <=( (not A300) and a5798a );
a5800a <=( a5799a and a5794a );
a5803a <=( A168 and (not A170) );
a5807a <=( A199 and A166 );
a5808a <=( (not A167) and a5807a );
a5809a <=( a5808a and a5803a );
a5813a <=( (not A299) and A298 );
a5814a <=( A200 and a5813a );
a5818a <=( (not A302) and (not A301) );
a5819a <=( (not A300) and a5818a );
a5820a <=( a5819a and a5814a );
a5823a <=( A168 and (not A170) );
a5827a <=( A199 and A166 );
a5828a <=( (not A167) and a5827a );
a5829a <=( a5828a and a5823a );
a5833a <=( A299 and (not A298) );
a5834a <=( A200 and a5833a );
a5838a <=( (not A302) and (not A301) );
a5839a <=( (not A300) and a5838a );
a5840a <=( a5839a and a5834a );
a5843a <=( A168 and (not A170) );
a5847a <=( (not A199) and A166 );
a5848a <=( (not A167) and a5847a );
a5849a <=( a5848a and a5843a );
a5853a <=( (not A299) and A298 );
a5854a <=( (not A200) and a5853a );
a5858a <=( (not A302) and (not A301) );
a5859a <=( (not A300) and a5858a );
a5860a <=( a5859a and a5854a );
a5863a <=( A168 and (not A170) );
a5867a <=( (not A199) and A166 );
a5868a <=( (not A167) and a5867a );
a5869a <=( a5868a and a5863a );
a5873a <=( A299 and (not A298) );
a5874a <=( (not A200) and a5873a );
a5878a <=( (not A302) and (not A301) );
a5879a <=( (not A300) and a5878a );
a5880a <=( a5879a and a5874a );
a5883a <=( (not A168) and (not A170) );
a5887a <=( A201 and A200 );
a5888a <=( (not A199) and a5887a );
a5889a <=( a5888a and a5883a );
a5893a <=( (not A299) and A298 );
a5894a <=( A202 and a5893a );
a5898a <=( (not A302) and (not A301) );
a5899a <=( (not A300) and a5898a );
a5900a <=( a5899a and a5894a );
a5903a <=( (not A168) and (not A170) );
a5907a <=( A201 and A200 );
a5908a <=( (not A199) and a5907a );
a5909a <=( a5908a and a5903a );
a5913a <=( A299 and (not A298) );
a5914a <=( A202 and a5913a );
a5918a <=( (not A302) and (not A301) );
a5919a <=( (not A300) and a5918a );
a5920a <=( a5919a and a5914a );
a5923a <=( (not A168) and (not A170) );
a5927a <=( A201 and A200 );
a5928a <=( (not A199) and a5927a );
a5929a <=( a5928a and a5923a );
a5933a <=( (not A299) and A298 );
a5934a <=( A203 and a5933a );
a5938a <=( (not A302) and (not A301) );
a5939a <=( (not A300) and a5938a );
a5940a <=( a5939a and a5934a );
a5943a <=( (not A168) and (not A170) );
a5947a <=( A201 and A200 );
a5948a <=( (not A199) and a5947a );
a5949a <=( a5948a and a5943a );
a5953a <=( A299 and (not A298) );
a5954a <=( A203 and a5953a );
a5958a <=( (not A302) and (not A301) );
a5959a <=( (not A300) and a5958a );
a5960a <=( a5959a and a5954a );
a5963a <=( (not A168) and (not A170) );
a5967a <=( (not A201) and A200 );
a5968a <=( (not A199) and a5967a );
a5969a <=( a5968a and a5963a );
a5973a <=( A298 and (not A203) );
a5974a <=( (not A202) and a5973a );
a5978a <=( A301 and A300 );
a5979a <=( (not A299) and a5978a );
a5980a <=( a5979a and a5974a );
a5983a <=( (not A168) and (not A170) );
a5987a <=( (not A201) and A200 );
a5988a <=( (not A199) and a5987a );
a5989a <=( a5988a and a5983a );
a5993a <=( A298 and (not A203) );
a5994a <=( (not A202) and a5993a );
a5998a <=( A302 and A300 );
a5999a <=( (not A299) and a5998a );
a6000a <=( a5999a and a5994a );
a6003a <=( (not A168) and (not A170) );
a6007a <=( (not A201) and A200 );
a6008a <=( (not A199) and a6007a );
a6009a <=( a6008a and a6003a );
a6013a <=( (not A298) and (not A203) );
a6014a <=( (not A202) and a6013a );
a6018a <=( A301 and A300 );
a6019a <=( A299 and a6018a );
a6020a <=( a6019a and a6014a );
a6023a <=( (not A168) and (not A170) );
a6027a <=( (not A201) and A200 );
a6028a <=( (not A199) and a6027a );
a6029a <=( a6028a and a6023a );
a6033a <=( (not A298) and (not A203) );
a6034a <=( (not A202) and a6033a );
a6038a <=( A302 and A300 );
a6039a <=( A299 and a6038a );
a6040a <=( a6039a and a6034a );
a6043a <=( (not A168) and (not A170) );
a6047a <=( A201 and (not A200) );
a6048a <=( A199 and a6047a );
a6049a <=( a6048a and a6043a );
a6053a <=( (not A299) and A298 );
a6054a <=( A202 and a6053a );
a6058a <=( (not A302) and (not A301) );
a6059a <=( (not A300) and a6058a );
a6060a <=( a6059a and a6054a );
a6063a <=( (not A168) and (not A170) );
a6067a <=( A201 and (not A200) );
a6068a <=( A199 and a6067a );
a6069a <=( a6068a and a6063a );
a6073a <=( A299 and (not A298) );
a6074a <=( A202 and a6073a );
a6078a <=( (not A302) and (not A301) );
a6079a <=( (not A300) and a6078a );
a6080a <=( a6079a and a6074a );
a6083a <=( (not A168) and (not A170) );
a6087a <=( A201 and (not A200) );
a6088a <=( A199 and a6087a );
a6089a <=( a6088a and a6083a );
a6093a <=( (not A299) and A298 );
a6094a <=( A203 and a6093a );
a6098a <=( (not A302) and (not A301) );
a6099a <=( (not A300) and a6098a );
a6100a <=( a6099a and a6094a );
a6103a <=( (not A168) and (not A170) );
a6107a <=( A201 and (not A200) );
a6108a <=( A199 and a6107a );
a6109a <=( a6108a and a6103a );
a6113a <=( A299 and (not A298) );
a6114a <=( A203 and a6113a );
a6118a <=( (not A302) and (not A301) );
a6119a <=( (not A300) and a6118a );
a6120a <=( a6119a and a6114a );
a6123a <=( (not A168) and (not A170) );
a6127a <=( (not A201) and (not A200) );
a6128a <=( A199 and a6127a );
a6129a <=( a6128a and a6123a );
a6133a <=( A298 and (not A203) );
a6134a <=( (not A202) and a6133a );
a6138a <=( A301 and A300 );
a6139a <=( (not A299) and a6138a );
a6140a <=( a6139a and a6134a );
a6143a <=( (not A168) and (not A170) );
a6147a <=( (not A201) and (not A200) );
a6148a <=( A199 and a6147a );
a6149a <=( a6148a and a6143a );
a6153a <=( A298 and (not A203) );
a6154a <=( (not A202) and a6153a );
a6158a <=( A302 and A300 );
a6159a <=( (not A299) and a6158a );
a6160a <=( a6159a and a6154a );
a6163a <=( (not A168) and (not A170) );
a6167a <=( (not A201) and (not A200) );
a6168a <=( A199 and a6167a );
a6169a <=( a6168a and a6163a );
a6173a <=( (not A298) and (not A203) );
a6174a <=( (not A202) and a6173a );
a6178a <=( A301 and A300 );
a6179a <=( A299 and a6178a );
a6180a <=( a6179a and a6174a );
a6183a <=( (not A168) and (not A170) );
a6187a <=( (not A201) and (not A200) );
a6188a <=( A199 and a6187a );
a6189a <=( a6188a and a6183a );
a6193a <=( (not A298) and (not A203) );
a6194a <=( (not A202) and a6193a );
a6198a <=( A302 and A300 );
a6199a <=( A299 and a6198a );
a6200a <=( a6199a and a6194a );
a6203a <=( A168 and A169 );
a6207a <=( A201 and (not A166) );
a6208a <=( A167 and a6207a );
a6209a <=( a6208a and a6203a );
a6213a <=( A298 and (not A203) );
a6214a <=( (not A202) and a6213a );
a6218a <=( A301 and A300 );
a6219a <=( (not A299) and a6218a );
a6220a <=( a6219a and a6214a );
a6223a <=( A168 and A169 );
a6227a <=( A201 and (not A166) );
a6228a <=( A167 and a6227a );
a6229a <=( a6228a and a6223a );
a6233a <=( A298 and (not A203) );
a6234a <=( (not A202) and a6233a );
a6238a <=( A302 and A300 );
a6239a <=( (not A299) and a6238a );
a6240a <=( a6239a and a6234a );
a6243a <=( A168 and A169 );
a6247a <=( A201 and (not A166) );
a6248a <=( A167 and a6247a );
a6249a <=( a6248a and a6243a );
a6253a <=( (not A298) and (not A203) );
a6254a <=( (not A202) and a6253a );
a6258a <=( A301 and A300 );
a6259a <=( A299 and a6258a );
a6260a <=( a6259a and a6254a );
a6263a <=( A168 and A169 );
a6267a <=( A201 and (not A166) );
a6268a <=( A167 and a6267a );
a6269a <=( a6268a and a6263a );
a6273a <=( (not A298) and (not A203) );
a6274a <=( (not A202) and a6273a );
a6278a <=( A302 and A300 );
a6279a <=( A299 and a6278a );
a6280a <=( a6279a and a6274a );
a6283a <=( A168 and A169 );
a6287a <=( (not A201) and (not A166) );
a6288a <=( A167 and a6287a );
a6289a <=( a6288a and a6283a );
a6293a <=( (not A299) and A298 );
a6294a <=( A202 and a6293a );
a6298a <=( (not A302) and (not A301) );
a6299a <=( (not A300) and a6298a );
a6300a <=( a6299a and a6294a );
a6303a <=( A168 and A169 );
a6307a <=( (not A201) and (not A166) );
a6308a <=( A167 and a6307a );
a6309a <=( a6308a and a6303a );
a6313a <=( A299 and (not A298) );
a6314a <=( A202 and a6313a );
a6318a <=( (not A302) and (not A301) );
a6319a <=( (not A300) and a6318a );
a6320a <=( a6319a and a6314a );
a6323a <=( A168 and A169 );
a6327a <=( (not A201) and (not A166) );
a6328a <=( A167 and a6327a );
a6329a <=( a6328a and a6323a );
a6333a <=( (not A299) and A298 );
a6334a <=( A203 and a6333a );
a6338a <=( (not A302) and (not A301) );
a6339a <=( (not A300) and a6338a );
a6340a <=( a6339a and a6334a );
a6343a <=( A168 and A169 );
a6347a <=( (not A201) and (not A166) );
a6348a <=( A167 and a6347a );
a6349a <=( a6348a and a6343a );
a6353a <=( A299 and (not A298) );
a6354a <=( A203 and a6353a );
a6358a <=( (not A302) and (not A301) );
a6359a <=( (not A300) and a6358a );
a6360a <=( a6359a and a6354a );
a6363a <=( A168 and A169 );
a6367a <=( A199 and (not A166) );
a6368a <=( A167 and a6367a );
a6369a <=( a6368a and a6363a );
a6373a <=( (not A299) and A298 );
a6374a <=( A200 and a6373a );
a6378a <=( (not A302) and (not A301) );
a6379a <=( (not A300) and a6378a );
a6380a <=( a6379a and a6374a );
a6383a <=( A168 and A169 );
a6387a <=( A199 and (not A166) );
a6388a <=( A167 and a6387a );
a6389a <=( a6388a and a6383a );
a6393a <=( A299 and (not A298) );
a6394a <=( A200 and a6393a );
a6398a <=( (not A302) and (not A301) );
a6399a <=( (not A300) and a6398a );
a6400a <=( a6399a and a6394a );
a6403a <=( A168 and A169 );
a6407a <=( (not A199) and (not A166) );
a6408a <=( A167 and a6407a );
a6409a <=( a6408a and a6403a );
a6413a <=( (not A299) and A298 );
a6414a <=( (not A200) and a6413a );
a6418a <=( (not A302) and (not A301) );
a6419a <=( (not A300) and a6418a );
a6420a <=( a6419a and a6414a );
a6423a <=( A168 and A169 );
a6427a <=( (not A199) and (not A166) );
a6428a <=( A167 and a6427a );
a6429a <=( a6428a and a6423a );
a6433a <=( A299 and (not A298) );
a6434a <=( (not A200) and a6433a );
a6438a <=( (not A302) and (not A301) );
a6439a <=( (not A300) and a6438a );
a6440a <=( a6439a and a6434a );
a6443a <=( A168 and A169 );
a6447a <=( A201 and A166 );
a6448a <=( (not A167) and a6447a );
a6449a <=( a6448a and a6443a );
a6453a <=( A298 and (not A203) );
a6454a <=( (not A202) and a6453a );
a6458a <=( A301 and A300 );
a6459a <=( (not A299) and a6458a );
a6460a <=( a6459a and a6454a );
a6463a <=( A168 and A169 );
a6467a <=( A201 and A166 );
a6468a <=( (not A167) and a6467a );
a6469a <=( a6468a and a6463a );
a6473a <=( A298 and (not A203) );
a6474a <=( (not A202) and a6473a );
a6478a <=( A302 and A300 );
a6479a <=( (not A299) and a6478a );
a6480a <=( a6479a and a6474a );
a6483a <=( A168 and A169 );
a6487a <=( A201 and A166 );
a6488a <=( (not A167) and a6487a );
a6489a <=( a6488a and a6483a );
a6493a <=( (not A298) and (not A203) );
a6494a <=( (not A202) and a6493a );
a6498a <=( A301 and A300 );
a6499a <=( A299 and a6498a );
a6500a <=( a6499a and a6494a );
a6503a <=( A168 and A169 );
a6507a <=( A201 and A166 );
a6508a <=( (not A167) and a6507a );
a6509a <=( a6508a and a6503a );
a6513a <=( (not A298) and (not A203) );
a6514a <=( (not A202) and a6513a );
a6518a <=( A302 and A300 );
a6519a <=( A299 and a6518a );
a6520a <=( a6519a and a6514a );
a6523a <=( A168 and A169 );
a6527a <=( (not A201) and A166 );
a6528a <=( (not A167) and a6527a );
a6529a <=( a6528a and a6523a );
a6533a <=( (not A299) and A298 );
a6534a <=( A202 and a6533a );
a6538a <=( (not A302) and (not A301) );
a6539a <=( (not A300) and a6538a );
a6540a <=( a6539a and a6534a );
a6543a <=( A168 and A169 );
a6547a <=( (not A201) and A166 );
a6548a <=( (not A167) and a6547a );
a6549a <=( a6548a and a6543a );
a6553a <=( A299 and (not A298) );
a6554a <=( A202 and a6553a );
a6558a <=( (not A302) and (not A301) );
a6559a <=( (not A300) and a6558a );
a6560a <=( a6559a and a6554a );
a6563a <=( A168 and A169 );
a6567a <=( (not A201) and A166 );
a6568a <=( (not A167) and a6567a );
a6569a <=( a6568a and a6563a );
a6573a <=( (not A299) and A298 );
a6574a <=( A203 and a6573a );
a6578a <=( (not A302) and (not A301) );
a6579a <=( (not A300) and a6578a );
a6580a <=( a6579a and a6574a );
a6583a <=( A168 and A169 );
a6587a <=( (not A201) and A166 );
a6588a <=( (not A167) and a6587a );
a6589a <=( a6588a and a6583a );
a6593a <=( A299 and (not A298) );
a6594a <=( A203 and a6593a );
a6598a <=( (not A302) and (not A301) );
a6599a <=( (not A300) and a6598a );
a6600a <=( a6599a and a6594a );
a6603a <=( A168 and A169 );
a6607a <=( A199 and A166 );
a6608a <=( (not A167) and a6607a );
a6609a <=( a6608a and a6603a );
a6613a <=( (not A299) and A298 );
a6614a <=( A200 and a6613a );
a6618a <=( (not A302) and (not A301) );
a6619a <=( (not A300) and a6618a );
a6620a <=( a6619a and a6614a );
a6623a <=( A168 and A169 );
a6627a <=( A199 and A166 );
a6628a <=( (not A167) and a6627a );
a6629a <=( a6628a and a6623a );
a6633a <=( A299 and (not A298) );
a6634a <=( A200 and a6633a );
a6638a <=( (not A302) and (not A301) );
a6639a <=( (not A300) and a6638a );
a6640a <=( a6639a and a6634a );
a6643a <=( A168 and A169 );
a6647a <=( (not A199) and A166 );
a6648a <=( (not A167) and a6647a );
a6649a <=( a6648a and a6643a );
a6653a <=( (not A299) and A298 );
a6654a <=( (not A200) and a6653a );
a6658a <=( (not A302) and (not A301) );
a6659a <=( (not A300) and a6658a );
a6660a <=( a6659a and a6654a );
a6663a <=( A168 and A169 );
a6667a <=( (not A199) and A166 );
a6668a <=( (not A167) and a6667a );
a6669a <=( a6668a and a6663a );
a6673a <=( A299 and (not A298) );
a6674a <=( (not A200) and a6673a );
a6678a <=( (not A302) and (not A301) );
a6679a <=( (not A300) and a6678a );
a6680a <=( a6679a and a6674a );
a6683a <=( (not A168) and A169 );
a6687a <=( A201 and A200 );
a6688a <=( (not A199) and a6687a );
a6689a <=( a6688a and a6683a );
a6693a <=( (not A299) and A298 );
a6694a <=( A202 and a6693a );
a6698a <=( (not A302) and (not A301) );
a6699a <=( (not A300) and a6698a );
a6700a <=( a6699a and a6694a );
a6703a <=( (not A168) and A169 );
a6707a <=( A201 and A200 );
a6708a <=( (not A199) and a6707a );
a6709a <=( a6708a and a6703a );
a6713a <=( A299 and (not A298) );
a6714a <=( A202 and a6713a );
a6718a <=( (not A302) and (not A301) );
a6719a <=( (not A300) and a6718a );
a6720a <=( a6719a and a6714a );
a6723a <=( (not A168) and A169 );
a6727a <=( A201 and A200 );
a6728a <=( (not A199) and a6727a );
a6729a <=( a6728a and a6723a );
a6733a <=( (not A299) and A298 );
a6734a <=( A203 and a6733a );
a6738a <=( (not A302) and (not A301) );
a6739a <=( (not A300) and a6738a );
a6740a <=( a6739a and a6734a );
a6743a <=( (not A168) and A169 );
a6747a <=( A201 and A200 );
a6748a <=( (not A199) and a6747a );
a6749a <=( a6748a and a6743a );
a6753a <=( A299 and (not A298) );
a6754a <=( A203 and a6753a );
a6758a <=( (not A302) and (not A301) );
a6759a <=( (not A300) and a6758a );
a6760a <=( a6759a and a6754a );
a6763a <=( (not A168) and A169 );
a6767a <=( (not A201) and A200 );
a6768a <=( (not A199) and a6767a );
a6769a <=( a6768a and a6763a );
a6773a <=( A298 and (not A203) );
a6774a <=( (not A202) and a6773a );
a6778a <=( A301 and A300 );
a6779a <=( (not A299) and a6778a );
a6780a <=( a6779a and a6774a );
a6783a <=( (not A168) and A169 );
a6787a <=( (not A201) and A200 );
a6788a <=( (not A199) and a6787a );
a6789a <=( a6788a and a6783a );
a6793a <=( A298 and (not A203) );
a6794a <=( (not A202) and a6793a );
a6798a <=( A302 and A300 );
a6799a <=( (not A299) and a6798a );
a6800a <=( a6799a and a6794a );
a6803a <=( (not A168) and A169 );
a6807a <=( (not A201) and A200 );
a6808a <=( (not A199) and a6807a );
a6809a <=( a6808a and a6803a );
a6813a <=( (not A298) and (not A203) );
a6814a <=( (not A202) and a6813a );
a6818a <=( A301 and A300 );
a6819a <=( A299 and a6818a );
a6820a <=( a6819a and a6814a );
a6823a <=( (not A168) and A169 );
a6827a <=( (not A201) and A200 );
a6828a <=( (not A199) and a6827a );
a6829a <=( a6828a and a6823a );
a6833a <=( (not A298) and (not A203) );
a6834a <=( (not A202) and a6833a );
a6838a <=( A302 and A300 );
a6839a <=( A299 and a6838a );
a6840a <=( a6839a and a6834a );
a6843a <=( (not A168) and A169 );
a6847a <=( A201 and (not A200) );
a6848a <=( A199 and a6847a );
a6849a <=( a6848a and a6843a );
a6853a <=( (not A299) and A298 );
a6854a <=( A202 and a6853a );
a6858a <=( (not A302) and (not A301) );
a6859a <=( (not A300) and a6858a );
a6860a <=( a6859a and a6854a );
a6863a <=( (not A168) and A169 );
a6867a <=( A201 and (not A200) );
a6868a <=( A199 and a6867a );
a6869a <=( a6868a and a6863a );
a6873a <=( A299 and (not A298) );
a6874a <=( A202 and a6873a );
a6878a <=( (not A302) and (not A301) );
a6879a <=( (not A300) and a6878a );
a6880a <=( a6879a and a6874a );
a6883a <=( (not A168) and A169 );
a6887a <=( A201 and (not A200) );
a6888a <=( A199 and a6887a );
a6889a <=( a6888a and a6883a );
a6893a <=( (not A299) and A298 );
a6894a <=( A203 and a6893a );
a6898a <=( (not A302) and (not A301) );
a6899a <=( (not A300) and a6898a );
a6900a <=( a6899a and a6894a );
a6903a <=( (not A168) and A169 );
a6907a <=( A201 and (not A200) );
a6908a <=( A199 and a6907a );
a6909a <=( a6908a and a6903a );
a6913a <=( A299 and (not A298) );
a6914a <=( A203 and a6913a );
a6918a <=( (not A302) and (not A301) );
a6919a <=( (not A300) and a6918a );
a6920a <=( a6919a and a6914a );
a6923a <=( (not A168) and A169 );
a6927a <=( (not A201) and (not A200) );
a6928a <=( A199 and a6927a );
a6929a <=( a6928a and a6923a );
a6933a <=( A298 and (not A203) );
a6934a <=( (not A202) and a6933a );
a6938a <=( A301 and A300 );
a6939a <=( (not A299) and a6938a );
a6940a <=( a6939a and a6934a );
a6943a <=( (not A168) and A169 );
a6947a <=( (not A201) and (not A200) );
a6948a <=( A199 and a6947a );
a6949a <=( a6948a and a6943a );
a6953a <=( A298 and (not A203) );
a6954a <=( (not A202) and a6953a );
a6958a <=( A302 and A300 );
a6959a <=( (not A299) and a6958a );
a6960a <=( a6959a and a6954a );
a6963a <=( (not A168) and A169 );
a6967a <=( (not A201) and (not A200) );
a6968a <=( A199 and a6967a );
a6969a <=( a6968a and a6963a );
a6973a <=( (not A298) and (not A203) );
a6974a <=( (not A202) and a6973a );
a6978a <=( A301 and A300 );
a6979a <=( A299 and a6978a );
a6980a <=( a6979a and a6974a );
a6983a <=( (not A168) and A169 );
a6987a <=( (not A201) and (not A200) );
a6988a <=( A199 and a6987a );
a6989a <=( a6988a and a6983a );
a6993a <=( (not A298) and (not A203) );
a6994a <=( (not A202) and a6993a );
a6998a <=( A302 and A300 );
a6999a <=( A299 and a6998a );
a7000a <=( a6999a and a6994a );
a7003a <=( (not A169) and A170 );
a7007a <=( A200 and (not A199) );
a7008a <=( A168 and a7007a );
a7009a <=( a7008a and a7003a );
a7013a <=( A298 and A202 );
a7014a <=( A201 and a7013a );
a7018a <=( A301 and A300 );
a7019a <=( (not A299) and a7018a );
a7020a <=( a7019a and a7014a );
a7023a <=( (not A169) and A170 );
a7027a <=( A200 and (not A199) );
a7028a <=( A168 and a7027a );
a7029a <=( a7028a and a7023a );
a7033a <=( A298 and A202 );
a7034a <=( A201 and a7033a );
a7038a <=( A302 and A300 );
a7039a <=( (not A299) and a7038a );
a7040a <=( a7039a and a7034a );
a7043a <=( (not A169) and A170 );
a7047a <=( A200 and (not A199) );
a7048a <=( A168 and a7047a );
a7049a <=( a7048a and a7043a );
a7053a <=( (not A298) and A202 );
a7054a <=( A201 and a7053a );
a7058a <=( A301 and A300 );
a7059a <=( A299 and a7058a );
a7060a <=( a7059a and a7054a );
a7063a <=( (not A169) and A170 );
a7067a <=( A200 and (not A199) );
a7068a <=( A168 and a7067a );
a7069a <=( a7068a and a7063a );
a7073a <=( (not A298) and A202 );
a7074a <=( A201 and a7073a );
a7078a <=( A302 and A300 );
a7079a <=( A299 and a7078a );
a7080a <=( a7079a and a7074a );
a7083a <=( (not A169) and A170 );
a7087a <=( A200 and (not A199) );
a7088a <=( A168 and a7087a );
a7089a <=( a7088a and a7083a );
a7093a <=( A298 and A203 );
a7094a <=( A201 and a7093a );
a7098a <=( A301 and A300 );
a7099a <=( (not A299) and a7098a );
a7100a <=( a7099a and a7094a );
a7103a <=( (not A169) and A170 );
a7107a <=( A200 and (not A199) );
a7108a <=( A168 and a7107a );
a7109a <=( a7108a and a7103a );
a7113a <=( A298 and A203 );
a7114a <=( A201 and a7113a );
a7118a <=( A302 and A300 );
a7119a <=( (not A299) and a7118a );
a7120a <=( a7119a and a7114a );
a7123a <=( (not A169) and A170 );
a7127a <=( A200 and (not A199) );
a7128a <=( A168 and a7127a );
a7129a <=( a7128a and a7123a );
a7133a <=( (not A298) and A203 );
a7134a <=( A201 and a7133a );
a7138a <=( A301 and A300 );
a7139a <=( A299 and a7138a );
a7140a <=( a7139a and a7134a );
a7143a <=( (not A169) and A170 );
a7147a <=( A200 and (not A199) );
a7148a <=( A168 and a7147a );
a7149a <=( a7148a and a7143a );
a7153a <=( (not A298) and A203 );
a7154a <=( A201 and a7153a );
a7158a <=( A302 and A300 );
a7159a <=( A299 and a7158a );
a7160a <=( a7159a and a7154a );
a7163a <=( (not A169) and A170 );
a7167a <=( (not A200) and A199 );
a7168a <=( A168 and a7167a );
a7169a <=( a7168a and a7163a );
a7173a <=( A298 and A202 );
a7174a <=( A201 and a7173a );
a7178a <=( A301 and A300 );
a7179a <=( (not A299) and a7178a );
a7180a <=( a7179a and a7174a );
a7183a <=( (not A169) and A170 );
a7187a <=( (not A200) and A199 );
a7188a <=( A168 and a7187a );
a7189a <=( a7188a and a7183a );
a7193a <=( A298 and A202 );
a7194a <=( A201 and a7193a );
a7198a <=( A302 and A300 );
a7199a <=( (not A299) and a7198a );
a7200a <=( a7199a and a7194a );
a7203a <=( (not A169) and A170 );
a7207a <=( (not A200) and A199 );
a7208a <=( A168 and a7207a );
a7209a <=( a7208a and a7203a );
a7213a <=( (not A298) and A202 );
a7214a <=( A201 and a7213a );
a7218a <=( A301 and A300 );
a7219a <=( A299 and a7218a );
a7220a <=( a7219a and a7214a );
a7223a <=( (not A169) and A170 );
a7227a <=( (not A200) and A199 );
a7228a <=( A168 and a7227a );
a7229a <=( a7228a and a7223a );
a7233a <=( (not A298) and A202 );
a7234a <=( A201 and a7233a );
a7238a <=( A302 and A300 );
a7239a <=( A299 and a7238a );
a7240a <=( a7239a and a7234a );
a7243a <=( (not A169) and A170 );
a7247a <=( (not A200) and A199 );
a7248a <=( A168 and a7247a );
a7249a <=( a7248a and a7243a );
a7253a <=( A298 and A203 );
a7254a <=( A201 and a7253a );
a7258a <=( A301 and A300 );
a7259a <=( (not A299) and a7258a );
a7260a <=( a7259a and a7254a );
a7263a <=( (not A169) and A170 );
a7267a <=( (not A200) and A199 );
a7268a <=( A168 and a7267a );
a7269a <=( a7268a and a7263a );
a7273a <=( A298 and A203 );
a7274a <=( A201 and a7273a );
a7278a <=( A302 and A300 );
a7279a <=( (not A299) and a7278a );
a7280a <=( a7279a and a7274a );
a7283a <=( (not A169) and A170 );
a7287a <=( (not A200) and A199 );
a7288a <=( A168 and a7287a );
a7289a <=( a7288a and a7283a );
a7293a <=( (not A298) and A203 );
a7294a <=( A201 and a7293a );
a7298a <=( A301 and A300 );
a7299a <=( A299 and a7298a );
a7300a <=( a7299a and a7294a );
a7303a <=( (not A169) and A170 );
a7307a <=( (not A200) and A199 );
a7308a <=( A168 and a7307a );
a7309a <=( a7308a and a7303a );
a7313a <=( (not A298) and A203 );
a7314a <=( A201 and a7313a );
a7318a <=( A302 and A300 );
a7319a <=( A299 and a7318a );
a7320a <=( a7319a and a7314a );
a7323a <=( (not A169) and A170 );
a7327a <=( (not A166) and A167 );
a7328a <=( (not A168) and a7327a );
a7329a <=( a7328a and a7323a );
a7333a <=( A298 and A202 );
a7334a <=( (not A201) and a7333a );
a7338a <=( A301 and A300 );
a7339a <=( (not A299) and a7338a );
a7340a <=( a7339a and a7334a );
a7343a <=( (not A169) and A170 );
a7347a <=( (not A166) and A167 );
a7348a <=( (not A168) and a7347a );
a7349a <=( a7348a and a7343a );
a7353a <=( A298 and A202 );
a7354a <=( (not A201) and a7353a );
a7358a <=( A302 and A300 );
a7359a <=( (not A299) and a7358a );
a7360a <=( a7359a and a7354a );
a7363a <=( (not A169) and A170 );
a7367a <=( (not A166) and A167 );
a7368a <=( (not A168) and a7367a );
a7369a <=( a7368a and a7363a );
a7373a <=( (not A298) and A202 );
a7374a <=( (not A201) and a7373a );
a7378a <=( A301 and A300 );
a7379a <=( A299 and a7378a );
a7380a <=( a7379a and a7374a );
a7383a <=( (not A169) and A170 );
a7387a <=( (not A166) and A167 );
a7388a <=( (not A168) and a7387a );
a7389a <=( a7388a and a7383a );
a7393a <=( (not A298) and A202 );
a7394a <=( (not A201) and a7393a );
a7398a <=( A302 and A300 );
a7399a <=( A299 and a7398a );
a7400a <=( a7399a and a7394a );
a7403a <=( (not A169) and A170 );
a7407a <=( (not A166) and A167 );
a7408a <=( (not A168) and a7407a );
a7409a <=( a7408a and a7403a );
a7413a <=( A298 and A203 );
a7414a <=( (not A201) and a7413a );
a7418a <=( A301 and A300 );
a7419a <=( (not A299) and a7418a );
a7420a <=( a7419a and a7414a );
a7423a <=( (not A169) and A170 );
a7427a <=( (not A166) and A167 );
a7428a <=( (not A168) and a7427a );
a7429a <=( a7428a and a7423a );
a7433a <=( A298 and A203 );
a7434a <=( (not A201) and a7433a );
a7438a <=( A302 and A300 );
a7439a <=( (not A299) and a7438a );
a7440a <=( a7439a and a7434a );
a7443a <=( (not A169) and A170 );
a7447a <=( (not A166) and A167 );
a7448a <=( (not A168) and a7447a );
a7449a <=( a7448a and a7443a );
a7453a <=( (not A298) and A203 );
a7454a <=( (not A201) and a7453a );
a7458a <=( A301 and A300 );
a7459a <=( A299 and a7458a );
a7460a <=( a7459a and a7454a );
a7463a <=( (not A169) and A170 );
a7467a <=( (not A166) and A167 );
a7468a <=( (not A168) and a7467a );
a7469a <=( a7468a and a7463a );
a7473a <=( (not A298) and A203 );
a7474a <=( (not A201) and a7473a );
a7478a <=( A302 and A300 );
a7479a <=( A299 and a7478a );
a7480a <=( a7479a and a7474a );
a7483a <=( (not A169) and A170 );
a7487a <=( (not A166) and A167 );
a7488a <=( (not A168) and a7487a );
a7489a <=( a7488a and a7483a );
a7493a <=( A298 and A200 );
a7494a <=( A199 and a7493a );
a7498a <=( A301 and A300 );
a7499a <=( (not A299) and a7498a );
a7500a <=( a7499a and a7494a );
a7503a <=( (not A169) and A170 );
a7507a <=( (not A166) and A167 );
a7508a <=( (not A168) and a7507a );
a7509a <=( a7508a and a7503a );
a7513a <=( A298 and A200 );
a7514a <=( A199 and a7513a );
a7518a <=( A302 and A300 );
a7519a <=( (not A299) and a7518a );
a7520a <=( a7519a and a7514a );
a7523a <=( (not A169) and A170 );
a7527a <=( (not A166) and A167 );
a7528a <=( (not A168) and a7527a );
a7529a <=( a7528a and a7523a );
a7533a <=( (not A298) and A200 );
a7534a <=( A199 and a7533a );
a7538a <=( A301 and A300 );
a7539a <=( A299 and a7538a );
a7540a <=( a7539a and a7534a );
a7543a <=( (not A169) and A170 );
a7547a <=( (not A166) and A167 );
a7548a <=( (not A168) and a7547a );
a7549a <=( a7548a and a7543a );
a7553a <=( (not A298) and A200 );
a7554a <=( A199 and a7553a );
a7558a <=( A302 and A300 );
a7559a <=( A299 and a7558a );
a7560a <=( a7559a and a7554a );
a7563a <=( (not A169) and A170 );
a7567a <=( (not A166) and A167 );
a7568a <=( (not A168) and a7567a );
a7569a <=( a7568a and a7563a );
a7573a <=( A298 and (not A200) );
a7574a <=( (not A199) and a7573a );
a7578a <=( A301 and A300 );
a7579a <=( (not A299) and a7578a );
a7580a <=( a7579a and a7574a );
a7583a <=( (not A169) and A170 );
a7587a <=( (not A166) and A167 );
a7588a <=( (not A168) and a7587a );
a7589a <=( a7588a and a7583a );
a7593a <=( A298 and (not A200) );
a7594a <=( (not A199) and a7593a );
a7598a <=( A302 and A300 );
a7599a <=( (not A299) and a7598a );
a7600a <=( a7599a and a7594a );
a7603a <=( (not A169) and A170 );
a7607a <=( (not A166) and A167 );
a7608a <=( (not A168) and a7607a );
a7609a <=( a7608a and a7603a );
a7613a <=( (not A298) and (not A200) );
a7614a <=( (not A199) and a7613a );
a7618a <=( A301 and A300 );
a7619a <=( A299 and a7618a );
a7620a <=( a7619a and a7614a );
a7623a <=( (not A169) and A170 );
a7627a <=( (not A166) and A167 );
a7628a <=( (not A168) and a7627a );
a7629a <=( a7628a and a7623a );
a7633a <=( (not A298) and (not A200) );
a7634a <=( (not A199) and a7633a );
a7638a <=( A302 and A300 );
a7639a <=( A299 and a7638a );
a7640a <=( a7639a and a7634a );
a7643a <=( (not A169) and A170 );
a7647a <=( A166 and (not A167) );
a7648a <=( (not A168) and a7647a );
a7649a <=( a7648a and a7643a );
a7653a <=( A298 and A202 );
a7654a <=( (not A201) and a7653a );
a7658a <=( A301 and A300 );
a7659a <=( (not A299) and a7658a );
a7660a <=( a7659a and a7654a );
a7663a <=( (not A169) and A170 );
a7667a <=( A166 and (not A167) );
a7668a <=( (not A168) and a7667a );
a7669a <=( a7668a and a7663a );
a7673a <=( A298 and A202 );
a7674a <=( (not A201) and a7673a );
a7678a <=( A302 and A300 );
a7679a <=( (not A299) and a7678a );
a7680a <=( a7679a and a7674a );
a7683a <=( (not A169) and A170 );
a7687a <=( A166 and (not A167) );
a7688a <=( (not A168) and a7687a );
a7689a <=( a7688a and a7683a );
a7693a <=( (not A298) and A202 );
a7694a <=( (not A201) and a7693a );
a7698a <=( A301 and A300 );
a7699a <=( A299 and a7698a );
a7700a <=( a7699a and a7694a );
a7703a <=( (not A169) and A170 );
a7707a <=( A166 and (not A167) );
a7708a <=( (not A168) and a7707a );
a7709a <=( a7708a and a7703a );
a7713a <=( (not A298) and A202 );
a7714a <=( (not A201) and a7713a );
a7718a <=( A302 and A300 );
a7719a <=( A299 and a7718a );
a7720a <=( a7719a and a7714a );
a7723a <=( (not A169) and A170 );
a7727a <=( A166 and (not A167) );
a7728a <=( (not A168) and a7727a );
a7729a <=( a7728a and a7723a );
a7733a <=( A298 and A203 );
a7734a <=( (not A201) and a7733a );
a7738a <=( A301 and A300 );
a7739a <=( (not A299) and a7738a );
a7740a <=( a7739a and a7734a );
a7743a <=( (not A169) and A170 );
a7747a <=( A166 and (not A167) );
a7748a <=( (not A168) and a7747a );
a7749a <=( a7748a and a7743a );
a7753a <=( A298 and A203 );
a7754a <=( (not A201) and a7753a );
a7758a <=( A302 and A300 );
a7759a <=( (not A299) and a7758a );
a7760a <=( a7759a and a7754a );
a7763a <=( (not A169) and A170 );
a7767a <=( A166 and (not A167) );
a7768a <=( (not A168) and a7767a );
a7769a <=( a7768a and a7763a );
a7773a <=( (not A298) and A203 );
a7774a <=( (not A201) and a7773a );
a7778a <=( A301 and A300 );
a7779a <=( A299 and a7778a );
a7780a <=( a7779a and a7774a );
a7783a <=( (not A169) and A170 );
a7787a <=( A166 and (not A167) );
a7788a <=( (not A168) and a7787a );
a7789a <=( a7788a and a7783a );
a7793a <=( (not A298) and A203 );
a7794a <=( (not A201) and a7793a );
a7798a <=( A302 and A300 );
a7799a <=( A299 and a7798a );
a7800a <=( a7799a and a7794a );
a7803a <=( (not A169) and A170 );
a7807a <=( A166 and (not A167) );
a7808a <=( (not A168) and a7807a );
a7809a <=( a7808a and a7803a );
a7813a <=( A298 and A200 );
a7814a <=( A199 and a7813a );
a7818a <=( A301 and A300 );
a7819a <=( (not A299) and a7818a );
a7820a <=( a7819a and a7814a );
a7823a <=( (not A169) and A170 );
a7827a <=( A166 and (not A167) );
a7828a <=( (not A168) and a7827a );
a7829a <=( a7828a and a7823a );
a7833a <=( A298 and A200 );
a7834a <=( A199 and a7833a );
a7838a <=( A302 and A300 );
a7839a <=( (not A299) and a7838a );
a7840a <=( a7839a and a7834a );
a7843a <=( (not A169) and A170 );
a7847a <=( A166 and (not A167) );
a7848a <=( (not A168) and a7847a );
a7849a <=( a7848a and a7843a );
a7853a <=( (not A298) and A200 );
a7854a <=( A199 and a7853a );
a7858a <=( A301 and A300 );
a7859a <=( A299 and a7858a );
a7860a <=( a7859a and a7854a );
a7863a <=( (not A169) and A170 );
a7867a <=( A166 and (not A167) );
a7868a <=( (not A168) and a7867a );
a7869a <=( a7868a and a7863a );
a7873a <=( (not A298) and A200 );
a7874a <=( A199 and a7873a );
a7878a <=( A302 and A300 );
a7879a <=( A299 and a7878a );
a7880a <=( a7879a and a7874a );
a7883a <=( (not A169) and A170 );
a7887a <=( A166 and (not A167) );
a7888a <=( (not A168) and a7887a );
a7889a <=( a7888a and a7883a );
a7893a <=( A298 and (not A200) );
a7894a <=( (not A199) and a7893a );
a7898a <=( A301 and A300 );
a7899a <=( (not A299) and a7898a );
a7900a <=( a7899a and a7894a );
a7903a <=( (not A169) and A170 );
a7907a <=( A166 and (not A167) );
a7908a <=( (not A168) and a7907a );
a7909a <=( a7908a and a7903a );
a7913a <=( A298 and (not A200) );
a7914a <=( (not A199) and a7913a );
a7918a <=( A302 and A300 );
a7919a <=( (not A299) and a7918a );
a7920a <=( a7919a and a7914a );
a7923a <=( (not A169) and A170 );
a7927a <=( A166 and (not A167) );
a7928a <=( (not A168) and a7927a );
a7929a <=( a7928a and a7923a );
a7933a <=( (not A298) and (not A200) );
a7934a <=( (not A199) and a7933a );
a7938a <=( A301 and A300 );
a7939a <=( A299 and a7938a );
a7940a <=( a7939a and a7934a );
a7943a <=( (not A169) and A170 );
a7947a <=( A166 and (not A167) );
a7948a <=( (not A168) and a7947a );
a7949a <=( a7948a and a7943a );
a7953a <=( (not A298) and (not A200) );
a7954a <=( (not A199) and a7953a );
a7958a <=( A302 and A300 );
a7959a <=( A299 and a7958a );
a7960a <=( a7959a and a7954a );
a7964a <=( (not A199) and A166 );
a7965a <=( A167 and a7964a );
a7969a <=( (not A202) and (not A201) );
a7970a <=( A200 and a7969a );
a7971a <=( a7970a and a7965a );
a7975a <=( (not A299) and A298 );
a7976a <=( (not A203) and a7975a );
a7980a <=( (not A302) and (not A301) );
a7981a <=( (not A300) and a7980a );
a7982a <=( a7981a and a7976a );
a7986a <=( (not A199) and A166 );
a7987a <=( A167 and a7986a );
a7991a <=( (not A202) and (not A201) );
a7992a <=( A200 and a7991a );
a7993a <=( a7992a and a7987a );
a7997a <=( A299 and (not A298) );
a7998a <=( (not A203) and a7997a );
a8002a <=( (not A302) and (not A301) );
a8003a <=( (not A300) and a8002a );
a8004a <=( a8003a and a7998a );
a8008a <=( A199 and A166 );
a8009a <=( A167 and a8008a );
a8013a <=( (not A202) and (not A201) );
a8014a <=( (not A200) and a8013a );
a8015a <=( a8014a and a8009a );
a8019a <=( (not A299) and A298 );
a8020a <=( (not A203) and a8019a );
a8024a <=( (not A302) and (not A301) );
a8025a <=( (not A300) and a8024a );
a8026a <=( a8025a and a8020a );
a8030a <=( A199 and A166 );
a8031a <=( A167 and a8030a );
a8035a <=( (not A202) and (not A201) );
a8036a <=( (not A200) and a8035a );
a8037a <=( a8036a and a8031a );
a8041a <=( A299 and (not A298) );
a8042a <=( (not A203) and a8041a );
a8046a <=( (not A302) and (not A301) );
a8047a <=( (not A300) and a8046a );
a8048a <=( a8047a and a8042a );
a8052a <=( (not A199) and (not A166) );
a8053a <=( (not A167) and a8052a );
a8057a <=( (not A202) and (not A201) );
a8058a <=( A200 and a8057a );
a8059a <=( a8058a and a8053a );
a8063a <=( (not A299) and A298 );
a8064a <=( (not A203) and a8063a );
a8068a <=( (not A302) and (not A301) );
a8069a <=( (not A300) and a8068a );
a8070a <=( a8069a and a8064a );
a8074a <=( (not A199) and (not A166) );
a8075a <=( (not A167) and a8074a );
a8079a <=( (not A202) and (not A201) );
a8080a <=( A200 and a8079a );
a8081a <=( a8080a and a8075a );
a8085a <=( A299 and (not A298) );
a8086a <=( (not A203) and a8085a );
a8090a <=( (not A302) and (not A301) );
a8091a <=( (not A300) and a8090a );
a8092a <=( a8091a and a8086a );
a8096a <=( A199 and (not A166) );
a8097a <=( (not A167) and a8096a );
a8101a <=( (not A202) and (not A201) );
a8102a <=( (not A200) and a8101a );
a8103a <=( a8102a and a8097a );
a8107a <=( (not A299) and A298 );
a8108a <=( (not A203) and a8107a );
a8112a <=( (not A302) and (not A301) );
a8113a <=( (not A300) and a8112a );
a8114a <=( a8113a and a8108a );
a8118a <=( A199 and (not A166) );
a8119a <=( (not A167) and a8118a );
a8123a <=( (not A202) and (not A201) );
a8124a <=( (not A200) and a8123a );
a8125a <=( a8124a and a8119a );
a8129a <=( A299 and (not A298) );
a8130a <=( (not A203) and a8129a );
a8134a <=( (not A302) and (not A301) );
a8135a <=( (not A300) and a8134a );
a8136a <=( a8135a and a8130a );
a8140a <=( A167 and A168 );
a8141a <=( (not A170) and a8140a );
a8145a <=( (not A202) and A201 );
a8146a <=( (not A166) and a8145a );
a8147a <=( a8146a and a8141a );
a8151a <=( (not A299) and A298 );
a8152a <=( (not A203) and a8151a );
a8156a <=( (not A302) and (not A301) );
a8157a <=( (not A300) and a8156a );
a8158a <=( a8157a and a8152a );
a8162a <=( A167 and A168 );
a8163a <=( (not A170) and a8162a );
a8167a <=( (not A202) and A201 );
a8168a <=( (not A166) and a8167a );
a8169a <=( a8168a and a8163a );
a8173a <=( A299 and (not A298) );
a8174a <=( (not A203) and a8173a );
a8178a <=( (not A302) and (not A301) );
a8179a <=( (not A300) and a8178a );
a8180a <=( a8179a and a8174a );
a8184a <=( (not A167) and A168 );
a8185a <=( (not A170) and a8184a );
a8189a <=( (not A202) and A201 );
a8190a <=( A166 and a8189a );
a8191a <=( a8190a and a8185a );
a8195a <=( (not A299) and A298 );
a8196a <=( (not A203) and a8195a );
a8200a <=( (not A302) and (not A301) );
a8201a <=( (not A300) and a8200a );
a8202a <=( a8201a and a8196a );
a8206a <=( (not A167) and A168 );
a8207a <=( (not A170) and a8206a );
a8211a <=( (not A202) and A201 );
a8212a <=( A166 and a8211a );
a8213a <=( a8212a and a8207a );
a8217a <=( A299 and (not A298) );
a8218a <=( (not A203) and a8217a );
a8222a <=( (not A302) and (not A301) );
a8223a <=( (not A300) and a8222a );
a8224a <=( a8223a and a8218a );
a8228a <=( (not A199) and (not A168) );
a8229a <=( (not A170) and a8228a );
a8233a <=( (not A202) and (not A201) );
a8234a <=( A200 and a8233a );
a8235a <=( a8234a and a8229a );
a8239a <=( (not A299) and A298 );
a8240a <=( (not A203) and a8239a );
a8244a <=( (not A302) and (not A301) );
a8245a <=( (not A300) and a8244a );
a8246a <=( a8245a and a8240a );
a8250a <=( (not A199) and (not A168) );
a8251a <=( (not A170) and a8250a );
a8255a <=( (not A202) and (not A201) );
a8256a <=( A200 and a8255a );
a8257a <=( a8256a and a8251a );
a8261a <=( A299 and (not A298) );
a8262a <=( (not A203) and a8261a );
a8266a <=( (not A302) and (not A301) );
a8267a <=( (not A300) and a8266a );
a8268a <=( a8267a and a8262a );
a8272a <=( A199 and (not A168) );
a8273a <=( (not A170) and a8272a );
a8277a <=( (not A202) and (not A201) );
a8278a <=( (not A200) and a8277a );
a8279a <=( a8278a and a8273a );
a8283a <=( (not A299) and A298 );
a8284a <=( (not A203) and a8283a );
a8288a <=( (not A302) and (not A301) );
a8289a <=( (not A300) and a8288a );
a8290a <=( a8289a and a8284a );
a8294a <=( A199 and (not A168) );
a8295a <=( (not A170) and a8294a );
a8299a <=( (not A202) and (not A201) );
a8300a <=( (not A200) and a8299a );
a8301a <=( a8300a and a8295a );
a8305a <=( A299 and (not A298) );
a8306a <=( (not A203) and a8305a );
a8310a <=( (not A302) and (not A301) );
a8311a <=( (not A300) and a8310a );
a8312a <=( a8311a and a8306a );
a8316a <=( A167 and A168 );
a8317a <=( A169 and a8316a );
a8321a <=( (not A202) and A201 );
a8322a <=( (not A166) and a8321a );
a8323a <=( a8322a and a8317a );
a8327a <=( (not A299) and A298 );
a8328a <=( (not A203) and a8327a );
a8332a <=( (not A302) and (not A301) );
a8333a <=( (not A300) and a8332a );
a8334a <=( a8333a and a8328a );
a8338a <=( A167 and A168 );
a8339a <=( A169 and a8338a );
a8343a <=( (not A202) and A201 );
a8344a <=( (not A166) and a8343a );
a8345a <=( a8344a and a8339a );
a8349a <=( A299 and (not A298) );
a8350a <=( (not A203) and a8349a );
a8354a <=( (not A302) and (not A301) );
a8355a <=( (not A300) and a8354a );
a8356a <=( a8355a and a8350a );
a8360a <=( (not A167) and A168 );
a8361a <=( A169 and a8360a );
a8365a <=( (not A202) and A201 );
a8366a <=( A166 and a8365a );
a8367a <=( a8366a and a8361a );
a8371a <=( (not A299) and A298 );
a8372a <=( (not A203) and a8371a );
a8376a <=( (not A302) and (not A301) );
a8377a <=( (not A300) and a8376a );
a8378a <=( a8377a and a8372a );
a8382a <=( (not A167) and A168 );
a8383a <=( A169 and a8382a );
a8387a <=( (not A202) and A201 );
a8388a <=( A166 and a8387a );
a8389a <=( a8388a and a8383a );
a8393a <=( A299 and (not A298) );
a8394a <=( (not A203) and a8393a );
a8398a <=( (not A302) and (not A301) );
a8399a <=( (not A300) and a8398a );
a8400a <=( a8399a and a8394a );
a8404a <=( (not A199) and (not A168) );
a8405a <=( A169 and a8404a );
a8409a <=( (not A202) and (not A201) );
a8410a <=( A200 and a8409a );
a8411a <=( a8410a and a8405a );
a8415a <=( (not A299) and A298 );
a8416a <=( (not A203) and a8415a );
a8420a <=( (not A302) and (not A301) );
a8421a <=( (not A300) and a8420a );
a8422a <=( a8421a and a8416a );
a8426a <=( (not A199) and (not A168) );
a8427a <=( A169 and a8426a );
a8431a <=( (not A202) and (not A201) );
a8432a <=( A200 and a8431a );
a8433a <=( a8432a and a8427a );
a8437a <=( A299 and (not A298) );
a8438a <=( (not A203) and a8437a );
a8442a <=( (not A302) and (not A301) );
a8443a <=( (not A300) and a8442a );
a8444a <=( a8443a and a8438a );
a8448a <=( A199 and (not A168) );
a8449a <=( A169 and a8448a );
a8453a <=( (not A202) and (not A201) );
a8454a <=( (not A200) and a8453a );
a8455a <=( a8454a and a8449a );
a8459a <=( (not A299) and A298 );
a8460a <=( (not A203) and a8459a );
a8464a <=( (not A302) and (not A301) );
a8465a <=( (not A300) and a8464a );
a8466a <=( a8465a and a8460a );
a8470a <=( A199 and (not A168) );
a8471a <=( A169 and a8470a );
a8475a <=( (not A202) and (not A201) );
a8476a <=( (not A200) and a8475a );
a8477a <=( a8476a and a8471a );
a8481a <=( A299 and (not A298) );
a8482a <=( (not A203) and a8481a );
a8486a <=( (not A302) and (not A301) );
a8487a <=( (not A300) and a8486a );
a8488a <=( a8487a and a8482a );
a8492a <=( A168 and (not A169) );
a8493a <=( A170 and a8492a );
a8497a <=( A201 and A200 );
a8498a <=( (not A199) and a8497a );
a8499a <=( a8498a and a8493a );
a8503a <=( (not A299) and A298 );
a8504a <=( A202 and a8503a );
a8508a <=( (not A302) and (not A301) );
a8509a <=( (not A300) and a8508a );
a8510a <=( a8509a and a8504a );
a8514a <=( A168 and (not A169) );
a8515a <=( A170 and a8514a );
a8519a <=( A201 and A200 );
a8520a <=( (not A199) and a8519a );
a8521a <=( a8520a and a8515a );
a8525a <=( A299 and (not A298) );
a8526a <=( A202 and a8525a );
a8530a <=( (not A302) and (not A301) );
a8531a <=( (not A300) and a8530a );
a8532a <=( a8531a and a8526a );
a8536a <=( A168 and (not A169) );
a8537a <=( A170 and a8536a );
a8541a <=( A201 and A200 );
a8542a <=( (not A199) and a8541a );
a8543a <=( a8542a and a8537a );
a8547a <=( (not A299) and A298 );
a8548a <=( A203 and a8547a );
a8552a <=( (not A302) and (not A301) );
a8553a <=( (not A300) and a8552a );
a8554a <=( a8553a and a8548a );
a8558a <=( A168 and (not A169) );
a8559a <=( A170 and a8558a );
a8563a <=( A201 and A200 );
a8564a <=( (not A199) and a8563a );
a8565a <=( a8564a and a8559a );
a8569a <=( A299 and (not A298) );
a8570a <=( A203 and a8569a );
a8574a <=( (not A302) and (not A301) );
a8575a <=( (not A300) and a8574a );
a8576a <=( a8575a and a8570a );
a8580a <=( A168 and (not A169) );
a8581a <=( A170 and a8580a );
a8585a <=( (not A201) and A200 );
a8586a <=( (not A199) and a8585a );
a8587a <=( a8586a and a8581a );
a8591a <=( A298 and (not A203) );
a8592a <=( (not A202) and a8591a );
a8596a <=( A301 and A300 );
a8597a <=( (not A299) and a8596a );
a8598a <=( a8597a and a8592a );
a8602a <=( A168 and (not A169) );
a8603a <=( A170 and a8602a );
a8607a <=( (not A201) and A200 );
a8608a <=( (not A199) and a8607a );
a8609a <=( a8608a and a8603a );
a8613a <=( A298 and (not A203) );
a8614a <=( (not A202) and a8613a );
a8618a <=( A302 and A300 );
a8619a <=( (not A299) and a8618a );
a8620a <=( a8619a and a8614a );
a8624a <=( A168 and (not A169) );
a8625a <=( A170 and a8624a );
a8629a <=( (not A201) and A200 );
a8630a <=( (not A199) and a8629a );
a8631a <=( a8630a and a8625a );
a8635a <=( (not A298) and (not A203) );
a8636a <=( (not A202) and a8635a );
a8640a <=( A301 and A300 );
a8641a <=( A299 and a8640a );
a8642a <=( a8641a and a8636a );
a8646a <=( A168 and (not A169) );
a8647a <=( A170 and a8646a );
a8651a <=( (not A201) and A200 );
a8652a <=( (not A199) and a8651a );
a8653a <=( a8652a and a8647a );
a8657a <=( (not A298) and (not A203) );
a8658a <=( (not A202) and a8657a );
a8662a <=( A302 and A300 );
a8663a <=( A299 and a8662a );
a8664a <=( a8663a and a8658a );
a8668a <=( A168 and (not A169) );
a8669a <=( A170 and a8668a );
a8673a <=( A201 and (not A200) );
a8674a <=( A199 and a8673a );
a8675a <=( a8674a and a8669a );
a8679a <=( (not A299) and A298 );
a8680a <=( A202 and a8679a );
a8684a <=( (not A302) and (not A301) );
a8685a <=( (not A300) and a8684a );
a8686a <=( a8685a and a8680a );
a8690a <=( A168 and (not A169) );
a8691a <=( A170 and a8690a );
a8695a <=( A201 and (not A200) );
a8696a <=( A199 and a8695a );
a8697a <=( a8696a and a8691a );
a8701a <=( A299 and (not A298) );
a8702a <=( A202 and a8701a );
a8706a <=( (not A302) and (not A301) );
a8707a <=( (not A300) and a8706a );
a8708a <=( a8707a and a8702a );
a8712a <=( A168 and (not A169) );
a8713a <=( A170 and a8712a );
a8717a <=( A201 and (not A200) );
a8718a <=( A199 and a8717a );
a8719a <=( a8718a and a8713a );
a8723a <=( (not A299) and A298 );
a8724a <=( A203 and a8723a );
a8728a <=( (not A302) and (not A301) );
a8729a <=( (not A300) and a8728a );
a8730a <=( a8729a and a8724a );
a8734a <=( A168 and (not A169) );
a8735a <=( A170 and a8734a );
a8739a <=( A201 and (not A200) );
a8740a <=( A199 and a8739a );
a8741a <=( a8740a and a8735a );
a8745a <=( A299 and (not A298) );
a8746a <=( A203 and a8745a );
a8750a <=( (not A302) and (not A301) );
a8751a <=( (not A300) and a8750a );
a8752a <=( a8751a and a8746a );
a8756a <=( A168 and (not A169) );
a8757a <=( A170 and a8756a );
a8761a <=( (not A201) and (not A200) );
a8762a <=( A199 and a8761a );
a8763a <=( a8762a and a8757a );
a8767a <=( A298 and (not A203) );
a8768a <=( (not A202) and a8767a );
a8772a <=( A301 and A300 );
a8773a <=( (not A299) and a8772a );
a8774a <=( a8773a and a8768a );
a8778a <=( A168 and (not A169) );
a8779a <=( A170 and a8778a );
a8783a <=( (not A201) and (not A200) );
a8784a <=( A199 and a8783a );
a8785a <=( a8784a and a8779a );
a8789a <=( A298 and (not A203) );
a8790a <=( (not A202) and a8789a );
a8794a <=( A302 and A300 );
a8795a <=( (not A299) and a8794a );
a8796a <=( a8795a and a8790a );
a8800a <=( A168 and (not A169) );
a8801a <=( A170 and a8800a );
a8805a <=( (not A201) and (not A200) );
a8806a <=( A199 and a8805a );
a8807a <=( a8806a and a8801a );
a8811a <=( (not A298) and (not A203) );
a8812a <=( (not A202) and a8811a );
a8816a <=( A301 and A300 );
a8817a <=( A299 and a8816a );
a8818a <=( a8817a and a8812a );
a8822a <=( A168 and (not A169) );
a8823a <=( A170 and a8822a );
a8827a <=( (not A201) and (not A200) );
a8828a <=( A199 and a8827a );
a8829a <=( a8828a and a8823a );
a8833a <=( (not A298) and (not A203) );
a8834a <=( (not A202) and a8833a );
a8838a <=( A302 and A300 );
a8839a <=( A299 and a8838a );
a8840a <=( a8839a and a8834a );
a8844a <=( (not A168) and (not A169) );
a8845a <=( A170 and a8844a );
a8849a <=( A201 and (not A166) );
a8850a <=( A167 and a8849a );
a8851a <=( a8850a and a8845a );
a8855a <=( A298 and (not A203) );
a8856a <=( (not A202) and a8855a );
a8860a <=( A301 and A300 );
a8861a <=( (not A299) and a8860a );
a8862a <=( a8861a and a8856a );
a8866a <=( (not A168) and (not A169) );
a8867a <=( A170 and a8866a );
a8871a <=( A201 and (not A166) );
a8872a <=( A167 and a8871a );
a8873a <=( a8872a and a8867a );
a8877a <=( A298 and (not A203) );
a8878a <=( (not A202) and a8877a );
a8882a <=( A302 and A300 );
a8883a <=( (not A299) and a8882a );
a8884a <=( a8883a and a8878a );
a8888a <=( (not A168) and (not A169) );
a8889a <=( A170 and a8888a );
a8893a <=( A201 and (not A166) );
a8894a <=( A167 and a8893a );
a8895a <=( a8894a and a8889a );
a8899a <=( (not A298) and (not A203) );
a8900a <=( (not A202) and a8899a );
a8904a <=( A301 and A300 );
a8905a <=( A299 and a8904a );
a8906a <=( a8905a and a8900a );
a8910a <=( (not A168) and (not A169) );
a8911a <=( A170 and a8910a );
a8915a <=( A201 and (not A166) );
a8916a <=( A167 and a8915a );
a8917a <=( a8916a and a8911a );
a8921a <=( (not A298) and (not A203) );
a8922a <=( (not A202) and a8921a );
a8926a <=( A302 and A300 );
a8927a <=( A299 and a8926a );
a8928a <=( a8927a and a8922a );
a8932a <=( (not A168) and (not A169) );
a8933a <=( A170 and a8932a );
a8937a <=( (not A201) and (not A166) );
a8938a <=( A167 and a8937a );
a8939a <=( a8938a and a8933a );
a8943a <=( (not A299) and A298 );
a8944a <=( A202 and a8943a );
a8948a <=( (not A302) and (not A301) );
a8949a <=( (not A300) and a8948a );
a8950a <=( a8949a and a8944a );
a8954a <=( (not A168) and (not A169) );
a8955a <=( A170 and a8954a );
a8959a <=( (not A201) and (not A166) );
a8960a <=( A167 and a8959a );
a8961a <=( a8960a and a8955a );
a8965a <=( A299 and (not A298) );
a8966a <=( A202 and a8965a );
a8970a <=( (not A302) and (not A301) );
a8971a <=( (not A300) and a8970a );
a8972a <=( a8971a and a8966a );
a8976a <=( (not A168) and (not A169) );
a8977a <=( A170 and a8976a );
a8981a <=( (not A201) and (not A166) );
a8982a <=( A167 and a8981a );
a8983a <=( a8982a and a8977a );
a8987a <=( (not A299) and A298 );
a8988a <=( A203 and a8987a );
a8992a <=( (not A302) and (not A301) );
a8993a <=( (not A300) and a8992a );
a8994a <=( a8993a and a8988a );
a8998a <=( (not A168) and (not A169) );
a8999a <=( A170 and a8998a );
a9003a <=( (not A201) and (not A166) );
a9004a <=( A167 and a9003a );
a9005a <=( a9004a and a8999a );
a9009a <=( A299 and (not A298) );
a9010a <=( A203 and a9009a );
a9014a <=( (not A302) and (not A301) );
a9015a <=( (not A300) and a9014a );
a9016a <=( a9015a and a9010a );
a9020a <=( (not A168) and (not A169) );
a9021a <=( A170 and a9020a );
a9025a <=( A199 and (not A166) );
a9026a <=( A167 and a9025a );
a9027a <=( a9026a and a9021a );
a9031a <=( (not A299) and A298 );
a9032a <=( A200 and a9031a );
a9036a <=( (not A302) and (not A301) );
a9037a <=( (not A300) and a9036a );
a9038a <=( a9037a and a9032a );
a9042a <=( (not A168) and (not A169) );
a9043a <=( A170 and a9042a );
a9047a <=( A199 and (not A166) );
a9048a <=( A167 and a9047a );
a9049a <=( a9048a and a9043a );
a9053a <=( A299 and (not A298) );
a9054a <=( A200 and a9053a );
a9058a <=( (not A302) and (not A301) );
a9059a <=( (not A300) and a9058a );
a9060a <=( a9059a and a9054a );
a9064a <=( (not A168) and (not A169) );
a9065a <=( A170 and a9064a );
a9069a <=( (not A199) and (not A166) );
a9070a <=( A167 and a9069a );
a9071a <=( a9070a and a9065a );
a9075a <=( (not A299) and A298 );
a9076a <=( (not A200) and a9075a );
a9080a <=( (not A302) and (not A301) );
a9081a <=( (not A300) and a9080a );
a9082a <=( a9081a and a9076a );
a9086a <=( (not A168) and (not A169) );
a9087a <=( A170 and a9086a );
a9091a <=( (not A199) and (not A166) );
a9092a <=( A167 and a9091a );
a9093a <=( a9092a and a9087a );
a9097a <=( A299 and (not A298) );
a9098a <=( (not A200) and a9097a );
a9102a <=( (not A302) and (not A301) );
a9103a <=( (not A300) and a9102a );
a9104a <=( a9103a and a9098a );
a9108a <=( (not A168) and (not A169) );
a9109a <=( A170 and a9108a );
a9113a <=( A201 and A166 );
a9114a <=( (not A167) and a9113a );
a9115a <=( a9114a and a9109a );
a9119a <=( A298 and (not A203) );
a9120a <=( (not A202) and a9119a );
a9124a <=( A301 and A300 );
a9125a <=( (not A299) and a9124a );
a9126a <=( a9125a and a9120a );
a9130a <=( (not A168) and (not A169) );
a9131a <=( A170 and a9130a );
a9135a <=( A201 and A166 );
a9136a <=( (not A167) and a9135a );
a9137a <=( a9136a and a9131a );
a9141a <=( A298 and (not A203) );
a9142a <=( (not A202) and a9141a );
a9146a <=( A302 and A300 );
a9147a <=( (not A299) and a9146a );
a9148a <=( a9147a and a9142a );
a9152a <=( (not A168) and (not A169) );
a9153a <=( A170 and a9152a );
a9157a <=( A201 and A166 );
a9158a <=( (not A167) and a9157a );
a9159a <=( a9158a and a9153a );
a9163a <=( (not A298) and (not A203) );
a9164a <=( (not A202) and a9163a );
a9168a <=( A301 and A300 );
a9169a <=( A299 and a9168a );
a9170a <=( a9169a and a9164a );
a9174a <=( (not A168) and (not A169) );
a9175a <=( A170 and a9174a );
a9179a <=( A201 and A166 );
a9180a <=( (not A167) and a9179a );
a9181a <=( a9180a and a9175a );
a9185a <=( (not A298) and (not A203) );
a9186a <=( (not A202) and a9185a );
a9190a <=( A302 and A300 );
a9191a <=( A299 and a9190a );
a9192a <=( a9191a and a9186a );
a9196a <=( (not A168) and (not A169) );
a9197a <=( A170 and a9196a );
a9201a <=( (not A201) and A166 );
a9202a <=( (not A167) and a9201a );
a9203a <=( a9202a and a9197a );
a9207a <=( (not A299) and A298 );
a9208a <=( A202 and a9207a );
a9212a <=( (not A302) and (not A301) );
a9213a <=( (not A300) and a9212a );
a9214a <=( a9213a and a9208a );
a9218a <=( (not A168) and (not A169) );
a9219a <=( A170 and a9218a );
a9223a <=( (not A201) and A166 );
a9224a <=( (not A167) and a9223a );
a9225a <=( a9224a and a9219a );
a9229a <=( A299 and (not A298) );
a9230a <=( A202 and a9229a );
a9234a <=( (not A302) and (not A301) );
a9235a <=( (not A300) and a9234a );
a9236a <=( a9235a and a9230a );
a9240a <=( (not A168) and (not A169) );
a9241a <=( A170 and a9240a );
a9245a <=( (not A201) and A166 );
a9246a <=( (not A167) and a9245a );
a9247a <=( a9246a and a9241a );
a9251a <=( (not A299) and A298 );
a9252a <=( A203 and a9251a );
a9256a <=( (not A302) and (not A301) );
a9257a <=( (not A300) and a9256a );
a9258a <=( a9257a and a9252a );
a9262a <=( (not A168) and (not A169) );
a9263a <=( A170 and a9262a );
a9267a <=( (not A201) and A166 );
a9268a <=( (not A167) and a9267a );
a9269a <=( a9268a and a9263a );
a9273a <=( A299 and (not A298) );
a9274a <=( A203 and a9273a );
a9278a <=( (not A302) and (not A301) );
a9279a <=( (not A300) and a9278a );
a9280a <=( a9279a and a9274a );
a9284a <=( (not A168) and (not A169) );
a9285a <=( A170 and a9284a );
a9289a <=( A199 and A166 );
a9290a <=( (not A167) and a9289a );
a9291a <=( a9290a and a9285a );
a9295a <=( (not A299) and A298 );
a9296a <=( A200 and a9295a );
a9300a <=( (not A302) and (not A301) );
a9301a <=( (not A300) and a9300a );
a9302a <=( a9301a and a9296a );
a9306a <=( (not A168) and (not A169) );
a9307a <=( A170 and a9306a );
a9311a <=( A199 and A166 );
a9312a <=( (not A167) and a9311a );
a9313a <=( a9312a and a9307a );
a9317a <=( A299 and (not A298) );
a9318a <=( A200 and a9317a );
a9322a <=( (not A302) and (not A301) );
a9323a <=( (not A300) and a9322a );
a9324a <=( a9323a and a9318a );
a9328a <=( (not A168) and (not A169) );
a9329a <=( A170 and a9328a );
a9333a <=( (not A199) and A166 );
a9334a <=( (not A167) and a9333a );
a9335a <=( a9334a and a9329a );
a9339a <=( (not A299) and A298 );
a9340a <=( (not A200) and a9339a );
a9344a <=( (not A302) and (not A301) );
a9345a <=( (not A300) and a9344a );
a9346a <=( a9345a and a9340a );
a9350a <=( (not A168) and (not A169) );
a9351a <=( A170 and a9350a );
a9355a <=( (not A199) and A166 );
a9356a <=( (not A167) and a9355a );
a9357a <=( a9356a and a9351a );
a9361a <=( A299 and (not A298) );
a9362a <=( (not A200) and a9361a );
a9366a <=( (not A302) and (not A301) );
a9367a <=( (not A300) and a9366a );
a9368a <=( a9367a and a9362a );
a9372a <=( A168 and (not A169) );
a9373a <=( A170 and a9372a );
a9377a <=( (not A201) and A200 );
a9378a <=( (not A199) and a9377a );
a9379a <=( a9378a and a9373a );
a9383a <=( A298 and (not A203) );
a9384a <=( (not A202) and a9383a );
a9387a <=( (not A300) and (not A299) );
a9390a <=( (not A302) and (not A301) );
a9391a <=( a9390a and a9387a );
a9392a <=( a9391a and a9384a );
a9396a <=( A168 and (not A169) );
a9397a <=( A170 and a9396a );
a9401a <=( (not A201) and A200 );
a9402a <=( (not A199) and a9401a );
a9403a <=( a9402a and a9397a );
a9407a <=( (not A298) and (not A203) );
a9408a <=( (not A202) and a9407a );
a9411a <=( (not A300) and A299 );
a9414a <=( (not A302) and (not A301) );
a9415a <=( a9414a and a9411a );
a9416a <=( a9415a and a9408a );
a9420a <=( A168 and (not A169) );
a9421a <=( A170 and a9420a );
a9425a <=( (not A201) and (not A200) );
a9426a <=( A199 and a9425a );
a9427a <=( a9426a and a9421a );
a9431a <=( A298 and (not A203) );
a9432a <=( (not A202) and a9431a );
a9435a <=( (not A300) and (not A299) );
a9438a <=( (not A302) and (not A301) );
a9439a <=( a9438a and a9435a );
a9440a <=( a9439a and a9432a );
a9444a <=( A168 and (not A169) );
a9445a <=( A170 and a9444a );
a9449a <=( (not A201) and (not A200) );
a9450a <=( A199 and a9449a );
a9451a <=( a9450a and a9445a );
a9455a <=( (not A298) and (not A203) );
a9456a <=( (not A202) and a9455a );
a9459a <=( (not A300) and A299 );
a9462a <=( (not A302) and (not A301) );
a9463a <=( a9462a and a9459a );
a9464a <=( a9463a and a9456a );
a9468a <=( (not A168) and (not A169) );
a9469a <=( A170 and a9468a );
a9473a <=( A201 and (not A166) );
a9474a <=( A167 and a9473a );
a9475a <=( a9474a and a9469a );
a9479a <=( A298 and (not A203) );
a9480a <=( (not A202) and a9479a );
a9483a <=( (not A300) and (not A299) );
a9486a <=( (not A302) and (not A301) );
a9487a <=( a9486a and a9483a );
a9488a <=( a9487a and a9480a );
a9492a <=( (not A168) and (not A169) );
a9493a <=( A170 and a9492a );
a9497a <=( A201 and (not A166) );
a9498a <=( A167 and a9497a );
a9499a <=( a9498a and a9493a );
a9503a <=( (not A298) and (not A203) );
a9504a <=( (not A202) and a9503a );
a9507a <=( (not A300) and A299 );
a9510a <=( (not A302) and (not A301) );
a9511a <=( a9510a and a9507a );
a9512a <=( a9511a and a9504a );
a9516a <=( (not A168) and (not A169) );
a9517a <=( A170 and a9516a );
a9521a <=( A201 and A166 );
a9522a <=( (not A167) and a9521a );
a9523a <=( a9522a and a9517a );
a9527a <=( A298 and (not A203) );
a9528a <=( (not A202) and a9527a );
a9531a <=( (not A300) and (not A299) );
a9534a <=( (not A302) and (not A301) );
a9535a <=( a9534a and a9531a );
a9536a <=( a9535a and a9528a );
a9540a <=( (not A168) and (not A169) );
a9541a <=( A170 and a9540a );
a9545a <=( A201 and A166 );
a9546a <=( (not A167) and a9545a );
a9547a <=( a9546a and a9541a );
a9551a <=( (not A298) and (not A203) );
a9552a <=( (not A202) and a9551a );
a9555a <=( (not A300) and A299 );
a9558a <=( (not A302) and (not A301) );
a9559a <=( a9558a and a9555a );
a9560a <=( a9559a and a9552a );
end x25_3x_behav;
|
gpl-3.0
|
rhexsel/xinu-cMIPS
|
vhdl/core.vhd
|
1
|
125889
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- CPU core
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
use work.p_exception.all;
entity core is
port (
rst : in std_logic;
clk : in std_logic;
phi1 : in std_logic;
phi2 : in std_logic;
phi3 : in std_logic;
i_aVal : out std_logic;
i_wait : in std_logic;
i_addr : out reg32;
instr : in reg32;
d_aVal : out std_logic;
d_wait : in std_logic;
d_addr : out reg32;
data_inp : in reg32;
data_out : out reg32;
wr : out std_logic;
b_sel : out reg4;
busFree : out std_logic;
nmi : in std_logic;
irq : in reg6;
i_busErr : in std_logic;
d_busErr : in std_logic);
end core;
architecture rtl of core is
-- control pipeline registers ------------
component reg_excp_IF_RF is
port(clk, rst, ld: in std_logic;
IF_excp_type: in exception_type;
RF_excp_type: out exception_type;
PC_abort: in boolean;
RF_PC_abort: out boolean;
IF_PC: in std_logic_vector;
RF_PC: out std_logic_vector);
end component reg_excp_IF_RF;
component reg_excp_RF_EX is
port(clk, rst, ld: in std_logic;
RF_cop0_reg: in reg5;
EX_cop0_reg: out reg5;
RF_cop0_sel: in reg3;
EX_cop0_sel: out reg3;
RF_can_trap: in std_logic_vector;
EX_can_trap: out std_logic_vector;
RF_exception: in exception_type;
EX_exception: out exception_type;
RF_is_delayslot: in std_logic;
EX_is_delayslot: out std_logic;
RF_PC_abort: in boolean;
EX_PC_abort: out boolean;
RF_PC: in std_logic_vector;
EX_PC: out std_logic_vector;
RF_trap_taken: in boolean;
EX_trapped: out boolean);
end component reg_excp_RF_EX;
component reg_excp_EX_MM is
port(clk, rst, ld: in std_logic;
EX_cop0_reg: in reg5;
MM_cop0_reg: out reg5;
EX_cop0_sel: in reg3;
MM_cop0_sel: out reg3;
EX_PC: in std_logic_vector;
MM_PC: out std_logic_vector;
EX_v_addr: in std_logic_vector;
MM_v_addr: out std_logic_vector;
EX_nullify: in boolean;
MM_nullify: out boolean;
EX_addrError: in boolean;
MM_addrError: out boolean;
EX_addrErr_stage_mm: in boolean;
MM_addrErr_stage_mm: out boolean;
EX_is_delayslot: in std_logic;
MM_is_delayslot: out std_logic;
EX_trapped: in boolean;
MM_trapped: out boolean;
EX_ll_sc_abort: in boolean;
MM_ll_sc_abort: out boolean;
EX_tlb_exception: in boolean;
MM_tlb_exception: out boolean;
EX_tlb_stage_MM: in boolean;
MM_tlb_stage_MM: out boolean;
EX_int_req: in reg6;
MM_int_req: out reg6;
EX_is_SC: in boolean;
MM_is_SC: out boolean;
EX_is_MFC0: in boolean;
MM_is_MFC0: out boolean;
EX_is_exception: in exception_type;
MM_is_exception: out exception_type);
end component reg_excp_EX_MM;
component reg_excp_MM_WB is
port(clk, rst, ld: in std_logic;
MM_PC: in std_logic_vector;
WB_PC: out std_logic_vector;
MM_cop0_LLbit: in std_logic;
WB_cop0_LLbit: out std_logic;
MM_is_delayslot: in std_logic;
WB_is_delayslot: out std_logic;
MM_cop0_val: in std_logic_vector;
WB_cop0_val: out std_logic_vector);
end component reg_excp_MM_WB;
signal nullify_MM_pre, nullify_MM_int :std_logic;
signal annul_1, annul_2, annul_twice : std_logic;
signal interrupt, exception_stall : std_logic;
signal dly_i0, dly_i1, dly_i2, dly_interr: std_logic;
signal exception_taken, interrupt_taken, tlb_excp_taken : std_logic;
signal nullify_fetch, nullify, MM_nullify : boolean;
signal addrError, MM_addrError, abort_ref, MM_ll_sc_abort : boolean;
signal PC_abort, RF_PC_abort, EX_PC_abort : boolean;
signal IF_excp_type,RF_excp_type : exception_type;
signal mem_excp_type, tlb_excp_type : exception_type;
signal trap_instr: instr_type;
signal RF_PC,EX_PC,MM_PC,WB_PC, LLaddr: reg32;
signal ll_sc_bit, MM_LLbit,WB_LLbit: std_logic;
signal LL_update, LL_SC_abort, LL_SC_differ: std_logic;
signal EX_trapped, MM_trapped, EX_ovfl, trap_taken: boolean;
signal int_req, MM_int_req: reg6;
signal can_trap,EX_can_trap : reg2;
signal is_trap, tr_signed, tr_stall: std_logic;
signal tr_is_equal, tr_less_than: std_logic;
signal tr_fwd_A, tr_fwd_B, tr_result : reg32;
signal excp_IF_RF_ld,excp_RF_EX_ld,excp_EX_MM_ld,excp_MM_WB_ld: std_logic;
signal update, not_stalled: std_logic;
signal update_reg : reg5;
signal status_update,epc_update,compare_update: std_logic;
signal disable_count, compare_set, compare_clr: std_logic;
signal STATUSinp, STATUS, CAUSE, EPCinp,EPC : reg32;
signal COUNT, COMPARE : reg32;
signal count_eq_compare,count_update,count_enable : std_logic;
signal exception,EX_exception, MM_exception : exception_type;
signal is_exception, EX_is_exception : exception_type;
signal ExcCode : reg5 := cop0code_NULL;
signal exception_dec,TLB_excp_num,trap_dec: integer; -- debugging
signal RF_is_delayslot,EX_is_delayslot,MM_is_delayslot,WB_is_delayslot,is_delayslot : std_logic;
signal cop0_sel, EX_cop0_sel, MM_cop0_sel, epc_source : reg3;
signal cop0_reg,EX_cop0_reg,MM_cop0_reg : reg5;
signal cop0_inp, RF_cop0_val,MM_cop0_val,WB_cop0_val : reg32;
signal BadVAddr, BadVAddr_inp : reg32;
signal BadVAddr_update : std_logic;
signal is_SC, MM_is_SC, is_MFC0, MM_is_MFC0 : boolean;
signal is_busError, is_nmi, is_interr, is_ovfl : boolean;
signal busError_type : exception_type;
-- MMU signals --
signal INDEX, index_inp, RANDOM, WIRED, wired_inp : reg32;
signal index_update, wired_update : std_logic;
signal EntryLo0, EntryLo1, EntryLo0_inp, EntryLo1_inp : reg32;
signal EntryHi, EntryHi_inp, v_addr, MM_v_addr : reg32;
signal Context, PageMask, PageMask_inp : reg32;
signal entryLo0_update, entryLo1_update, entryHi_update : std_logic;
signal context_upd_pte, context_upd_bad, tlb_read, tlb_ex_2 : std_logic;
signal tlb_entrylo0_mm, tlb_entrylo1_mm, tlb_entryhi : reg32;
signal tlb_tag0_updt, tlb_tag1_updt, tlb_tag2_updt, tlb_tag3_updt : std_logic;
signal tlb_tag4_updt, tlb_tag5_updt, tlb_tag6_updt, tlb_tag7_updt : std_logic;
signal tlb_dat0_updt, tlb_dat1_updt, tlb_dat2_updt, tlb_dat3_updt : std_logic;
signal tlb_dat4_updt, tlb_dat5_updt, tlb_dat6_updt, tlb_dat7_updt : std_logic;
signal hit0_pc, hit1_pc, hit2_pc, hit3_pc, hit_pc : boolean;
signal hit4_pc, hit5_pc, hit6_pc, hit7_pc : boolean;
signal hit0_mm, hit1_mm, hit2_mm, hit3_mm, hit_mm : boolean;
signal hit4_mm, hit5_mm, hit6_mm, hit7_mm: boolean;
signal tlb_exception,MM_tlb_exception,tlb_stage_mm,MM_tlb_stage_mm : boolean;
signal addrErr_stage_mm, MM_addrErr_stage_mm : boolean;
signal hit_mm_v, hit_mm_d, hit_pc_v : std_logic;
signal tlb_adr_mm : MMU_idx_bits;
signal tlb_probe, probe_hit, hit_mm_bit : std_logic;
signal mm, tlb_excp_VA : std_logic_vector(VA_HI_BIT downto VA_LO_BIT);
signal tlb_adr,tlb_a0_pc,tlb_a1_pc,tlb_a2_pc : natural range 0 to (MMU_CAPACITY-1);
signal hit_pc_adr, hit_mm_adr : natural range 0 to (MMU_CAPACITY-1);
signal tlb_a0_mm,tlb_a1_mm,tlb_a2_mm : natural range 0 to (MMU_CAPACITY-1);
signal tlb_ppn_pc0,tlb_ppn_pc1 : mmu_dat_reg;
signal tlb_ppn_mm0,tlb_ppn_mm1 : mmu_dat_reg;
signal tlb_ppn_mm, tlb_ppn_pc : std_logic_vector(PPN_BITS - 1 downto 0);
signal tlb_tag0, tlb_tag1, tlb_tag2, tlb_tag3, tlb_tag_inp : reg32;
signal tlb_tag4, tlb_tag5, tlb_tag6, tlb_tag7, e_hi, e_hi_inp : reg32;
signal tlb_dat0_inp, tlb_dat1_inp, e_lo0, e_lo1 : mmu_dat_reg;
signal tlb_dat0_0, tlb_dat1_0, tlb_dat2_0, tlb_dat3_0 : mmu_dat_reg;
signal tlb_dat0_1, tlb_dat1_1, tlb_dat2_1, tlb_dat3_1 : mmu_dat_reg;
signal tlb_dat4_0, tlb_dat5_0, tlb_dat6_0, tlb_dat7_0 : mmu_dat_reg;
signal tlb_dat4_1, tlb_dat5_1, tlb_dat6_1, tlb_dat7_1 : mmu_dat_reg;
signal tlb_entryLo0, tlb_entryLo1, phy_i_addr, phy_d_addr : reg32;
-- other components ------------
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
component adder32 is
port(A, B : in std_logic_vector;
C : out std_logic_vector);
end component adder32;
component mf_alt_add_4 IS
port(datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) );
end component mf_alt_add_4;
component mf_alt_adder IS
port(dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end component mf_alt_adder;
component subtr32 IS
port(A,B : in std_logic_vector (31 downto 0);
C : out std_logic_vector (31 downto 0);
sgnd : in std_logic;
ovfl,lt : out std_logic);
end component subtr32;
component reg_bank is
port(wrclk, rdclk, wren: in std_logic;
a_rs, a_rt, a_rd: in std_logic_vector;
C: in std_logic_vector;
A, B: out std_logic_vector);
end component reg_bank;
component register32 is
generic (INITIAL_VALUE: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component register32;
component registerN is
generic (NUM_BITS: integer; INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component registerN;
component counter32 is
generic (INITIAL_VALUE: std_logic_vector);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector;
Q: out std_logic_vector);
end component counter32;
component alu is
port(clk, rst: in std_logic;
A, B: in std_logic_vector;
C: out std_logic_vector;
LO: out std_logic_vector;
HI: out std_logic_vector;
wr_hilo: in std_logic;
move_ok: out std_logic;
fun: in t_alu_fun;
postn: in std_logic_vector;
shamt: in std_logic_vector;
ovfl: out std_logic);
end component alu;
signal PC,PC_aligned : reg32;
signal PCinp,PCinp_noExcp, PCincd : reg32;
signal instr_fetched : reg32;
signal PCload, IF_RF_ld : std_logic;
signal PCsel : reg2;
signal excp_PCsel : reg3;
signal rom_stall, iaVal, if_stalled, mem_stall, pipe_stall : std_logic;
signal ram_stall, daVal, mm_stalled : std_logic;
signal br_target, br_addend, br_tgt_pl4, br_tgt_displ, j_target : reg32;
signal RF_PCincd, RF_instruction : reg32;
signal eq_fwd_A,eq_fwd_B : reg32;
signal dbg_jr_stall: integer; -- debugging only
-- register fetch/read and instruction decode --
component reg_IF_RF is
port(clk, rst, ld: in std_logic;
PCincd_d: in std_logic_vector;
PCincd_q: out std_logic_vector;
instr: in std_logic_vector;
RF_instr: out std_logic_vector);
end component reg_IF_RF;
signal opcode, func: reg6;
signal ctrl_word: t_control_type;
signal funct_word: t_function_type;
signal rimm_word: t_rimm_type;
signal syscall_n : reg20;
signal displ16: reg16;
signal br_operand: reg32;
signal br_opr: reg2;
signal br_equal,br_negative,br_eq_zero: boolean;
signal flush_RF_EX: boolean := FALSE;
signal is_branch: std_logic;
signal c_sel : reg2;
-- execution and beyond --
signal RF_EX_ld, EX_MM_ld, MM_WB_ld: std_logic;
signal a_rs,EX_a_rs, a_rt,EX_a_rt,MM_a_rt, a_rd: reg5;
signal a_c,EX_a_c,MM_a_c,WB_a_c: reg5;
signal move,EX_move,MM_move : std_logic;
signal is_load,EX_is_load,MM_is_load : boolean;
signal muxC,EX_muxC,MM_muxC,WB_muxC: reg3;
signal wreg,EX_wreg_pre,EX_wreg,MM_wreg_cond,MM_wreg,WB_wreg: std_logic;
signal aVal,EX_aVal,EX_aVal_cond,MM_aVal: std_logic;
signal wrmem,EX_wrmem,EX_wrmem_cond,MM_wrmem, m_sign_ext: std_logic;
signal mem_t, EX_mem_t,MM_mem_t: reg4;
signal WB_mem_t : reg2;
signal alu_inp_A,alu_fwd_B,alu_inp_B : reg32;
signal alu_move_ok, MM_alu_move_ok, ovfl : std_logic;
signal selB,EX_selB: std_logic;
signal oper,EX_oper: t_alu_fun;
signal EX_postn, shamt,EX_shamt: reg5;
signal regs_A,EX_A,MM_A,WB_A, regs_B,EX_B,MM_B: reg32;
signal displ32,EX_displ32: reg32;
signal result,MM_result,WB_result,WB_C, EX_addr,MM_addr: reg32;
signal pc_p8,EX_pc_p8,MM_pc_p8,WB_pc_p8 : reg32;
signal HI,MM_HI,WB_HI, LO,MM_LO,WB_LO : reg32;
-- data memory --
signal rd_data_raw, rd_data, WB_rd_data, WB_mem_data: reg32;
signal MM_B_data, WB_B_data: reg32;
signal jr_stall, br_stall, sw_stall, lw_stall : std_logic;
signal fwd_lwlr : boolean;
signal fwd_mem, WB_addr2: reg2;
component reg_RF_EX is
port(clk, rst, ld: in std_logic;
selB: in std_logic;
EX_selB: out std_logic;
oper: in t_alu_fun;
EX_oper: out t_alu_fun;
a_rs: in std_logic_vector;
EX_a_rs: out std_logic_vector;
a_rt: in std_logic_vector;
EX_a_rt: out std_logic_vector;
a_c: in std_logic_vector;
EX_a_c: out std_logic_vector;
wreg: in std_logic;
EX_wreg: out std_logic;
muxC: in std_logic_vector;
EX_muxC: out std_logic_vector;
move: in std_logic;
EX_move: out std_logic;
postn: in std_logic_vector;
EX_postn: out std_logic_vector;
shamt: in std_logic_vector;
EX_shamt: out std_logic_vector;
aVal: in std_logic;
EX_aVal: out std_logic;
wrmem: in std_logic;
EX_wrmem: out std_logic;
mem_t: in std_logic_vector;
EX_mem_t: out std_logic_vector;
is_load: in boolean;
EX_is_load: out boolean;
A: in std_logic_vector;
EX_A: out std_logic_vector;
B: in std_logic_vector;
EX_B: out std_logic_vector;
displ32: in std_logic_vector;
EX_displ32: out std_logic_vector;
pc_p8: in std_logic_vector;
EX_pc_p8: out std_logic_vector);
end component reg_RF_EX;
component reg_EX_MM is
port(clk, rst, ld: in std_logic;
EX_a_rt: in std_logic_vector;
MM_a_rt: out std_logic_vector;
EX_a_c: in std_logic_vector;
MM_a_c: out std_logic_vector;
EX_wreg: in std_logic;
MM_wreg: out std_logic;
EX_muxC: in std_logic_vector;
MM_muxC: out std_logic_vector;
EX_aVal: in std_logic;
MM_aVal: out std_logic;
EX_wrmem: in std_logic;
MM_wrmem: out std_logic;
EX_mem_t: in std_logic_vector;
MM_mem_t: out std_logic_vector;
EX_is_load: in boolean;
MM_is_load: out boolean;
EX_A: in std_logic_vector;
MM_A: out std_logic_vector;
EX_B: in std_logic_vector;
MM_B: out std_logic_vector;
EX_result: in std_logic_vector;
MM_result: out std_logic_vector;
EX_addr: in std_logic_vector;
MM_addr: out std_logic_vector;
HI: in std_logic_vector;
MM_HI: out std_logic_vector;
LO: in std_logic_vector;
MM_LO: out std_logic_vector;
EX_alu_move_ok: in std_logic;
MM_alu_move_ok: out std_logic;
EX_move: in std_logic;
MM_move: out std_logic;
EX_pc_p8: in std_logic_vector;
MM_pc_p8: out std_logic_vector);
end component reg_EX_MM;
component reg_MM_WB is
port(clk, rst, ld: in std_logic;
MM_a_c: in std_logic_vector;
WB_a_c: out std_logic_vector;
MM_wreg: in std_logic;
WB_wreg: out std_logic;
MM_muxC: in std_logic_vector;
WB_muxC: out std_logic_vector;
MM_A: in std_logic_vector;
WB_A: out std_logic_vector;
MM_result: in std_logic_vector;
WB_result: out std_logic_vector;
MM_HI: in std_logic_vector;
WB_HI: out std_logic_vector;
MM_LO: in std_logic_vector;
WB_LO: out std_logic_vector;
rd_data: in std_logic_vector;
WB_rd_data: out std_logic_vector;
MM_B_data: in std_logic_vector;
WB_B_data: out std_logic_vector;
MM_addr2: in std_logic_vector;
WB_addr2: out std_logic_vector;
MM_oper: in std_logic_vector;
WB_oper: out std_logic_vector;
MM_pc_p8: in std_logic_vector;
WB_pc_p8: out std_logic_vector);
end component reg_MM_WB;
-- fields of the control table
-- aVal: std_logic; -- addressValid, enable data-mem=0
-- wmem: std_logic; -- READ=1/WRITE=0 in/to memory
-- i: instr_type; -- instruction
-- wreg: std_logic; -- register write=0
-- selB: std_logic; -- B ALU input, reg=0 ext=1
-- fun: std_logic; -- check function_field=1
-- oper: t_alu_fun; -- ALU operation
-- muxC: reg3; -- select result mem=0 ula=1 jr=2 pc+8=3
-- c_sel: reg2; -- select destination reg RD=0 RT=1 31=2
-- extS: std_logic; -- sign-extend=1, zero-ext=0
-- PCsel: reg2; -- PCmux 0=PC+4 1=beq 2=j 3=jr
-- br_t: t_comparison; -- branch: 0=no 1=beq 2=bne
-- excp: reg2 -- stage with exception 0=no,1=rf,2=ex,3=mm
constant ctrl_table : t_control_mem := (
--aVal wmem ins wreg selB fun oper muxC csel extS PCsel br_t excp
('1','1',iALU, '1','0','1',opNOP,"001","00", '0', "00",cNOP,"00"),--ALU=0
('1','1',RIMM, '1','0','0',opNOP,"001","00", '1', "00",cOTH,"00"),--BR=1
('1','1',J, '1','0','0',opNOP,"001","00", '0', "10",cNOP,"00"),--j=2
('1','1',JAL, '0','0','0',opNOP,"011","10", '0', "10",cNOP,"00"),--jal=3
('1','1',BEQ, '1','0','0',opNOP,"001","00", '1', "01",cEQU,"00"),--beq=4
('1','1',BNE, '1','0','0',opNOP,"001","00", '1', "01",cNEQ,"00"),--bne=5
('1','1',BLEZ, '1','0','0',opNOP,"001","00", '1', "01",cLEZ,"00"),--blez=6
('1','1',BGTZ, '1','0','0',opNOP,"001","00", '1', "01",cGTZ,"00"),--bgtz=7
('1','1',ADDI, '0','1','0',opADD,"001","01", '1', "00",cNOP,"10"),--addi=8
('1','1',ADDIU,'0','1','0',opADD,"001","01", '1', "00",cNOP,"00"),--addiu=9
('1','1',SLTI, '0','1','0',opSLT,"001","01", '1', "00",cNOP,"10"),--slti=10
('1','1',SLTIU,'0','1','0',opSLTU,"001","01",'1', "00",cNOP,"00"),--sltiu11
('1','1',ANDI, '0','1','0',opAND,"001","01", '0', "00",cNOP,"00"),--andi=12
('1','1',ORI, '0','1','0',opOR, "001","01", '0', "00",cNOP,"00"),--ori=13
('1','1',XORI, '0','1','0',opXOR,"001","01", '0', "00",cNOP,"00"),--xori=14
('1','1',LUI, '0','1','0',opLUI,"001","01", '0', "00",cNOP,"00"),--lui=15
('1','1',COP0, '1','0','1',opNOP,"110","01", '0', "00",cNOP,"00"),--COP0=16
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--17
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--18
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--19
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--beql=20
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--bnel=21
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--blzel=22
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--bgtzl=23
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--24
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--25
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--26
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--27
('1','1',SPEC2,'0','0','0',opSPC,"001","00", '0', "00",cNOP,"00"),--28
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--29
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--30
('1','1',SPEC3,'0','0','0',opSPC,"001","00", '0', "00",cNOP,"00"),--special3
('0','1',LB, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lb=32
('0','1',LH, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lh=33
('0','1',LWL, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lwl=34
('0','1',LW, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lw=35
('0','1',LBU, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lbu=36
('0','1',LHU, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lhu=37
('0','1',LWR, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--lwr=38
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--39
('0','0',SB, '1','1','0',opADD,"001","00", '1', "00",cNOP,"11"),--sb=40
('0','0',SH, '1','1','0',opADD,"001","00", '1', "00",cNOP,"11"),--sh=41
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--swl=42
('0','0',SW, '1','1','0',opADD,"001","00", '1', "00",cNOP,"11"),--sw=43
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--44
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--45
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--swr=46
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--cache=47
('0','1',LL, '0','1','0',opADD,"000","01", '1', "00",cNOP,"11"),--ll=48
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--lwc1=49
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--lwc2=50
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--pref=51
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--52
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--ldc1=53
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--ldc2=54
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--55
('0','0',SC, '0','1','0',opADD,"111","01", '1', "00",cNOP,"11"),--sc=56
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--swc1=57
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--swc2=58
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--59
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--60
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--sdc1=61
('1','1',NIL, '1','0','0',opNOP,"001","00", '0', "00",cNOP,"00"),--sdc2=62
('1','1',NOP, '1','0','0',opNOP,"000","00", '0', "00",cNOP,"00") --63
);
-- fields of the function table (opcode=0)
-- i: instr_type; -- instruction
-- wreg: std_logic; -- register write=0
-- selB: std_logic; -- B ALU input, reg=0 ext=1
-- oper: t_alu_fun; -- ALU operation
-- muxC: reg3; -- select result mem=0 ula=1 jr=2 pc+8=3
-- trap: std_logic; -- trap on compare
-- move: std_logic; -- conditional move
-- sync: std_logic; -- synch the memory hierarchy
-- PCsel: reg2; -- PCmux 0=PC+4 1=beq 2=j 3=jr
-- excp: reg2 -- stage with exception 0=no,1=rf,2=ex,3=mm
constant func_table : t_function_mem := (
-- i wreg selB oper muxC trap mov syn PCsel excp
(iSLL, '0','0',opSLL, "001",'0','0','0',"00","00"), --sll=0, EHB
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --1, FlPoint
(iSRL, '0','0',opSRL, "001",'0','0','0',"00","00"), --srl=2
(iSRA, '0','0',opSRA, "001",'0','0','0',"00","00"), --sra=3
(SLLV, '0','0',opSLLV, "001",'0','0','0',"00","00"), --sllv=4
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --5
(SRLV, '0','0',opSRLV, "001",'0','0','0',"00","00"), --srlv=6
(SRAV, '0','0',opSRAV, "001",'0','0','0',"00","00"), --srav=7
(JR, '1','0',opNOP, "001",'0','0','0',"11","00"), --jr=8
(JALR, '0','0',opNOP, "011",'0','0','0',"11","00"), --jalr=9
(MOVZ, '0','0',opMOVZ, "001",'0','1','0',"00","00"), --movz=10
(MOVN, '0','0',opMOVN, "001",'0','1','0',"00","00"), --movn=11
(SYSCALL,'1','0',trNOP,"001",'1','0','0',"00","00"), --syscall=12
(BREAK,'1','0',trNOP, "001",'1','0','0',"00","00"), --break=13
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --14
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --15
(MFHI, '0','0',opMFHI, "100",'0','0','0',"00","00"), --mfhi=16
(MTHI, '1','0',opMTHI, "001",'0','0','0',"00","00"), --mthi=17
(MFLO, '0','0',opMFLO, "101",'0','0','0',"00","00"), --mflo=18
(MTLO, '1','0',opMTLO, "001",'0','0','0',"00","00"), --mtlo=19
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --20
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --21
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --22
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --23
(MULT, '1','0',opMULT, "001",'0','0','0',"00","00"), --mult=24
(MULTU,'1','0',opMULTU,"001",'0','0','0',"00","00"), --multu=25
(DIV, '1','0',opDIV, "001",'0','0','0',"00","00"), --div=26
(DIVU, '1','0',opDIVU, "001",'0','0','0',"00","00"), --divu=27
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --28
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --29
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --30
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --31
(ADD, '0','0',opADD, "001",'0','0','0',"00","10"), --add=32
(ADDU, '0','0',opADDU, "001",'0','0','0',"00","00"), --addu=33
(SUB, '0','0',opSUB, "001",'0','0','0',"00","10"), --sub=34
(SUBU, '0','0',opSUBU, "001",'0','0','0',"00","00"), --subu=35
(iAND, '0','0',opAND, "001",'0','0','0',"00","00"), --and=36
(iOR, '0','0',opOR, "001",'0','0','0',"00","00"), --or=37
(iXOR, '0','0',opXOR, "001",'0','0','0',"00","00"), --xor=38
(iNOR, '0','0',opNOR, "001",'0','0','0',"00","00"), --nor=39
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --40
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --41
(SLT, '0','0',opSLT, "001",'0','0','0',"00","10"), --slt=42
(SLTU, '0','0',opSLTU, "001",'0','0','0',"00","00"), --sltu=43
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --44
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --45
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --46
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --47
(TGE, '1','0',trGEQ, "001",'1','0','0',"00","10"), --tge=48
(TGEU, '1','0',trGEU, "001",'1','0','0',"00","10"), --tgeu=49
(TLT, '1','0',trLTH, "001",'1','0','0',"00","10"), --tlt=50
(TLTU, '1','0',trLTU, "001",'1','0','0',"00","10"), --tltu=51
(TEQ, '1','0',trEQU, "001",'1','0','0',"00","10"), --teq=52
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --53
(TNE, '1','0',trNEQ, "001",'1','0','0',"00","10"), --tne=54
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --55
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --56
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --57
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --58
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --59
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --60
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --61
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --62
(NOP, '1','0',opNOP, "001",'0','0','0',"00","00") --63
);
-- fields of the register-immediate control table (opcode=1)
-- i: instr_type; -- instruction
-- wreg: std_logic; -- register write=0
-- selB: std_logic; -- B ALU input, reg=0 ext=1
-- br_t: t_comparison; -- comparison type: ltz,gez
-- muxC: reg3; -- select result mem=0 ula=1 jr=2 *al(pc+8)=3
-- c_sel: reg2 -- select destination reg rd=0 rt=1 31=2
-- trap: std_logic; -- trap on compare
-- PCsel: reg2; -- PCmux 0=PC+4 1=beq 2=j 3=jr
-- excp: reg2 -- stage with exception 0=no,1=rf,2=ex,3=mm
constant rimm_table : t_rimm_mem := (
-- i wreg selB br_t muxC csel trap PCsel excp
(BLTZ, '1','0',cLTZ, "001","00",'0',"01","00"), --0bltz
(BGEZ, '1','0',cGEZ, "001","00",'0',"01","00"), --1bgez
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --2
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --3
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --4
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --5
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --6
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --7
(TGEI, '1','1',tGEQ, "001","00",'1',"00","10"), --8tgei
(TGEIU,'1','1',tGEU, "001","00",'1',"00","10"), --9tgeiu
(TLTI, '1','1',tLTH, "001","00",'1',"00","10"), --10tlti
(TLTIU,'1','1',tLTU, "001","00",'1',"00","10"), --11tltiu
(TEQI, '1','1',tEQU, "001","00",'1',"00","10"), --12teqi
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --13
(TNEI, '1','1',tNEQ, "001","00",'1',"00","10"), --14tnei
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --15
(BLTZAL,'0','0',cLTZ,"011","10",'0',"01","00"), --16bltzal
(BGEZAL,'0','0',cGEZ,"011","10",'0',"01","00"), --17bgezal
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --18
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --19
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --20
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --21
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --22
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --23
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --24
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --25
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --26
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --27
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --28
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --29
(NIL, '1','0',cNOP, "001","00",'0',"00","00"), --30
(NOP, '1','0',cNOP, "001","00",'0',"00","00") --31
);
-- Table 8-30 Config Register Field Descriptions, pg 101
constant CONFIG0 : reg32 := (
'1'& -- M, Config1 implemented = 1
b"000"& -- K23, with MMU, kseg2,kseg3 coherency algorithm
b"000"& -- KU, with MMU, kuseg coherency algorithm
b"000000000"& -- Impl, implementation dependent = 0
'0'& -- BE, little endian = 0
b"00"& -- AT, MIPS32 = 0
b"001"& -- AR, Release 2 = 1
b"001"& -- MT, MMU type = 1, standard
b"000"& -- nil, always zero = 0
'1'& -- VI, Instruction Cache is virtual = 1
b"000" -- K0, Kseg0 coherency algorithm
);
-- Table 8-31 Config1 Register Field Descriptions, pg 103
constant CONFIG1 : reg32 := (
'0'& -- M, Config2 not implemented = 0
MMU_SIZE & -- MMUsz, MMU entries minus 1
IC_SETS_PER_WAY & -- ICS, IC sets per way
IC_LINE_SIZE & -- ICL, IC line size
IC_ASSOCIATIVITY & -- ICA, IC associativity
DC_SETS_PER_WAY & -- DCS, DC sets per way
DC_LINE_SIZE & -- DCL, DC line size = 3 16 bytes/line
DC_ASSOCIATIVITY & -- DCA, DC associativity = 0 direct mapped
'0'& -- C2, No coprocessor 2 implemented = 0
'0'& -- MD, No MDMX ASE implemented = 0
'0'& -- PC, No performance counters implemented = 0
'0'& -- WR, No watch registers implemented = 0
'0'& -- CA, No code compression implemented = 0
'0'& -- EP, No EJTAG implemented = 0
'0' -- FP, No FPU implemented = 0
);
-- pipeline ============================================================
begin
-- INSTR_FETCH_STATE_MACHINE: instruction-bus control
U_ifetch_stalled: FFD port map (clk => phi2, rst => rst, set => '1',
D => mem_stall, Q => if_stalled);
-- iaVal <= '1' when ((phi0 = '1' and if_stalled = '0')) else '0';
i_aVal <= '0'; -- interface signal/port, always fetches a new instruction
iaVal <= '0'; -- internal signal
rom_stall <= not(iaVal) and not(i_wait);
mem_stall <= ram_stall or rom_stall;
not_stalled <= not(mem_stall);
-- end INSTR_FETCH_STATE_MACHINE --------------------------
-- PROGRAM COUNTER AND INSTRUCTION FETCH ------------------
pipe_stall <= rom_stall or ram_stall or jr_stall or br_stall or
sw_stall or lw_stall or tr_stall or exception_stall;
PCload <= '1' when pipe_stall = '1' else '0';
IF_RF_ld <= '1' when pipe_stall = '1' else '0';
RF_EX_ld <= mem_stall; -- or exception_stall;
EX_MM_ld <= mem_stall;
MM_WB_ld <= mem_stall;
excp_IF_RF_ld <= '1' when pipe_stall = '1' else '0';
excp_RF_EX_ld <= mem_stall; -- or exception_stall;
excp_EX_MM_ld <= mem_stall;
excp_MM_WB_ld <= mem_stall;
with PCsel select
PCinp_noExcp <= PCincd when b"00", -- next instruction
br_target when b"01", -- taken branch
j_target when b"10", -- jump
eq_fwd_A when b"11", -- jump register regs_A
(others => 'X') when others;
with excp_PCsel select
PCinp <= PCinp_noExcp when PCsel_EXC_none, -- no exception
EPC when PCsel_EXC_EPC, -- ERET
x_EXCEPTION_0000 when PCsel_EXC_0000, -- TLBrefill entry point
x_EXCEPTION_0180 when PCsel_EXC_0180, -- general exception handler
x_EXCEPTION_0200 when PCsel_EXC_0200, -- separate interrupt handler
x_EXCEPTION_BFC0 when PCsel_EXC_BFC0, -- NMI or soft-reset handler
(others => 'X') when others;
-- x_EXCEPTION_0100 when PCsel_EXC_0100, -- Cache Error
PC_abort <= PC(1 downto 0) /= b"00";
IF_excp_type <= IFaddressError when PC_abort else exNOP;
PIPESTAGE_PC: register32 generic map (x_INST_BASE_ADDR)
port map (clk, rst, PCload, PCinp, PC);
PC_aligned <= PC(31 downto 2) & b"00";
-- PCincd <= std_logic_vector( 4 + signed(PC_aligned) );
U_INCPC: mf_alt_add_4 PORT MAP( datab => PC_aligned, result => PCincd );
-- uncomment this when NOT making use of the TLB
i_addr <= PC_aligned; -- fetch instruction from aligned address
-- uncomment this when making use of the TLB
-- i_addr <= phy_i_addr;
nullify_fetch <= (MM_tlb_exception and not(MM_tlb_stage_mm));
instr_fetched(25 downto 0) <= instr(25 downto 0);
instr_fetched(31 downto 26) <= instr(31 downto 26)
when not(nullify_fetch or PC_abort
or MM_addrError)
else NULL_INSTRUCTION(31 downto 26); -- x"fc";
PIPESTAGE_IF_RF: reg_IF_RF
port map (clk,rst, IF_RF_ld, PCincd, RF_PCincd,
instr_fetched, RF_instruction);
-- INSTRUCTION DECODE AND REGISTER FETCH -----------------
annul_1 <= BOOL2SL(nullify or MM_addrError);
U_NULLIFY_TWICE: FFD port map (clk, rst, '1', annul_1, annul_2);
annul_twice <= annul_1 or annul_2;
opcode <= RF_instruction(31 downto 26) when annul_twice = '0' else
NULL_INSTRUCTION (31 downto 26);
a_rs <= RF_instruction(25 downto 21);
a_rt <= RF_instruction(20 downto 16);
a_rd <= RF_instruction(15 downto 11);
shamt <= RF_instruction(10 downto 6);
func <= RF_instruction( 5 downto 0);
displ16 <= RF_instruction(15 downto 0);
syscall_n <= RF_instruction(25 downto 6);
ctrl_word <= ctrl_table( to_integer(unsigned(opcode)) );
funct_word <=
func_table( to_integer(unsigned(func)) ) when opcode = b"000000" else
func_table( 63 ); -- null instruction (sigs inactive)
rimm_word <=
rimm_table( to_integer(unsigned(a_rt)) ) when opcode = b"000001" else
rimm_table( 31 ); -- null instruction (sigs inactive)
is_branch <= '1' when ((ctrl_word.br_t /= cNOP)
or((rimm_word.br_t /= cNOP)and(rimm_word.trap='0')))
else '0';
is_trap <= '1' when ((funct_word.trap = '1')or(rimm_word.trap = '1'))
else '0';
RF_is_delayslot <= '1' when ((ctrl_word.PCsel /= "00") or
(funct_word.PCsel /= "00") or
(rimm_word.PCsel /= "00"))
else '0';
RF_STOP_SIMULATION: process (rst, phi2, opcode, func,
ctrl_word, funct_word, rimm_word,
RF_PC, exception, syscall_n)
begin
if rst = '1' and phi2 = '1' then
-- normal end of simulation, instruction "wait 0"
assert not(exception = exWAIT and syscall_n = x"80000")
report LF & "cMIPS BREAKPOINT at PC="& SLV32HEX(RF_PC) &
" opc="& SLV2STR(opcode) & " fun=" & SLV2STR(func) &
" brk=" & SLV2STR(syscall_n) &
LF & "SIMULATION ENDED (correctly?) AT exit();"
severity failure;
-- simulation aborted by instruction "wait N"
assert not(exception = exWAIT and syscall_n /= x"80000")
report LF & " PC="& SLV32HEX(PC) &
" EPC="& SLV32HEX(EPC) &
" bad="& SLV32HEX(BadVAddr) &
" opc="& SLV2STR(opcode) & " wait=" & SLV2STR(syscall_n(7 downto 0)) &
" instr=" & SLV32HEX(RF_instruction) &
LF & "SIMULATION ABORTED AT EXCEPTION HANDLER;"
severity failure;
-- abort on invalid/unimplemented opcodes
if opcode = b"000000" and funct_word.i = NIL then
assert (1=0)
report LF & "INVALID OPCODE at PC="& SLV32HEX(RF_PC) &
" opc="& SLV2STR(opcode) & " instr=" & SLV32HEX(RF_instruction) &
LF & "SIMULATION ABORTED"
severity failure;
elsif opcode = b"000001" and rimm_word.i = NIL then
assert (1=0)
report LF & "INVALID OPCODE at PC="& SLV32HEX(RF_PC) &
" opc="& SLV2STR(opcode) & " instr=" & SLV32HEX(RF_instruction) &
LF & "SIMULATION ABORTED"
severity failure;
elsif ctrl_word.i = NIL then
assert (1=0)
report LF & "INVALID OPCODE at PC="& SLV32HEX(RF_PC) &
" opc="& SLV2STR(opcode) & " instr=" & SLV32HEX(RF_instruction) &
LF & "SIMULATION ABORTED"
severity failure;
end if;
end if;
end process RF_STOP_SIMULATION;
move <= funct_word.move when opcode = b"000000" else '0';
U_regs: reg_bank -- phi1=read_early, clk=write_late
port map (clk, phi1, WB_wreg, a_rs,a_rt, WB_a_c,WB_C, regs_A,regs_B);
-- U_PC_plus_8: adder32 port map (x"00000004", RF_PCincd, pc_p8); -- (PC+4)+4
-- pc_p8 <= std_logic_vector( 4 + signed(RF_PCincd) ); -- (PC+4)+4
U_PC_plus_8: mf_alt_add_4 PORT MAP( datab => RF_PCincd, result => pc_p8 );
displ32 <= x"FFFF" & displ16 when
(displ16(15) = '1' and ctrl_word.extS = '1') else
x"0000" & displ16;
j_target <= RF_PCincd(31 downto 28) & RF_instruction(25 downto 0) & b"00";
RF_JR_STALL: process (funct_word,a_rs,EX_a_c,MM_a_c,EX_wreg,MM_wreg,
MM_is_load)
variable i_dbg_jr_stall : integer := 0; -- debug only
begin
if ( (funct_word.PCsel = b"11")and -- load-delay slot
(EX_a_c /= a_rs)and(EX_wreg = '0')and
(MM_a_c = a_rs)and(MM_wreg = '0')and(MM_a_c /= b"00000") ) then
jr_stall <= '1';
i_dbg_jr_stall := 1;
elsif ( (funct_word.PCsel = b"11")and -- ALU hazard
(EX_a_c = a_rs)and(EX_wreg = '0')and(EX_a_c /= b"00000") ) then
jr_stall <= '1';
i_dbg_jr_stall := 2;
elsif ( (funct_word.PCsel = b"11")and -- 2nd load-delay slot
MM_is_load and
(MM_a_c = a_rs)and(MM_wreg = '0')and(MM_a_c /= b"00000") ) then
jr_stall <= '1';
i_dbg_jr_stall := 3;
else
jr_stall <= '0';
i_dbg_jr_stall := 0;
end if;
dbg_jr_stall <= i_dbg_jr_stall;
end process RF_JR_STALL;
RF_LD_DELAY_SLOT: process (a_rs,a_rt,EX_a_c,EX_wreg,EX_is_load)
begin
if ( EX_is_load and
(EX_wreg = '0') and (EX_a_c /= b"00000") and
( (EX_a_c = a_rs)or(EX_a_c = a_rt) ) ) then
lw_stall <= '1';
else
lw_stall <= '0';
end if;
end process RF_LD_DELAY_SLOT;
RF_SW_STALL: process (ctrl_word,a_rs,EX_a_c,EX_wreg,EX_is_load)
variable is_store : boolean := false;
begin
case ctrl_word.i is
when LB | LH | LWL | LW | LBU | LHU | LWR =>
is_load <= TRUE;
is_store := FALSE;
when SB | SH | SW =>
is_store := TRUE;
is_load <= FALSE;
when others =>
is_load <= FALSE;
is_store := FALSE;
end case;
if ( is_store and EX_is_load and
(EX_a_c = a_rs)and(EX_wreg = '0')and(EX_a_c /= b"00000") ) then
sw_stall <= '1';
else
sw_stall <= '0';
end if;
end process RF_SW_STALL;
RF_FORWARDING_BRANCH: process (a_rs,a_rt,EX_wreg,EX_a_c,MM_wreg,MM_a_c,
MM_aVal,MM_result,MM_cop0_val,MM_is_MFC0,
regs_A,regs_B,is_branch,
is_SC, LL_SC_abort)
variable rs_stall, rt_stall : boolean;
begin
if ( (is_branch = '1') and -- forward_A
(EX_wreg = '0') and (EX_a_c = a_rs) and (EX_a_c /= b"00000") ) then
if is_SC then
eq_fwd_A <= x"0000000" & b"000" & not(LL_SC_abort);
rs_stall := FALSE;
else
eq_fwd_A <= regs_A;
rs_stall := TRUE;
end if;
elsif ( (MM_wreg = '0') and (MM_a_c = a_rs) and (MM_a_c /= b"00000") ) then
if ( (MM_aVal = '0') and (is_branch = '1') ) then -- LW load-delay slot
eq_fwd_A <= regs_A;
rs_stall := TRUE;
elsif MM_is_MFC0 then -- non-LW
eq_fwd_A <= MM_cop0_val;
rs_stall := FALSE;
elsif MM_is_SC then
eq_fwd_A <= x"00000000";
rs_stall := FALSE;
else
eq_fwd_A <= MM_result;
rs_stall := FALSE;
end if;
else
eq_fwd_A <= regs_A;
rs_stall := FALSE;
end if;
if ( (is_branch = '1') and -- forward_B
(EX_wreg = '0') and (EX_a_c = a_rt) and (EX_a_c /= b"00000") ) then
if is_SC then
eq_fwd_B <= x"0000000" & b"000" & not(LL_SC_abort);
rt_stall := FALSE;
else
eq_fwd_B <= regs_B;
rt_stall := TRUE;
end if;
elsif ( (MM_wreg = '0') and (MM_a_c = a_rt) and (MM_a_c /= b"00000") ) then
if ( (MM_aVal = '0') and (is_branch = '1') ) then -- LW load-delay slot
eq_fwd_B <= regs_B;
rt_stall := TRUE;
elsif MM_is_MFC0 then -- non-LW
eq_fwd_B <= MM_cop0_val;
rt_stall := FALSE;
elsif MM_is_SC then
eq_fwd_B <= x"00000000";
rt_stall := FALSE;
else
eq_fwd_B <= MM_result;
rt_stall := FALSE;
end if;
else
eq_fwd_B <= regs_B;
rt_stall := FALSE;
end if;
br_stall <= BOOL2SL(rs_stall or rt_stall);
end process RF_FORWARDING_BRANCH;
br_equal <= (eq_fwd_A = eq_fwd_B);
br_negative <= (eq_fwd_A(31) = '1');
br_eq_zero <= (eq_fwd_A = x"00000000");
RF_BR_tgt_select: process (br_equal,br_negative,br_eq_zero,
ctrl_word,rimm_word)
variable branch_type, regimm_br_type : t_comparison;
variable i_br_opr : reg2;
begin
branch_type := ctrl_word.br_t;
regimm_br_type := rimm_word.br_t;
i_br_opr := b"01"; -- assume not taken, PC+4 + 4 (delay slot)
case branch_type is
when cNOP => -- no branch, PC+4
i_br_opr := b"00";
when cEQU => -- beq
if br_equal then i_br_opr := b"10"; -- br_target;
end if;
when cNEQ => -- bne
if not(br_equal) then i_br_opr := b"10"; -- br_target;
end if;
when cLEZ =>
if (br_negative or br_eq_zero) then i_br_opr := b"10"; -- br_target;
end if;
when cGTZ =>
if not(br_negative or br_eq_zero) then i_br_opr := b"10"; -- br_target;
end if;
when cOTH => -- bltz,blez,bgtz,bgez
case regimm_br_type is
when cLTZ =>
if br_negative then i_br_opr := b"10"; -- br_target;
end if;
when cGEZ =>
if not(br_negative) then i_br_opr := b"10"; -- br_target;
end if;
when others =>
i_br_opr := b"00"; -- x"00000000";
end case;
when others =>
i_br_opr := b"00"; -- x"00000000";
end case;
br_opr <= i_br_opr;
-- assert false report
-- "branch_add32 A="& SLV32HEX(RF_PCincd) &" B="& SLV32HEX(br_operand) &
-- " A+B="& SLV32HEX(br_target); -- DEBUG
end process RF_BR_tgt_select;
-- U_BR_ADDER: adder32 port map (RF_PCincd, br_operand, br_target);
-- br_target <= std_logic_vector( signed(RF_PCincd) + signed(br_operand) );
-- branch target computation is in the citical path; add early, select late
br_addend <= displ32(29 downto 0) & b"00";
U_BR_tgt_pl_4: mf_alt_add_4 port map (RF_PCincd, br_tgt_pl4);
U_BR_tgt_pl_displ: mf_alt_adder port map (RF_PCincd, br_addend, br_tgt_displ);
with br_opr select
br_target <= br_tgt_pl4 when b"01",
br_tgt_displ when b"10",
RF_PCincd when others;
RF_DECODE_FUNCT: process (opcode,IF_RF_ld,ctrl_word,funct_word,rimm_word,
func,shamt, a_rs,a_rd, STATUS,
RF_excp_type,RF_instruction)
variable i_wreg : std_logic;
variable i_csel : reg2;
variable i_oper : t_alu_fun := opNOP;
variable i_exception : exception_type;
variable i_trap : instr_type;
variable i_cop0_reg : reg5;
variable i_cop0_sel : reg3;
begin
i_wreg := '1';
i_exception := exNOP;
i_oper := opNOP;
i_csel := "00";
i_trap := NOP;
i_cop0_reg := b"00000";
i_cop0_sel := b"000";
case opcode is
when b"000000" => -- ALU
i_wreg := funct_word.wreg;
selB <= funct_word.selB;
i_oper := funct_word.oper;
muxC <= funct_word.muxC;
i_csel := ctrl_word.c_sel;
PCsel <= funct_word.PCsel;
i_trap := funct_word.i;
if (funct_word.trap = '1') then -- traps
case funct_word.i is
when SYSCALL => i_exception := exSYSCALL;
when BREAK => i_exception := exBREAK;
when iSLL =>
if RF_instruction = x"000000c0" then
i_exception := exEHB;
end if;
when others => i_exception := exNOP;
end case;
end if;
when b"000001" => -- register immediate
i_wreg := rimm_word.wreg;
selB <= rimm_word.selB;
muxC <= rimm_word.muxC;
i_csel := rimm_word.c_sel;
PCsel <= rimm_word.PCsel;
i_trap := rimm_word.i;
i_oper := opNOP; -- no ALU operation
if (rimm_word.trap = '1') then -- traps
i_exception := exNOP;
end if;
when b"010000" => -- COP-0
i_cop0_reg := a_rd;
i_cop0_sel := func(2 downto 0);
case a_rs is
when b"00100" => -- MTC0
i_exception := exMTC0;
when b"00000" => -- MFC0
i_exception := exMFC0;
i_wreg := '0';
when b"10000" => -- ERET
case func is
when b"000001" => i_exception := exTLBR;
when b"000010" => i_exception := exTLBWI;
when b"000110" => i_exception := exTLBWR;
when b"001000" => i_exception := exTLBP;
when b"011000" => i_exception := exERET;
when b"011111" => i_exception := exDERET;
when b"100000" => i_exception := exWAIT;
when others => i_exception := exRESV_INSTR;
end case;
when b"01011" => -- EI and DI
case func is
when b"100000" => -- EI;
i_exception := exEI;
i_wreg := '0';
when b"000000" => -- DI;
i_exception := exDI;
i_wreg := '0';
when others => i_exception := exRESV_INSTR;
end case;
when others => i_exception := exRESV_INSTR;
end case;
selB <= '0';
i_oper := opNOP;
muxC <= ctrl_word.muxC;
i_csel := ctrl_word.c_sel;
PCsel <= ctrl_word.PCsel;
when b"011100" => -- special2
i_wreg := ctrl_word.wreg;
selB <= ctrl_word.selB;
muxC <= ctrl_word.muxC;
i_csel := ctrl_word.c_sel;
PCsel <= ctrl_word.PCsel;
case func is
when b"000010" => -- MUL R[rd] <= R[rs]*R[rt]
i_oper := opMUL;
when others =>
i_oper := opNOP;
i_exception := exRESV_INSTR;
end case;
when b"011111" => -- special3
case func is
when b"100000" => -- BSHFL
i_csel := ctrl_word.c_sel;
case shamt is
when b"00010" => -- word swap bytes within halfwords
i_oper := opSWAP;
when b"10000" => -- sign-extend byte
i_oper := opSEB;
when b"11000" => -- sign-extend halfword
i_oper := opSEH;
when others =>
i_oper := opNOP;
end case;
when b"000000" => -- extract bit field
i_csel := b"01"; -- dest = rt
i_oper := opEXT;
when b"000100" => -- insert bit field
i_csel := b"01"; -- dest = rt
i_oper := opINS;
when others => i_exception := exRESV_INSTR;
end case;
i_wreg := ctrl_word.wreg;
selB <= ctrl_word.selB;
muxC <= ctrl_word.muxC;
PCsel <= ctrl_word.PCsel;
when others =>
case opcode is
when b"110000" => i_exception := exLL; -- not REALLY exceptions
when b"111000" => i_exception := exSC;
when others => null; -- i_exception := exRESV_INSTR;
end case;
i_wreg := ctrl_word.wreg;
selB <= ctrl_word.selB;
i_oper := ctrl_word.oper;
muxC <= ctrl_word.muxC;
i_csel := ctrl_word.c_sel;
PCsel <= ctrl_word.PCsel;
end case;
oper <= i_oper;
c_sel <= i_csel;
trap_instr <= i_trap;
cop0_reg <= i_cop0_reg;
cop0_sel <= i_cop0_sel;
if IF_RF_ld = '1' then -- bubble (OR flush_RF_EX)
wreg <= '1';
aVal <= '1';
wrmem <= '1';
exception <= exNOP;
else
wreg <= i_wreg;
aVal <= ctrl_word.aVal;
wrmem <= ctrl_word.wmem;
exception <= i_exception;
end if;
end process RF_DECODE_FUNCT;
-- exception_dec <= exception_type'pos(exception); -- debugging only
can_trap <= ctrl_word.excp or funct_word.excp or rimm_word.excp;
RF_DECODE_MEM_REF: process (ctrl_word)
variable i_type : reg4;
-- bit3: LWL,LWR=1, bit2: signed=1, bits10:xx,byte,half,word
begin
case ctrl_word.i is
when LB => i_type := b"0101"; -- signed, byte (sign extend)
when LH => i_type := b"0110"; -- signed, half-word
when LW | LL => i_type := b"0011"; -- word
when LBU => i_type := b"0001"; -- unsigned, byte (zero extend)
when LHU => i_type := b"0010"; -- unsigned, half-word
when SB => i_type := b"0001";
when SH => i_type := b"0010";
when SW | SC => i_type := b"0011";
when LWL => i_type := b"1011"; -- unaligned LOADS
when LWR => i_type := b"1111"; -- unaligned LOADS
when others => i_type := b"0000";
end case;
mem_t <= i_type;
end process RF_DECODE_MEM_REF;
with c_sel select -- select destination register
a_c <= a_rd when b"00", -- type-R
a_rt when b"01", -- type-I
b"11111" when b"10", -- jal
b"00000" when others;
PIPESTAGE_RF_EX: reg_RF_EX
port map (clk,rst, RF_EX_ld, selB,EX_selB, oper,EX_oper,
a_rs,EX_a_rs, a_rt,EX_a_rt, a_c,EX_a_c,
wreg,EX_wreg_pre, muxC,EX_muxC, move,EX_move,
a_rd,EX_postn, shamt,EX_shamt, aVal,EX_aVal,
wrmem,EX_wrmem, mem_t,EX_mem_t, is_load,EX_is_load,
regs_A,EX_A, regs_B,EX_B, displ32,EX_displ32,
pc_p8,EX_pc_p8);
-- EXECUTION ---------------------------------------------
EX_FORWARDING_ALU: process (EX_a_rs,EX_a_rt,EX_a_c, EX_A,EX_B,
MM_ll_sc_abort, MM_is_SC,
MM_a_c,MM_wreg,WB_a_c,WB_wreg,
MM_is_MFC0,MM_cop0_val, MM_result,WB_C)
variable i_A,i_B : reg32;
begin
FORWARD_A:
if ((MM_wreg = '0')and(MM_a_c /= b"00000")and(MM_a_c = EX_a_rs)) then
if MM_is_MFC0 then
i_A := MM_cop0_val;
elsif MM_is_SC then
i_A := x"0000000" & b"000" & not( BOOL2SL(MM_ll_sc_abort) );
else
i_A := MM_result;
end if;
elsif ((WB_wreg = '0')and(WB_a_c /= b"00000")and(WB_a_c = EX_a_rs)) then
i_A := WB_C;
else
i_A := EX_A;
end if;
alu_inp_A <= i_A;
assert TRUE report -- DEBUG
"FWD_A: alu_A="&SLV32HEX(alu_inp_A)&" alu_B="&SLV32HEX(alu_fwd_B);
FORWARD_B:
if ((MM_wreg = '0')and(MM_a_c /= b"00000")and(MM_a_c = EX_a_rt)) then
if MM_is_MFC0 then
i_B := MM_cop0_val;
elsif MM_is_SC then
i_B := x"0000000" & b"000" & not( BOOL2SL(MM_ll_sc_abort) );
else
i_B := MM_result;
end if;
elsif ((WB_wreg = '0')and(WB_a_c /= b"00000")and(WB_a_c = EX_a_rt)) then
i_B := WB_C;
else
i_B := EX_B;
end if;
alu_fwd_B <= i_B;
assert TRUE report -- DEBUG
"FWD_B: alu_A="&SLV32HEX(alu_inp_A)&" alu_B="&SLV32HEX(alu_fwd_B);
end process EX_FORWARDING_ALU;
alu_inp_B <= alu_fwd_B when (EX_selB = '0') else EX_displ32;
U_ALU: alu port map(clk,rst,
alu_inp_A, alu_inp_B, result, LO, HI, annul_twice,
alu_move_ok, EX_oper,EX_postn,EX_shamt, ovfl);
-- this adder performs address calculation so the TLB can be checked during
-- EX and thus signal an exception as early as possible
U_VIR_ADDR_ADD: mf_alt_adder port map (alu_inp_A, EX_displ32, v_addr);
U_EX_ADDR_ERR_EXCP: process(EX_mem_t,EX_aVal,EX_wrmem, v_addr)
variable i_stage_mm, i_addrError : boolean;
variable i_excp_type : exception_type;
begin
case EX_mem_t(1 downto 0) is -- xx,by,hf,wd
when b"11" =>
if ( EX_mem_t(3) = '0' and -- normal LOAD, not LWL,LWR
EX_aVal = '0' and v_addr(1 downto 0) /= b"00" ) then
if EX_wrmem = '1' then
i_excp_type := MMaddressErrorLD;
else
i_excp_type := MMaddressErrorST;
end if;
i_addrError := TRUE;
i_stage_mm := TRUE;
else
i_excp_type := exNOP;
i_addrError := FALSE;
i_stage_mm := FALSE;
end if;
when b"10" => -- LH*, SH
if EX_aVal = '0' and v_addr(0) /= '0' then
if EX_wrmem = '1' then
i_excp_type := MMaddressErrorLD;
else
i_excp_type := MMaddressErrorST;
end if;
i_addrError := TRUE;
i_stage_mm := TRUE;
else
i_excp_type := exNOP;
i_addrError := FALSE;
i_stage_mm := FALSE;
end if;
when others => -- LB*, SB
i_excp_type := exNOP;
i_addrError := FALSE;
i_stage_mm := FALSE;
end case;
mem_excp_type <= i_excp_type;
addrErr_stage_mm <= i_stage_mm;
addrError <= i_addrError;
-- assert mem_excp_type = exNOP -- DEBUG
-- report LF & "SIMULATION ERROR -- data addressing error: " &
-- integer'image(exception_type'pos(mem_excp_type)) &
-- " at address: " & SLV32HEX(v_addr)
-- severity error;
end process U_EX_ADDR_ERR_EXCP; ----------------------------------
-- uncomment this when making use of the TLB CHANGE
-- EX_addr <= phy_d_addr; -- with TLB
-- uncomment this when NOT making use of the TLB
EX_addr <= v_addr; -- without TLB
-- assert ( (phy_d_addr = v_addr) and (EX_aVal = '0') ) -- DEBUG
-- report LF&"mapping mismatch V:P "&SLV32HEX(v_addr)&":"&SLV32HEX(phy_d_addr);
EX_wreg <= EX_wreg_pre -- movz,movn, move/DO_NOT move
-- abort wr if previous exception in EX
or ( BOOL2SL(nullify) and not(MM_is_delayslot) )
-- abort wr if TLB exception in EX (nullify=1 on next cycle)
or ( BOOL2SL( tlb_exception and tlb_stage_mm ) );
EX_wrmem_cond <= EX_wrmem
or BOOL2SL(abort_ref) -- abort write if exception in MEM
or LL_SC_abort -- SC is to be killed
-- abort memWrite if exception in EX, but not in IF
or ( BOOL2SL(nullify) and
(MM_is_delayslot and not BOOL2SL(nullify_fetch)) )
or ( BOOL2SL(nullify) and not BOOL2SL(nullify_fetch) );
-- check_this
EX_aVal_cond <= EX_aVal
or BOOL2SL(abort_ref) -- abort ref if exception in MEM
or LL_SC_abort -- SC is to be killed
-- abort memWrite if exception in EX, but not in IF
or ( BOOL2SL(nullify) and
(MM_is_delayslot and not BOOL2SL(nullify_fetch)) )
or ( BOOL2SL(nullify) and not BOOL2SL(nullify_fetch) );
-- check_this
abort_ref <= (addrError or (tlb_exception and tlb_stage_mm));
busFree <= EX_aVal_cond;
-- ----------------------------------------------------------------------
PIPESTAGE_EX_MM: reg_EX_MM
port map (clk,rst, EX_MM_ld,
EX_a_rt,MM_a_rt, EX_a_c,MM_a_c, EX_wreg,MM_wreg,
EX_muxC,MM_muxC, EX_aVal_cond,MM_aVal, EX_wrmem_cond,MM_wrmem,
EX_mem_t,MM_mem_t, EX_is_load,MM_is_load,
EX_A,MM_A, alu_fwd_B,MM_B,
result,MM_result, EX_addr,MM_addr,
HI,MM_HI, LO,MM_LO,
alu_move_ok,MM_alu_move_ok, EX_move,MM_move,
EX_pc_p8,MM_pc_p8);
-- MEMORY ---------------------------------------------------------------
-- DATA_BUS_STATE_MACHINE: data-bus control
U_dmem_stalled: FFD port map (clk => phi2, rst => rst, set => '1',
D => mem_stall, Q => mm_stalled);
d_aVal <= MM_aVal; -- interface signal/port
daVal <= MM_aVal; -- internal signal
ram_stall <= not(daVal) and not(d_wait);
-- end DATA_BUS_STATE_MACHINE -------------------------------------
wr <= MM_wrmem; -- abort write if SC fails
rd_data_raw <= data_inp when (MM_wrmem = '1' and MM_aVal = '0') else
(others => 'X');
MM_MEM_CTRL_INTERFACE: process(MM_mem_t, MM_addr)
variable i_d_addr : reg2;
variable i_byte_sel : reg4;
begin
case MM_mem_t(1 downto 0) is -- xx,by,hf,wd
when b"11" =>
i_byte_sel := b"1111"; -- LW, SW, LWL, LWR
i_d_addr := b"00"; -- align reference
when b"10" =>
i_d_addr := MM_addr(1) & '0'; -- align reference
if MM_addr(1) = '0' then -- LH*, SH
i_byte_sel := b"0011";
else
i_byte_sel := b"1100";
end if;
when b"01" => -- LB*, SB
i_d_addr := MM_addr(1 downto 0);
case MM_addr(1 downto 0) is
when b"00" => i_byte_sel := b"0001";
when b"01" => i_byte_sel := b"0010";
when b"10" => i_byte_sel := b"0100";
when others => i_byte_sel := b"1000";
end case;
when others =>
i_d_addr := (others => 'X'); -- MM_addr;
i_byte_sel := b"0000";
end case;
d_addr <= MM_addr(31 downto 2) & i_d_addr;
b_sel <= i_byte_sel;
end process MM_MEM_CTRL_INTERFACE; ---------------------------------
MM_MEM_DATA_INTERFACE: process(MM_mem_t, MM_addr, rd_data_raw)
variable bytes_read : reg32;
variable i_byte : reg8;
variable i_half : reg16;
constant c_24_ones : reg24 := b"111111111111111111111111";
constant c_24_zeros : reg24 := b"000000000000000000000000";
constant c_16_ones : reg16 := b"1111111111111111";
constant c_16_zeros : reg16 := b"0000000000000000";
begin
case MM_mem_t(1 downto 0) is -- 10:xx,by,hf,wd
when b"11" =>
bytes_read := rd_data_raw;
when b"10" =>
if MM_addr(1) = '0' then -- LH*, SH
i_half := rd_data_raw(15 downto 0);
else
i_half := rd_data_raw(31 downto 16);
end if;
if MM_mem_t(2) = '1' and i_half(15) = '1' then -- mem_t(2):signed=1
bytes_read := c_16_ones & i_half;
else
bytes_read := c_16_zeros & i_half;
end if;
when b"01" => -- LB*, SB
case MM_addr(1 downto 0) is
when b"00" => i_byte := rd_data_raw(7 downto 0);
when b"01" => i_byte := rd_data_raw(15 downto 8);
when b"10" => i_byte := rd_data_raw(23 downto 16);
when others => i_byte := rd_data_raw(31 downto 24);
end case;
if MM_mem_t(2) = '1' and i_byte(7) = '1' then -- mem_t(2):signed=1
bytes_read := c_24_ones & i_byte;
else
bytes_read := c_24_zeros & i_byte;
end if;
when others =>
bytes_read := (others => 'X');
end case;
rd_data <= bytes_read;
end process MM_MEM_DATA_INTERFACE; ---------------------------------
-- forwarding for LW -> SW
MM_FORWARDING_MEM: process (MM_aVal,MM_wrmem,MM_a_rt,WB_a_c,WB_wreg,WB_C,MM_B)
variable f_m: reg2;
variable i_data : reg32;
begin
f_m := "XX";
if ( (MM_wrmem = '0') and (MM_aVal = '0') ) then
if ( (MM_a_rt = WB_a_c) and (WB_wreg = '0') and (WB_a_c /= b"00000")) then
f_m := "01"; -- forward from WB
i_data := WB_C;
else
f_m := "00"; -- not forwarding
i_data := MM_B;
end if;
else
f_m := "11"; -- not a write, (others=>'Z')
i_data := (others => 'X');
end if;
fwd_mem <= f_m; -- for debugging
data_out <= i_data;
end process MM_FORWARDING_MEM; -------------------------------
-- forwarding for LWL, LWR
MM_FWD_LWLR: process (MM_aVal,MM_wreg,MM_a_rt,WB_a_c,WB_wreg,WB_C,MM_B)
variable f_m: boolean;
variable i_data : reg32;
begin
if ( (MM_wreg = '0') and (MM_aVal = '0') and
(MM_a_rt = WB_a_c) and (WB_wreg = '0') and
(WB_a_c /= b"00000") ) then
f_m := TRUE; -- forward from WB
i_data := WB_C;
else
f_m := FALSE; -- not forwarding
i_data := MM_B;
end if;
fwd_lwlr <= f_m; -- for debugging
MM_B_data <= i_data;
end process MM_FWD_LWLR;
-- if interrupt is in J/BR delaySlot, and JR was stalled, kill instr in MM
U_NULLIFY_THRICE:
FFD port map (clk, rst, '1', nullify_MM_pre, nullify_MM_int);
MM_wreg_cond <= '1' when ( (ram_stall = '1')
or MM_addrError -- abort regWrite if excptn in MEM
or (MM_move = '1' and MM_alu_move_ok = '0')
or (nullify_MM_int = '1')
)
else MM_wreg;
-- ----------------------------------------------------------------------
PIPESTAGE_MM_WB: reg_MM_WB
port map (clk,rst, MM_WB_ld,
MM_a_c,WB_a_c, MM_wreg_cond,WB_wreg, MM_muxC,WB_muxC,
MM_A,WB_A, MM_result,WB_result, MM_HI,WB_HI,MM_LO,WB_LO,
rd_data,WB_rd_data, MM_B_data,WB_B_data,
MM_addr(1 downto 0),WB_addr2, MM_mem_t(3 downto 2),WB_mem_t,
MM_pc_p8,WB_pc_p8);
-- WRITE BACK -----------------------------------------------------------
-- merge unaligned loads LWL,LWR
mergeLOAD: process (WB_rd_data, WB_B_data, WB_addr2, WB_mem_t)
variable mem, reg, res : reg32;
begin
mem := WB_rd_data;
reg := WB_B_data;
case WB_mem_t is
when "10" => -- LWL
case WB_addr2 is
when "00" =>
res := mem( 7 downto 0) & reg(23 downto 0);
when "01" =>
res := mem(15 downto 0) & reg(15 downto 0);
when "10" =>
res := mem(23 downto 0) & reg( 7 downto 0);
when others =>
res := mem;
end case;
when "11" => -- LWR
case WB_addr2 is
when "01" =>
res := reg(31 downto 24) & mem(31 downto 8);
when "10" =>
res := reg(31 downto 16) & mem(31 downto 16);
when "11" =>
res := reg(31 downto 8) & mem(31 downto 24);
when others =>
res := mem;
end case;
when others => -- normal LOAD
res := mem;
end case;
WB_mem_data <= res;
end process mergeLOAD;
with WB_muxC select WB_C <=
WB_mem_data when b"000", -- from memory
WB_result when b"001", -- from ALU
WB_A when b"010", -- A, for jr
WB_pc_p8 when b"011", -- PC+8 for jal
WB_HI when b"100", -- MFHI
WB_LO when b"101", -- MFLO
WB_cop0_val when b"110", -- from COP0 registers
(x"0000000" & b"000" & WB_LLbit) when b"111", -- from LLbit
(others => 'X') when others; -- invalid selection
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- end of data pipeline
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- control pipeline
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- IF instruction fetch ---------------------------------------------
PIPESTAGE_EXCP_IF_RF: reg_excp_IF_RF
port map (clk, rst, excp_IF_RF_ld,
IF_excp_type,RF_excp_type, PC_abort,RF_PC_abort, PC,RF_PC);
-- RF decode & register fetch ---------------------------------------------
RF_FORWARDING_TRAPS: process (a_rs,a_rt,rimm_word,displ32,
EX_wreg,EX_a_c,MM_wreg,MM_a_c,
MM_aVal,MM_result,regs_A,regs_B,is_trap)
begin
tr_stall <= '0';
if ( (is_trap = '1') and -- forward_A:
(EX_wreg = '0') and (EX_a_c = a_rs) and (EX_a_c /= b"00000") ) then
tr_stall <= '1';
tr_fwd_A <= regs_A;
elsif ((MM_wreg = '0') and (MM_a_c = a_rs) and (MM_a_c /= b"00000")) then
if (MM_aVal = '0') then -- LW load-delay slot
if (is_trap = '1') then
tr_stall <= '1';
end if;
tr_fwd_A <= regs_A;
else -- non-LW
tr_fwd_A <= MM_result;
end if;
else
tr_fwd_A <= regs_A;
end if;
if ( (is_trap = '1') and (rimm_word.selB = '1') ) then -- from immediate
tr_fwd_B <= displ32;
elsif ( (is_trap = '1') and -- forward_B:
(EX_wreg = '0') and (EX_a_c = a_rt) and (EX_a_c /= b"00000") ) then
tr_stall <= '1';
tr_fwd_B <= regs_B;
elsif ((MM_wreg = '0') and (MM_a_c = a_rt) and (MM_a_c /= b"00000")) then
if (MM_aVal = '0') then -- LW load-delay slot
if (is_trap = '1') then
tr_stall <= '1';
end if;
tr_fwd_B <= regs_B;
else -- non-LW
tr_fwd_B <= MM_result;
end if;
else
tr_fwd_B <= regs_B;
end if;
end process RF_FORWARDING_TRAPS;
tr_signed <= '0' when ((funct_word.trap = '1' and
((funct_word.oper = trGEU)or(funct_word.oper = trLTU)))
or
(rimm_word.trap = '1' and
((rimm_word.br_t = tGEU)or(rimm_word.br_t = tLTU))))
else '1';
tr_is_equal <= '1' when (tr_fwd_A = tr_fwd_B) else '0';
U_COMP_TRAP: subtr32
port map (tr_fwd_A, tr_fwd_B, tr_result, tr_signed, open, tr_less_than);
trap_dec <= instr_type'pos(trap_instr); -- debugging only
RF_EVALUATE_TRAPS: process (trap_instr, tr_is_equal, tr_less_than)
variable i_take_trap : boolean;
begin
case trap_instr is
when TEQ | TEQI =>
i_take_trap := tr_is_equal = '1';
when TNE | TNEI =>
i_take_trap := tr_is_equal = '0';
when TLT | TLTI | TLTU | TLTIU =>
i_take_trap := tr_less_than = '1';
when TGE | TGEI | TGEU | TGEIU =>
i_take_trap := tr_less_than = '0';
when others =>
i_take_trap := FALSE;
end case;
trap_taken <= i_take_trap;
end process RF_EVALUATE_TRAPS;
-- ----------------------------------------------------------------------
PIPESTAGE_EXCP_RF_EX: reg_excp_RF_EX
port map (clk, rst, excp_RF_EX_ld,
cop0_reg,EX_cop0_reg, cop0_sel,EX_cop0_sel,
can_trap,EX_can_trap,
exception,EX_exception,
RF_is_delayslot,EX_is_delayslot,
RF_PC_abort,EX_PC_abort, RF_PC,EX_PC,
trap_taken,EX_trapped);
is_nmi <= ( (nmi = '1') and (STATUS(STATUS_ERL) = '0') );
int_req(5) <= (irq(5) or count_eq_compare);
int_req(4) <= irq(4);
int_req(3) <= irq(3);
int_req(2) <= irq(2);
int_req(1) <= irq(1);
int_req(0) <= irq(0);
interrupt <= int_req(5) or int_req(4) or int_req(3) or int_req(2) or
int_req(1) or int_req(0) or
CAUSE(CAUSE_IP1) or CAUSE(CAUSE_IP0);
is_interr <= ( (interrupt = '1') and
(STATUS(STATUS_EXL) = '0') and
(STATUS(STATUS_ERL) = '0') and
(STATUS(STATUS_IE) = '1') and
(dly_interr = '0') and
(interrupt_taken = '0') ); -- single cycle exception req
-- While returning from an exception (especially another interrupt),
-- delay the IRQ to make sure the interrupted instruction completes;
-- This is needed to ensure forward-progress: at least one instruction
-- must complete before another interrupt may be taken.
-- Also, delay the interrupt requests to avoid hazards while
-- the interrupt-enable bit is changed in the STATUS register.
-- dly_i0 <= '1' when ( (EX_exception = exERET) or -- forward progress
-- (EX_exception = exEI) or -- interrupt hazard
-- (EX_exception = exDI) or -- interrupt hazard
-- (EX_exception = exEHB) or -- interrupt hazard
-- (EX_exception = exMTC0 -- interrupt hazard
-- and EX_cop0_reg = cop0reg_STATUS) or
-- (EX_exception = exMFC0 -- interrupt hazard
-- and EX_cop0_reg = cop0reg_STATUS) ) else
-- '0';
dly_i0 <= '1' when ( EX_exception /= exNOP ) else '0';
U_DLY_INT1: FFD port map (clk, rst, '1',dly_i0, dly_i1);
U_DLY_INT2: FFD port map (clk, rst, '1',dly_i1, dly_i2);
dly_interr <= dly_i0 or dly_i1 or dly_i2;
-- check for overflow in EX, send it to MM for later processing
is_ovfl <= (EX_can_trap = b"10" and ovfl = '1');
is_SC <= (EX_exception = exSC); -- is StoreConditional? (alu_fwd)
is_mfc0 <= (EX_exception = exMFC0); -- is MFC0? (alu_fwd)
-- priority is always given to events later in the pipeline
busError_type <= exDBE when d_busErr = '0' else
exIBE when i_busErr = '0' else
exNOP;
is_busError <= (i_busErr = '0') or (d_busErr = '0');
EX_is_exception <= busError_type when is_busError else
TLB_excp_type when tlb_exception else
mem_excp_type when addrError else
IFaddressError when EX_PC_abort else
exTrap when EX_trapped else
exOvfl when is_ovfl else
exNMI when is_nmi else
exInterr when is_interr else
EX_exception;
exception_dec <= exception_type'pos(EX_is_exception); -- debugging only
-- ----------------------------------------------------------------------
PIPESTAGE_EXCP_EX_MM: reg_excp_EX_MM
port map (clk, rst, excp_EX_MM_ld,
EX_cop0_reg, MM_cop0_reg, EX_cop0_sel, MM_cop0_sel,
EX_PC,MM_PC, v_addr,MM_v_addr, nullify,MM_nullify,
addrError,MM_addrError,
addrErr_stage_mm,MM_addrErr_stage_mm,
EX_is_delayslot,MM_is_delayslot,
EX_trapped,MM_trapped,
SL2BOOL(LL_SC_abort), MM_ll_sc_abort,
tlb_exception,MM_tlb_exception,
tlb_stage_mm,MM_tlb_stage_mm,
int_req,MM_int_req,
is_SC, MM_is_SC, is_MFC0, MM_is_MFC0,
EX_is_exception, is_exception);
-- exception_dec <= exception_type'pos(is_exception); -- debugging only
-- STATUS -- pg 79 -- cop0_12 --------------------
COP0_DECODE_EXCEPTION_AND_UPDATE_STATUS:
process (MM_a_rt, is_exception, cop0_inp,
MM_cop0_reg, MM_cop0_sel,
RF_is_delayslot, EX_is_delayslot, MM_is_delayslot, WB_is_delayslot,
rom_stall,ram_stall, STATUS)
variable newSTATUS : reg32;
variable i_update,i_epc_update,i_stall : std_logic;
variable i_nullify: boolean;
variable i_update_r : reg5;
variable i_epc_source : reg3;
begin
newSTATUS := STATUS;
i_epc_update := '1';
i_epc_source := EPC_src_PC;
i_update := '0';
i_update_r := b"00000";
i_stall := '0';
i_nullify := FALSE;
exception_taken <= '0';
interrupt_taken <= '0';
ExcCode <= cop0code_NULL;
is_delayslot <= '0';
nullify_MM_pre <= '0';
newSTATUS := STATUS; -- preserve as needed
newSTATUS(STATUS_BEV) := '0'; -- interrupts at offset 0x200, not boot
newSTATUS(STATUS_CU3) := '0'; -- COP-3 absent (always)
newSTATUS(STATUS_CU2) := '0'; -- COP-2 absent (always)
newSTATUS(STATUS_CU1) := '0'; -- COP-1 absent (always)
newSTATUS(STATUS_CU0) := '1'; -- COP-0 present=1 (always)
newSTATUS(STATUS_RP) := '0'; -- reduced power (always)
case is_exception is
when exMTC0 => -- move to COP-0
i_update_r := MM_cop0_reg;
case MM_cop0_reg is
when cop0reg_STATUS =>
newSTATUS := cop0_inp;
i_update := '1';
i_stall := '0';
when cop0reg_COUNT | cop0reg_COMPARE | cop0reg_CAUSE |
cop0reg_EntryLo0 | cop0reg_EntryLo1 | cop0reg_EntryHi |
cop0reg_Index | cop0reg_Context | cop0reg_Wired =>
i_update := '1';
i_stall := '0';
when cop0reg_EPC =>
i_epc_update := '0';
i_epc_source := EPC_src_B;
i_stall := '0';
when others =>
i_stall := '0';
i_update := '0';
end case;
when exEI => -- enable interrupts
newSTATUS(STATUS_IE) := '1';
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
when exDI => -- disable interrupts
newSTATUS(STATUS_IE) := '0';
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
when exMFC0 => -- move from COP-0
i_stall := '0'; -- register selection below
when exERET => -- EXCEPTION RETURN
newSTATUS(STATUS_EXL) := '0'; -- leave exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0'; -- do not stall
i_nullify := TRUE; -- nullify instructions in IF,RF
-- when processor goes into exception-level, IRQs are ignored,
-- hence disabled
when exSYSCALL | exBREAK => -- SYSCALL, BREAK
i_stall := '0';
if is_exception = exSYSCALL then
ExcCode <= cop0code_Sys;
else
ExcCode <= cop0code_Bp;
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
newSTATUS(STATUS_UM) := '0'; -- enter kernel mode
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0'; -- do not stall
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF
exception_taken <= '1';
if MM_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM;
is_delayslot <= MM_is_delayslot;
end if;
when exTRAP =>
ExcCode <= cop0code_Tr;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
newSTATUS(STATUS_UM) := '0'; -- enter kernel mode
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
exception_taken <= '1';
if MM_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- WB_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- MM_PC
is_delayslot <= MM_is_delayslot;
end if;
when exLL => -- load linked (not a real exception)
i_update := '1';
i_update_r := cop0reg_LLaddr;
-- when exSC => null; if treated here, SC might delay an interrupt
when exRESV_INSTR => -- reserved instruction ABORT SIMULATION
assert FALSE -- invalid opcode
report LF & "invalid opcode (resv instr) at PC="& SLV32HEX(EX_PC)
severity failure;
when exOvfl => -- OVERFLOW happened one cycle earlier
newSTATUS(STATUS_EXL) := '1'; -- at exception level
exception_taken <= '1';
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
ExcCode <= cop0code_Ov;
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
if WB_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- WB_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- offending instr PC is in MM_PC
is_delayslot <= MM_is_delayslot;
end if;
when IFaddressError => -- fetch from UNALIGNED ADDRESS
newSTATUS(STATUS_EXL) := '1'; -- at exception level
exception_taken <= '1';
i_update := '1';
i_update_r := cop0reg_STATUS;
ExcCode <= cop0code_AdEL;
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
i_epc_source := EPC_src_MM; -- bad address is in EXCP_MM_PC
i_epc_update := '0';
is_delayslot <= MM_is_delayslot;
when MMaddressErrorLD | MMaddressErrorST =>
-- load/store from/to UNALIGNED ADDRESS
newSTATUS(STATUS_EXL) := '1'; -- at exception level
exception_taken <= '1';
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
if is_exception = MMaddressErrorST then
ExcCode <= cop0code_AdES;
else
ExcCode <= cop0code_AdEL;
end if;
if WB_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- WB_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- offending instr PC is in MM_PC
is_delayslot <= MM_is_delayslot;
end if;
when exEHB => -- stall processor to clear hazards
i_stall := '1';
when exTLBP | exTLBR | exTLBWI | exTLBWR => -- TLB access
i_stall := '0'; -- do not stall the processor
when exTLBrefillIF =>
ExcCode <= cop0code_TLBL;
if RF_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_EX; -- EX_PC, re-execute branch/jump
is_delayslot <= RF_is_delayslot;
elsif EX_is_delayslot = '1' then
i_epc_source := EPC_src_MM; -- MM_PC check_this
is_delayslot <= '0';
else
i_epc_source := EPC_src_RF; -- RF_PC check_this
is_delayslot <= '0';
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
exception_taken <= '1';
when exTLBrefillRD | exTLBrefillWR =>
case is_exception is
when exTLBrefillRD =>
ExcCode <= cop0code_TLBL;
when exTLBrefillWR =>
ExcCode <= cop0code_TLBS;
when others => null;
end case;
if WB_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- MM_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- EX_PC
is_delayslot <= MM_is_delayslot;
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
exception_taken <= '1';
when exTLBdblFaultIF | exTLBinvalIF =>
ExcCode <= cop0code_TLBL;
if RF_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_RF; -- RF_PC, re-execute branch/jump
is_delayslot <= RF_is_delayslot;
else
i_epc_source := EPC_src_PC; -- PC
is_delayslot <= '0';
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
when exTLBdblFaultRD | exTLBdblFaultWR |
exTLBinvalRD | exTLBinvalWR | exTLBmod =>
case is_exception is
when exTLBinvalRD | exTLBdblFaultRD =>
ExcCode <= cop0code_TLBL;
when exTLBinvalWR | exTLBdblFaultWR =>
ExcCode <= cop0code_TLBS;
when exTLBmod =>
ExcCode <= cop0code_Mod;
when others => null;
end case;
if WB_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_WB; -- MM_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
i_epc_source := EPC_src_MM; -- EX_PC
is_delayslot <= MM_is_delayslot;
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
when exIBE | exDBE => -- BUS ERROR
if is_exception = exIBE then
ExcCode <= cop0code_IBE;
else
ExcCode <= cop0code_DBE;
end if;
newSTATUS(STATUS_EXL) := '1'; -- at exception level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
exception_taken <= '1';
when exInterr => -- normal interrupt
if (rom_stall = '0') and (ram_stall = '0') then
assert TRUE report "interrupt PC="&SLV32HEX(PC) severity note;
interrupt_taken <= '1';
newSTATUS(STATUS_UM) := '0'; -- enter kernel mode
newSTATUS(STATUS_EXL) := '1'; -- at exception level
ExcCode <= cop0code_Int;
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
if MM_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_MM; -- re-execute branch/jump
is_delayslot <= MM_is_delayslot;
nullify_MM_pre <= '1'; -- if stalled, kill instrn in MM
else
i_epc_source := EPC_src_EX;
is_delayslot <= EX_is_delayslot;
nullify_MM_pre <= '0';
end if;
end if;
when exNMI => -- non maskable interrupt
-- assert false report "NMinterrupt PC="&SLV32HEX(PC) severity note;
exception_taken <= '1';
newSTATUS(STATUS_BEV) := '1'; -- locationVector at bootstrap
newSTATUS(STATUS_TS) := '0'; -- not TLBmatchesSeveral
newSTATUS(STATUS_SR) := '0'; -- not softReset
newSTATUS(STATUS_NMI) := '1'; -- non maskable interrupt
newSTATUS(STATUS_ERL) := '1'; -- at error level
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
i_epc_update := '0';
i_nullify := TRUE; -- nullify instructions in IF,RF,EX
if MM_is_delayslot = '1' then -- instr is in delay slot
i_epc_source := EPC_src_MM; -- re-execute branch/jump
is_delayslot <= MM_is_delayslot;
nullify_MM_pre <= '1'; -- if stalled, kill instrn in MM
else
i_epc_source := EPC_src_EX;
is_delayslot <= EX_is_delayslot;
nullify_MM_pre <= '0';
end if;
when others => null;
end case;
STATUSinp <= newSTATUS;
update <= i_update;
update_reg <= i_update_r;
if is_exception = exMTC0 and MM_cop0_reg = cop0reg_EPC then
epc_update <= i_epc_update;
else
epc_update <= i_epc_update OR STATUS(STATUS_EXL);
end if;
epc_source <= i_epc_source;
exception_stall <= i_stall;
nullify <= i_nullify;
end process COP0_DECODE_EXCEPTION_AND_UPDATE_STATUS;
-- Select value to be read by instruction MFC0 --------------------
COP0_READ: process (is_exception, MM_cop0_reg, MM_cop0_sel,
INDEX, RANDOM, EntryLo0, EntryLo1,
CONTEXT, PAGEMASK, WIRED, EntryHi,
COUNT, COMPARE, STATUS, CAUSE, EPC, BadVAddr)
variable i_COP0_rd : reg32;
begin
case is_exception is
when exEI | exDI => -- enable/disable interrupts
i_COP0_rd := STATUS;
when exMFC0 => -- move from COP-0
case MM_cop0_reg is
when cop0reg_Index => i_COP0_rd := INDEX;
when cop0reg_Random => i_COP0_rd := RANDOM;
when cop0reg_EntryLo0 => i_COP0_rd := EntryLo0;
when cop0reg_EntryLo1 => i_COP0_rd := EntryLo1;
when cop0reg_Context => i_COP0_rd := CONTEXT;
when cop0reg_PageMask => i_COP0_rd := PAGEMASK;
when cop0reg_Wired => i_COP0_rd := WIRED;
when cop0reg_EntryHi => i_COP0_rd := EntryHi;
when cop0reg_COUNT => i_COP0_rd := COUNT;
when cop0reg_COMPARE => i_COP0_rd := COMPARE;
when cop0reg_STATUS => i_COP0_rd := STATUS;
when cop0reg_CAUSE => i_COP0_rd := CAUSE;
when cop0reg_EPC => i_COP0_rd := EPC;
when cop0reg_BadVAddr => i_COP0_rd := BadVAddr;
when cop0reg_CONFIG =>
if MM_cop0_sel = b"000" then
i_COP0_rd := CONFIG0; -- constant
else
i_COP0_rd := CONFIG1; -- constant
end if;
when others =>
i_COP0_rd := STATUS;
end case;
when others =>
i_COP0_rd := STATUS;
end case;
MM_cop0_val <= i_COP0_rd;
end process COP0_READ;
-- Select input to PC on an exception --------------------
COP0_SEL_EPC: process (is_exception, STATUS, CAUSE, MM_trapped)
variable i_excp_PCsel : reg3;
begin
case is_exception is
when exERET => -- exception return
i_excp_PCsel := PCsel_EXC_EPC; -- PC <= EPC
when exSYSCALL | exBREAK | exRESV_INSTR | exOvfl
| IFaddressError | MMaddressErrorLD | MMaddressErrorST
| exTLBdblFaultIF | exTLBdblFaultRD | exTLBdblFaultWR
| exTLBinvalIF | exTLBinvalRD | exTLBinvalWR | exTLBmod
| exIBE | exDBE =>
i_excp_PCsel := PCsel_EXC_0180; -- PC <= exception_180
when exTRAP =>
if MM_trapped then
i_excp_PCsel := PCsel_EXC_0180; -- PC <= exception_180
else
i_excp_PCsel := PCsel_EXC_none;
end if;
when exTLBrefillIF | exTLBrefillRD | exTLBrefillWR =>
i_excp_PCsel := PCsel_EXC_0000; -- PC <= exception_0000
when exNMI => -- non maskable interrupt
i_excp_PCsel := PCsel_EXC_BFC0; -- PC <= 0xBFC0.0000
when exInterr => -- normal interrupt
if CAUSE(CAUSE_IV) = '1' then
i_excp_PCsel := PCsel_EXC_0200; -- PC <= exception_0200
else
i_excp_PCsel := PCsel_EXC_0180; -- PC <= exception_0180
end if;
-- when exNOP =>
-- i_excp_PCsel := PCsel_EXC_none; -- no exception, do nothing to PC
when others => -- should never get here
i_excp_PCsel := PCsel_EXC_none;
end case;
excp_PCsel <= i_excp_PCsel;
end process COP0_SEL_EPC;
COP0_FORWARDING: process (WB_a_c,WB_wreg,MM_a_rt,WB_C,MM_B)
variable i_B : reg32;
begin
if ((WB_wreg = '0')and(WB_a_c /= b"00000")and(WB_a_c = MM_a_rt)) then
i_B := WB_C;
else
i_B := MM_B;
end if;
cop0_inp <= i_B;
end process COP0_FORWARDING;
-- STATUS -- pg 79 -- cop0_12 --------------------
status_update <= '0' when (update = '1' and update_reg = cop0reg_STATUS and
not_stalled = '1')
else '1';
COP0_STATUS: register32 generic map (RESET_STATUS)
port map (clk, rst, status_update, STATUSinp, STATUS);
U_DLY_TLB_EXCP: FFD
port map (clk, rst, '1', BOOL2SL(tlb_exception), tlb_excp_taken);
-- CAUSE -- pg 92-- cop0_13 --------------------------
COP0_COMPUTE_CAUSE: process(rst, clk)
-- update, update_reg,
-- MM_int_req, ExcCode, cop0_inp, is_delayslot,
-- count_eq_compare,
-- interrupt_taken, exception_taken,
-- STATUS)
variable branch_delay : std_logic;
variable excp_code : reg5;
begin
if (STATUS(STATUS_EXL) = '1') then
branch_delay := CAUSE(CAUSE_BD); -- do NOT update
else
branch_delay := is_delayslot; -- may update
end if;
if ( (interrupt_taken = '1') or (exception_taken = '1') or
(tlb_excp_taken = '1') )
then
excp_code := ExcCode; -- record new exception
elsif ( (is_exception = exMFC0) and (MM_cop0_reg = cop0reg_CAUSE) ) then
excp_code := cop0code_NULL; -- clear code when sw reads CAUSE
else
excp_code := CAUSE(CAUSE_ExcCodeHi downto CAUSE_ExcCodeLo); -- hold
end if;
if rst = '0' then
CAUSE <= RESET_CAUSE;
elsif rising_edge(clk) then
if (update = '1' and update_reg = cop0reg_CAUSE) then
CAUSE <= branch_delay & -- b31, CAUSE_BD
count_eq_compare & -- b30, CAUSE_TI timer interrupt
b"00" & -- b29,28, CAUSE_CE1,CAUSE_CE0
cop0_inp(CAUSE_DC) & -- b27, disable COUNT register
'0' & -- b26, CAUSE_PCI
b"00" & -- b25,b24, nil
cop0_inp(CAUSE_IV) & -- b23, separate interrupr vector
cop0_inp(CAUSE_WP) & -- b22, watch exception
b"000000" & -- b21..b16, nil
MM_int_req(5 downto 0) & -- b15..b10, update HW IRQs
cop0_inp(CAUSE_IP1 downto CAUSE_IP0) & -- b10,b9, SW IRQs
'0' & -- b7, nil
excp_code & -- b6..b2, ExcCode
b"00"; -- b1,b0, nil
else
CAUSE <= branch_delay & -- b31, CAUSE_BD
count_eq_compare & -- b30, CAUSE_TI timer interrupt
b"00" & -- b29,b28, CAUSE_CE1,CAUSE_CE0
CAUSE(CAUSE_DC) & -- b27, disable COUNT register
'0' & -- b26, CAUSE(CAUSE_PCI)
b"00" & -- b25,b24, nil
CAUSE(CAUSE_IV) & -- b23, separate interrupr vector
CAUSE(CAUSE_WP) & -- b22, watch exception
b"000000" & -- b21..b16, nil
MM_int_req(5 downto 0) & -- b15..b10, update HW IRQs
CAUSE(CAUSE_IP1 downto CAUSE_IP0) & -- b10,b9, SW IRQs
'0' & -- b7, nil
excp_code & -- b6..b2, ExcCode
b"00"; -- b1,b0, nil
end if;
end if;
end process COP0_COMPUTE_CAUSE;
-- EPC -- pg 97 -- cop0_14 -------------------
with epc_source select EPCinp <=
PC when EPC_src_PC, -- instr fetch exception
RF_PC when EPC_src_RF, -- invalid instr exception
EX_PC when EPC_src_EX, -- interrupt, eret, overflow
MM_PC when EPC_src_MM, -- data memory exception
WB_PC when EPC_src_WB, -- overflow in a branch delay slot
MM_B when EPC_src_B, -- mtc0
(others => 'X') when others; -- invalid selection
COP0_EPC: register32 generic map (x"00000000")
port map (clk, rst, epc_update, EPCinp, EPC);
-- COUNT & COMPARE -- pg 75, 78 -----------------
compare_update <= '0' when (update = '1' and update_reg = cop0reg_COMPARE)
else '1';
COP0_COMPARE: register32 generic map(x"00000000")
port map (clk, rst, compare_update, cop0_inp, COMPARE);
count_update <= '0' when (update = '1' and update_reg = cop0reg_COUNT)
else '1';
COP0_COUNT: counter32 generic map (x"00000001")
port map (clk, rst, count_update, count_enable, cop0_inp, COUNT);
-- port map (clk, rst, count_update, PCload, cop0_inp, COUNT); -- DEBUG
compare_set <= (count_eq_compare or BOOL2SL(COUNT = COMPARE))
when compare_update = '1'
else '0';
COP0_COUNT_INTERRUPT: FFD
port map (clk, rst, '1', compare_set, count_eq_compare);
disable_count <= CAUSE(CAUSE_DC) when (CAUSE(CAUSE_DC) /= count_enable)
else count_enable; -- load new CAUSE(CAUSE_DC)
COP0_DISABLE_COUNT: FFD port map (clk,'1',rst, disable_count, count_enable);
-- BadVAddr -- pg 74 ---------------------------
U_BadVAddr_UPDATE: process(is_exception, RF_is_delayslot, RF_PC, EX_PC,
MM_v_addr)
variable i_update : std_logic;
begin
case is_exception is
when IFaddressError | exTLBrefillIF | exTLBdblFaultIF | exTLBinvalIF =>
if RF_is_delayslot = '1' then -- instr is in delay slot
BadVAddr_inp <= EX_PC;
else
BadVAddr_inp <= RF_PC;
end if;
i_update := '0';
when MMaddressErrorLD | MMaddressErrorST | exTLBrefillRD | exTLBrefillWR
| exTLBdblFaultRD | exTLBdblFaultWR | exTLBinvalRD | exTLBinvalWR
| exTLBmod =>
BadVAddr_inp <= MM_v_addr;
i_update := '0';
when others =>
BadVAddr_inp <= (others => 'X');
i_update := '1';
end case;
BadVAddr_update <= i_update;
end process U_BadVAddr_UPDATE;
COP0_BadVAddr: register32 generic map(x"00000000")
port map (clk, rst, BadVAddr_update, BadVAddr_inp, BadVAddr);
-- LLaddr & LLbit --------------------------------------------------
-- check address of SC at stage EX, in time to kill memory reference
LL_update <= '0' when (update = '1' and update_reg = cop0reg_LLAddr)
else '1';
COP0_LLaddr: register32 generic map(x"00000000") -- update at MM
port map (clk, rst, LL_update, MM_v_addr, LLaddr);
LL_SC_differ <= '0' when (v_addr = LLaddr) else '1'; -- check at EX
LL_SC_abort <= (LL_SC_differ or not(ll_sc_bit))
when (EX_exception = exSC) -- and pipe_stall = '0')
else '0';
COP0_LLbit: process(rst,clk)
begin
if rst = '0' then
ll_sc_bit <= '0';
elsif rising_edge(clk) then
case is_exception is
when exERET =>
ll_sc_bit <= '0'; -- break SC -> LL
when exLL =>
ll_sc_bit <= not LL_update; -- update only if instr is an LL
when others =>
null;
end case;
end if;
end process COP0_LLbit;
MM_llbit <= ll_sc_bit and not(BOOL2SL(MM_ll_sc_abort));
-- MMU-TLB ===============================================================
-- assert false -- true -- DEBUG
-- report "pgSz " & integer'image(PAGE_SZ_BITS) &
-- " va-1 "& integer'image(VABITS-1) &
-- " pg+1 "& integer'image(PAGE_SZ_BITS+1) &
-- " add " & integer'image(VABITS-1 - PAGE_SZ_BITS+1) &
-- " lef "&integer'image( PC(VABITS-1 downto PAGE_SZ_BITS+1)'left)&
-- " rig "&integer'image(PC(VABITS-1 downto PAGE_SZ_BITS+1)'right);
-- MMU Index -- cop0_0 -------------------------
index_update <= '0' when (update = '1' and update_reg = cop0reg_Index)
else not(tlb_probe);
hit_mm_bit <= '0' when (hit_mm = TRUE) else '1';
with hit_mm_adr select tlb_adr_mm <= "000" when 0,
"001" when 1,
"010" when 2,
"011" when 3,
"100" when 4,
"101" when 5,
"110" when 6,
"111" when 7,
"XXX" when others;
index_inp <= hit_mm_bit & MMU_IDX_0s & tlb_adr_mm when tlb_probe = '1' else
hit_mm_bit & MMU_IDX_0s & cop0_inp(MMU_CAPACITY_BITS-1 downto 0);
MMU_Index: register32 generic map(x"00000000")
port map (clk, rst, index_update, index_inp, INDEX);
-- MMU Wired -- pg 72 -- cop0_6 ----------------
wired_update <= '0' when (update = '1' and update_reg = cop0reg_Wired)
else '1';
wired_inp <= '0' & MMU_IDX_0s & cop0_inp(MMU_CAPACITY_BITS-1 downto 0);
MMU_Wired: register32 generic map(MMU_WIRED_INIT)
port map (clk, rst, wired_update, wired_inp, WIRED);
-- MMU Random -- cop0_1 ------------------------
MMU_Random: process(clk, rst, WIRED, wired_update)
variable count : integer range -1 to MMU_CAPACITY-1 := MMU_CAPACITY-1;
begin
if rst = '0' then
count := MMU_CAPACITY - 1;
elsif rising_edge(clk) then
count := count - 1;
if count = to_integer(unsigned(WIRED))-1 or wired_update = '0' then
count := MMU_CAPACITY - 1;
end if;
end if;
RANDOM <= std_logic_vector(to_signed(count, 32));
end process MMU_Random;
-- MMU EntryLo0 -- pg 63 -- cop0_2 ------------
entryLo0_update <= '0' when (update = '1' and update_reg = cop0reg_EntryLo0)
else not(tlb_read);
entryLo0_inp <= cop0_inp when tlb_read = '0' else tlb_entryLo0;
MMU_EntryLo0: register32 generic map(x"00000000")
port map (clk, rst, entryLo0_update, entryLo0_inp, EntryLo0);
-- MMU EntryLo1 -- pg 63 -- cop0_3 ------------
entryLo1_update <= '0' when (update = '1' and update_reg = cop0reg_EntryLo1)
else not(tlb_read);
entryLo1_inp <= cop0_inp when tlb_read = '0' else tlb_entryLo1;
MMU_EntryLo1: register32 generic map(x"00000000")
port map (clk, rst, entryLo1_update, entryLo1_inp, EntryLo1);
-- MMU Context -- pg 67 -- cop0_4 ------------
context_upd_pte <= '0' when (update = '1' and update_reg = cop0reg_Context)
else '1';
--
-- these registers are non-compliant so the Page Table can be set
-- at low addresses
--
-- MMU_ContextPTE: registerN generic map(9, ContextPTE_init)
-- port map (clk, rst, context_upd_pte,
-- cop0_inp(31 downto 23), Context(31 downto 23));
MMU_ContextPTE: registerN generic map(16, b"0000000000000000")
port map (clk, rst, context_upd_pte,
cop0_inp(31 downto 16), Context(31 downto 16));
context_upd_bad <= '0' when MM_tlb_exception else '1';
-- MMU_ContextBAD: registerN generic map(19, b"0000000000000000000")
-- port map (clk, rst, context_upd_bad, tlb_context_inp, Context(22 downto 4));
MMU_ContextBAD: registerN generic map(12, b"000000000000")
port map (clk, rst, context_upd_bad,
tlb_excp_VA(VA_HI_BIT-7 downto VA_LO_BIT), Context(15 downto 4));
Context(3 downto 0) <= b"0000";
-- MMU Pagemask -- pg 68 -- cop0_5 -----------
-- page size is fixed = 4k, thus PageMask is not register
-- pageMask_update <= '0' when (update='1' and update_reg=cop0reg_PageMask)
-- else '1';
-- pageMask_inp <= cop0_inp when tlb_read = '0' else tlb_pageMask_mm;
-- MMU_PageMask: register32 generic map(x"00000000")
-- port map (clk, rst, pageMask_update, pageMask_inp, PageMask);
PageMask <= mmu_PageMask;
-- MMU EntryHi -- pg 76 -- cop0_10 -----------
-- EntryHi holds the ASID of the current process, to check for a match
entryHi_update <= '0' when ( (update = '1' and update_reg = cop0reg_EntryHi)
or ( MM_tlb_exception ) )
else not(tlb_read);
entryHi_inp <= tlb_excp_VA & EHI_ZEROS & EntryHi(EHI_G_BIT) & EntryHi(EHI_ASIDHI_BIT downto EHI_ASIDLO_BIT) when MM_tlb_exception else
cop0_inp when tlb_read = '0' else
tlb_entryhi;
MMU_EntryHi: register32 generic map(x"00000000")
port map (clk, rst, entryHi_update, entryHi_inp, EntryHi);
-- == MMU ===============================================================
-- -- pg 41 ----------------------------------
MMU_exceptions: process(iaVal, EX_wrmem, EX_aVal, hit_mm, hit_pc,
hit_mm_v, hit_mm_d, hit_pc_v, STATUS, tlb_ex_2)
variable i_stage_mm, i_exception, i_miss_mm, i_miss_pc : boolean;
variable i_excp_type : exception_type;
begin
i_miss_pc := not(hit_pc) and (iAval = '0');
i_miss_mm := not(hit_mm) and (EX_aval = '0');
-- check first for events later in the pipeline: LOADS and STORES
if i_miss_mm then
if EX_wrmem = '0' then
if STATUS(STATUS_EXL) = '1' then
i_excp_type := exTLBdblFaultWR;
else
i_excp_type := exTLBrefillWR;
end if;
else
if STATUS(STATUS_EXL) = '1' then
i_excp_type := exTLBdblFaultRD;
else
i_excp_type := exTLBrefillRD;
end if;
end if;
i_stage_mm := TRUE;
i_exception := TRUE;
elsif (i_miss_pc and FALSE) then -- only MM exceptions with TLB
if STATUS(STATUS_EXL) = '1' then
i_excp_type := exTLBdblFaultIF;
else
i_excp_type := exTLBrefillIF;
end if;
i_exception := TRUE;
i_stage_mm := FALSE;
elsif hit_mm and EX_aVal = '0' then
if hit_mm_v = '0' then -- check for TLBinvalid
if EX_wrmem = '0' then
i_excp_type := exTLBinvalWR;
else
i_excp_type := exTLBinvalRD;
end if;
i_exception := TRUE;
elsif (EX_wrmem = '0' and hit_mm_d = '0') then -- check for TLBmodified
i_excp_type := exTLBmod;
i_exception := TRUE;
else
i_excp_type := exNOP;
i_exception := FALSE;
end if;
i_stage_mm := TRUE;
elsif (hit_pc and hit_pc_v = '0' and iaVal = '0' and FALSE) then -- TLBinvalid IF?
i_excp_type := exTLBinvalIF;
i_stage_mm := FALSE;
i_exception := TRUE;
else
i_excp_type := exNOP;
i_stage_mm := FALSE;
i_exception := FALSE;
end if;
-- uncomment when making use of the TLB
-- TLB_excp_type <= i_excp_type;
-- tlb_stage_MM <= i_stage_mm;
-- tlb_exception <= i_exception and not(SL2BOOL(tlb_ex_2));
-- uncomment when NOT making use of the TLB
TLB_excp_type <= exNOP;
tlb_stage_MM <= FALSE;
tlb_exception <= FALSE;
end process MMU_exceptions; -- -----------------------------------------
-- catch only first exception, if there are two in consecutive cycles
U_TLB_EXCP_ONCE: FFD port map (clk, rst, '1',
BOOL2SL(tlb_exception), tlb_ex_2);
TLB_excp_num <= exception_type'pos(TLB_excp_type); -- for debugging only
-- MMU TLB TAG-DATA array -- pg 17 ------------------------------------
-- TLB_tag: 31..13 = VPN, 12..9 = 0, 8 = G, 7..0 = ASID
-- TLB_dat: 29..6 = PPN, 5..3 = C, 2 = D, 1 = V, 0 = G
MMU_CONTROL: process(is_exception, INDEX, RANDOM)
variable i_tlb_adr : integer range MMU_CAPACITY-1 downto 0;
begin
tlb_tag0_updt <= '1';
tlb_tag1_updt <= '1';
tlb_tag2_updt <= '1';
tlb_tag3_updt <= '1';
tlb_tag4_updt <= '1';
tlb_tag5_updt <= '1';
tlb_tag6_updt <= '1';
tlb_tag7_updt <= '1';
tlb_dat0_updt <= '1';
tlb_dat1_updt <= '1';
tlb_dat2_updt <= '1';
tlb_dat3_updt <= '1';
tlb_dat4_updt <= '1';
tlb_dat5_updt <= '1';
tlb_dat6_updt <= '1';
tlb_dat7_updt <= '1';
case is_exception is
when exTLBP =>
tlb_probe <= '1';
tlb_read <= '0';
i_tlb_adr := 0;
when exTLBR =>
tlb_probe <= '0';
tlb_read <= '1';
i_tlb_adr := to_integer(unsigned(INDEX(MMU_CAPACITY-1 downto 0)));
when exTLBWI | exTLBWR =>
tlb_probe <= '0';
tlb_read <= '0';
if is_exception = exTLBWI then
i_tlb_adr := to_integer(unsigned(INDEX(MMU_CAPACITY-1 downto 0)));
else
i_tlb_adr := to_integer(unsigned(RANDOM));
end if;
case i_tlb_adr is
when 0 => tlb_tag0_updt <= '0'; tlb_dat0_updt <= '0';
when 1 => tlb_tag1_updt <= '0'; tlb_dat1_updt <= '0';
when 2 => tlb_tag2_updt <= '0'; tlb_dat2_updt <= '0';
when 3 => tlb_tag3_updt <= '0'; tlb_dat3_updt <= '0';
when 4 => tlb_tag4_updt <= '0'; tlb_dat4_updt <= '0';
when 5 => tlb_tag5_updt <= '0'; tlb_dat5_updt <= '0';
when 6 => tlb_tag6_updt <= '0'; tlb_dat6_updt <= '0';
when 7 => tlb_tag7_updt <= '0'; tlb_dat7_updt <= '0';
when others => null;
end case;
when others =>
tlb_probe <= '0';
tlb_read <= '0';
i_tlb_adr := 0;
end case;
tlb_adr <= i_tlb_adr;
end process MMU_CONTROL; ------------------------------------------------
with tlb_adr select
e_hi <= tlb_tag0 when 0,
tlb_tag1 when 1,
tlb_tag2 when 2,
tlb_tag3 when 3,
tlb_tag4 when 4,
tlb_tag5 when 5,
tlb_tag6 when 6,
tlb_tag7 when others;
with tlb_adr select
e_lo0 <= tlb_dat0_0 when 0,
tlb_dat1_0 when 1,
tlb_dat2_0 when 2,
tlb_dat3_0 when 3,
tlb_dat4_0 when 4,
tlb_dat5_0 when 5,
tlb_dat6_0 when 6,
tlb_dat7_0 when others;
with tlb_adr select
e_lo1 <= tlb_dat0_1 when 0,
tlb_dat1_1 when 1,
tlb_dat2_1 when 2,
tlb_dat3_1 when 3,
tlb_dat4_1 when 4,
tlb_dat5_1 when 5,
tlb_dat6_1 when 6,
tlb_dat7_1 when others;
-- assert false
-- report "e_hi="&SLV32HEX(e_hi)&" adr="&natural'image(tlb_adr);--DEBUG
-- tlb_entryhi(EHI_AHI_BIT downto EHI_ALO_BIT)
tlb_entryhi(31 downto PAGE_SZ_BITS + 1)
<= e_hi(TAG_AHI_BIT downto TAG_ALO_BIT);
tlb_entryhi(PAGE_SZ_BITS downto EHI_ASIDHI_BIT+1) <= (others => '0');
tlb_entryhi(EHI_ASIDHI_BIT downto EHI_ASIDLO_BIT)
<= e_hi(TAG_ASIDHI_BIT downto TAG_ASIDLO_BIT);
tlb_entryLo0(31 downto ELO_AHI_BIT+1) <= (others => '0');
tlb_entryLo0(ELO_AHI_BIT downto ELO_ALO_BIT)
<= e_lo0(DAT_AHI_BIT downto DAT_ALO_BIT);
tlb_entryLo0(ELO_CHI_BIT downto ELO_CLO_BIT)
<= e_lo0(DAT_CHI_BIT downto DAT_CLO_BIT);
tlb_entryLo0(ELO_D_BIT) <= e_lo0(DAT_D_BIT);
tlb_entryLo0(ELO_V_BIT) <= e_lo0(DAT_V_BIT);
tlb_entryLo0(ELO_G_BIT) <= e_lo0(DAT_G_BIT);
tlb_entryLo1(31 downto ELO_AHI_BIT+1) <= (others => '0');
tlb_entryLo1(ELO_AHI_BIT downto ELO_ALO_BIT)
<= e_lo1(DAT_AHI_BIT downto DAT_ALO_BIT);
tlb_entryLo1(ELO_CHI_BIT downto ELO_CLO_BIT)
<= e_lo1(DAT_CHI_BIT downto DAT_CLO_BIT);
tlb_entryLo1(ELO_D_BIT) <= e_lo1(DAT_D_BIT);
tlb_entryLo1(ELO_V_BIT) <= e_lo1(DAT_V_BIT);
tlb_entryLo1(ELO_G_BIT) <= e_lo1(DAT_G_BIT);
e_hi_inp <= EntryHi(EHI_AHI_BIT downto EHI_ALO_BIT) & EHI_ZEROS &
(EntryLo0(ELO_G_BIT) and EntryLo1(ELO_G_BIT)) &
EntryHi(EHI_ASIDHI_BIT downto EHI_ASIDLO_BIT); -- pg64
tlb_tag_inp <= e_hi_inp;
tlb_dat0_inp <= EntryLo0(ELO_AHI_BIT downto ELO_G_BIT);
tlb_dat1_inp <= EntryLo1(ELO_AHI_BIT downto ELO_G_BIT);
-- MMU TLB TAG+DATA array -------------------------
mm <= entryHi(EHI_AHI_BIT downto EHI_ALO_BIT) when tlb_probe = '1' else
v_addr(VA_HI_BIT downto VA_LO_BIT);
tlb_excp_VA <= MM_v_addr(VA_HI_BIT downto VA_LO_BIT) when MM_tlb_stage_mm else
PC(VA_HI_BIT downto VA_LO_BIT);
-- TLB entry 0 -- initialized to 1st,2nd pages of ROM
-- this mapping must be pinned down at all times (Wired >= 2, see next entry)
MMU_TAG0: register32 generic map(MMU_ini_tag_ROM0)
port map (clk, rst, tlb_tag0_updt, tlb_tag_inp, tlb_tag0);
MMU_DAT0_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM0)
port map (clk, rst, tlb_dat0_updt, tlb_dat0_inp, tlb_dat0_0); -- d=1,v=1,g=1
MMU_DAT0_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM1)
port map (clk, rst, tlb_dat0_updt, tlb_dat1_inp, tlb_dat0_1); -- d=1,v=1,g=1
hit0_pc <= TRUE when (tlb_tag0(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag0(TAG_G_BIT) = '1') OR
tlb_tag0(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit0_mm <= TRUE when (tlb_tag0(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag0(TAG_G_BIT) = '1') OR
tlb_tag0(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 1 -- initialized to page with I/O devices
-- this mapping must be pinned down at all times (Wired >= 2)
MMU_TAG1: register32 generic map(MMU_ini_tag_IO)
port map (clk, rst, tlb_tag1_updt, tlb_tag_inp, tlb_tag1);
MMU_DAT1_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_IO0) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat1_updt, tlb_dat0_inp, tlb_dat1_0);
MMU_DAT1_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_IO1) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat1_updt, tlb_dat1_inp, tlb_dat1_1);
hit1_pc <= TRUE when (tlb_tag1(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag1(TAG_G_BIT) = '1') OR
tlb_tag1(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit1_mm <= TRUE when (tlb_tag1(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag1(TAG_G_BIT) = '1') OR
tlb_tag1(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 2 -- initialized to 3rd,4th pages of ROM
MMU_TAG2: register32 generic map(MMU_ini_tag_ROM2)
port map (clk, rst, tlb_tag2_updt, tlb_tag_inp, tlb_tag2);
MMU_DAT2_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM2) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat2_updt, tlb_dat0_inp, tlb_dat2_0);
MMU_DAT2_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM3) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat2_updt, tlb_dat1_inp, tlb_dat2_1);
hit2_pc <= TRUE when (tlb_tag2(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag2(TAG_G_BIT) = '1') OR
tlb_tag2(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit2_mm <= TRUE when (tlb_tag2(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag2(TAG_G_BIT) = '1') OR
tlb_tag2(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 3 -- initialized to 5th,6th pages of ROM
MMU_TAG3: register32 generic map(MMU_ini_tag_ROM4)
port map (clk, rst, tlb_tag3_updt, tlb_tag_inp, tlb_tag3);
MMU_DAT3_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM5) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat3_updt, tlb_dat0_inp, tlb_dat3_0);
MMU_DAT3_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_ROM6) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat3_updt, tlb_dat1_inp, tlb_dat3_1);
hit3_pc <= TRUE when (tlb_tag3(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag3(TAG_G_BIT) = '1') OR
tlb_tag3(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit3_mm <= TRUE when (tlb_tag3(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag3(TAG_G_BIT) = '1') OR
tlb_tag3(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 4 -- initialized to 1st,2nd pages of RAM
MMU_TAG4: register32 generic map(MMU_ini_tag_RAM0)
port map (clk, rst, tlb_tag4_updt, tlb_tag_inp, tlb_tag4);
MMU_DAT4_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM0) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat4_updt, tlb_dat0_inp, tlb_dat4_0);
MMU_DAT4_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM1) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat4_updt, tlb_dat1_inp, tlb_dat4_1);
hit4_pc <= TRUE when (tlb_tag4(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag4(TAG_G_BIT) = '1') OR
tlb_tag4(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit4_mm <= TRUE when (tlb_tag4(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag4(TAG_G_BIT) = '1') OR
tlb_tag4(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 5 -- initialized to 3rd,4th pages of RAM
MMU_TAG5: register32 generic map(MMU_ini_tag_RAM2)
port map (clk, rst, tlb_tag5_updt, tlb_tag_inp, tlb_tag5);
MMU_DAT5_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM2) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat5_updt, tlb_dat0_inp, tlb_dat5_0);
MMU_DAT5_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM3) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat5_updt, tlb_dat1_inp, tlb_dat5_1);
hit5_pc <= TRUE when (tlb_tag5(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag5(TAG_G_BIT) = '1') OR
tlb_tag5(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit5_mm <= TRUE when (tlb_tag5(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag5(TAG_G_BIT) = '1') OR
tlb_tag5(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 6 -- initialized to RAM 5th, 6th (1st,2nd pages of SDRAM)
MMU_TAG6: register32 generic map(MMU_ini_tag_RAM4)
port map (clk, rst, tlb_tag6_updt, tlb_tag_inp, tlb_tag6);
MMU_DAT6_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM4) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat6_updt, tlb_dat0_inp, tlb_dat6_0);
MMU_DAT6_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM5) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat6_updt, tlb_dat1_inp, tlb_dat6_1);
hit6_pc <= TRUE when (tlb_tag6(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag6(TAG_G_BIT) = '1') OR
tlb_tag6(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit6_mm <= TRUE when (tlb_tag6(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag6(TAG_G_BIT) = '1') OR
tlb_tag6(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- TLB entry 7 -- initialized to 7th,8th pages of RAM = stack
MMU_TAG7: register32 generic map(MMU_ini_tag_RAM6)
port map (clk, rst, tlb_tag7_updt, tlb_tag_inp, tlb_tag7);
MMU_DAT7_0: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM6) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat7_updt, tlb_dat0_inp, tlb_dat7_0);
MMU_DAT7_1: registerN generic map(DAT_REG_BITS, MMU_ini_dat_RAM7) -- d=1,v=1,g=1
port map (clk, rst, tlb_dat7_updt, tlb_dat1_inp, tlb_dat7_1);
hit7_pc <= TRUE when (tlb_tag7(VA_HI_BIT downto VA_LO_BIT) = PC(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag7(TAG_G_BIT) = '1') OR
tlb_tag7(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
hit7_mm <= TRUE when (tlb_tag7(VA_HI_BIT downto VA_LO_BIT) = mm(VA_HI_BIT downto VA_LO_BIT)
and ( (tlb_tag7(TAG_G_BIT) = '1') OR
tlb_tag7(ASID_HI_BIT downto 0) = EntryHi(ASID_HI_BIT downto 0) ) )
else FALSE;
-- end of TLB TAG+DATA ARRAY ----------------------------------------
-- select mapping for IF --------------------------------------------
tlb_a2_pc <= 4 when (hit4_pc or hit5_pc or hit6_pc or hit7_pc) else 0;
tlb_a1_pc <= 2 when (hit2_pc or hit3_pc or hit6_pc or hit7_pc) else 0;
tlb_a0_pc <= 1 when (hit1_pc or hit3_pc or hit5_pc or hit7_pc) else 0;
hit_pc <= hit0_pc or hit1_pc or hit2_pc or hit3_pc or
hit4_pc or hit5_pc or hit6_pc or hit7_pc;
hit_pc_adr <= (tlb_a2_pc + tlb_a1_pc + tlb_a0_pc);
with hit_pc_adr select
tlb_ppn_pc0 <= tlb_dat0_0 when 0,
tlb_dat1_0 when 1,
tlb_dat2_0 when 2,
tlb_dat3_0 when 3,
tlb_dat4_0 when 4,
tlb_dat5_0 when 5,
tlb_dat6_0 when 6,
tlb_dat7_0 when others;
with hit_pc_adr select
tlb_ppn_pc1 <= tlb_dat0_1 when 0,
tlb_dat1_1 when 1,
tlb_dat2_1 when 2,
tlb_dat3_1 when 3,
tlb_dat4_1 when 4,
tlb_dat5_1 when 5,
tlb_dat6_1 when 6,
tlb_dat7_1 when others;
tlb_ppn_pc <= tlb_ppn_pc0(DAT_AHI_BIT downto DAT_ALO_BIT)
when PC(PAGE_SZ_BITS) = '0'
else tlb_ppn_pc1(DAT_AHI_BIT downto DAT_ALO_BIT);
hit_pc_v <= tlb_ppn_pc0(DAT_V_BIT) when PC(PAGE_SZ_BITS) = '0' else
tlb_ppn_pc1(DAT_V_BIT);
phy_i_addr <= tlb_ppn_pc(PPN_BITS-1 downto 0) & PC(PAGE_SZ_BITS-1 downto 0);
-- select mapping for MM --------------------------------------------
tlb_a2_mm <= 4 when (hit4_mm or hit5_mm or hit6_mm or hit7_mm) else 0;
tlb_a1_mm <= 2 when (hit2_mm or hit3_mm or hit6_mm or hit7_mm) else 0;
tlb_a0_mm <= 1 when (hit1_mm or hit3_mm or hit5_mm or hit7_mm) else 0;
hit_mm <= (hit0_mm or hit1_mm or hit2_mm or hit3_mm or
hit4_mm or hit5_mm or hit6_mm or hit7_mm);
-- and EX_mem_t /= b"0000"; -- hit AND is load or store
hit_mm_adr <= (tlb_a2_mm + tlb_a1_mm + tlb_a0_mm);
with hit_mm_adr select
tlb_ppn_mm0 <= tlb_dat0_0 when 0,
tlb_dat1_0 when 1,
tlb_dat2_0 when 2,
tlb_dat3_0 when 3,
tlb_dat4_0 when 4,
tlb_dat5_0 when 5,
tlb_dat6_0 when 6,
tlb_dat7_0 when others;
with hit_mm_adr select
tlb_ppn_mm1 <= tlb_dat0_1 when 0,
tlb_dat1_1 when 1,
tlb_dat2_1 when 2,
tlb_dat3_1 when 3,
tlb_dat4_1 when 4,
tlb_dat5_1 when 5,
tlb_dat6_1 when 6,
tlb_dat7_1 when others;
tlb_ppn_mm <= tlb_ppn_mm0(DAT_AHI_BIT downto DAT_ALO_BIT) when v_addr(PAGE_SZ_BITS) = '0' else
tlb_ppn_mm1(DAT_AHI_BIT downto DAT_ALO_BIT);
hit_mm_v <= tlb_ppn_mm0(DAT_V_BIT) when v_addr(PAGE_SZ_BITS) = '0' else
tlb_ppn_mm1(DAT_V_BIT);
hit_mm_d <= tlb_ppn_mm0(DAT_D_BIT) when v_addr(PAGE_SZ_BITS) = '0' else
tlb_ppn_mm1(DAT_D_BIT);
phy_d_addr <= tlb_ppn_mm(PPN_BITS-1 downto 0) & v_addr(PAGE_SZ_BITS-1 downto 0);
-- MMU-TLB == end =======================================================
-- ----------------------------------------------------------------------
PIPESTAGE_EXCP_MM_WB: reg_excp_MM_WB
port map (clk, rst, excp_MM_WB_ld,
MM_PC,WB_PC, MM_LLbit,WB_LLbit,
MM_is_delayslot,WB_is_delayslot,
MM_cop0_val,WB_cop0_val);
-- WB is shared with datapath -------------------------------------------
-- nothing to do here
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- end of control pipeline
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
end rtl;
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
rcls/sdr
|
vhdl/phasedetect.vhd
|
1
|
7140
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity phasedetect is
port(xx_in : in signed36; -- overkill, could have reduced to 18 bits by now.
yy_in : in signed36;
in_last : in std_logic;
phase : out unsigned18;
out_strobe : out std_logic;
out_last : out std_logic;
phasor_last : in unsigned18;
clk : in std_logic);
end phasedetect;
-- The main phase detect uses a pipeline, 16 iterations, main usage is
-- (iterations 1 to 15):
-- stage1: yy_div = yy right-shifted (by 2n).
-- stage2: trial xx' = xx + yy_div, yy' = yy - xx
-- stage3: commit, if yy' has not underflown, update angle.
-- We want to reuse the first time through the pipeline:
-- shift=0. If no underflow, then swap xx and yy.
-- We load every 20 (?) cycles,
-- and ship out 60 cycles later.
-- The phase detection is bypassed when out_last is asserted; we take
-- phasor_last instead.
architecture behavioural of phasedetect is
constant width : integer := 20;
subtype xunsigned is unsigned(width - 1 downto 0);
subtype yunsigned is unsigned(width downto 0);
signal shift : boolean;
signal x_shift, y_shift : unsigned36;
signal shift_last : std_logic;
signal xx1 : xunsigned; -- Real component.
signal yy1 : yunsigned; -- Imaginary component.
signal last1 : std_logic;
signal angle1 : unsigned18; -- Accumulated angle.
signal positive1 : boolean; -- Positive adjustments to angle.
signal xx2 : xunsigned;
signal yy2 : yunsigned;
signal yy2_shifted : yunsigned;
signal angle2 : unsigned18;
signal positive2 : boolean;
signal load2 : boolean;
signal last2 : std_logic;
signal xx3 : xunsigned;
signal yy3 : yunsigned;
signal xx3_trial : xunsigned;
signal yy3_trial : yunsigned;
signal angle3 : unsigned18;
signal angle3_update : unsigned16;
signal positive3 : boolean;
signal start3 : boolean;
signal last3 : std_logic;
signal count : integer range 0 to 19;
type stage_t is array(0 to 19) of integer range 0 to 19;
-- For pipeline stage 1, map the cycle counter to the iteration of the
-- calculation.
constant iteration1 : stage_t :=
(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
-- Iteration number for pipeline stage 2.
constant iteration2 : stage_t :=
(13, 14, 15, 16, 17, 18, 19, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12);
-- Iteration number for pipeline stage 3.
constant iteration3 : stage_t :=
(6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 0, 1, 2, 3, 4, 5);
-- Angle updates. Exhaustive testing indicates that the odd first value is
-- best.
type angles_t is array(0 to 19) of unsigned16;
constant angle_update : angles_t :=
(x"fffe", x"4b90", x"27ed", x"1444",
x"0a2c", x"0517", x"028c", x"0146",
x"00a3", x"0051", x"0029", x"0014",
x"000a", x"0005", x"0003", x"0001",
x"0000", x"0000", x"0000", x"0000");
begin
process
begin
wait until rising_edge(clk);
-- Preprocess each sample for 20 cycles, left shifting as much as possible.
-- This reduces the precision required in the main calculations.
if shift then
if load2 then
x_shift <= unsigned(xx_in);
y_shift <= unsigned(yy_in);
shift_last <= in_last;
else
x_shift <= x_shift sll 1;
y_shift <= y_shift sll 1;
end if;
end if;
if count = 19 then
shift <= true; -- Same cycle as load2.
elsif load2 then
shift <= xx_in(35) = xx_in(34) and yy_in(35) = yy_in(34);
else
shift <= shift and
x_shift(34) = x_shift(33) and y_shift(34) = y_shift(33);
end if;
if count >= 13 then
count <= count - 13;
else
count <= count + 7;
end if;
start3 <= (count = 7);
-- The default flow is just to cycle things around; override later if
-- need be.
xx2 <= xx1;
yy2 <= yy1;
angle2 <= angle1;
positive2 <= positive1;
last2 <= last1;
xx3 <= xx2;
-- Include left shift. If this loses a bit, then the trial will succeed
-- anyway, and get us back.
yy3 <= yy2 sll 1;
angle3 <= angle2;
positive3 <= positive2;
last3 <= last2;
xx1 <= xx3;
yy1 <= yy3;
angle1 <= angle3;
positive1 <= positive3;
last1 <= last3;
-- First pipeline stage is the right shift. Note that for the start
-- iteration, the high bit of yy is still zero, so the high bit of
-- yy_shifted will always be zero.
yy2_shifted <= yy1 srl (2 * (count mod 16));
load2 <= (count = 19);
-- Second pipeline stage is the trial operation. It also handles the
-- loading of data into the pipeline.
xx3_trial <= xx2 + yy2_shifted(width - 1 downto 0);
-- Note that yy is at most twice the 36 bit xx, so if the arithmetic does
-- not overflow, then the result of the subtract will fit in 36 bits.
-- Except for round-0 (where we normalise to the first octant). In that
-- case everything is 36 bits.
yy3_trial <= yy2 - ('0' & xx2);
angle3_update <= angle_update(iteration2(count));
if load2 then
last3 <= shift_last;
yy3_trial(width) <= '1'; -- Make sure we don't adjust on next cycle.
-- 'not' is cheaper than proper true negation. And given our
-- round-towards-negative behaviour, more accurate.
if x_shift(35) = '0' then
xx3 <= x_shift(35 downto 36 - width);
else
xx3 <= not x_shift(35 downto 36 - width);
end if;
if y_shift(35) = '0' then
yy3 <= '0' & y_shift(35 downto 36 - width);
else
yy3 <= '0' & not y_shift(35 downto 36 - width);
end if;
positive3 <= (x_shift(35) xor y_shift(35)) = '1';
-- Our convention is that angle zero covers the first sliver of the
-- first quadrant etc., so bias the start angle just into the
-- appropriate quadrant. Yes the 0=>1 looks like a step too far,
-- but after exhaustive testing, it gives better results, presumably
-- because of the granularity of the result.
angle3 <= (17 => y_shift(35), 0 => '1',
others => x_shift(35) xor y_shift(35));
if last2 = '1' then
phase <= phasor_last;
else
phase <= angle2; -- ship out previous result.
end if;
out_last <= last2;
end if;
out_strobe <= b2s(load2);
-- Third pipeline stage is commitment.
if yy3_trial(width) = '0' then
if not start3 then
xx1 <= xx3_trial;
-- yy got left shifted at the previous stage, but yy_trial did not.
-- so take that into account.
yy1 <= yy3_trial sll 1;
else
-- No overflow, yy is bigger than xx, so swap things over. Remember
-- that yy got left shifted, so take that into account in the swap.
xx1 <= yy3(width downto 1);
yy1 <= xx3 & '0';
positive1 <= not positive3;
end if;
if positive3 then
angle1 <= angle3 + ("00" & angle3_update);
else
angle1 <= angle3 - ("00" & angle3_update);
end if;
end if;
end process;
end behavioural;
|
gpl-3.0
|
jc38x/X38-02FO16
|
benchmarks/VHDL_Generado_desde_C++/inputs-4bits_outputs5bits/5-EWF/metaheurísticas/ewf_nsga2.vhd
|
1
|
2973
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:30:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_nsga2_entity;
ARCHITECTURE ewf_nsga2_description OF ewf_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register2 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register1 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register4 * 10;
WHEN "00000111" =>
register3 := register3 + register5;
WHEN "00001000" =>
register3 := register3 * 12;
register4 := register4 + register5;
register6 := register1 + register6;
WHEN "00001001" =>
register1 := register1 + register6;
output1 <= register6 + register4;
WHEN "00001010" =>
register1 := register1 * 15;
register3 := register2 + register3;
WHEN "00001011" =>
register2 := register2 + register3;
WHEN "00001100" =>
register2 := register2 * 17;
WHEN "00001101" =>
register2 := register2 + 19;
WHEN "00001110" =>
output2 <= register3 + register2;
register2 := register5 + register3;
WHEN "00001111" =>
register2 := register2 + 22;
WHEN "00010000" =>
register3 := register2 * 24;
WHEN "00010001" =>
register3 := register3 + 26;
WHEN "00010010" =>
output3 <= register2 + register3;
register1 := register1 + 29;
WHEN "00010011" =>
register2 := register1 + 31;
WHEN "00010100" =>
register2 := register2 * 33;
WHEN "00010101" =>
output4 <= register1 + register2;
register1 := register6 + register1;
WHEN "00010110" =>
register1 := register1 + 36;
WHEN "00010111" =>
register2 := register1 * 38;
WHEN "00011000" =>
register2 := register2 + 40;
WHEN "00011001" =>
output5 <= register1 + register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_nsga2_description;
|
gpl-3.0
|
jouyang3/FMCW
|
DSP/Radar_DSP/FPGA/Individual Modules/Working_FFT/Working_FFT/FFT_Mag/simulation/modelsim/work/magnitude/_primary.vhd
|
2
|
515
|
library verilog;
use verilog.vl_types.all;
entity magnitude is
port(
clk : in vl_logic;
Y0 : in vl_logic_vector(11 downto 0);
Y1 : in vl_logic_vector(11 downto 0);
Y2 : in vl_logic_vector(11 downto 0);
Y3 : in vl_logic_vector(11 downto 0);
mag1 : out vl_logic_vector(11 downto 0);
mag2 : out vl_logic_vector(11 downto 0)
);
end magnitude;
|
gpl-3.0
|
ECE492W2014G4/G4Capstone
|
AppNote/sdramBuffer.vhd
|
1
|
3762
|
-- reverbBuffer.vhd
-- This file was auto-generated as a prototype implementation of a module
-- created in component editor. It ties off all outputs to ground and
-- ignores all inputs. It needs to be edited to make it do something
-- useful.
--
-- This file will not be automatically regenerated. You should check it in
-- to your version control system if you want to keep it.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sdramBuffer is
generic (
AUTO_CLOCK_CLOCK_RATE : string := "-1";
base_addr : std_logic_vector(31 downto 0) := X"00000000";
buffersize : std_logic_vector(31 downto 0) := X"00002948"-- X"000014A4" X"00000A52"
);
port (
avm_m0_address : out std_logic_vector(31 downto 0); -- m0.address
avm_m0_read : out std_logic; -- .read
avm_m0_waitrequest : in std_logic := '0'; -- .waitrequest
avm_m0_readdata : in std_logic_vector(15 downto 0) := (others => '0'); -- .readdata
avm_m0_write : out std_logic; -- .write
avm_m0_writedata : out std_logic_vector(15 downto 0); -- .writedata
avm_m0_readdatavalid : in std_logic := '0'; -- .readdatavalid
buffer_in_valid : in std_logic;
buffer_in : in std_logic_vector(15 downto 0);
buffer_out_valid : out std_logic;
buffer_out : out std_logic_vector(15 downto 0);
clk : in std_logic := '0';
reset : in std_logic := '0' -- reset.reset_n
);
end entity sdramBuffer;
architecture rtl of sdramBuffer is
type state is (idle, reading, writing);
signal current_state: state;
signal read_addr, write_addr: std_logic_vector(31 downto 0) := base_addr;
begin
fsm: process(clk,reset)
begin
if reset = '0' then
write_addr <= base_addr;
read_addr <= base_addr;
current_state <= idle;
elsif rising_edge(clk) then
case current_state is
when idle =>
if buffer_in_valid = '1' then -- I have data avail.
avm_m0_write <= '1'; -- Telling the SDRAM we're writing to it.
current_state <= writing;
else
avm_m0_write <= '0';
end if;
when reading => -- Reading the SDRAM
if avm_m0_waitrequest = '0' then
avm_m0_address <= read_addr;
buffer_out <= avm_m0_readdata;
if read_addr = std_logic_vector(signed(buffersize) - 1) then
read_addr <= base_addr; -- To the beginning
elsif read_addr > write_addr then
read_addr <= std_logic_vector(signed(read_addr)+2);
else
read_addr <= std_logic_vector(signed(write_addr) - 2);
end if;
current_state <= idle;
buffer_out_valid <= '1';
else
buffer_out_valid <= '0';
end if;
when writing =>
if avm_m0_waitrequest = '0' then
avm_m0_address <= write_addr; -- can only write when waitrequest = 0
avm_m0_writedata <= buffer_in; -- Writes to SDRAM
if write_addr = std_logic_vector(signed(buffersize)-1) then
write_addr <= base_addr; -- Reset the write addr
else
write_addr <= std_logic_vector(signed(write_addr) + 2);
end if;
avm_m0_write <= '0'; -- Telling SDRAM we've stopped writing
avm_m0_read <= '1'; -- Read SDRAM (next cycle)
current_state <= reading;
end if;
when others =>
current_state <= idle;
end case;
end if;
end process;
end architecture rtl; -- of reverbBuffer
|
gpl-3.0
|
rhexsel/cmips
|
cMIPS/vhdl/aux.vhd
|
2
|
8688
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- 32-bit register, synchronous load active in '0'
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity register32 is
generic (INITIAL_VALUE: reg32 := x"00000000");
port(clk, rst, ld: in std_logic;
D: in reg32;
Q: out reg32);
end register32;
architecture functional of register32 is
begin
process(clk, rst)
variable state: reg32;
begin
if rst = '0' then
state := INITIAL_VALUE;
elsif rising_edge(clk) then
if ld = '0' then
state := D;
end if;
end if;
Q <= state;
end process;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- N-bit register, synchronous load active in '0', asynch reset
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity registerN is
generic (NUM_BITS: integer := 16;
INIT_VAL: std_logic_vector);
port(clk, rst, ld: in std_logic;
D: in std_logic_vector(NUM_BITS-1 downto 0);
Q: out std_logic_vector(NUM_BITS-1 downto 0));
end registerN;
architecture functional of registerN is
begin
process(clk, rst)
variable state: std_logic_vector(NUM_BITS-1 downto 0);
begin
if rst = '0' then
state := INIT_VAL;
elsif rising_edge(clk) then
if ld = '0' then
state := D;
end if;
end if;
Q <= state;
end process;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- 32-bit UP counter, {load,enable} synchronous, active in '0'
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_WIRES.all;
entity counter32 is
generic (INITIAL_VALUE: reg32 := x"00000000");
port(clk, rst, ld, en: in std_logic;
D: in reg32;
Q: out reg32);
end counter32;
architecture functional of counter32 is
signal count: reg32;
begin
process(clk, rst)
begin
if rst = '0' then
count <= INITIAL_VALUE;
elsif rising_edge(clk) then
if ld = '0' then
count <= D;
elsif en = '0' then
count <= std_logic_vector(unsigned(count) + 1);
end if;
end if;
end process;
Q <= count;
end functional;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- N-bit counter, synch load (=1), synch enable (=1), asynch reset (=0)
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity countNup is
generic (NUM_BITS: integer := 16);
port(clk, rst, ld, en: in std_logic;
D: in std_logic_vector((NUM_BITS - 1) downto 0);
Q: out std_logic_vector((NUM_BITS - 1) downto 0);
co: out std_logic);
end countNup;
architecture functional of countNup is
signal count: std_logic_vector(NUM_BITS downto 0);
begin
process(clk, rst)
constant ZERO : std_logic_vector(NUM_BITS downto 0) := (others => '0');
begin
if rst = '0' then
count <= ZERO;
elsif rising_edge(clk) then
if ld = '1' then
count <= '0' & D;
elsif en = '1' then
count <= std_logic_vector(unsigned(count) + 1);
end if;
end if;
end process;
Q <= count((NUM_BITS - 1) downto 0);
co <= count(NUM_BITS);
end functional;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ring-counter, generates four-phase internal clock, on falling-edge
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity count4phases is
port(clk, rst : in std_logic;
p0,p1,p2,p3 : out std_logic);
-- attribute ASYNC_SET_RESET of rst : signal is true;
-- attribute CLOCK_SIGNAL of clk : signal is "yes";
end count4phases;
architecture functional of count4phases is
signal count: reg4 := b"1000";
begin
process(clk, rst)
begin
if rst = '0' then
count <= b"1000";
elsif falling_edge(clk) then
count <= count(2 downto 0) & count(3);
end if;
end process;
p0 <= count(0);
p1 <= count(1);
p2 <= count(2);
p3 <= count(3);
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- D-type flip-flop with set and reset
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all;
entity FFD is
port(clk, rst, set : in std_logic;
D : in std_logic;
Q : out std_logic);
end FFD;
architecture functional of FFD is
begin
process(clk, rst, set)
variable state: std_logic;
begin
if rst = '0' then
state := '0';
elsif set = '0' then
state := '1';
elsif rising_edge(clk) then
state := D;
end if;
Q <= state;
end process;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- D-type flip-flop with reset
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all;
entity FFDsimple is
port(clk, rst : in std_logic;
D : in std_logic;
Q : out std_logic);
end FFDsimple;
architecture functional of FFDsimple is
begin
process(clk, rst)
variable state: std_logic;
begin
if rst = '0' then
state := '0';
elsif rising_edge(clk) then
state := D;
end if;
Q <= state;
end process;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- T-type flip-flop with reset (active 0)
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE; use IEEE.std_logic_1164.all;
entity FFT is
port(clk, rst : in std_logic;
T : in std_logic;
Q : out std_logic);
end FFT;
architecture functional of FFT is
begin
process(clk, rst)
variable state: std_logic;
begin
if rst = '0' then
state := '0';
elsif rising_edge(clk) then
state := T xor state;
end if;
Q <= state;
end process;
end functional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity subtr32 IS
port(A, B : in std_logic_vector (31 downto 0);
C : out std_logic_vector (31 downto 0);
sgnd : in std_logic;
ovfl, lt : out std_logic);
end subtr32;
architecture functional of subtr32 is
signal extA,extB,extC,negB : std_logic_vector (32 downto 0);
begin
extA <= A(31) & A when sgnd = '1'
else '0' & A;
extB <= B(31) & B when sgnd = '1'
else '0' & B;
negB <= not(extB);
extC <= std_logic_vector( signed(extA) + signed(negB) + 1);
C <= extC(31 downto 0);
ovfl <= '1' when extC(32) /= extC(31) else '0';
lt <= not(extC(31)) when (extC(32) /= extC(31)) else extC(31);
end architecture functional;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
ECE492W2014G4/G4Capstone
|
AppNote/sdram_circular_buffer.vhd
|
1
|
9058
|
-- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity sdram_circular_buffer is
port
(
-- Input ports and 50 MHz Clock
CLOCK_50 : in std_logic;
CLOCK_27 : in std_logic;
SW : in std_logic_vector(0 downto 0);
KEY : in std_logic_vector(0 downto 0);
-- SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
--Audio Signals on board
--From audio appnote
AUD_ADCLRCK : inout std_logic;
AUD_ADCDAT : in std_logic;
AUD_DACLRCK : inout std_logic;
AUD_DACDAT : out std_logic;
AUD_XCK : out std_logic;
AUD_BCLK : inout std_logic;
-- Audio/Video Config I2C interface
-- From audio appnote
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic
);
end sdram_circular_buffer;
architecture structure of sdram_circular_buffer is
-- Declarations (optional)
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
clk_0_clk : in std_logic := 'X'; -- clk
reset_0_reset_n : in std_logic := 'X'; -- reset_n
audio_0_external_interface_ADCDAT : in std_logic := 'X'; -- ADCDAT
audio_0_external_interface_ADCLRCK : in std_logic := 'X'; -- ADCLRCK
audio_0_external_interface_BCLK : in std_logic := 'X'; -- BCLK
audio_0_external_interface_DACDAT : out std_logic; -- DACDAT
audio_0_external_interface_DACLRCK : in std_logic := 'X'; -- DACLRCK
audio_and_video_config_0_external_interface_SDAT : inout std_logic := 'X'; -- SDAT
audio_and_video_config_0_external_interface_SCLK : out std_logic; -- SCLK
audio_clk_clk : out std_logic;
dram_clk_clk : out std_logic -- clk
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
clk_0_clk => CLOCK_27,
reset_0_reset_n => KEY(0),
audio_0_external_interface_ADCDAT => AUD_ADCDAT,
audio_0_external_interface_ADCLRCK => AUD_ADCLRCK,
audio_0_external_interface_BCLK => AUD_BCLK,
audio_0_external_interface_DACDAT => AUD_DACDAT,
audio_0_external_interface_DACLRCK => AUD_DACLRCK,
audio_and_video_config_0_external_interface_SDAT => I2C_SDAT,
audio_and_video_config_0_external_interface_SCLK => I2C_SCLK,
audio_clk_clk => AUD_XCK,
dram_clk_clk => DRAM_CLK
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
|
gpl-3.0
|
rhexsel/cmips
|
cMIPS/vhdl/exception.vhd
|
2
|
7500
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-------------------------------------------------------------------------
-- Interrupt/exception pipeline registers
-------------------------------------------------------------------------
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- exception IF-RF
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
use work.p_EXCEPTION.all;
entity reg_excp_IF_RF is
port(clk, rst, ld: in std_logic;
IF_excp_type: in exception_type;
RF_excp_type: out exception_type;
PC_abort: in boolean;
RF_PC_abort: out boolean;
IF_PC: in reg32;
RF_PC: out reg32);
end reg_excp_IF_RF;
architecture funcional of reg_excp_IF_RF is
begin
process(clk, rst, ld)
begin
if rising_edge(clk) then
if ld = '0' then
RF_excp_type <= IF_excp_type ;
RF_PC_abort <= PC_abort ;
RF_PC <= IF_PC ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- exception RF-EX
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
use work.p_EXCEPTION.all;
entity reg_excp_RF_EX is
port(clk, rst, ld: in std_logic;
RF_cop0_reg: in reg5;
EX_cop0_reg: out reg5;
RF_cop0_sel: in reg3;
EX_cop0_sel: out reg3;
RF_can_trap: in reg2;
EX_can_trap: out reg2;
RF_exception: in exception_type;
EX_exception: out exception_type;
RF_is_delayslot: in std_logic;
EX_is_delayslot: out std_logic;
RF_PC_abort: in boolean;
EX_PC_abort: out boolean;
RF_PC: in reg32;
EX_PC: out reg32;
RF_trap_taken: in boolean;
EX_trapped: out boolean);
end reg_excp_RF_EX;
architecture funcional of reg_excp_RF_EX is
begin
process(clk, rst, ld)
begin
if rst = '0' then
EX_can_trap <= b"00";
EX_is_delayslot <= '0';
EX_trapped <= FALSE;
elsif rising_edge(clk) then
if ld = '0' then
EX_cop0_reg <= RF_cop0_reg ;
EX_cop0_sel <= RF_cop0_sel ;
EX_can_trap <= RF_can_trap ;
EX_exception <= RF_exception ;
EX_is_delayslot <= RF_is_delayslot ;
EX_PC_abort <= RF_PC_abort ;
EX_PC <= RF_PC ;
EX_trapped <= RF_trap_taken ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- exception EX-MEM
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
use work.p_EXCEPTION.all;
entity reg_excp_EX_MM is
port(clk, rst, ld: in std_logic;
EX_cop0_reg: in reg5;
MM_cop0_reg: out reg5;
EX_cop0_sel: in reg3;
MM_cop0_sel: out reg3;
EX_PC: in reg32;
MM_PC: out reg32;
EX_v_addr: in reg32;
MM_v_addr: out reg32;
EX_nullify: in boolean;
MM_nullify: out boolean;
EX_addrError: in boolean;
MM_addrError: out boolean;
EX_addrErr_stage_mm: in boolean;
MM_addrErr_stage_mm: out boolean;
EX_is_delayslot: in std_logic;
MM_is_delayslot: out std_logic;
EX_trapped: in boolean;
MM_trapped: out boolean;
EX_ll_sc_abort: in boolean;
MM_ll_sc_abort: out boolean;
EX_tlb_exception: in boolean;
MM_tlb_exception: out boolean;
EX_tlb_stage_mm: in boolean;
MM_tlb_stage_mm: out boolean;
EX_int_req: in reg6;
MM_int_req: out reg6;
EX_is_SC: in boolean;
MM_is_SC: out boolean;
EX_is_MFC0: in boolean;
MM_is_MFC0: out boolean;
EX_is_exception: in exception_type;
MM_is_exception: out exception_type);
end reg_excp_EX_MM;
architecture funcional of reg_excp_EX_MM is
begin
process(clk, rst, ld)
begin
if rst = '0' then
MM_trapped <= FALSE;
MM_nullify <= FALSE;
MM_addrError <= FALSE;
MM_trapped <= FALSE;
MM_tlb_exception <= FALSE;
MM_is_exception <= exNOP;
elsif rising_edge(clk) then
if ld = '0' then
MM_cop0_reg <= EX_cop0_reg ;
MM_cop0_sel <= EX_cop0_sel ;
MM_PC <= EX_PC ;
MM_v_addr <= EX_v_addr ;
MM_nullify <= EX_nullify ;
MM_addrError <= EX_addrError ;
MM_addrErr_stage_mm <= EX_addrErr_stage_mm;
MM_is_delayslot <= EX_is_delayslot;
MM_trapped <= EX_trapped ;
MM_ll_sc_abort <= EX_ll_sc_abort ;
MM_tlb_exception <= EX_tlb_exception;
MM_tlb_stage_MM <= EX_tlb_stage_MM;
MM_int_req <= EX_int_req ;
MM_is_SC <= EX_is_SC ;
MM_is_MFC0 <= EX_is_MFC0 ;
MM_is_exception <= EX_is_exception;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- exception MEM-WB
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
use work.p_EXCEPTION.all;
entity reg_excp_MM_WB is
port(clk, rst, ld: in std_logic;
MM_PC: in reg32;
WB_PC: out reg32;
MM_cop0_LLbit: in std_logic;
WB_cop0_LLbit: out std_logic;
MM_is_delayslot: in std_logic;
WB_is_delayslot: out std_logic;
MM_cop0_val: in reg32;
WB_cop0_val: out reg32);
end reg_excp_MM_WB;
architecture funcional of reg_excp_MM_WB is
begin
process(clk, rst, ld)
begin
if rst = '0' then
WB_cop0_LLbit <= '0';
elsif rising_edge(clk) then
if ld = '0' then
WB_PC <= MM_PC ;
WB_cop0_LLbit <= MM_cop0_LLbit ;
WB_is_delayslot <= MM_is_delayslot;
WB_cop0_val <= MM_cop0_val ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
gpl-3.0
|
jmacneal/Design-Project
|
FFT_HDL/transceiver_hdl/OFDM_transmitter/IFFT_HDL_Optimized.vhd
|
1
|
124472
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/IFFT_HDL_Optimized.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: IFFT_HDL_Optimized
-- Source Path: OFDM_transmitter/IFFT HDL Optimized
-- Hierarchy Level: 1
--
-- FFT HDL Optimized
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.OFDM_transmitter_pkg.ALL;
ENTITY IFFT_HDL_Optimized IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dataIn_re : IN vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
dataIn_im : IN vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
validIn : IN std_logic;
dataOut_re : OUT vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
dataOut_im : OUT vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
validOut : OUT std_logic
);
END IFFT_HDL_Optimized;
ARCHITECTURE rtl OF IFFT_HDL_Optimized IS
-- Component Declarations
COMPONENT RADIX22FFT_SDNF1_1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_1 : IN std_logic; -- ufix1
dout_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_2_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_1_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_5 : IN std_logic; -- ufix1
dout_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_1_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_3_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_4_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_1 : IN std_logic; -- ufix1
dout_1_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_5_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_5_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_5_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_7
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_8
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_8_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_5 : IN std_logic; -- ufix1
dout_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_5_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_9 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_11 : IN std_logic; -- ufix1
dout_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_10
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_10_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_13 : IN std_logic; -- ufix1
dout_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_2_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_11
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_12
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block3
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_9 : IN std_logic; -- ufix1
dout_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block4
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_11 : IN std_logic; -- ufix1
dout_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_11_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_14
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_15
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLROM_3_16
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_vld : OUT std_logic
);
END COMPONENT;
COMPONENT TWDLMULT_SDNF1_3_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_16_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF1_3_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block5
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_13 : IN std_logic; -- ufix1
dout_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
COMPONENT RADIX22FFT_SDNF2_4_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : RADIX22FFT_SDNF1_1
USE ENTITY work.RADIX22FFT_SDNF1_1(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block3
USE ENTITY work.RADIX22FFT_SDNF1_1_block3(rtl);
FOR ALL : RADIX22FFT_SDNF2_2
USE ENTITY work.RADIX22FFT_SDNF2_2(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block
USE ENTITY work.RADIX22FFT_SDNF1_1_block(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block4
USE ENTITY work.RADIX22FFT_SDNF1_1_block4(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block
USE ENTITY work.RADIX22FFT_SDNF2_2_block(rtl);
FOR ALL : TWDLROM_3_2
USE ENTITY work.TWDLROM_3_2(rtl);
FOR ALL : TWDLMULT_SDNF1_3
USE ENTITY work.TWDLMULT_SDNF1_3(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block1
USE ENTITY work.RADIX22FFT_SDNF1_1_block1(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block5
USE ENTITY work.RADIX22FFT_SDNF1_1_block5(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block1
USE ENTITY work.RADIX22FFT_SDNF2_2_block1(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block2
USE ENTITY work.RADIX22FFT_SDNF1_1_block2(rtl);
FOR ALL : RADIX22FFT_SDNF1_1_block6
USE ENTITY work.RADIX22FFT_SDNF1_1_block6(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block2
USE ENTITY work.RADIX22FFT_SDNF2_2_block2(rtl);
FOR ALL : TWDLROM_3_3
USE ENTITY work.TWDLROM_3_3(rtl);
FOR ALL : TWDLROM_3_4
USE ENTITY work.TWDLROM_3_4(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block
USE ENTITY work.TWDLMULT_SDNF1_3_block(rtl);
FOR ALL : RADIX22FFT_SDNF1_3
USE ENTITY work.RADIX22FFT_SDNF1_3(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block
USE ENTITY work.RADIX22FFT_SDNF1_3_block(rtl);
FOR ALL : RADIX22FFT_SDNF2_4
USE ENTITY work.RADIX22FFT_SDNF2_4(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block
USE ENTITY work.RADIX22FFT_SDNF2_4_block(rtl);
FOR ALL : TWDLROM_3_6
USE ENTITY work.TWDLROM_3_6(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block1
USE ENTITY work.TWDLMULT_SDNF1_3_block1(rtl);
FOR ALL : TWDLROM_3_7
USE ENTITY work.TWDLROM_3_7(rtl);
FOR ALL : TWDLROM_3_8
USE ENTITY work.TWDLROM_3_8(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block2
USE ENTITY work.TWDLMULT_SDNF1_3_block2(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block1
USE ENTITY work.RADIX22FFT_SDNF1_3_block1(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block2
USE ENTITY work.RADIX22FFT_SDNF1_3_block2(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block1
USE ENTITY work.RADIX22FFT_SDNF2_4_block1(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block2
USE ENTITY work.RADIX22FFT_SDNF2_4_block2(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block3
USE ENTITY work.RADIX22FFT_SDNF2_2_block3(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block4
USE ENTITY work.RADIX22FFT_SDNF2_2_block4(rtl);
FOR ALL : TWDLROM_3_10
USE ENTITY work.TWDLROM_3_10(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block3
USE ENTITY work.TWDLMULT_SDNF1_3_block3(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block5
USE ENTITY work.RADIX22FFT_SDNF2_2_block5(rtl);
FOR ALL : RADIX22FFT_SDNF2_2_block6
USE ENTITY work.RADIX22FFT_SDNF2_2_block6(rtl);
FOR ALL : TWDLROM_3_11
USE ENTITY work.TWDLROM_3_11(rtl);
FOR ALL : TWDLROM_3_12
USE ENTITY work.TWDLROM_3_12(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block4
USE ENTITY work.TWDLMULT_SDNF1_3_block4(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block3
USE ENTITY work.RADIX22FFT_SDNF1_3_block3(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block4
USE ENTITY work.RADIX22FFT_SDNF1_3_block4(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block3
USE ENTITY work.RADIX22FFT_SDNF2_4_block3(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block4
USE ENTITY work.RADIX22FFT_SDNF2_4_block4(rtl);
FOR ALL : TWDLROM_3_14
USE ENTITY work.TWDLROM_3_14(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block5
USE ENTITY work.TWDLMULT_SDNF1_3_block5(rtl);
FOR ALL : TWDLROM_3_15
USE ENTITY work.TWDLROM_3_15(rtl);
FOR ALL : TWDLROM_3_16
USE ENTITY work.TWDLROM_3_16(rtl);
FOR ALL : TWDLMULT_SDNF1_3_block6
USE ENTITY work.TWDLMULT_SDNF1_3_block6(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block5
USE ENTITY work.RADIX22FFT_SDNF1_3_block5(rtl);
FOR ALL : RADIX22FFT_SDNF1_3_block6
USE ENTITY work.RADIX22FFT_SDNF1_3_block6(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block5
USE ENTITY work.RADIX22FFT_SDNF2_4_block5(rtl);
FOR ALL : RADIX22FFT_SDNF2_4_block6
USE ENTITY work.RADIX22FFT_SDNF2_4_block6(rtl);
-- Signals
SIGNAL rotate_1 : std_logic; -- ufix1
SIGNAL rotate_1_1 : std_logic; -- ufix1
SIGNAL twdlXdin_1_vld : std_logic;
SIGNAL softReset : std_logic;
SIGNAL dout_1_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_vld : std_logic;
SIGNAL dout_9_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_vld : std_logic;
SIGNAL dout_1_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld : std_logic;
SIGNAL rotate_3 : std_logic; -- ufix1
SIGNAL dout_3_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_vld : std_logic;
SIGNAL dout_11_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_vld : std_logic;
SIGNAL dout_3_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_1 : std_logic;
SIGNAL twdl_3_1_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_1_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_2_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_2_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_2_vld : std_logic;
SIGNAL twdlXdin_1_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_1_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_2_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_2_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_1_vld_1 : std_logic;
SIGNAL rotate_5 : std_logic; -- ufix1
SIGNAL dout_5_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_vld : std_logic;
SIGNAL dout_13_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_vld : std_logic;
SIGNAL dout_5_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_2 : std_logic;
SIGNAL rotate_7 : std_logic; -- ufix1
SIGNAL dout_7_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_vld : std_logic;
SIGNAL dout_15_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_vld : std_logic;
SIGNAL dout_7_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_3 : std_logic;
SIGNAL twdl_3_3_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_3_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_3_vld : std_logic;
SIGNAL twdl_3_4_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_4_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_4_vld : std_logic;
SIGNAL twdlXdin_3_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_3_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_4_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_4_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_3_vld : std_logic;
SIGNAL dout_1_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_1_vld_1 : std_logic;
SIGNAL dout_3_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_4_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_3_vld_1 : std_logic;
SIGNAL dout_4_vld : std_logic;
SIGNAL rotate_3_1 : std_logic; -- ufix1
SIGNAL dout_4_vld_1 : std_logic;
SIGNAL rotate_5_1 : std_logic; -- ufix1
SIGNAL twdl_3_5_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_5_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_6_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_6_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_6_vld : std_logic;
SIGNAL twdlXdin_5_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_5_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_6_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_6_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_5_vld : std_logic;
SIGNAL twdl_3_7_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_7_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_7_vld : std_logic;
SIGNAL twdl_3_8_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_8_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_8_vld : std_logic;
SIGNAL twdlXdin_7_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_7_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_8_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_8_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_7_vld : std_logic;
SIGNAL dout_5_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_6_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_5_vld_1 : std_logic;
SIGNAL dout_7_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_8_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_7_vld_1 : std_logic;
SIGNAL dout_4_vld_2 : std_logic;
SIGNAL rotate_7_1 : std_logic; -- ufix1
SIGNAL dout_4_vld_3 : std_logic;
SIGNAL rotate_9 : std_logic; -- ufix1
SIGNAL rotate_9_1 : std_logic; -- ufix1
SIGNAL dout_9_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_4 : std_logic;
SIGNAL rotate_11 : std_logic; -- ufix1
SIGNAL dout_11_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_5 : std_logic;
SIGNAL twdl_3_9_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_9_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_10_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_10_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_10_vld : std_logic;
SIGNAL twdlXdin_9_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_9_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_10_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_10_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_9_vld : std_logic;
SIGNAL rotate_13 : std_logic; -- ufix1
SIGNAL dout_13_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_6 : std_logic;
SIGNAL rotate_15 : std_logic; -- ufix1
SIGNAL dout_15_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_re_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_im_1 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_2_vld_7 : std_logic;
SIGNAL twdl_3_11_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_11_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_11_vld : std_logic;
SIGNAL twdl_3_12_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_12_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_12_vld : std_logic;
SIGNAL twdlXdin_11_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_11_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_12_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_12_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_11_vld : std_logic;
SIGNAL dout_9_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_10_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_9_vld_1 : std_logic;
SIGNAL dout_11_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_12_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_11_vld_1 : std_logic;
SIGNAL dout_4_vld_4 : std_logic;
SIGNAL rotate_11_1 : std_logic; -- ufix1
SIGNAL dout_4_vld_5 : std_logic;
SIGNAL rotate_13_1 : std_logic; -- ufix1
SIGNAL twdl_3_13_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_13_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_14_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_14_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_14_vld : std_logic;
SIGNAL twdlXdin_13_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_13_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_14_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_14_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_13_vld : std_logic;
SIGNAL twdl_3_15_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_15_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_15_vld : std_logic;
SIGNAL twdl_3_16_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_16_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdl_3_16_vld : std_logic;
SIGNAL twdlXdin_15_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_15_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_16_re : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_16_im : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_15_vld : std_logic;
SIGNAL dout_13_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_14_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_13_vld_1 : std_logic;
SIGNAL dout_15_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_re_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_16_im_2 : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL dout_15_vld_1 : std_logic;
SIGNAL dout_4_vld_6 : std_logic;
SIGNAL rotate_15_1 : std_logic; -- ufix1
SIGNAL dout_4_vld_7 : std_logic;
SIGNAL dataOut_re_tmp : vector_of_std_logic_vector16(0 TO 15); -- ufix16 [16]
SIGNAL dataOut_im_tmp : vector_of_std_logic_vector16(0 TO 15); -- ufix16 [16]
BEGIN
u_SDNF1_1_1 : RADIX22FFT_SDNF1_1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_1_re => dataIn_im(0), -- sfix16_En13
twdlXdin_1_im => dataIn_re(0), -- sfix16_En13
twdlXdin_9_re => dataIn_im(8), -- sfix16_En13
twdlXdin_9_im => dataIn_re(8), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_1_re => dout_1_re, -- sfix16_En13
dout_1_im => dout_1_im, -- sfix16_En13
dout_2_re => dout_2_re, -- sfix16_En13
dout_2_im => dout_2_im, -- sfix16_En13
dout_1_vld => dout_1_vld
);
u_SDNF1_1_9 : RADIX22FFT_SDNF1_1_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_5_re => dataIn_im(4), -- sfix16_En13
twdlXdin_5_im => dataIn_re(4), -- sfix16_En13
twdlXdin_13_re => dataIn_im(12), -- sfix16_En13
twdlXdin_13_im => dataIn_re(12), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_9_re => dout_9_re, -- sfix16_En13
dout_9_im => dout_9_im, -- sfix16_En13
dout_10_re => dout_10_re, -- sfix16_En13
dout_10_im => dout_10_im, -- sfix16_En13
dout_9_vld => dout_9_vld
);
u_SDNF2_2_1 : RADIX22FFT_SDNF2_2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_1 => rotate_1_1, -- ufix1
dout_1_re => dout_1_re, -- sfix16_En13
dout_1_im => dout_1_im, -- sfix16_En13
dout_9_re => dout_9_re, -- sfix16_En13
dout_9_im => dout_9_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_1_re_1 => dout_1_re_1, -- sfix16_En13
dout_1_im_1 => dout_1_im_1, -- sfix16_En13
dout_2_re => dout_2_re_1, -- sfix16_En13
dout_2_im => dout_2_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld
);
u_SDNF1_1_3 : RADIX22FFT_SDNF1_1_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_2_re => dataIn_im(1), -- sfix16_En13
twdlXdin_2_im => dataIn_re(1), -- sfix16_En13
twdlXdin_10_re => dataIn_im(9), -- sfix16_En13
twdlXdin_10_im => dataIn_re(9), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_3_re => dout_3_re, -- sfix16_En13
dout_3_im => dout_3_im, -- sfix16_En13
dout_4_re => dout_4_re, -- sfix16_En13
dout_4_im => dout_4_im, -- sfix16_En13
dout_3_vld => dout_3_vld
);
u_SDNF1_1_11 : RADIX22FFT_SDNF1_1_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_6_re => dataIn_im(5), -- sfix16_En13
twdlXdin_6_im => dataIn_re(5), -- sfix16_En13
twdlXdin_14_re => dataIn_im(13), -- sfix16_En13
twdlXdin_14_im => dataIn_re(13), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_11_re => dout_11_re, -- sfix16_En13
dout_11_im => dout_11_im, -- sfix16_En13
dout_12_re => dout_12_re, -- sfix16_En13
dout_12_im => dout_12_im, -- sfix16_En13
dout_11_vld => dout_11_vld
);
u_SDNF2_2_3 : RADIX22FFT_SDNF2_2_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_3 => rotate_3, -- ufix1
dout_3_re => dout_3_re, -- sfix16_En13
dout_3_im => dout_3_im, -- sfix16_En13
dout_11_re => dout_11_re, -- sfix16_En13
dout_11_im => dout_11_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_3_re_1 => dout_3_re_1, -- sfix16_En13
dout_3_im_1 => dout_3_im_1, -- sfix16_En13
dout_4_re => dout_4_re_1, -- sfix16_En13
dout_4_im => dout_4_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_1
);
u_twdlROM_3_2 : TWDLROM_3_2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_2_re => twdl_3_2_re, -- sfix16_En14
twdl_3_2_im => twdl_3_2_im, -- sfix16_En14
twdl_3_2_vld => twdl_3_2_vld
);
u_TWDLMULT_SDNF1_3_1 : TWDLMULT_SDNF1_3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_1_re => dout_1_re_1, -- sfix16_En13
dout_1_im => dout_1_im_1, -- sfix16_En13
dout_3_re => dout_3_re_1, -- sfix16_En13
dout_3_im => dout_3_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_1_re => std_logic_vector(twdl_3_1_re), -- sfix16_En14
twdl_3_1_im => std_logic_vector(twdl_3_1_im), -- sfix16_En14
twdl_3_2_re => twdl_3_2_re, -- sfix16_En14
twdl_3_2_im => twdl_3_2_im, -- sfix16_En14
twdl_3_2_vld => twdl_3_2_vld,
softReset => softReset,
twdlXdin_1_re => twdlXdin_1_re, -- sfix16_En13
twdlXdin_1_im => twdlXdin_1_im, -- sfix16_En13
twdlXdin_2_re => twdlXdin_2_re, -- sfix16_En13
twdlXdin_2_im => twdlXdin_2_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1
);
u_SDNF1_1_5 : RADIX22FFT_SDNF1_1_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_3_re => dataIn_im(2), -- sfix16_En13
twdlXdin_3_im => dataIn_re(2), -- sfix16_En13
twdlXdin_11_re => dataIn_im(10), -- sfix16_En13
twdlXdin_11_im => dataIn_re(10), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_5_re => dout_5_re, -- sfix16_En13
dout_5_im => dout_5_im, -- sfix16_En13
dout_6_re => dout_6_re, -- sfix16_En13
dout_6_im => dout_6_im, -- sfix16_En13
dout_5_vld => dout_5_vld
);
u_SDNF1_1_13 : RADIX22FFT_SDNF1_1_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_7_re => dataIn_im(6), -- sfix16_En13
twdlXdin_7_im => dataIn_re(6), -- sfix16_En13
twdlXdin_15_re => dataIn_im(14), -- sfix16_En13
twdlXdin_15_im => dataIn_re(14), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_13_re => dout_13_re, -- sfix16_En13
dout_13_im => dout_13_im, -- sfix16_En13
dout_14_re => dout_14_re, -- sfix16_En13
dout_14_im => dout_14_im, -- sfix16_En13
dout_13_vld => dout_13_vld
);
u_SDNF2_2_5 : RADIX22FFT_SDNF2_2_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_5 => rotate_5, -- ufix1
dout_5_re => dout_5_re, -- sfix16_En13
dout_5_im => dout_5_im, -- sfix16_En13
dout_13_re => dout_13_re, -- sfix16_En13
dout_13_im => dout_13_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_5_re_1 => dout_5_re_1, -- sfix16_En13
dout_5_im_1 => dout_5_im_1, -- sfix16_En13
dout_6_re => dout_6_re_1, -- sfix16_En13
dout_6_im => dout_6_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_2
);
u_SDNF1_1_7 : RADIX22FFT_SDNF1_1_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_4_re => dataIn_im(3), -- sfix16_En13
twdlXdin_4_im => dataIn_re(3), -- sfix16_En13
twdlXdin_12_re => dataIn_im(11), -- sfix16_En13
twdlXdin_12_im => dataIn_re(11), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_7_re => dout_7_re, -- sfix16_En13
dout_7_im => dout_7_im, -- sfix16_En13
dout_8_re => dout_8_re, -- sfix16_En13
dout_8_im => dout_8_im, -- sfix16_En13
dout_7_vld => dout_7_vld
);
u_SDNF1_1_15 : RADIX22FFT_SDNF1_1_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_8_re => dataIn_im(7), -- sfix16_En13
twdlXdin_8_im => dataIn_re(7), -- sfix16_En13
twdlXdin_16_re => dataIn_im(15), -- sfix16_En13
twdlXdin_16_im => dataIn_re(15), -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld,
softReset => softReset,
dout_15_re => dout_15_re, -- sfix16_En13
dout_15_im => dout_15_im, -- sfix16_En13
dout_16_re => dout_16_re, -- sfix16_En13
dout_16_im => dout_16_im, -- sfix16_En13
dout_15_vld => dout_15_vld
);
u_SDNF2_2_7 : RADIX22FFT_SDNF2_2_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_7 => rotate_7, -- ufix1
dout_7_re => dout_7_re, -- sfix16_En13
dout_7_im => dout_7_im, -- sfix16_En13
dout_15_re => dout_15_re, -- sfix16_En13
dout_15_im => dout_15_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_7_re_1 => dout_7_re_1, -- sfix16_En13
dout_7_im_1 => dout_7_im_1, -- sfix16_En13
dout_8_re => dout_8_re_1, -- sfix16_En13
dout_8_im => dout_8_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_3
);
u_twdlROM_3_3 : TWDLROM_3_3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_3_re => twdl_3_3_re, -- sfix16_En14
twdl_3_3_im => twdl_3_3_im, -- sfix16_En14
twdl_3_3_vld => twdl_3_3_vld
);
u_twdlROM_3_4 : TWDLROM_3_4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_4_re => twdl_3_4_re, -- sfix16_En14
twdl_3_4_im => twdl_3_4_im, -- sfix16_En14
twdl_3_4_vld => twdl_3_4_vld
);
u_TWDLMULT_SDNF1_3_3 : TWDLMULT_SDNF1_3_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_5_re => dout_5_re_1, -- sfix16_En13
dout_5_im => dout_5_im_1, -- sfix16_En13
dout_7_re => dout_7_re_1, -- sfix16_En13
dout_7_im => dout_7_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_3_re => twdl_3_3_re, -- sfix16_En14
twdl_3_3_im => twdl_3_3_im, -- sfix16_En14
twdl_3_4_re => twdl_3_4_re, -- sfix16_En14
twdl_3_4_im => twdl_3_4_im, -- sfix16_En14
twdl_3_4_vld => twdl_3_4_vld,
softReset => softReset,
twdlXdin_3_re => twdlXdin_3_re, -- sfix16_En13
twdlXdin_3_im => twdlXdin_3_im, -- sfix16_En13
twdlXdin_4_re => twdlXdin_4_re, -- sfix16_En13
twdlXdin_4_im => twdlXdin_4_im, -- sfix16_En13
twdlXdin_3_vld => twdlXdin_3_vld
);
u_SDNF1_3_1 : RADIX22FFT_SDNF1_3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_1_re => twdlXdin_1_re, -- sfix16_En13
twdlXdin_1_im => twdlXdin_1_im, -- sfix16_En13
twdlXdin_3_re => twdlXdin_3_re, -- sfix16_En13
twdlXdin_3_im => twdlXdin_3_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_1_re => dout_1_re_2, -- sfix16_En13
dout_1_im => dout_1_im_2, -- sfix16_En13
dout_2_re => dout_2_re_2, -- sfix16_En13
dout_2_im => dout_2_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1
);
u_SDNF1_3_3 : RADIX22FFT_SDNF1_3_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_2_re => twdlXdin_2_re, -- sfix16_En13
twdlXdin_2_im => twdlXdin_2_im, -- sfix16_En13
twdlXdin_4_re => twdlXdin_4_re, -- sfix16_En13
twdlXdin_4_im => twdlXdin_4_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_3_re => dout_3_re_2, -- sfix16_En13
dout_3_im => dout_3_im_2, -- sfix16_En13
dout_4_re => dout_4_re_2, -- sfix16_En13
dout_4_im => dout_4_im_2, -- sfix16_En13
dout_3_vld => dout_3_vld_1
);
u_SDNF2_4_1 : RADIX22FFT_SDNF2_4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_1 => rotate_1, -- ufix1
dout_1_re => dout_1_re_2, -- sfix16_En13
dout_1_im => dout_1_im_2, -- sfix16_En13
dout_3_re => dout_3_re_2, -- sfix16_En13
dout_3_im => dout_3_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_1_re_1 => dataOut_im_tmp(0), -- sfix16_En13
dout_1_im_1 => dataOut_re_tmp(0), -- sfix16_En13
dout_2_re => dataOut_im_tmp(1), -- sfix16_En13
dout_2_im => dataOut_re_tmp(1), -- sfix16_En13
dout_4_vld => dout_4_vld
);
u_SDNF2_4_3 : RADIX22FFT_SDNF2_4_block
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_3 => rotate_3_1, -- ufix1
dout_2_re => dout_2_re_2, -- sfix16_En13
dout_2_im => dout_2_im_2, -- sfix16_En13
dout_4_re => dout_4_re_2, -- sfix16_En13
dout_4_im => dout_4_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_3_re => dataOut_im_tmp(2), -- sfix16_En13
dout_3_im => dataOut_re_tmp(2), -- sfix16_En13
dout_4_re_1 => dataOut_im_tmp(3), -- sfix16_En13
dout_4_im_1 => dataOut_re_tmp(3), -- sfix16_En13
dout_4_vld => dout_4_vld_1
);
u_twdlROM_3_6 : TWDLROM_3_6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_6_re => twdl_3_6_re, -- sfix16_En14
twdl_3_6_im => twdl_3_6_im, -- sfix16_En14
twdl_3_6_vld => twdl_3_6_vld
);
u_TWDLMULT_SDNF1_3_5 : TWDLMULT_SDNF1_3_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_re => dout_2_re_1, -- sfix16_En13
dout_2_im => dout_2_im_1, -- sfix16_En13
dout_4_re => dout_4_re_1, -- sfix16_En13
dout_4_im => dout_4_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_5_re => std_logic_vector(twdl_3_5_re), -- sfix16_En14
twdl_3_5_im => std_logic_vector(twdl_3_5_im), -- sfix16_En14
twdl_3_6_re => twdl_3_6_re, -- sfix16_En14
twdl_3_6_im => twdl_3_6_im, -- sfix16_En14
twdl_3_6_vld => twdl_3_6_vld,
softReset => softReset,
twdlXdin_5_re => twdlXdin_5_re, -- sfix16_En13
twdlXdin_5_im => twdlXdin_5_im, -- sfix16_En13
twdlXdin_6_re => twdlXdin_6_re, -- sfix16_En13
twdlXdin_6_im => twdlXdin_6_im, -- sfix16_En13
twdlXdin_5_vld => twdlXdin_5_vld
);
u_twdlROM_3_7 : TWDLROM_3_7
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_7_re => twdl_3_7_re, -- sfix16_En14
twdl_3_7_im => twdl_3_7_im, -- sfix16_En14
twdl_3_7_vld => twdl_3_7_vld
);
u_twdlROM_3_8 : TWDLROM_3_8
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_8_re => twdl_3_8_re, -- sfix16_En14
twdl_3_8_im => twdl_3_8_im, -- sfix16_En14
twdl_3_8_vld => twdl_3_8_vld
);
u_TWDLMULT_SDNF1_3_7 : TWDLMULT_SDNF1_3_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_6_re => dout_6_re_1, -- sfix16_En13
dout_6_im => dout_6_im_1, -- sfix16_En13
dout_8_re => dout_8_re_1, -- sfix16_En13
dout_8_im => dout_8_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_7_re => twdl_3_7_re, -- sfix16_En14
twdl_3_7_im => twdl_3_7_im, -- sfix16_En14
twdl_3_8_re => twdl_3_8_re, -- sfix16_En14
twdl_3_8_im => twdl_3_8_im, -- sfix16_En14
twdl_3_8_vld => twdl_3_8_vld,
softReset => softReset,
twdlXdin_7_re => twdlXdin_7_re, -- sfix16_En13
twdlXdin_7_im => twdlXdin_7_im, -- sfix16_En13
twdlXdin_8_re => twdlXdin_8_re, -- sfix16_En13
twdlXdin_8_im => twdlXdin_8_im, -- sfix16_En13
twdlXdin_7_vld => twdlXdin_7_vld
);
u_SDNF1_3_5 : RADIX22FFT_SDNF1_3_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_5_re => twdlXdin_5_re, -- sfix16_En13
twdlXdin_5_im => twdlXdin_5_im, -- sfix16_En13
twdlXdin_7_re => twdlXdin_7_re, -- sfix16_En13
twdlXdin_7_im => twdlXdin_7_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_5_re => dout_5_re_2, -- sfix16_En13
dout_5_im => dout_5_im_2, -- sfix16_En13
dout_6_re => dout_6_re_2, -- sfix16_En13
dout_6_im => dout_6_im_2, -- sfix16_En13
dout_5_vld => dout_5_vld_1
);
u_SDNF1_3_7 : RADIX22FFT_SDNF1_3_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_6_re => twdlXdin_6_re, -- sfix16_En13
twdlXdin_6_im => twdlXdin_6_im, -- sfix16_En13
twdlXdin_8_re => twdlXdin_8_re, -- sfix16_En13
twdlXdin_8_im => twdlXdin_8_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_7_re => dout_7_re_2, -- sfix16_En13
dout_7_im => dout_7_im_2, -- sfix16_En13
dout_8_re => dout_8_re_2, -- sfix16_En13
dout_8_im => dout_8_im_2, -- sfix16_En13
dout_7_vld => dout_7_vld_1
);
u_SDNF2_4_5 : RADIX22FFT_SDNF2_4_block1
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_5 => rotate_5_1, -- ufix1
dout_5_re => dout_5_re_2, -- sfix16_En13
dout_5_im => dout_5_im_2, -- sfix16_En13
dout_7_re => dout_7_re_2, -- sfix16_En13
dout_7_im => dout_7_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_5_re_1 => dataOut_im_tmp(4), -- sfix16_En13
dout_5_im_1 => dataOut_re_tmp(4), -- sfix16_En13
dout_6_re => dataOut_im_tmp(5), -- sfix16_En13
dout_6_im => dataOut_re_tmp(5), -- sfix16_En13
dout_4_vld => dout_4_vld_2
);
u_SDNF2_4_7 : RADIX22FFT_SDNF2_4_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_7 => rotate_7_1, -- ufix1
dout_6_re => dout_6_re_2, -- sfix16_En13
dout_6_im => dout_6_im_2, -- sfix16_En13
dout_8_re => dout_8_re_2, -- sfix16_En13
dout_8_im => dout_8_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_7_re => dataOut_im_tmp(6), -- sfix16_En13
dout_7_im => dataOut_re_tmp(6), -- sfix16_En13
dout_8_re_1 => dataOut_im_tmp(7), -- sfix16_En13
dout_8_im_1 => dataOut_re_tmp(7), -- sfix16_En13
dout_4_vld => dout_4_vld_3
);
u_SDNF2_2_9 : RADIX22FFT_SDNF2_2_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_9 => rotate_9_1, -- ufix1
dout_2_re => dout_2_re, -- sfix16_En13
dout_2_im => dout_2_im, -- sfix16_En13
dout_10_re => dout_10_re, -- sfix16_En13
dout_10_im => dout_10_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_9_re => dout_9_re_1, -- sfix16_En13
dout_9_im => dout_9_im_1, -- sfix16_En13
dout_10_re_1 => dout_10_re_1, -- sfix16_En13
dout_10_im_1 => dout_10_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_4
);
u_SDNF2_2_11 : RADIX22FFT_SDNF2_2_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_11 => rotate_11, -- ufix1
dout_4_re => dout_4_re, -- sfix16_En13
dout_4_im => dout_4_im, -- sfix16_En13
dout_12_re => dout_12_re, -- sfix16_En13
dout_12_im => dout_12_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_11_re => dout_11_re_1, -- sfix16_En13
dout_11_im => dout_11_im_1, -- sfix16_En13
dout_12_re_1 => dout_12_re_1, -- sfix16_En13
dout_12_im_1 => dout_12_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_5
);
u_twdlROM_3_10 : TWDLROM_3_10
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_10_re => twdl_3_10_re, -- sfix16_En14
twdl_3_10_im => twdl_3_10_im, -- sfix16_En14
twdl_3_10_vld => twdl_3_10_vld
);
u_TWDLMULT_SDNF1_3_9 : TWDLMULT_SDNF1_3_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_9_re => dout_9_re_1, -- sfix16_En13
dout_9_im => dout_9_im_1, -- sfix16_En13
dout_11_re => dout_11_re_1, -- sfix16_En13
dout_11_im => dout_11_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_9_re => std_logic_vector(twdl_3_9_re), -- sfix16_En14
twdl_3_9_im => std_logic_vector(twdl_3_9_im), -- sfix16_En14
twdl_3_10_re => twdl_3_10_re, -- sfix16_En14
twdl_3_10_im => twdl_3_10_im, -- sfix16_En14
twdl_3_10_vld => twdl_3_10_vld,
softReset => softReset,
twdlXdin_9_re => twdlXdin_9_re, -- sfix16_En13
twdlXdin_9_im => twdlXdin_9_im, -- sfix16_En13
twdlXdin_10_re => twdlXdin_10_re, -- sfix16_En13
twdlXdin_10_im => twdlXdin_10_im, -- sfix16_En13
twdlXdin_9_vld => twdlXdin_9_vld
);
u_SDNF2_2_13 : RADIX22FFT_SDNF2_2_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_13 => rotate_13, -- ufix1
dout_6_re => dout_6_re, -- sfix16_En13
dout_6_im => dout_6_im, -- sfix16_En13
dout_14_re => dout_14_re, -- sfix16_En13
dout_14_im => dout_14_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_13_re => dout_13_re_1, -- sfix16_En13
dout_13_im => dout_13_im_1, -- sfix16_En13
dout_14_re_1 => dout_14_re_1, -- sfix16_En13
dout_14_im_1 => dout_14_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_6
);
u_SDNF2_2_15 : RADIX22FFT_SDNF2_2_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_15 => rotate_15, -- ufix1
dout_8_re => dout_8_re, -- sfix16_En13
dout_8_im => dout_8_im, -- sfix16_En13
dout_16_re => dout_16_re, -- sfix16_En13
dout_16_im => dout_16_im, -- sfix16_En13
dout_1_vld => dout_1_vld,
softReset => softReset,
dout_15_re => dout_15_re_1, -- sfix16_En13
dout_15_im => dout_15_im_1, -- sfix16_En13
dout_16_re_1 => dout_16_re_1, -- sfix16_En13
dout_16_im_1 => dout_16_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld_7
);
u_twdlROM_3_11 : TWDLROM_3_11
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_11_re => twdl_3_11_re, -- sfix16_En14
twdl_3_11_im => twdl_3_11_im, -- sfix16_En14
twdl_3_11_vld => twdl_3_11_vld
);
u_twdlROM_3_12 : TWDLROM_3_12
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_12_re => twdl_3_12_re, -- sfix16_En14
twdl_3_12_im => twdl_3_12_im, -- sfix16_En14
twdl_3_12_vld => twdl_3_12_vld
);
u_TWDLMULT_SDNF1_3_11 : TWDLMULT_SDNF1_3_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_13_re => dout_13_re_1, -- sfix16_En13
dout_13_im => dout_13_im_1, -- sfix16_En13
dout_15_re => dout_15_re_1, -- sfix16_En13
dout_15_im => dout_15_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_11_re => twdl_3_11_re, -- sfix16_En14
twdl_3_11_im => twdl_3_11_im, -- sfix16_En14
twdl_3_12_re => twdl_3_12_re, -- sfix16_En14
twdl_3_12_im => twdl_3_12_im, -- sfix16_En14
twdl_3_12_vld => twdl_3_12_vld,
softReset => softReset,
twdlXdin_11_re => twdlXdin_11_re, -- sfix16_En13
twdlXdin_11_im => twdlXdin_11_im, -- sfix16_En13
twdlXdin_12_re => twdlXdin_12_re, -- sfix16_En13
twdlXdin_12_im => twdlXdin_12_im, -- sfix16_En13
twdlXdin_11_vld => twdlXdin_11_vld
);
u_SDNF1_3_9 : RADIX22FFT_SDNF1_3_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_9_re => twdlXdin_9_re, -- sfix16_En13
twdlXdin_9_im => twdlXdin_9_im, -- sfix16_En13
twdlXdin_11_re => twdlXdin_11_re, -- sfix16_En13
twdlXdin_11_im => twdlXdin_11_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_9_re => dout_9_re_2, -- sfix16_En13
dout_9_im => dout_9_im_2, -- sfix16_En13
dout_10_re => dout_10_re_2, -- sfix16_En13
dout_10_im => dout_10_im_2, -- sfix16_En13
dout_9_vld => dout_9_vld_1
);
u_SDNF1_3_11 : RADIX22FFT_SDNF1_3_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_10_re => twdlXdin_10_re, -- sfix16_En13
twdlXdin_10_im => twdlXdin_10_im, -- sfix16_En13
twdlXdin_12_re => twdlXdin_12_re, -- sfix16_En13
twdlXdin_12_im => twdlXdin_12_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_11_re => dout_11_re_2, -- sfix16_En13
dout_11_im => dout_11_im_2, -- sfix16_En13
dout_12_re => dout_12_re_2, -- sfix16_En13
dout_12_im => dout_12_im_2, -- sfix16_En13
dout_11_vld => dout_11_vld_1
);
u_SDNF2_4_9 : RADIX22FFT_SDNF2_4_block3
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_9 => rotate_9, -- ufix1
dout_9_re => dout_9_re_2, -- sfix16_En13
dout_9_im => dout_9_im_2, -- sfix16_En13
dout_11_re => dout_11_re_2, -- sfix16_En13
dout_11_im => dout_11_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_9_re_1 => dataOut_im_tmp(8), -- sfix16_En13
dout_9_im_1 => dataOut_re_tmp(8), -- sfix16_En13
dout_10_re => dataOut_im_tmp(9), -- sfix16_En13
dout_10_im => dataOut_re_tmp(9), -- sfix16_En13
dout_4_vld => dout_4_vld_4
);
u_SDNF2_4_11 : RADIX22FFT_SDNF2_4_block4
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_11 => rotate_11_1, -- ufix1
dout_10_re => dout_10_re_2, -- sfix16_En13
dout_10_im => dout_10_im_2, -- sfix16_En13
dout_12_re => dout_12_re_2, -- sfix16_En13
dout_12_im => dout_12_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_11_re => dataOut_im_tmp(10), -- sfix16_En13
dout_11_im => dataOut_re_tmp(10), -- sfix16_En13
dout_12_re_1 => dataOut_im_tmp(11), -- sfix16_En13
dout_12_im_1 => dataOut_re_tmp(11), -- sfix16_En13
dout_4_vld => dout_4_vld_5
);
u_twdlROM_3_14 : TWDLROM_3_14
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_14_re => twdl_3_14_re, -- sfix16_En14
twdl_3_14_im => twdl_3_14_im, -- sfix16_En14
twdl_3_14_vld => twdl_3_14_vld
);
u_TWDLMULT_SDNF1_3_13 : TWDLMULT_SDNF1_3_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_10_re => dout_10_re_1, -- sfix16_En13
dout_10_im => dout_10_im_1, -- sfix16_En13
dout_12_re => dout_12_re_1, -- sfix16_En13
dout_12_im => dout_12_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_13_re => std_logic_vector(twdl_3_13_re), -- sfix16_En14
twdl_3_13_im => std_logic_vector(twdl_3_13_im), -- sfix16_En14
twdl_3_14_re => twdl_3_14_re, -- sfix16_En14
twdl_3_14_im => twdl_3_14_im, -- sfix16_En14
twdl_3_14_vld => twdl_3_14_vld,
softReset => softReset,
twdlXdin_13_re => twdlXdin_13_re, -- sfix16_En13
twdlXdin_13_im => twdlXdin_13_im, -- sfix16_En13
twdlXdin_14_re => twdlXdin_14_re, -- sfix16_En13
twdlXdin_14_im => twdlXdin_14_im, -- sfix16_En13
twdlXdin_13_vld => twdlXdin_13_vld
);
u_twdlROM_3_15 : TWDLROM_3_15
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_15_re => twdl_3_15_re, -- sfix16_En14
twdl_3_15_im => twdl_3_15_im, -- sfix16_En14
twdl_3_15_vld => twdl_3_15_vld
);
u_twdlROM_3_16 : TWDLROM_3_16
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_2_vld => dout_2_vld,
softReset => softReset,
twdl_3_16_re => twdl_3_16_re, -- sfix16_En14
twdl_3_16_im => twdl_3_16_im, -- sfix16_En14
twdl_3_16_vld => twdl_3_16_vld
);
u_TWDLMULT_SDNF1_3_15 : TWDLMULT_SDNF1_3_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dout_14_re => dout_14_re_1, -- sfix16_En13
dout_14_im => dout_14_im_1, -- sfix16_En13
dout_16_re => dout_16_re_1, -- sfix16_En13
dout_16_im => dout_16_im_1, -- sfix16_En13
dout_2_vld => dout_2_vld,
twdl_3_15_re => twdl_3_15_re, -- sfix16_En14
twdl_3_15_im => twdl_3_15_im, -- sfix16_En14
twdl_3_16_re => twdl_3_16_re, -- sfix16_En14
twdl_3_16_im => twdl_3_16_im, -- sfix16_En14
twdl_3_16_vld => twdl_3_16_vld,
softReset => softReset,
twdlXdin_15_re => twdlXdin_15_re, -- sfix16_En13
twdlXdin_15_im => twdlXdin_15_im, -- sfix16_En13
twdlXdin_16_re => twdlXdin_16_re, -- sfix16_En13
twdlXdin_16_im => twdlXdin_16_im, -- sfix16_En13
twdlXdin_15_vld => twdlXdin_15_vld
);
u_SDNF1_3_13 : RADIX22FFT_SDNF1_3_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_13_re => twdlXdin_13_re, -- sfix16_En13
twdlXdin_13_im => twdlXdin_13_im, -- sfix16_En13
twdlXdin_15_re => twdlXdin_15_re, -- sfix16_En13
twdlXdin_15_im => twdlXdin_15_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_13_re => dout_13_re_2, -- sfix16_En13
dout_13_im => dout_13_im_2, -- sfix16_En13
dout_14_re => dout_14_re_2, -- sfix16_En13
dout_14_im => dout_14_im_2, -- sfix16_En13
dout_13_vld => dout_13_vld_1
);
u_SDNF1_3_15 : RADIX22FFT_SDNF1_3_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
twdlXdin_14_re => twdlXdin_14_re, -- sfix16_En13
twdlXdin_14_im => twdlXdin_14_im, -- sfix16_En13
twdlXdin_16_re => twdlXdin_16_re, -- sfix16_En13
twdlXdin_16_im => twdlXdin_16_im, -- sfix16_En13
twdlXdin_1_vld => twdlXdin_1_vld_1,
softReset => softReset,
dout_15_re => dout_15_re_2, -- sfix16_En13
dout_15_im => dout_15_im_2, -- sfix16_En13
dout_16_re => dout_16_re_2, -- sfix16_En13
dout_16_im => dout_16_im_2, -- sfix16_En13
dout_15_vld => dout_15_vld_1
);
u_SDNF2_4_13 : RADIX22FFT_SDNF2_4_block5
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_13 => rotate_13_1, -- ufix1
dout_13_re => dout_13_re_2, -- sfix16_En13
dout_13_im => dout_13_im_2, -- sfix16_En13
dout_15_re => dout_15_re_2, -- sfix16_En13
dout_15_im => dout_15_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_13_re_1 => dataOut_im_tmp(12), -- sfix16_En13
dout_13_im_1 => dataOut_re_tmp(12), -- sfix16_En13
dout_14_re => dataOut_im_tmp(13), -- sfix16_En13
dout_14_im => dataOut_re_tmp(13), -- sfix16_En13
dout_4_vld => dout_4_vld_6
);
u_SDNF2_4_15 : RADIX22FFT_SDNF2_4_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
rotate_15 => rotate_15_1, -- ufix1
dout_14_re => dout_14_re_2, -- sfix16_En13
dout_14_im => dout_14_im_2, -- sfix16_En13
dout_16_re => dout_16_re_2, -- sfix16_En13
dout_16_im => dout_16_im_2, -- sfix16_En13
dout_1_vld => dout_1_vld_1,
softReset => softReset,
dout_15_re => dataOut_im_tmp(14), -- sfix16_En13
dout_15_im => dataOut_re_tmp(14), -- sfix16_En13
dout_16_re_1 => dataOut_im_tmp(15), -- sfix16_En13
dout_16_im_1 => dataOut_re_tmp(15), -- sfix16_En13
dout_4_vld => dout_4_vld_7
);
rotate_1 <= '0';
rotate_1_1 <= '0';
twdlXdin_1_vld <= '1' WHEN validIn /= '0' ELSE
'0';
softReset <= '0';
rotate_3 <= '0';
twdl_3_1_re <= to_signed(16#4000#, 16);
twdl_3_1_im <= to_signed(16#0000#, 16);
rotate_5 <= '0';
rotate_7 <= '0';
rotate_3_1 <= '1';
rotate_5_1 <= '0';
twdl_3_5_re <= to_signed(16#4000#, 16);
twdl_3_5_im <= to_signed(16#0000#, 16);
rotate_7_1 <= '1';
rotate_9 <= '0';
rotate_9_1 <= '1';
rotate_11 <= '1';
twdl_3_9_re <= to_signed(16#4000#, 16);
twdl_3_9_im <= to_signed(16#0000#, 16);
rotate_13 <= '1';
rotate_15 <= '1';
rotate_11_1 <= '1';
rotate_13_1 <= '0';
twdl_3_13_re <= to_signed(16#4000#, 16);
twdl_3_13_im <= to_signed(16#0000#, 16);
rotate_15_1 <= '1';
dataOut_re <= dataOut_re_tmp;
dataOut_im <= dataOut_im_tmp;
validOut <= dout_4_vld;
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_4_block2.vhd
|
1
|
7169
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_4_block2.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block2
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_6_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_6_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block2 IS
-- Signals
SIGNAL dout_6_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_6_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_8_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_8_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_7_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_7_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_8_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_8_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_6_re_signed <= signed(dout_6_re);
dout_6_im_signed <= signed(dout_6_im);
dout_8_re_signed <= signed(dout_8_re);
dout_8_im_signed <= signed(dout_8_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_6_re_signed, dout_6_im_signed,
dout_8_re_signed, dout_8_im_signed, dout_1_vld, rotate_7)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_7 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_6_re_signed, 18) + resize(dout_8_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_6_re_signed, 18) - resize(dout_8_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_6_im_signed, 18) + resize(dout_8_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_6_im_signed, 18) - resize(dout_8_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_6_re_signed, 18) + resize(dout_8_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_6_re_signed, 18) - resize(dout_8_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_6_im_signed, 18) + resize(dout_8_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_6_im_signed, 18) - resize(dout_8_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_7_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_7_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_8_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_8_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_7_re <= std_logic_vector(dout_7_re_tmp);
dout_7_im <= std_logic_vector(dout_7_im_tmp);
dout_8_re_1 <= std_logic_vector(dout_8_re_tmp);
dout_8_im_1 <= std_logic_vector(dout_8_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block1.vhd
|
1
|
7106
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block1.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block1
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_5 : IN std_logic; -- ufix1
dout_5_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_5_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_13_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_13_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_5_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_6_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_6_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block1 IS
-- Signals
SIGNAL dout_5_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_5_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_13_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_13_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_5_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_5_im_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_6_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_6_im_tmp : signed(18 DOWNTO 0); -- sfix19
BEGIN
dout_5_re_signed <= signed(dout_5_re);
din1_re <= resize(dout_5_re_signed, 19);
dout_5_im_signed <= signed(dout_5_im);
din1_im <= resize(dout_5_im_signed, 19);
dout_13_re_signed <= signed(dout_13_re);
din2_re <= resize(dout_13_re_signed, 19);
dout_13_im_signed <= signed(dout_13_im);
din2_im <= resize(dout_13_im_signed, 19);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_5)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_5 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) - resize(din2_re, 20);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) - resize(din2_im, 20);
END IF;
dout_5_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(18 DOWNTO 0);
dout_5_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(18 DOWNTO 0);
dout_6_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(18 DOWNTO 0);
dout_6_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(18 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
dout_5_re_1 <= std_logic_vector(dout_5_re_tmp);
dout_5_im_1 <= std_logic_vector(dout_5_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
FFT_HDL/transceiver_hdl/OFDM_transmitter/RADIX22FFT_SDNF2_4_block2.vhd
|
1
|
8562
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_4_block2.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block2
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block2 IS
-- Signals
SIGNAL dout_6_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_6_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_7_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_7_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
dout_6_re_signed <= signed(dout_6_re);
dout_6_im_signed <= signed(dout_6_im);
dout_8_re_signed <= signed(dout_8_re);
dout_8_im_signed <= signed(dout_8_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_6_re_signed, dout_6_im_signed,
dout_8_re_signed, dout_8_im_signed, dout_1_vld, rotate_7)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE add_cast_3 : signed(16 DOWNTO 0);
VARIABLE add_cast_4 : signed(16 DOWNTO 0);
VARIABLE add_cast_5 : signed(16 DOWNTO 0);
VARIABLE add_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_3 : signed(16 DOWNTO 0);
VARIABLE sub_cast_4 : signed(16 DOWNTO 0);
VARIABLE sub_cast_5 : signed(16 DOWNTO 0);
VARIABLE sub_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_7 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(dout_6_re_signed, 17);
add_cast_2 := resize(dout_8_im_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(dout_6_re_signed, 17);
sub_cast_2 := resize(dout_8_im_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(dout_6_im_signed, 17);
add_cast_6 := resize(dout_8_re_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(dout_6_im_signed, 17);
sub_cast_6 := resize(dout_8_re_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(dout_6_re_signed, 17);
add_cast_0 := resize(dout_8_re_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(dout_6_re_signed, 17);
sub_cast_0 := resize(dout_8_re_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(dout_6_im_signed, 17);
add_cast_4 := resize(dout_8_im_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(dout_6_im_signed, 17);
sub_cast_4 := resize(dout_8_im_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_7_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_7_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_8_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_8_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_7_re <= std_logic_vector(dout_7_re_tmp);
dout_7_im <= std_logic_vector(dout_7_im_tmp);
dout_8_re_1 <= std_logic_vector(dout_8_re_tmp);
dout_8_im_1 <= std_logic_vector(dout_8_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_1_block2.vhd
|
1
|
6717
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_1_block2.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block2
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_12_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_12_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_7_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block2 IS
-- Signals
SIGNAL twdlXdin_4_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_4_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_12_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_12_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_7_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_7_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_8_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_8_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_4_re_signed <= signed(twdlXdin_4_re);
twdlXdin_4_im_signed <= signed(twdlXdin_4_im);
twdlXdin_12_re_signed <= signed(twdlXdin_12_re);
twdlXdin_12_im_signed <= signed(twdlXdin_12_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_4_re_signed,
twdlXdin_4_im_signed, twdlXdin_12_re_signed, twdlXdin_12_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_4_re_signed, 18) + resize(twdlXdin_12_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_4_re_signed, 18) - resize(twdlXdin_12_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_4_im_signed, 18) + resize(twdlXdin_12_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_4_im_signed, 18) - resize(twdlXdin_12_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_7_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_7_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_8_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_8_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_7_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_7_re <= std_logic_vector(dout_7_re_tmp);
dout_7_im <= std_logic_vector(dout_7_im_tmp);
dout_8_re <= std_logic_vector(dout_8_re_tmp);
dout_8_im <= std_logic_vector(dout_8_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block6.vhd
|
1
|
6375
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block6.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block6
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_14_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_14_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_16_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_16_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_15_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_16_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_16_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_15_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block6 IS
-- Signals
SIGNAL twdlXdin_14_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_14_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_16_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_16_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_15_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_15_im_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_16_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_16_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
twdlXdin_14_re_signed <= signed(twdlXdin_14_re);
twdlXdin_14_im_signed <= signed(twdlXdin_14_im);
twdlXdin_16_re_signed <= signed(twdlXdin_16_re);
twdlXdin_16_im_signed <= signed(twdlXdin_16_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_14_re_signed,
twdlXdin_14_im_signed, twdlXdin_16_re_signed, twdlXdin_16_im_signed,
twdlXdin_1_vld)
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_14_re_signed, 21) + resize(twdlXdin_16_re_signed, 21);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_14_re_signed, 21) - resize(twdlXdin_16_re_signed, 21);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_14_im_signed, 21) + resize(twdlXdin_16_im_signed, 21);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_14_im_signed, 21) - resize(twdlXdin_16_im_signed, 21);
END IF;
dout_15_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(19 DOWNTO 0);
dout_15_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(19 DOWNTO 0);
dout_16_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(19 DOWNTO 0);
dout_16_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(19 DOWNTO 0);
dout_15_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re <= std_logic_vector(dout_16_re_tmp);
dout_16_im <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block5.vhd
|
1
|
14747
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block5.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block5
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_10_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_10_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_12_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_12_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : IN std_logic;
twdl_3_13_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_13_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_13_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_13_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_14_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_14_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_13_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block5;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block5 IS
-- Component Declarations
COMPONENT Complex3Multiply_block8
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din2_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
di2_vld_dly3 : IN std_logic;
twdl_3_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_14_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_14_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block8
USE ENTITY work.Complex3Multiply_block8(rtl);
-- Signals
SIGNAL dout_10_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly4 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly5 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly6 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly7 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly8 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly9 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_10_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly4 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly5 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly6 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly7 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly8 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly9 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_12_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_12_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_14_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_14_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
BEGIN
u_MUL3_2 : Complex3Multiply_block8
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix17
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix17
di2_vld_dly3 => di2_vld_dly3,
twdl_3_14_re => twdl_3_14_re, -- sfix17_En15
twdl_3_14_im => twdl_3_14_im, -- sfix17_En15
softReset => softReset,
twdlXdin_14_re => twdlXdin_14_re_tmp, -- sfix17
twdlXdin_14_im => twdlXdin_14_im_tmp, -- sfix17
twdlXdin2_vld => twdlXdin_13_vld
);
dout_10_re_signed <= signed(dout_10_re);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly1 <= dout_10_re_signed;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly4 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly4 <= din1_re_dly3;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly5 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly5 <= din1_re_dly4;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly6 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly6 <= din1_re_dly5;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly7 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly7 <= din1_re_dly6;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly8 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly8 <= din1_re_dly7;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly9 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly9 <= din1_re_dly8;
END IF;
END IF;
END PROCESS intdelay_8_process;
twdlXdin_13_re <= std_logic_vector(din1_re_dly9);
dout_10_im_signed <= signed(dout_10_im);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly1 <= dout_10_im_signed;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly4 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly4 <= din1_im_dly3;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly5 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly5 <= din1_im_dly4;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly6 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly6 <= din1_im_dly5;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly7 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly7 <= din1_im_dly6;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly8 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly8 <= din1_im_dly7;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly9 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly9 <= din1_im_dly8;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_13_im <= std_logic_vector(din1_im_dly9);
dout_12_re_signed <= signed(dout_12_re);
intdelay_18_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly1 <= dout_12_re_signed;
END IF;
END IF;
END PROCESS intdelay_18_process;
intdelay_19_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_19_process;
dout_12_im_signed <= signed(dout_12_im);
intdelay_20_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly1 <= dout_12_im_signed;
END IF;
END IF;
END PROCESS intdelay_20_process;
intdelay_21_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_21_process;
intdelay_22_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_22_process;
intdelay_23_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_23_process;
intdelay_24_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_24_process;
intdelay_25_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_25_process;
intdelay_26_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_26_process;
twdlXdin_14_re <= twdlXdin_14_re_tmp;
twdlXdin_14_im <= twdlXdin_14_im_tmp;
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block3.vhd
|
1
|
7112
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_2_block3.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block3
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_9 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_2_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_10_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_10_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_9_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_10_re_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_10_im_1 : OUT std_logic_vector(18 DOWNTO 0); -- sfix19
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block3;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block3 IS
-- Signals
SIGNAL dout_2_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_2_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din1_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_10_re_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_re : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_10_im_signed : signed(17 DOWNTO 0); -- sfix18
SIGNAL din2_im : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_9_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_9_im_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_10_re_tmp : signed(18 DOWNTO 0); -- sfix19
SIGNAL dout_10_im_tmp : signed(18 DOWNTO 0); -- sfix19
BEGIN
dout_2_re_signed <= signed(dout_2_re);
din1_re <= resize(dout_2_re_signed, 19);
dout_2_im_signed <= signed(dout_2_im);
din1_im <= resize(dout_2_im_signed, 19);
dout_10_re_signed <= signed(dout_10_re);
din2_re <= resize(dout_10_re_signed, 19);
dout_10_im_signed <= signed(dout_10_im);
din2_im <= resize(dout_10_im_signed, 19);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_9)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_9 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) - resize(din2_re, 20);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 20) + resize(din2_re, 20);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 20) - resize(din2_re, 20);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 20) + resize(din2_im, 20);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 20) - resize(din2_im, 20);
END IF;
dout_9_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(18 DOWNTO 0);
dout_9_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(18 DOWNTO 0);
dout_10_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(18 DOWNTO 0);
dout_10_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(18 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_9_re <= std_logic_vector(dout_9_re_tmp);
dout_9_im <= std_logic_vector(dout_9_im_tmp);
dout_10_re_1 <= std_logic_vector(dout_10_re_tmp);
dout_10_im_1 <= std_logic_vector(dout_10_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/Complex3Multiply_block3.vhd
|
1
|
12224
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/Complex3Multiply_block3.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block3
-- Source Path: hdl_ofdm_tx/ifft/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din1_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_vld_dly3 : IN std_logic;
twdl_3_7_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_7_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_7_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_7_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block3;
ARCHITECTURE rtl OF Complex3Multiply_block3 IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din_re_reg : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly3_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din_im_reg : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL adder_add_cast : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL adder_add_cast_1 : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL din_sum : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL twdl_3_7_re_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_re_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_7_im_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_im_reg : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL adder_add_cast_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL adder_add_cast_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL twdl_sum : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(18 DOWNTO 0) := to_signed(16#00000#, 19); -- sfix19
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(18 DOWNTO 0) := to_signed(16#00000#, 19); -- sfix19
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(19 DOWNTO 0) := to_signed(16#00000#, 20); -- sfix20
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(36 DOWNTO 0) := to_signed(0, 37); -- sfix37
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(15 DOWNTO 0) := to_signed(16#0000#, 16); -- sfix16
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(15 DOWNTO 0) := to_signed(16#0000#, 16); -- sfix16
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(16 DOWNTO 0) := to_signed(16#00000#, 17); -- sfix17
SIGNAL prodOfRe : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35_En27
SIGNAL prodOfIm : signed(34 DOWNTO 0) := to_signed(0, 35); -- sfix35_En27
SIGNAL prodOfSum : signed(36 DOWNTO 0) := to_signed(0, 37); -- sfix37_En27
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_multRes_re_reg1 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_re_reg2 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_im_reg : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_tmpResult_reg_next : signed(36 DOWNTO 0); -- sfix37_En27
SIGNAL Complex3Add_multRes_re_reg1_next : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_multRes_re_reg2_next : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_multRes_im_reg_next : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL Complex3Add_sub_cast : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_sub_cast_1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_sub_cast_2 : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL Complex3Add_sub_cast_3 : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL Complex3Add_add_cast : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_add_cast_1 : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL Complex3Add_add_temp : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL multResFP_re : signed(35 DOWNTO 0); -- sfix36_En27
SIGNAL multResFP_im : signed(37 DOWNTO 0); -- sfix38_En27
SIGNAL twdlXdin_7_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_7_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 19);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 19);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
adder_add_cast <= resize(din_re_reg, 20);
adder_add_cast_1 <= resize(din_im_reg, 20);
din_sum <= adder_add_cast + adder_add_cast_1;
twdl_3_7_re_signed <= signed(twdl_3_7_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#0000#, 16);
ELSE
twdl_re_reg <= twdl_3_7_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_7_im_signed <= signed(twdl_3_7_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#0000#, 16);
ELSE
twdl_im_reg <= twdl_3_7_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast_2 <= resize(twdl_re_reg, 17);
adder_add_cast_3 <= resize(twdl_im_reg, 17);
twdl_sum <= adder_add_cast_2 + adder_add_cast_3;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 37);
Complex3Add_tmpResult_reg <= to_signed(0, 37);
Complex3Add_multRes_re_reg1 <= to_signed(0, 36);
Complex3Add_multRes_re_reg2 <= to_signed(0, 36);
Complex3Add_multRes_im_reg <= to_signed(0, 38);
Complex3Add_prod_vld_reg1 <= '0';
twdlXdin1_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prodOfSum_reg <= prodOfSum;
twdlXdin1_vld <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1 <= prod_vld;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
Complex3Add_sub_cast <= resize(prodOfRe, 36);
Complex3Add_sub_cast_1 <= resize(prodOfIm, 36);
Complex3Add_multRes_re_reg1_next <= Complex3Add_sub_cast - Complex3Add_sub_cast_1;
Complex3Add_sub_cast_2 <= resize(Complex3Add_prodOfSum_reg, 38);
Complex3Add_sub_cast_3 <= resize(Complex3Add_tmpResult_reg, 38);
Complex3Add_multRes_im_reg_next <= Complex3Add_sub_cast_2 - Complex3Add_sub_cast_3;
Complex3Add_add_cast <= resize(prodOfRe, 36);
Complex3Add_add_cast_1 <= resize(prodOfIm, 36);
Complex3Add_add_temp <= Complex3Add_add_cast + Complex3Add_add_cast_1;
Complex3Add_tmpResult_reg_next <= resize(Complex3Add_add_temp, 37);
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin_7_re_tmp <= multResFP_re(32 DOWNTO 14);
twdlXdin_7_re <= std_logic_vector(twdlXdin_7_re_tmp);
twdlXdin_7_im_tmp <= multResFP_im(32 DOWNTO 14);
twdlXdin_7_im <= std_logic_vector(twdlXdin_7_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
FFT_HDL/transceiver_hdl/OFDM_transmitter/RADIX22FFT_SDNF1_3_block6.vhd
|
1
|
7485
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_3_block6.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block6
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block6 IS
-- Signals
SIGNAL twdlXdin_14_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_14_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_16_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_16_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_15_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_15_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
twdlXdin_14_re_signed <= signed(twdlXdin_14_re);
twdlXdin_14_im_signed <= signed(twdlXdin_14_im);
twdlXdin_16_re_signed <= signed(twdlXdin_16_re);
twdlXdin_16_im_signed <= signed(twdlXdin_16_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_14_re_signed,
twdlXdin_14_im_signed, twdlXdin_16_re_signed, twdlXdin_16_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_14_re_signed, 17);
add_cast_0 := resize(twdlXdin_16_re_signed, 17);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_14_re_signed, 17);
sub_cast_0 := resize(twdlXdin_16_re_signed, 17);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_14_im_signed, 17);
add_cast_2 := resize(twdlXdin_16_im_signed, 17);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_14_im_signed, 17);
sub_cast_2 := resize(twdlXdin_16_im_signed, 17);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_15_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_15_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_16_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_16_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_15_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re <= std_logic_vector(dout_16_re_tmp);
dout_16_im <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_3_block6.vhd
|
1
|
7126
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_3_block6.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block6
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF1_3_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_12_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_12_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_16_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_16_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_15_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_16_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_16_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_15_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block6 IS
-- Signals
SIGNAL twdlXdin_12_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_12_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_16_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_16_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_15_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_15_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_16_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_16_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
BEGIN
twdlXdin_12_re_signed <= signed(twdlXdin_12_re);
twdlXdin_12_im_signed <= signed(twdlXdin_12_im);
twdlXdin_16_re_signed <= signed(twdlXdin_16_re);
twdlXdin_16_im_signed <= signed(twdlXdin_16_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_12_re_signed,
twdlXdin_12_im_signed, twdlXdin_16_re_signed, twdlXdin_16_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(19 DOWNTO 0);
VARIABLE add_cast_0 : signed(19 DOWNTO 0);
VARIABLE sub_cast : signed(19 DOWNTO 0);
VARIABLE sub_cast_0 : signed(19 DOWNTO 0);
VARIABLE add_cast_1 : signed(19 DOWNTO 0);
VARIABLE add_cast_2 : signed(19 DOWNTO 0);
VARIABLE sub_cast_1 : signed(19 DOWNTO 0);
VARIABLE sub_cast_2 : signed(19 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_12_re_signed, 20);
add_cast_0 := resize(twdlXdin_16_re_signed, 20);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_12_re_signed, 20);
sub_cast_0 := resize(twdlXdin_16_re_signed, 20);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_12_im_signed, 20);
add_cast_2 := resize(twdlXdin_16_im_signed, 20);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_12_im_signed, 20);
sub_cast_2 := resize(twdlXdin_16_im_signed, 20);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
dout_15_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(18 DOWNTO 0);
dout_15_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(18 DOWNTO 0);
dout_16_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(18 DOWNTO 0);
dout_16_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(18 DOWNTO 0);
dout_15_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re <= std_logic_vector(dout_16_re_tmp);
dout_16_im <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3_block6.vhd
|
1
|
6740
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3_block6.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block6
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_15_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block6 IS
-- Signals
SIGNAL twdlXdin_14_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_14_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_16_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_16_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_15_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_15_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_16_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_16_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_14_re_signed <= signed(twdlXdin_14_re);
twdlXdin_14_im_signed <= signed(twdlXdin_14_im);
twdlXdin_16_re_signed <= signed(twdlXdin_16_re);
twdlXdin_16_im_signed <= signed(twdlXdin_16_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_14_re_signed,
twdlXdin_14_im_signed, twdlXdin_16_re_signed, twdlXdin_16_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_14_re_signed, 18) + resize(twdlXdin_16_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_14_re_signed, 18) - resize(twdlXdin_16_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_14_im_signed, 18) + resize(twdlXdin_16_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_14_im_signed, 18) - resize(twdlXdin_16_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_15_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_15_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_16_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_16_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_15_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re <= std_logic_vector(dout_16_re_tmp);
dout_16_im <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3_block5.vhd
|
1
|
6740
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3_block5.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block5
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_13_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_13_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_13_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block5;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block5 IS
-- Signals
SIGNAL twdlXdin_13_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_13_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_15_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_15_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_13_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_13_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_13_re_signed <= signed(twdlXdin_13_re);
twdlXdin_13_im_signed <= signed(twdlXdin_13_im);
twdlXdin_15_re_signed <= signed(twdlXdin_15_re);
twdlXdin_15_im_signed <= signed(twdlXdin_15_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_13_re_signed,
twdlXdin_13_im_signed, twdlXdin_15_re_signed, twdlXdin_15_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_13_re_signed, 18) + resize(twdlXdin_15_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_13_re_signed, 18) - resize(twdlXdin_15_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_13_im_signed, 18) + resize(twdlXdin_15_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_13_im_signed, 18) - resize(twdlXdin_15_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_13_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_13_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_14_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_14_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_13_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_13_re <= std_logic_vector(dout_13_re_tmp);
dout_13_im <= std_logic_vector(dout_13_im_tmp);
dout_14_re <= std_logic_vector(dout_14_re_tmp);
dout_14_im <= std_logic_vector(dout_14_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_2_block2.vhd
|
1
|
7183
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_2_block2.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block2
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_7 : IN std_logic; -- ufix1
dout_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_7_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block2 IS
-- Signals
SIGNAL dout_7_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_7_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_15_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_15_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_7_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_7_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_8_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_8_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_7_re_signed <= signed(dout_7_re);
dout_7_im_signed <= signed(dout_7_im);
dout_15_re_signed <= signed(dout_15_re);
dout_15_im_signed <= signed(dout_15_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_7_re_signed, dout_7_im_signed,
dout_15_re_signed, dout_15_im_signed, dout_1_vld, rotate_7)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_7 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_7_re_signed, 18) + resize(dout_15_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_7_re_signed, 18) - resize(dout_15_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_7_im_signed, 18) + resize(dout_15_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_7_im_signed, 18) - resize(dout_15_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_7_re_signed, 18) + resize(dout_15_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_7_re_signed, 18) - resize(dout_15_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_7_im_signed, 18) + resize(dout_15_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_7_im_signed, 18) - resize(dout_15_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_7_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_7_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_8_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_8_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_8_re <= std_logic_vector(dout_8_re_tmp);
dout_8_im <= std_logic_vector(dout_8_im_tmp);
dout_7_re_1 <= std_logic_vector(dout_7_re_tmp);
dout_7_im_1 <= std_logic_vector(dout_7_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/Complex3Multiply_block7.vhd
|
1
|
12399
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/Complex3Multiply_block7.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block7
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block7 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din2_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
di2_vld_dly3 : IN std_logic;
twdl_3_12_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_12_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_12_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_12_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin2_vld : OUT std_logic
);
END Complex3Multiply_block7;
ARCHITECTURE rtl OF Complex3Multiply_block7 IS
-- Signals
SIGNAL din2_re_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_sum : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdl_3_12_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_12_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfIm : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfSum : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_re_reg1 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_re_reg2 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_im_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_tmpResult_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL multResFP_re : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL multResFP_im : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL twdlXdin_12_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_12_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
din2_re_dly3_signed <= signed(din2_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSE
din_re_reg <= din2_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din2_im_dly3_signed <= signed(din2_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSE
din_im_reg <= din2_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 18) + resize(din_im_reg, 18);
twdl_3_12_re_signed <= signed(twdl_3_12_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_12_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_12_im_signed <= signed(twdl_3_12_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_12_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= di2_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 36);
Complex3Add_tmpResult_reg <= to_signed(0, 36);
Complex3Add_multRes_re_reg1 <= to_signed(0, 35);
Complex3Add_multRes_re_reg2 <= to_signed(0, 35);
Complex3Add_multRes_im_reg <= to_signed(0, 37);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(34 DOWNTO 0);
VARIABLE sub_cast_0 : signed(34 DOWNTO 0);
VARIABLE sub_cast_1 : signed(36 DOWNTO 0);
VARIABLE sub_cast_2 : signed(36 DOWNTO 0);
VARIABLE add_cast : signed(34 DOWNTO 0);
VARIABLE add_cast_0 : signed(34 DOWNTO 0);
VARIABLE add_temp : signed(34 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 35);
sub_cast_0 := resize(prodOfIm, 35);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 37);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 37);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 35);
add_cast_0 := resize(prodOfIm, 35);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 36);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin2_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_12_re_tmp <= multResFP_re(31 DOWNTO 15);
twdlXdin_12_re <= std_logic_vector(twdlXdin_12_re_tmp);
twdlXdin_12_im_tmp <= multResFP_im(31 DOWNTO 15);
twdlXdin_12_im <= std_logic_vector(twdlXdin_12_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block6.vhd
|
1
|
13312
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block6.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block6
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_14_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_14_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : IN std_logic;
twdl_3_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block6;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block6 IS
-- Component Declarations
COMPONENT Complex3Multiply_block9
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_vld_dly3 : IN std_logic;
twdl_3_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT Complex3Multiply_block10
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din2_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
di2_vld_dly3 : IN std_logic;
twdl_3_16_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block9
USE ENTITY work.Complex3Multiply_block9(rtl);
FOR ALL : Complex3Multiply_block10
USE ENTITY work.Complex3Multiply_block10(rtl);
-- Signals
SIGNAL dout_14_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_14_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_vld_dly1 : std_logic;
SIGNAL din1_vld_dly2 : std_logic;
SIGNAL din1_vld_dly3 : std_logic;
SIGNAL twdlXdin_15_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_15_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin1_vld : std_logic;
SIGNAL dout_16_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_16_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_16_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_16_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
BEGIN
u_MUL3_1 : Complex3Multiply_block9
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din1_re_dly3 => std_logic_vector(din1_re_dly3), -- sfix17
din1_im_dly3 => std_logic_vector(din1_im_dly3), -- sfix17
din1_vld_dly3 => din1_vld_dly3,
twdl_3_15_re => twdl_3_15_re, -- sfix17_En15
twdl_3_15_im => twdl_3_15_im, -- sfix17_En15
softReset => softReset,
twdlXdin_15_re => twdlXdin_15_re_tmp, -- sfix17
twdlXdin_15_im => twdlXdin_15_im_tmp, -- sfix17
twdlXdin1_vld => twdlXdin1_vld
);
u_MUL3_2 : Complex3Multiply_block10
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix17
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix17
di2_vld_dly3 => di2_vld_dly3,
twdl_3_16_re => twdl_3_16_re, -- sfix17_En15
twdl_3_16_im => twdl_3_16_im, -- sfix17_En15
softReset => softReset,
twdlXdin_16_re => twdlXdin_16_re_tmp, -- sfix17
twdlXdin_16_im => twdlXdin_16_im_tmp, -- sfix17
twdlXdin2_vld => twdlXdin_15_vld
);
dout_14_re_signed <= signed(dout_14_re);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly1 <= dout_14_re_signed;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
dout_14_im_signed <= signed(dout_14_im);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly1 <= dout_14_im_signed;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly2 <= din1_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly3 <= din1_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_8_process;
dout_16_re_signed <= signed(dout_16_re);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly1 <= dout_16_re_signed;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
dout_16_im_signed <= signed(dout_16_im);
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly1 <= dout_16_im_signed;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_15_re <= twdlXdin_15_re_tmp;
twdlXdin_15_im <= twdlXdin_15_im_tmp;
twdlXdin_16_re <= twdlXdin_16_re_tmp;
twdlXdin_16_im <= twdlXdin_16_im_tmp;
END rtl;
|
gpl-3.0
|
AloriumTechnology/XLR8Float
|
extras/rtl/xlr8_float/xlr8_float_mult2/dspba_library_package.vhd
|
2
|
7089
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_sync_reg is
generic (
width1 : natural := 8;
width2 : natural := 8;
depth : natural := 2;
init_value : std_logic_vector;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end component;
component dspba_mux2 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_mux3 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_mux4 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xin3 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intadd_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intadd_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intaddsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
component dspba_intaddsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/ifft_16_bit.vhd
|
1
|
3848
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/ifft_16_bit.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 0.2
-- Target subsystem base rate: 0.2
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 0.2
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- Out1_re ce_out 0.2
-- Out1_im ce_out 0.2
-- Out2 ce_out 0.2
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: ifft_16_bit
-- Source Path: ifft_16_bit
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ifft_16_bit_pkg.ALL;
ENTITY ifft_16_bit IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
In1 : IN vector_of_std_logic_vector16(0 TO 15); -- uint16 [16]
ce_out : OUT std_logic;
Out1_re : OUT vector_of_std_logic_vector17(0 TO 15); -- sfix17 [16]
Out1_im : OUT vector_of_std_logic_vector17(0 TO 15); -- sfix17 [16]
Out2 : OUT std_logic
);
END ifft_16_bit;
ARCHITECTURE rtl OF ifft_16_bit IS
-- Component Declarations
COMPONENT IFFT_HDL_Optimized
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dataIn : IN vector_of_std_logic_vector16(0 TO 15); -- uint16 [16]
validIn : IN std_logic;
dataOut_re : OUT vector_of_std_logic_vector17(0 TO 15); -- sfix17 [16]
dataOut_im : OUT vector_of_std_logic_vector17(0 TO 15); -- sfix17 [16]
validOut : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : IFFT_HDL_Optimized
USE ENTITY work.IFFT_HDL_Optimized(rtl);
-- Signals
SIGNAL Constant_out1 : std_logic;
SIGNAL IFFT_HDL_Optimized_out1_re : vector_of_std_logic_vector17(0 TO 15); -- ufix17 [16]
SIGNAL IFFT_HDL_Optimized_out1_im : vector_of_std_logic_vector17(0 TO 15); -- ufix17 [16]
SIGNAL IFFT_HDL_Optimized_out2 : std_logic;
BEGIN
u_IFFT_HDL_Optimized : IFFT_HDL_Optimized
PORT MAP( clk => clk,
reset => reset,
enb => clk_enable,
dataIn => In1, -- uint16 [16]
validIn => Constant_out1,
dataOut_re => IFFT_HDL_Optimized_out1_re, -- sfix17 [16]
dataOut_im => IFFT_HDL_Optimized_out1_im, -- sfix17 [16]
validOut => IFFT_HDL_Optimized_out2
);
Constant_out1 <= '1';
ce_out <= clk_enable;
Out1_re <= IFFT_HDL_Optimized_out1_re;
Out1_im <= IFFT_HDL_Optimized_out1_im;
Out2 <= IFFT_HDL_Optimized_out2;
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/fft_16_bit/Complex3Multiply_block.vhd
|
1
|
12380
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_im_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_vld_dly3 : IN std_logic;
twdl_3_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_3_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block;
ARCHITECTURE rtl OF Complex3Multiply_block IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_sum : signed(20 DOWNTO 0); -- sfix21
SIGNAL twdl_3_3_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_3_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(20 DOWNTO 0); -- sfix21
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfIm : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfSum : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_multRes_re_reg1 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_re_reg2 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_im_reg : signed(39 DOWNTO 0); -- sfix40
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_tmpResult_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL multResFP_re : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL multResFP_im : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL twdlXdin_3_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_3_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 21) + resize(din_im_reg, 21);
twdl_3_3_re_signed <= signed(twdl_3_3_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_3_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_3_im_signed <= signed(twdl_3_3_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_3_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 39);
Complex3Add_tmpResult_reg <= to_signed(0, 39);
Complex3Add_multRes_re_reg1 <= to_signed(0, 38);
Complex3Add_multRes_re_reg2 <= to_signed(0, 38);
Complex3Add_multRes_im_reg <= to_signed(0, 40);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(37 DOWNTO 0);
VARIABLE sub_cast_0 : signed(37 DOWNTO 0);
VARIABLE sub_cast_1 : signed(39 DOWNTO 0);
VARIABLE sub_cast_2 : signed(39 DOWNTO 0);
VARIABLE add_cast : signed(37 DOWNTO 0);
VARIABLE add_cast_0 : signed(37 DOWNTO 0);
VARIABLE add_temp : signed(37 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 38);
sub_cast_0 := resize(prodOfIm, 38);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 40);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 40);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 38);
add_cast_0 := resize(prodOfIm, 38);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 39);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin1_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_3_re_tmp <= multResFP_re(34 DOWNTO 15);
twdlXdin_3_re <= std_logic_vector(twdlXdin_3_re_tmp);
twdlXdin_3_im_tmp <= multResFP_im(34 DOWNTO 15);
twdlXdin_3_im <= std_logic_vector(twdlXdin_3_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
FFT_HDL/transceiver_hdl/OFDM_transmitter/RADIX22FFT_SDNF1_1_block2.vhd
|
1
|
7462
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_1_block2.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block2
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_8_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_7_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block2 IS
-- Signals
SIGNAL twdlXdin_4_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_4_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_12_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_12_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_7_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_7_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_8_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
twdlXdin_4_re_signed <= signed(twdlXdin_4_re);
twdlXdin_4_im_signed <= signed(twdlXdin_4_im);
twdlXdin_12_re_signed <= signed(twdlXdin_12_re);
twdlXdin_12_im_signed <= signed(twdlXdin_12_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_4_re_signed,
twdlXdin_4_im_signed, twdlXdin_12_re_signed, twdlXdin_12_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_4_re_signed, 17);
add_cast_0 := resize(twdlXdin_12_re_signed, 17);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_4_re_signed, 17);
sub_cast_0 := resize(twdlXdin_12_re_signed, 17);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_4_im_signed, 17);
add_cast_2 := resize(twdlXdin_12_im_signed, 17);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_4_im_signed, 17);
sub_cast_2 := resize(twdlXdin_12_im_signed, 17);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_7_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_7_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_8_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_8_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_7_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_7_re <= std_logic_vector(dout_7_re_tmp);
dout_7_im <= std_logic_vector(dout_7_im_tmp);
dout_8_re <= std_logic_vector(dout_8_re_tmp);
dout_8_im <= std_logic_vector(dout_8_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4_block1.vhd
|
1
|
8533
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4_block1.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block1
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF2_4_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_5 : IN std_logic; -- ufix1
dout_5_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_5_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_13_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_13_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_5_im_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_6_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_6_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block1 IS
-- Signals
SIGNAL dout_5_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_5_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_13_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_13_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL dout_5_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_5_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_6_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_6_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
BEGIN
dout_5_re_signed <= signed(dout_5_re);
din1_re <= resize(dout_5_re_signed, 20);
dout_5_im_signed <= signed(dout_5_im);
din1_im <= resize(dout_5_im_signed, 20);
dout_13_re_signed <= signed(dout_13_re);
din2_re <= resize(dout_13_re_signed, 20);
dout_13_im_signed <= signed(dout_13_im);
din2_im <= resize(dout_13_im_signed, 20);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 21);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_5)
VARIABLE add_cast : signed(20 DOWNTO 0);
VARIABLE add_cast_0 : signed(20 DOWNTO 0);
VARIABLE add_cast_1 : signed(20 DOWNTO 0);
VARIABLE add_cast_2 : signed(20 DOWNTO 0);
VARIABLE sub_cast : signed(20 DOWNTO 0);
VARIABLE sub_cast_0 : signed(20 DOWNTO 0);
VARIABLE sub_cast_1 : signed(20 DOWNTO 0);
VARIABLE sub_cast_2 : signed(20 DOWNTO 0);
VARIABLE add_cast_3 : signed(20 DOWNTO 0);
VARIABLE add_cast_4 : signed(20 DOWNTO 0);
VARIABLE add_cast_5 : signed(20 DOWNTO 0);
VARIABLE add_cast_6 : signed(20 DOWNTO 0);
VARIABLE sub_cast_3 : signed(20 DOWNTO 0);
VARIABLE sub_cast_4 : signed(20 DOWNTO 0);
VARIABLE sub_cast_5 : signed(20 DOWNTO 0);
VARIABLE sub_cast_6 : signed(20 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_5 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(din1_re, 21);
add_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(din1_re, 21);
sub_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(din1_im, 21);
add_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(din1_im, 21);
sub_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(din1_re, 21);
add_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(din1_re, 21);
sub_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(din1_im, 21);
add_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(din1_im, 21);
sub_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
dout_5_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(19 DOWNTO 0);
dout_5_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(19 DOWNTO 0);
dout_6_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(19 DOWNTO 0);
dout_6_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(19 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
dout_5_re_1 <= std_logic_vector(dout_5_re_tmp);
dout_5_im_1 <= std_logic_vector(dout_5_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4_block6.vhd
|
1
|
8547
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4_block6.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block6
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF2_4_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_8_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_8_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_16_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_16_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_15_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_16_re_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_16_im_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block6 IS
-- Signals
SIGNAL dout_8_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_8_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_16_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_16_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL dout_15_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_15_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_16_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_16_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
BEGIN
dout_8_re_signed <= signed(dout_8_re);
din1_re <= resize(dout_8_re_signed, 20);
dout_8_im_signed <= signed(dout_8_im);
din1_im <= resize(dout_8_im_signed, 20);
dout_16_re_signed <= signed(dout_16_re);
din2_re <= resize(dout_16_re_signed, 20);
dout_16_im_signed <= signed(dout_16_im);
din2_im <= resize(dout_16_im_signed, 20);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 21);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_15)
VARIABLE add_cast : signed(20 DOWNTO 0);
VARIABLE add_cast_0 : signed(20 DOWNTO 0);
VARIABLE add_cast_1 : signed(20 DOWNTO 0);
VARIABLE add_cast_2 : signed(20 DOWNTO 0);
VARIABLE sub_cast : signed(20 DOWNTO 0);
VARIABLE sub_cast_0 : signed(20 DOWNTO 0);
VARIABLE sub_cast_1 : signed(20 DOWNTO 0);
VARIABLE sub_cast_2 : signed(20 DOWNTO 0);
VARIABLE add_cast_3 : signed(20 DOWNTO 0);
VARIABLE add_cast_4 : signed(20 DOWNTO 0);
VARIABLE add_cast_5 : signed(20 DOWNTO 0);
VARIABLE add_cast_6 : signed(20 DOWNTO 0);
VARIABLE sub_cast_3 : signed(20 DOWNTO 0);
VARIABLE sub_cast_4 : signed(20 DOWNTO 0);
VARIABLE sub_cast_5 : signed(20 DOWNTO 0);
VARIABLE sub_cast_6 : signed(20 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_15 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(din1_re, 21);
add_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(din1_re, 21);
sub_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(din1_im, 21);
add_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(din1_im, 21);
sub_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(din1_re, 21);
add_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(din1_re, 21);
sub_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(din1_im, 21);
add_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(din1_im, 21);
sub_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
dout_15_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(19 DOWNTO 0);
dout_15_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(19 DOWNTO 0);
dout_16_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(19 DOWNTO 0);
dout_16_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(19 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re_1 <= std_logic_vector(dout_16_re_tmp);
dout_16_im_1 <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
gpl-3.0
|
freecores/dds_synthesizer
|
vhdl/sine_lut/sine_lut_8_x_10.vhd
|
2
|
3241
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 8;
constant AMPL_WIDTH : integer := 10;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_cos_hdl.vhd
|
1
|
21260
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_cos_hdl.vhd
-- Created: 2018-02-27 13:25:15
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: hdl_modulator_cos_hdl
-- Source Path: hdl_modulator/wave_generator/sincos hdl/cos_hdl
-- Hierarchy Level: 4
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_modulator_hdl_modulator_pkg.ALL;
ENTITY hdl_modulator_cos_hdl IS
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
x : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END hdl_modulator_cos_hdl;
ARCHITECTURE rtl OF hdl_modulator_cos_hdl IS
-- Constants
CONSTANT nc : vector_of_signed16(0 TO 511) :=
(to_signed(16#0000#, 16), to_signed(16#0032#, 16), to_signed(16#0065#, 16), to_signed(16#0097#, 16),
to_signed(16#00C9#, 16), to_signed(16#00FC#, 16), to_signed(16#012E#, 16), to_signed(16#0161#, 16),
to_signed(16#0193#, 16), to_signed(16#01C5#, 16), to_signed(16#01F8#, 16), to_signed(16#022A#, 16),
to_signed(16#025C#, 16), to_signed(16#028F#, 16), to_signed(16#02C1#, 16), to_signed(16#02F3#, 16),
to_signed(16#0325#, 16), to_signed(16#0358#, 16), to_signed(16#038A#, 16), to_signed(16#03BC#, 16),
to_signed(16#03EF#, 16), to_signed(16#0421#, 16), to_signed(16#0453#, 16), to_signed(16#0485#, 16),
to_signed(16#04B8#, 16), to_signed(16#04EA#, 16), to_signed(16#051C#, 16), to_signed(16#054E#, 16),
to_signed(16#0580#, 16), to_signed(16#05B3#, 16), to_signed(16#05E5#, 16), to_signed(16#0617#, 16),
to_signed(16#0649#, 16), to_signed(16#067B#, 16), to_signed(16#06AD#, 16), to_signed(16#06DF#, 16),
to_signed(16#0711#, 16), to_signed(16#0743#, 16), to_signed(16#0775#, 16), to_signed(16#07A7#, 16),
to_signed(16#07D9#, 16), to_signed(16#080B#, 16), to_signed(16#083D#, 16), to_signed(16#086F#, 16),
to_signed(16#08A1#, 16), to_signed(16#08D3#, 16), to_signed(16#0905#, 16), to_signed(16#0937#, 16),
to_signed(16#0969#, 16), to_signed(16#099B#, 16), to_signed(16#09CC#, 16), to_signed(16#09FE#, 16),
to_signed(16#0A30#, 16), to_signed(16#0A61#, 16), to_signed(16#0A93#, 16), to_signed(16#0AC5#, 16),
to_signed(16#0AF6#, 16), to_signed(16#0B28#, 16), to_signed(16#0B5A#, 16), to_signed(16#0B8B#, 16),
to_signed(16#0BBD#, 16), to_signed(16#0BEE#, 16), to_signed(16#0C20#, 16), to_signed(16#0C51#, 16),
to_signed(16#0C83#, 16), to_signed(16#0CB4#, 16), to_signed(16#0CE5#, 16), to_signed(16#0D17#, 16),
to_signed(16#0D48#, 16), to_signed(16#0D79#, 16), to_signed(16#0DAA#, 16), to_signed(16#0DDC#, 16),
to_signed(16#0E0D#, 16), to_signed(16#0E3E#, 16), to_signed(16#0E6F#, 16), to_signed(16#0EA0#, 16),
to_signed(16#0ED1#, 16), to_signed(16#0F02#, 16), to_signed(16#0F33#, 16), to_signed(16#0F64#, 16),
to_signed(16#0F95#, 16), to_signed(16#0FC5#, 16), to_signed(16#0FF6#, 16), to_signed(16#1027#, 16),
to_signed(16#1058#, 16), to_signed(16#1088#, 16), to_signed(16#10B9#, 16), to_signed(16#10EA#, 16),
to_signed(16#111A#, 16), to_signed(16#114B#, 16), to_signed(16#117B#, 16), to_signed(16#11AC#, 16),
to_signed(16#11DC#, 16), to_signed(16#120C#, 16), to_signed(16#123D#, 16), to_signed(16#126D#, 16),
to_signed(16#129D#, 16), to_signed(16#12CD#, 16), to_signed(16#12FD#, 16), to_signed(16#132D#, 16),
to_signed(16#135D#, 16), to_signed(16#138D#, 16), to_signed(16#13BD#, 16), to_signed(16#13ED#, 16),
to_signed(16#141D#, 16), to_signed(16#144D#, 16), to_signed(16#147D#, 16), to_signed(16#14AC#, 16),
to_signed(16#14DC#, 16), to_signed(16#150C#, 16), to_signed(16#153B#, 16), to_signed(16#156B#, 16),
to_signed(16#159A#, 16), to_signed(16#15C9#, 16), to_signed(16#15F9#, 16), to_signed(16#1628#, 16),
to_signed(16#1657#, 16), to_signed(16#1686#, 16), to_signed(16#16B5#, 16), to_signed(16#16E5#, 16),
to_signed(16#1714#, 16), to_signed(16#1742#, 16), to_signed(16#1771#, 16), to_signed(16#17A0#, 16),
to_signed(16#17CF#, 16), to_signed(16#17FE#, 16), to_signed(16#182C#, 16), to_signed(16#185B#, 16),
to_signed(16#188A#, 16), to_signed(16#18B8#, 16), to_signed(16#18E6#, 16), to_signed(16#1915#, 16),
to_signed(16#1943#, 16), to_signed(16#1971#, 16), to_signed(16#19A0#, 16), to_signed(16#19CE#, 16),
to_signed(16#19FC#, 16), to_signed(16#1A2A#, 16), to_signed(16#1A58#, 16), to_signed(16#1A85#, 16),
to_signed(16#1AB3#, 16), to_signed(16#1AE1#, 16), to_signed(16#1B0F#, 16), to_signed(16#1B3C#, 16),
to_signed(16#1B6A#, 16), to_signed(16#1B97#, 16), to_signed(16#1BC5#, 16), to_signed(16#1BF2#, 16),
to_signed(16#1C1F#, 16), to_signed(16#1C4D#, 16), to_signed(16#1C7A#, 16), to_signed(16#1CA7#, 16),
to_signed(16#1CD4#, 16), to_signed(16#1D01#, 16), to_signed(16#1D2E#, 16), to_signed(16#1D5A#, 16),
to_signed(16#1D87#, 16), to_signed(16#1DB4#, 16), to_signed(16#1DE0#, 16), to_signed(16#1E0D#, 16),
to_signed(16#1E39#, 16), to_signed(16#1E66#, 16), to_signed(16#1E92#, 16), to_signed(16#1EBE#, 16),
to_signed(16#1EEA#, 16), to_signed(16#1F16#, 16), to_signed(16#1F42#, 16), to_signed(16#1F6E#, 16),
to_signed(16#1F9A#, 16), to_signed(16#1FC6#, 16), to_signed(16#1FF1#, 16), to_signed(16#201D#, 16),
to_signed(16#2049#, 16), to_signed(16#2074#, 16), to_signed(16#209F#, 16), to_signed(16#20CB#, 16),
to_signed(16#20F6#, 16), to_signed(16#2121#, 16), to_signed(16#214C#, 16), to_signed(16#2177#, 16),
to_signed(16#21A2#, 16), to_signed(16#21CD#, 16), to_signed(16#21F7#, 16), to_signed(16#2222#, 16),
to_signed(16#224D#, 16), to_signed(16#2277#, 16), to_signed(16#22A2#, 16), to_signed(16#22CC#, 16),
to_signed(16#22F6#, 16), to_signed(16#2320#, 16), to_signed(16#234A#, 16), to_signed(16#2374#, 16),
to_signed(16#239E#, 16), to_signed(16#23C8#, 16), to_signed(16#23F2#, 16), to_signed(16#241B#, 16),
to_signed(16#2445#, 16), to_signed(16#246E#, 16), to_signed(16#2498#, 16), to_signed(16#24C1#, 16),
to_signed(16#24EA#, 16), to_signed(16#2513#, 16), to_signed(16#253C#, 16), to_signed(16#2565#, 16),
to_signed(16#258E#, 16), to_signed(16#25B7#, 16), to_signed(16#25DF#, 16), to_signed(16#2608#, 16),
to_signed(16#2630#, 16), to_signed(16#2659#, 16), to_signed(16#2681#, 16), to_signed(16#26A9#, 16),
to_signed(16#26D1#, 16), to_signed(16#26F9#, 16), to_signed(16#2721#, 16), to_signed(16#2749#, 16),
to_signed(16#2771#, 16), to_signed(16#2798#, 16), to_signed(16#27C0#, 16), to_signed(16#27E7#, 16),
to_signed(16#280F#, 16), to_signed(16#2836#, 16), to_signed(16#285D#, 16), to_signed(16#2884#, 16),
to_signed(16#28AB#, 16), to_signed(16#28D2#, 16), to_signed(16#28F9#, 16), to_signed(16#291F#, 16),
to_signed(16#2946#, 16), to_signed(16#296C#, 16), to_signed(16#2992#, 16), to_signed(16#29B9#, 16),
to_signed(16#29DF#, 16), to_signed(16#2A05#, 16), to_signed(16#2A2B#, 16), to_signed(16#2A51#, 16),
to_signed(16#2A76#, 16), to_signed(16#2A9C#, 16), to_signed(16#2AC2#, 16), to_signed(16#2AE7#, 16),
to_signed(16#2B0C#, 16), to_signed(16#2B32#, 16), to_signed(16#2B57#, 16), to_signed(16#2B7C#, 16),
to_signed(16#2BA1#, 16), to_signed(16#2BC5#, 16), to_signed(16#2BEA#, 16), to_signed(16#2C0F#, 16),
to_signed(16#2C33#, 16), to_signed(16#2C57#, 16), to_signed(16#2C7C#, 16), to_signed(16#2CA0#, 16),
to_signed(16#2CC4#, 16), to_signed(16#2CE8#, 16), to_signed(16#2D0C#, 16), to_signed(16#2D2F#, 16),
to_signed(16#2D53#, 16), to_signed(16#2D77#, 16), to_signed(16#2D9A#, 16), to_signed(16#2DBD#, 16),
to_signed(16#2DE0#, 16), to_signed(16#2E03#, 16), to_signed(16#2E26#, 16), to_signed(16#2E49#, 16),
to_signed(16#2E6C#, 16), to_signed(16#2E8F#, 16), to_signed(16#2EB1#, 16), to_signed(16#2ED3#, 16),
to_signed(16#2EF6#, 16), to_signed(16#2F18#, 16), to_signed(16#2F3A#, 16), to_signed(16#2F5C#, 16),
to_signed(16#2F7E#, 16), to_signed(16#2F9F#, 16), to_signed(16#2FC1#, 16), to_signed(16#2FE2#, 16),
to_signed(16#3004#, 16), to_signed(16#3025#, 16), to_signed(16#3046#, 16), to_signed(16#3067#, 16),
to_signed(16#3088#, 16), to_signed(16#30A9#, 16), to_signed(16#30CA#, 16), to_signed(16#30EA#, 16),
to_signed(16#310A#, 16), to_signed(16#312B#, 16), to_signed(16#314B#, 16), to_signed(16#316B#, 16),
to_signed(16#318B#, 16), to_signed(16#31AB#, 16), to_signed(16#31CA#, 16), to_signed(16#31EA#, 16),
to_signed(16#320A#, 16), to_signed(16#3229#, 16), to_signed(16#3248#, 16), to_signed(16#3267#, 16),
to_signed(16#3286#, 16), to_signed(16#32A5#, 16), to_signed(16#32C4#, 16), to_signed(16#32E2#, 16),
to_signed(16#3301#, 16), to_signed(16#331F#, 16), to_signed(16#333D#, 16), to_signed(16#335C#, 16),
to_signed(16#337A#, 16), to_signed(16#3397#, 16), to_signed(16#33B5#, 16), to_signed(16#33D3#, 16),
to_signed(16#33F0#, 16), to_signed(16#340E#, 16), to_signed(16#342B#, 16), to_signed(16#3448#, 16),
to_signed(16#3465#, 16), to_signed(16#3482#, 16), to_signed(16#349F#, 16), to_signed(16#34BB#, 16),
to_signed(16#34D8#, 16), to_signed(16#34F4#, 16), to_signed(16#3510#, 16), to_signed(16#352C#, 16),
to_signed(16#3548#, 16), to_signed(16#3564#, 16), to_signed(16#3580#, 16), to_signed(16#359B#, 16),
to_signed(16#35B7#, 16), to_signed(16#35D2#, 16), to_signed(16#35ED#, 16), to_signed(16#3608#, 16),
to_signed(16#3623#, 16), to_signed(16#363E#, 16), to_signed(16#3659#, 16), to_signed(16#3673#, 16),
to_signed(16#368E#, 16), to_signed(16#36A8#, 16), to_signed(16#36C2#, 16), to_signed(16#36DC#, 16),
to_signed(16#36F6#, 16), to_signed(16#3710#, 16), to_signed(16#3729#, 16), to_signed(16#3743#, 16),
to_signed(16#375C#, 16), to_signed(16#3775#, 16), to_signed(16#378E#, 16), to_signed(16#37A7#, 16),
to_signed(16#37C0#, 16), to_signed(16#37D9#, 16), to_signed(16#37F1#, 16), to_signed(16#380A#, 16),
to_signed(16#3822#, 16), to_signed(16#383A#, 16), to_signed(16#3852#, 16), to_signed(16#386A#, 16),
to_signed(16#3882#, 16), to_signed(16#3899#, 16), to_signed(16#38B1#, 16), to_signed(16#38C8#, 16),
to_signed(16#38DF#, 16), to_signed(16#38F6#, 16), to_signed(16#390D#, 16), to_signed(16#3924#, 16),
to_signed(16#393A#, 16), to_signed(16#3951#, 16), to_signed(16#3967#, 16), to_signed(16#397D#, 16),
to_signed(16#3994#, 16), to_signed(16#39A9#, 16), to_signed(16#39BF#, 16), to_signed(16#39D5#, 16),
to_signed(16#39EA#, 16), to_signed(16#3A00#, 16), to_signed(16#3A15#, 16), to_signed(16#3A2A#, 16),
to_signed(16#3A3F#, 16), to_signed(16#3A54#, 16), to_signed(16#3A68#, 16), to_signed(16#3A7D#, 16),
to_signed(16#3A91#, 16), to_signed(16#3AA6#, 16), to_signed(16#3ABA#, 16), to_signed(16#3ACE#, 16),
to_signed(16#3AE1#, 16), to_signed(16#3AF5#, 16), to_signed(16#3B09#, 16), to_signed(16#3B1C#, 16),
to_signed(16#3B2F#, 16), to_signed(16#3B42#, 16), to_signed(16#3B55#, 16), to_signed(16#3B68#, 16),
to_signed(16#3B7B#, 16), to_signed(16#3B8D#, 16), to_signed(16#3BA0#, 16), to_signed(16#3BB2#, 16),
to_signed(16#3BC4#, 16), to_signed(16#3BD6#, 16), to_signed(16#3BE8#, 16), to_signed(16#3BF9#, 16),
to_signed(16#3C0B#, 16), to_signed(16#3C1C#, 16), to_signed(16#3C2D#, 16), to_signed(16#3C3F#, 16),
to_signed(16#3C4F#, 16), to_signed(16#3C60#, 16), to_signed(16#3C71#, 16), to_signed(16#3C81#, 16),
to_signed(16#3C92#, 16), to_signed(16#3CA2#, 16), to_signed(16#3CB2#, 16), to_signed(16#3CC2#, 16),
to_signed(16#3CD2#, 16), to_signed(16#3CE1#, 16), to_signed(16#3CF1#, 16), to_signed(16#3D00#, 16),
to_signed(16#3D0F#, 16), to_signed(16#3D1E#, 16), to_signed(16#3D2D#, 16), to_signed(16#3D3C#, 16),
to_signed(16#3D4A#, 16), to_signed(16#3D59#, 16), to_signed(16#3D67#, 16), to_signed(16#3D75#, 16),
to_signed(16#3D83#, 16), to_signed(16#3D91#, 16), to_signed(16#3D9F#, 16), to_signed(16#3DAC#, 16),
to_signed(16#3DBA#, 16), to_signed(16#3DC7#, 16), to_signed(16#3DD4#, 16), to_signed(16#3DE1#, 16),
to_signed(16#3DEE#, 16), to_signed(16#3DFA#, 16), to_signed(16#3E07#, 16), to_signed(16#3E13#, 16),
to_signed(16#3E1F#, 16), to_signed(16#3E2B#, 16), to_signed(16#3E37#, 16), to_signed(16#3E43#, 16),
to_signed(16#3E4F#, 16), to_signed(16#3E5A#, 16), to_signed(16#3E65#, 16), to_signed(16#3E70#, 16),
to_signed(16#3E7B#, 16), to_signed(16#3E86#, 16), to_signed(16#3E91#, 16), to_signed(16#3E9B#, 16),
to_signed(16#3EA6#, 16), to_signed(16#3EB0#, 16), to_signed(16#3EBA#, 16), to_signed(16#3EC4#, 16),
to_signed(16#3ECE#, 16), to_signed(16#3ED7#, 16), to_signed(16#3EE1#, 16), to_signed(16#3EEA#, 16),
to_signed(16#3EF3#, 16), to_signed(16#3EFC#, 16), to_signed(16#3F05#, 16), to_signed(16#3F0E#, 16),
to_signed(16#3F16#, 16), to_signed(16#3F1F#, 16), to_signed(16#3F27#, 16), to_signed(16#3F2F#, 16),
to_signed(16#3F37#, 16), to_signed(16#3F3F#, 16), to_signed(16#3F46#, 16), to_signed(16#3F4E#, 16),
to_signed(16#3F55#, 16), to_signed(16#3F5C#, 16), to_signed(16#3F63#, 16), to_signed(16#3F6A#, 16),
to_signed(16#3F71#, 16), to_signed(16#3F78#, 16), to_signed(16#3F7E#, 16), to_signed(16#3F84#, 16),
to_signed(16#3F8A#, 16), to_signed(16#3F90#, 16), to_signed(16#3F96#, 16), to_signed(16#3F9C#, 16),
to_signed(16#3FA1#, 16), to_signed(16#3FA7#, 16), to_signed(16#3FAC#, 16), to_signed(16#3FB1#, 16),
to_signed(16#3FB6#, 16), to_signed(16#3FBA#, 16), to_signed(16#3FBF#, 16), to_signed(16#3FC3#, 16),
to_signed(16#3FC8#, 16), to_signed(16#3FCC#, 16), to_signed(16#3FD0#, 16), to_signed(16#3FD3#, 16),
to_signed(16#3FD7#, 16), to_signed(16#3FDB#, 16), to_signed(16#3FDE#, 16), to_signed(16#3FE1#, 16),
to_signed(16#3FE4#, 16), to_signed(16#3FE7#, 16), to_signed(16#3FEA#, 16), to_signed(16#3FEC#, 16),
to_signed(16#3FEF#, 16), to_signed(16#3FF1#, 16), to_signed(16#3FF3#, 16), to_signed(16#3FF5#, 16),
to_signed(16#3FF7#, 16), to_signed(16#3FF8#, 16), to_signed(16#3FFA#, 16), to_signed(16#3FFB#, 16),
to_signed(16#3FFC#, 16), to_signed(16#3FFD#, 16), to_signed(16#3FFE#, 16), to_signed(16#3FFF#, 16),
to_signed(16#3FFF#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16)); -- sfix16 [512]
-- Signals
SIGNAL In1_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL insig_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL Point25_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp25_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp25_relop1 : std_logic;
SIGNAL Point75_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL GTEp75_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL GTEp75_relop1 : std_logic;
SIGNAL alpha1st_or_4th_Quad_bool : std_logic;
SIGNAL alpha1st_or_4th_Quad_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL pow2switch_out1 : std_logic;
SIGNAL Point50_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL p75mA_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p75mA_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p75mA_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp75_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp75_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp75_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp25_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp25_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp25_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p25mA_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p25mA_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL p25mA_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL LTEp50_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp50_relop1 : std_logic;
SIGNAL QuadHandle1b_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL QuadHandle1b_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle1a_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL QuadHandle1a_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle2_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL CastU16En1_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL CastU16En3_out1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL x4_out1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL CastU16En2_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Switch_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_k : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Negate_cast : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_cast_1 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Cosine : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- (C) 2016 Mathworks, Inc
In1_signed <= signed(In1);
insig_out1 <= unsigned(In1_signed(13 DOWNTO 5));
Point25_out1 <= to_unsigned(16#4000#, 16);
LTEp25_1_cast <= insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
LTEp25_relop1 <= '1' WHEN LTEp25_1_cast <= Point25_out1 ELSE
'0';
Point75_out1 <= to_unsigned(16#C000#, 16);
GTEp75_1_cast <= insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
GTEp75_relop1 <= '1' WHEN GTEp75_1_cast >= Point75_out1 ELSE
'0';
alpha1st_or_4th_Quad_bool <= LTEp25_relop1 OR GTEp75_relop1;
alpha1st_or_4th_Quad_out1 <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & alpha1st_or_4th_Quad_bool;
pow2switch_out1 <= '0';
Point50_out1 <= to_unsigned(16#8000#, 16);
p75mA_sub_cast <= signed(resize(Point75_out1, 17));
p75mA_sub_cast_1 <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
p75mA_out1 <= p75mA_sub_cast - p75mA_sub_cast_1;
Amp75_sub_cast <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
Amp75_sub_cast_1 <= signed(resize(Point75_out1, 17));
Amp75_out1 <= Amp75_sub_cast - Amp75_sub_cast_1;
Amp25_sub_cast <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
Amp25_sub_cast_1 <= signed(resize(Point25_out1, 17));
Amp25_out1 <= Amp25_sub_cast - Amp25_sub_cast_1;
p25mA_sub_cast <= signed(resize(Point25_out1, 17));
p25mA_sub_cast_1 <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
p25mA_out1 <= p25mA_sub_cast - p25mA_sub_cast_1;
LTEp50_1_cast <= insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
LTEp50_relop1 <= '1' WHEN LTEp50_1_cast <= Point50_out1 ELSE
'0';
QuadHandle1b_out1 <= p75mA_out1 WHEN GTEp75_relop1 = '0' ELSE
Amp75_out1;
QuadHandle1b_out1_dtc <= "111111111" WHEN (QuadHandle1b_out1(16) = '0') AND (QuadHandle1b_out1(15 DOWNTO 7) = "111111111") ELSE
"000000000" WHEN QuadHandle1b_out1(16) = '1' ELSE
unsigned(QuadHandle1b_out1(15 DOWNTO 7));
QuadHandle1a_out1 <= Amp25_out1 WHEN LTEp25_relop1 = '0' ELSE
p25mA_out1;
QuadHandle1a_out1_dtc <= "111111111" WHEN (QuadHandle1a_out1(16) = '0') AND (QuadHandle1a_out1(15 DOWNTO 7) = "111111111") ELSE
"000000000" WHEN QuadHandle1a_out1(16) = '1' ELSE
unsigned(QuadHandle1a_out1(15 DOWNTO 7));
QuadHandle2_out1 <= QuadHandle1b_out1_dtc WHEN LTEp50_relop1 = '0' ELSE
QuadHandle1a_out1_dtc;
CastU16En1_out1 <= QuadHandle2_out1;
CastU16En3_out1 <= resize(CastU16En1_out1, 10);
-- equivalent to multiply
-- by 4 with saturation
x4_out1 <= CastU16En3_out1 sll 2;
-- saturation block maybe optimized away
-- if the NumDataPoints is a power of 2
CastU16En2_out1 <= "111111111" WHEN x4_out1(9) /= '0' ELSE
x4_out1(8 DOWNTO 0);
Switch_out1 <= CastU16En2_out1 WHEN pow2switch_out1 = '0' ELSE
CastU16En2_out1;
Look_Up_Table_k <= to_unsigned(16#000#, 9) WHEN Switch_out1 = to_unsigned(16#000#, 9) ELSE
to_unsigned(16#1FF#, 9) WHEN Switch_out1 = to_unsigned(16#1FF#, 9) ELSE
Switch_out1;
Look_Up_Table_out1 <= nc(to_integer(Look_Up_Table_k));
Negate_cast <= resize(Look_Up_Table_out1, 17);
Negate_cast_1 <= - (Negate_cast);
Negate_out1 <= Negate_cast_1(15 DOWNTO 0);
Cosine <= Negate_out1 WHEN alpha1st_or_4th_Quad_out1 = to_unsigned(16#00#, 8) ELSE
Look_Up_Table_out1;
x <= std_logic_vector(Cosine);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_2_block1.vhd
|
1
|
8523
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_2_block1.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block1
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF2_2_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_5 : IN std_logic; -- ufix1
dout_5_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_5_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re_1 : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_5_im_1 : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_6_re : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_6_im : OUT std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block1 IS
-- Signals
SIGNAL dout_5_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din1_re : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_5_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din1_im : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_7_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din2_re : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_7_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL din2_im : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(18 DOWNTO 0); -- sfix19
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_5_re_tmp : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_5_im_tmp : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_6_re_tmp : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL dout_6_im_tmp : signed(17 DOWNTO 0); -- sfix18_En13
BEGIN
dout_5_re_signed <= signed(dout_5_re);
din1_re <= resize(dout_5_re_signed, 18);
dout_5_im_signed <= signed(dout_5_im);
din1_im <= resize(dout_5_im_signed, 18);
dout_7_re_signed <= signed(dout_7_re);
din2_re <= resize(dout_7_re_signed, 18);
dout_7_im_signed <= signed(dout_7_im);
din2_im <= resize(dout_7_im_signed, 18);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 19);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_5)
VARIABLE add_cast : signed(18 DOWNTO 0);
VARIABLE add_cast_0 : signed(18 DOWNTO 0);
VARIABLE add_cast_1 : signed(18 DOWNTO 0);
VARIABLE add_cast_2 : signed(18 DOWNTO 0);
VARIABLE sub_cast : signed(18 DOWNTO 0);
VARIABLE sub_cast_0 : signed(18 DOWNTO 0);
VARIABLE sub_cast_1 : signed(18 DOWNTO 0);
VARIABLE sub_cast_2 : signed(18 DOWNTO 0);
VARIABLE add_cast_3 : signed(18 DOWNTO 0);
VARIABLE add_cast_4 : signed(18 DOWNTO 0);
VARIABLE add_cast_5 : signed(18 DOWNTO 0);
VARIABLE add_cast_6 : signed(18 DOWNTO 0);
VARIABLE sub_cast_3 : signed(18 DOWNTO 0);
VARIABLE sub_cast_4 : signed(18 DOWNTO 0);
VARIABLE sub_cast_5 : signed(18 DOWNTO 0);
VARIABLE sub_cast_6 : signed(18 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_5 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(din1_re, 19);
add_cast_2 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(din1_re, 19);
sub_cast_2 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(din1_im, 19);
add_cast_6 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(din1_im, 19);
sub_cast_6 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(din1_re, 19);
add_cast_0 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(din1_re, 19);
sub_cast_0 := resize(din2_re, 19);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(din1_im, 19);
add_cast_4 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(din1_im, 19);
sub_cast_4 := resize(din2_im, 19);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
dout_5_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(17 DOWNTO 0);
dout_5_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(17 DOWNTO 0);
dout_6_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(17 DOWNTO 0);
dout_6_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(17 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
dout_5_re_1 <= std_logic_vector(dout_5_re_tmp);
dout_5_im_1 <= std_logic_vector(dout_5_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/fft_16_bit/TWDLROM_3_4.vhd
|
1
|
13821
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_4.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_4
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_4_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_4_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_4_vld : OUT std_logic
);
END TWDLROM_3_4;
ARCHITECTURE rtl OF TWDLROM_3_4 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_4_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_4_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#0#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#0#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_4_re_tmp <= twdlIn_re;
twdl_3_4_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_4_re <= std_logic_vector(twdl_3_4_re_tmp);
twdl_3_4_im <= std_logic_vector(twdl_3_4_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_4_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_4_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/fft_16_bit/TWDLROM_3_16.vhd
|
1
|
13835
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/TWDLROM_3_16.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_16
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLROM_3_16
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_16 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_vld : OUT std_logic
);
END TWDLROM_3_16;
ARCHITECTURE rtl OF TWDLROM_3_16 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_16_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_16_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#3#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_16_re_tmp <= twdlIn_re;
twdl_3_16_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_16_re <= std_logic_vector(twdl_3_16_re_tmp);
twdl_3_16_im <= std_logic_vector(twdl_3_16_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_16_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_16_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
gpl-3.0
|
freecores/dds_synthesizer
|
vhdl/sine_lut/sine_lut_16_x_8.vhd
|
2
|
694839
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 8;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
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conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
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conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
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conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
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conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
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conv_std_logic_vector(105,AMPL_WIDTH),
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conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
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conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
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conv_std_logic_vector(105,AMPL_WIDTH),
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conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(106,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
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conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(121,AMPL_WIDTH),
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conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(124,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(125,AMPL_WIDTH),
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conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
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conv_std_logic_vector(126,AMPL_WIDTH),
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conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
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conv_std_logic_vector(126,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
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conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg;
|
gpl-3.0
|
jmacneal/Design-Project
|
FFT_HDL/transceiver_hdl/OFDM_transmitter/RADIX22FFT_SDNF1_3_block3.vhd
|
1
|
7468
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_3_block3.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block3
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_9_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_9_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block3;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block3 IS
-- Signals
SIGNAL twdlXdin_9_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_9_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_11_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_11_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_9_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_9_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_10_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_10_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
twdlXdin_9_re_signed <= signed(twdlXdin_9_re);
twdlXdin_9_im_signed <= signed(twdlXdin_9_im);
twdlXdin_11_re_signed <= signed(twdlXdin_11_re);
twdlXdin_11_im_signed <= signed(twdlXdin_11_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_9_re_signed,
twdlXdin_9_im_signed, twdlXdin_11_re_signed, twdlXdin_11_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_9_re_signed, 17);
add_cast_0 := resize(twdlXdin_11_re_signed, 17);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_9_re_signed, 17);
sub_cast_0 := resize(twdlXdin_11_re_signed, 17);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_9_im_signed, 17);
add_cast_2 := resize(twdlXdin_11_im_signed, 17);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_9_im_signed, 17);
sub_cast_2 := resize(twdlXdin_11_im_signed, 17);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_9_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_9_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_10_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_10_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_9_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_9_re <= std_logic_vector(dout_9_re_tmp);
dout_9_im <= std_logic_vector(dout_9_im_tmp);
dout_10_re <= std_logic_vector(dout_10_re_tmp);
dout_10_im <= std_logic_vector(dout_10_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/fft_16_bit/Complex3Multiply_block9.vhd
|
1
|
12397
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/Complex3Multiply_block9.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block9
-- Source Path: fft_16_bit/FFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block9 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_im_dly3 : IN std_logic_vector(19 DOWNTO 0); -- sfix20
din1_vld_dly3 : IN std_logic;
twdl_3_15_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_15_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_15_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_15_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block9;
ARCHITECTURE rtl OF Complex3Multiply_block9 IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im_dly3_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL din_sum : signed(20 DOWNTO 0); -- sfix21
SIGNAL twdl_3_15_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_15_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(19 DOWNTO 0); -- sfix20
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(20 DOWNTO 0); -- sfix21
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfIm : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL prodOfSum : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_multRes_re_reg1 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_re_reg2 : signed(37 DOWNTO 0); -- sfix38
SIGNAL Complex3Add_multRes_im_reg : signed(39 DOWNTO 0); -- sfix40
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(38 DOWNTO 0); -- sfix39
SIGNAL Complex3Add_tmpResult_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(38 DOWNTO 0); -- sfix39_En15
SIGNAL multResFP_re : signed(37 DOWNTO 0); -- sfix38_En15
SIGNAL multResFP_im : signed(39 DOWNTO 0); -- sfix40_En15
SIGNAL twdlXdin_15_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_15_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 20);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 20);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 21) + resize(din_im_reg, 21);
twdl_3_15_re_signed <= signed(twdl_3_15_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_15_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_15_im_signed <= signed(twdl_3_15_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_15_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 39);
Complex3Add_tmpResult_reg <= to_signed(0, 39);
Complex3Add_multRes_re_reg1 <= to_signed(0, 38);
Complex3Add_multRes_re_reg2 <= to_signed(0, 38);
Complex3Add_multRes_im_reg <= to_signed(0, 40);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(37 DOWNTO 0);
VARIABLE sub_cast_0 : signed(37 DOWNTO 0);
VARIABLE sub_cast_1 : signed(39 DOWNTO 0);
VARIABLE sub_cast_2 : signed(39 DOWNTO 0);
VARIABLE add_cast : signed(37 DOWNTO 0);
VARIABLE add_cast_0 : signed(37 DOWNTO 0);
VARIABLE add_temp : signed(37 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 38);
sub_cast_0 := resize(prodOfIm, 38);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 40);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 40);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 38);
add_cast_0 := resize(prodOfIm, 38);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 39);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin1_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_15_re_tmp <= multResFP_re(34 DOWNTO 15);
twdlXdin_15_re <= std_logic_vector(twdlXdin_15_re_tmp);
twdlXdin_15_im_tmp <= multResFP_im(34 DOWNTO 15);
twdlXdin_15_im <= std_logic_vector(twdlXdin_15_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block5.vhd
|
1
|
6375
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block5.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block5
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_13_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_13_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_15_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_15_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_13_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_14_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_14_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_13_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block5;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block5 IS
-- Signals
SIGNAL twdlXdin_13_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_13_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_15_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_15_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_13_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_13_im_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_14_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_14_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
twdlXdin_13_re_signed <= signed(twdlXdin_13_re);
twdlXdin_13_im_signed <= signed(twdlXdin_13_im);
twdlXdin_15_re_signed <= signed(twdlXdin_15_re);
twdlXdin_15_im_signed <= signed(twdlXdin_15_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_13_re_signed,
twdlXdin_13_im_signed, twdlXdin_15_re_signed, twdlXdin_15_im_signed,
twdlXdin_1_vld)
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_13_re_signed, 21) + resize(twdlXdin_15_re_signed, 21);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_13_re_signed, 21) - resize(twdlXdin_15_re_signed, 21);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_13_im_signed, 21) + resize(twdlXdin_15_im_signed, 21);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_13_im_signed, 21) - resize(twdlXdin_15_im_signed, 21);
END IF;
dout_13_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(19 DOWNTO 0);
dout_13_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(19 DOWNTO 0);
dout_14_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(19 DOWNTO 0);
dout_14_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(19 DOWNTO 0);
dout_13_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_13_re <= std_logic_vector(dout_13_re_tmp);
dout_13_im <= std_logic_vector(dout_13_im_tmp);
dout_14_re <= std_logic_vector(dout_14_re_tmp);
dout_14_im <= std_logic_vector(dout_14_im_tmp);
END rtl;
|
gpl-3.0
|
freecores/dds_synthesizer
|
vhdl/sine_lut/sine_lut_14_x_12.vhd
|
2
|
179252
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 14;
constant AMPL_WIDTH : integer := 12;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(1,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(2,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(4,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(5,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(7,AMPL_WIDTH),
conv_std_logic_vector(8,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(10,AMPL_WIDTH),
conv_std_logic_vector(11,AMPL_WIDTH),
conv_std_logic_vector(12,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(14,AMPL_WIDTH),
conv_std_logic_vector(15,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(17,AMPL_WIDTH),
conv_std_logic_vector(18,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(20,AMPL_WIDTH),
conv_std_logic_vector(21,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(23,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(24,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(26,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(27,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(29,AMPL_WIDTH),
conv_std_logic_vector(30,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(32,AMPL_WIDTH),
conv_std_logic_vector(33,AMPL_WIDTH),
conv_std_logic_vector(34,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(36,AMPL_WIDTH),
conv_std_logic_vector(37,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(39,AMPL_WIDTH),
conv_std_logic_vector(40,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(42,AMPL_WIDTH),
conv_std_logic_vector(43,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(45,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(46,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(48,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(49,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(51,AMPL_WIDTH),
conv_std_logic_vector(52,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(54,AMPL_WIDTH),
conv_std_logic_vector(55,AMPL_WIDTH),
conv_std_logic_vector(56,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(58,AMPL_WIDTH),
conv_std_logic_vector(59,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(61,AMPL_WIDTH),
conv_std_logic_vector(62,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(64,AMPL_WIDTH),
conv_std_logic_vector(65,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(67,AMPL_WIDTH),
conv_std_logic_vector(68,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(70,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(71,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(73,AMPL_WIDTH),
conv_std_logic_vector(74,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(76,AMPL_WIDTH),
conv_std_logic_vector(77,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(78,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(80,AMPL_WIDTH),
conv_std_logic_vector(81,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(83,AMPL_WIDTH),
conv_std_logic_vector(84,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(86,AMPL_WIDTH),
conv_std_logic_vector(87,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(89,AMPL_WIDTH),
conv_std_logic_vector(90,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(92,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(93,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(95,AMPL_WIDTH),
conv_std_logic_vector(96,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(98,AMPL_WIDTH),
conv_std_logic_vector(99,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(102,AMPL_WIDTH),
conv_std_logic_vector(103,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(105,AMPL_WIDTH),
conv_std_logic_vector(106,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(108,AMPL_WIDTH),
conv_std_logic_vector(109,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(111,AMPL_WIDTH),
conv_std_logic_vector(112,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(114,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(115,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(117,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(118,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(120,AMPL_WIDTH),
conv_std_logic_vector(121,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(122,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(124,AMPL_WIDTH),
conv_std_logic_vector(125,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(127,AMPL_WIDTH),
conv_std_logic_vector(128,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(130,AMPL_WIDTH),
conv_std_logic_vector(131,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(133,AMPL_WIDTH),
conv_std_logic_vector(134,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(136,AMPL_WIDTH),
conv_std_logic_vector(137,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(139,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(140,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(142,AMPL_WIDTH),
conv_std_logic_vector(143,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(144,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(146,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(147,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(149,AMPL_WIDTH),
conv_std_logic_vector(150,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(152,AMPL_WIDTH),
conv_std_logic_vector(153,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(155,AMPL_WIDTH),
conv_std_logic_vector(156,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(158,AMPL_WIDTH),
conv_std_logic_vector(159,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(161,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(162,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(164,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(165,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(167,AMPL_WIDTH),
conv_std_logic_vector(168,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(169,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(171,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(172,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(174,AMPL_WIDTH),
conv_std_logic_vector(175,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(177,AMPL_WIDTH),
conv_std_logic_vector(178,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(180,AMPL_WIDTH),
conv_std_logic_vector(181,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(183,AMPL_WIDTH),
conv_std_logic_vector(184,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(186,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(187,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(189,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(190,AMPL_WIDTH),
conv_std_logic_vector(191,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(193,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(194,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(196,AMPL_WIDTH),
conv_std_logic_vector(197,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(199,AMPL_WIDTH),
conv_std_logic_vector(200,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(202,AMPL_WIDTH),
conv_std_logic_vector(203,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(205,AMPL_WIDTH),
conv_std_logic_vector(206,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(208,AMPL_WIDTH),
conv_std_logic_vector(209,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(211,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(212,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(215,AMPL_WIDTH),
conv_std_logic_vector(216,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(218,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(219,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(221,AMPL_WIDTH),
conv_std_logic_vector(222,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(224,AMPL_WIDTH),
conv_std_logic_vector(225,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(227,AMPL_WIDTH),
conv_std_logic_vector(228,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(230,AMPL_WIDTH),
conv_std_logic_vector(231,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(233,AMPL_WIDTH),
conv_std_logic_vector(234,AMPL_WIDTH),
conv_std_logic_vector(235,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(237,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(240,AMPL_WIDTH),
conv_std_logic_vector(241,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(243,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(244,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(246,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(247,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(249,AMPL_WIDTH),
conv_std_logic_vector(250,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(252,AMPL_WIDTH),
conv_std_logic_vector(253,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(255,AMPL_WIDTH),
conv_std_logic_vector(256,AMPL_WIDTH),
conv_std_logic_vector(257,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(259,AMPL_WIDTH),
conv_std_logic_vector(260,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(262,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(265,AMPL_WIDTH),
conv_std_logic_vector(266,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(268,AMPL_WIDTH),
conv_std_logic_vector(269,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(271,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(272,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(274,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(277,AMPL_WIDTH),
conv_std_logic_vector(278,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(279,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(281,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(282,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(284,AMPL_WIDTH),
conv_std_logic_vector(285,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(287,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(290,AMPL_WIDTH),
conv_std_logic_vector(291,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(293,AMPL_WIDTH),
conv_std_logic_vector(294,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(296,AMPL_WIDTH),
conv_std_logic_vector(297,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(299,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(301,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(303,AMPL_WIDTH),
conv_std_logic_vector(304,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(306,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(307,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(309,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(310,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(312,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(315,AMPL_WIDTH),
conv_std_logic_vector(316,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(318,AMPL_WIDTH),
conv_std_logic_vector(319,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(321,AMPL_WIDTH),
conv_std_logic_vector(322,AMPL_WIDTH),
conv_std_logic_vector(323,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(326,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(328,AMPL_WIDTH),
conv_std_logic_vector(329,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(331,AMPL_WIDTH),
conv_std_logic_vector(332,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(334,AMPL_WIDTH),
conv_std_logic_vector(335,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(337,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(340,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(341,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(343,AMPL_WIDTH),
conv_std_logic_vector(344,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(345,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(347,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(348,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(351,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(353,AMPL_WIDTH),
conv_std_logic_vector(354,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(356,AMPL_WIDTH),
conv_std_logic_vector(357,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(359,AMPL_WIDTH),
conv_std_logic_vector(360,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(363,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(365,AMPL_WIDTH),
conv_std_logic_vector(366,AMPL_WIDTH),
conv_std_logic_vector(367,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(369,AMPL_WIDTH),
conv_std_logic_vector(370,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(372,AMPL_WIDTH),
conv_std_logic_vector(373,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(376,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(378,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(379,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(381,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(382,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(384,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(385,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(388,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(389,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(391,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(392,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(394,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(395,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(397,AMPL_WIDTH),
conv_std_logic_vector(398,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(400,AMPL_WIDTH),
conv_std_logic_vector(401,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(403,AMPL_WIDTH),
conv_std_logic_vector(404,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(406,AMPL_WIDTH),
conv_std_logic_vector(407,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(409,AMPL_WIDTH),
conv_std_logic_vector(410,AMPL_WIDTH),
conv_std_logic_vector(411,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(413,AMPL_WIDTH),
conv_std_logic_vector(414,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(416,AMPL_WIDTH),
conv_std_logic_vector(417,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(419,AMPL_WIDTH),
conv_std_logic_vector(420,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(422,AMPL_WIDTH),
conv_std_logic_vector(423,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(425,AMPL_WIDTH),
conv_std_logic_vector(426,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(428,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(429,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(431,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(432,AMPL_WIDTH),
conv_std_logic_vector(433,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(435,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(438,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(439,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(441,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(442,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(444,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(445,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(447,AMPL_WIDTH),
conv_std_logic_vector(448,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(450,AMPL_WIDTH),
conv_std_logic_vector(451,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(453,AMPL_WIDTH),
conv_std_logic_vector(454,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(455,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(457,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(458,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(460,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(463,AMPL_WIDTH),
conv_std_logic_vector(464,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(466,AMPL_WIDTH),
conv_std_logic_vector(467,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(469,AMPL_WIDTH),
conv_std_logic_vector(470,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(472,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(475,AMPL_WIDTH),
conv_std_logic_vector(476,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(478,AMPL_WIDTH),
conv_std_logic_vector(479,AMPL_WIDTH),
conv_std_logic_vector(480,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(482,AMPL_WIDTH),
conv_std_logic_vector(483,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(486,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(488,AMPL_WIDTH),
conv_std_logic_vector(489,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(491,AMPL_WIDTH),
conv_std_logic_vector(492,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(494,AMPL_WIDTH),
conv_std_logic_vector(495,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(498,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(500,AMPL_WIDTH),
conv_std_logic_vector(501,AMPL_WIDTH),
conv_std_logic_vector(502,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(504,AMPL_WIDTH),
conv_std_logic_vector(505,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(507,AMPL_WIDTH),
conv_std_logic_vector(508,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(511,AMPL_WIDTH),
conv_std_logic_vector(512,AMPL_WIDTH),
conv_std_logic_vector(513,AMPL_WIDTH),
conv_std_logic_vector(513,AMPL_WIDTH),
conv_std_logic_vector(514,AMPL_WIDTH),
conv_std_logic_vector(515,AMPL_WIDTH),
conv_std_logic_vector(516,AMPL_WIDTH),
conv_std_logic_vector(516,AMPL_WIDTH),
conv_std_logic_vector(517,AMPL_WIDTH),
conv_std_logic_vector(518,AMPL_WIDTH),
conv_std_logic_vector(519,AMPL_WIDTH),
conv_std_logic_vector(519,AMPL_WIDTH),
conv_std_logic_vector(520,AMPL_WIDTH),
conv_std_logic_vector(521,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(523,AMPL_WIDTH),
conv_std_logic_vector(524,AMPL_WIDTH),
conv_std_logic_vector(525,AMPL_WIDTH),
conv_std_logic_vector(526,AMPL_WIDTH),
conv_std_logic_vector(526,AMPL_WIDTH),
conv_std_logic_vector(527,AMPL_WIDTH),
conv_std_logic_vector(528,AMPL_WIDTH),
conv_std_logic_vector(529,AMPL_WIDTH),
conv_std_logic_vector(529,AMPL_WIDTH),
conv_std_logic_vector(530,AMPL_WIDTH),
conv_std_logic_vector(531,AMPL_WIDTH),
conv_std_logic_vector(532,AMPL_WIDTH),
conv_std_logic_vector(532,AMPL_WIDTH),
conv_std_logic_vector(533,AMPL_WIDTH),
conv_std_logic_vector(534,AMPL_WIDTH),
conv_std_logic_vector(535,AMPL_WIDTH),
conv_std_logic_vector(535,AMPL_WIDTH),
conv_std_logic_vector(536,AMPL_WIDTH),
conv_std_logic_vector(537,AMPL_WIDTH),
conv_std_logic_vector(538,AMPL_WIDTH),
conv_std_logic_vector(538,AMPL_WIDTH),
conv_std_logic_vector(539,AMPL_WIDTH),
conv_std_logic_vector(540,AMPL_WIDTH),
conv_std_logic_vector(541,AMPL_WIDTH),
conv_std_logic_vector(541,AMPL_WIDTH),
conv_std_logic_vector(542,AMPL_WIDTH),
conv_std_logic_vector(543,AMPL_WIDTH),
conv_std_logic_vector(544,AMPL_WIDTH),
conv_std_logic_vector(544,AMPL_WIDTH),
conv_std_logic_vector(545,AMPL_WIDTH),
conv_std_logic_vector(546,AMPL_WIDTH),
conv_std_logic_vector(547,AMPL_WIDTH),
conv_std_logic_vector(547,AMPL_WIDTH),
conv_std_logic_vector(548,AMPL_WIDTH),
conv_std_logic_vector(549,AMPL_WIDTH),
conv_std_logic_vector(550,AMPL_WIDTH),
conv_std_logic_vector(550,AMPL_WIDTH),
conv_std_logic_vector(551,AMPL_WIDTH),
conv_std_logic_vector(552,AMPL_WIDTH),
conv_std_logic_vector(553,AMPL_WIDTH),
conv_std_logic_vector(554,AMPL_WIDTH),
conv_std_logic_vector(554,AMPL_WIDTH),
conv_std_logic_vector(555,AMPL_WIDTH),
conv_std_logic_vector(556,AMPL_WIDTH),
conv_std_logic_vector(557,AMPL_WIDTH),
conv_std_logic_vector(557,AMPL_WIDTH),
conv_std_logic_vector(558,AMPL_WIDTH),
conv_std_logic_vector(559,AMPL_WIDTH),
conv_std_logic_vector(560,AMPL_WIDTH),
conv_std_logic_vector(560,AMPL_WIDTH),
conv_std_logic_vector(561,AMPL_WIDTH),
conv_std_logic_vector(562,AMPL_WIDTH),
conv_std_logic_vector(563,AMPL_WIDTH),
conv_std_logic_vector(563,AMPL_WIDTH),
conv_std_logic_vector(564,AMPL_WIDTH),
conv_std_logic_vector(565,AMPL_WIDTH),
conv_std_logic_vector(566,AMPL_WIDTH),
conv_std_logic_vector(566,AMPL_WIDTH),
conv_std_logic_vector(567,AMPL_WIDTH),
conv_std_logic_vector(568,AMPL_WIDTH),
conv_std_logic_vector(569,AMPL_WIDTH),
conv_std_logic_vector(569,AMPL_WIDTH),
conv_std_logic_vector(570,AMPL_WIDTH),
conv_std_logic_vector(571,AMPL_WIDTH),
conv_std_logic_vector(572,AMPL_WIDTH),
conv_std_logic_vector(572,AMPL_WIDTH),
conv_std_logic_vector(573,AMPL_WIDTH),
conv_std_logic_vector(574,AMPL_WIDTH),
conv_std_logic_vector(575,AMPL_WIDTH),
conv_std_logic_vector(575,AMPL_WIDTH),
conv_std_logic_vector(576,AMPL_WIDTH),
conv_std_logic_vector(577,AMPL_WIDTH),
conv_std_logic_vector(578,AMPL_WIDTH),
conv_std_logic_vector(578,AMPL_WIDTH),
conv_std_logic_vector(579,AMPL_WIDTH),
conv_std_logic_vector(580,AMPL_WIDTH),
conv_std_logic_vector(581,AMPL_WIDTH),
conv_std_logic_vector(581,AMPL_WIDTH),
conv_std_logic_vector(582,AMPL_WIDTH),
conv_std_logic_vector(583,AMPL_WIDTH),
conv_std_logic_vector(584,AMPL_WIDTH),
conv_std_logic_vector(584,AMPL_WIDTH),
conv_std_logic_vector(585,AMPL_WIDTH),
conv_std_logic_vector(586,AMPL_WIDTH),
conv_std_logic_vector(587,AMPL_WIDTH),
conv_std_logic_vector(587,AMPL_WIDTH),
conv_std_logic_vector(588,AMPL_WIDTH),
conv_std_logic_vector(589,AMPL_WIDTH),
conv_std_logic_vector(590,AMPL_WIDTH),
conv_std_logic_vector(590,AMPL_WIDTH),
conv_std_logic_vector(591,AMPL_WIDTH),
conv_std_logic_vector(592,AMPL_WIDTH),
conv_std_logic_vector(593,AMPL_WIDTH),
conv_std_logic_vector(593,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(595,AMPL_WIDTH),
conv_std_logic_vector(596,AMPL_WIDTH),
conv_std_logic_vector(596,AMPL_WIDTH),
conv_std_logic_vector(597,AMPL_WIDTH),
conv_std_logic_vector(598,AMPL_WIDTH),
conv_std_logic_vector(599,AMPL_WIDTH),
conv_std_logic_vector(599,AMPL_WIDTH),
conv_std_logic_vector(600,AMPL_WIDTH),
conv_std_logic_vector(601,AMPL_WIDTH),
conv_std_logic_vector(602,AMPL_WIDTH),
conv_std_logic_vector(602,AMPL_WIDTH),
conv_std_logic_vector(603,AMPL_WIDTH),
conv_std_logic_vector(604,AMPL_WIDTH),
conv_std_logic_vector(605,AMPL_WIDTH),
conv_std_logic_vector(605,AMPL_WIDTH),
conv_std_logic_vector(606,AMPL_WIDTH),
conv_std_logic_vector(607,AMPL_WIDTH),
conv_std_logic_vector(608,AMPL_WIDTH),
conv_std_logic_vector(608,AMPL_WIDTH),
conv_std_logic_vector(609,AMPL_WIDTH),
conv_std_logic_vector(610,AMPL_WIDTH),
conv_std_logic_vector(611,AMPL_WIDTH),
conv_std_logic_vector(611,AMPL_WIDTH),
conv_std_logic_vector(612,AMPL_WIDTH),
conv_std_logic_vector(613,AMPL_WIDTH),
conv_std_logic_vector(614,AMPL_WIDTH),
conv_std_logic_vector(614,AMPL_WIDTH),
conv_std_logic_vector(615,AMPL_WIDTH),
conv_std_logic_vector(616,AMPL_WIDTH),
conv_std_logic_vector(617,AMPL_WIDTH),
conv_std_logic_vector(617,AMPL_WIDTH),
conv_std_logic_vector(618,AMPL_WIDTH),
conv_std_logic_vector(619,AMPL_WIDTH),
conv_std_logic_vector(620,AMPL_WIDTH),
conv_std_logic_vector(620,AMPL_WIDTH),
conv_std_logic_vector(621,AMPL_WIDTH),
conv_std_logic_vector(622,AMPL_WIDTH),
conv_std_logic_vector(623,AMPL_WIDTH),
conv_std_logic_vector(623,AMPL_WIDTH),
conv_std_logic_vector(624,AMPL_WIDTH),
conv_std_logic_vector(625,AMPL_WIDTH),
conv_std_logic_vector(626,AMPL_WIDTH),
conv_std_logic_vector(626,AMPL_WIDTH),
conv_std_logic_vector(627,AMPL_WIDTH),
conv_std_logic_vector(628,AMPL_WIDTH),
conv_std_logic_vector(629,AMPL_WIDTH),
conv_std_logic_vector(629,AMPL_WIDTH),
conv_std_logic_vector(630,AMPL_WIDTH),
conv_std_logic_vector(631,AMPL_WIDTH),
conv_std_logic_vector(632,AMPL_WIDTH),
conv_std_logic_vector(632,AMPL_WIDTH),
conv_std_logic_vector(633,AMPL_WIDTH),
conv_std_logic_vector(634,AMPL_WIDTH),
conv_std_logic_vector(635,AMPL_WIDTH),
conv_std_logic_vector(635,AMPL_WIDTH),
conv_std_logic_vector(636,AMPL_WIDTH),
conv_std_logic_vector(637,AMPL_WIDTH),
conv_std_logic_vector(638,AMPL_WIDTH),
conv_std_logic_vector(638,AMPL_WIDTH),
conv_std_logic_vector(639,AMPL_WIDTH),
conv_std_logic_vector(640,AMPL_WIDTH),
conv_std_logic_vector(641,AMPL_WIDTH),
conv_std_logic_vector(641,AMPL_WIDTH),
conv_std_logic_vector(642,AMPL_WIDTH),
conv_std_logic_vector(643,AMPL_WIDTH),
conv_std_logic_vector(644,AMPL_WIDTH),
conv_std_logic_vector(644,AMPL_WIDTH),
conv_std_logic_vector(645,AMPL_WIDTH),
conv_std_logic_vector(646,AMPL_WIDTH),
conv_std_logic_vector(647,AMPL_WIDTH),
conv_std_logic_vector(647,AMPL_WIDTH),
conv_std_logic_vector(648,AMPL_WIDTH),
conv_std_logic_vector(649,AMPL_WIDTH),
conv_std_logic_vector(650,AMPL_WIDTH),
conv_std_logic_vector(650,AMPL_WIDTH),
conv_std_logic_vector(651,AMPL_WIDTH),
conv_std_logic_vector(652,AMPL_WIDTH),
conv_std_logic_vector(653,AMPL_WIDTH),
conv_std_logic_vector(653,AMPL_WIDTH),
conv_std_logic_vector(654,AMPL_WIDTH),
conv_std_logic_vector(655,AMPL_WIDTH),
conv_std_logic_vector(656,AMPL_WIDTH),
conv_std_logic_vector(656,AMPL_WIDTH),
conv_std_logic_vector(657,AMPL_WIDTH),
conv_std_logic_vector(658,AMPL_WIDTH),
conv_std_logic_vector(658,AMPL_WIDTH),
conv_std_logic_vector(659,AMPL_WIDTH),
conv_std_logic_vector(660,AMPL_WIDTH),
conv_std_logic_vector(661,AMPL_WIDTH),
conv_std_logic_vector(661,AMPL_WIDTH),
conv_std_logic_vector(662,AMPL_WIDTH),
conv_std_logic_vector(663,AMPL_WIDTH),
conv_std_logic_vector(664,AMPL_WIDTH),
conv_std_logic_vector(664,AMPL_WIDTH),
conv_std_logic_vector(665,AMPL_WIDTH),
conv_std_logic_vector(666,AMPL_WIDTH),
conv_std_logic_vector(667,AMPL_WIDTH),
conv_std_logic_vector(667,AMPL_WIDTH),
conv_std_logic_vector(668,AMPL_WIDTH),
conv_std_logic_vector(669,AMPL_WIDTH),
conv_std_logic_vector(670,AMPL_WIDTH),
conv_std_logic_vector(670,AMPL_WIDTH),
conv_std_logic_vector(671,AMPL_WIDTH),
conv_std_logic_vector(672,AMPL_WIDTH),
conv_std_logic_vector(673,AMPL_WIDTH),
conv_std_logic_vector(673,AMPL_WIDTH),
conv_std_logic_vector(674,AMPL_WIDTH),
conv_std_logic_vector(675,AMPL_WIDTH),
conv_std_logic_vector(676,AMPL_WIDTH),
conv_std_logic_vector(676,AMPL_WIDTH),
conv_std_logic_vector(677,AMPL_WIDTH),
conv_std_logic_vector(678,AMPL_WIDTH),
conv_std_logic_vector(679,AMPL_WIDTH),
conv_std_logic_vector(679,AMPL_WIDTH),
conv_std_logic_vector(680,AMPL_WIDTH),
conv_std_logic_vector(681,AMPL_WIDTH),
conv_std_logic_vector(681,AMPL_WIDTH),
conv_std_logic_vector(682,AMPL_WIDTH),
conv_std_logic_vector(683,AMPL_WIDTH),
conv_std_logic_vector(684,AMPL_WIDTH),
conv_std_logic_vector(684,AMPL_WIDTH),
conv_std_logic_vector(685,AMPL_WIDTH),
conv_std_logic_vector(686,AMPL_WIDTH),
conv_std_logic_vector(687,AMPL_WIDTH),
conv_std_logic_vector(687,AMPL_WIDTH),
conv_std_logic_vector(688,AMPL_WIDTH),
conv_std_logic_vector(689,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(691,AMPL_WIDTH),
conv_std_logic_vector(692,AMPL_WIDTH),
conv_std_logic_vector(693,AMPL_WIDTH),
conv_std_logic_vector(693,AMPL_WIDTH),
conv_std_logic_vector(694,AMPL_WIDTH),
conv_std_logic_vector(695,AMPL_WIDTH),
conv_std_logic_vector(696,AMPL_WIDTH),
conv_std_logic_vector(696,AMPL_WIDTH),
conv_std_logic_vector(697,AMPL_WIDTH),
conv_std_logic_vector(698,AMPL_WIDTH),
conv_std_logic_vector(698,AMPL_WIDTH),
conv_std_logic_vector(699,AMPL_WIDTH),
conv_std_logic_vector(700,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(702,AMPL_WIDTH),
conv_std_logic_vector(703,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(705,AMPL_WIDTH),
conv_std_logic_vector(706,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(708,AMPL_WIDTH),
conv_std_logic_vector(709,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(711,AMPL_WIDTH),
conv_std_logic_vector(712,AMPL_WIDTH),
conv_std_logic_vector(712,AMPL_WIDTH),
conv_std_logic_vector(713,AMPL_WIDTH),
conv_std_logic_vector(714,AMPL_WIDTH),
conv_std_logic_vector(715,AMPL_WIDTH),
conv_std_logic_vector(715,AMPL_WIDTH),
conv_std_logic_vector(716,AMPL_WIDTH),
conv_std_logic_vector(717,AMPL_WIDTH),
conv_std_logic_vector(718,AMPL_WIDTH),
conv_std_logic_vector(718,AMPL_WIDTH),
conv_std_logic_vector(719,AMPL_WIDTH),
conv_std_logic_vector(720,AMPL_WIDTH),
conv_std_logic_vector(721,AMPL_WIDTH),
conv_std_logic_vector(721,AMPL_WIDTH),
conv_std_logic_vector(722,AMPL_WIDTH),
conv_std_logic_vector(723,AMPL_WIDTH),
conv_std_logic_vector(724,AMPL_WIDTH),
conv_std_logic_vector(724,AMPL_WIDTH),
conv_std_logic_vector(725,AMPL_WIDTH),
conv_std_logic_vector(726,AMPL_WIDTH),
conv_std_logic_vector(726,AMPL_WIDTH),
conv_std_logic_vector(727,AMPL_WIDTH),
conv_std_logic_vector(728,AMPL_WIDTH),
conv_std_logic_vector(729,AMPL_WIDTH),
conv_std_logic_vector(729,AMPL_WIDTH),
conv_std_logic_vector(730,AMPL_WIDTH),
conv_std_logic_vector(731,AMPL_WIDTH),
conv_std_logic_vector(732,AMPL_WIDTH),
conv_std_logic_vector(732,AMPL_WIDTH),
conv_std_logic_vector(733,AMPL_WIDTH),
conv_std_logic_vector(734,AMPL_WIDTH),
conv_std_logic_vector(735,AMPL_WIDTH),
conv_std_logic_vector(735,AMPL_WIDTH),
conv_std_logic_vector(736,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(738,AMPL_WIDTH),
conv_std_logic_vector(739,AMPL_WIDTH),
conv_std_logic_vector(740,AMPL_WIDTH),
conv_std_logic_vector(740,AMPL_WIDTH),
conv_std_logic_vector(741,AMPL_WIDTH),
conv_std_logic_vector(742,AMPL_WIDTH),
conv_std_logic_vector(743,AMPL_WIDTH),
conv_std_logic_vector(743,AMPL_WIDTH),
conv_std_logic_vector(744,AMPL_WIDTH),
conv_std_logic_vector(745,AMPL_WIDTH),
conv_std_logic_vector(745,AMPL_WIDTH),
conv_std_logic_vector(746,AMPL_WIDTH),
conv_std_logic_vector(747,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(749,AMPL_WIDTH),
conv_std_logic_vector(750,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(752,AMPL_WIDTH),
conv_std_logic_vector(753,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(755,AMPL_WIDTH),
conv_std_logic_vector(756,AMPL_WIDTH),
conv_std_logic_vector(756,AMPL_WIDTH),
conv_std_logic_vector(757,AMPL_WIDTH),
conv_std_logic_vector(758,AMPL_WIDTH),
conv_std_logic_vector(759,AMPL_WIDTH),
conv_std_logic_vector(759,AMPL_WIDTH),
conv_std_logic_vector(760,AMPL_WIDTH),
conv_std_logic_vector(761,AMPL_WIDTH),
conv_std_logic_vector(762,AMPL_WIDTH),
conv_std_logic_vector(762,AMPL_WIDTH),
conv_std_logic_vector(763,AMPL_WIDTH),
conv_std_logic_vector(764,AMPL_WIDTH),
conv_std_logic_vector(764,AMPL_WIDTH),
conv_std_logic_vector(765,AMPL_WIDTH),
conv_std_logic_vector(766,AMPL_WIDTH),
conv_std_logic_vector(767,AMPL_WIDTH),
conv_std_logic_vector(767,AMPL_WIDTH),
conv_std_logic_vector(768,AMPL_WIDTH),
conv_std_logic_vector(769,AMPL_WIDTH),
conv_std_logic_vector(770,AMPL_WIDTH),
conv_std_logic_vector(770,AMPL_WIDTH),
conv_std_logic_vector(771,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(773,AMPL_WIDTH),
conv_std_logic_vector(774,AMPL_WIDTH),
conv_std_logic_vector(775,AMPL_WIDTH),
conv_std_logic_vector(775,AMPL_WIDTH),
conv_std_logic_vector(776,AMPL_WIDTH),
conv_std_logic_vector(777,AMPL_WIDTH),
conv_std_logic_vector(778,AMPL_WIDTH),
conv_std_logic_vector(778,AMPL_WIDTH),
conv_std_logic_vector(779,AMPL_WIDTH),
conv_std_logic_vector(780,AMPL_WIDTH),
conv_std_logic_vector(780,AMPL_WIDTH),
conv_std_logic_vector(781,AMPL_WIDTH),
conv_std_logic_vector(782,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(784,AMPL_WIDTH),
conv_std_logic_vector(785,AMPL_WIDTH),
conv_std_logic_vector(786,AMPL_WIDTH),
conv_std_logic_vector(786,AMPL_WIDTH),
conv_std_logic_vector(787,AMPL_WIDTH),
conv_std_logic_vector(788,AMPL_WIDTH),
conv_std_logic_vector(788,AMPL_WIDTH),
conv_std_logic_vector(789,AMPL_WIDTH),
conv_std_logic_vector(790,AMPL_WIDTH),
conv_std_logic_vector(791,AMPL_WIDTH),
conv_std_logic_vector(791,AMPL_WIDTH),
conv_std_logic_vector(792,AMPL_WIDTH),
conv_std_logic_vector(793,AMPL_WIDTH),
conv_std_logic_vector(793,AMPL_WIDTH),
conv_std_logic_vector(794,AMPL_WIDTH),
conv_std_logic_vector(795,AMPL_WIDTH),
conv_std_logic_vector(796,AMPL_WIDTH),
conv_std_logic_vector(796,AMPL_WIDTH),
conv_std_logic_vector(797,AMPL_WIDTH),
conv_std_logic_vector(798,AMPL_WIDTH),
conv_std_logic_vector(799,AMPL_WIDTH),
conv_std_logic_vector(799,AMPL_WIDTH),
conv_std_logic_vector(800,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(802,AMPL_WIDTH),
conv_std_logic_vector(803,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(805,AMPL_WIDTH),
conv_std_logic_vector(806,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(808,AMPL_WIDTH),
conv_std_logic_vector(809,AMPL_WIDTH),
conv_std_logic_vector(809,AMPL_WIDTH),
conv_std_logic_vector(810,AMPL_WIDTH),
conv_std_logic_vector(811,AMPL_WIDTH),
conv_std_logic_vector(812,AMPL_WIDTH),
conv_std_logic_vector(812,AMPL_WIDTH),
conv_std_logic_vector(813,AMPL_WIDTH),
conv_std_logic_vector(814,AMPL_WIDTH),
conv_std_logic_vector(814,AMPL_WIDTH),
conv_std_logic_vector(815,AMPL_WIDTH),
conv_std_logic_vector(816,AMPL_WIDTH),
conv_std_logic_vector(817,AMPL_WIDTH),
conv_std_logic_vector(817,AMPL_WIDTH),
conv_std_logic_vector(818,AMPL_WIDTH),
conv_std_logic_vector(819,AMPL_WIDTH),
conv_std_logic_vector(819,AMPL_WIDTH),
conv_std_logic_vector(820,AMPL_WIDTH),
conv_std_logic_vector(821,AMPL_WIDTH),
conv_std_logic_vector(822,AMPL_WIDTH),
conv_std_logic_vector(822,AMPL_WIDTH),
conv_std_logic_vector(823,AMPL_WIDTH),
conv_std_logic_vector(824,AMPL_WIDTH),
conv_std_logic_vector(825,AMPL_WIDTH),
conv_std_logic_vector(825,AMPL_WIDTH),
conv_std_logic_vector(826,AMPL_WIDTH),
conv_std_logic_vector(827,AMPL_WIDTH),
conv_std_logic_vector(827,AMPL_WIDTH),
conv_std_logic_vector(828,AMPL_WIDTH),
conv_std_logic_vector(829,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(831,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(833,AMPL_WIDTH),
conv_std_logic_vector(834,AMPL_WIDTH),
conv_std_logic_vector(835,AMPL_WIDTH),
conv_std_logic_vector(835,AMPL_WIDTH),
conv_std_logic_vector(836,AMPL_WIDTH),
conv_std_logic_vector(837,AMPL_WIDTH),
conv_std_logic_vector(837,AMPL_WIDTH),
conv_std_logic_vector(838,AMPL_WIDTH),
conv_std_logic_vector(839,AMPL_WIDTH),
conv_std_logic_vector(840,AMPL_WIDTH),
conv_std_logic_vector(840,AMPL_WIDTH),
conv_std_logic_vector(841,AMPL_WIDTH),
conv_std_logic_vector(842,AMPL_WIDTH),
conv_std_logic_vector(842,AMPL_WIDTH),
conv_std_logic_vector(843,AMPL_WIDTH),
conv_std_logic_vector(844,AMPL_WIDTH),
conv_std_logic_vector(845,AMPL_WIDTH),
conv_std_logic_vector(845,AMPL_WIDTH),
conv_std_logic_vector(846,AMPL_WIDTH),
conv_std_logic_vector(847,AMPL_WIDTH),
conv_std_logic_vector(847,AMPL_WIDTH),
conv_std_logic_vector(848,AMPL_WIDTH),
conv_std_logic_vector(849,AMPL_WIDTH),
conv_std_logic_vector(850,AMPL_WIDTH),
conv_std_logic_vector(850,AMPL_WIDTH),
conv_std_logic_vector(851,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(853,AMPL_WIDTH),
conv_std_logic_vector(854,AMPL_WIDTH),
conv_std_logic_vector(855,AMPL_WIDTH),
conv_std_logic_vector(855,AMPL_WIDTH),
conv_std_logic_vector(856,AMPL_WIDTH),
conv_std_logic_vector(857,AMPL_WIDTH),
conv_std_logic_vector(857,AMPL_WIDTH),
conv_std_logic_vector(858,AMPL_WIDTH),
conv_std_logic_vector(859,AMPL_WIDTH),
conv_std_logic_vector(860,AMPL_WIDTH),
conv_std_logic_vector(860,AMPL_WIDTH),
conv_std_logic_vector(861,AMPL_WIDTH),
conv_std_logic_vector(862,AMPL_WIDTH),
conv_std_logic_vector(862,AMPL_WIDTH),
conv_std_logic_vector(863,AMPL_WIDTH),
conv_std_logic_vector(864,AMPL_WIDTH),
conv_std_logic_vector(865,AMPL_WIDTH),
conv_std_logic_vector(865,AMPL_WIDTH),
conv_std_logic_vector(866,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(868,AMPL_WIDTH),
conv_std_logic_vector(869,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(871,AMPL_WIDTH),
conv_std_logic_vector(872,AMPL_WIDTH),
conv_std_logic_vector(872,AMPL_WIDTH),
conv_std_logic_vector(873,AMPL_WIDTH),
conv_std_logic_vector(874,AMPL_WIDTH),
conv_std_logic_vector(874,AMPL_WIDTH),
conv_std_logic_vector(875,AMPL_WIDTH),
conv_std_logic_vector(876,AMPL_WIDTH),
conv_std_logic_vector(877,AMPL_WIDTH),
conv_std_logic_vector(877,AMPL_WIDTH),
conv_std_logic_vector(878,AMPL_WIDTH),
conv_std_logic_vector(879,AMPL_WIDTH),
conv_std_logic_vector(879,AMPL_WIDTH),
conv_std_logic_vector(880,AMPL_WIDTH),
conv_std_logic_vector(881,AMPL_WIDTH),
conv_std_logic_vector(882,AMPL_WIDTH),
conv_std_logic_vector(882,AMPL_WIDTH),
conv_std_logic_vector(883,AMPL_WIDTH),
conv_std_logic_vector(884,AMPL_WIDTH),
conv_std_logic_vector(884,AMPL_WIDTH),
conv_std_logic_vector(885,AMPL_WIDTH),
conv_std_logic_vector(886,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(888,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(890,AMPL_WIDTH),
conv_std_logic_vector(891,AMPL_WIDTH),
conv_std_logic_vector(891,AMPL_WIDTH),
conv_std_logic_vector(892,AMPL_WIDTH),
conv_std_logic_vector(893,AMPL_WIDTH),
conv_std_logic_vector(894,AMPL_WIDTH),
conv_std_logic_vector(894,AMPL_WIDTH),
conv_std_logic_vector(895,AMPL_WIDTH),
conv_std_logic_vector(896,AMPL_WIDTH),
conv_std_logic_vector(896,AMPL_WIDTH),
conv_std_logic_vector(897,AMPL_WIDTH),
conv_std_logic_vector(898,AMPL_WIDTH),
conv_std_logic_vector(899,AMPL_WIDTH),
conv_std_logic_vector(899,AMPL_WIDTH),
conv_std_logic_vector(900,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(902,AMPL_WIDTH),
conv_std_logic_vector(903,AMPL_WIDTH),
conv_std_logic_vector(903,AMPL_WIDTH),
conv_std_logic_vector(904,AMPL_WIDTH),
conv_std_logic_vector(905,AMPL_WIDTH),
conv_std_logic_vector(906,AMPL_WIDTH),
conv_std_logic_vector(906,AMPL_WIDTH),
conv_std_logic_vector(907,AMPL_WIDTH),
conv_std_logic_vector(908,AMPL_WIDTH),
conv_std_logic_vector(908,AMPL_WIDTH),
conv_std_logic_vector(909,AMPL_WIDTH),
conv_std_logic_vector(910,AMPL_WIDTH),
conv_std_logic_vector(911,AMPL_WIDTH),
conv_std_logic_vector(911,AMPL_WIDTH),
conv_std_logic_vector(912,AMPL_WIDTH),
conv_std_logic_vector(913,AMPL_WIDTH),
conv_std_logic_vector(913,AMPL_WIDTH),
conv_std_logic_vector(914,AMPL_WIDTH),
conv_std_logic_vector(915,AMPL_WIDTH),
conv_std_logic_vector(915,AMPL_WIDTH),
conv_std_logic_vector(916,AMPL_WIDTH),
conv_std_logic_vector(917,AMPL_WIDTH),
conv_std_logic_vector(918,AMPL_WIDTH),
conv_std_logic_vector(918,AMPL_WIDTH),
conv_std_logic_vector(919,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(921,AMPL_WIDTH),
conv_std_logic_vector(922,AMPL_WIDTH),
conv_std_logic_vector(922,AMPL_WIDTH),
conv_std_logic_vector(923,AMPL_WIDTH),
conv_std_logic_vector(924,AMPL_WIDTH),
conv_std_logic_vector(925,AMPL_WIDTH),
conv_std_logic_vector(925,AMPL_WIDTH),
conv_std_logic_vector(926,AMPL_WIDTH),
conv_std_logic_vector(927,AMPL_WIDTH),
conv_std_logic_vector(927,AMPL_WIDTH),
conv_std_logic_vector(928,AMPL_WIDTH),
conv_std_logic_vector(929,AMPL_WIDTH),
conv_std_logic_vector(929,AMPL_WIDTH),
conv_std_logic_vector(930,AMPL_WIDTH),
conv_std_logic_vector(931,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(933,AMPL_WIDTH),
conv_std_logic_vector(934,AMPL_WIDTH),
conv_std_logic_vector(934,AMPL_WIDTH),
conv_std_logic_vector(935,AMPL_WIDTH),
conv_std_logic_vector(936,AMPL_WIDTH),
conv_std_logic_vector(936,AMPL_WIDTH),
conv_std_logic_vector(937,AMPL_WIDTH),
conv_std_logic_vector(938,AMPL_WIDTH),
conv_std_logic_vector(939,AMPL_WIDTH),
conv_std_logic_vector(939,AMPL_WIDTH),
conv_std_logic_vector(940,AMPL_WIDTH),
conv_std_logic_vector(941,AMPL_WIDTH),
conv_std_logic_vector(941,AMPL_WIDTH),
conv_std_logic_vector(942,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(944,AMPL_WIDTH),
conv_std_logic_vector(945,AMPL_WIDTH),
conv_std_logic_vector(946,AMPL_WIDTH),
conv_std_logic_vector(946,AMPL_WIDTH),
conv_std_logic_vector(947,AMPL_WIDTH),
conv_std_logic_vector(948,AMPL_WIDTH),
conv_std_logic_vector(948,AMPL_WIDTH),
conv_std_logic_vector(949,AMPL_WIDTH),
conv_std_logic_vector(950,AMPL_WIDTH),
conv_std_logic_vector(950,AMPL_WIDTH),
conv_std_logic_vector(951,AMPL_WIDTH),
conv_std_logic_vector(952,AMPL_WIDTH),
conv_std_logic_vector(952,AMPL_WIDTH),
conv_std_logic_vector(953,AMPL_WIDTH),
conv_std_logic_vector(954,AMPL_WIDTH),
conv_std_logic_vector(955,AMPL_WIDTH),
conv_std_logic_vector(955,AMPL_WIDTH),
conv_std_logic_vector(956,AMPL_WIDTH),
conv_std_logic_vector(957,AMPL_WIDTH),
conv_std_logic_vector(957,AMPL_WIDTH),
conv_std_logic_vector(958,AMPL_WIDTH),
conv_std_logic_vector(959,AMPL_WIDTH),
conv_std_logic_vector(959,AMPL_WIDTH),
conv_std_logic_vector(960,AMPL_WIDTH),
conv_std_logic_vector(961,AMPL_WIDTH),
conv_std_logic_vector(961,AMPL_WIDTH),
conv_std_logic_vector(962,AMPL_WIDTH),
conv_std_logic_vector(963,AMPL_WIDTH),
conv_std_logic_vector(964,AMPL_WIDTH),
conv_std_logic_vector(964,AMPL_WIDTH),
conv_std_logic_vector(965,AMPL_WIDTH),
conv_std_logic_vector(966,AMPL_WIDTH),
conv_std_logic_vector(966,AMPL_WIDTH),
conv_std_logic_vector(967,AMPL_WIDTH),
conv_std_logic_vector(968,AMPL_WIDTH),
conv_std_logic_vector(968,AMPL_WIDTH),
conv_std_logic_vector(969,AMPL_WIDTH),
conv_std_logic_vector(970,AMPL_WIDTH),
conv_std_logic_vector(970,AMPL_WIDTH),
conv_std_logic_vector(971,AMPL_WIDTH),
conv_std_logic_vector(972,AMPL_WIDTH),
conv_std_logic_vector(973,AMPL_WIDTH),
conv_std_logic_vector(973,AMPL_WIDTH),
conv_std_logic_vector(974,AMPL_WIDTH),
conv_std_logic_vector(975,AMPL_WIDTH),
conv_std_logic_vector(975,AMPL_WIDTH),
conv_std_logic_vector(976,AMPL_WIDTH),
conv_std_logic_vector(977,AMPL_WIDTH),
conv_std_logic_vector(977,AMPL_WIDTH),
conv_std_logic_vector(978,AMPL_WIDTH),
conv_std_logic_vector(979,AMPL_WIDTH),
conv_std_logic_vector(979,AMPL_WIDTH),
conv_std_logic_vector(980,AMPL_WIDTH),
conv_std_logic_vector(981,AMPL_WIDTH),
conv_std_logic_vector(982,AMPL_WIDTH),
conv_std_logic_vector(982,AMPL_WIDTH),
conv_std_logic_vector(983,AMPL_WIDTH),
conv_std_logic_vector(984,AMPL_WIDTH),
conv_std_logic_vector(984,AMPL_WIDTH),
conv_std_logic_vector(985,AMPL_WIDTH),
conv_std_logic_vector(986,AMPL_WIDTH),
conv_std_logic_vector(986,AMPL_WIDTH),
conv_std_logic_vector(987,AMPL_WIDTH),
conv_std_logic_vector(988,AMPL_WIDTH),
conv_std_logic_vector(988,AMPL_WIDTH),
conv_std_logic_vector(989,AMPL_WIDTH),
conv_std_logic_vector(990,AMPL_WIDTH),
conv_std_logic_vector(990,AMPL_WIDTH),
conv_std_logic_vector(991,AMPL_WIDTH),
conv_std_logic_vector(992,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(994,AMPL_WIDTH),
conv_std_logic_vector(995,AMPL_WIDTH),
conv_std_logic_vector(995,AMPL_WIDTH),
conv_std_logic_vector(996,AMPL_WIDTH),
conv_std_logic_vector(997,AMPL_WIDTH),
conv_std_logic_vector(997,AMPL_WIDTH),
conv_std_logic_vector(998,AMPL_WIDTH),
conv_std_logic_vector(999,AMPL_WIDTH),
conv_std_logic_vector(999,AMPL_WIDTH),
conv_std_logic_vector(1000,AMPL_WIDTH),
conv_std_logic_vector(1001,AMPL_WIDTH),
conv_std_logic_vector(1001,AMPL_WIDTH),
conv_std_logic_vector(1002,AMPL_WIDTH),
conv_std_logic_vector(1003,AMPL_WIDTH),
conv_std_logic_vector(1003,AMPL_WIDTH),
conv_std_logic_vector(1004,AMPL_WIDTH),
conv_std_logic_vector(1005,AMPL_WIDTH),
conv_std_logic_vector(1006,AMPL_WIDTH),
conv_std_logic_vector(1006,AMPL_WIDTH),
conv_std_logic_vector(1007,AMPL_WIDTH),
conv_std_logic_vector(1008,AMPL_WIDTH),
conv_std_logic_vector(1008,AMPL_WIDTH),
conv_std_logic_vector(1009,AMPL_WIDTH),
conv_std_logic_vector(1010,AMPL_WIDTH),
conv_std_logic_vector(1010,AMPL_WIDTH),
conv_std_logic_vector(1011,AMPL_WIDTH),
conv_std_logic_vector(1012,AMPL_WIDTH),
conv_std_logic_vector(1012,AMPL_WIDTH),
conv_std_logic_vector(1013,AMPL_WIDTH),
conv_std_logic_vector(1014,AMPL_WIDTH),
conv_std_logic_vector(1014,AMPL_WIDTH),
conv_std_logic_vector(1015,AMPL_WIDTH),
conv_std_logic_vector(1016,AMPL_WIDTH),
conv_std_logic_vector(1016,AMPL_WIDTH),
conv_std_logic_vector(1017,AMPL_WIDTH),
conv_std_logic_vector(1018,AMPL_WIDTH),
conv_std_logic_vector(1019,AMPL_WIDTH),
conv_std_logic_vector(1019,AMPL_WIDTH),
conv_std_logic_vector(1020,AMPL_WIDTH),
conv_std_logic_vector(1021,AMPL_WIDTH),
conv_std_logic_vector(1021,AMPL_WIDTH),
conv_std_logic_vector(1022,AMPL_WIDTH),
conv_std_logic_vector(1023,AMPL_WIDTH),
conv_std_logic_vector(1023,AMPL_WIDTH),
conv_std_logic_vector(1024,AMPL_WIDTH),
conv_std_logic_vector(1025,AMPL_WIDTH),
conv_std_logic_vector(1025,AMPL_WIDTH),
conv_std_logic_vector(1026,AMPL_WIDTH),
conv_std_logic_vector(1027,AMPL_WIDTH),
conv_std_logic_vector(1027,AMPL_WIDTH),
conv_std_logic_vector(1028,AMPL_WIDTH),
conv_std_logic_vector(1029,AMPL_WIDTH),
conv_std_logic_vector(1029,AMPL_WIDTH),
conv_std_logic_vector(1030,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1032,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1034,AMPL_WIDTH),
conv_std_logic_vector(1035,AMPL_WIDTH),
conv_std_logic_vector(1035,AMPL_WIDTH),
conv_std_logic_vector(1036,AMPL_WIDTH),
conv_std_logic_vector(1037,AMPL_WIDTH),
conv_std_logic_vector(1038,AMPL_WIDTH),
conv_std_logic_vector(1038,AMPL_WIDTH),
conv_std_logic_vector(1039,AMPL_WIDTH),
conv_std_logic_vector(1040,AMPL_WIDTH),
conv_std_logic_vector(1040,AMPL_WIDTH),
conv_std_logic_vector(1041,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1043,AMPL_WIDTH),
conv_std_logic_vector(1044,AMPL_WIDTH),
conv_std_logic_vector(1044,AMPL_WIDTH),
conv_std_logic_vector(1045,AMPL_WIDTH),
conv_std_logic_vector(1046,AMPL_WIDTH),
conv_std_logic_vector(1046,AMPL_WIDTH),
conv_std_logic_vector(1047,AMPL_WIDTH),
conv_std_logic_vector(1048,AMPL_WIDTH),
conv_std_logic_vector(1048,AMPL_WIDTH),
conv_std_logic_vector(1049,AMPL_WIDTH),
conv_std_logic_vector(1050,AMPL_WIDTH),
conv_std_logic_vector(1050,AMPL_WIDTH),
conv_std_logic_vector(1051,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1053,AMPL_WIDTH),
conv_std_logic_vector(1054,AMPL_WIDTH),
conv_std_logic_vector(1054,AMPL_WIDTH),
conv_std_logic_vector(1055,AMPL_WIDTH),
conv_std_logic_vector(1056,AMPL_WIDTH),
conv_std_logic_vector(1056,AMPL_WIDTH),
conv_std_logic_vector(1057,AMPL_WIDTH),
conv_std_logic_vector(1058,AMPL_WIDTH),
conv_std_logic_vector(1058,AMPL_WIDTH),
conv_std_logic_vector(1059,AMPL_WIDTH),
conv_std_logic_vector(1060,AMPL_WIDTH),
conv_std_logic_vector(1060,AMPL_WIDTH),
conv_std_logic_vector(1061,AMPL_WIDTH),
conv_std_logic_vector(1062,AMPL_WIDTH),
conv_std_logic_vector(1062,AMPL_WIDTH),
conv_std_logic_vector(1063,AMPL_WIDTH),
conv_std_logic_vector(1064,AMPL_WIDTH),
conv_std_logic_vector(1064,AMPL_WIDTH),
conv_std_logic_vector(1065,AMPL_WIDTH),
conv_std_logic_vector(1066,AMPL_WIDTH),
conv_std_logic_vector(1066,AMPL_WIDTH),
conv_std_logic_vector(1067,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1069,AMPL_WIDTH),
conv_std_logic_vector(1070,AMPL_WIDTH),
conv_std_logic_vector(1070,AMPL_WIDTH),
conv_std_logic_vector(1071,AMPL_WIDTH),
conv_std_logic_vector(1072,AMPL_WIDTH),
conv_std_logic_vector(1072,AMPL_WIDTH),
conv_std_logic_vector(1073,AMPL_WIDTH),
conv_std_logic_vector(1074,AMPL_WIDTH),
conv_std_logic_vector(1075,AMPL_WIDTH),
conv_std_logic_vector(1075,AMPL_WIDTH),
conv_std_logic_vector(1076,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1078,AMPL_WIDTH),
conv_std_logic_vector(1079,AMPL_WIDTH),
conv_std_logic_vector(1079,AMPL_WIDTH),
conv_std_logic_vector(1080,AMPL_WIDTH),
conv_std_logic_vector(1081,AMPL_WIDTH),
conv_std_logic_vector(1081,AMPL_WIDTH),
conv_std_logic_vector(1082,AMPL_WIDTH),
conv_std_logic_vector(1083,AMPL_WIDTH),
conv_std_logic_vector(1083,AMPL_WIDTH),
conv_std_logic_vector(1084,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1086,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1088,AMPL_WIDTH),
conv_std_logic_vector(1088,AMPL_WIDTH),
conv_std_logic_vector(1089,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1091,AMPL_WIDTH),
conv_std_logic_vector(1092,AMPL_WIDTH),
conv_std_logic_vector(1092,AMPL_WIDTH),
conv_std_logic_vector(1093,AMPL_WIDTH),
conv_std_logic_vector(1094,AMPL_WIDTH),
conv_std_logic_vector(1094,AMPL_WIDTH),
conv_std_logic_vector(1095,AMPL_WIDTH),
conv_std_logic_vector(1096,AMPL_WIDTH),
conv_std_logic_vector(1096,AMPL_WIDTH),
conv_std_logic_vector(1097,AMPL_WIDTH),
conv_std_logic_vector(1098,AMPL_WIDTH),
conv_std_logic_vector(1098,AMPL_WIDTH),
conv_std_logic_vector(1099,AMPL_WIDTH),
conv_std_logic_vector(1100,AMPL_WIDTH),
conv_std_logic_vector(1100,AMPL_WIDTH),
conv_std_logic_vector(1101,AMPL_WIDTH),
conv_std_logic_vector(1102,AMPL_WIDTH),
conv_std_logic_vector(1102,AMPL_WIDTH),
conv_std_logic_vector(1103,AMPL_WIDTH),
conv_std_logic_vector(1104,AMPL_WIDTH),
conv_std_logic_vector(1104,AMPL_WIDTH),
conv_std_logic_vector(1105,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1107,AMPL_WIDTH),
conv_std_logic_vector(1108,AMPL_WIDTH),
conv_std_logic_vector(1108,AMPL_WIDTH),
conv_std_logic_vector(1109,AMPL_WIDTH),
conv_std_logic_vector(1110,AMPL_WIDTH),
conv_std_logic_vector(1110,AMPL_WIDTH),
conv_std_logic_vector(1111,AMPL_WIDTH),
conv_std_logic_vector(1112,AMPL_WIDTH),
conv_std_logic_vector(1112,AMPL_WIDTH),
conv_std_logic_vector(1113,AMPL_WIDTH),
conv_std_logic_vector(1114,AMPL_WIDTH),
conv_std_logic_vector(1114,AMPL_WIDTH),
conv_std_logic_vector(1115,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1117,AMPL_WIDTH),
conv_std_logic_vector(1118,AMPL_WIDTH),
conv_std_logic_vector(1118,AMPL_WIDTH),
conv_std_logic_vector(1119,AMPL_WIDTH),
conv_std_logic_vector(1120,AMPL_WIDTH),
conv_std_logic_vector(1120,AMPL_WIDTH),
conv_std_logic_vector(1121,AMPL_WIDTH),
conv_std_logic_vector(1122,AMPL_WIDTH),
conv_std_logic_vector(1122,AMPL_WIDTH),
conv_std_logic_vector(1123,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1125,AMPL_WIDTH),
conv_std_logic_vector(1125,AMPL_WIDTH),
conv_std_logic_vector(1126,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1128,AMPL_WIDTH),
conv_std_logic_vector(1129,AMPL_WIDTH),
conv_std_logic_vector(1129,AMPL_WIDTH),
conv_std_logic_vector(1130,AMPL_WIDTH),
conv_std_logic_vector(1131,AMPL_WIDTH),
conv_std_logic_vector(1131,AMPL_WIDTH),
conv_std_logic_vector(1132,AMPL_WIDTH),
conv_std_logic_vector(1133,AMPL_WIDTH),
conv_std_logic_vector(1133,AMPL_WIDTH),
conv_std_logic_vector(1134,AMPL_WIDTH),
conv_std_logic_vector(1135,AMPL_WIDTH),
conv_std_logic_vector(1135,AMPL_WIDTH),
conv_std_logic_vector(1136,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1138,AMPL_WIDTH),
conv_std_logic_vector(1139,AMPL_WIDTH),
conv_std_logic_vector(1139,AMPL_WIDTH),
conv_std_logic_vector(1140,AMPL_WIDTH),
conv_std_logic_vector(1141,AMPL_WIDTH),
conv_std_logic_vector(1141,AMPL_WIDTH),
conv_std_logic_vector(1142,AMPL_WIDTH),
conv_std_logic_vector(1142,AMPL_WIDTH),
conv_std_logic_vector(1143,AMPL_WIDTH),
conv_std_logic_vector(1144,AMPL_WIDTH),
conv_std_logic_vector(1144,AMPL_WIDTH),
conv_std_logic_vector(1145,AMPL_WIDTH),
conv_std_logic_vector(1146,AMPL_WIDTH),
conv_std_logic_vector(1146,AMPL_WIDTH),
conv_std_logic_vector(1147,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1149,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1151,AMPL_WIDTH),
conv_std_logic_vector(1152,AMPL_WIDTH),
conv_std_logic_vector(1152,AMPL_WIDTH),
conv_std_logic_vector(1153,AMPL_WIDTH),
conv_std_logic_vector(1154,AMPL_WIDTH),
conv_std_logic_vector(1154,AMPL_WIDTH),
conv_std_logic_vector(1155,AMPL_WIDTH),
conv_std_logic_vector(1155,AMPL_WIDTH),
conv_std_logic_vector(1156,AMPL_WIDTH),
conv_std_logic_vector(1157,AMPL_WIDTH),
conv_std_logic_vector(1157,AMPL_WIDTH),
conv_std_logic_vector(1158,AMPL_WIDTH),
conv_std_logic_vector(1159,AMPL_WIDTH),
conv_std_logic_vector(1159,AMPL_WIDTH),
conv_std_logic_vector(1160,AMPL_WIDTH),
conv_std_logic_vector(1161,AMPL_WIDTH),
conv_std_logic_vector(1161,AMPL_WIDTH),
conv_std_logic_vector(1162,AMPL_WIDTH),
conv_std_logic_vector(1163,AMPL_WIDTH),
conv_std_logic_vector(1163,AMPL_WIDTH),
conv_std_logic_vector(1164,AMPL_WIDTH),
conv_std_logic_vector(1165,AMPL_WIDTH),
conv_std_logic_vector(1165,AMPL_WIDTH),
conv_std_logic_vector(1166,AMPL_WIDTH),
conv_std_logic_vector(1166,AMPL_WIDTH),
conv_std_logic_vector(1167,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1169,AMPL_WIDTH),
conv_std_logic_vector(1170,AMPL_WIDTH),
conv_std_logic_vector(1170,AMPL_WIDTH),
conv_std_logic_vector(1171,AMPL_WIDTH),
conv_std_logic_vector(1172,AMPL_WIDTH),
conv_std_logic_vector(1172,AMPL_WIDTH),
conv_std_logic_vector(1173,AMPL_WIDTH),
conv_std_logic_vector(1174,AMPL_WIDTH),
conv_std_logic_vector(1174,AMPL_WIDTH),
conv_std_logic_vector(1175,AMPL_WIDTH),
conv_std_logic_vector(1175,AMPL_WIDTH),
conv_std_logic_vector(1176,AMPL_WIDTH),
conv_std_logic_vector(1177,AMPL_WIDTH),
conv_std_logic_vector(1177,AMPL_WIDTH),
conv_std_logic_vector(1178,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1180,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1182,AMPL_WIDTH),
conv_std_logic_vector(1183,AMPL_WIDTH),
conv_std_logic_vector(1183,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1185,AMPL_WIDTH),
conv_std_logic_vector(1186,AMPL_WIDTH),
conv_std_logic_vector(1186,AMPL_WIDTH),
conv_std_logic_vector(1187,AMPL_WIDTH),
conv_std_logic_vector(1188,AMPL_WIDTH),
conv_std_logic_vector(1188,AMPL_WIDTH),
conv_std_logic_vector(1189,AMPL_WIDTH),
conv_std_logic_vector(1190,AMPL_WIDTH),
conv_std_logic_vector(1190,AMPL_WIDTH),
conv_std_logic_vector(1191,AMPL_WIDTH),
conv_std_logic_vector(1191,AMPL_WIDTH),
conv_std_logic_vector(1192,AMPL_WIDTH),
conv_std_logic_vector(1193,AMPL_WIDTH),
conv_std_logic_vector(1193,AMPL_WIDTH),
conv_std_logic_vector(1194,AMPL_WIDTH),
conv_std_logic_vector(1195,AMPL_WIDTH),
conv_std_logic_vector(1195,AMPL_WIDTH),
conv_std_logic_vector(1196,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1198,AMPL_WIDTH),
conv_std_logic_vector(1198,AMPL_WIDTH),
conv_std_logic_vector(1199,AMPL_WIDTH),
conv_std_logic_vector(1200,AMPL_WIDTH),
conv_std_logic_vector(1200,AMPL_WIDTH),
conv_std_logic_vector(1201,AMPL_WIDTH),
conv_std_logic_vector(1202,AMPL_WIDTH),
conv_std_logic_vector(1202,AMPL_WIDTH),
conv_std_logic_vector(1203,AMPL_WIDTH),
conv_std_logic_vector(1204,AMPL_WIDTH),
conv_std_logic_vector(1204,AMPL_WIDTH),
conv_std_logic_vector(1205,AMPL_WIDTH),
conv_std_logic_vector(1205,AMPL_WIDTH),
conv_std_logic_vector(1206,AMPL_WIDTH),
conv_std_logic_vector(1207,AMPL_WIDTH),
conv_std_logic_vector(1207,AMPL_WIDTH),
conv_std_logic_vector(1208,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1210,AMPL_WIDTH),
conv_std_logic_vector(1211,AMPL_WIDTH),
conv_std_logic_vector(1211,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1213,AMPL_WIDTH),
conv_std_logic_vector(1214,AMPL_WIDTH),
conv_std_logic_vector(1214,AMPL_WIDTH),
conv_std_logic_vector(1215,AMPL_WIDTH),
conv_std_logic_vector(1216,AMPL_WIDTH),
conv_std_logic_vector(1216,AMPL_WIDTH),
conv_std_logic_vector(1217,AMPL_WIDTH),
conv_std_logic_vector(1218,AMPL_WIDTH),
conv_std_logic_vector(1218,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1220,AMPL_WIDTH),
conv_std_logic_vector(1221,AMPL_WIDTH),
conv_std_logic_vector(1221,AMPL_WIDTH),
conv_std_logic_vector(1222,AMPL_WIDTH),
conv_std_logic_vector(1223,AMPL_WIDTH),
conv_std_logic_vector(1223,AMPL_WIDTH),
conv_std_logic_vector(1224,AMPL_WIDTH),
conv_std_logic_vector(1224,AMPL_WIDTH),
conv_std_logic_vector(1225,AMPL_WIDTH),
conv_std_logic_vector(1226,AMPL_WIDTH),
conv_std_logic_vector(1226,AMPL_WIDTH),
conv_std_logic_vector(1227,AMPL_WIDTH),
conv_std_logic_vector(1228,AMPL_WIDTH),
conv_std_logic_vector(1228,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1230,AMPL_WIDTH),
conv_std_logic_vector(1231,AMPL_WIDTH),
conv_std_logic_vector(1231,AMPL_WIDTH),
conv_std_logic_vector(1232,AMPL_WIDTH),
conv_std_logic_vector(1233,AMPL_WIDTH),
conv_std_logic_vector(1233,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1235,AMPL_WIDTH),
conv_std_logic_vector(1236,AMPL_WIDTH),
conv_std_logic_vector(1236,AMPL_WIDTH),
conv_std_logic_vector(1237,AMPL_WIDTH),
conv_std_logic_vector(1238,AMPL_WIDTH),
conv_std_logic_vector(1238,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1240,AMPL_WIDTH),
conv_std_logic_vector(1241,AMPL_WIDTH),
conv_std_logic_vector(1241,AMPL_WIDTH),
conv_std_logic_vector(1242,AMPL_WIDTH),
conv_std_logic_vector(1243,AMPL_WIDTH),
conv_std_logic_vector(1243,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1245,AMPL_WIDTH),
conv_std_logic_vector(1246,AMPL_WIDTH),
conv_std_logic_vector(1246,AMPL_WIDTH),
conv_std_logic_vector(1247,AMPL_WIDTH),
conv_std_logic_vector(1248,AMPL_WIDTH),
conv_std_logic_vector(1248,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1250,AMPL_WIDTH),
conv_std_logic_vector(1251,AMPL_WIDTH),
conv_std_logic_vector(1251,AMPL_WIDTH),
conv_std_logic_vector(1252,AMPL_WIDTH),
conv_std_logic_vector(1253,AMPL_WIDTH),
conv_std_logic_vector(1253,AMPL_WIDTH),
conv_std_logic_vector(1254,AMPL_WIDTH),
conv_std_logic_vector(1254,AMPL_WIDTH),
conv_std_logic_vector(1255,AMPL_WIDTH),
conv_std_logic_vector(1256,AMPL_WIDTH),
conv_std_logic_vector(1256,AMPL_WIDTH),
conv_std_logic_vector(1257,AMPL_WIDTH),
conv_std_logic_vector(1258,AMPL_WIDTH),
conv_std_logic_vector(1258,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1260,AMPL_WIDTH),
conv_std_logic_vector(1261,AMPL_WIDTH),
conv_std_logic_vector(1261,AMPL_WIDTH),
conv_std_logic_vector(1262,AMPL_WIDTH),
conv_std_logic_vector(1262,AMPL_WIDTH),
conv_std_logic_vector(1263,AMPL_WIDTH),
conv_std_logic_vector(1264,AMPL_WIDTH),
conv_std_logic_vector(1264,AMPL_WIDTH),
conv_std_logic_vector(1265,AMPL_WIDTH),
conv_std_logic_vector(1266,AMPL_WIDTH),
conv_std_logic_vector(1266,AMPL_WIDTH),
conv_std_logic_vector(1267,AMPL_WIDTH),
conv_std_logic_vector(1267,AMPL_WIDTH),
conv_std_logic_vector(1268,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1270,AMPL_WIDTH),
conv_std_logic_vector(1270,AMPL_WIDTH),
conv_std_logic_vector(1271,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1273,AMPL_WIDTH),
conv_std_logic_vector(1274,AMPL_WIDTH),
conv_std_logic_vector(1274,AMPL_WIDTH),
conv_std_logic_vector(1275,AMPL_WIDTH),
conv_std_logic_vector(1275,AMPL_WIDTH),
conv_std_logic_vector(1276,AMPL_WIDTH),
conv_std_logic_vector(1277,AMPL_WIDTH),
conv_std_logic_vector(1277,AMPL_WIDTH),
conv_std_logic_vector(1278,AMPL_WIDTH),
conv_std_logic_vector(1278,AMPL_WIDTH),
conv_std_logic_vector(1279,AMPL_WIDTH),
conv_std_logic_vector(1280,AMPL_WIDTH),
conv_std_logic_vector(1280,AMPL_WIDTH),
conv_std_logic_vector(1281,AMPL_WIDTH),
conv_std_logic_vector(1282,AMPL_WIDTH),
conv_std_logic_vector(1282,AMPL_WIDTH),
conv_std_logic_vector(1283,AMPL_WIDTH),
conv_std_logic_vector(1283,AMPL_WIDTH),
conv_std_logic_vector(1284,AMPL_WIDTH),
conv_std_logic_vector(1285,AMPL_WIDTH),
conv_std_logic_vector(1285,AMPL_WIDTH),
conv_std_logic_vector(1286,AMPL_WIDTH),
conv_std_logic_vector(1286,AMPL_WIDTH),
conv_std_logic_vector(1287,AMPL_WIDTH),
conv_std_logic_vector(1288,AMPL_WIDTH),
conv_std_logic_vector(1288,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1290,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1292,AMPL_WIDTH),
conv_std_logic_vector(1293,AMPL_WIDTH),
conv_std_logic_vector(1293,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1295,AMPL_WIDTH),
conv_std_logic_vector(1296,AMPL_WIDTH),
conv_std_logic_vector(1296,AMPL_WIDTH),
conv_std_logic_vector(1297,AMPL_WIDTH),
conv_std_logic_vector(1297,AMPL_WIDTH),
conv_std_logic_vector(1298,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1300,AMPL_WIDTH),
conv_std_logic_vector(1300,AMPL_WIDTH),
conv_std_logic_vector(1301,AMPL_WIDTH),
conv_std_logic_vector(1302,AMPL_WIDTH),
conv_std_logic_vector(1302,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1304,AMPL_WIDTH),
conv_std_logic_vector(1305,AMPL_WIDTH),
conv_std_logic_vector(1305,AMPL_WIDTH),
conv_std_logic_vector(1306,AMPL_WIDTH),
conv_std_logic_vector(1306,AMPL_WIDTH),
conv_std_logic_vector(1307,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1309,AMPL_WIDTH),
conv_std_logic_vector(1309,AMPL_WIDTH),
conv_std_logic_vector(1310,AMPL_WIDTH),
conv_std_logic_vector(1311,AMPL_WIDTH),
conv_std_logic_vector(1311,AMPL_WIDTH),
conv_std_logic_vector(1312,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1314,AMPL_WIDTH),
conv_std_logic_vector(1314,AMPL_WIDTH),
conv_std_logic_vector(1315,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1317,AMPL_WIDTH),
conv_std_logic_vector(1317,AMPL_WIDTH),
conv_std_logic_vector(1318,AMPL_WIDTH),
conv_std_logic_vector(1319,AMPL_WIDTH),
conv_std_logic_vector(1319,AMPL_WIDTH),
conv_std_logic_vector(1320,AMPL_WIDTH),
conv_std_logic_vector(1320,AMPL_WIDTH),
conv_std_logic_vector(1321,AMPL_WIDTH),
conv_std_logic_vector(1322,AMPL_WIDTH),
conv_std_logic_vector(1322,AMPL_WIDTH),
conv_std_logic_vector(1323,AMPL_WIDTH),
conv_std_logic_vector(1323,AMPL_WIDTH),
conv_std_logic_vector(1324,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1326,AMPL_WIDTH),
conv_std_logic_vector(1326,AMPL_WIDTH),
conv_std_logic_vector(1327,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1329,AMPL_WIDTH),
conv_std_logic_vector(1329,AMPL_WIDTH),
conv_std_logic_vector(1330,AMPL_WIDTH),
conv_std_logic_vector(1330,AMPL_WIDTH),
conv_std_logic_vector(1331,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1333,AMPL_WIDTH),
conv_std_logic_vector(1333,AMPL_WIDTH),
conv_std_logic_vector(1334,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1336,AMPL_WIDTH),
conv_std_logic_vector(1336,AMPL_WIDTH),
conv_std_logic_vector(1337,AMPL_WIDTH),
conv_std_logic_vector(1338,AMPL_WIDTH),
conv_std_logic_vector(1338,AMPL_WIDTH),
conv_std_logic_vector(1339,AMPL_WIDTH),
conv_std_logic_vector(1339,AMPL_WIDTH),
conv_std_logic_vector(1340,AMPL_WIDTH),
conv_std_logic_vector(1341,AMPL_WIDTH),
conv_std_logic_vector(1341,AMPL_WIDTH),
conv_std_logic_vector(1342,AMPL_WIDTH),
conv_std_logic_vector(1342,AMPL_WIDTH),
conv_std_logic_vector(1343,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1345,AMPL_WIDTH),
conv_std_logic_vector(1345,AMPL_WIDTH),
conv_std_logic_vector(1346,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1348,AMPL_WIDTH),
conv_std_logic_vector(1348,AMPL_WIDTH),
conv_std_logic_vector(1349,AMPL_WIDTH),
conv_std_logic_vector(1349,AMPL_WIDTH),
conv_std_logic_vector(1350,AMPL_WIDTH),
conv_std_logic_vector(1351,AMPL_WIDTH),
conv_std_logic_vector(1351,AMPL_WIDTH),
conv_std_logic_vector(1352,AMPL_WIDTH),
conv_std_logic_vector(1352,AMPL_WIDTH),
conv_std_logic_vector(1353,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1355,AMPL_WIDTH),
conv_std_logic_vector(1355,AMPL_WIDTH),
conv_std_logic_vector(1356,AMPL_WIDTH),
conv_std_logic_vector(1357,AMPL_WIDTH),
conv_std_logic_vector(1357,AMPL_WIDTH),
conv_std_logic_vector(1358,AMPL_WIDTH),
conv_std_logic_vector(1358,AMPL_WIDTH),
conv_std_logic_vector(1359,AMPL_WIDTH),
conv_std_logic_vector(1359,AMPL_WIDTH),
conv_std_logic_vector(1360,AMPL_WIDTH),
conv_std_logic_vector(1361,AMPL_WIDTH),
conv_std_logic_vector(1361,AMPL_WIDTH),
conv_std_logic_vector(1362,AMPL_WIDTH),
conv_std_logic_vector(1362,AMPL_WIDTH),
conv_std_logic_vector(1363,AMPL_WIDTH),
conv_std_logic_vector(1364,AMPL_WIDTH),
conv_std_logic_vector(1364,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1366,AMPL_WIDTH),
conv_std_logic_vector(1367,AMPL_WIDTH),
conv_std_logic_vector(1367,AMPL_WIDTH),
conv_std_logic_vector(1368,AMPL_WIDTH),
conv_std_logic_vector(1368,AMPL_WIDTH),
conv_std_logic_vector(1369,AMPL_WIDTH),
conv_std_logic_vector(1369,AMPL_WIDTH),
conv_std_logic_vector(1370,AMPL_WIDTH),
conv_std_logic_vector(1371,AMPL_WIDTH),
conv_std_logic_vector(1371,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1373,AMPL_WIDTH),
conv_std_logic_vector(1374,AMPL_WIDTH),
conv_std_logic_vector(1374,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1376,AMPL_WIDTH),
conv_std_logic_vector(1376,AMPL_WIDTH),
conv_std_logic_vector(1377,AMPL_WIDTH),
conv_std_logic_vector(1378,AMPL_WIDTH),
conv_std_logic_vector(1378,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1380,AMPL_WIDTH),
conv_std_logic_vector(1380,AMPL_WIDTH),
conv_std_logic_vector(1381,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1383,AMPL_WIDTH),
conv_std_logic_vector(1383,AMPL_WIDTH),
conv_std_logic_vector(1384,AMPL_WIDTH),
conv_std_logic_vector(1385,AMPL_WIDTH),
conv_std_logic_vector(1385,AMPL_WIDTH),
conv_std_logic_vector(1386,AMPL_WIDTH),
conv_std_logic_vector(1386,AMPL_WIDTH),
conv_std_logic_vector(1387,AMPL_WIDTH),
conv_std_logic_vector(1387,AMPL_WIDTH),
conv_std_logic_vector(1388,AMPL_WIDTH),
conv_std_logic_vector(1389,AMPL_WIDTH),
conv_std_logic_vector(1389,AMPL_WIDTH),
conv_std_logic_vector(1390,AMPL_WIDTH),
conv_std_logic_vector(1390,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1392,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1394,AMPL_WIDTH),
conv_std_logic_vector(1394,AMPL_WIDTH),
conv_std_logic_vector(1395,AMPL_WIDTH),
conv_std_logic_vector(1395,AMPL_WIDTH),
conv_std_logic_vector(1396,AMPL_WIDTH),
conv_std_logic_vector(1397,AMPL_WIDTH),
conv_std_logic_vector(1397,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1399,AMPL_WIDTH),
conv_std_logic_vector(1400,AMPL_WIDTH),
conv_std_logic_vector(1400,AMPL_WIDTH),
conv_std_logic_vector(1401,AMPL_WIDTH),
conv_std_logic_vector(1401,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1403,AMPL_WIDTH),
conv_std_logic_vector(1404,AMPL_WIDTH),
conv_std_logic_vector(1404,AMPL_WIDTH),
conv_std_logic_vector(1405,AMPL_WIDTH),
conv_std_logic_vector(1405,AMPL_WIDTH),
conv_std_logic_vector(1406,AMPL_WIDTH),
conv_std_logic_vector(1406,AMPL_WIDTH),
conv_std_logic_vector(1407,AMPL_WIDTH),
conv_std_logic_vector(1408,AMPL_WIDTH),
conv_std_logic_vector(1408,AMPL_WIDTH),
conv_std_logic_vector(1409,AMPL_WIDTH),
conv_std_logic_vector(1409,AMPL_WIDTH),
conv_std_logic_vector(1410,AMPL_WIDTH),
conv_std_logic_vector(1410,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1412,AMPL_WIDTH),
conv_std_logic_vector(1413,AMPL_WIDTH),
conv_std_logic_vector(1413,AMPL_WIDTH),
conv_std_logic_vector(1414,AMPL_WIDTH),
conv_std_logic_vector(1414,AMPL_WIDTH),
conv_std_logic_vector(1415,AMPL_WIDTH),
conv_std_logic_vector(1415,AMPL_WIDTH),
conv_std_logic_vector(1416,AMPL_WIDTH),
conv_std_logic_vector(1417,AMPL_WIDTH),
conv_std_logic_vector(1417,AMPL_WIDTH),
conv_std_logic_vector(1418,AMPL_WIDTH),
conv_std_logic_vector(1418,AMPL_WIDTH),
conv_std_logic_vector(1419,AMPL_WIDTH),
conv_std_logic_vector(1419,AMPL_WIDTH),
conv_std_logic_vector(1420,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1422,AMPL_WIDTH),
conv_std_logic_vector(1422,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1424,AMPL_WIDTH),
conv_std_logic_vector(1425,AMPL_WIDTH),
conv_std_logic_vector(1425,AMPL_WIDTH),
conv_std_logic_vector(1426,AMPL_WIDTH),
conv_std_logic_vector(1426,AMPL_WIDTH),
conv_std_logic_vector(1427,AMPL_WIDTH),
conv_std_logic_vector(1427,AMPL_WIDTH),
conv_std_logic_vector(1428,AMPL_WIDTH),
conv_std_logic_vector(1428,AMPL_WIDTH),
conv_std_logic_vector(1429,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1431,AMPL_WIDTH),
conv_std_logic_vector(1431,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1433,AMPL_WIDTH),
conv_std_logic_vector(1434,AMPL_WIDTH),
conv_std_logic_vector(1434,AMPL_WIDTH),
conv_std_logic_vector(1435,AMPL_WIDTH),
conv_std_logic_vector(1435,AMPL_WIDTH),
conv_std_logic_vector(1436,AMPL_WIDTH),
conv_std_logic_vector(1436,AMPL_WIDTH),
conv_std_logic_vector(1437,AMPL_WIDTH),
conv_std_logic_vector(1437,AMPL_WIDTH),
conv_std_logic_vector(1438,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1440,AMPL_WIDTH),
conv_std_logic_vector(1440,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1442,AMPL_WIDTH),
conv_std_logic_vector(1442,AMPL_WIDTH),
conv_std_logic_vector(1443,AMPL_WIDTH),
conv_std_logic_vector(1444,AMPL_WIDTH),
conv_std_logic_vector(1444,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1446,AMPL_WIDTH),
conv_std_logic_vector(1446,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1448,AMPL_WIDTH),
conv_std_logic_vector(1449,AMPL_WIDTH),
conv_std_logic_vector(1449,AMPL_WIDTH),
conv_std_logic_vector(1450,AMPL_WIDTH),
conv_std_logic_vector(1450,AMPL_WIDTH),
conv_std_logic_vector(1451,AMPL_WIDTH),
conv_std_logic_vector(1451,AMPL_WIDTH),
conv_std_logic_vector(1452,AMPL_WIDTH),
conv_std_logic_vector(1452,AMPL_WIDTH),
conv_std_logic_vector(1453,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1455,AMPL_WIDTH),
conv_std_logic_vector(1455,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1457,AMPL_WIDTH),
conv_std_logic_vector(1457,AMPL_WIDTH),
conv_std_logic_vector(1458,AMPL_WIDTH),
conv_std_logic_vector(1459,AMPL_WIDTH),
conv_std_logic_vector(1459,AMPL_WIDTH),
conv_std_logic_vector(1460,AMPL_WIDTH),
conv_std_logic_vector(1460,AMPL_WIDTH),
conv_std_logic_vector(1461,AMPL_WIDTH),
conv_std_logic_vector(1461,AMPL_WIDTH),
conv_std_logic_vector(1462,AMPL_WIDTH),
conv_std_logic_vector(1462,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1464,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1466,AMPL_WIDTH),
conv_std_logic_vector(1466,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1468,AMPL_WIDTH),
conv_std_logic_vector(1468,AMPL_WIDTH),
conv_std_logic_vector(1469,AMPL_WIDTH),
conv_std_logic_vector(1469,AMPL_WIDTH),
conv_std_logic_vector(1470,AMPL_WIDTH),
conv_std_logic_vector(1471,AMPL_WIDTH),
conv_std_logic_vector(1471,AMPL_WIDTH),
conv_std_logic_vector(1472,AMPL_WIDTH),
conv_std_logic_vector(1472,AMPL_WIDTH),
conv_std_logic_vector(1473,AMPL_WIDTH),
conv_std_logic_vector(1473,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1475,AMPL_WIDTH),
conv_std_logic_vector(1475,AMPL_WIDTH),
conv_std_logic_vector(1476,AMPL_WIDTH),
conv_std_logic_vector(1477,AMPL_WIDTH),
conv_std_logic_vector(1477,AMPL_WIDTH),
conv_std_logic_vector(1478,AMPL_WIDTH),
conv_std_logic_vector(1478,AMPL_WIDTH),
conv_std_logic_vector(1479,AMPL_WIDTH),
conv_std_logic_vector(1479,AMPL_WIDTH),
conv_std_logic_vector(1480,AMPL_WIDTH),
conv_std_logic_vector(1480,AMPL_WIDTH),
conv_std_logic_vector(1481,AMPL_WIDTH),
conv_std_logic_vector(1481,AMPL_WIDTH),
conv_std_logic_vector(1482,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1484,AMPL_WIDTH),
conv_std_logic_vector(1484,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1486,AMPL_WIDTH),
conv_std_logic_vector(1486,AMPL_WIDTH),
conv_std_logic_vector(1487,AMPL_WIDTH),
conv_std_logic_vector(1487,AMPL_WIDTH),
conv_std_logic_vector(1488,AMPL_WIDTH),
conv_std_logic_vector(1488,AMPL_WIDTH),
conv_std_logic_vector(1489,AMPL_WIDTH),
conv_std_logic_vector(1490,AMPL_WIDTH),
conv_std_logic_vector(1490,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1492,AMPL_WIDTH),
conv_std_logic_vector(1492,AMPL_WIDTH),
conv_std_logic_vector(1493,AMPL_WIDTH),
conv_std_logic_vector(1493,AMPL_WIDTH),
conv_std_logic_vector(1494,AMPL_WIDTH),
conv_std_logic_vector(1494,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1496,AMPL_WIDTH),
conv_std_logic_vector(1497,AMPL_WIDTH),
conv_std_logic_vector(1497,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1499,AMPL_WIDTH),
conv_std_logic_vector(1499,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1501,AMPL_WIDTH),
conv_std_logic_vector(1501,AMPL_WIDTH),
conv_std_logic_vector(1502,AMPL_WIDTH),
conv_std_logic_vector(1502,AMPL_WIDTH),
conv_std_logic_vector(1503,AMPL_WIDTH),
conv_std_logic_vector(1503,AMPL_WIDTH),
conv_std_logic_vector(1504,AMPL_WIDTH),
conv_std_logic_vector(1505,AMPL_WIDTH),
conv_std_logic_vector(1505,AMPL_WIDTH),
conv_std_logic_vector(1506,AMPL_WIDTH),
conv_std_logic_vector(1506,AMPL_WIDTH),
conv_std_logic_vector(1507,AMPL_WIDTH),
conv_std_logic_vector(1507,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1509,AMPL_WIDTH),
conv_std_logic_vector(1509,AMPL_WIDTH),
conv_std_logic_vector(1510,AMPL_WIDTH),
conv_std_logic_vector(1510,AMPL_WIDTH),
conv_std_logic_vector(1511,AMPL_WIDTH),
conv_std_logic_vector(1511,AMPL_WIDTH),
conv_std_logic_vector(1512,AMPL_WIDTH),
conv_std_logic_vector(1513,AMPL_WIDTH),
conv_std_logic_vector(1513,AMPL_WIDTH),
conv_std_logic_vector(1514,AMPL_WIDTH),
conv_std_logic_vector(1514,AMPL_WIDTH),
conv_std_logic_vector(1515,AMPL_WIDTH),
conv_std_logic_vector(1515,AMPL_WIDTH),
conv_std_logic_vector(1516,AMPL_WIDTH),
conv_std_logic_vector(1516,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1518,AMPL_WIDTH),
conv_std_logic_vector(1518,AMPL_WIDTH),
conv_std_logic_vector(1519,AMPL_WIDTH),
conv_std_logic_vector(1519,AMPL_WIDTH),
conv_std_logic_vector(1520,AMPL_WIDTH),
conv_std_logic_vector(1520,AMPL_WIDTH),
conv_std_logic_vector(1521,AMPL_WIDTH),
conv_std_logic_vector(1521,AMPL_WIDTH),
conv_std_logic_vector(1522,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1524,AMPL_WIDTH),
conv_std_logic_vector(1524,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1526,AMPL_WIDTH),
conv_std_logic_vector(1526,AMPL_WIDTH),
conv_std_logic_vector(1527,AMPL_WIDTH),
conv_std_logic_vector(1527,AMPL_WIDTH),
conv_std_logic_vector(1528,AMPL_WIDTH),
conv_std_logic_vector(1528,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1530,AMPL_WIDTH),
conv_std_logic_vector(1530,AMPL_WIDTH),
conv_std_logic_vector(1531,AMPL_WIDTH),
conv_std_logic_vector(1531,AMPL_WIDTH),
conv_std_logic_vector(1532,AMPL_WIDTH),
conv_std_logic_vector(1532,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1534,AMPL_WIDTH),
conv_std_logic_vector(1535,AMPL_WIDTH),
conv_std_logic_vector(1535,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1537,AMPL_WIDTH),
conv_std_logic_vector(1537,AMPL_WIDTH),
conv_std_logic_vector(1538,AMPL_WIDTH),
conv_std_logic_vector(1538,AMPL_WIDTH),
conv_std_logic_vector(1539,AMPL_WIDTH),
conv_std_logic_vector(1539,AMPL_WIDTH),
conv_std_logic_vector(1540,AMPL_WIDTH),
conv_std_logic_vector(1540,AMPL_WIDTH),
conv_std_logic_vector(1541,AMPL_WIDTH),
conv_std_logic_vector(1541,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1543,AMPL_WIDTH),
conv_std_logic_vector(1543,AMPL_WIDTH),
conv_std_logic_vector(1544,AMPL_WIDTH),
conv_std_logic_vector(1544,AMPL_WIDTH),
conv_std_logic_vector(1545,AMPL_WIDTH),
conv_std_logic_vector(1545,AMPL_WIDTH),
conv_std_logic_vector(1546,AMPL_WIDTH),
conv_std_logic_vector(1546,AMPL_WIDTH),
conv_std_logic_vector(1547,AMPL_WIDTH),
conv_std_logic_vector(1547,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1549,AMPL_WIDTH),
conv_std_logic_vector(1549,AMPL_WIDTH),
conv_std_logic_vector(1550,AMPL_WIDTH),
conv_std_logic_vector(1551,AMPL_WIDTH),
conv_std_logic_vector(1551,AMPL_WIDTH),
conv_std_logic_vector(1552,AMPL_WIDTH),
conv_std_logic_vector(1552,AMPL_WIDTH),
conv_std_logic_vector(1553,AMPL_WIDTH),
conv_std_logic_vector(1553,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1555,AMPL_WIDTH),
conv_std_logic_vector(1555,AMPL_WIDTH),
conv_std_logic_vector(1556,AMPL_WIDTH),
conv_std_logic_vector(1556,AMPL_WIDTH),
conv_std_logic_vector(1557,AMPL_WIDTH),
conv_std_logic_vector(1557,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1559,AMPL_WIDTH),
conv_std_logic_vector(1559,AMPL_WIDTH),
conv_std_logic_vector(1560,AMPL_WIDTH),
conv_std_logic_vector(1560,AMPL_WIDTH),
conv_std_logic_vector(1561,AMPL_WIDTH),
conv_std_logic_vector(1561,AMPL_WIDTH),
conv_std_logic_vector(1562,AMPL_WIDTH),
conv_std_logic_vector(1562,AMPL_WIDTH),
conv_std_logic_vector(1563,AMPL_WIDTH),
conv_std_logic_vector(1563,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1565,AMPL_WIDTH),
conv_std_logic_vector(1565,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1567,AMPL_WIDTH),
conv_std_logic_vector(1567,AMPL_WIDTH),
conv_std_logic_vector(1568,AMPL_WIDTH),
conv_std_logic_vector(1568,AMPL_WIDTH),
conv_std_logic_vector(1569,AMPL_WIDTH),
conv_std_logic_vector(1569,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1571,AMPL_WIDTH),
conv_std_logic_vector(1571,AMPL_WIDTH),
conv_std_logic_vector(1572,AMPL_WIDTH),
conv_std_logic_vector(1572,AMPL_WIDTH),
conv_std_logic_vector(1573,AMPL_WIDTH),
conv_std_logic_vector(1573,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1575,AMPL_WIDTH),
conv_std_logic_vector(1575,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1577,AMPL_WIDTH),
conv_std_logic_vector(1577,AMPL_WIDTH),
conv_std_logic_vector(1578,AMPL_WIDTH),
conv_std_logic_vector(1578,AMPL_WIDTH),
conv_std_logic_vector(1579,AMPL_WIDTH),
conv_std_logic_vector(1579,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1581,AMPL_WIDTH),
conv_std_logic_vector(1581,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1583,AMPL_WIDTH),
conv_std_logic_vector(1583,AMPL_WIDTH),
conv_std_logic_vector(1584,AMPL_WIDTH),
conv_std_logic_vector(1584,AMPL_WIDTH),
conv_std_logic_vector(1585,AMPL_WIDTH),
conv_std_logic_vector(1585,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1587,AMPL_WIDTH),
conv_std_logic_vector(1587,AMPL_WIDTH),
conv_std_logic_vector(1588,AMPL_WIDTH),
conv_std_logic_vector(1588,AMPL_WIDTH),
conv_std_logic_vector(1589,AMPL_WIDTH),
conv_std_logic_vector(1589,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1591,AMPL_WIDTH),
conv_std_logic_vector(1591,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1593,AMPL_WIDTH),
conv_std_logic_vector(1593,AMPL_WIDTH),
conv_std_logic_vector(1594,AMPL_WIDTH),
conv_std_logic_vector(1594,AMPL_WIDTH),
conv_std_logic_vector(1595,AMPL_WIDTH),
conv_std_logic_vector(1595,AMPL_WIDTH),
conv_std_logic_vector(1596,AMPL_WIDTH),
conv_std_logic_vector(1596,AMPL_WIDTH),
conv_std_logic_vector(1597,AMPL_WIDTH),
conv_std_logic_vector(1597,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1599,AMPL_WIDTH),
conv_std_logic_vector(1599,AMPL_WIDTH),
conv_std_logic_vector(1600,AMPL_WIDTH),
conv_std_logic_vector(1600,AMPL_WIDTH),
conv_std_logic_vector(1601,AMPL_WIDTH),
conv_std_logic_vector(1601,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1603,AMPL_WIDTH),
conv_std_logic_vector(1603,AMPL_WIDTH),
conv_std_logic_vector(1604,AMPL_WIDTH),
conv_std_logic_vector(1604,AMPL_WIDTH),
conv_std_logic_vector(1605,AMPL_WIDTH),
conv_std_logic_vector(1605,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1607,AMPL_WIDTH),
conv_std_logic_vector(1607,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1609,AMPL_WIDTH),
conv_std_logic_vector(1609,AMPL_WIDTH),
conv_std_logic_vector(1610,AMPL_WIDTH),
conv_std_logic_vector(1610,AMPL_WIDTH),
conv_std_logic_vector(1611,AMPL_WIDTH),
conv_std_logic_vector(1611,AMPL_WIDTH),
conv_std_logic_vector(1612,AMPL_WIDTH),
conv_std_logic_vector(1612,AMPL_WIDTH),
conv_std_logic_vector(1613,AMPL_WIDTH),
conv_std_logic_vector(1613,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1615,AMPL_WIDTH),
conv_std_logic_vector(1615,AMPL_WIDTH),
conv_std_logic_vector(1616,AMPL_WIDTH),
conv_std_logic_vector(1616,AMPL_WIDTH),
conv_std_logic_vector(1617,AMPL_WIDTH),
conv_std_logic_vector(1617,AMPL_WIDTH),
conv_std_logic_vector(1618,AMPL_WIDTH),
conv_std_logic_vector(1618,AMPL_WIDTH),
conv_std_logic_vector(1619,AMPL_WIDTH),
conv_std_logic_vector(1619,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1622,AMPL_WIDTH),
conv_std_logic_vector(1622,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1624,AMPL_WIDTH),
conv_std_logic_vector(1624,AMPL_WIDTH),
conv_std_logic_vector(1625,AMPL_WIDTH),
conv_std_logic_vector(1625,AMPL_WIDTH),
conv_std_logic_vector(1626,AMPL_WIDTH),
conv_std_logic_vector(1626,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1628,AMPL_WIDTH),
conv_std_logic_vector(1628,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1630,AMPL_WIDTH),
conv_std_logic_vector(1630,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1631,AMPL_WIDTH),
conv_std_logic_vector(1632,AMPL_WIDTH),
conv_std_logic_vector(1632,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1634,AMPL_WIDTH),
conv_std_logic_vector(1634,AMPL_WIDTH),
conv_std_logic_vector(1635,AMPL_WIDTH),
conv_std_logic_vector(1635,AMPL_WIDTH),
conv_std_logic_vector(1636,AMPL_WIDTH),
conv_std_logic_vector(1636,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1638,AMPL_WIDTH),
conv_std_logic_vector(1638,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1640,AMPL_WIDTH),
conv_std_logic_vector(1640,AMPL_WIDTH),
conv_std_logic_vector(1641,AMPL_WIDTH),
conv_std_logic_vector(1641,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1643,AMPL_WIDTH),
conv_std_logic_vector(1643,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1645,AMPL_WIDTH),
conv_std_logic_vector(1645,AMPL_WIDTH),
conv_std_logic_vector(1646,AMPL_WIDTH),
conv_std_logic_vector(1646,AMPL_WIDTH),
conv_std_logic_vector(1647,AMPL_WIDTH),
conv_std_logic_vector(1647,AMPL_WIDTH),
conv_std_logic_vector(1647,AMPL_WIDTH),
conv_std_logic_vector(1648,AMPL_WIDTH),
conv_std_logic_vector(1648,AMPL_WIDTH),
conv_std_logic_vector(1649,AMPL_WIDTH),
conv_std_logic_vector(1649,AMPL_WIDTH),
conv_std_logic_vector(1650,AMPL_WIDTH),
conv_std_logic_vector(1650,AMPL_WIDTH),
conv_std_logic_vector(1651,AMPL_WIDTH),
conv_std_logic_vector(1651,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1653,AMPL_WIDTH),
conv_std_logic_vector(1654,AMPL_WIDTH),
conv_std_logic_vector(1654,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1656,AMPL_WIDTH),
conv_std_logic_vector(1656,AMPL_WIDTH),
conv_std_logic_vector(1657,AMPL_WIDTH),
conv_std_logic_vector(1657,AMPL_WIDTH),
conv_std_logic_vector(1658,AMPL_WIDTH),
conv_std_logic_vector(1658,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1660,AMPL_WIDTH),
conv_std_logic_vector(1660,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1662,AMPL_WIDTH),
conv_std_logic_vector(1662,AMPL_WIDTH),
conv_std_logic_vector(1663,AMPL_WIDTH),
conv_std_logic_vector(1663,AMPL_WIDTH),
conv_std_logic_vector(1664,AMPL_WIDTH),
conv_std_logic_vector(1664,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1665,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1667,AMPL_WIDTH),
conv_std_logic_vector(1667,AMPL_WIDTH),
conv_std_logic_vector(1668,AMPL_WIDTH),
conv_std_logic_vector(1668,AMPL_WIDTH),
conv_std_logic_vector(1669,AMPL_WIDTH),
conv_std_logic_vector(1669,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1670,AMPL_WIDTH),
conv_std_logic_vector(1671,AMPL_WIDTH),
conv_std_logic_vector(1671,AMPL_WIDTH),
conv_std_logic_vector(1672,AMPL_WIDTH),
conv_std_logic_vector(1672,AMPL_WIDTH),
conv_std_logic_vector(1673,AMPL_WIDTH),
conv_std_logic_vector(1673,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1675,AMPL_WIDTH),
conv_std_logic_vector(1675,AMPL_WIDTH),
conv_std_logic_vector(1676,AMPL_WIDTH),
conv_std_logic_vector(1676,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1678,AMPL_WIDTH),
conv_std_logic_vector(1678,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1679,AMPL_WIDTH),
conv_std_logic_vector(1680,AMPL_WIDTH),
conv_std_logic_vector(1680,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1682,AMPL_WIDTH),
conv_std_logic_vector(1682,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1684,AMPL_WIDTH),
conv_std_logic_vector(1684,AMPL_WIDTH),
conv_std_logic_vector(1685,AMPL_WIDTH),
conv_std_logic_vector(1685,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1687,AMPL_WIDTH),
conv_std_logic_vector(1687,AMPL_WIDTH),
conv_std_logic_vector(1687,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1689,AMPL_WIDTH),
conv_std_logic_vector(1689,AMPL_WIDTH),
conv_std_logic_vector(1690,AMPL_WIDTH),
conv_std_logic_vector(1690,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1691,AMPL_WIDTH),
conv_std_logic_vector(1692,AMPL_WIDTH),
conv_std_logic_vector(1692,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1694,AMPL_WIDTH),
conv_std_logic_vector(1694,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1696,AMPL_WIDTH),
conv_std_logic_vector(1696,AMPL_WIDTH),
conv_std_logic_vector(1697,AMPL_WIDTH),
conv_std_logic_vector(1697,AMPL_WIDTH),
conv_std_logic_vector(1698,AMPL_WIDTH),
conv_std_logic_vector(1698,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1700,AMPL_WIDTH),
conv_std_logic_vector(1700,AMPL_WIDTH),
conv_std_logic_vector(1701,AMPL_WIDTH),
conv_std_logic_vector(1701,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1703,AMPL_WIDTH),
conv_std_logic_vector(1703,AMPL_WIDTH),
conv_std_logic_vector(1704,AMPL_WIDTH),
conv_std_logic_vector(1704,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1706,AMPL_WIDTH),
conv_std_logic_vector(1706,AMPL_WIDTH),
conv_std_logic_vector(1707,AMPL_WIDTH),
conv_std_logic_vector(1707,AMPL_WIDTH),
conv_std_logic_vector(1708,AMPL_WIDTH),
conv_std_logic_vector(1708,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1710,AMPL_WIDTH),
conv_std_logic_vector(1710,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1712,AMPL_WIDTH),
conv_std_logic_vector(1713,AMPL_WIDTH),
conv_std_logic_vector(1713,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1715,AMPL_WIDTH),
conv_std_logic_vector(1715,AMPL_WIDTH),
conv_std_logic_vector(1715,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1717,AMPL_WIDTH),
conv_std_logic_vector(1717,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1719,AMPL_WIDTH),
conv_std_logic_vector(1719,AMPL_WIDTH),
conv_std_logic_vector(1720,AMPL_WIDTH),
conv_std_logic_vector(1720,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1722,AMPL_WIDTH),
conv_std_logic_vector(1722,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1725,AMPL_WIDTH),
conv_std_logic_vector(1725,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1726,AMPL_WIDTH),
conv_std_logic_vector(1727,AMPL_WIDTH),
conv_std_logic_vector(1727,AMPL_WIDTH),
conv_std_logic_vector(1728,AMPL_WIDTH),
conv_std_logic_vector(1728,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1730,AMPL_WIDTH),
conv_std_logic_vector(1730,AMPL_WIDTH),
conv_std_logic_vector(1731,AMPL_WIDTH),
conv_std_logic_vector(1731,AMPL_WIDTH),
conv_std_logic_vector(1732,AMPL_WIDTH),
conv_std_logic_vector(1732,AMPL_WIDTH),
conv_std_logic_vector(1732,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1734,AMPL_WIDTH),
conv_std_logic_vector(1735,AMPL_WIDTH),
conv_std_logic_vector(1735,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1737,AMPL_WIDTH),
conv_std_logic_vector(1737,AMPL_WIDTH),
conv_std_logic_vector(1737,AMPL_WIDTH),
conv_std_logic_vector(1738,AMPL_WIDTH),
conv_std_logic_vector(1738,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1739,AMPL_WIDTH),
conv_std_logic_vector(1740,AMPL_WIDTH),
conv_std_logic_vector(1740,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1741,AMPL_WIDTH),
conv_std_logic_vector(1742,AMPL_WIDTH),
conv_std_logic_vector(1742,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1744,AMPL_WIDTH),
conv_std_logic_vector(1745,AMPL_WIDTH),
conv_std_logic_vector(1745,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1747,AMPL_WIDTH),
conv_std_logic_vector(1747,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1748,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1750,AMPL_WIDTH),
conv_std_logic_vector(1750,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1751,AMPL_WIDTH),
conv_std_logic_vector(1752,AMPL_WIDTH),
conv_std_logic_vector(1752,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1753,AMPL_WIDTH),
conv_std_logic_vector(1754,AMPL_WIDTH),
conv_std_logic_vector(1754,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1757,AMPL_WIDTH),
conv_std_logic_vector(1758,AMPL_WIDTH),
conv_std_logic_vector(1758,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1759,AMPL_WIDTH),
conv_std_logic_vector(1760,AMPL_WIDTH),
conv_std_logic_vector(1760,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1761,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1763,AMPL_WIDTH),
conv_std_logic_vector(1763,AMPL_WIDTH),
conv_std_logic_vector(1763,AMPL_WIDTH),
conv_std_logic_vector(1764,AMPL_WIDTH),
conv_std_logic_vector(1764,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1766,AMPL_WIDTH),
conv_std_logic_vector(1766,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1767,AMPL_WIDTH),
conv_std_logic_vector(1768,AMPL_WIDTH),
conv_std_logic_vector(1768,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1770,AMPL_WIDTH),
conv_std_logic_vector(1770,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1772,AMPL_WIDTH),
conv_std_logic_vector(1773,AMPL_WIDTH),
conv_std_logic_vector(1773,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1776,AMPL_WIDTH),
conv_std_logic_vector(1777,AMPL_WIDTH),
conv_std_logic_vector(1777,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1778,AMPL_WIDTH),
conv_std_logic_vector(1779,AMPL_WIDTH),
conv_std_logic_vector(1779,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1782,AMPL_WIDTH),
conv_std_logic_vector(1782,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1784,AMPL_WIDTH),
conv_std_logic_vector(1784,AMPL_WIDTH),
conv_std_logic_vector(1785,AMPL_WIDTH),
conv_std_logic_vector(1785,AMPL_WIDTH),
conv_std_logic_vector(1785,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1786,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1788,AMPL_WIDTH),
conv_std_logic_vector(1788,AMPL_WIDTH),
conv_std_logic_vector(1788,AMPL_WIDTH),
conv_std_logic_vector(1789,AMPL_WIDTH),
conv_std_logic_vector(1789,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1791,AMPL_WIDTH),
conv_std_logic_vector(1791,AMPL_WIDTH),
conv_std_logic_vector(1791,AMPL_WIDTH),
conv_std_logic_vector(1792,AMPL_WIDTH),
conv_std_logic_vector(1792,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1794,AMPL_WIDTH),
conv_std_logic_vector(1794,AMPL_WIDTH),
conv_std_logic_vector(1794,AMPL_WIDTH),
conv_std_logic_vector(1795,AMPL_WIDTH),
conv_std_logic_vector(1795,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1797,AMPL_WIDTH),
conv_std_logic_vector(1797,AMPL_WIDTH),
conv_std_logic_vector(1797,AMPL_WIDTH),
conv_std_logic_vector(1798,AMPL_WIDTH),
conv_std_logic_vector(1798,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1800,AMPL_WIDTH),
conv_std_logic_vector(1800,AMPL_WIDTH),
conv_std_logic_vector(1800,AMPL_WIDTH),
conv_std_logic_vector(1801,AMPL_WIDTH),
conv_std_logic_vector(1801,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1803,AMPL_WIDTH),
conv_std_logic_vector(1803,AMPL_WIDTH),
conv_std_logic_vector(1803,AMPL_WIDTH),
conv_std_logic_vector(1804,AMPL_WIDTH),
conv_std_logic_vector(1804,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1806,AMPL_WIDTH),
conv_std_logic_vector(1806,AMPL_WIDTH),
conv_std_logic_vector(1806,AMPL_WIDTH),
conv_std_logic_vector(1807,AMPL_WIDTH),
conv_std_logic_vector(1807,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1808,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1810,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1813,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1814,AMPL_WIDTH),
conv_std_logic_vector(1815,AMPL_WIDTH),
conv_std_logic_vector(1815,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1816,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1819,AMPL_WIDTH),
conv_std_logic_vector(1819,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1820,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1822,AMPL_WIDTH),
conv_std_logic_vector(1822,AMPL_WIDTH),
conv_std_logic_vector(1822,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1825,AMPL_WIDTH),
conv_std_logic_vector(1825,AMPL_WIDTH),
conv_std_logic_vector(1825,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1826,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1829,AMPL_WIDTH),
conv_std_logic_vector(1829,AMPL_WIDTH),
conv_std_logic_vector(1829,AMPL_WIDTH),
conv_std_logic_vector(1830,AMPL_WIDTH),
conv_std_logic_vector(1830,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1832,AMPL_WIDTH),
conv_std_logic_vector(1832,AMPL_WIDTH),
conv_std_logic_vector(1832,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1833,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1835,AMPL_WIDTH),
conv_std_logic_vector(1836,AMPL_WIDTH),
conv_std_logic_vector(1836,AMPL_WIDTH),
conv_std_logic_vector(1836,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1838,AMPL_WIDTH),
conv_std_logic_vector(1839,AMPL_WIDTH),
conv_std_logic_vector(1839,AMPL_WIDTH),
conv_std_logic_vector(1839,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1841,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1842,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1844,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1847,AMPL_WIDTH),
conv_std_logic_vector(1847,AMPL_WIDTH),
conv_std_logic_vector(1847,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1848,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1851,AMPL_WIDTH),
conv_std_logic_vector(1851,AMPL_WIDTH),
conv_std_logic_vector(1851,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1853,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1854,AMPL_WIDTH),
conv_std_logic_vector(1855,AMPL_WIDTH),
conv_std_logic_vector(1855,AMPL_WIDTH),
conv_std_logic_vector(1855,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1857,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1858,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1860,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1863,AMPL_WIDTH),
conv_std_logic_vector(1863,AMPL_WIDTH),
conv_std_logic_vector(1863,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1864,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1867,AMPL_WIDTH),
conv_std_logic_vector(1867,AMPL_WIDTH),
conv_std_logic_vector(1867,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1869,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1870,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1872,AMPL_WIDTH),
conv_std_logic_vector(1872,AMPL_WIDTH),
conv_std_logic_vector(1872,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1873,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1875,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1877,AMPL_WIDTH),
conv_std_logic_vector(1877,AMPL_WIDTH),
conv_std_logic_vector(1877,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1879,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1880,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1882,AMPL_WIDTH),
conv_std_logic_vector(1882,AMPL_WIDTH),
conv_std_logic_vector(1882,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1883,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1885,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1888,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1889,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1892,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1894,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1895,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1897,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1898,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1899,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1902,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1904,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1907,AMPL_WIDTH),
conv_std_logic_vector(1907,AMPL_WIDTH),
conv_std_logic_vector(1907,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1908,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1911,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1913,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1916,AMPL_WIDTH),
conv_std_logic_vector(1916,AMPL_WIDTH),
conv_std_logic_vector(1916,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1917,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1920,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1922,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1924,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1926,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1929,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1930,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1933,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1935,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1938,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1939,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1941,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1942,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1945,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1946,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1949,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1952,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1954,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1957,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1958,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1960,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1961,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1963,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1964,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1967,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1968,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1970,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1971,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1974,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1977,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1980,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1982,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1985,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1988,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1991,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1993,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1995,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1996,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1998,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(1999,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2001,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2002,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2004,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2007,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2011,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2013,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2014,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2018,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2020,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2024,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2026,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2029,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/Complex3Multiply_block3.vhd
|
1
|
12388
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/Complex3Multiply_block3.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Complex3Multiply_block3
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3/Complex3Multiply
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY Complex3Multiply_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_vld_dly3 : IN std_logic;
twdl_3_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin1_vld : OUT std_logic
);
END Complex3Multiply_block3;
ARCHITECTURE rtl OF Complex3Multiply_block3 IS
-- Signals
SIGNAL din1_re_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly3_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL din_sum : signed(17 DOWNTO 0); -- sfix18
SIGNAL twdl_3_7_re_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_re_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_7_im_signed : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_im_reg : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL adder_add_cast : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL adder_add_cast_1 : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL twdl_sum : signed(17 DOWNTO 0); -- sfix18_En15
SIGNAL Complex3Multiply_din1_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_din1_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL Complex3Multiply_prodOfRe_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_ProdOfIm_pipe1 : signed(33 DOWNTO 0); -- sfix34
SIGNAL Complex3Multiply_prodOfSum_pipe1 : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Multiply_twiddle_re_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_im_pipe1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL Complex3Multiply_twiddle_sum_pipe1 : signed(17 DOWNTO 0); -- sfix18
SIGNAL prodOfRe : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfIm : signed(33 DOWNTO 0); -- sfix34_En15
SIGNAL prodOfSum : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL din_vld_dly1 : std_logic;
SIGNAL din_vld_dly2 : std_logic;
SIGNAL din_vld_dly3 : std_logic;
SIGNAL prod_vld : std_logic;
SIGNAL Complex3Add_tmpResult_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_multRes_re_reg1 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_re_reg2 : signed(34 DOWNTO 0); -- sfix35
SIGNAL Complex3Add_multRes_im_reg : signed(36 DOWNTO 0); -- sfix37
SIGNAL Complex3Add_prod_vld_reg1 : std_logic;
SIGNAL Complex3Add_prod_vld_reg2 : std_logic;
SIGNAL Complex3Add_prodOfSum_reg : signed(35 DOWNTO 0); -- sfix36
SIGNAL Complex3Add_tmpResult_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL Complex3Add_multRes_re_reg1_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_re_reg2_next : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL Complex3Add_multRes_im_reg_next : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL Complex3Add_prod_vld_reg1_next : std_logic;
SIGNAL Complex3Add_prod_vld_reg2_next : std_logic;
SIGNAL Complex3Add_prodOfSum_reg_next : signed(35 DOWNTO 0); -- sfix36_En15
SIGNAL multResFP_re : signed(34 DOWNTO 0); -- sfix35_En15
SIGNAL multResFP_im : signed(36 DOWNTO 0); -- sfix37_En15
SIGNAL twdlXdin_7_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_7_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
din1_re_dly3_signed <= signed(din1_re_dly3);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_re_reg <= to_signed(16#00000#, 17);
ELSE
din_re_reg <= din1_re_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_process;
din1_im_dly3_signed <= signed(din1_im_dly3);
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
din_im_reg <= to_signed(16#00000#, 17);
ELSE
din_im_reg <= din1_im_dly3_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_1_process;
din_sum <= resize(din_re_reg, 18) + resize(din_im_reg, 18);
twdl_3_7_re_signed <= signed(twdl_3_7_re);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_re_reg <= to_signed(16#00000#, 17);
ELSE
twdl_re_reg <= twdl_3_7_re_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_2_process;
twdl_3_7_im_signed <= signed(twdl_3_7_im);
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF softReset = '1' THEN
twdl_im_reg <= to_signed(16#00000#, 17);
ELSE
twdl_im_reg <= twdl_3_7_im_signed;
END IF;
END IF;
END IF;
END PROCESS intdelay_3_process;
adder_add_cast <= resize(twdl_re_reg, 18);
adder_add_cast_1 <= resize(twdl_im_reg, 18);
twdl_sum <= adder_add_cast + adder_add_cast_1;
-- Complex3Multiply
Complex3Multiply_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prodOfRe <= Complex3Multiply_prodOfRe_pipe1;
prodOfIm <= Complex3Multiply_ProdOfIm_pipe1;
prodOfSum <= Complex3Multiply_prodOfSum_pipe1;
Complex3Multiply_twiddle_re_pipe1 <= twdl_re_reg;
Complex3Multiply_twiddle_im_pipe1 <= twdl_im_reg;
Complex3Multiply_twiddle_sum_pipe1 <= twdl_sum;
Complex3Multiply_din1_re_pipe1 <= din_re_reg;
Complex3Multiply_din1_im_pipe1 <= din_im_reg;
Complex3Multiply_din1_sum_pipe1 <= din_sum;
Complex3Multiply_prodOfRe_pipe1 <= Complex3Multiply_din1_re_pipe1 * Complex3Multiply_twiddle_re_pipe1;
Complex3Multiply_ProdOfIm_pipe1 <= Complex3Multiply_din1_im_pipe1 * Complex3Multiply_twiddle_im_pipe1;
Complex3Multiply_prodOfSum_pipe1 <= Complex3Multiply_din1_sum_pipe1 * Complex3Multiply_twiddle_sum_pipe1;
END IF;
END IF;
END PROCESS Complex3Multiply_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly1 <= din1_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly2 <= din_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din_vld_dly3 <= din_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
prod_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
prod_vld <= din_vld_dly3;
END IF;
END IF;
END PROCESS intdelay_7_process;
-- Complex3Add
Complex3Add_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Complex3Add_prodOfSum_reg <= to_signed(0, 36);
Complex3Add_tmpResult_reg <= to_signed(0, 36);
Complex3Add_multRes_re_reg1 <= to_signed(0, 35);
Complex3Add_multRes_re_reg2 <= to_signed(0, 35);
Complex3Add_multRes_im_reg <= to_signed(0, 37);
Complex3Add_prod_vld_reg1 <= '0';
Complex3Add_prod_vld_reg2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Complex3Add_tmpResult_reg <= Complex3Add_tmpResult_reg_next;
Complex3Add_multRes_re_reg1 <= Complex3Add_multRes_re_reg1_next;
Complex3Add_multRes_re_reg2 <= Complex3Add_multRes_re_reg2_next;
Complex3Add_multRes_im_reg <= Complex3Add_multRes_im_reg_next;
Complex3Add_prod_vld_reg1 <= Complex3Add_prod_vld_reg1_next;
Complex3Add_prod_vld_reg2 <= Complex3Add_prod_vld_reg2_next;
Complex3Add_prodOfSum_reg <= Complex3Add_prodOfSum_reg_next;
END IF;
END IF;
END PROCESS Complex3Add_process;
Complex3Add_output : PROCESS (Complex3Add_tmpResult_reg, Complex3Add_multRes_re_reg1,
Complex3Add_multRes_re_reg2, Complex3Add_multRes_im_reg,
Complex3Add_prod_vld_reg1, Complex3Add_prod_vld_reg2,
Complex3Add_prodOfSum_reg, prodOfRe, prodOfIm, prodOfSum, prod_vld)
VARIABLE sub_cast : signed(34 DOWNTO 0);
VARIABLE sub_cast_0 : signed(34 DOWNTO 0);
VARIABLE sub_cast_1 : signed(36 DOWNTO 0);
VARIABLE sub_cast_2 : signed(36 DOWNTO 0);
VARIABLE add_cast : signed(34 DOWNTO 0);
VARIABLE add_cast_0 : signed(34 DOWNTO 0);
VARIABLE add_temp : signed(34 DOWNTO 0);
BEGIN
Complex3Add_tmpResult_reg_next <= Complex3Add_tmpResult_reg;
Complex3Add_multRes_re_reg1_next <= Complex3Add_multRes_re_reg1;
Complex3Add_prodOfSum_reg_next <= Complex3Add_prodOfSum_reg;
Complex3Add_multRes_re_reg2_next <= Complex3Add_multRes_re_reg1;
IF prod_vld = '1' THEN
sub_cast := resize(prodOfRe, 35);
sub_cast_0 := resize(prodOfIm, 35);
Complex3Add_multRes_re_reg1_next <= sub_cast - sub_cast_0;
END IF;
sub_cast_1 := resize(Complex3Add_prodOfSum_reg, 37);
sub_cast_2 := resize(Complex3Add_tmpResult_reg, 37);
Complex3Add_multRes_im_reg_next <= sub_cast_1 - sub_cast_2;
IF prod_vld = '1' THEN
add_cast := resize(prodOfRe, 35);
add_cast_0 := resize(prodOfIm, 35);
add_temp := add_cast + add_cast_0;
Complex3Add_tmpResult_reg_next <= resize(add_temp, 36);
END IF;
IF prod_vld = '1' THEN
Complex3Add_prodOfSum_reg_next <= prodOfSum;
END IF;
Complex3Add_prod_vld_reg2_next <= Complex3Add_prod_vld_reg1;
Complex3Add_prod_vld_reg1_next <= prod_vld;
multResFP_re <= Complex3Add_multRes_re_reg2;
multResFP_im <= Complex3Add_multRes_im_reg;
twdlXdin1_vld <= Complex3Add_prod_vld_reg2;
END PROCESS Complex3Add_output;
twdlXdin_7_re_tmp <= multResFP_re(31 DOWNTO 15);
twdlXdin_7_re <= std_logic_vector(twdlXdin_7_re_tmp);
twdlXdin_7_im_tmp <= multResFP_im(31 DOWNTO 15);
twdlXdin_7_im <= std_logic_vector(twdlXdin_7_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3_block1.vhd
|
1
|
6707
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_3_block1.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block1
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_5_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_5_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_5_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_6_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_6_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_5_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block1 IS
-- Signals
SIGNAL twdlXdin_5_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_5_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_7_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_7_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_5_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_5_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_6_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_6_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_5_re_signed <= signed(twdlXdin_5_re);
twdlXdin_5_im_signed <= signed(twdlXdin_5_im);
twdlXdin_7_re_signed <= signed(twdlXdin_7_re);
twdlXdin_7_im_signed <= signed(twdlXdin_7_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_5_re_signed,
twdlXdin_5_im_signed, twdlXdin_7_re_signed, twdlXdin_7_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_5_re_signed, 18) + resize(twdlXdin_7_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_5_re_signed, 18) - resize(twdlXdin_7_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_5_im_signed, 18) + resize(twdlXdin_7_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_5_im_signed, 18) - resize(twdlXdin_7_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_5_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_5_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_6_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_6_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_5_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_5_re <= std_logic_vector(dout_5_re_tmp);
dout_5_im <= std_logic_vector(dout_5_im_tmp);
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_modulator/real_carrier_wave.vhd
|
1
|
19503
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_modulator/real_carrier_wave.vhd
-- Created: 2018-02-07 20:06:23
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: real_carrier_wave
-- Source Path: hdl_modulator/real_carrier_wave
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_modulator_pac.ALL;
ENTITY real_carrier_wave IS
PORT( u_u : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
x_x : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END real_carrier_wave;
ARCHITECTURE rtl OF real_carrier_wave IS
-- Constants
CONSTANT nc : vector_of_signed16(0 TO 511) :=
(to_signed(16#0000#, 16), to_signed(16#0032#, 16), to_signed(16#0065#, 16), to_signed(16#0097#, 16),
to_signed(16#00C9#, 16), to_signed(16#00FC#, 16), to_signed(16#012E#, 16), to_signed(16#0161#, 16),
to_signed(16#0193#, 16), to_signed(16#01C5#, 16), to_signed(16#01F8#, 16), to_signed(16#022A#, 16),
to_signed(16#025C#, 16), to_signed(16#028F#, 16), to_signed(16#02C1#, 16), to_signed(16#02F3#, 16),
to_signed(16#0325#, 16), to_signed(16#0358#, 16), to_signed(16#038A#, 16), to_signed(16#03BC#, 16),
to_signed(16#03EF#, 16), to_signed(16#0421#, 16), to_signed(16#0453#, 16), to_signed(16#0485#, 16),
to_signed(16#04B8#, 16), to_signed(16#04EA#, 16), to_signed(16#051C#, 16), to_signed(16#054E#, 16),
to_signed(16#0580#, 16), to_signed(16#05B3#, 16), to_signed(16#05E5#, 16), to_signed(16#0617#, 16),
to_signed(16#0649#, 16), to_signed(16#067B#, 16), to_signed(16#06AD#, 16), to_signed(16#06DF#, 16),
to_signed(16#0711#, 16), to_signed(16#0743#, 16), to_signed(16#0775#, 16), to_signed(16#07A7#, 16),
to_signed(16#07D9#, 16), to_signed(16#080B#, 16), to_signed(16#083D#, 16), to_signed(16#086F#, 16),
to_signed(16#08A1#, 16), to_signed(16#08D3#, 16), to_signed(16#0905#, 16), to_signed(16#0937#, 16),
to_signed(16#0969#, 16), to_signed(16#099B#, 16), to_signed(16#09CC#, 16), to_signed(16#09FE#, 16),
to_signed(16#0A30#, 16), to_signed(16#0A61#, 16), to_signed(16#0A93#, 16), to_signed(16#0AC5#, 16),
to_signed(16#0AF6#, 16), to_signed(16#0B28#, 16), to_signed(16#0B5A#, 16), to_signed(16#0B8B#, 16),
to_signed(16#0BBD#, 16), to_signed(16#0BEE#, 16), to_signed(16#0C20#, 16), to_signed(16#0C51#, 16),
to_signed(16#0C83#, 16), to_signed(16#0CB4#, 16), to_signed(16#0CE5#, 16), to_signed(16#0D17#, 16),
to_signed(16#0D48#, 16), to_signed(16#0D79#, 16), to_signed(16#0DAA#, 16), to_signed(16#0DDC#, 16),
to_signed(16#0E0D#, 16), to_signed(16#0E3E#, 16), to_signed(16#0E6F#, 16), to_signed(16#0EA0#, 16),
to_signed(16#0ED1#, 16), to_signed(16#0F02#, 16), to_signed(16#0F33#, 16), to_signed(16#0F64#, 16),
to_signed(16#0F95#, 16), to_signed(16#0FC5#, 16), to_signed(16#0FF6#, 16), to_signed(16#1027#, 16),
to_signed(16#1058#, 16), to_signed(16#1088#, 16), to_signed(16#10B9#, 16), to_signed(16#10EA#, 16),
to_signed(16#111A#, 16), to_signed(16#114B#, 16), to_signed(16#117B#, 16), to_signed(16#11AC#, 16),
to_signed(16#11DC#, 16), to_signed(16#120C#, 16), to_signed(16#123D#, 16), to_signed(16#126D#, 16),
to_signed(16#129D#, 16), to_signed(16#12CD#, 16), to_signed(16#12FD#, 16), to_signed(16#132D#, 16),
to_signed(16#135D#, 16), to_signed(16#138D#, 16), to_signed(16#13BD#, 16), to_signed(16#13ED#, 16),
to_signed(16#141D#, 16), to_signed(16#144D#, 16), to_signed(16#147D#, 16), to_signed(16#14AC#, 16),
to_signed(16#14DC#, 16), to_signed(16#150C#, 16), to_signed(16#153B#, 16), to_signed(16#156B#, 16),
to_signed(16#159A#, 16), to_signed(16#15C9#, 16), to_signed(16#15F9#, 16), to_signed(16#1628#, 16),
to_signed(16#1657#, 16), to_signed(16#1686#, 16), to_signed(16#16B5#, 16), to_signed(16#16E5#, 16),
to_signed(16#1714#, 16), to_signed(16#1742#, 16), to_signed(16#1771#, 16), to_signed(16#17A0#, 16),
to_signed(16#17CF#, 16), to_signed(16#17FE#, 16), to_signed(16#182C#, 16), to_signed(16#185B#, 16),
to_signed(16#188A#, 16), to_signed(16#18B8#, 16), to_signed(16#18E6#, 16), to_signed(16#1915#, 16),
to_signed(16#1943#, 16), to_signed(16#1971#, 16), to_signed(16#19A0#, 16), to_signed(16#19CE#, 16),
to_signed(16#19FC#, 16), to_signed(16#1A2A#, 16), to_signed(16#1A58#, 16), to_signed(16#1A85#, 16),
to_signed(16#1AB3#, 16), to_signed(16#1AE1#, 16), to_signed(16#1B0F#, 16), to_signed(16#1B3C#, 16),
to_signed(16#1B6A#, 16), to_signed(16#1B97#, 16), to_signed(16#1BC5#, 16), to_signed(16#1BF2#, 16),
to_signed(16#1C1F#, 16), to_signed(16#1C4D#, 16), to_signed(16#1C7A#, 16), to_signed(16#1CA7#, 16),
to_signed(16#1CD4#, 16), to_signed(16#1D01#, 16), to_signed(16#1D2E#, 16), to_signed(16#1D5A#, 16),
to_signed(16#1D87#, 16), to_signed(16#1DB4#, 16), to_signed(16#1DE0#, 16), to_signed(16#1E0D#, 16),
to_signed(16#1E39#, 16), to_signed(16#1E66#, 16), to_signed(16#1E92#, 16), to_signed(16#1EBE#, 16),
to_signed(16#1EEA#, 16), to_signed(16#1F16#, 16), to_signed(16#1F42#, 16), to_signed(16#1F6E#, 16),
to_signed(16#1F9A#, 16), to_signed(16#1FC6#, 16), to_signed(16#1FF1#, 16), to_signed(16#201D#, 16),
to_signed(16#2049#, 16), to_signed(16#2074#, 16), to_signed(16#209F#, 16), to_signed(16#20CB#, 16),
to_signed(16#20F6#, 16), to_signed(16#2121#, 16), to_signed(16#214C#, 16), to_signed(16#2177#, 16),
to_signed(16#21A2#, 16), to_signed(16#21CD#, 16), to_signed(16#21F7#, 16), to_signed(16#2222#, 16),
to_signed(16#224D#, 16), to_signed(16#2277#, 16), to_signed(16#22A2#, 16), to_signed(16#22CC#, 16),
to_signed(16#22F6#, 16), to_signed(16#2320#, 16), to_signed(16#234A#, 16), to_signed(16#2374#, 16),
to_signed(16#239E#, 16), to_signed(16#23C8#, 16), to_signed(16#23F2#, 16), to_signed(16#241B#, 16),
to_signed(16#2445#, 16), to_signed(16#246E#, 16), to_signed(16#2498#, 16), to_signed(16#24C1#, 16),
to_signed(16#24EA#, 16), to_signed(16#2513#, 16), to_signed(16#253C#, 16), to_signed(16#2565#, 16),
to_signed(16#258E#, 16), to_signed(16#25B7#, 16), to_signed(16#25DF#, 16), to_signed(16#2608#, 16),
to_signed(16#2630#, 16), to_signed(16#2659#, 16), to_signed(16#2681#, 16), to_signed(16#26A9#, 16),
to_signed(16#26D1#, 16), to_signed(16#26F9#, 16), to_signed(16#2721#, 16), to_signed(16#2749#, 16),
to_signed(16#2771#, 16), to_signed(16#2798#, 16), to_signed(16#27C0#, 16), to_signed(16#27E7#, 16),
to_signed(16#280F#, 16), to_signed(16#2836#, 16), to_signed(16#285D#, 16), to_signed(16#2884#, 16),
to_signed(16#28AB#, 16), to_signed(16#28D2#, 16), to_signed(16#28F9#, 16), to_signed(16#291F#, 16),
to_signed(16#2946#, 16), to_signed(16#296C#, 16), to_signed(16#2992#, 16), to_signed(16#29B9#, 16),
to_signed(16#29DF#, 16), to_signed(16#2A05#, 16), to_signed(16#2A2B#, 16), to_signed(16#2A51#, 16),
to_signed(16#2A76#, 16), to_signed(16#2A9C#, 16), to_signed(16#2AC2#, 16), to_signed(16#2AE7#, 16),
to_signed(16#2B0C#, 16), to_signed(16#2B32#, 16), to_signed(16#2B57#, 16), to_signed(16#2B7C#, 16),
to_signed(16#2BA1#, 16), to_signed(16#2BC5#, 16), to_signed(16#2BEA#, 16), to_signed(16#2C0F#, 16),
to_signed(16#2C33#, 16), to_signed(16#2C57#, 16), to_signed(16#2C7C#, 16), to_signed(16#2CA0#, 16),
to_signed(16#2CC4#, 16), to_signed(16#2CE8#, 16), to_signed(16#2D0C#, 16), to_signed(16#2D2F#, 16),
to_signed(16#2D53#, 16), to_signed(16#2D77#, 16), to_signed(16#2D9A#, 16), to_signed(16#2DBD#, 16),
to_signed(16#2DE0#, 16), to_signed(16#2E03#, 16), to_signed(16#2E26#, 16), to_signed(16#2E49#, 16),
to_signed(16#2E6C#, 16), to_signed(16#2E8F#, 16), to_signed(16#2EB1#, 16), to_signed(16#2ED3#, 16),
to_signed(16#2EF6#, 16), to_signed(16#2F18#, 16), to_signed(16#2F3A#, 16), to_signed(16#2F5C#, 16),
to_signed(16#2F7E#, 16), to_signed(16#2F9F#, 16), to_signed(16#2FC1#, 16), to_signed(16#2FE2#, 16),
to_signed(16#3004#, 16), to_signed(16#3025#, 16), to_signed(16#3046#, 16), to_signed(16#3067#, 16),
to_signed(16#3088#, 16), to_signed(16#30A9#, 16), to_signed(16#30CA#, 16), to_signed(16#30EA#, 16),
to_signed(16#310A#, 16), to_signed(16#312B#, 16), to_signed(16#314B#, 16), to_signed(16#316B#, 16),
to_signed(16#318B#, 16), to_signed(16#31AB#, 16), to_signed(16#31CA#, 16), to_signed(16#31EA#, 16),
to_signed(16#320A#, 16), to_signed(16#3229#, 16), to_signed(16#3248#, 16), to_signed(16#3267#, 16),
to_signed(16#3286#, 16), to_signed(16#32A5#, 16), to_signed(16#32C4#, 16), to_signed(16#32E2#, 16),
to_signed(16#3301#, 16), to_signed(16#331F#, 16), to_signed(16#333D#, 16), to_signed(16#335C#, 16),
to_signed(16#337A#, 16), to_signed(16#3397#, 16), to_signed(16#33B5#, 16), to_signed(16#33D3#, 16),
to_signed(16#33F0#, 16), to_signed(16#340E#, 16), to_signed(16#342B#, 16), to_signed(16#3448#, 16),
to_signed(16#3465#, 16), to_signed(16#3482#, 16), to_signed(16#349F#, 16), to_signed(16#34BB#, 16),
to_signed(16#34D8#, 16), to_signed(16#34F4#, 16), to_signed(16#3510#, 16), to_signed(16#352C#, 16),
to_signed(16#3548#, 16), to_signed(16#3564#, 16), to_signed(16#3580#, 16), to_signed(16#359B#, 16),
to_signed(16#35B7#, 16), to_signed(16#35D2#, 16), to_signed(16#35ED#, 16), to_signed(16#3608#, 16),
to_signed(16#3623#, 16), to_signed(16#363E#, 16), to_signed(16#3659#, 16), to_signed(16#3673#, 16),
to_signed(16#368E#, 16), to_signed(16#36A8#, 16), to_signed(16#36C2#, 16), to_signed(16#36DC#, 16),
to_signed(16#36F6#, 16), to_signed(16#3710#, 16), to_signed(16#3729#, 16), to_signed(16#3743#, 16),
to_signed(16#375C#, 16), to_signed(16#3775#, 16), to_signed(16#378E#, 16), to_signed(16#37A7#, 16),
to_signed(16#37C0#, 16), to_signed(16#37D9#, 16), to_signed(16#37F1#, 16), to_signed(16#380A#, 16),
to_signed(16#3822#, 16), to_signed(16#383A#, 16), to_signed(16#3852#, 16), to_signed(16#386A#, 16),
to_signed(16#3882#, 16), to_signed(16#3899#, 16), to_signed(16#38B1#, 16), to_signed(16#38C8#, 16),
to_signed(16#38DF#, 16), to_signed(16#38F6#, 16), to_signed(16#390D#, 16), to_signed(16#3924#, 16),
to_signed(16#393A#, 16), to_signed(16#3951#, 16), to_signed(16#3967#, 16), to_signed(16#397D#, 16),
to_signed(16#3994#, 16), to_signed(16#39A9#, 16), to_signed(16#39BF#, 16), to_signed(16#39D5#, 16),
to_signed(16#39EA#, 16), to_signed(16#3A00#, 16), to_signed(16#3A15#, 16), to_signed(16#3A2A#, 16),
to_signed(16#3A3F#, 16), to_signed(16#3A54#, 16), to_signed(16#3A68#, 16), to_signed(16#3A7D#, 16),
to_signed(16#3A91#, 16), to_signed(16#3AA6#, 16), to_signed(16#3ABA#, 16), to_signed(16#3ACE#, 16),
to_signed(16#3AE1#, 16), to_signed(16#3AF5#, 16), to_signed(16#3B09#, 16), to_signed(16#3B1C#, 16),
to_signed(16#3B2F#, 16), to_signed(16#3B42#, 16), to_signed(16#3B55#, 16), to_signed(16#3B68#, 16),
to_signed(16#3B7B#, 16), to_signed(16#3B8D#, 16), to_signed(16#3BA0#, 16), to_signed(16#3BB2#, 16),
to_signed(16#3BC4#, 16), to_signed(16#3BD6#, 16), to_signed(16#3BE8#, 16), to_signed(16#3BF9#, 16),
to_signed(16#3C0B#, 16), to_signed(16#3C1C#, 16), to_signed(16#3C2D#, 16), to_signed(16#3C3F#, 16),
to_signed(16#3C4F#, 16), to_signed(16#3C60#, 16), to_signed(16#3C71#, 16), to_signed(16#3C81#, 16),
to_signed(16#3C92#, 16), to_signed(16#3CA2#, 16), to_signed(16#3CB2#, 16), to_signed(16#3CC2#, 16),
to_signed(16#3CD2#, 16), to_signed(16#3CE1#, 16), to_signed(16#3CF1#, 16), to_signed(16#3D00#, 16),
to_signed(16#3D0F#, 16), to_signed(16#3D1E#, 16), to_signed(16#3D2D#, 16), to_signed(16#3D3C#, 16),
to_signed(16#3D4A#, 16), to_signed(16#3D59#, 16), to_signed(16#3D67#, 16), to_signed(16#3D75#, 16),
to_signed(16#3D83#, 16), to_signed(16#3D91#, 16), to_signed(16#3D9F#, 16), to_signed(16#3DAC#, 16),
to_signed(16#3DBA#, 16), to_signed(16#3DC7#, 16), to_signed(16#3DD4#, 16), to_signed(16#3DE1#, 16),
to_signed(16#3DEE#, 16), to_signed(16#3DFA#, 16), to_signed(16#3E07#, 16), to_signed(16#3E13#, 16),
to_signed(16#3E1F#, 16), to_signed(16#3E2B#, 16), to_signed(16#3E37#, 16), to_signed(16#3E43#, 16),
to_signed(16#3E4F#, 16), to_signed(16#3E5A#, 16), to_signed(16#3E65#, 16), to_signed(16#3E70#, 16),
to_signed(16#3E7B#, 16), to_signed(16#3E86#, 16), to_signed(16#3E91#, 16), to_signed(16#3E9B#, 16),
to_signed(16#3EA6#, 16), to_signed(16#3EB0#, 16), to_signed(16#3EBA#, 16), to_signed(16#3EC4#, 16),
to_signed(16#3ECE#, 16), to_signed(16#3ED7#, 16), to_signed(16#3EE1#, 16), to_signed(16#3EEA#, 16),
to_signed(16#3EF3#, 16), to_signed(16#3EFC#, 16), to_signed(16#3F05#, 16), to_signed(16#3F0E#, 16),
to_signed(16#3F16#, 16), to_signed(16#3F1F#, 16), to_signed(16#3F27#, 16), to_signed(16#3F2F#, 16),
to_signed(16#3F37#, 16), to_signed(16#3F3F#, 16), to_signed(16#3F46#, 16), to_signed(16#3F4E#, 16),
to_signed(16#3F55#, 16), to_signed(16#3F5C#, 16), to_signed(16#3F63#, 16), to_signed(16#3F6A#, 16),
to_signed(16#3F71#, 16), to_signed(16#3F78#, 16), to_signed(16#3F7E#, 16), to_signed(16#3F84#, 16),
to_signed(16#3F8A#, 16), to_signed(16#3F90#, 16), to_signed(16#3F96#, 16), to_signed(16#3F9C#, 16),
to_signed(16#3FA1#, 16), to_signed(16#3FA7#, 16), to_signed(16#3FAC#, 16), to_signed(16#3FB1#, 16),
to_signed(16#3FB6#, 16), to_signed(16#3FBA#, 16), to_signed(16#3FBF#, 16), to_signed(16#3FC3#, 16),
to_signed(16#3FC8#, 16), to_signed(16#3FCC#, 16), to_signed(16#3FD0#, 16), to_signed(16#3FD3#, 16),
to_signed(16#3FD7#, 16), to_signed(16#3FDB#, 16), to_signed(16#3FDE#, 16), to_signed(16#3FE1#, 16),
to_signed(16#3FE4#, 16), to_signed(16#3FE7#, 16), to_signed(16#3FEA#, 16), to_signed(16#3FEC#, 16),
to_signed(16#3FEF#, 16), to_signed(16#3FF1#, 16), to_signed(16#3FF3#, 16), to_signed(16#3FF5#, 16),
to_signed(16#3FF7#, 16), to_signed(16#3FF8#, 16), to_signed(16#3FFA#, 16), to_signed(16#3FFB#, 16),
to_signed(16#3FFC#, 16), to_signed(16#3FFD#, 16), to_signed(16#3FFE#, 16), to_signed(16#3FFF#, 16),
to_signed(16#3FFF#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16), to_signed(16#4000#, 16));
-- sfix16 [512]
-- Signals
SIGNAL u_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL insig_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL Point50_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp50_1_cast : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp50_relop1 : std_logic;
SIGNAL pow2switch_out1 : std_logic;
SIGNAL Amp50_sub_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp50_sub_cast_1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Amp50_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL insig_out1_dtc : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL QuadHandle1_out1 : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL Point25_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL LTEp25_1_cast : signed(16 DOWNTO 0); -- sfix17_En16
SIGNAL LTEp25_relop1 : std_logic;
SIGNAL p50mA_sub_cast : signed(17 DOWNTO 0); -- sfix18_En16
SIGNAL p50mA_sub_cast_1 : signed(17 DOWNTO 0); -- sfix18_En16
SIGNAL p50mA_out1 : signed(17 DOWNTO 0); -- sfix18_En16
SIGNAL p50mA_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle1_out1_dtc : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL QuadHandle2_out1 : unsigned(8 DOWNTO 0); -- ufix9_En9
SIGNAL CastU16En2_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL CastU16En4_out1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL x4_out1 : unsigned(9 DOWNTO 0); -- ufix10
SIGNAL CastU16En3_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Switch_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_k : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Look_Up_Table_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Negate_cast : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_cast_1 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL Negate_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Sine : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Sine_1 : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- (C) 2016 Mathworks, Inc
u_signed <= signed(u_u);
insig_out1 <= unsigned(u_signed(13 DOWNTO 5));
Point50_out1 <= to_unsigned(16#8000#, 16);
LTEp50_1_cast <= insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0';
LTEp50_relop1 <= '1' WHEN LTEp50_1_cast <= Point50_out1 ELSE
'0';
pow2switch_out1 <= '0';
Amp50_sub_cast <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
Amp50_sub_cast_1 <= signed(resize(Point50_out1, 17));
Amp50_out1 <= Amp50_sub_cast - Amp50_sub_cast_1;
insig_out1_dtc <= signed(resize(insig_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0', 17));
QuadHandle1_out1 <= Amp50_out1 WHEN LTEp50_relop1 = '0' ELSE
insig_out1_dtc;
Point25_out1 <= to_unsigned(16#4000#, 16);
LTEp25_1_cast <= signed(resize(Point25_out1, 17));
LTEp25_relop1 <= '1' WHEN QuadHandle1_out1 <= LTEp25_1_cast ELSE
'0';
p50mA_sub_cast <= signed(resize(Point50_out1, 18));
p50mA_sub_cast_1 <= resize(QuadHandle1_out1, 18);
p50mA_out1 <= p50mA_sub_cast - p50mA_sub_cast_1;
p50mA_out1_dtc <= unsigned(p50mA_out1(15 DOWNTO 7));
QuadHandle1_out1_dtc <= unsigned(QuadHandle1_out1(15 DOWNTO 7));
QuadHandle2_out1 <= p50mA_out1_dtc WHEN LTEp25_relop1 = '0' ELSE
QuadHandle1_out1_dtc;
CastU16En2_out1 <= QuadHandle2_out1;
CastU16En4_out1 <= resize(CastU16En2_out1, 10);
-- equivalent to multiply
-- by 4 with saturation
x4_out1 <= CastU16En4_out1 sll 2;
-- saturation block maybe optimized away
-- if the NumDataPoints is a power of 2
CastU16En3_out1 <= "111111111" WHEN x4_out1(9) /= '0' ELSE
x4_out1(8 DOWNTO 0);
Switch_out1 <= CastU16En3_out1 WHEN pow2switch_out1 = '0' ELSE
CastU16En3_out1;
Look_Up_Table_k <= to_unsigned(16#000#, 9) WHEN Switch_out1 = to_unsigned(16#000#, 9) ELSE
to_unsigned(16#1FF#, 9) WHEN Switch_out1 = to_unsigned(16#1FF#, 9) ELSE
Switch_out1;
Look_Up_Table_out1 <= nc(to_integer(Look_Up_Table_k));
Negate_cast <= resize(Look_Up_Table_out1, 17);
Negate_cast_1 <= - (Negate_cast);
Negate_out1 <= Negate_cast_1(15 DOWNTO 0);
Sine <= Negate_out1 WHEN LTEp50_relop1 = '0' ELSE
Look_Up_Table_out1;
Sine_1 <= Sine;
x_x <= std_logic_vector(Sine_1);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block1.vhd
|
1
|
15602
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block1.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block1
-- Source Path: hdl_ofdm_tx/ifft/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_5_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_5_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_7_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_7_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_vld : IN std_logic;
twdl_3_5_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_5_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_5_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_5_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_6_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_6_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_5_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block1;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block1 IS
-- Component Declarations
COMPONENT Complex3Multiply_block2
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din2_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
di2_vld_dly3 : IN std_logic;
twdl_3_6_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_6_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_6_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_6_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block2
USE ENTITY work.Complex3Multiply_block2(rtl);
-- Signals
SIGNAL dout_5_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly4 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly5 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly6 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly7 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly8 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly9 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_5_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly4 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly5 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly6 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly7 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly8 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly9 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_7_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_7_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_6_re_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin_6_im_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
BEGIN
u_MUL3_2 : Complex3Multiply_block2
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix19_En13
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix19_En13
di2_vld_dly3 => di2_vld_dly3,
twdl_3_6_re => twdl_3_6_re, -- sfix16_En14
twdl_3_6_im => twdl_3_6_im, -- sfix16_En14
softReset => softReset,
twdlXdin_6_re => twdlXdin_6_re_tmp, -- sfix19_En13
twdlXdin_6_im => twdlXdin_6_im_tmp, -- sfix19_En13
twdlXdin2_vld => twdlXdin_5_vld
);
dout_5_re_signed <= signed(dout_5_re);
din_re <= resize(dout_5_re_signed, 19);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly1 <= din_re;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly4 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly4 <= din1_re_dly3;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly5 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly5 <= din1_re_dly4;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly6 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly6 <= din1_re_dly5;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly7 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly7 <= din1_re_dly6;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly8 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly8 <= din1_re_dly7;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly9 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly9 <= din1_re_dly8;
END IF;
END IF;
END PROCESS intdelay_8_process;
twdlXdin_5_re <= std_logic_vector(din1_re_dly9);
dout_5_im_signed <= signed(dout_5_im);
din_im <= resize(dout_5_im_signed, 19);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly1 <= din_im;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly4 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly4 <= din1_im_dly3;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly5 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly5 <= din1_im_dly4;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly6 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly6 <= din1_im_dly5;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly7 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly7 <= din1_im_dly6;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly8 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly8 <= din1_im_dly7;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly9 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly9 <= din1_im_dly8;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_5_im <= std_logic_vector(din1_im_dly9);
dout_7_re_signed <= signed(dout_7_re);
din_re_1 <= resize(dout_7_re_signed, 19);
intdelay_18_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly1 <= din_re_1;
END IF;
END IF;
END PROCESS intdelay_18_process;
intdelay_19_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_19_process;
dout_7_im_signed <= signed(dout_7_im);
din_im_1 <= resize(dout_7_im_signed, 19);
intdelay_20_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly1 <= din_im_1;
END IF;
END IF;
END PROCESS intdelay_20_process;
intdelay_21_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_21_process;
intdelay_22_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_22_process;
intdelay_23_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_23_process;
intdelay_24_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_24_process;
intdelay_25_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_25_process;
intdelay_26_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_26_process;
twdlXdin_6_re <= twdlXdin_6_re_tmp;
twdlXdin_6_im <= twdlXdin_6_im_tmp;
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/ifft_16_bit/TWDLROM_3_2.vhd
|
1
|
13825
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_2.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_2
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLROM_3_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ifft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_2_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_2_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_2_vld : OUT std_logic
);
END TWDLROM_3_2;
ARCHITECTURE rtl OF TWDLROM_3_2 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_2_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_2_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#1#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#0#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#0#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_2_re_tmp <= twdlIn_re;
twdl_3_2_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_2_re <= std_logic_vector(twdl_3_2_re_tmp);
twdl_3_2_im <= std_logic_vector(twdl_3_2_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_2_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_2_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
FFT_HDL/transceiver_hdl/OFDM_transmitter/RADIX22FFT_SDNF2_4_block.vhd
|
1
|
8557
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_4_block.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_3_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block IS
-- Signals
SIGNAL dout_2_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_2_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_4_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_4_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_3_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_3_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_4_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_4_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
dout_2_re_signed <= signed(dout_2_re);
dout_2_im_signed <= signed(dout_2_im);
dout_4_re_signed <= signed(dout_4_re);
dout_4_im_signed <= signed(dout_4_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_2_re_signed, dout_2_im_signed,
dout_4_re_signed, dout_4_im_signed, dout_1_vld, rotate_3)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE add_cast_3 : signed(16 DOWNTO 0);
VARIABLE add_cast_4 : signed(16 DOWNTO 0);
VARIABLE add_cast_5 : signed(16 DOWNTO 0);
VARIABLE add_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_3 : signed(16 DOWNTO 0);
VARIABLE sub_cast_4 : signed(16 DOWNTO 0);
VARIABLE sub_cast_5 : signed(16 DOWNTO 0);
VARIABLE sub_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_3 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(dout_2_re_signed, 17);
add_cast_2 := resize(dout_4_im_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(dout_2_re_signed, 17);
sub_cast_2 := resize(dout_4_im_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(dout_2_im_signed, 17);
add_cast_6 := resize(dout_4_re_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(dout_2_im_signed, 17);
sub_cast_6 := resize(dout_4_re_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(dout_2_re_signed, 17);
add_cast_0 := resize(dout_4_re_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(dout_2_re_signed, 17);
sub_cast_0 := resize(dout_4_re_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(dout_2_im_signed, 17);
add_cast_4 := resize(dout_4_im_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(dout_2_im_signed, 17);
sub_cast_4 := resize(dout_4_im_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_3_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_3_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_4_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_4_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_3_re <= std_logic_vector(dout_3_re_tmp);
dout_3_im <= std_logic_vector(dout_3_im_tmp);
dout_4_re_1 <= std_logic_vector(dout_4_re_tmp);
dout_4_im_1 <= std_logic_vector(dout_4_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
Display/hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block.vhd
|
1
|
6337
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_2_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_2_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_4_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_4_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_3_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_4_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_4_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20
dout_3_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block IS
-- Signals
SIGNAL twdlXdin_2_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_2_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_4_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL twdlXdin_4_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_3_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_3_im_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_4_re_tmp : signed(19 DOWNTO 0); -- sfix20
SIGNAL dout_4_im_tmp : signed(19 DOWNTO 0); -- sfix20
BEGIN
twdlXdin_2_re_signed <= signed(twdlXdin_2_re);
twdlXdin_2_im_signed <= signed(twdlXdin_2_im);
twdlXdin_4_re_signed <= signed(twdlXdin_4_re);
twdlXdin_4_im_signed <= signed(twdlXdin_4_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_2_re_signed,
twdlXdin_2_im_signed, twdlXdin_4_re_signed, twdlXdin_4_im_signed,
twdlXdin_1_vld)
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_2_re_signed, 21) + resize(twdlXdin_4_re_signed, 21);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_2_re_signed, 21) - resize(twdlXdin_4_re_signed, 21);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_2_im_signed, 21) + resize(twdlXdin_4_im_signed, 21);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_2_im_signed, 21) - resize(twdlXdin_4_im_signed, 21);
END IF;
dout_3_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(19 DOWNTO 0);
dout_3_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(19 DOWNTO 0);
dout_4_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(19 DOWNTO 0);
dout_4_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(19 DOWNTO 0);
dout_3_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_3_re <= std_logic_vector(dout_3_re_tmp);
dout_3_im <= std_logic_vector(dout_3_im_tmp);
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_1_block2.vhd
|
1
|
7093
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_1_block2.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block2
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF1_1_block2 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_8_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_8_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_7_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_7_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_8_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_8_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En13
dout_7_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block2;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block2 IS
-- Signals
SIGNAL twdlXdin_7_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_7_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_8_re_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL twdlXdin_8_im_signed : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_7_re_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_7_im_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_8_re_tmp : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_8_im_tmp : signed(16 DOWNTO 0); -- sfix17_En13
BEGIN
twdlXdin_7_re_signed <= signed(twdlXdin_7_re);
twdlXdin_7_im_signed <= signed(twdlXdin_7_im);
twdlXdin_8_re_signed <= signed(twdlXdin_8_re);
twdlXdin_8_im_signed <= signed(twdlXdin_8_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_7_re_signed,
twdlXdin_7_im_signed, twdlXdin_8_re_signed, twdlXdin_8_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(17 DOWNTO 0);
VARIABLE add_cast_0 : signed(17 DOWNTO 0);
VARIABLE sub_cast : signed(17 DOWNTO 0);
VARIABLE sub_cast_0 : signed(17 DOWNTO 0);
VARIABLE add_cast_1 : signed(17 DOWNTO 0);
VARIABLE add_cast_2 : signed(17 DOWNTO 0);
VARIABLE sub_cast_1 : signed(17 DOWNTO 0);
VARIABLE sub_cast_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_7_re_signed, 18);
add_cast_0 := resize(twdlXdin_8_re_signed, 18);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_7_re_signed, 18);
sub_cast_0 := resize(twdlXdin_8_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_7_im_signed, 18);
add_cast_2 := resize(twdlXdin_8_im_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_7_im_signed, 18);
sub_cast_2 := resize(twdlXdin_8_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
dout_7_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(16 DOWNTO 0);
dout_7_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(16 DOWNTO 0);
dout_8_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(16 DOWNTO 0);
dout_8_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(16 DOWNTO 0);
dout_7_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_7_re <= std_logic_vector(dout_7_re_tmp);
dout_7_im <= std_logic_vector(dout_7_im_tmp);
dout_8_re <= std_logic_vector(dout_8_re_tmp);
dout_8_im <= std_logic_vector(dout_8_im_tmp);
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLROM_3_15.vhd
|
1
|
14023
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLROM_3_15.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_15
-- Source Path: hdl_ofdm_tx/ifft/TWDLROM_3_15
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY TWDLROM_3_15 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_15_vld : OUT std_logic
);
END TWDLROM_3_15;
ARCHITECTURE rtl OF TWDLROM_3_15 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#4000#, 16), to_signed(16#3B21#, 16)); -- sfix16 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed16(0 TO 1) :=
(to_signed(16#0000#, 16), to_signed(-16#187E#, 16)); -- sfix16 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_re : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twiddleReg_im : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_15_re_tmp : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL twdl_3_15_im_tmp : signed(15 DOWNTO 0); -- sfix16_En14
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#2#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE addr_cast : unsigned(3 DOWNTO 0);
VARIABLE c : unsigned(1 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt;
Radix22TwdlMapping_phase_next <= Radix22TwdlMapping_phase;
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
c := unsigned'(Radix22TwdlMapping_cnt(0) & Radix22TwdlMapping_cnt(1));
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(c, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(c, 4) sll 1;
ELSE
addr_cast := resize(c, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (addr_cast sll 1) + addr_cast;
END IF;
IF dout_2_vld = '1' THEN
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000004#, 2);
END IF;
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(15 DOWNTO 0);
VARIABLE twdlIn_im : signed(15 DOWNTO 0);
VARIABLE cast : signed(16 DOWNTO 0);
VARIABLE cast_0 : signed(16 DOWNTO 0);
VARIABLE cast_1 : signed(16 DOWNTO 0);
VARIABLE cast_2 : signed(16 DOWNTO 0);
VARIABLE cast_3 : signed(16 DOWNTO 0);
VARIABLE cast_4 : signed(16 DOWNTO 0);
VARIABLE cast_5 : signed(16 DOWNTO 0);
VARIABLE cast_6 : signed(16 DOWNTO 0);
VARIABLE cast_7 : signed(16 DOWNTO 0);
VARIABLE cast_8 : signed(16 DOWNTO 0);
VARIABLE cast_9 : signed(16 DOWNTO 0);
VARIABLE cast_10 : signed(16 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "010" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
WHEN "100" =>
twdlIn_re := to_signed(-16#2D41#, 16);
twdlIn_im := to_signed(16#2D41#, 16);
WHEN OTHERS =>
twdlIn_re := to_signed(16#2D41#, 16);
twdlIn_im := to_signed(-16#2D41#, 16);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 17);
cast_0 := - (cast);
twdlIn_re := cast_0(15 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 17);
cast_6 := - (cast_5);
twdlIn_im := cast_6(15 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 17);
cast_8 := - (cast_7);
twdlIn_im := cast_8(15 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 17);
cast_2 := - (cast_1);
twdlIn_re := cast_2(15 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 17);
cast_4 := - (cast_3);
twdlIn_re := cast_4(15 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 17);
cast_10 := - (cast_9);
twdlIn_im := cast_10(15 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_15_re_tmp <= twdlIn_re;
twdl_3_15_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_15_re <= std_logic_vector(twdl_3_15_re_tmp);
twdl_3_15_im <= std_logic_vector(twdl_3_15_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_15_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
twdl_3_15_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
FFT_HDL/transceiver_hdl/OFDM_transmitter/TWDLMULT_SDNF1_3_block5.vhd
|
1
|
15164
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/TWDLMULT_SDNF1_3_block5.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block5
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : IN std_logic;
twdl_3_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block5;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block5 IS
-- Component Declarations
COMPONENT Complex3Multiply_block8
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
din2_im_dly3 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
di2_vld_dly3 : IN std_logic;
twdl_3_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block8
USE ENTITY work.Complex3Multiply_block8(rtl);
-- Signals
SIGNAL dout_10_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly1 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly2 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly3 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly4 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly5 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly6 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly7 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly8 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_re_dly9 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_10_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly1 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly2 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly3 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly4 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly5 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly6 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly7 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly8 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din1_im_dly9 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_12_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_re_dly1 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_re_dly2 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_12_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly1 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly2 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_re_dly3 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL din2_im_dly3 : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_14_re_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL twdlXdin_14_im_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
BEGIN
u_MUL3_2 : Complex3Multiply_block8
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix16_En13
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix16_En13
di2_vld_dly3 => di2_vld_dly3,
twdl_3_14_re => twdl_3_14_re, -- sfix16_En14
twdl_3_14_im => twdl_3_14_im, -- sfix16_En14
softReset => softReset,
twdlXdin_14_re => twdlXdin_14_re_tmp, -- sfix16_En13
twdlXdin_14_im => twdlXdin_14_im_tmp, -- sfix16_En13
twdlXdin2_vld => twdlXdin_13_vld
);
dout_10_re_signed <= signed(dout_10_re);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly1 <= dout_10_re_signed;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly4 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly4 <= din1_re_dly3;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly5 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly5 <= din1_re_dly4;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly6 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly6 <= din1_re_dly5;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly7 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly7 <= din1_re_dly6;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly8 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly8 <= din1_re_dly7;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly9 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly9 <= din1_re_dly8;
END IF;
END IF;
END PROCESS intdelay_8_process;
twdlXdin_13_re <= std_logic_vector(din1_re_dly9);
dout_10_im_signed <= signed(dout_10_im);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly1 <= dout_10_im_signed;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly4 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly4 <= din1_im_dly3;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly5 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly5 <= din1_im_dly4;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly6 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly6 <= din1_im_dly5;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly7 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly7 <= din1_im_dly6;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly8 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly8 <= din1_im_dly7;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly9 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly9 <= din1_im_dly8;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_13_im <= std_logic_vector(din1_im_dly9);
dout_12_re_signed <= signed(dout_12_re);
intdelay_18_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly1 <= dout_12_re_signed;
END IF;
END IF;
END PROCESS intdelay_18_process;
intdelay_19_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_19_process;
dout_12_im_signed <= signed(dout_12_im);
intdelay_20_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly1 <= dout_12_im_signed;
END IF;
END IF;
END PROCESS intdelay_20_process;
intdelay_21_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_21_process;
intdelay_22_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_22_process;
intdelay_23_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_23_process;
intdelay_24_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_24_process;
intdelay_25_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_25_process;
intdelay_26_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_26_process;
twdlXdin_14_re <= twdlXdin_14_re_tmp;
twdlXdin_14_im <= twdlXdin_14_im_tmp;
END rtl;
|
gpl-3.0
|
jmacneal/Design-Project
|
hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_3_block1.vhd
|
1
|
7093
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_3_block1.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block1
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF1_3_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_3_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_3_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_7_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_7_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_5_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_6_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_6_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_5_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block1 IS
-- Signals
SIGNAL twdlXdin_3_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_3_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_7_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_7_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_5_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_5_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_6_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_6_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
BEGIN
twdlXdin_3_re_signed <= signed(twdlXdin_3_re);
twdlXdin_3_im_signed <= signed(twdlXdin_3_im);
twdlXdin_7_re_signed <= signed(twdlXdin_7_re);
twdlXdin_7_im_signed <= signed(twdlXdin_7_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_3_re_signed,
twdlXdin_3_im_signed, twdlXdin_7_re_signed, twdlXdin_7_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(19 DOWNTO 0);
VARIABLE add_cast_0 : signed(19 DOWNTO 0);
VARIABLE sub_cast : signed(19 DOWNTO 0);
VARIABLE sub_cast_0 : signed(19 DOWNTO 0);
VARIABLE add_cast_1 : signed(19 DOWNTO 0);
VARIABLE add_cast_2 : signed(19 DOWNTO 0);
VARIABLE sub_cast_1 : signed(19 DOWNTO 0);
VARIABLE sub_cast_2 : signed(19 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_3_re_signed, 20);
add_cast_0 := resize(twdlXdin_7_re_signed, 20);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_3_re_signed, 20);
sub_cast_0 := resize(twdlXdin_7_re_signed, 20);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_3_im_signed, 20);
add_cast_2 := resize(twdlXdin_7_im_signed, 20);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_3_im_signed, 20);
sub_cast_2 := resize(twdlXdin_7_im_signed, 20);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
dout_5_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(18 DOWNTO 0);
dout_5_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(18 DOWNTO 0);
dout_6_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(18 DOWNTO 0);
dout_6_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(18 DOWNTO 0);
dout_5_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_5_re <= std_logic_vector(dout_5_re_tmp);
dout_5_im <= std_logic_vector(dout_5_im_tmp);
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
END rtl;
|
gpl-3.0
|
adelapie/noekeon_loop
|
theta.vhd
|
5
|
3797
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end theta;
architecture Behavioral of theta is
signal a_1_0_s : std_logic_vector(31 downto 0);
signal a_3_0_s : std_logic_vector(31 downto 0);
signal tmp_0_s : std_logic_vector(31 downto 0);
signal tmp_1_s : std_logic_vector(31 downto 0);
signal tmp_2_s : std_logic_vector(31 downto 0);
signal tmp_3_s : std_logic_vector(31 downto 0);
signal m_1_tmp_0_s : std_logic_vector(31 downto 0);
signal m_1_tmp_1_s : std_logic_vector(31 downto 0);
signal m_1_tmp_2_s : std_logic_vector(31 downto 0);
signal m_1_tmp_3_s : std_logic_vector(31 downto 0);
signal m_2_tmp_0_s : std_logic_vector(31 downto 0);
signal m_2_tmp_1_s : std_logic_vector(31 downto 0);
signal m_2_tmp_2_s : std_logic_vector(31 downto 0);
signal m_2_tmp_3_s : std_logic_vector(31 downto 0);
begin
--Theta(k,a){
-- temp = a[0]^a[2];
-- temp ^= temp>>>8 ^ temp<<<8;
-- a[1] ^= temp;
-- a[3] ^= temp;
-- a[0] ^= k[0];
-- a[1] ^= k[1];
-- a[2] ^= k[2];
-- a[3] ^= k[3];
-- temp = a[1]^a[3];
-- temp ^= temp>>>8 ^ temp<<<8;
-- a[0] ^= temp;
-- a[2] ^= temp;
--}
m_1_tmp_0_s <= a_0_in xor a_2_in; -- temp = a[0]^a[2];
m_1_tmp_1_s <= m_1_tmp_0_s(23 downto 0) & m_1_tmp_0_s(31 downto 24); -- temp>>>8
m_1_tmp_2_s <= m_1_tmp_0_s(7 downto 0) & m_1_tmp_0_s(31 downto 8); -- temp<<<8;
m_1_tmp_3_s <= m_1_tmp_0_s xor m_1_tmp_1_s xor m_1_tmp_2_s; -- temp ^= temp>>>8 ^ temp<<<8;
a_1_0_s <= a_1_in xor m_1_tmp_3_s; -- a[1] ^= temp;
a_3_0_s <= a_3_in xor m_1_tmp_3_s; -- a[3] ^= temp;
tmp_0_s <= a_0_in xor k_0_in; -- a[0] ^= k[0];
tmp_1_s <= a_1_0_s xor k_1_in; -- a[1] ^= k[1];
tmp_2_s <= a_2_in xor k_2_in; -- a[2] ^= k[2];
tmp_3_s <= a_3_0_s xor k_3_in; -- a[3] ^= k[3];
m_2_tmp_0_s <= tmp_1_s xor tmp_3_s; -- temp = a[1]^a[3];
m_2_tmp_1_s <= m_2_tmp_0_s(23 downto 0) & m_2_tmp_0_s(31 downto 24); -- temp>>>8
m_2_tmp_2_s <= m_2_tmp_0_s(7 downto 0) & m_2_tmp_0_s(31 downto 8); -- temp<<<8;
m_2_tmp_3_s <= m_2_tmp_0_s xor m_2_tmp_1_s xor m_2_tmp_2_s; -- temp ^= temp>>>8 ^ temp<<<8;
a_0_out <= tmp_0_s xor m_2_tmp_3_s; -- a[0] ^= temp;
a_2_out <= tmp_2_s xor m_2_tmp_3_s; -- a[2] ^= temp;
a_1_out <= tmp_1_s;
a_3_out <= tmp_3_s;
end Behavioral;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/rtl/iodrp_mcb_controller.vhd
|
19
|
18779
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_mcb_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 03/19/09: Initial version for IODRP_MCB read operations.
-- 1.1: 04/03/09: SLH - Added left shift for certain IOI's
-- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version.
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_mcb_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
--added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end entity iodrp_mcb_controller;
architecture trans of iodrp_mcb_controller is
type StType is (
READY,
DECIDE ,
ADDR_PHASE ,
ADDR_TO_DATA_GAP ,
ADDR_TO_DATA_GAP2,
ADDR_TO_DATA_GAP3,
DATA_PHASE ,
ALMOST_READY ,
ALMOST_READY2 ,
ALMOST_READY3
);
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(8 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal DRP_CS_pre : std_logic;
signal extra_cs : std_logic;
signal state,nextstate : StType;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "gray";
attribute fsm_encoding of nextstate : signal is "gray";
signal data_out : std_logic_vector(8 downto 0);
signal data_out_mux : std_logic_vector(8 downto 0);
signal DRP_SDI_pre : std_logic;
--synthesis translate_off
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
-- case(state)
--synthesis translate_on
-- The changes below are to compensate for an issue with 1.0 silicon.
-- It may still be necessary to add a clock cycle to the ADD and CS signals
--`define DRP_v1_0_FIX // Uncomment out this line for synthesis
procedure shift_n_expand(
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(8 downto 0)) is
variable data_out_xilinx2 : std_logic_vector(8 downto 0);
begin
if ((data_in(0)) = '1') then
data_out_xilinx2(1 downto 0) := "11";
else
data_out_xilinx2(1 downto 0) := "00";
end if;
if (data_in(1 downto 0) = "10") then
data_out_xilinx2(2 downto 1) := "11";
else
data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
end if;
if (data_in(2 downto 1) = "10") then
data_out_xilinx2(3 downto 2) := "11";
else
data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
end if;
if (data_in(3 downto 2) = "10") then
data_out_xilinx2(4 downto 3) := "11";
else
data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
end if;
if (data_in(4 downto 3) = "10") then
data_out_xilinx2(5 downto 4) := "11";
else
data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
end if;
if (data_in(5 downto 4) = "10") then
data_out_xilinx2(6 downto 5) := "11";
else
data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
end if;
if (data_in(6 downto 5) = "10") then
data_out_xilinx2(7 downto 6) := "11";
else
data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
end if;
if (data_in(7 downto 6) = "10") then
data_out_xilinx2(8 downto 7) := "11";
else
data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
end if;
end shift_n_expand;
-- Declare intermediate signals for referenced outputs
signal DRP_CS_xilinx1 : std_logic;
signal DRP_ADD_xilinx0 : std_logic;
signal ALMOST_READY2_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
begin
-- Drive referenced outputs
DRP_CS <= DRP_CS_xilinx1;
DRP_ADD <= DRP_ADD_xilinx0;
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY =>
-- state_ascii <= "ALMOST_READY";
-- when ALMOST_READY2 =>
-- state_ascii <= "ALMOST_READY2";
-- when ALMOST_READY3 =>
-- state_ascii <= "ALMOST_READY3";
-- when others =>
-- null;
-- end case;
-- end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when state = READY else '0';
process (drp_ioi_addr, data_out)
begin
case drp_ioi_addr is
when IOI_DQ0 =>
data_out_mux <= data_out;
when IOI_DQ1 =>
data_out_mux <= data_out;
when IOI_DQ2 =>
data_out_mux <= data_out;
when IOI_DQ3 =>
data_out_mux <= data_out;
when IOI_DQ4 =>
data_out_mux <= data_out;
when IOI_DQ5 =>
data_out_mux <= data_out;
when IOI_DQ6 =>
data_out_mux <= data_out;
when IOI_DQ7 =>
data_out_mux <= data_out;
when IOI_DQ8 =>
data_out_mux <= data_out;
when IOI_DQ9 =>
data_out_mux <= data_out;
when IOI_DQ10 =>
data_out_mux <= data_out;
when IOI_DQ11 =>
data_out_mux <= data_out;
when IOI_DQ12 =>
data_out_mux <= data_out;
when IOI_DQ13 =>
data_out_mux <= data_out;
when IOI_DQ14 =>
data_out_mux <= data_out;
when IOI_DQ15 =>
data_out_mux <= data_out;
when IOI_UDQS_CLK =>
data_out_mux <= data_out;
when IOI_UDQS_PIN =>
data_out_mux <= data_out;
when IOI_LDQS_CLK =>
data_out_mux <= data_out;
when IOI_LDQS_PIN =>
data_out_mux <= data_out;
when others =>
data_out_mux <= data_out;
end case;
end process;
data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
('0' & data_reg);
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "000000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
read_data <= "00000000";
else
if (state = ALMOST_READY3) then
read_data <= shift_through_reg(7 downto 0);
end if;
end if;
end if;
end process;
ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
-- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
'0';
DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI_pre;
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
load_shift_n <= '0';
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the alternative access method.
when ADDR_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
if (('1' and rd_not_write_reg) = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
load_shift_n <= '0';
nextstate <= ALMOST_READY2;
when ALMOST_READY2 =>
load_shift_n <= '0';
nextstate <= ALMOST_READY3;
when ALMOST_READY3 =>
load_shift_n <= '0';
nextstate <= READY;
when others =>
load_shift_n <= '0';
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/sim/sim_tb_top.vhd
|
1
|
49537
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C1_HW_TESTING : string := "FALSE";
constant C3_HW_TESTING : string := "FALSE";
function c1_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C1_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C1_MEMCLK_PERIOD : integer := 2500;
constant C1_RST_ACT_LOW : integer := 0;
constant C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
constant C1_CLK_PERIOD_NS : real := 2500.0 / 1000.0;
constant C1_TCYC_SYS : real := C1_CLK_PERIOD_NS/2.0;
constant C1_TCYC_SYS_DIV2 : time := C1_TCYC_SYS * 1 ns;
constant C1_NUM_DQ_PINS : integer := 16;
constant C1_MEM_ADDR_WIDTH : integer := 14;
constant C1_MEM_BANKADDR_WIDTH : integer := 3;
constant C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C1_P0_MASK_SIZE : integer := 4;
constant C1_P0_DATA_PORT_SIZE : integer := 32;
constant C1_P1_MASK_SIZE : integer := 4;
constant C1_P1_DATA_PORT_SIZE : integer := 32;
constant C1_MEM_BURST_LEN : integer := 8;
constant C1_MEM_NUM_COL_BITS : integer := 10;
constant C1_SIMULATION : string := "TRUE";
constant C1_CALIB_SOFT_IP : string := "TRUE";
constant C3_MEMCLK_PERIOD : integer := 2500;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
constant C3_CLK_PERIOD_NS : real := 2500.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C1_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C1_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C1_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"000002ff", x"02ffffff");
constant C1_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"fffffc00", x"fc000000");
constant C1_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr3_controller is
generic
(
C1_P0_MASK_SIZE : integer;
C1_P0_DATA_PORT_SIZE : integer;
C1_P1_MASK_SIZE : integer;
C1_P1_DATA_PORT_SIZE : integer;
C1_MEMCLK_PERIOD : integer;
C1_RST_ACT_LOW : integer;
C1_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C1_CALIB_SOFT_IP : string;
C1_SIMULATION : string;
C1_MEM_ADDR_ORDER : string;
C1_NUM_DQ_PINS : integer;
C1_MEM_ADDR_WIDTH : integer;
C1_MEM_BANKADDR_WIDTH : integer;
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
c1_sys_clk_p : in std_logic;
c1_sys_clk_n : in std_logic;
c1_sys_rst_i : in std_logic;
c1_calib_done : out std_logic;
c1_clk0 : out std_logic;
c1_rst0 : out std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb1_dram_reset_n : out std_logic; mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_reset_n : out std_logic; c1_p0_cmd_clk : in std_logic;
c1_p0_cmd_en : in std_logic;
c1_p0_cmd_instr : in std_logic_vector(2 downto 0);
c1_p0_cmd_bl : in std_logic_vector(5 downto 0);
c1_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p0_cmd_empty : out std_logic;
c1_p0_cmd_full : out std_logic;
c1_p0_wr_clk : in std_logic;
c1_p0_wr_en : in std_logic;
c1_p0_wr_mask : in std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
c1_p0_wr_data : in std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_wr_full : out std_logic;
c1_p0_wr_empty : out std_logic;
c1_p0_wr_count : out std_logic_vector(6 downto 0);
c1_p0_wr_underrun : out std_logic;
c1_p0_wr_error : out std_logic;
c1_p0_rd_clk : in std_logic;
c1_p0_rd_en : in std_logic;
c1_p0_rd_data : out std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_rd_full : out std_logic;
c1_p0_rd_empty : out std_logic;
c1_p0_rd_count : out std_logic_vector(6 downto 0);
c1_p0_rd_overflow : out std_logic;
c1_p0_rd_error : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
component ddr3_model_c1 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C1_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C1_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C1_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component memc1_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c1_sys_clk : std_logic := '0';
signal c1_sys_clk_p : std_logic;
signal c1_sys_clk_n : std_logic;
-- System Reset
signal c1_sys_rst : std_logic := '0';
signal c1_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c1_error : std_logic;
signal c1_calib_done : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal mcb1_dram_a : std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
signal mcb1_dram_ba : std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb1_dram_ck : std_logic;
signal mcb1_dram_ck_n : std_logic;
signal mcb1_dram_dq : std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
signal mcb1_dram_dqs : std_logic;
signal mcb1_dram_dqs_n : std_logic;
signal mcb1_dram_dm : std_logic;
signal mcb1_dram_ras_n : std_logic;
signal mcb1_dram_cas_n : std_logic;
signal mcb1_dram_we_n : std_logic;
signal mcb1_dram_cke : std_logic;
signal mcb1_dram_odt : std_logic;
signal mcb1_dram_reset_n : std_logic;
signal mcb1_dram_udqs : std_logic;
signal mcb1_dram_udqs_n : std_logic;
signal mcb1_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_udm :std_logic; -- for X16 parts
signal mcb1_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c1_clk0 : std_logic;
signal c1_rst0 : std_logic;
signal c1_cmp_error : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb1_command : std_logic_vector(2 downto 0);
signal mcb1_enable1 : std_logic;
signal mcb1_enable2 : std_logic;
signal c1_p0_cmd_en : std_logic;
signal c1_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c1_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c1_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c1_p0_cmd_empty : std_logic;
signal c1_p0_cmd_full : std_logic;
signal c1_p0_wr_en : std_logic;
signal c1_p0_wr_mask : std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
signal c1_p0_wr_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_wr_full : std_logic;
signal c1_p0_wr_empty : std_logic;
signal c1_p0_wr_count : std_logic_vector(6 downto 0);
signal c1_p0_wr_underrun : std_logic;
signal c1_p0_wr_error : std_logic;
signal c1_p0_rd_en : std_logic;
signal c1_p0_rd_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_rd_full : std_logic;
signal c1_p0_rd_empty : std_logic;
signal c1_p0_rd_count : std_logic_vector(6 downto 0);
signal c1_p0_rd_overflow : std_logic;
signal c1_p0_rd_error : std_logic;
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq1 : std_logic;
signal rzq3 : std_logic;
signal zio1 : std_logic;
signal zio3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c1_sys_clk <= not c1_sys_clk;
wait for (C1_TCYC_SYS_DIV2);
end process;
c1_sys_clk_p <= c1_sys_clk;
c1_sys_clk_n <= not c1_sys_clk;
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c1_sys_rst <= '0';
wait for 200 ns;
c1_sys_rst <= '1';
wait;
end process;
c1_sys_rst_i <= c1_sys_rst when (C1_RST_ACT_LOW = 1) else (not c1_sys_rst);
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c1_error or c3_error;
calib_done <= c1_calib_done and c3_calib_done;
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown1 : PULLDOWN port map(O => zio1);
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown1 : PULLDOWN port map(O => rzq1);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr3_controller generic map
(
C1_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C1_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C1_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C1_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C1_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C1_RST_ACT_LOW => C1_RST_ACT_LOW,
C1_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C1_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C1_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C1_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C1_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C1_SIMULATION => C1_SIMULATION,
C1_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c1_sys_clk_p => c1_sys_clk_p,
c1_sys_clk_n => c1_sys_clk_n,
c1_sys_rst_i => c1_sys_rst_i,
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_udqs => mcb1_dram_udqs, -- for X16 parts
mcb1_dram_udqs_n => mcb1_dram_udqs_n, -- for X16 parts
mcb1_dram_udm => mcb1_dram_udm, -- for X16 parts
mcb1_dram_dm => mcb1_dram_dm,
c1_clk0 => c1_clk0,
c1_rst0 => c1_rst0,
c1_calib_done => c1_calib_done,
mcb1_rzq => rzq1,
mcb1_zio => zio1,
c1_p0_cmd_clk => (c1_clk0),
c1_p0_cmd_en => c1_p0_cmd_en,
c1_p0_cmd_instr => c1_p0_cmd_instr,
c1_p0_cmd_bl => c1_p0_cmd_bl,
c1_p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
c1_p0_cmd_empty => c1_p0_cmd_empty,
c1_p0_cmd_full => c1_p0_cmd_full,
c1_p0_wr_clk => (c1_clk0),
c1_p0_wr_en => c1_p0_wr_en,
c1_p0_wr_mask => c1_p0_wr_mask,
c1_p0_wr_data => c1_p0_wr_data,
c1_p0_wr_full => c1_p0_wr_full,
c1_p0_wr_empty => c1_p0_wr_empty,
c1_p0_wr_count => c1_p0_wr_count,
c1_p0_wr_underrun => c1_p0_wr_underrun,
c1_p0_wr_error => c1_p0_wr_error,
c1_p0_rd_clk => (c1_clk0),
c1_p0_rd_en => c1_p0_rd_en,
c1_p0_rd_data => c1_p0_rd_data,
c1_p0_rd_full => c1_p0_rd_full,
c1_p0_rd_empty => c1_p0_rd_empty,
c1_p0_rd_count => c1_p0_rd_count,
c1_p0_rd_overflow => c1_p0_rd_overflow,
c1_p0_rd_error => c1_p0_rd_error,
c3_sys_clk_p => c3_sys_clk_p,
c3_sys_clk_n => c3_sys_clk_n,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
c3_p0_cmd_clk => (c3_clk0),
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => (c3_clk0),
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => (c3_clk0),
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error
);
-- user interface
memc1_tb_top_inst : memc1_tb_top generic map
(
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C1_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C1_p0_DATA_MODE,
C_p0_END_ADDRESS => C1_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C1_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C1_p0_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c1_clk0,
rst0 => c1_rst0,
calib_done => c1_calib_done,
cmp_error => c1_cmp_error,
error => c1_error,
error_status => c1_error_status,
vio_modify_enable => c1_vio_modify_enable,
vio_data_mode_value => c1_vio_data_mode_value,
vio_addr_mode_value => c1_vio_addr_mode_value,
p0_mcb_cmd_en_o => c1_p0_cmd_en,
p0_mcb_cmd_instr_o => c1_p0_cmd_instr,
p0_mcb_cmd_bl_o => c1_p0_cmd_bl,
p0_mcb_cmd_addr_o => c1_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c1_p0_cmd_full,
p0_mcb_wr_en_o => c1_p0_wr_en,
p0_mcb_wr_mask_o => c1_p0_wr_mask,
p0_mcb_wr_data_o => c1_p0_wr_data,
p0_mcb_wr_full_i => c1_p0_wr_full,
p0_mcb_wr_fifo_counts => c1_p0_wr_count,
p0_mcb_rd_en_o => c1_p0_rd_en,
p0_mcb_rd_data_i => c1_p0_rd_data,
p0_mcb_rd_empty_i => c1_p0_rd_empty,
p0_mcb_rd_fifo_counts => c1_p0_rd_count
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb1_command <= (mcb1_dram_ras_n & mcb1_dram_cas_n & mcb1_dram_we_n);
process(mcb1_dram_ck)
begin
if (rising_edge(mcb1_dram_ck)) then
if (c1_sys_rst = '0') then
mcb1_enable1 <= '0';
mcb1_enable2 <= '0';
elsif (mcb1_command = "100") then
mcb1_enable2 <= '0';
elsif (mcb1_command = "101") then
mcb1_enable2 <= '1';
else
mcb1_enable2 <= mcb1_enable2;
end if;
mcb1_enable1 <= mcb1_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb1_dram_dqs_vector(1 downto 0) <= (mcb1_dram_udqs & mcb1_dram_dqs)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
mcb1_dram_dqs_n_vector(1 downto 0) <= (mcb1_dram_udqs_n & mcb1_dram_dqs_n)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb1_dram_dqs <= mcb1_dram_dqs_vector(0)
when ( mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs <= mcb1_dram_dqs_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_dqs_n <= mcb1_dram_dqs_n_vector(0)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs_n <= mcb1_dram_dqs_n_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb1_dram_dm_vector <= (mcb1_dram_udm & mcb1_dram_dm);
u_mem_c1 : ddr3_model_c1 port map
(
ck => mcb1_dram_ck,
ck_n => mcb1_dram_ck_n,
cke => mcb1_dram_cke,
cs_n => '0',
ras_n => mcb1_dram_ras_n,
cas_n => mcb1_dram_cas_n,
we_n => mcb1_dram_we_n,
dm_tdqs => mcb1_dram_dm_vector,
ba => mcb1_dram_ba,
addr => mcb1_dram_a,
dq => mcb1_dram_dq,
dqs => mcb1_dram_dqs_vector,
dqs_n => mcb1_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb1_dram_odt,
rst_n => mcb1_dram_reset_n
);
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
gpl-3.0
|
adelapie/noekeon_loop
|
noekeon_loop_k_4.vhd
|
1
|
10146
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is loop unrolling (for K = 2) implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon_loop_k_4 is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon_loop_k_4;
architecture Behavioral of noekeon_loop_k_4 is
component round_f is
port(enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(71 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_2_s : std_logic_vector(7 downto 0);
signal rc_3_s : std_logic_vector(7 downto 0);
signal rc_4_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal rc_2_ext_s : std_logic_vector(31 downto 0);
signal rc_3_ext_s : std_logic_vector(31 downto 0);
signal rc_4_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_0_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_1_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_2_out_s : std_logic_vector(31 downto 0);
signal stage_0_a_3_out_s : std_logic_vector(31 downto 0);
signal stage_1_a_0_out_s : std_logic_vector(31 downto 0);
signal stage_1_a_1_out_s : std_logic_vector(31 downto 0);
signal stage_1_a_2_out_s : std_logic_vector(31 downto 0);
signal stage_1_a_3_out_s : std_logic_vector(31 downto 0);
signal stage_2_a_0_out_s : std_logic_vector(31 downto 0);
signal stage_2_a_1_out_s : std_logic_vector(31 downto 0);
signal stage_2_a_2_out_s : std_logic_vector(31 downto 0);
signal stage_2_a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal init_val_shr_0 : std_logic_vector(71 downto 0);
signal init_val_shr_1 : std_logic_vector(71 downto 0);
signal init_val_shr_2 : std_logic_vector(71 downto 0);
signal init_val_shr_3 : std_logic_vector(71 downto 0);
begin
init_val_shr_0 <= X"80d82fc6d400000000";
init_val_shr_1 <= X"1bab5e97d400000000";
init_val_shr_2 <= X"364dbc35d400000000";
init_val_shr_3 <= X"6c9a636ad400000000";
RC_SHR_0 : rc_shr port map (clk, rst, init_val_shr_0, rc_s);
RC_SHR_1 : rc_shr port map (clk, rst, init_val_shr_1, rc_2_s);
RC_SHR_2 : rc_shr port map (clk, rst, init_val_shr_2, rc_3_s);
RC_SHR_3 : rc_shr port map (clk, rst, init_val_shr_3, rc_4_s);
rc_ext_s <= X"000000" & rc_s;
rc_2_ext_s <= X"000000" & rc_2_s;
rc_3_ext_s <= X"000000" & rc_3_s;
rc_4_ext_s <= X"000000" & rc_4_s;
ROUND_F_0 : round_f port map (enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
stage_0_a_0_out_s,
stage_0_a_1_out_s,
stage_0_a_2_out_s,
stage_0_a_3_out_s);
ROUND_F_1 : round_f port map (enc,
rc_2_ext_s,
stage_0_a_0_out_s,
stage_0_a_1_out_s,
stage_0_a_2_out_s,
stage_0_a_3_out_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
stage_1_a_0_out_s,
stage_1_a_1_out_s,
stage_1_a_2_out_s,
stage_1_a_3_out_s);
ROUND_F_2 : round_f port map (enc,
rc_3_ext_s,
stage_1_a_0_out_s,
stage_1_a_1_out_s,
stage_1_a_2_out_s,
stage_1_a_3_out_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
stage_2_a_0_out_s,
stage_2_a_1_out_s,
stage_2_a_2_out_s,
stage_2_a_3_out_s);
ROUND_F_3 : round_f port map (enc,
rc_4_ext_s,
stage_2_a_0_out_s,
stage_2_a_1_out_s,
stage_2_a_2_out_s,
stage_2_a_3_out_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/rtl/mcb_raw_wrapper.vhd
|
10
|
299135
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_raw_wrapper.v
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:04 $
-- \ \ / \ Date Created: Thu June 24 2008
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose:
--Reference:
-- This module is the intialization control logic of the memory interface.
-- All commands are issued from here acoording to the burst, CAS Latency and
-- the user commands.
--
-- Revised History:
-- Rev 1.1 - added port_enable assignment for all configurations and rearrange
-- assignment siganls according to port number
-- - added timescale directive -SN 7-28-08
-- - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through
-- 15 -SN 7-28-08
-- - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
-- - removed ghighb, gpwrdnb, gsr, gwe in port declaration.
-- For now tb need to force the signals inside the MCB and Wrapper
-- until a glbl.v is ready. Not sure how to do this in NCVerilog
-- flow. -SN 7-28-08
--
-- Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
-- Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08
-- Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09
-- Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
-- delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90
-- delay_we_90 ,delay_address,delay_ba_90 =
-- --removed :assign #50 delay_dqnum = dqnum;
-- --removed :assign #50 delay_dqpum = dqpum;
-- --removed :assign #50 delay_dqnlm = dqnlm;
-- --removed :assign #50 delay_dqplm = dqplm;
-- --removed : delay_dqsIO_w_en_90_n
-- --removed : delay_dqsIO_w_en_90_p
-- --removed : delay_dqsIO_w_en_0
-- -- corrected spelling error: C_MEM_RTRAS
-- Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09
-- -- rename the memc_wrapper.v to mcb_raw_wrapper.v
-- Rev 1.7 -- -- .READEN is removed in IODRP2_MCB 1-28-09
-- -- connection has been updated
-- Rev 1.8 -- update memory parameter equations. 1-30_2009
-- -- added portion of Soft IP
-- -- CAL_CLK_DIV is not used but MCB still has it
-- Rev 1.9 -- added Error checking for Invalid command to unidirectional port
-- Rev 1.10 -- changed the backend connection so that Simulation will work while
-- sw tools try to fix the model issues. 2-3-2009
-- sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
-- It is acutally 180 degree difference.
-- Rev 1.11 -- Added MCB_Soft_Calibration_top.
-- Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009
-- Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
-- Rev 1.14 -- Added minium condition for tRTP valud/
-- REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009
-- Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009
-- Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
-- Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
-- Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009.
-- Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
-- Dynamic DQS calibration in Soft Calibration module.
-- Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
-- RTT value is set to "disabled"
-- -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
-- -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010
-- Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- Rev 1.23 -- Fixed CR 558661. In Config "B64B64" mode, mig_p5_wr_data <= p1_wr_data(63 downto 32).
-- Rev 1.24 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE"
-- Rev 1.25 -- Fixed reset problem when MCB exits from SUSPEND SELFREFRESH mode. 10-20-2010
-- Rev 1.26 -- Synchronize sys_rst before connecting to mcb_soft_calibration module to fix
-- CDC static timing issue. 2-14-2011
--*************************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_raw_wrapper is
generic(
C_MEMCLK_PERIOD : integer := 2500;
C_PORT_ENABLE : std_logic_vector(5 downto 0) := (others => '1');
C_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_PORT_CONFIG : string := "B32_B32_W32_W32_W32_W32";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_NUM_DQ_PINS : integer := 8;
C_MEM_TYPE : string := "DDR3";
C_MEM_DENSITY : string := "512M";
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 4;
C_MEM_ADDR_WIDTH : integer := 13;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR3_CAS_LATENCY : integer := 7;
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_MDDR_ODS : string := "FULL";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "OFF";
C_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIB_BYPASS : string := "NO";
C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := "000";
C_CALIB_SOFT_IP : string := "TRUE";
C_SKIP_IN_TERM_CAL : integer := 0; --provides option to skip the input termination calibration
C_SKIP_DYNAMIC_CAL : integer := 0; --provides option to skip the dynamic delay calibration
C_SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
--- ADDED for 1.0 silicon support to bypass Calibration //////
-- 07-10-09 chipl
--////////////////////////////////////////////////////////////
LDQSP_TAP_DELAY_VAL : integer := 0;
UDQSP_TAP_DELAY_VAL : integer := 0;
LDQSN_TAP_DELAY_VAL : integer := 0;
UDQSN_TAP_DELAY_VAL : integer := 0;
DQ0_TAP_DELAY_VAL : integer := 0;
DQ1_TAP_DELAY_VAL : integer := 0;
DQ2_TAP_DELAY_VAL : integer := 0;
DQ3_TAP_DELAY_VAL : integer := 0;
DQ4_TAP_DELAY_VAL : integer := 0;
DQ5_TAP_DELAY_VAL : integer := 0;
DQ6_TAP_DELAY_VAL : integer := 0;
DQ7_TAP_DELAY_VAL : integer := 0;
DQ8_TAP_DELAY_VAL : integer := 0;
DQ9_TAP_DELAY_VAL : integer := 0;
DQ10_TAP_DELAY_VAL : integer := 0;
DQ11_TAP_DELAY_VAL : integer := 0;
DQ12_TAP_DELAY_VAL : integer := 0;
DQ13_TAP_DELAY_VAL : integer := 0;
DQ14_TAP_DELAY_VAL : integer := 0;
DQ15_TAP_DELAY_VAL : integer := 0;
C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
C_MC_CALIBRATION_CLK_DIV : integer := 1;
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "HALF";
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32
);
PORT (
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0);
p2_wr_data : in std_logic_vector(31 downto 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0);
p4_cmd_bl : in std_logic_vector(5 downto 0);
p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0);
p4_wr_data : in std_logic_vector(31 downto 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 downto 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 downto 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0);
p5_cmd_bl : in std_logic_vector(5 downto 0);
p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 downto 0);
p5_wr_data : in std_logic_vector(31 downto 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 downto 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcbx_dram_dqs : INOUT std_logic;
mcbx_dram_dqs_n : INOUT std_logic;
mcbx_dram_udqs : INOUT std_logic;
mcbx_dram_udqs_n : INOUT std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : INOUT std_logic;
zio : INOUT std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 downto 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 downto 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 downto 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 downto 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end mcb_raw_wrapper;
architecture aarch of mcb_raw_wrapper is
component mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR3" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end component;
constant C_OSERDES2_DATA_RATE_OQ : STRING := "SDR";
constant C_OSERDES2_DATA_RATE_OT : STRING := "SDR";
constant C_OSERDES2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_OSERDES2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_OSERDES2_OUTPUT_MODE_SE : STRING := "SINGLE_ENDED";
constant C_OSERDES2_OUTPUT_MODE_DIFF : STRING := "DIFFERENTIAL";
constant C_BUFPLL_0_LOCK_SRC : STRING := "LOCK_TO_0";
constant C_DQ_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQ_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQ_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_DQS_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQS_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQS_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
-- MIG always set the below ADD_LATENCY to zero
constant C_MEM_DDR3_ADD_LATENCY : STRING := "OFF";
constant C_MEM_DDR2_ADD_LATENCY : INTEGER := 0;
constant C_MEM_MOBILE_TC_SR : INTEGER := 0;
-- convert the memory timing to memory clock units. I
constant MEM_RAS_VAL : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RCD_VAL : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_REFI_VAL : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD) - 25;
constant MEM_RFC_VAL : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RP_VAL : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_WR_VAL : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
function cdiv return integer is
begin
if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then
return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1;
else
return (C_MEM_TRTP/C_MEMCLK_PERIOD);
end if;
end function cdiv;
constant MEM_RTP_VAL1 : INTEGER := cdiv;
function MEM_RTP_CYC1 return integer is
begin
if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then
return 4;
else if(MEM_RTP_VAL1 < 2) then
return 2;
else
return MEM_RTP_VAL1;
end if;
end if;
end function MEM_RTP_CYC1;
constant MEM_RTP_VAL : INTEGER := MEM_RTP_CYC1;
function MEM_WTR_CYC return integer is
begin
if (C_MEM_TYPE = "DDR") then
return 2;
elsif (C_MEM_TYPE = "DDR3") then
return 4;
elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then
return C_MEM_TWTR;
elsif (C_MEM_TYPE = "DDR2" AND (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then
return ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
elsif (C_MEM_TYPE = "DDR2")then
return 2;
else
return 3;
end if;
end function MEM_WTR_CYC;
constant MEM_WTR_VAL : INTEGER := MEM_WTR_CYC;
function DDR2_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR2")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR2_WRT_RECOVERY_CYC;
constant C_MEM_DDR2_WRT_RECOVERY : INTEGER := DDR2_WRT_RECOVERY_CYC;
function DDR3_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR3")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR3_WRT_RECOVERY_CYC;
constant C_MEM_DDR3_WRT_RECOVERY : INTEGER := DDR3_WRT_RECOVERY_CYC;
--CR 596422
constant allzero : std_logic_vector(127 downto 0) := (others => '0');
--signal allzero : std_logic_vector(127 downto 0) := (others => '0');
----------------------------------------------------------------------------
-- signal Declarations
----------------------------------------------------------------------------
signal addr_in0 : std_logic_vector(31 downto 0);
signal dqs_out_p : std_logic;
signal dqs_out_n : std_logic;
signal dqs_sys_p : std_logic; --from dqs_gen to IOclk network
signal dqs_sys_n : std_logic; --from dqs_gen to IOclk network
signal udqs_sys_p: std_logic;
signal udqs_sys_n: std_logic;
signal dqs_p : std_logic; -- open net now ?
signal dqs_n : std_logic; -- open net now ?
-- IOI and IOB enable/tristate interface
signal dqIO_w_en_0 : std_logic; --enable DQ pads
signal dqsIO_w_en_90_p : std_logic; --enable p side of DQS
signal dqsIO_w_en_90_n : std_logic; --enable n side of DQS
--memory chip control interface
signal address_90 : std_logic_vector(14 downto 0);
signal ba_90 : std_logic_vector(2 downto 0);
signal ras_90 : std_logic;
signal cas_90 : std_logic;
signal we_90 : std_logic;
signal cke_90 : std_logic;
signal odt_90 : std_logic;
signal rst_90 : std_logic;
-- calibration IDELAY control signals
signal ioi_drp_clk : std_logic; --DRP interface - synchronous clock output
signal ioi_drp_addr : std_logic_vector(4 downto 0); --DRP interface - IOI selection
signal ioi_drp_sdo : std_logic; --DRP interface - serial output for commmands
signal ioi_drp_sdi : std_logic; --DRP interface - serial input for commands
signal ioi_drp_cs : std_logic; --DRP interface - chip select doubles as DONE signal
signal ioi_drp_add : std_logic; --DRP interface - serial address signal
signal ioi_drp_broadcast : std_logic;
signal ioi_drp_train : std_logic;
-- Calibration datacapture siganls
signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux
signal dq_in_p : std_logic; --positive signal sent to calibration logic
signal dq_in_n : std_logic; --negative signal sent to calibration logic
signal cal_done: std_logic;
--DQS calibration interface
signal udqs_n : std_logic;
signal udqs_p : std_logic;
signal udqs_dqocal_p : std_logic;
signal udqs_dqocal_n : std_logic;
-- MUI enable interface
signal df_en_n90 : std_logic;
--INTERNAL signal FOR DRP chain
-- IOI <-> MUI
signal ioi_int_tmp : std_logic;
signal dqo_n : std_logic_vector(15 downto 0);
signal dqo_p : std_logic_vector(15 downto 0);
signal dqnlm : std_logic;
signal dqplm : std_logic;
signal dqnum : std_logic;
signal dqpum : std_logic;
-- IOI <-> IOB routes
signal ioi_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal ioi_cas : std_logic;
signal ioi_ck : std_logic;
signal ioi_ckn : std_logic;
signal ioi_cke : std_logic;
signal ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal ioi_dqs : std_logic;
signal ioi_dqsn : std_logic;
signal ioi_udqs : std_logic;
signal ioi_udqsn : std_logic;
signal ioi_odt : std_logic;
signal ioi_ras : std_logic;
signal ioi_rst : std_logic;
signal ioi_we : std_logic;
signal ioi_udm : std_logic;
signal ioi_ldm : std_logic;
signal in_dq : std_logic_vector(15 downto 0);
signal in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal in_dqs : std_logic;
signal in_pre_dqsp : std_logic;
signal in_pre_dqsn : std_logic;
signal in_pre_udqsp : std_logic;
signal in_pre_udqsn : std_logic;
signal in_udqs : std_logic;
-- Memory tri-state control signals
signal t_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal t_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal t_cas : std_logic;
signal t_ck : std_logic;
signal t_ckn : std_logic;
signal t_cke : std_logic;
signal t_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal t_dqs : std_logic;
signal t_dqsn : std_logic;
signal t_udqs : std_logic;
signal t_udqsn : std_logic;
signal t_odt : std_logic;
signal t_ras : std_logic;
signal t_rst : std_logic;
signal t_we : std_logic;
signal t_udm : std_logic;
signal t_ldm : std_logic;
signal idelay_dqs_ioi_s : std_logic;
signal idelay_dqs_ioi_m : std_logic;
signal idelay_udqs_ioi_s : std_logic;
signal idelay_udqs_ioi_m : std_logic;
signal dqs_pin : std_logic;
signal udqs_pin : std_logic;
-- USER Interface signals
-- translated memory addresses
signal p0_cmd_ra : std_logic_vector(14 downto 0);
signal p0_cmd_ba : std_logic_vector(2 downto 0);
signal p0_cmd_ca : std_logic_vector(11 downto 0);
signal p1_cmd_ra : std_logic_vector(14 downto 0);
signal p1_cmd_ba : std_logic_vector(2 downto 0);
signal p1_cmd_ca : std_logic_vector(11 downto 0);
signal p2_cmd_ra : std_logic_vector(14 downto 0);
signal p2_cmd_ba : std_logic_vector(2 downto 0);
signal p2_cmd_ca : std_logic_vector(11 downto 0);
signal p3_cmd_ra : std_logic_vector(14 downto 0);
signal p3_cmd_ba : std_logic_vector(2 downto 0);
signal p3_cmd_ca : std_logic_vector(11 downto 0);
signal p4_cmd_ra : std_logic_vector(14 downto 0);
signal p4_cmd_ba : std_logic_vector(2 downto 0);
signal p4_cmd_ca : std_logic_vector(11 downto 0);
signal p5_cmd_ra : std_logic_vector(14 downto 0);
signal p5_cmd_ba : std_logic_vector(2 downto 0);
signal p5_cmd_ca : std_logic_vector(11 downto 0);
-- user command wires mapped from logical ports to physical ports
signal mig_p0_arb_en : std_logic;
signal mig_p0_cmd_clk : std_logic;
signal mig_p0_cmd_en : std_logic;
signal mig_p0_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p0_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p0_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p0_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p0_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p0_cmd_empty : std_logic;
signal mig_p0_cmd_full : std_logic;
signal mig_p1_arb_en : std_logic;
signal mig_p1_cmd_clk : std_logic;
signal mig_p1_cmd_en : std_logic;
signal mig_p1_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p1_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p1_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p1_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p1_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p1_cmd_empty : std_logic;
signal mig_p1_cmd_full : std_logic;
signal mig_p2_arb_en : std_logic;
signal mig_p2_cmd_clk : std_logic;
signal mig_p2_cmd_en : std_logic;
signal mig_p2_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p2_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p2_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p2_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p2_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p2_cmd_empty : std_logic;
signal mig_p2_cmd_full : std_logic;
signal mig_p3_arb_en : std_logic;
signal mig_p3_cmd_clk : std_logic;
signal mig_p3_cmd_en : std_logic;
signal mig_p3_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p3_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p3_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p3_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p3_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p3_cmd_empty : std_logic;
signal mig_p3_cmd_full : std_logic;
signal mig_p4_arb_en : std_logic;
signal mig_p4_cmd_clk : std_logic;
signal mig_p4_cmd_en : std_logic;
signal mig_p4_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p4_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p4_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p4_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p4_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p4_cmd_empty : std_logic;
signal mig_p4_cmd_full : std_logic;
signal mig_p5_arb_en : std_logic;
signal mig_p5_cmd_clk : std_logic;
signal mig_p5_cmd_en : std_logic;
signal mig_p5_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p5_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p5_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p5_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p5_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p5_cmd_empty : std_logic;
signal mig_p5_cmd_full : std_logic;
signal mig_p0_wr_clk : std_logic;
signal mig_p0_rd_clk : std_logic;
signal mig_p1_wr_clk : std_logic;
signal mig_p1_rd_clk : std_logic;
signal mig_p2_clk : std_logic;
signal mig_p3_clk : std_logic;
signal mig_p4_clk : std_logic;
signal mig_p5_clk : std_logic;
signal mig_p0_wr_en : std_logic;
signal mig_p0_rd_en : std_logic;
signal mig_p1_wr_en : std_logic;
signal mig_p1_rd_en : std_logic;
signal mig_p2_en : std_logic;
signal mig_p3_en : std_logic;
signal mig_p4_en : std_logic;
signal mig_p5_en : std_logic;
signal mig_p0_wr_data : std_logic_vector(31 downto 0);
signal mig_p1_wr_data : std_logic_vector(31 downto 0);
signal mig_p2_wr_data : std_logic_vector(31 downto 0);
signal mig_p3_wr_data : std_logic_vector(31 downto 0);
signal mig_p4_wr_data : std_logic_vector(31 downto 0);
signal mig_p5_wr_data : std_logic_vector(31 downto 0);
signal mig_p0_wr_mask : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
signal mig_p1_wr_mask : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
signal mig_p2_wr_mask : std_logic_vector(3 downto 0);
signal mig_p3_wr_mask : std_logic_vector(3 downto 0);
signal mig_p4_wr_mask : std_logic_vector(3 downto 0);
signal mig_p5_wr_mask : std_logic_vector(3 downto 0);
signal mig_p0_rd_data : std_logic_vector(31 downto 0);
signal mig_p1_rd_data : std_logic_vector(31 downto 0);
signal mig_p2_rd_data : std_logic_vector(31 downto 0);
signal mig_p3_rd_data : std_logic_vector(31 downto 0);
signal mig_p4_rd_data : std_logic_vector(31 downto 0);
signal mig_p5_rd_data : std_logic_vector(31 downto 0);
signal mig_p0_rd_overflow : std_logic;
signal mig_p1_rd_overflow : std_logic;
signal mig_p2_overflow : std_logic;
signal mig_p3_overflow : std_logic;
signal mig_p4_overflow : std_logic;
signal mig_p5_overflow : std_logic;
signal mig_p0_wr_underrun : std_logic;
signal mig_p1_wr_underrun : std_logic;
signal mig_p2_underrun : std_logic;
signal mig_p3_underrun : std_logic;
signal mig_p4_underrun : std_logic;
signal mig_p5_underrun : std_logic;
signal mig_p0_rd_error : std_logic;
signal mig_p0_wr_error : std_logic;
signal mig_p1_rd_error : std_logic;
signal mig_p1_wr_error : std_logic;
signal mig_p2_error : std_logic;
signal mig_p3_error : std_logic;
signal mig_p4_error : std_logic;
signal mig_p5_error : std_logic;
signal mig_p0_wr_count : std_logic_vector(6 downto 0);
signal mig_p1_wr_count : std_logic_vector(6 downto 0);
signal mig_p0_rd_count : std_logic_vector(6 downto 0);
signal mig_p1_rd_count : std_logic_vector(6 downto 0);
signal mig_p2_count : std_logic_vector(6 downto 0);
signal mig_p3_count : std_logic_vector(6 downto 0);
signal mig_p4_count : std_logic_vector(6 downto 0);
signal mig_p5_count : std_logic_vector(6 downto 0);
signal mig_p0_wr_full : std_logic;
signal mig_p1_wr_full : std_logic;
signal mig_p0_rd_empty : std_logic;
signal mig_p1_rd_empty : std_logic;
signal mig_p0_wr_empty : std_logic;
signal mig_p1_wr_empty : std_logic;
signal mig_p0_rd_full : std_logic;
signal mig_p1_rd_full : std_logic;
signal mig_p2_full : std_logic;
signal mig_p3_full : std_logic;
signal mig_p4_full : std_logic;
signal mig_p5_full : std_logic;
signal mig_p2_empty : std_logic;
signal mig_p3_empty : std_logic;
signal mig_p4_empty : std_logic;
signal mig_p5_empty : std_logic;
-- SELFREESH control signal for suspend feature
signal selfrefresh_mcb_enter : std_logic;
signal selfrefresh_mcb_mode : std_logic;
signal selfrefresh_mode_sig : std_logic;
signal MCB_SYSRST : std_logic;
signal ioclk0 : std_logic;
signal ioclk90 : std_logic;
signal hard_done_cal : std_logic;
signal uo_data_int : std_logic_vector(7 downto 0);
signal uo_data_valid_int : std_logic;
signal uo_cmd_ready_in_int : std_logic;
signal syn_uiclk_pll_lock : std_logic;
signal int_sys_rst : std_logic;
--testing
signal ioi_drp_update : std_logic;
signal aux_sdi_sdo : std_logic_vector(7 downto 0);
signal mcb_recal : std_logic;
signal mcb_ui_read : std_logic;
signal mcb_ui_add : std_logic;
signal mcb_ui_cs : std_logic;
signal mcb_ui_clk : std_logic;
signal mcb_ui_sdi : std_logic;
signal mcb_ui_addr : STD_LOGIC_vector(4 downto 0);
signal mcb_ui_broadcast : std_logic;
signal mcb_ui_drp_update : std_logic;
signal mcb_ui_done_cal : std_logic;
signal mcb_ui_cmd : std_logic;
signal mcb_ui_cmd_in : std_logic;
signal mcb_ui_cmd_en : std_logic;
signal mcb_ui_dqcount : std_logic_vector(3 downto 0);
signal mcb_ui_dq_lower_dec : std_logic;
signal mcb_ui_dq_lower_inc : std_logic;
signal mcb_ui_dq_upper_dec : std_logic;
signal mcb_ui_dq_upper_inc : std_logic;
signal mcb_ui_udqs_inc : std_logic;
signal mcb_ui_udqs_dec : std_logic;
signal mcb_ui_ldqs_inc : std_logic;
signal mcb_ui_ldqs_dec : std_logic;
signal DONE_SOFTANDHARD_CAL : std_logic;
signal ck_shiftout0_1 : std_logic;
signal ck_shiftout0_2 : std_logic;
signal ck_shiftout1_3 : std_logic;
signal ck_shiftout1_4 : std_logic;
signal udm_oq : std_logic;
signal udm_t : std_logic;
signal ldm_oq : std_logic;
signal ldm_t : std_logic;
signal dqsp_oq : std_logic;
signal dqsp_tq : std_logic;
signal dqs_shiftout0_1 : std_logic;
signal dqs_shiftout0_2 : std_logic;
signal dqs_shiftout1_3 : std_logic;
signal dqs_shiftout1_4 : std_logic;
signal dqsn_oq : std_logic;
signal dqsn_tq : std_logic;
signal udqsp_oq : std_logic;
signal udqsp_tq : std_logic;
signal udqs_shiftout0_1 : std_logic;
signal udqs_shiftout0_2 : std_logic;
signal udqs_shiftout1_3 : std_logic;
signal udqs_shiftout1_4 : std_logic;
signal udqsn_oq : std_logic;
signal udqsn_tq : std_logic;
signal aux_sdi_out_dqsp : std_logic;
signal aux_sdi_out_udqsp : std_logic;
signal aux_sdi_out_udqsn : std_logic;
signal aux_sdi_out_0 : std_logic;
signal aux_sdi_out_1 : std_logic;
signal aux_sdi_out_2 : std_logic;
signal aux_sdi_out_3 : std_logic;
signal aux_sdi_out_5 : std_logic;
signal aux_sdi_out_6 : std_logic;
signal aux_sdi_out_7 : std_logic;
signal aux_sdi_out_9 : std_logic;
signal aux_sdi_out_10 : std_logic;
signal aux_sdi_out_11 : std_logic;
signal aux_sdi_out_12 : std_logic;
signal aux_sdi_out_13 : std_logic;
signal aux_sdi_out_14 : std_logic;
signal aux_sdi_out_15 : std_logic;
signal aux_sdi_out_8 : std_logic;
signal aux_sdi_out_dqsn : std_logic;
signal aux_sdi_out_4 : std_logic;
signal aux_sdi_out_udm : std_logic;
signal aux_sdi_out_ldm : std_logic;
signal uo_cal_start_int : std_logic;
signal cke_train : std_logic;
signal dq_oq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal dq_tq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal p0_wr_full_i : std_logic;
signal p0_rd_empty_i : std_logic;
signal p1_wr_full_i : std_logic;
signal p1_rd_empty_i : std_logic;
signal pllclk1 : std_logic_vector(1 downto 0);
signal pllce1 : std_logic_vector(1 downto 0);
signal uo_refrsh_flag_xhdl23 : std_logic;
signal uo_sdo_xhdl24 : STD_LOGIC;
signal Max_Value_Cal_Error : std_logic;
signal uo_done_cal_sig : std_logic;
signal wait_200us_counter : std_logic_vector(15 downto 0);
signal cke_train_reg : std_logic;
signal wait_200us_done_r1 : std_logic;
signal wait_200us_done_r2 : std_logic;
signal syn1_sys_rst : std_logic;
signal syn2_sys_rst : std_logic;
signal selfrefresh_enter_r1 : std_logic;
signal selfrefresh_enter_r2 : std_logic;
signal selfrefresh_enter_r3 : std_logic;
signal gated_pll_lock : std_logic;
signal soft_cal_selfrefresh_req : std_logic;
signal normal_operation_window : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute max_fanout of int_sys_rst : signal is "1";
attribute syn_maxfan of int_sys_rst : signal is 1;
begin
uo_cmd_ready_in <= uo_cmd_ready_in_int;
uo_data_valid <= uo_data_valid_int;
uo_data <= uo_data_int;
uo_refrsh_flag <= uo_refrsh_flag_xhdl23;
uo_sdo <= uo_sdo_xhdl24;
p0_wr_full <= p0_wr_full_i;
p0_rd_empty <= p0_rd_empty_i;
p1_wr_full <= p1_wr_full_i;
p1_rd_empty <= p1_rd_empty_i;
ioclk0 <= sysclk_2x;
ioclk90 <= sysclk_2x_180;
pllclk1 <= (ioclk90 & ioclk0);
pllce1 <= (pll_ce_90 & pll_ce_0);
-- Assign the output signals with corresponding intermediate signals
uo_done_cal <= uo_done_cal_sig;
-- Added 2/22 - Add flop to pll_lock status signal to improve timing
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if ((selfrefresh_enter = '0') and (gated_pll_lock = '0')) then
syn_uiclk_pll_lock <= pll_lock;
end if;
end if;
end process;
-- logic to determine if Memory is SELFREFRESH mode operation or NORMAL mode.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
normal_operation_window <= '1';
elsif (selfrefresh_enter_r2 = '1' or selfrefresh_mode_sig = '1') then
normal_operation_window <= '0';
elsif ((selfrefresh_enter_r2 = '0') and (selfrefresh_mode_sig = '0')) then
normal_operation_window <= '1';
else
normal_operation_window <= normal_operation_window;
end if;
end if;
end process;
process(normal_operation_window,pll_lock,syn_uiclk_pll_lock)
begin
if (normal_operation_window = '1') then
gated_pll_lock <= pll_lock;
else
gated_pll_lock <= syn_uiclk_pll_lock;
end if;
end process;
-- int_sys_rst will be asserted if pll lose lock during normal operation.
-- It uses the syn_uiclk_pll_lock version when it is entering suspend window , hence
-- reset will not be generated.
int_sys_rst <= sys_rst or not(gated_pll_lock);
-- synchronize the selfrefresh_enter
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
selfrefresh_enter_r1 <= '0';
selfrefresh_enter_r2 <= '0';
selfrefresh_enter_r3 <= '0';
else
selfrefresh_enter_r1 <= selfrefresh_enter;
selfrefresh_enter_r2 <= selfrefresh_enter_r1;
selfrefresh_enter_r3 <= selfrefresh_enter_r2;
end if;
end if;
end process;
-- The soft_cal_selfrefresh siganl is conditioned before connect to mcb_soft_calibration module.
-- It will not deassert selfrefresh_mcb_enter to MCB until input pll_lock reestablished in system.
-- This is to ensure the IOI stables before issued a selfrefresh exit command to dram.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
soft_cal_selfrefresh_req <= '0';
elsif (selfrefresh_enter_r3 = '1') then
soft_cal_selfrefresh_req <= '1';
elsif (selfrefresh_enter_r3 = '0' and pll_lock = '1') then
soft_cal_selfrefresh_req <= '0';
else
soft_cal_selfrefresh_req <= soft_cal_selfrefresh_req;
end if;
end if;
end process;
--Address Remapping
-- Byte Address remapping
--
-- Bank Address[x:0] & Row Address[x:0] & Column Address[x:0]
-- column address remap for port 0
x16_addr : if(C_NUM_DQ_PINS = 16) generate -- port bus remapping sections for CONFIG 2 15,3,12
x16_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row Column
-- port 0 address remapping
x16_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate; --x16_addr_rbc
x16_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x16_rbc_n_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p0_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_rbc_n_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p1_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_rbc_n_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p2_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_rbc_n_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p3_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_rbc_n_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p4_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_rbc_n_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p5_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate;--x16_addr_rbc_n
end generate; --x16_addr
x8_addr : if(C_NUM_DQ_PINS = 8) generate
x8_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x8_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 2 address remapping
x8_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,2,10 ***
end generate;
x8_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc
x8_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
--port 2 address remapping
x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) &
p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc_n
end generate; --x8_addr
x4_addr : if(C_NUM_DQ_PINS = 4) generate
x4_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x4_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5
end generate; --x4_addr_rbc
x4_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5_n: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5_n
end generate; --x4_addr_rbc_n
end generate; --x4_addr
-- if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
u_config1_0: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
--synthesis translate_off
-- PORT2
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 2";
end if;
end process;
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 2";
end if;
end process;
-- PORT3
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 3";
end if;
end process;
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 3";
end if;
end process;
-- PORT4
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 4";
end if;
end process;
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 4";
end if;
end process;
-- PORT5
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 5";
end if;
end process;
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 5";
end if;
end process;
--synthesis translate_on
-- the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up
-- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
-- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
--
-- Inputs from Application CMD Port
p0_cmd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty;
p0_cmd_full <= mig_p0_cmd_full ;
end generate;
p0_cmd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
end generate;
p1_cmd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p1_cmd_empty;
p1_cmd_full <= mig_p1_cmd_full ;
end generate;
p1_cmd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
end generate;
p2_cmd_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p2_cmd_empty;
p2_cmd_full <= mig_p2_cmd_full ;
end generate;
p2_cmd_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
end generate;
p3_cmd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_arb_en <= p3_arb_en ;
mig_p3_cmd_clk <= p3_cmd_clk ;
mig_p3_cmd_en <= p3_cmd_en ;
mig_p3_cmd_ra <= p3_cmd_ra ;
mig_p3_cmd_ba <= p3_cmd_ba ;
mig_p3_cmd_ca <= p3_cmd_ca ;
mig_p3_cmd_instr <= p3_cmd_instr;
mig_p3_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
p3_cmd_empty <= mig_p3_cmd_empty;
p3_cmd_full <= mig_p3_cmd_full ;
end generate;
p3_cmd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
p3_cmd_empty <= '0';
p3_cmd_full <= '0';
end generate;
p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_arb_en <= p4_arb_en ;
mig_p4_cmd_clk <= p4_cmd_clk ;
mig_p4_cmd_en <= p4_cmd_en ;
mig_p4_cmd_ra <= p4_cmd_ra ;
mig_p4_cmd_ba <= p4_cmd_ba ;
mig_p4_cmd_ca <= p4_cmd_ca ;
mig_p4_cmd_instr <= p4_cmd_instr;
mig_p4_cmd_bl <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0)) ;
p4_cmd_empty <= mig_p4_cmd_empty;
p4_cmd_full <= mig_p4_cmd_full ;
end generate;
p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
end generate;
p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_arb_en <= p5_arb_en ;
mig_p5_cmd_clk <= p5_cmd_clk ;
mig_p5_cmd_en <= p5_cmd_en ;
mig_p5_cmd_ra <= p5_cmd_ra ;
mig_p5_cmd_ba <= p5_cmd_ba ;
mig_p5_cmd_ca <= p5_cmd_ca ;
mig_p5_cmd_instr <= p5_cmd_instr;
mig_p5_cmd_bl <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0)) ;
p5_cmd_empty <= mig_p5_cmd_empty;
p5_cmd_full <= mig_p5_cmd_full ;
end generate;
p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
end generate;
p0_wr_rd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
mig_p0_wr_data <= p0_wr_data(31 downto 0);
p0_rd_data <= mig_p0_rd_data;
p0_rd_full <= mig_p0_rd_full;
p0_rd_empty_i <= mig_p0_rd_empty;
p0_rd_error <= mig_p0_rd_error;
p0_wr_error <= mig_p0_wr_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p0_wr_full_i <= mig_p0_wr_full;
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_wr_rd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_rd_en <= '0';
mig_p0_wr_mask <= (others => '0');
mig_p0_wr_data <= (others => '0');
p0_rd_data <= (others => '0');
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
p0_rd_error <= '0';
p0_wr_error <= '0';
p0_rd_overflow <= '0';
p0_wr_underrun <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_wr_rd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_clk <= p1_rd_clk;
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_rd_en <= p1_rd_en;
p1_rd_data <= mig_p1_rd_data;
p1_rd_empty_i <= mig_p1_rd_empty;
p1_rd_full <= mig_p1_rd_full;
p1_rd_error <= mig_p1_rd_error;
p1_wr_error <= mig_p1_wr_error;
p1_rd_overflow <= mig_p1_rd_overflow;
p1_wr_underrun <= mig_p1_wr_underrun;
p1_wr_empty <= mig_p1_wr_empty;
p1_wr_full_i <= mig_p1_wr_full;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count ;
end generate;
p1_wr_rd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p1_wr_en <= '0';
mig_p1_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_rd_en <= '0';
p1_rd_data <= (others => '0');
p1_rd_empty_i <= '0';
p1_rd_full <= '0';
p1_rd_error <= '0';
p1_wr_error <= '0';
p1_rd_overflow <= '0';
p1_wr_underrun <= '0';
p1_wr_empty <= '0';
p1_wr_full_i <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
end generate;
--whenever PORT 2 is in Write mode
-- xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE
--u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate
u_config1_2W: if( C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
p2_wr_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_wr_clk;
mig_p2_wr_data <= p2_wr_data(31 downto 0);
mig_p2_wr_mask <= p2_wr_mask(3 downto 0);
mig_p2_en <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir
p2_wr_error <= mig_p2_error;
p2_wr_full <= mig_p2_full;
p2_wr_empty <= mig_p2_empty;
p2_wr_underrun <= mig_p2_underrun;
p2_wr_count <= mig_p2_count ;-- wr port
end generate;
p2_wr_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
mig_p2_en <= '0';
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
p2_rd_data <= (others => '0');
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
-- p2_rd_error <= '0';
end generate;
--u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate
u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate
p2_rd_ena : if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_rd_clk;
p2_rd_data <= mig_p2_rd_data;
mig_p2_en <= p2_rd_en;
p2_rd_overflow <= mig_p2_overflow;
p2_rd_error <= mig_p2_error;
p2_rd_full <= mig_p2_full;
p2_rd_empty <= mig_p2_empty;
p2_rd_count <= mig_p2_count ;-- wr port
end generate;
p2_rd_dis : if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
p2_rd_data <= (others => '0');
mig_p2_en <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
end generate;
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
--u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64) = "W32") generate --whenever PORT 3 is in Write mode
u_config1_3W: if(
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode
p3_wr_ena: if (C_PORT_ENABLE(3) = '1')generate
mig_p3_clk <= p3_wr_clk;
mig_p3_wr_data <= p3_wr_data(31 downto 0);
mig_p3_wr_mask <= p3_wr_mask(3 downto 0);
mig_p3_en <= p3_wr_en;
p3_wr_full <= mig_p3_full;
p3_wr_empty <= mig_p3_empty;
p3_wr_underrun <= mig_p3_underrun;
p3_wr_count <= mig_p3_count ;-- wr port
p3_wr_error <= mig_p3_error;
end generate;
p3_wr_dis: if (C_PORT_ENABLE(3) = '0')generate
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p3_en <= '0';
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
end generate;
p3_rd_overflow <= '0';
p3_rd_error <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_data <= (others => '0');
end generate;
u_config1_3R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate
p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_clk <= p3_rd_clk;
p3_rd_data <= mig_p3_rd_data;
mig_p3_en <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir
p3_rd_overflow <= mig_p3_overflow;
p3_rd_error <= mig_p3_error;
p3_rd_full <= mig_p3_full;
p3_rd_empty <= mig_p3_empty;
p3_rd_count <= mig_p3_count ;-- wr port
end generate;
p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_clk <= '0';
mig_p3_en <= '0';
p3_rd_overflow <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_error <= '0';
p3_rd_data <= (others => '0');
end generate;
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
end generate;
u_config1_4W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 4 is in Write mode
p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_wr_clk;
mig_p4_wr_data <= p4_wr_data(31 downto 0);
mig_p4_wr_mask <= p4_wr_mask(3 downto 0);
mig_p4_en <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir
p4_wr_full <= mig_p4_full;
p4_wr_empty <= mig_p4_empty;
p4_wr_underrun <= mig_p4_underrun;
p4_wr_count <= mig_p4_count ;-- wr port
p4_wr_error <= mig_p4_error;
end generate;
p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p4_en <= '0';
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
end generate;
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
p4_rd_data <= (others => '0');
end generate;
u_config1_4R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate
p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_rd_clk;
p4_rd_data <= mig_p4_rd_data;
mig_p4_en <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir
p4_rd_overflow <= mig_p4_overflow;
p4_rd_error <= mig_p4_error;
p4_rd_full <= mig_p4_full;
p4_rd_empty <= mig_p4_empty;
p4_rd_count <= mig_p4_count ;-- wr port
end generate;
p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
p4_rd_data <= (others => '0');
mig_p4_en <= '0';
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
end generate;
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
end generate;
u_config1_5W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 5 is in Write mode
p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_clk <= p5_wr_clk;
mig_p5_wr_data <= p5_wr_data(31 downto 0);
mig_p5_wr_mask <= p5_wr_mask(3 downto 0);
mig_p5_en <= p5_wr_en;
p5_wr_full <= mig_p5_full;
p5_wr_empty <= mig_p5_empty;
p5_wr_underrun <= mig_p5_underrun;
p5_wr_count <= mig_p5_count ;
p5_wr_error <= mig_p5_error;
end generate;
p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_clk <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p5_en <= '0';
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
end generate;
p5_rd_data <= (others => '0');
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
u_config1_5R :if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate
p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate
mig_p5_clk <= p5_rd_clk;
p5_rd_data <= mig_p5_rd_data;
mig_p5_en <= p5_rd_en;
p5_rd_overflow <= mig_p5_overflow;
p5_rd_error <= mig_p5_error;
p5_rd_full <= mig_p5_full;
p5_rd_empty <= mig_p5_empty;
p5_rd_count <= mig_p5_count ;
end generate;
p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate
mig_p5_clk <= '0';
p5_rd_data <= (others => '0');
mig_p5_en <= '0';
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
end generate;
--//////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
----
---- B32_B32_B32_B32
----
--///////////////////////////////////////////////////////////////////////////
--//////////////////////////////////////////////////////////////////////////
u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate
-- Inputs from Application CMD Port
-- ************* need to hook up rd /wr error outputs
p0_c2_ena: if (C_PORT_ENABLE(0) = '1') generate
-- command port signals
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_c2_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_rd_en <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate
-- command port signals
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_en <= p1_rd_en;
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_rd_clk <= p1_rd_clk;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count;
end generate;
p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
-- Data port signals
mig_p1_wr_en <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_en <= '0';
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
mig_p1_rd_clk <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate
--MCB Physical port Logical Port
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
mig_p2_en <= p2_rd_en;
mig_p2_clk <= p2_rd_clk;
mig_p3_en <= p2_wr_en;
mig_p3_clk <= p2_wr_clk;
mig_p3_wr_data <= p2_wr_data(31 downto 0);
mig_p3_wr_mask <= p2_wr_mask(3 downto 0);
p2_wr_count <= mig_p3_count;
p2_rd_count <= mig_p2_count;
end generate;
p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_en <= '0';
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_count <= (others => '0');
end generate;
p3_c2_ena: if (C_PORT_ENABLE(3) = '1') generate
--MCB Physical port Logical Port
mig_p4_arb_en <= p3_arb_en ;
mig_p4_cmd_clk <= p3_cmd_clk ;
mig_p4_cmd_en <= p3_cmd_en ;
mig_p4_cmd_ra <= p3_cmd_ra ;
mig_p4_cmd_ba <= p3_cmd_ba ;
mig_p4_cmd_ca <= p3_cmd_ca ;
mig_p4_cmd_instr <= p3_cmd_instr;
mig_p4_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
mig_p4_clk <= p3_rd_clk;
mig_p4_en <= p3_rd_en;
mig_p5_clk <= p3_wr_clk;
mig_p5_en <= p3_wr_en;
mig_p5_wr_data <= p3_wr_data(31 downto 0);
mig_p5_wr_mask <= p3_wr_mask(3 downto 0);
p3_rd_count <= mig_p4_count;
p3_wr_count <= mig_p5_count;
end generate;
p3_c2_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p4_clk <= '0';
mig_p4_en <= '0';
mig_p5_clk <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
p3_rd_count <= (others => '0');
p3_wr_count <= (others => '0');
end generate;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p1_cmd_empty <= mig_p1_cmd_empty ;
p1_cmd_full <= mig_p1_cmd_full ;
p2_cmd_empty <= mig_p2_cmd_empty ;
p2_cmd_full <= mig_p2_cmd_full ;
p3_cmd_empty <= mig_p4_cmd_empty ;
p3_cmd_full <= mig_p4_cmd_full ;
-- outputs to Applications User Port
p0_rd_data <= mig_p0_rd_data;
p1_rd_data <= mig_p1_rd_data;
p2_rd_data <= mig_p2_rd_data;
p3_rd_data <= mig_p4_rd_data;
p0_rd_empty_i <= mig_p0_rd_empty;
p1_rd_empty_i <= mig_p1_rd_empty;
p2_rd_empty <= mig_p2_empty;
p3_rd_empty <= mig_p4_empty;
p0_rd_full <= mig_p0_rd_full;
p1_rd_full <= mig_p1_rd_full;
p2_rd_full <= mig_p2_full;
p3_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error;
p1_rd_error <= mig_p1_rd_error;
p2_rd_error <= mig_p2_error;
p3_rd_error <= mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p1_rd_overflow <= mig_p1_rd_overflow;
p2_rd_overflow <= mig_p2_overflow;
p3_rd_overflow <= mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p1_wr_underrun <= mig_p1_wr_underrun;
p2_wr_underrun <= mig_p3_underrun;
p3_wr_underrun <= mig_p5_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p1_wr_empty <= mig_p1_wr_empty;
p2_wr_empty <= mig_p3_empty;
p3_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p0_wr_full;
p1_wr_full_i <= mig_p1_wr_full;
p2_wr_full <= mig_p3_full;
p3_wr_full <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error;
p1_wr_error <= mig_p1_wr_error;
p2_wr_error <= mig_p3_error;
p3_wr_error <= mig_p5_error;
-- unused ports signals
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
mig_p2_wr_mask <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p2_wr_data <= (others => '0');
mig_p4_wr_data <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--
--
-- --//////////////////////////////////////////////////////////////////////////
-- --///////////////////////////////////////////////////////////////////////////
-- ----
-- ---- B64_B32_B32
-- ----
-- --///////////////////////////////////////////////////////////////////////////
-- --//////////////////////////////////////////////////////////////////////////
--
--
--
u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate
-- Inputs from Application CMD Port
p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
p0_rd_empty_i <= mig_p1_rd_empty;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_wr_count <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output
p0_rd_count <= mig_p1_rd_count;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
end generate;
p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
p0_rd_empty_i <= '0';
p0_rd_data <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_empty <= '0';
p0_wr_error <= '0';
p0_wr_full_i <= '0';
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
end generate;
p1_c3_ena: if (C_PORT_ENABLE(1) = '1')generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p2_cmd_empty;
p1_cmd_full <= mig_p2_cmd_full;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en;
p1_rd_data <= mig_p2_rd_data;
p1_wr_count <= mig_p3_count;
p1_rd_count <= mig_p2_count;
p1_wr_empty <= mig_p3_empty;
p1_wr_error <= mig_p3_error;
p1_wr_full_i <= mig_p3_full;
p1_wr_underrun <= mig_p3_underrun;
p1_rd_overflow <= mig_p2_overflow;
p1_rd_error <= mig_p2_error;
p1_rd_full <= mig_p2_full;
p1_rd_empty_i <= mig_p2_empty;
end generate;
p1_c3_dis: if (C_PORT_ENABLE(1) = '0')generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
mig_p3_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_clk <= '0';
p1_rd_data <= (others => '0');
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_empty <= '0';
p1_wr_error <= '0';
p1_wr_full_i <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
end generate;
p2_c3_ena: if (C_PORT_ENABLE(2) = '1')generate
mig_p4_arb_en <= p2_arb_en ;
mig_p4_cmd_clk <= p2_cmd_clk ;
mig_p4_cmd_en <= p2_cmd_en ;
mig_p4_cmd_ra <= p2_cmd_ra ;
mig_p4_cmd_ba <= p2_cmd_ba ;
mig_p4_cmd_ca <= p2_cmd_ca ;
mig_p4_cmd_instr <= p2_cmd_instr;
mig_p4_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p4_cmd_empty ;
p2_cmd_full <= mig_p4_cmd_full ;
mig_p5_en <= p2_wr_en;
mig_p5_wr_data <= p2_wr_data(31 downto 0);
mig_p5_wr_mask <= p2_wr_mask(3 downto 0);
mig_p4_en <= p2_rd_en;
mig_p4_clk <= p2_rd_clk;
mig_p5_clk <= p2_wr_clk;
p2_rd_data <= mig_p4_rd_data;
p2_wr_count <= mig_p5_count;
p2_rd_count <= mig_p4_count;
p2_wr_empty <= mig_p5_empty;
p2_wr_full <= mig_p5_full;
p2_wr_error <= mig_p5_error;
p2_wr_underrun <= mig_p5_underrun;
p2_rd_overflow <= mig_p4_overflow;
p2_rd_error <= mig_p4_error;
p2_rd_full <= mig_p4_full;
p2_rd_empty <= mig_p4_empty;
end generate;
p2_c3_dis: if (C_PORT_ENABLE(2) = '0')generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p4_en <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
p2_rd_data <= (others => '0');
p2_wr_count <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_empty <= '0';
p2_wr_full <= '0';
p2_wr_error <= '0';
p2_wr_underrun <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
end generate;
-- MCB's port 1,3,5 is not used in this Config mode
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate
-- Inputs from Application CMD Port
p0_c4_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p1_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_count <= mig_p1_wr_count;
p0_rd_count <= mig_p1_rd_count;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
p0_rd_empty_i <= mig_p1_rd_empty;
end generate;
p0_c4_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
-- mig_p1_wr_en <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_rd_data <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_error <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
end generate;
p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p4_clk <= p1_rd_clk;
mig_p5_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en and not p1_wr_full_i;
mig_p5_en <= p1_wr_en and not p1_wr_full_i;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p5_wr_data <= p1_wr_data(63 downto 32);
mig_p5_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en and not p1_rd_empty_i;
mig_p4_en <= p1_rd_en and not p1_rd_empty_i;
p1_cmd_empty <= mig_p2_cmd_empty ;
p1_cmd_full <= mig_p2_cmd_full ;
p1_wr_count <= mig_p5_count;
p1_rd_count <= mig_p4_count;
p1_wr_full_i <= mig_p5_full;
p1_wr_error <= mig_p5_error or mig_p5_error;
p1_wr_empty <= mig_p5_empty;
p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun;
p1_rd_overflow <= mig_p4_overflow;
p1_rd_error <= mig_p4_error;
p1_rd_full <= mig_p4_full;
p1_rd_empty_i <= mig_p4_empty;
p1_rd_data <= (mig_p4_rd_data & mig_p2_rd_data);
end generate;
p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p2_arb_en <= '0';
-- mig_p3_arb_en <= (others => '0');
-- mig_p4_arb_en <= (others => '0');
-- mig_p5_arb_en <= (others => '0');
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_clk <= '0';
mig_p3_clk <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
mig_p3_en <= '0';
mig_p5_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p4_en <= '0';
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_full_i <= '0';
p1_wr_error <= '0';
p1_wr_empty <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
p1_rd_data <= (others => '0');
end generate;
-- unused MCB's signals in this configuration
mig_p3_arb_en <= '0';
mig_p4_arb_en <= '0';
mig_p5_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--*******************************BEGIN OF CONFIG 5 SIGNALS ********************************
u_config_5: if(C_PORT_CONFIG = "B128" ) generate
-- Inputs from Application CMD Port
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
-- Inputs from Application User Port
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p2_clk <= p0_rd_clk;
mig_p3_clk <= p0_wr_clk;
mig_p4_clk <= p0_rd_clk;
mig_p5_clk <= p0_wr_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p3_en <= p0_wr_en and not p0_wr_full_i;
mig_p5_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p3_wr_data <= p0_wr_data(95 downto 64);
mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11 downto 8);
mig_p5_wr_data <= p0_wr_data(127 downto 96);
mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15 downto 12);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p2_en <= p0_rd_en and not p0_rd_empty_i;
mig_p4_en <= p0_rd_en and not p0_rd_empty_i;
-- outputs to Applications User Port
p0_rd_data <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data);
p0_rd_empty_i <= mig_p4_empty;
p0_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun;
p0_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error;
p0_wr_count <= mig_p5_count;
p0_rd_count <= mig_p4_count;
-- unused MCB's siganls in this configuration
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
--*******************************END OF CONFIG 5 SIGNALS ********************************
end generate;
uo_cal_start <= uo_cal_start_int;
samc_0: MCB
GENERIC MAP
( PORT_CONFIG => C_PORT_CONFIG,
MEM_WIDTH => C_NUM_DQ_PINS ,
MEM_TYPE => C_MEM_TYPE ,
MEM_BURST_LEN => C_MEM_BURST_LEN ,
MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY ,
MEM_DDR2_WRT_RECOVERY => C_MEM_DDR2_WRT_RECOVERY ,
MEM_DDR3_WRT_RECOVERY => C_MEM_DDR3_WRT_RECOVERY ,
MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR ,
MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS ,
MEM_DDR3_ODS => C_MEM_DDR3_ODS ,
MEM_DDR2_RTT => C_MEM_DDR2_RTT ,
MEM_DDR3_RTT => C_MEM_DDR3_RTT ,
MEM_DDR3_ADD_LATENCY => C_MEM_DDR3_ADD_LATENCY ,
MEM_DDR2_ADD_LATENCY => C_MEM_DDR2_ADD_LATENCY ,
MEM_MOBILE_TC_SR => C_MEM_MOBILE_TC_SR ,
MEM_MDDR_ODS => C_MEM_MDDR_ODS ,
MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN ,
MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR ,
MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR ,
MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT ,
MEM_RA_SIZE => C_MEM_ADDR_WIDTH ,
MEM_BA_SIZE => C_MEM_BANKADDR_WIDTH ,
MEM_CA_SIZE => C_MEM_NUM_COL_BITS ,
MEM_RAS_VAL => MEM_RAS_VAL ,
MEM_RCD_VAL => MEM_RCD_VAL ,
MEM_REFI_VAL => MEM_REFI_VAL ,
MEM_RFC_VAL => MEM_RFC_VAL ,
MEM_RP_VAL => MEM_RP_VAL ,
MEM_WR_VAL => MEM_WR_VAL ,
MEM_RTP_VAL => MEM_RTP_VAL ,
MEM_WTR_VAL => MEM_WTR_VAL ,
CAL_BYPASS => C_MC_CALIB_BYPASS,
CAL_RA => C_MC_CALIBRATION_RA,
CAL_BA => C_MC_CALIBRATION_BA ,
CAL_CA => C_MC_CALIBRATION_CA,
CAL_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
CAL_DELAY => C_MC_CALIBRATION_DELAY,
-- CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE,
ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
ARB_TIME_SLOT_0 => C_ARB_TIME_SLOT_0,
ARB_TIME_SLOT_1 => C_ARB_TIME_SLOT_1,
ARB_TIME_SLOT_2 => C_ARB_TIME_SLOT_2,
ARB_TIME_SLOT_3 => C_ARB_TIME_SLOT_3,
ARB_TIME_SLOT_4 => C_ARB_TIME_SLOT_4,
ARB_TIME_SLOT_5 => C_ARB_TIME_SLOT_5,
ARB_TIME_SLOT_6 => C_ARB_TIME_SLOT_6,
ARB_TIME_SLOT_7 => C_ARB_TIME_SLOT_7,
ARB_TIME_SLOT_8 => C_ARB_TIME_SLOT_8,
ARB_TIME_SLOT_9 => C_ARB_TIME_SLOT_9,
ARB_TIME_SLOT_10 => C_ARB_TIME_SLOT_10,
ARB_TIME_SLOT_11 => C_ARB_TIME_SLOT_11
) PORT MAP
(
-- HIGH-SPEED PLL clock interface
PLLCLK => pllclk1,
PLLCE => pllce1,
PLLLOCK => '1',
-- DQS CLOCK NETWork interface
DQSIOIN => idelay_dqs_ioi_s,
DQSIOIP => idelay_dqs_ioi_m,
UDQSIOIN => idelay_udqs_ioi_s,
UDQSIOIP => idelay_udqs_ioi_m,
--DQSPIN => in_pre_dqsp,
DQI => in_dq,
-- RESETS - GLOBAl and local
SYSRST => MCB_SYSRST ,
-- command port 0
P0ARBEN => mig_p0_arb_en,
P0CMDCLK => mig_p0_cmd_clk,
P0CMDEN => mig_p0_cmd_en,
P0CMDRA => mig_p0_cmd_ra,
P0CMDBA => mig_p0_cmd_ba,
P0CMDCA => mig_p0_cmd_ca,
P0CMDINSTR => mig_p0_cmd_instr,
P0CMDBL => mig_p0_cmd_bl,
P0CMDEMPTY => mig_p0_cmd_empty,
P0CMDFULL => mig_p0_cmd_full,
-- command port 1
P1ARBEN => mig_p1_arb_en,
P1CMDCLK => mig_p1_cmd_clk,
P1CMDEN => mig_p1_cmd_en,
P1CMDRA => mig_p1_cmd_ra,
P1CMDBA => mig_p1_cmd_ba,
P1CMDCA => mig_p1_cmd_ca,
P1CMDINSTR => mig_p1_cmd_instr,
P1CMDBL => mig_p1_cmd_bl,
P1CMDEMPTY => mig_p1_cmd_empty,
P1CMDFULL => mig_p1_cmd_full,
-- command port 2
P2ARBEN => mig_p2_arb_en,
P2CMDCLK => mig_p2_cmd_clk,
P2CMDEN => mig_p2_cmd_en,
P2CMDRA => mig_p2_cmd_ra,
P2CMDBA => mig_p2_cmd_ba,
P2CMDCA => mig_p2_cmd_ca,
P2CMDINSTR => mig_p2_cmd_instr,
P2CMDBL => mig_p2_cmd_bl,
P2CMDEMPTY => mig_p2_cmd_empty,
P2CMDFULL => mig_p2_cmd_full,
-- command port 3
P3ARBEN => mig_p3_arb_en,
P3CMDCLK => mig_p3_cmd_clk,
P3CMDEN => mig_p3_cmd_en,
P3CMDRA => mig_p3_cmd_ra,
P3CMDBA => mig_p3_cmd_ba,
P3CMDCA => mig_p3_cmd_ca,
P3CMDINSTR => mig_p3_cmd_instr,
P3CMDBL => mig_p3_cmd_bl,
P3CMDEMPTY => mig_p3_cmd_empty,
P3CMDFULL => mig_p3_cmd_full,
-- command port 4 -- don't care in config 2
P4ARBEN => mig_p4_arb_en,
P4CMDCLK => mig_p4_cmd_clk,
P4CMDEN => mig_p4_cmd_en,
P4CMDRA => mig_p4_cmd_ra,
P4CMDBA => mig_p4_cmd_ba,
P4CMDCA => mig_p4_cmd_ca,
P4CMDINSTR => mig_p4_cmd_instr,
P4CMDBL => mig_p4_cmd_bl,
P4CMDEMPTY => mig_p4_cmd_empty,
P4CMDFULL => mig_p4_cmd_full,
-- command port 5-- don't care in config 2
P5ARBEN => mig_p5_arb_en,
P5CMDCLK => mig_p5_cmd_clk,
P5CMDEN => mig_p5_cmd_en,
P5CMDRA => mig_p5_cmd_ra,
P5CMDBA => mig_p5_cmd_ba,
P5CMDCA => mig_p5_cmd_ca,
P5CMDINSTR => mig_p5_cmd_instr,
P5CMDBL => mig_p5_cmd_bl,
P5CMDEMPTY => mig_p5_cmd_empty,
P5CMDFULL => mig_p5_cmd_full,
-- IOI & IOB SIGNals/tristate interface
DQIOWEN0 => dqIO_w_en_0,
DQSIOWEN90P => dqsIO_w_en_90_p,
DQSIOWEN90N => dqsIO_w_en_90_n,
-- IOB MEMORY INTerface signals
ADDR => address_90,
BA => ba_90 ,
RAS => ras_90 ,
CAS => cas_90 ,
WE => we_90 ,
CKE => cke_90 ,
ODT => odt_90 ,
RST => rst_90 ,
-- CALIBRATION DRP interface
IOIDRPCLK => ioi_drp_clk ,
IOIDRPADDR => ioi_drp_addr ,
IOIDRPSDO => ioi_drp_sdo ,
IOIDRPSDI => ioi_drp_sdi ,
IOIDRPCS => ioi_drp_cs ,
IOIDRPADD => ioi_drp_add ,
IOIDRPBROADCAST => ioi_drp_broadcast ,
IOIDRPTRAIN => ioi_drp_train ,
IOIDRPUPDATE => ioi_drp_update ,
-- CALIBRATION DAtacapture interface
--SPECIAL COMMANDs
RECAL => mcb_recal ,
UIREAD => mcb_ui_read,
UIADD => mcb_ui_add ,
UICS => mcb_ui_cs ,
UICLK => mcb_ui_clk ,
UISDI => mcb_ui_sdi ,
UIADDR => mcb_ui_addr ,
UIBROADCAST => mcb_ui_broadcast,
UIDRPUPDATE => mcb_ui_drp_update,
UIDONECAL => mcb_ui_done_cal,
UICMD => mcb_ui_cmd,
UICMDIN => mcb_ui_cmd_in,
UICMDEN => mcb_ui_cmd_en,
UIDQCOUNT => mcb_ui_dqcount,
UIDQLOWERDEC => mcb_ui_dq_lower_dec,
UIDQLOWERINC => mcb_ui_dq_lower_inc,
UIDQUPPERDEC => mcb_ui_dq_upper_dec,
UIDQUPPERINC => mcb_ui_dq_upper_inc,
UIUDQSDEC => mcb_ui_udqs_dec,
UIUDQSINC => mcb_ui_udqs_inc,
UILDQSDEC => mcb_ui_ldqs_dec,
UILDQSINC => mcb_ui_ldqs_inc,
UODATA => uo_data_int,
UODATAVALID => uo_data_valid_int,
UODONECAL => hard_done_cal ,
UOCMDREADYIN => uo_cmd_ready_in_int,
UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
UOCALSTART => uo_cal_start_int,
UOSDO => uo_sdo_xhdl24,
--CONTROL SIGNALS
STATUS => status,
SELFREFRESHENTER => selfrefresh_mcb_enter,
SELFREFRESHMODE => selfrefresh_mcb_mode,
------------------------------------------------
--MUIs
------------------------------------------------
P0RDDATA => mig_p0_rd_data ( 31 downto 0),
P1RDDATA => mig_p1_rd_data ( 31 downto 0),
P2RDDATA => mig_p2_rd_data ( 31 downto 0),
P3RDDATA => mig_p3_rd_data ( 31 downto 0),
P4RDDATA => mig_p4_rd_data ( 31 downto 0),
P5RDDATA => mig_p5_rd_data ( 31 downto 0),
LDMN => dqnlm ,
UDMN => dqnum ,
DQON => dqo_n ,
DQOP => dqo_p ,
LDMP => dqplm ,
UDMP => dqpum ,
P0RDCOUNT => mig_p0_rd_count ,
P0WRCOUNT => mig_p0_wr_count ,
P1RDCOUNT => mig_p1_rd_count ,
P1WRCOUNT => mig_p1_wr_count ,
P2COUNT => mig_p2_count ,
P3COUNT => mig_p3_count ,
P4COUNT => mig_p4_count ,
P5COUNT => mig_p5_count ,
-- NEW ADDED FIFo status siganls
-- MIG USER PORT 0
P0RDEMPTY => mig_p0_rd_empty,
P0RDFULL => mig_p0_rd_full,
P0RDOVERFLOW => mig_p0_rd_overflow,
P0WREMPTY => mig_p0_wr_empty,
P0WRFULL => mig_p0_wr_full,
P0WRUNDERRUN => mig_p0_wr_underrun,
-- MIG USER PORT 1
P1RDEMPTY => mig_p1_rd_empty,
P1RDFULL => mig_p1_rd_full,
P1RDOVERFLOW => mig_p1_rd_overflow,
P1WREMPTY => mig_p1_wr_empty,
P1WRFULL => mig_p1_wr_full,
P1WRUNDERRUN => mig_p1_wr_underrun,
-- MIG USER PORT 2
P2EMPTY => mig_p2_empty,
P2FULL => mig_p2_full,
P2RDOVERFLOW => mig_p2_overflow,
P2WRUNDERRUN => mig_p2_underrun,
P3EMPTY => mig_p3_empty ,
P3FULL => mig_p3_full ,
P3RDOVERFLOW => mig_p3_overflow,
P3WRUNDERRUN => mig_p3_underrun ,
-- MIG USER PORT 3
P4EMPTY => mig_p4_empty,
P4FULL => mig_p4_full,
P4RDOVERFLOW => mig_p4_overflow,
P4WRUNDERRUN => mig_p4_underrun,
P5EMPTY => mig_p5_empty ,
P5FULL => mig_p5_full ,
P5RDOVERFLOW => mig_p5_overflow,
P5WRUNDERRUN => mig_p5_underrun,
---------------------------------------------------------
P0WREN => mig_p0_wr_en,
P0RDEN => mig_p0_rd_en,
P1WREN => mig_p1_wr_en,
P1RDEN => mig_p1_rd_en,
P2EN => mig_p2_en,
P3EN => mig_p3_en,
P4EN => mig_p4_en,
P5EN => mig_p5_en,
-- WRITE MASK BIts connection
P0RWRMASK => mig_p0_wr_mask(3 downto 0),
P1RWRMASK => mig_p1_wr_mask(3 downto 0),
P2WRMASK => mig_p2_wr_mask(3 downto 0),
P3WRMASK => mig_p3_wr_mask(3 downto 0),
P4WRMASK => mig_p4_wr_mask(3 downto 0),
P5WRMASK => mig_p5_wr_mask(3 downto 0),
-- DATA WRITE COnnection
P0WRDATA => mig_p0_wr_data(31 downto 0),
P1WRDATA => mig_p1_wr_data(31 downto 0),
P2WRDATA => mig_p2_wr_data(31 downto 0),
P3WRDATA => mig_p3_wr_data(31 downto 0),
P4WRDATA => mig_p4_wr_data(31 downto 0),
P5WRDATA => mig_p5_wr_data(31 downto 0),
P0WRERROR => mig_p0_wr_error,
P1WRERROR => mig_p1_wr_error,
P0RDERROR => mig_p0_rd_error,
P1RDERROR => mig_p1_rd_error,
P2ERROR => mig_p2_error,
P3ERROR => mig_p3_error,
P4ERROR => mig_p4_error,
P5ERROR => mig_p5_error,
-- USER SIDE DAta ports clock
-- 128 BITS CONnections
P0WRCLK => mig_p0_wr_clk ,
P1WRCLK => mig_p1_wr_clk ,
P0RDCLK => mig_p0_rd_clk ,
P1RDCLK => mig_p1_rd_clk ,
P2CLK => mig_p2_clk ,
P3CLK => mig_p3_clk ,
P4CLK => mig_p4_clk ,
P5CLK => mig_p5_clk
);
--//////////////////////////////////////////////////////
--// Input Termination Calibration
--//////////////////////////////////////////////////////
--process(ui_clk)
--begin
--if (ui_clk'event and ui_clk = '1') then
-- syn1_sys_rst <= sys_rst;
-- syn2_sys_rst <= syn1_sys_rst;
--end if;
--end process;
uo_done_cal_sig <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE
hard_done_cal;
gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE
mcb_soft_calibration_top_inst : mcb_soft_calibration_top
generic map ( C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
PORT MAP (
UI_CLK => ui_clk,
--RST => syn2_sys_rst,
RST => int_sys_rst,
IOCLK => ioclk0,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL,
--PLL_LOCK => pll_lock,
PLL_LOCK => gated_pll_lock,
--SELFREFRESH_REQ => selfrefresh_enter, -- from user app
SELFREFRESH_REQ => soft_cal_selfrefresh_req, -- from user app
SELFREFRESH_MCB_MODE => selfrefresh_mcb_mode, -- from MCB
SELFREFRESH_MCB_REQ => selfrefresh_mcb_enter, -- to mcb
SELFREFRESH_MODE => selfrefresh_mode_sig, -- to user app
MCB_UIADD => mcb_ui_add,
MCB_UISDI => mcb_ui_sdi,
MCB_UOSDO => uo_sdo_xhdl24,
MCB_UODONECAL => hard_done_cal,
MCB_UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
MCB_UICS => mcb_ui_cs,
MCB_UIDRPUPDATE => mcb_ui_drp_update,
MCB_UIBROADCAST => mcb_ui_broadcast,
MCB_UIADDR => mcb_ui_addr,
MCB_UICMDEN => mcb_ui_cmd_en,
MCB_UIDONECAL => mcb_ui_done_cal,
MCB_UIDQLOWERDEC => mcb_ui_dq_lower_dec,
MCB_UIDQLOWERINC => mcb_ui_dq_lower_inc,
MCB_UIDQUPPERDEC => mcb_ui_dq_upper_dec,
MCB_UIDQUPPERINC => mcb_ui_dq_upper_inc,
MCB_UILDQSDEC => mcb_ui_ldqs_dec,
MCB_UILDQSINC => mcb_ui_ldqs_inc,
MCB_UIREAD => mcb_ui_read,
MCB_UIUDQSDEC => mcb_ui_udqs_dec,
MCB_UIUDQSINC => mcb_ui_udqs_inc,
MCB_RECAL => mcb_recal,
MCB_SYSRST => MCB_SYSRST,
MCB_UICMD => mcb_ui_cmd,
MCB_UICMDIN => mcb_ui_cmd_in,
MCB_UIDQCOUNT => mcb_ui_dqcount,
MCB_UODATA => uo_data_int,
MCB_UODATAVALID => uo_data_valid_int,
MCB_UOCMDREADY => uo_cmd_ready_in_int,
MCB_UO_CAL_START => uo_cal_start_int,
RZQ_PIN => rzq,
ZIO_PIN => zio,
CKE_Train => cke_train
);
mcb_ui_clk <= ui_clk;
END GENERATE;
gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate
DONE_SOFTANDHARD_CAL <= '0';
MCB_SYSRST <= int_sys_rst or not(wait_200us_counter(15));
mcb_recal <= calib_recal;
mcb_ui_read <= ui_read;
mcb_ui_add <= ui_add;
mcb_ui_cs <= ui_cs;
mcb_ui_clk <= ui_clk;
mcb_ui_sdi <= ui_sdi;
mcb_ui_addr <= ui_addr;
mcb_ui_broadcast <= ui_broadcast;
mcb_ui_drp_update <= ui_drp_update;
mcb_ui_done_cal <= ui_done_cal;
mcb_ui_cmd <= ui_cmd;
mcb_ui_cmd_in <= ui_cmd_in;
mcb_ui_cmd_en <= ui_cmd_en;
mcb_ui_dqcount <= ui_dqcount;
mcb_ui_dq_lower_dec <= ui_dq_lower_dec;
mcb_ui_dq_lower_inc <= ui_dq_lower_inc;
mcb_ui_dq_upper_dec <= ui_dq_upper_dec;
mcb_ui_dq_upper_inc <= ui_dq_upper_inc;
mcb_ui_udqs_inc <= ui_udqs_inc;
mcb_ui_udqs_dec <= ui_udqs_dec;
mcb_ui_ldqs_inc <= ui_ldqs_inc;
mcb_ui_ldqs_dec <= ui_ldqs_dec;
selfrefresh_mode_sig <= '0';
-- synthesis translate_off
init_sequence: if (C_SIMULATION = "FALSE") generate
-- synthesis translate_on
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
wait_200us_counter <= (others => '0');
elsif (ui_clk'event and ui_clk = '1') then -- UI_CLK maximum is up to 100 MHz
if (wait_200us_counter(15) = '1') then
wait_200us_counter <= wait_200us_counter;
else
wait_200us_counter <= wait_200us_counter + '1';
end if;
end if;
end process;
-- synthesis translate_off
end generate;
init_sequence_skip: if (C_SIMULATION = "TRUE") generate
wait_200us_counter <= X"FFFF";
process
begin
report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
wait;
end process;
end generate;
-- synthesis translate_on
gen_cketrain_a: if (C_MEM_TYPE = "DDR2") generate
process (ui_clk)
begin
-- When wait_200us_[13] and wait_200us_[14] are both asserted,
-- 200 us wait should have been passed.
if (ui_clk'event and ui_clk = '1') then
if ((wait_200us_counter(14) and wait_200us_counter(13)) = '1') then
wait_200us_done_r1 <= '1';
else
wait_200us_done_r1 <= '0';
end if;
wait_200us_done_r2 <= wait_200us_done_r1;
end if;
end process;
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
cke_train_reg <= '0';
elsif (ui_clk'event and ui_clk = '1') then
if ((wait_200us_done_r1 and not(wait_200us_done_r2)) = '1') then
cke_train_reg <= '1';
elsif (uo_done_cal_sig = '1') then
cke_train_reg <= '0';
end if;
end if;
end process;
cke_train <= cke_train_reg;
end generate;
gen_cketrain_b: if (NOT(C_MEM_TYPE = "DDR2")) generate
cke_train <= '0';
end generate;
end generate;
--//////////////////////////////////////////////////////
--//ODDRDES2 instantiations
--//////////////////////////////////////////////////////
--------
--ADDR
--------
gen_addr_oserdes2 : FOR addr_ioi IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
ioi_addr_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_addr(addr_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_addr(addr_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => address_90(addr_ioi),
D2 => address_90(addr_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--BA
--------
gen_ba_oserdes2 : FOR ba_ioi IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
ioi_ba_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ba(ba_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ba(ba_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ba_90(ba_ioi),
D2 => ba_90(ba_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--CAS
--------
ioi_cas_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_cas,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cas,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cas_90,
D2 => cas_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CKE
--------
ioi_cke_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 15
)
PORT MAP (
OQ => ioi_cke,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cke,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cke_90,
D2 => cke_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => cke_train
);
--------
--ODT
--------
xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE
ioi_odt_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => ioi_odt,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_odt,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => odt_90,
D2 => odt_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--RAS
--------
ioi_ras_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ras,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ras,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ras_90,
D2 => ras_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--RST
--------
xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE
ioi_rst_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_rst,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_rst,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => rst_90,
D2 => rst_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--WE
--------
ioi_we_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_we,
TQ => t_we,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => we_90,
D2 => we_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CK
--------
ioi_ck_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ck,
SHIFTOUT1 => open,--ck_shiftout0_1,
SHIFTOUT2 => open,--ck_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ck,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
----------
----CKN
----------
-- ioi_ckn_0 : OSERDES2
-- GENERIC MAP (
-- BYPASS_GCLK_FF => TRUE,
-- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
-- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
-- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
-- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
-- DATA_WIDTH => 2
-- )
-- PORT MAP (
-- OQ => ioi_ckn,
-- SHIFTOUT1 => open,
-- SHIFTOUT2 => open,
-- SHIFTOUT3 => open,--ck_shiftout1_3,
-- SHIFTOUT4 => open,--ck_shiftout1_4,
-- TQ => t_ckn,
-- CLK0 => ioclk0,
-- CLK1 => '0',
-- CLKDIV => '0',
-- D1 => '1',
-- D2 => '0',
-- D3 => '0',
-- D4 => '0',
-- IOCE => pll_ce_0,
-- OCE => '1',
-- RST => '0',
-- SHIFTIN1 => '0',
-- SHIFTIN2 => '0',
-- SHIFTIN3 => '0',
-- SHIFTIN4 => '0',
-- T1 => '0',
-- T2 => '0',
-- T3 => '0',
-- T4 => '0',
-- TCE => '1',
-- TRAIN => '0'
-- );
--
--------
--UDM
--------
ioi_udm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => udm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqpum,
D2 => dqnum,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--LDM
--------
ioi_ldm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ldm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => ldm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqplm,
D2 => dqnlm,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQ
--------
gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE
oserdes2_dq_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 5
)
PORT MAP (
OQ => dq_oq(dq),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dq_tq(dq),
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqo_p(dq),
D2 => dqo_n(dq),
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => ioi_drp_train
);
END GENERATE;
--------
--DQSP
--------
oserdes2_dqsp_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsp_oq,
SHIFTOUT1 => open,--dqs_shiftout0_1,
SHIFTOUT2 => open,--dqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--dqs_shiftout1_3,
SHIFTIN4 => '0',--dqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQSN
--------
oserdes2_dqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--dqs_shiftout1_3,
SHIFTOUT4 => open,--dqs_shiftout1_4,
TQ => dqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--dqs_shiftout0_1,
SHIFTIN2 => '0',--dqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--UDQSP
--------
oserdeS2_UDQSP_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsp_oq,
SHIFTOUT1 => open,--udqs_shiftout0_1,
SHIFTOUT2 => open,--udqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--udqs_shiftout1_3,
SHIFTIN4 => '0',--udqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
t2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
tce => '1',
train => '0'
);
--------
--UDQSN
--------
oserdes2_udqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--udqs_shiftout1_3,
SHIFTOUT4 => open,--udqs_shiftout1_4,
TQ => udqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--udqs_shiftout0_1,
SHIFTIN2 => '0',--udqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
------------------------------------------------------
--*********************************** OSERDES2 instantiations end *******************************************
------------------------------------------------------
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
---#####################################--X16 MEMORY WIDTH-#############################################
dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE
--////////////////////////////////////////////////
--DQ14
--////////////////////////////////////////////////
iodrp2_DQ_14 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ14_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_14,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(14),
DQSOUTN => open,
DQSOUTP => in_dq(14),
SDO => open,
TOUT => t_dq(14),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_15,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(14),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(14),
SDI => ioi_drp_sdo,
T => dq_tq(14)
);
--////////////////////////////////////////////////
--DQ15
--////////////////////////////////////////////////
iodrp2_dq_15 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ15_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_15,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(15),
DQSOUTN => open,
DQSOUTP => in_dq(15),
SDO => open,
TOUT => t_dq(15),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(15),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(15),
SDI => ioi_drp_sdo,
T => dq_tq(15)
);
--////////////////////////////////////////////////
--DQ12
--////////////////////////////////////////////////
iodrp2_DQ_12 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ12_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_12,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(12),
DQSOUTN => open,
DQSOUTP => in_dq(12),
SDO => open,
TOUT => t_dq(12),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_13,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(12),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(12),
SDI => ioi_drp_sdo,
T => dq_tq(12)
);
--////////////////////////////////////////////////
--DQ13
--////////////////////////////////////////////////
iodrp2_dq_13 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ13_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_13,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(13),
DQSOUTN => open,
DQSOUTP => in_dq(13),
SDO => open,
TOUT => t_dq(13),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_14,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(13),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(13),
SDI => ioi_drp_sdo,
T => dq_tq(13)
);
--/////////
--UDQSP
--/////////
iodrp2_UDQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqs,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_m,
SDO => open,
TOUT => t_udqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsp_oq,
SDI => ioi_drp_sdo,
T => udqsp_tq
);
--/////////
--UDQSN
--/////////
iodrp2_udqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqsn,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_s,
SDO => open,
TOUT => t_udqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_12,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsn_oq,
SDI => ioi_drp_sdo,
T => udqsn_tq
);
--/////////////////////////////////////////////////
--//DQ10
--////////////////////////////////////////////////
iodrp2_DQ_10 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ10_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_10,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(10),
DQSOUTN => open,
DQSOUTP => in_dq(10),
SDO => open,
TOUT => t_dq(10),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_11,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(10),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(10),
SDI => ioi_drp_sdo,
T => dq_tq(10)
);
--/////////////////////////////////////////////////
--//DQ11
--////////////////////////////////////////////////
iodrp2_dq_11 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ11_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_11,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(11),
DQSOUTN => open,
DQSOUTP => in_dq(11),
SDO => open,
TOUT => t_dq(11),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(11),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(11),
SDI => ioi_drp_sdo,
T => dq_tq(11)
);
--/////////////////////////////////////////////////
--//DQ8
--////////////////////////////////////////////////
iodrp2_DQ_8 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ8_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_8,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(8),
DQSOUTN => open,
DQSOUTP => in_dq(8),
SDO => open,
TOUT => t_dq(8),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_9,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(8),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(8),
SDI => ioi_drp_sdo,
T => dq_tq(8)
);
--/////////////////////////////////////////////////
--//DQ9
--////////////////////////////////////////////////
iodrp2_dq_9 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ9_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_9,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(9),
DQSOUTN => open,
DQSOUTP => in_dq(9),
SDO => open,
TOUT => t_dq(9),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_10,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(9),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(9),
SDI => ioi_drp_sdo,
T => dq_tq(9)
);
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_8,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X8 MEMORY WIDTH-#############################################
dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--NEED TO GENERATE UDM so that user won't instantiate in this location
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X4 MEMORY WIDTH-#############################################
dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--///////////////////////////////////////////////
--DQSP
--///////////////////////////////////////////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--///////////////////////////////////////////////
--DQSN
--///////////////////////////////////////////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--///////////////////////////////////////////////
--UDM
--//////////////////////////////////////////////
--NEED TO GENERATE UDM so that user won't instantiate in this location
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--///////////////////////////////////////////////
--LDM
--//////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
-------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--IOBs instantiations
-- this part need more inputs from design team
-- for now just use as listed in fpga.v
-----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- DRAM Address
gen_addr_obuft : FOR addr_i IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
iob_addr_inst : OBUFT
PORT MAP (
I => ioi_addr(addr_i),
T => t_addr(addr_i),
O => mcbx_dram_addr(addr_i)
);
END GENERATE;
gen_ba_obuft : FOR ba_i IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
iob_ba_inst : OBUFT
PORT MAP (
I => ioi_ba(ba_i),
T => t_ba(ba_i),
O => mcbx_dram_ba(ba_i)
);
END GENERATE;
-- DRAM control
--RAS
iob_ras : OBUFT
PORT MAP (
O => mcbx_dram_ras_n,
I => ioi_ras,
T => t_ras
);
--CAS
iob_cas : OBUFT
PORT MAP (
O => mcbx_dram_cas_n,
I => ioi_cas,
T => t_cas
);
--WE
iob_we : OBUFT
PORT MAP (
O => mcbx_dram_we_n,
I => ioi_we,
T => t_we
);
--CKE
iob_cke : OBUFT
PORT MAP (
O => mcbx_dram_cke,
I => ioi_cke,
T => t_cke
);
--DDR3 RST
gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE
iob_rst : OBUFT
PORT MAP (
O => mcbx_dram_ddr3_rst,
I => ioi_rst,
T => t_rst
);
END GENERATE;
--ODT
gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF")))
OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE
iob_odt : OBUFT
PORT MAP (
O => mcbx_dram_odt,
I => ioi_odt,
t => t_odt
);
END GENERATE;
--MEMORY CLOCK
iob_clk : OBUFTDS
PORT MAP (
I => ioi_ck,
T => t_ck,
O => mcbx_dram_clk,
OB => mcbx_dram_clk_n
);
--DQ
gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE
gen_iob_dq_inst : IOBUF
PORT MAP (
IO => mcbx_dram_dq(dq_i),
I => ioi_dq(dq_i),
T => t_dq(dq_i),
O => in_pre_dq(dq_i)
);
END GENERATE;
-- x4 and x8
--DQS
gen_dqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate
iob_dqs : IOBUF
PORT MAP (
IO => mcbx_dram_dqs,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
--DQSP/DQSN
gen_dqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
iob_dqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_dqs,
IOB => mcbx_dram_dqs_n,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
-- x16
--UDQS
gen_udqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUF
PORT MAP (
IO => mcbx_dram_udqs,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
----UDQSP/UDQSN
gen_udqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_udqs,
IOB => mcbx_dram_udqs_n,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
-- DQS PULLDWON
gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate
dqs_pulldown : PULLDOWN port map (O => mcbx_dram_dqs);
end generate;
gen_dqs_pullupdn_ds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs);
dqs_n_pullup : PULLUP port map (O => mcbx_dram_dqs_n);
end generate;
-- DQSN PULLUP
gen_udqs_pullupdn : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
udqs_pulldown : PULLDOWN port map (O => mcbx_dram_udqs);
end generate;
gen_udqs_pullupdn_ds : if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate
udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs);
udqs_n_pullup : PULLUP port map (O => mcbx_dram_udqs_n);
end generate;
--UDM
gen_udm : if(C_NUM_DQ_PINS = 16) generate
iob_udm : OBUFT
PORT MAP (
I => ioi_udm,
T => t_udm,
O => mcbx_dram_udm
);
end generate;
--LDM
iob_ldm : OBUFT
PORT MAP (
I => ioi_ldm,
T => t_ldm,
O => mcbx_dram_ldm
);
selfrefresh_mode <= selfrefresh_mode_sig;
end aarch;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/example_design/rtl/mcb_raw_wrapper.vhd
|
10
|
299135
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_raw_wrapper.v
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:04 $
-- \ \ / \ Date Created: Thu June 24 2008
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose:
--Reference:
-- This module is the intialization control logic of the memory interface.
-- All commands are issued from here acoording to the burst, CAS Latency and
-- the user commands.
--
-- Revised History:
-- Rev 1.1 - added port_enable assignment for all configurations and rearrange
-- assignment siganls according to port number
-- - added timescale directive -SN 7-28-08
-- - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through
-- 15 -SN 7-28-08
-- - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
-- - removed ghighb, gpwrdnb, gsr, gwe in port declaration.
-- For now tb need to force the signals inside the MCB and Wrapper
-- until a glbl.v is ready. Not sure how to do this in NCVerilog
-- flow. -SN 7-28-08
--
-- Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
-- Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08
-- Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09
-- Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
-- delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90
-- delay_we_90 ,delay_address,delay_ba_90 =
-- --removed :assign #50 delay_dqnum = dqnum;
-- --removed :assign #50 delay_dqpum = dqpum;
-- --removed :assign #50 delay_dqnlm = dqnlm;
-- --removed :assign #50 delay_dqplm = dqplm;
-- --removed : delay_dqsIO_w_en_90_n
-- --removed : delay_dqsIO_w_en_90_p
-- --removed : delay_dqsIO_w_en_0
-- -- corrected spelling error: C_MEM_RTRAS
-- Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09
-- -- rename the memc_wrapper.v to mcb_raw_wrapper.v
-- Rev 1.7 -- -- .READEN is removed in IODRP2_MCB 1-28-09
-- -- connection has been updated
-- Rev 1.8 -- update memory parameter equations. 1-30_2009
-- -- added portion of Soft IP
-- -- CAL_CLK_DIV is not used but MCB still has it
-- Rev 1.9 -- added Error checking for Invalid command to unidirectional port
-- Rev 1.10 -- changed the backend connection so that Simulation will work while
-- sw tools try to fix the model issues. 2-3-2009
-- sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
-- It is acutally 180 degree difference.
-- Rev 1.11 -- Added MCB_Soft_Calibration_top.
-- Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009
-- Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
-- Rev 1.14 -- Added minium condition for tRTP valud/
-- REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009
-- Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009
-- Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
-- Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
-- Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009.
-- Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
-- Dynamic DQS calibration in Soft Calibration module.
-- Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
-- RTT value is set to "disabled"
-- -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
-- -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010
-- Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- Rev 1.23 -- Fixed CR 558661. In Config "B64B64" mode, mig_p5_wr_data <= p1_wr_data(63 downto 32).
-- Rev 1.24 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE"
-- Rev 1.25 -- Fixed reset problem when MCB exits from SUSPEND SELFREFRESH mode. 10-20-2010
-- Rev 1.26 -- Synchronize sys_rst before connecting to mcb_soft_calibration module to fix
-- CDC static timing issue. 2-14-2011
--*************************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_raw_wrapper is
generic(
C_MEMCLK_PERIOD : integer := 2500;
C_PORT_ENABLE : std_logic_vector(5 downto 0) := (others => '1');
C_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_PORT_CONFIG : string := "B32_B32_W32_W32_W32_W32";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_NUM_DQ_PINS : integer := 8;
C_MEM_TYPE : string := "DDR3";
C_MEM_DENSITY : string := "512M";
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 4;
C_MEM_ADDR_WIDTH : integer := 13;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR3_CAS_LATENCY : integer := 7;
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_MDDR_ODS : string := "FULL";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "OFF";
C_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIB_BYPASS : string := "NO";
C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := "000";
C_CALIB_SOFT_IP : string := "TRUE";
C_SKIP_IN_TERM_CAL : integer := 0; --provides option to skip the input termination calibration
C_SKIP_DYNAMIC_CAL : integer := 0; --provides option to skip the dynamic delay calibration
C_SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
--- ADDED for 1.0 silicon support to bypass Calibration //////
-- 07-10-09 chipl
--////////////////////////////////////////////////////////////
LDQSP_TAP_DELAY_VAL : integer := 0;
UDQSP_TAP_DELAY_VAL : integer := 0;
LDQSN_TAP_DELAY_VAL : integer := 0;
UDQSN_TAP_DELAY_VAL : integer := 0;
DQ0_TAP_DELAY_VAL : integer := 0;
DQ1_TAP_DELAY_VAL : integer := 0;
DQ2_TAP_DELAY_VAL : integer := 0;
DQ3_TAP_DELAY_VAL : integer := 0;
DQ4_TAP_DELAY_VAL : integer := 0;
DQ5_TAP_DELAY_VAL : integer := 0;
DQ6_TAP_DELAY_VAL : integer := 0;
DQ7_TAP_DELAY_VAL : integer := 0;
DQ8_TAP_DELAY_VAL : integer := 0;
DQ9_TAP_DELAY_VAL : integer := 0;
DQ10_TAP_DELAY_VAL : integer := 0;
DQ11_TAP_DELAY_VAL : integer := 0;
DQ12_TAP_DELAY_VAL : integer := 0;
DQ13_TAP_DELAY_VAL : integer := 0;
DQ14_TAP_DELAY_VAL : integer := 0;
DQ15_TAP_DELAY_VAL : integer := 0;
C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
C_MC_CALIBRATION_CLK_DIV : integer := 1;
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "HALF";
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32
);
PORT (
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0);
p2_wr_data : in std_logic_vector(31 downto 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0);
p4_cmd_bl : in std_logic_vector(5 downto 0);
p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0);
p4_wr_data : in std_logic_vector(31 downto 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 downto 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 downto 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0);
p5_cmd_bl : in std_logic_vector(5 downto 0);
p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 downto 0);
p5_wr_data : in std_logic_vector(31 downto 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 downto 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcbx_dram_dqs : INOUT std_logic;
mcbx_dram_dqs_n : INOUT std_logic;
mcbx_dram_udqs : INOUT std_logic;
mcbx_dram_udqs_n : INOUT std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : INOUT std_logic;
zio : INOUT std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 downto 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 downto 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 downto 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 downto 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end mcb_raw_wrapper;
architecture aarch of mcb_raw_wrapper is
component mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR3" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end component;
constant C_OSERDES2_DATA_RATE_OQ : STRING := "SDR";
constant C_OSERDES2_DATA_RATE_OT : STRING := "SDR";
constant C_OSERDES2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_OSERDES2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_OSERDES2_OUTPUT_MODE_SE : STRING := "SINGLE_ENDED";
constant C_OSERDES2_OUTPUT_MODE_DIFF : STRING := "DIFFERENTIAL";
constant C_BUFPLL_0_LOCK_SRC : STRING := "LOCK_TO_0";
constant C_DQ_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQ_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQ_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_DQS_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQS_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQS_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
-- MIG always set the below ADD_LATENCY to zero
constant C_MEM_DDR3_ADD_LATENCY : STRING := "OFF";
constant C_MEM_DDR2_ADD_LATENCY : INTEGER := 0;
constant C_MEM_MOBILE_TC_SR : INTEGER := 0;
-- convert the memory timing to memory clock units. I
constant MEM_RAS_VAL : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RCD_VAL : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_REFI_VAL : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD) - 25;
constant MEM_RFC_VAL : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RP_VAL : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_WR_VAL : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
function cdiv return integer is
begin
if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then
return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1;
else
return (C_MEM_TRTP/C_MEMCLK_PERIOD);
end if;
end function cdiv;
constant MEM_RTP_VAL1 : INTEGER := cdiv;
function MEM_RTP_CYC1 return integer is
begin
if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then
return 4;
else if(MEM_RTP_VAL1 < 2) then
return 2;
else
return MEM_RTP_VAL1;
end if;
end if;
end function MEM_RTP_CYC1;
constant MEM_RTP_VAL : INTEGER := MEM_RTP_CYC1;
function MEM_WTR_CYC return integer is
begin
if (C_MEM_TYPE = "DDR") then
return 2;
elsif (C_MEM_TYPE = "DDR3") then
return 4;
elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then
return C_MEM_TWTR;
elsif (C_MEM_TYPE = "DDR2" AND (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then
return ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
elsif (C_MEM_TYPE = "DDR2")then
return 2;
else
return 3;
end if;
end function MEM_WTR_CYC;
constant MEM_WTR_VAL : INTEGER := MEM_WTR_CYC;
function DDR2_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR2")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR2_WRT_RECOVERY_CYC;
constant C_MEM_DDR2_WRT_RECOVERY : INTEGER := DDR2_WRT_RECOVERY_CYC;
function DDR3_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR3")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR3_WRT_RECOVERY_CYC;
constant C_MEM_DDR3_WRT_RECOVERY : INTEGER := DDR3_WRT_RECOVERY_CYC;
--CR 596422
constant allzero : std_logic_vector(127 downto 0) := (others => '0');
--signal allzero : std_logic_vector(127 downto 0) := (others => '0');
----------------------------------------------------------------------------
-- signal Declarations
----------------------------------------------------------------------------
signal addr_in0 : std_logic_vector(31 downto 0);
signal dqs_out_p : std_logic;
signal dqs_out_n : std_logic;
signal dqs_sys_p : std_logic; --from dqs_gen to IOclk network
signal dqs_sys_n : std_logic; --from dqs_gen to IOclk network
signal udqs_sys_p: std_logic;
signal udqs_sys_n: std_logic;
signal dqs_p : std_logic; -- open net now ?
signal dqs_n : std_logic; -- open net now ?
-- IOI and IOB enable/tristate interface
signal dqIO_w_en_0 : std_logic; --enable DQ pads
signal dqsIO_w_en_90_p : std_logic; --enable p side of DQS
signal dqsIO_w_en_90_n : std_logic; --enable n side of DQS
--memory chip control interface
signal address_90 : std_logic_vector(14 downto 0);
signal ba_90 : std_logic_vector(2 downto 0);
signal ras_90 : std_logic;
signal cas_90 : std_logic;
signal we_90 : std_logic;
signal cke_90 : std_logic;
signal odt_90 : std_logic;
signal rst_90 : std_logic;
-- calibration IDELAY control signals
signal ioi_drp_clk : std_logic; --DRP interface - synchronous clock output
signal ioi_drp_addr : std_logic_vector(4 downto 0); --DRP interface - IOI selection
signal ioi_drp_sdo : std_logic; --DRP interface - serial output for commmands
signal ioi_drp_sdi : std_logic; --DRP interface - serial input for commands
signal ioi_drp_cs : std_logic; --DRP interface - chip select doubles as DONE signal
signal ioi_drp_add : std_logic; --DRP interface - serial address signal
signal ioi_drp_broadcast : std_logic;
signal ioi_drp_train : std_logic;
-- Calibration datacapture siganls
signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux
signal dq_in_p : std_logic; --positive signal sent to calibration logic
signal dq_in_n : std_logic; --negative signal sent to calibration logic
signal cal_done: std_logic;
--DQS calibration interface
signal udqs_n : std_logic;
signal udqs_p : std_logic;
signal udqs_dqocal_p : std_logic;
signal udqs_dqocal_n : std_logic;
-- MUI enable interface
signal df_en_n90 : std_logic;
--INTERNAL signal FOR DRP chain
-- IOI <-> MUI
signal ioi_int_tmp : std_logic;
signal dqo_n : std_logic_vector(15 downto 0);
signal dqo_p : std_logic_vector(15 downto 0);
signal dqnlm : std_logic;
signal dqplm : std_logic;
signal dqnum : std_logic;
signal dqpum : std_logic;
-- IOI <-> IOB routes
signal ioi_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal ioi_cas : std_logic;
signal ioi_ck : std_logic;
signal ioi_ckn : std_logic;
signal ioi_cke : std_logic;
signal ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal ioi_dqs : std_logic;
signal ioi_dqsn : std_logic;
signal ioi_udqs : std_logic;
signal ioi_udqsn : std_logic;
signal ioi_odt : std_logic;
signal ioi_ras : std_logic;
signal ioi_rst : std_logic;
signal ioi_we : std_logic;
signal ioi_udm : std_logic;
signal ioi_ldm : std_logic;
signal in_dq : std_logic_vector(15 downto 0);
signal in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal in_dqs : std_logic;
signal in_pre_dqsp : std_logic;
signal in_pre_dqsn : std_logic;
signal in_pre_udqsp : std_logic;
signal in_pre_udqsn : std_logic;
signal in_udqs : std_logic;
-- Memory tri-state control signals
signal t_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal t_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal t_cas : std_logic;
signal t_ck : std_logic;
signal t_ckn : std_logic;
signal t_cke : std_logic;
signal t_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal t_dqs : std_logic;
signal t_dqsn : std_logic;
signal t_udqs : std_logic;
signal t_udqsn : std_logic;
signal t_odt : std_logic;
signal t_ras : std_logic;
signal t_rst : std_logic;
signal t_we : std_logic;
signal t_udm : std_logic;
signal t_ldm : std_logic;
signal idelay_dqs_ioi_s : std_logic;
signal idelay_dqs_ioi_m : std_logic;
signal idelay_udqs_ioi_s : std_logic;
signal idelay_udqs_ioi_m : std_logic;
signal dqs_pin : std_logic;
signal udqs_pin : std_logic;
-- USER Interface signals
-- translated memory addresses
signal p0_cmd_ra : std_logic_vector(14 downto 0);
signal p0_cmd_ba : std_logic_vector(2 downto 0);
signal p0_cmd_ca : std_logic_vector(11 downto 0);
signal p1_cmd_ra : std_logic_vector(14 downto 0);
signal p1_cmd_ba : std_logic_vector(2 downto 0);
signal p1_cmd_ca : std_logic_vector(11 downto 0);
signal p2_cmd_ra : std_logic_vector(14 downto 0);
signal p2_cmd_ba : std_logic_vector(2 downto 0);
signal p2_cmd_ca : std_logic_vector(11 downto 0);
signal p3_cmd_ra : std_logic_vector(14 downto 0);
signal p3_cmd_ba : std_logic_vector(2 downto 0);
signal p3_cmd_ca : std_logic_vector(11 downto 0);
signal p4_cmd_ra : std_logic_vector(14 downto 0);
signal p4_cmd_ba : std_logic_vector(2 downto 0);
signal p4_cmd_ca : std_logic_vector(11 downto 0);
signal p5_cmd_ra : std_logic_vector(14 downto 0);
signal p5_cmd_ba : std_logic_vector(2 downto 0);
signal p5_cmd_ca : std_logic_vector(11 downto 0);
-- user command wires mapped from logical ports to physical ports
signal mig_p0_arb_en : std_logic;
signal mig_p0_cmd_clk : std_logic;
signal mig_p0_cmd_en : std_logic;
signal mig_p0_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p0_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p0_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p0_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p0_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p0_cmd_empty : std_logic;
signal mig_p0_cmd_full : std_logic;
signal mig_p1_arb_en : std_logic;
signal mig_p1_cmd_clk : std_logic;
signal mig_p1_cmd_en : std_logic;
signal mig_p1_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p1_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p1_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p1_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p1_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p1_cmd_empty : std_logic;
signal mig_p1_cmd_full : std_logic;
signal mig_p2_arb_en : std_logic;
signal mig_p2_cmd_clk : std_logic;
signal mig_p2_cmd_en : std_logic;
signal mig_p2_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p2_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p2_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p2_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p2_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p2_cmd_empty : std_logic;
signal mig_p2_cmd_full : std_logic;
signal mig_p3_arb_en : std_logic;
signal mig_p3_cmd_clk : std_logic;
signal mig_p3_cmd_en : std_logic;
signal mig_p3_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p3_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p3_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p3_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p3_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p3_cmd_empty : std_logic;
signal mig_p3_cmd_full : std_logic;
signal mig_p4_arb_en : std_logic;
signal mig_p4_cmd_clk : std_logic;
signal mig_p4_cmd_en : std_logic;
signal mig_p4_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p4_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p4_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p4_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p4_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p4_cmd_empty : std_logic;
signal mig_p4_cmd_full : std_logic;
signal mig_p5_arb_en : std_logic;
signal mig_p5_cmd_clk : std_logic;
signal mig_p5_cmd_en : std_logic;
signal mig_p5_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p5_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p5_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p5_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p5_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p5_cmd_empty : std_logic;
signal mig_p5_cmd_full : std_logic;
signal mig_p0_wr_clk : std_logic;
signal mig_p0_rd_clk : std_logic;
signal mig_p1_wr_clk : std_logic;
signal mig_p1_rd_clk : std_logic;
signal mig_p2_clk : std_logic;
signal mig_p3_clk : std_logic;
signal mig_p4_clk : std_logic;
signal mig_p5_clk : std_logic;
signal mig_p0_wr_en : std_logic;
signal mig_p0_rd_en : std_logic;
signal mig_p1_wr_en : std_logic;
signal mig_p1_rd_en : std_logic;
signal mig_p2_en : std_logic;
signal mig_p3_en : std_logic;
signal mig_p4_en : std_logic;
signal mig_p5_en : std_logic;
signal mig_p0_wr_data : std_logic_vector(31 downto 0);
signal mig_p1_wr_data : std_logic_vector(31 downto 0);
signal mig_p2_wr_data : std_logic_vector(31 downto 0);
signal mig_p3_wr_data : std_logic_vector(31 downto 0);
signal mig_p4_wr_data : std_logic_vector(31 downto 0);
signal mig_p5_wr_data : std_logic_vector(31 downto 0);
signal mig_p0_wr_mask : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
signal mig_p1_wr_mask : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
signal mig_p2_wr_mask : std_logic_vector(3 downto 0);
signal mig_p3_wr_mask : std_logic_vector(3 downto 0);
signal mig_p4_wr_mask : std_logic_vector(3 downto 0);
signal mig_p5_wr_mask : std_logic_vector(3 downto 0);
signal mig_p0_rd_data : std_logic_vector(31 downto 0);
signal mig_p1_rd_data : std_logic_vector(31 downto 0);
signal mig_p2_rd_data : std_logic_vector(31 downto 0);
signal mig_p3_rd_data : std_logic_vector(31 downto 0);
signal mig_p4_rd_data : std_logic_vector(31 downto 0);
signal mig_p5_rd_data : std_logic_vector(31 downto 0);
signal mig_p0_rd_overflow : std_logic;
signal mig_p1_rd_overflow : std_logic;
signal mig_p2_overflow : std_logic;
signal mig_p3_overflow : std_logic;
signal mig_p4_overflow : std_logic;
signal mig_p5_overflow : std_logic;
signal mig_p0_wr_underrun : std_logic;
signal mig_p1_wr_underrun : std_logic;
signal mig_p2_underrun : std_logic;
signal mig_p3_underrun : std_logic;
signal mig_p4_underrun : std_logic;
signal mig_p5_underrun : std_logic;
signal mig_p0_rd_error : std_logic;
signal mig_p0_wr_error : std_logic;
signal mig_p1_rd_error : std_logic;
signal mig_p1_wr_error : std_logic;
signal mig_p2_error : std_logic;
signal mig_p3_error : std_logic;
signal mig_p4_error : std_logic;
signal mig_p5_error : std_logic;
signal mig_p0_wr_count : std_logic_vector(6 downto 0);
signal mig_p1_wr_count : std_logic_vector(6 downto 0);
signal mig_p0_rd_count : std_logic_vector(6 downto 0);
signal mig_p1_rd_count : std_logic_vector(6 downto 0);
signal mig_p2_count : std_logic_vector(6 downto 0);
signal mig_p3_count : std_logic_vector(6 downto 0);
signal mig_p4_count : std_logic_vector(6 downto 0);
signal mig_p5_count : std_logic_vector(6 downto 0);
signal mig_p0_wr_full : std_logic;
signal mig_p1_wr_full : std_logic;
signal mig_p0_rd_empty : std_logic;
signal mig_p1_rd_empty : std_logic;
signal mig_p0_wr_empty : std_logic;
signal mig_p1_wr_empty : std_logic;
signal mig_p0_rd_full : std_logic;
signal mig_p1_rd_full : std_logic;
signal mig_p2_full : std_logic;
signal mig_p3_full : std_logic;
signal mig_p4_full : std_logic;
signal mig_p5_full : std_logic;
signal mig_p2_empty : std_logic;
signal mig_p3_empty : std_logic;
signal mig_p4_empty : std_logic;
signal mig_p5_empty : std_logic;
-- SELFREESH control signal for suspend feature
signal selfrefresh_mcb_enter : std_logic;
signal selfrefresh_mcb_mode : std_logic;
signal selfrefresh_mode_sig : std_logic;
signal MCB_SYSRST : std_logic;
signal ioclk0 : std_logic;
signal ioclk90 : std_logic;
signal hard_done_cal : std_logic;
signal uo_data_int : std_logic_vector(7 downto 0);
signal uo_data_valid_int : std_logic;
signal uo_cmd_ready_in_int : std_logic;
signal syn_uiclk_pll_lock : std_logic;
signal int_sys_rst : std_logic;
--testing
signal ioi_drp_update : std_logic;
signal aux_sdi_sdo : std_logic_vector(7 downto 0);
signal mcb_recal : std_logic;
signal mcb_ui_read : std_logic;
signal mcb_ui_add : std_logic;
signal mcb_ui_cs : std_logic;
signal mcb_ui_clk : std_logic;
signal mcb_ui_sdi : std_logic;
signal mcb_ui_addr : STD_LOGIC_vector(4 downto 0);
signal mcb_ui_broadcast : std_logic;
signal mcb_ui_drp_update : std_logic;
signal mcb_ui_done_cal : std_logic;
signal mcb_ui_cmd : std_logic;
signal mcb_ui_cmd_in : std_logic;
signal mcb_ui_cmd_en : std_logic;
signal mcb_ui_dqcount : std_logic_vector(3 downto 0);
signal mcb_ui_dq_lower_dec : std_logic;
signal mcb_ui_dq_lower_inc : std_logic;
signal mcb_ui_dq_upper_dec : std_logic;
signal mcb_ui_dq_upper_inc : std_logic;
signal mcb_ui_udqs_inc : std_logic;
signal mcb_ui_udqs_dec : std_logic;
signal mcb_ui_ldqs_inc : std_logic;
signal mcb_ui_ldqs_dec : std_logic;
signal DONE_SOFTANDHARD_CAL : std_logic;
signal ck_shiftout0_1 : std_logic;
signal ck_shiftout0_2 : std_logic;
signal ck_shiftout1_3 : std_logic;
signal ck_shiftout1_4 : std_logic;
signal udm_oq : std_logic;
signal udm_t : std_logic;
signal ldm_oq : std_logic;
signal ldm_t : std_logic;
signal dqsp_oq : std_logic;
signal dqsp_tq : std_logic;
signal dqs_shiftout0_1 : std_logic;
signal dqs_shiftout0_2 : std_logic;
signal dqs_shiftout1_3 : std_logic;
signal dqs_shiftout1_4 : std_logic;
signal dqsn_oq : std_logic;
signal dqsn_tq : std_logic;
signal udqsp_oq : std_logic;
signal udqsp_tq : std_logic;
signal udqs_shiftout0_1 : std_logic;
signal udqs_shiftout0_2 : std_logic;
signal udqs_shiftout1_3 : std_logic;
signal udqs_shiftout1_4 : std_logic;
signal udqsn_oq : std_logic;
signal udqsn_tq : std_logic;
signal aux_sdi_out_dqsp : std_logic;
signal aux_sdi_out_udqsp : std_logic;
signal aux_sdi_out_udqsn : std_logic;
signal aux_sdi_out_0 : std_logic;
signal aux_sdi_out_1 : std_logic;
signal aux_sdi_out_2 : std_logic;
signal aux_sdi_out_3 : std_logic;
signal aux_sdi_out_5 : std_logic;
signal aux_sdi_out_6 : std_logic;
signal aux_sdi_out_7 : std_logic;
signal aux_sdi_out_9 : std_logic;
signal aux_sdi_out_10 : std_logic;
signal aux_sdi_out_11 : std_logic;
signal aux_sdi_out_12 : std_logic;
signal aux_sdi_out_13 : std_logic;
signal aux_sdi_out_14 : std_logic;
signal aux_sdi_out_15 : std_logic;
signal aux_sdi_out_8 : std_logic;
signal aux_sdi_out_dqsn : std_logic;
signal aux_sdi_out_4 : std_logic;
signal aux_sdi_out_udm : std_logic;
signal aux_sdi_out_ldm : std_logic;
signal uo_cal_start_int : std_logic;
signal cke_train : std_logic;
signal dq_oq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal dq_tq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal p0_wr_full_i : std_logic;
signal p0_rd_empty_i : std_logic;
signal p1_wr_full_i : std_logic;
signal p1_rd_empty_i : std_logic;
signal pllclk1 : std_logic_vector(1 downto 0);
signal pllce1 : std_logic_vector(1 downto 0);
signal uo_refrsh_flag_xhdl23 : std_logic;
signal uo_sdo_xhdl24 : STD_LOGIC;
signal Max_Value_Cal_Error : std_logic;
signal uo_done_cal_sig : std_logic;
signal wait_200us_counter : std_logic_vector(15 downto 0);
signal cke_train_reg : std_logic;
signal wait_200us_done_r1 : std_logic;
signal wait_200us_done_r2 : std_logic;
signal syn1_sys_rst : std_logic;
signal syn2_sys_rst : std_logic;
signal selfrefresh_enter_r1 : std_logic;
signal selfrefresh_enter_r2 : std_logic;
signal selfrefresh_enter_r3 : std_logic;
signal gated_pll_lock : std_logic;
signal soft_cal_selfrefresh_req : std_logic;
signal normal_operation_window : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute max_fanout of int_sys_rst : signal is "1";
attribute syn_maxfan of int_sys_rst : signal is 1;
begin
uo_cmd_ready_in <= uo_cmd_ready_in_int;
uo_data_valid <= uo_data_valid_int;
uo_data <= uo_data_int;
uo_refrsh_flag <= uo_refrsh_flag_xhdl23;
uo_sdo <= uo_sdo_xhdl24;
p0_wr_full <= p0_wr_full_i;
p0_rd_empty <= p0_rd_empty_i;
p1_wr_full <= p1_wr_full_i;
p1_rd_empty <= p1_rd_empty_i;
ioclk0 <= sysclk_2x;
ioclk90 <= sysclk_2x_180;
pllclk1 <= (ioclk90 & ioclk0);
pllce1 <= (pll_ce_90 & pll_ce_0);
-- Assign the output signals with corresponding intermediate signals
uo_done_cal <= uo_done_cal_sig;
-- Added 2/22 - Add flop to pll_lock status signal to improve timing
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if ((selfrefresh_enter = '0') and (gated_pll_lock = '0')) then
syn_uiclk_pll_lock <= pll_lock;
end if;
end if;
end process;
-- logic to determine if Memory is SELFREFRESH mode operation or NORMAL mode.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
normal_operation_window <= '1';
elsif (selfrefresh_enter_r2 = '1' or selfrefresh_mode_sig = '1') then
normal_operation_window <= '0';
elsif ((selfrefresh_enter_r2 = '0') and (selfrefresh_mode_sig = '0')) then
normal_operation_window <= '1';
else
normal_operation_window <= normal_operation_window;
end if;
end if;
end process;
process(normal_operation_window,pll_lock,syn_uiclk_pll_lock)
begin
if (normal_operation_window = '1') then
gated_pll_lock <= pll_lock;
else
gated_pll_lock <= syn_uiclk_pll_lock;
end if;
end process;
-- int_sys_rst will be asserted if pll lose lock during normal operation.
-- It uses the syn_uiclk_pll_lock version when it is entering suspend window , hence
-- reset will not be generated.
int_sys_rst <= sys_rst or not(gated_pll_lock);
-- synchronize the selfrefresh_enter
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
selfrefresh_enter_r1 <= '0';
selfrefresh_enter_r2 <= '0';
selfrefresh_enter_r3 <= '0';
else
selfrefresh_enter_r1 <= selfrefresh_enter;
selfrefresh_enter_r2 <= selfrefresh_enter_r1;
selfrefresh_enter_r3 <= selfrefresh_enter_r2;
end if;
end if;
end process;
-- The soft_cal_selfrefresh siganl is conditioned before connect to mcb_soft_calibration module.
-- It will not deassert selfrefresh_mcb_enter to MCB until input pll_lock reestablished in system.
-- This is to ensure the IOI stables before issued a selfrefresh exit command to dram.
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
if (sys_rst = '1') then
soft_cal_selfrefresh_req <= '0';
elsif (selfrefresh_enter_r3 = '1') then
soft_cal_selfrefresh_req <= '1';
elsif (selfrefresh_enter_r3 = '0' and pll_lock = '1') then
soft_cal_selfrefresh_req <= '0';
else
soft_cal_selfrefresh_req <= soft_cal_selfrefresh_req;
end if;
end if;
end process;
--Address Remapping
-- Byte Address remapping
--
-- Bank Address[x:0] & Row Address[x:0] & Column Address[x:0]
-- column address remap for port 0
x16_addr : if(C_NUM_DQ_PINS = 16) generate -- port bus remapping sections for CONFIG 2 15,3,12
x16_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row Column
-- port 0 address remapping
x16_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate; --x16_addr_rbc
x16_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x16_rbc_n_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p0_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_rbc_n_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p1_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_rbc_n_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p2_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_rbc_n_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p3_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_rbc_n_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p4_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_rbc_n_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p5_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate;--x16_addr_rbc_n
end generate; --x16_addr
x8_addr : if(C_NUM_DQ_PINS = 8) generate
x8_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x8_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 2 address remapping
x8_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,2,10 ***
end generate;
x8_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc
x8_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
--port 2 address remapping
x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) &
p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc_n
end generate; --x8_addr
x4_addr : if(C_NUM_DQ_PINS = 4) generate
x4_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x4_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5
end generate; --x4_addr_rbc
x4_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5_n: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5_n
end generate; --x4_addr_rbc_n
end generate; --x4_addr
-- if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
u_config1_0: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
--synthesis translate_off
-- PORT2
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 2";
end if;
end process;
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 2";
end if;
end process;
-- PORT3
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 3";
end if;
end process;
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 3";
end if;
end process;
-- PORT4
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 4";
end if;
end process;
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 4";
end if;
end process;
-- PORT5
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 5";
end if;
end process;
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 5";
end if;
end process;
--synthesis translate_on
-- the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up
-- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
-- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
--
-- Inputs from Application CMD Port
p0_cmd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty;
p0_cmd_full <= mig_p0_cmd_full ;
end generate;
p0_cmd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
end generate;
p1_cmd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p1_cmd_empty;
p1_cmd_full <= mig_p1_cmd_full ;
end generate;
p1_cmd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
end generate;
p2_cmd_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p2_cmd_empty;
p2_cmd_full <= mig_p2_cmd_full ;
end generate;
p2_cmd_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
end generate;
p3_cmd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_arb_en <= p3_arb_en ;
mig_p3_cmd_clk <= p3_cmd_clk ;
mig_p3_cmd_en <= p3_cmd_en ;
mig_p3_cmd_ra <= p3_cmd_ra ;
mig_p3_cmd_ba <= p3_cmd_ba ;
mig_p3_cmd_ca <= p3_cmd_ca ;
mig_p3_cmd_instr <= p3_cmd_instr;
mig_p3_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
p3_cmd_empty <= mig_p3_cmd_empty;
p3_cmd_full <= mig_p3_cmd_full ;
end generate;
p3_cmd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
p3_cmd_empty <= '0';
p3_cmd_full <= '0';
end generate;
p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_arb_en <= p4_arb_en ;
mig_p4_cmd_clk <= p4_cmd_clk ;
mig_p4_cmd_en <= p4_cmd_en ;
mig_p4_cmd_ra <= p4_cmd_ra ;
mig_p4_cmd_ba <= p4_cmd_ba ;
mig_p4_cmd_ca <= p4_cmd_ca ;
mig_p4_cmd_instr <= p4_cmd_instr;
mig_p4_cmd_bl <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0)) ;
p4_cmd_empty <= mig_p4_cmd_empty;
p4_cmd_full <= mig_p4_cmd_full ;
end generate;
p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
end generate;
p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_arb_en <= p5_arb_en ;
mig_p5_cmd_clk <= p5_cmd_clk ;
mig_p5_cmd_en <= p5_cmd_en ;
mig_p5_cmd_ra <= p5_cmd_ra ;
mig_p5_cmd_ba <= p5_cmd_ba ;
mig_p5_cmd_ca <= p5_cmd_ca ;
mig_p5_cmd_instr <= p5_cmd_instr;
mig_p5_cmd_bl <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0)) ;
p5_cmd_empty <= mig_p5_cmd_empty;
p5_cmd_full <= mig_p5_cmd_full ;
end generate;
p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
end generate;
p0_wr_rd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
mig_p0_wr_data <= p0_wr_data(31 downto 0);
p0_rd_data <= mig_p0_rd_data;
p0_rd_full <= mig_p0_rd_full;
p0_rd_empty_i <= mig_p0_rd_empty;
p0_rd_error <= mig_p0_rd_error;
p0_wr_error <= mig_p0_wr_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p0_wr_full_i <= mig_p0_wr_full;
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_wr_rd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_rd_en <= '0';
mig_p0_wr_mask <= (others => '0');
mig_p0_wr_data <= (others => '0');
p0_rd_data <= (others => '0');
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
p0_rd_error <= '0';
p0_wr_error <= '0';
p0_rd_overflow <= '0';
p0_wr_underrun <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_wr_rd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_clk <= p1_rd_clk;
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_rd_en <= p1_rd_en;
p1_rd_data <= mig_p1_rd_data;
p1_rd_empty_i <= mig_p1_rd_empty;
p1_rd_full <= mig_p1_rd_full;
p1_rd_error <= mig_p1_rd_error;
p1_wr_error <= mig_p1_wr_error;
p1_rd_overflow <= mig_p1_rd_overflow;
p1_wr_underrun <= mig_p1_wr_underrun;
p1_wr_empty <= mig_p1_wr_empty;
p1_wr_full_i <= mig_p1_wr_full;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count ;
end generate;
p1_wr_rd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p1_wr_en <= '0';
mig_p1_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_rd_en <= '0';
p1_rd_data <= (others => '0');
p1_rd_empty_i <= '0';
p1_rd_full <= '0';
p1_rd_error <= '0';
p1_wr_error <= '0';
p1_rd_overflow <= '0';
p1_wr_underrun <= '0';
p1_wr_empty <= '0';
p1_wr_full_i <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
end generate;
--whenever PORT 2 is in Write mode
-- xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE
--u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate
u_config1_2W: if( C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
p2_wr_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_wr_clk;
mig_p2_wr_data <= p2_wr_data(31 downto 0);
mig_p2_wr_mask <= p2_wr_mask(3 downto 0);
mig_p2_en <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir
p2_wr_error <= mig_p2_error;
p2_wr_full <= mig_p2_full;
p2_wr_empty <= mig_p2_empty;
p2_wr_underrun <= mig_p2_underrun;
p2_wr_count <= mig_p2_count ;-- wr port
end generate;
p2_wr_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
mig_p2_en <= '0';
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
p2_rd_data <= (others => '0');
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
-- p2_rd_error <= '0';
end generate;
--u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate
u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate
p2_rd_ena : if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_rd_clk;
p2_rd_data <= mig_p2_rd_data;
mig_p2_en <= p2_rd_en;
p2_rd_overflow <= mig_p2_overflow;
p2_rd_error <= mig_p2_error;
p2_rd_full <= mig_p2_full;
p2_rd_empty <= mig_p2_empty;
p2_rd_count <= mig_p2_count ;-- wr port
end generate;
p2_rd_dis : if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
p2_rd_data <= (others => '0');
mig_p2_en <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
end generate;
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
--u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64) = "W32") generate --whenever PORT 3 is in Write mode
u_config1_3W: if(
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode
p3_wr_ena: if (C_PORT_ENABLE(3) = '1')generate
mig_p3_clk <= p3_wr_clk;
mig_p3_wr_data <= p3_wr_data(31 downto 0);
mig_p3_wr_mask <= p3_wr_mask(3 downto 0);
mig_p3_en <= p3_wr_en;
p3_wr_full <= mig_p3_full;
p3_wr_empty <= mig_p3_empty;
p3_wr_underrun <= mig_p3_underrun;
p3_wr_count <= mig_p3_count ;-- wr port
p3_wr_error <= mig_p3_error;
end generate;
p3_wr_dis: if (C_PORT_ENABLE(3) = '0')generate
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p3_en <= '0';
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
end generate;
p3_rd_overflow <= '0';
p3_rd_error <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_data <= (others => '0');
end generate;
u_config1_3R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate
p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_clk <= p3_rd_clk;
p3_rd_data <= mig_p3_rd_data;
mig_p3_en <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir
p3_rd_overflow <= mig_p3_overflow;
p3_rd_error <= mig_p3_error;
p3_rd_full <= mig_p3_full;
p3_rd_empty <= mig_p3_empty;
p3_rd_count <= mig_p3_count ;-- wr port
end generate;
p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_clk <= '0';
mig_p3_en <= '0';
p3_rd_overflow <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_error <= '0';
p3_rd_data <= (others => '0');
end generate;
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
end generate;
u_config1_4W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 4 is in Write mode
p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_wr_clk;
mig_p4_wr_data <= p4_wr_data(31 downto 0);
mig_p4_wr_mask <= p4_wr_mask(3 downto 0);
mig_p4_en <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir
p4_wr_full <= mig_p4_full;
p4_wr_empty <= mig_p4_empty;
p4_wr_underrun <= mig_p4_underrun;
p4_wr_count <= mig_p4_count ;-- wr port
p4_wr_error <= mig_p4_error;
end generate;
p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p4_en <= '0';
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
end generate;
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
p4_rd_data <= (others => '0');
end generate;
u_config1_4R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate
p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_rd_clk;
p4_rd_data <= mig_p4_rd_data;
mig_p4_en <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir
p4_rd_overflow <= mig_p4_overflow;
p4_rd_error <= mig_p4_error;
p4_rd_full <= mig_p4_full;
p4_rd_empty <= mig_p4_empty;
p4_rd_count <= mig_p4_count ;-- wr port
end generate;
p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
p4_rd_data <= (others => '0');
mig_p4_en <= '0';
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
end generate;
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
end generate;
u_config1_5W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 5 is in Write mode
p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_clk <= p5_wr_clk;
mig_p5_wr_data <= p5_wr_data(31 downto 0);
mig_p5_wr_mask <= p5_wr_mask(3 downto 0);
mig_p5_en <= p5_wr_en;
p5_wr_full <= mig_p5_full;
p5_wr_empty <= mig_p5_empty;
p5_wr_underrun <= mig_p5_underrun;
p5_wr_count <= mig_p5_count ;
p5_wr_error <= mig_p5_error;
end generate;
p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_clk <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p5_en <= '0';
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
end generate;
p5_rd_data <= (others => '0');
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
u_config1_5R :if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate
p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate
mig_p5_clk <= p5_rd_clk;
p5_rd_data <= mig_p5_rd_data;
mig_p5_en <= p5_rd_en;
p5_rd_overflow <= mig_p5_overflow;
p5_rd_error <= mig_p5_error;
p5_rd_full <= mig_p5_full;
p5_rd_empty <= mig_p5_empty;
p5_rd_count <= mig_p5_count ;
end generate;
p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate
mig_p5_clk <= '0';
p5_rd_data <= (others => '0');
mig_p5_en <= '0';
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
end generate;
--//////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
----
---- B32_B32_B32_B32
----
--///////////////////////////////////////////////////////////////////////////
--//////////////////////////////////////////////////////////////////////////
u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate
-- Inputs from Application CMD Port
-- ************* need to hook up rd /wr error outputs
p0_c2_ena: if (C_PORT_ENABLE(0) = '1') generate
-- command port signals
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_c2_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_rd_en <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate
-- command port signals
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_en <= p1_rd_en;
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_rd_clk <= p1_rd_clk;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count;
end generate;
p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
-- Data port signals
mig_p1_wr_en <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_en <= '0';
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
mig_p1_rd_clk <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate
--MCB Physical port Logical Port
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
mig_p2_en <= p2_rd_en;
mig_p2_clk <= p2_rd_clk;
mig_p3_en <= p2_wr_en;
mig_p3_clk <= p2_wr_clk;
mig_p3_wr_data <= p2_wr_data(31 downto 0);
mig_p3_wr_mask <= p2_wr_mask(3 downto 0);
p2_wr_count <= mig_p3_count;
p2_rd_count <= mig_p2_count;
end generate;
p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_en <= '0';
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_count <= (others => '0');
end generate;
p3_c2_ena: if (C_PORT_ENABLE(3) = '1') generate
--MCB Physical port Logical Port
mig_p4_arb_en <= p3_arb_en ;
mig_p4_cmd_clk <= p3_cmd_clk ;
mig_p4_cmd_en <= p3_cmd_en ;
mig_p4_cmd_ra <= p3_cmd_ra ;
mig_p4_cmd_ba <= p3_cmd_ba ;
mig_p4_cmd_ca <= p3_cmd_ca ;
mig_p4_cmd_instr <= p3_cmd_instr;
mig_p4_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
mig_p4_clk <= p3_rd_clk;
mig_p4_en <= p3_rd_en;
mig_p5_clk <= p3_wr_clk;
mig_p5_en <= p3_wr_en;
mig_p5_wr_data <= p3_wr_data(31 downto 0);
mig_p5_wr_mask <= p3_wr_mask(3 downto 0);
p3_rd_count <= mig_p4_count;
p3_wr_count <= mig_p5_count;
end generate;
p3_c2_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p4_clk <= '0';
mig_p4_en <= '0';
mig_p5_clk <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
p3_rd_count <= (others => '0');
p3_wr_count <= (others => '0');
end generate;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p1_cmd_empty <= mig_p1_cmd_empty ;
p1_cmd_full <= mig_p1_cmd_full ;
p2_cmd_empty <= mig_p2_cmd_empty ;
p2_cmd_full <= mig_p2_cmd_full ;
p3_cmd_empty <= mig_p4_cmd_empty ;
p3_cmd_full <= mig_p4_cmd_full ;
-- outputs to Applications User Port
p0_rd_data <= mig_p0_rd_data;
p1_rd_data <= mig_p1_rd_data;
p2_rd_data <= mig_p2_rd_data;
p3_rd_data <= mig_p4_rd_data;
p0_rd_empty_i <= mig_p0_rd_empty;
p1_rd_empty_i <= mig_p1_rd_empty;
p2_rd_empty <= mig_p2_empty;
p3_rd_empty <= mig_p4_empty;
p0_rd_full <= mig_p0_rd_full;
p1_rd_full <= mig_p1_rd_full;
p2_rd_full <= mig_p2_full;
p3_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error;
p1_rd_error <= mig_p1_rd_error;
p2_rd_error <= mig_p2_error;
p3_rd_error <= mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p1_rd_overflow <= mig_p1_rd_overflow;
p2_rd_overflow <= mig_p2_overflow;
p3_rd_overflow <= mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p1_wr_underrun <= mig_p1_wr_underrun;
p2_wr_underrun <= mig_p3_underrun;
p3_wr_underrun <= mig_p5_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p1_wr_empty <= mig_p1_wr_empty;
p2_wr_empty <= mig_p3_empty;
p3_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p0_wr_full;
p1_wr_full_i <= mig_p1_wr_full;
p2_wr_full <= mig_p3_full;
p3_wr_full <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error;
p1_wr_error <= mig_p1_wr_error;
p2_wr_error <= mig_p3_error;
p3_wr_error <= mig_p5_error;
-- unused ports signals
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
mig_p2_wr_mask <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p2_wr_data <= (others => '0');
mig_p4_wr_data <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--
--
-- --//////////////////////////////////////////////////////////////////////////
-- --///////////////////////////////////////////////////////////////////////////
-- ----
-- ---- B64_B32_B32
-- ----
-- --///////////////////////////////////////////////////////////////////////////
-- --//////////////////////////////////////////////////////////////////////////
--
--
--
u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate
-- Inputs from Application CMD Port
p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
p0_rd_empty_i <= mig_p1_rd_empty;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_wr_count <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output
p0_rd_count <= mig_p1_rd_count;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
end generate;
p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
p0_rd_empty_i <= '0';
p0_rd_data <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_empty <= '0';
p0_wr_error <= '0';
p0_wr_full_i <= '0';
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
end generate;
p1_c3_ena: if (C_PORT_ENABLE(1) = '1')generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p2_cmd_empty;
p1_cmd_full <= mig_p2_cmd_full;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en;
p1_rd_data <= mig_p2_rd_data;
p1_wr_count <= mig_p3_count;
p1_rd_count <= mig_p2_count;
p1_wr_empty <= mig_p3_empty;
p1_wr_error <= mig_p3_error;
p1_wr_full_i <= mig_p3_full;
p1_wr_underrun <= mig_p3_underrun;
p1_rd_overflow <= mig_p2_overflow;
p1_rd_error <= mig_p2_error;
p1_rd_full <= mig_p2_full;
p1_rd_empty_i <= mig_p2_empty;
end generate;
p1_c3_dis: if (C_PORT_ENABLE(1) = '0')generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
mig_p3_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_clk <= '0';
p1_rd_data <= (others => '0');
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_empty <= '0';
p1_wr_error <= '0';
p1_wr_full_i <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
end generate;
p2_c3_ena: if (C_PORT_ENABLE(2) = '1')generate
mig_p4_arb_en <= p2_arb_en ;
mig_p4_cmd_clk <= p2_cmd_clk ;
mig_p4_cmd_en <= p2_cmd_en ;
mig_p4_cmd_ra <= p2_cmd_ra ;
mig_p4_cmd_ba <= p2_cmd_ba ;
mig_p4_cmd_ca <= p2_cmd_ca ;
mig_p4_cmd_instr <= p2_cmd_instr;
mig_p4_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p4_cmd_empty ;
p2_cmd_full <= mig_p4_cmd_full ;
mig_p5_en <= p2_wr_en;
mig_p5_wr_data <= p2_wr_data(31 downto 0);
mig_p5_wr_mask <= p2_wr_mask(3 downto 0);
mig_p4_en <= p2_rd_en;
mig_p4_clk <= p2_rd_clk;
mig_p5_clk <= p2_wr_clk;
p2_rd_data <= mig_p4_rd_data;
p2_wr_count <= mig_p5_count;
p2_rd_count <= mig_p4_count;
p2_wr_empty <= mig_p5_empty;
p2_wr_full <= mig_p5_full;
p2_wr_error <= mig_p5_error;
p2_wr_underrun <= mig_p5_underrun;
p2_rd_overflow <= mig_p4_overflow;
p2_rd_error <= mig_p4_error;
p2_rd_full <= mig_p4_full;
p2_rd_empty <= mig_p4_empty;
end generate;
p2_c3_dis: if (C_PORT_ENABLE(2) = '0')generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p4_en <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
p2_rd_data <= (others => '0');
p2_wr_count <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_empty <= '0';
p2_wr_full <= '0';
p2_wr_error <= '0';
p2_wr_underrun <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
end generate;
-- MCB's port 1,3,5 is not used in this Config mode
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate
-- Inputs from Application CMD Port
p0_c4_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p1_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_count <= mig_p1_wr_count;
p0_rd_count <= mig_p1_rd_count;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
p0_rd_empty_i <= mig_p1_rd_empty;
end generate;
p0_c4_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
-- mig_p1_wr_en <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_rd_data <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_error <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
end generate;
p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p4_clk <= p1_rd_clk;
mig_p5_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en and not p1_wr_full_i;
mig_p5_en <= p1_wr_en and not p1_wr_full_i;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p5_wr_data <= p1_wr_data(63 downto 32);
mig_p5_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en and not p1_rd_empty_i;
mig_p4_en <= p1_rd_en and not p1_rd_empty_i;
p1_cmd_empty <= mig_p2_cmd_empty ;
p1_cmd_full <= mig_p2_cmd_full ;
p1_wr_count <= mig_p5_count;
p1_rd_count <= mig_p4_count;
p1_wr_full_i <= mig_p5_full;
p1_wr_error <= mig_p5_error or mig_p5_error;
p1_wr_empty <= mig_p5_empty;
p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun;
p1_rd_overflow <= mig_p4_overflow;
p1_rd_error <= mig_p4_error;
p1_rd_full <= mig_p4_full;
p1_rd_empty_i <= mig_p4_empty;
p1_rd_data <= (mig_p4_rd_data & mig_p2_rd_data);
end generate;
p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p2_arb_en <= '0';
-- mig_p3_arb_en <= (others => '0');
-- mig_p4_arb_en <= (others => '0');
-- mig_p5_arb_en <= (others => '0');
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_clk <= '0';
mig_p3_clk <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
mig_p3_en <= '0';
mig_p5_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p4_en <= '0';
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_full_i <= '0';
p1_wr_error <= '0';
p1_wr_empty <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
p1_rd_data <= (others => '0');
end generate;
-- unused MCB's signals in this configuration
mig_p3_arb_en <= '0';
mig_p4_arb_en <= '0';
mig_p5_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--*******************************BEGIN OF CONFIG 5 SIGNALS ********************************
u_config_5: if(C_PORT_CONFIG = "B128" ) generate
-- Inputs from Application CMD Port
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
-- Inputs from Application User Port
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p2_clk <= p0_rd_clk;
mig_p3_clk <= p0_wr_clk;
mig_p4_clk <= p0_rd_clk;
mig_p5_clk <= p0_wr_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p3_en <= p0_wr_en and not p0_wr_full_i;
mig_p5_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p3_wr_data <= p0_wr_data(95 downto 64);
mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11 downto 8);
mig_p5_wr_data <= p0_wr_data(127 downto 96);
mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15 downto 12);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p2_en <= p0_rd_en and not p0_rd_empty_i;
mig_p4_en <= p0_rd_en and not p0_rd_empty_i;
-- outputs to Applications User Port
p0_rd_data <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data);
p0_rd_empty_i <= mig_p4_empty;
p0_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun;
p0_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error;
p0_wr_count <= mig_p5_count;
p0_rd_count <= mig_p4_count;
-- unused MCB's siganls in this configuration
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
--*******************************END OF CONFIG 5 SIGNALS ********************************
end generate;
uo_cal_start <= uo_cal_start_int;
samc_0: MCB
GENERIC MAP
( PORT_CONFIG => C_PORT_CONFIG,
MEM_WIDTH => C_NUM_DQ_PINS ,
MEM_TYPE => C_MEM_TYPE ,
MEM_BURST_LEN => C_MEM_BURST_LEN ,
MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY ,
MEM_DDR2_WRT_RECOVERY => C_MEM_DDR2_WRT_RECOVERY ,
MEM_DDR3_WRT_RECOVERY => C_MEM_DDR3_WRT_RECOVERY ,
MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR ,
MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS ,
MEM_DDR3_ODS => C_MEM_DDR3_ODS ,
MEM_DDR2_RTT => C_MEM_DDR2_RTT ,
MEM_DDR3_RTT => C_MEM_DDR3_RTT ,
MEM_DDR3_ADD_LATENCY => C_MEM_DDR3_ADD_LATENCY ,
MEM_DDR2_ADD_LATENCY => C_MEM_DDR2_ADD_LATENCY ,
MEM_MOBILE_TC_SR => C_MEM_MOBILE_TC_SR ,
MEM_MDDR_ODS => C_MEM_MDDR_ODS ,
MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN ,
MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR ,
MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR ,
MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT ,
MEM_RA_SIZE => C_MEM_ADDR_WIDTH ,
MEM_BA_SIZE => C_MEM_BANKADDR_WIDTH ,
MEM_CA_SIZE => C_MEM_NUM_COL_BITS ,
MEM_RAS_VAL => MEM_RAS_VAL ,
MEM_RCD_VAL => MEM_RCD_VAL ,
MEM_REFI_VAL => MEM_REFI_VAL ,
MEM_RFC_VAL => MEM_RFC_VAL ,
MEM_RP_VAL => MEM_RP_VAL ,
MEM_WR_VAL => MEM_WR_VAL ,
MEM_RTP_VAL => MEM_RTP_VAL ,
MEM_WTR_VAL => MEM_WTR_VAL ,
CAL_BYPASS => C_MC_CALIB_BYPASS,
CAL_RA => C_MC_CALIBRATION_RA,
CAL_BA => C_MC_CALIBRATION_BA ,
CAL_CA => C_MC_CALIBRATION_CA,
CAL_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
CAL_DELAY => C_MC_CALIBRATION_DELAY,
-- CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE,
ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
ARB_TIME_SLOT_0 => C_ARB_TIME_SLOT_0,
ARB_TIME_SLOT_1 => C_ARB_TIME_SLOT_1,
ARB_TIME_SLOT_2 => C_ARB_TIME_SLOT_2,
ARB_TIME_SLOT_3 => C_ARB_TIME_SLOT_3,
ARB_TIME_SLOT_4 => C_ARB_TIME_SLOT_4,
ARB_TIME_SLOT_5 => C_ARB_TIME_SLOT_5,
ARB_TIME_SLOT_6 => C_ARB_TIME_SLOT_6,
ARB_TIME_SLOT_7 => C_ARB_TIME_SLOT_7,
ARB_TIME_SLOT_8 => C_ARB_TIME_SLOT_8,
ARB_TIME_SLOT_9 => C_ARB_TIME_SLOT_9,
ARB_TIME_SLOT_10 => C_ARB_TIME_SLOT_10,
ARB_TIME_SLOT_11 => C_ARB_TIME_SLOT_11
) PORT MAP
(
-- HIGH-SPEED PLL clock interface
PLLCLK => pllclk1,
PLLCE => pllce1,
PLLLOCK => '1',
-- DQS CLOCK NETWork interface
DQSIOIN => idelay_dqs_ioi_s,
DQSIOIP => idelay_dqs_ioi_m,
UDQSIOIN => idelay_udqs_ioi_s,
UDQSIOIP => idelay_udqs_ioi_m,
--DQSPIN => in_pre_dqsp,
DQI => in_dq,
-- RESETS - GLOBAl and local
SYSRST => MCB_SYSRST ,
-- command port 0
P0ARBEN => mig_p0_arb_en,
P0CMDCLK => mig_p0_cmd_clk,
P0CMDEN => mig_p0_cmd_en,
P0CMDRA => mig_p0_cmd_ra,
P0CMDBA => mig_p0_cmd_ba,
P0CMDCA => mig_p0_cmd_ca,
P0CMDINSTR => mig_p0_cmd_instr,
P0CMDBL => mig_p0_cmd_bl,
P0CMDEMPTY => mig_p0_cmd_empty,
P0CMDFULL => mig_p0_cmd_full,
-- command port 1
P1ARBEN => mig_p1_arb_en,
P1CMDCLK => mig_p1_cmd_clk,
P1CMDEN => mig_p1_cmd_en,
P1CMDRA => mig_p1_cmd_ra,
P1CMDBA => mig_p1_cmd_ba,
P1CMDCA => mig_p1_cmd_ca,
P1CMDINSTR => mig_p1_cmd_instr,
P1CMDBL => mig_p1_cmd_bl,
P1CMDEMPTY => mig_p1_cmd_empty,
P1CMDFULL => mig_p1_cmd_full,
-- command port 2
P2ARBEN => mig_p2_arb_en,
P2CMDCLK => mig_p2_cmd_clk,
P2CMDEN => mig_p2_cmd_en,
P2CMDRA => mig_p2_cmd_ra,
P2CMDBA => mig_p2_cmd_ba,
P2CMDCA => mig_p2_cmd_ca,
P2CMDINSTR => mig_p2_cmd_instr,
P2CMDBL => mig_p2_cmd_bl,
P2CMDEMPTY => mig_p2_cmd_empty,
P2CMDFULL => mig_p2_cmd_full,
-- command port 3
P3ARBEN => mig_p3_arb_en,
P3CMDCLK => mig_p3_cmd_clk,
P3CMDEN => mig_p3_cmd_en,
P3CMDRA => mig_p3_cmd_ra,
P3CMDBA => mig_p3_cmd_ba,
P3CMDCA => mig_p3_cmd_ca,
P3CMDINSTR => mig_p3_cmd_instr,
P3CMDBL => mig_p3_cmd_bl,
P3CMDEMPTY => mig_p3_cmd_empty,
P3CMDFULL => mig_p3_cmd_full,
-- command port 4 -- don't care in config 2
P4ARBEN => mig_p4_arb_en,
P4CMDCLK => mig_p4_cmd_clk,
P4CMDEN => mig_p4_cmd_en,
P4CMDRA => mig_p4_cmd_ra,
P4CMDBA => mig_p4_cmd_ba,
P4CMDCA => mig_p4_cmd_ca,
P4CMDINSTR => mig_p4_cmd_instr,
P4CMDBL => mig_p4_cmd_bl,
P4CMDEMPTY => mig_p4_cmd_empty,
P4CMDFULL => mig_p4_cmd_full,
-- command port 5-- don't care in config 2
P5ARBEN => mig_p5_arb_en,
P5CMDCLK => mig_p5_cmd_clk,
P5CMDEN => mig_p5_cmd_en,
P5CMDRA => mig_p5_cmd_ra,
P5CMDBA => mig_p5_cmd_ba,
P5CMDCA => mig_p5_cmd_ca,
P5CMDINSTR => mig_p5_cmd_instr,
P5CMDBL => mig_p5_cmd_bl,
P5CMDEMPTY => mig_p5_cmd_empty,
P5CMDFULL => mig_p5_cmd_full,
-- IOI & IOB SIGNals/tristate interface
DQIOWEN0 => dqIO_w_en_0,
DQSIOWEN90P => dqsIO_w_en_90_p,
DQSIOWEN90N => dqsIO_w_en_90_n,
-- IOB MEMORY INTerface signals
ADDR => address_90,
BA => ba_90 ,
RAS => ras_90 ,
CAS => cas_90 ,
WE => we_90 ,
CKE => cke_90 ,
ODT => odt_90 ,
RST => rst_90 ,
-- CALIBRATION DRP interface
IOIDRPCLK => ioi_drp_clk ,
IOIDRPADDR => ioi_drp_addr ,
IOIDRPSDO => ioi_drp_sdo ,
IOIDRPSDI => ioi_drp_sdi ,
IOIDRPCS => ioi_drp_cs ,
IOIDRPADD => ioi_drp_add ,
IOIDRPBROADCAST => ioi_drp_broadcast ,
IOIDRPTRAIN => ioi_drp_train ,
IOIDRPUPDATE => ioi_drp_update ,
-- CALIBRATION DAtacapture interface
--SPECIAL COMMANDs
RECAL => mcb_recal ,
UIREAD => mcb_ui_read,
UIADD => mcb_ui_add ,
UICS => mcb_ui_cs ,
UICLK => mcb_ui_clk ,
UISDI => mcb_ui_sdi ,
UIADDR => mcb_ui_addr ,
UIBROADCAST => mcb_ui_broadcast,
UIDRPUPDATE => mcb_ui_drp_update,
UIDONECAL => mcb_ui_done_cal,
UICMD => mcb_ui_cmd,
UICMDIN => mcb_ui_cmd_in,
UICMDEN => mcb_ui_cmd_en,
UIDQCOUNT => mcb_ui_dqcount,
UIDQLOWERDEC => mcb_ui_dq_lower_dec,
UIDQLOWERINC => mcb_ui_dq_lower_inc,
UIDQUPPERDEC => mcb_ui_dq_upper_dec,
UIDQUPPERINC => mcb_ui_dq_upper_inc,
UIUDQSDEC => mcb_ui_udqs_dec,
UIUDQSINC => mcb_ui_udqs_inc,
UILDQSDEC => mcb_ui_ldqs_dec,
UILDQSINC => mcb_ui_ldqs_inc,
UODATA => uo_data_int,
UODATAVALID => uo_data_valid_int,
UODONECAL => hard_done_cal ,
UOCMDREADYIN => uo_cmd_ready_in_int,
UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
UOCALSTART => uo_cal_start_int,
UOSDO => uo_sdo_xhdl24,
--CONTROL SIGNALS
STATUS => status,
SELFREFRESHENTER => selfrefresh_mcb_enter,
SELFREFRESHMODE => selfrefresh_mcb_mode,
------------------------------------------------
--MUIs
------------------------------------------------
P0RDDATA => mig_p0_rd_data ( 31 downto 0),
P1RDDATA => mig_p1_rd_data ( 31 downto 0),
P2RDDATA => mig_p2_rd_data ( 31 downto 0),
P3RDDATA => mig_p3_rd_data ( 31 downto 0),
P4RDDATA => mig_p4_rd_data ( 31 downto 0),
P5RDDATA => mig_p5_rd_data ( 31 downto 0),
LDMN => dqnlm ,
UDMN => dqnum ,
DQON => dqo_n ,
DQOP => dqo_p ,
LDMP => dqplm ,
UDMP => dqpum ,
P0RDCOUNT => mig_p0_rd_count ,
P0WRCOUNT => mig_p0_wr_count ,
P1RDCOUNT => mig_p1_rd_count ,
P1WRCOUNT => mig_p1_wr_count ,
P2COUNT => mig_p2_count ,
P3COUNT => mig_p3_count ,
P4COUNT => mig_p4_count ,
P5COUNT => mig_p5_count ,
-- NEW ADDED FIFo status siganls
-- MIG USER PORT 0
P0RDEMPTY => mig_p0_rd_empty,
P0RDFULL => mig_p0_rd_full,
P0RDOVERFLOW => mig_p0_rd_overflow,
P0WREMPTY => mig_p0_wr_empty,
P0WRFULL => mig_p0_wr_full,
P0WRUNDERRUN => mig_p0_wr_underrun,
-- MIG USER PORT 1
P1RDEMPTY => mig_p1_rd_empty,
P1RDFULL => mig_p1_rd_full,
P1RDOVERFLOW => mig_p1_rd_overflow,
P1WREMPTY => mig_p1_wr_empty,
P1WRFULL => mig_p1_wr_full,
P1WRUNDERRUN => mig_p1_wr_underrun,
-- MIG USER PORT 2
P2EMPTY => mig_p2_empty,
P2FULL => mig_p2_full,
P2RDOVERFLOW => mig_p2_overflow,
P2WRUNDERRUN => mig_p2_underrun,
P3EMPTY => mig_p3_empty ,
P3FULL => mig_p3_full ,
P3RDOVERFLOW => mig_p3_overflow,
P3WRUNDERRUN => mig_p3_underrun ,
-- MIG USER PORT 3
P4EMPTY => mig_p4_empty,
P4FULL => mig_p4_full,
P4RDOVERFLOW => mig_p4_overflow,
P4WRUNDERRUN => mig_p4_underrun,
P5EMPTY => mig_p5_empty ,
P5FULL => mig_p5_full ,
P5RDOVERFLOW => mig_p5_overflow,
P5WRUNDERRUN => mig_p5_underrun,
---------------------------------------------------------
P0WREN => mig_p0_wr_en,
P0RDEN => mig_p0_rd_en,
P1WREN => mig_p1_wr_en,
P1RDEN => mig_p1_rd_en,
P2EN => mig_p2_en,
P3EN => mig_p3_en,
P4EN => mig_p4_en,
P5EN => mig_p5_en,
-- WRITE MASK BIts connection
P0RWRMASK => mig_p0_wr_mask(3 downto 0),
P1RWRMASK => mig_p1_wr_mask(3 downto 0),
P2WRMASK => mig_p2_wr_mask(3 downto 0),
P3WRMASK => mig_p3_wr_mask(3 downto 0),
P4WRMASK => mig_p4_wr_mask(3 downto 0),
P5WRMASK => mig_p5_wr_mask(3 downto 0),
-- DATA WRITE COnnection
P0WRDATA => mig_p0_wr_data(31 downto 0),
P1WRDATA => mig_p1_wr_data(31 downto 0),
P2WRDATA => mig_p2_wr_data(31 downto 0),
P3WRDATA => mig_p3_wr_data(31 downto 0),
P4WRDATA => mig_p4_wr_data(31 downto 0),
P5WRDATA => mig_p5_wr_data(31 downto 0),
P0WRERROR => mig_p0_wr_error,
P1WRERROR => mig_p1_wr_error,
P0RDERROR => mig_p0_rd_error,
P1RDERROR => mig_p1_rd_error,
P2ERROR => mig_p2_error,
P3ERROR => mig_p3_error,
P4ERROR => mig_p4_error,
P5ERROR => mig_p5_error,
-- USER SIDE DAta ports clock
-- 128 BITS CONnections
P0WRCLK => mig_p0_wr_clk ,
P1WRCLK => mig_p1_wr_clk ,
P0RDCLK => mig_p0_rd_clk ,
P1RDCLK => mig_p1_rd_clk ,
P2CLK => mig_p2_clk ,
P3CLK => mig_p3_clk ,
P4CLK => mig_p4_clk ,
P5CLK => mig_p5_clk
);
--//////////////////////////////////////////////////////
--// Input Termination Calibration
--//////////////////////////////////////////////////////
--process(ui_clk)
--begin
--if (ui_clk'event and ui_clk = '1') then
-- syn1_sys_rst <= sys_rst;
-- syn2_sys_rst <= syn1_sys_rst;
--end if;
--end process;
uo_done_cal_sig <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE
hard_done_cal;
gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE
mcb_soft_calibration_top_inst : mcb_soft_calibration_top
generic map ( C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
PORT MAP (
UI_CLK => ui_clk,
--RST => syn2_sys_rst,
RST => int_sys_rst,
IOCLK => ioclk0,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL,
--PLL_LOCK => pll_lock,
PLL_LOCK => gated_pll_lock,
--SELFREFRESH_REQ => selfrefresh_enter, -- from user app
SELFREFRESH_REQ => soft_cal_selfrefresh_req, -- from user app
SELFREFRESH_MCB_MODE => selfrefresh_mcb_mode, -- from MCB
SELFREFRESH_MCB_REQ => selfrefresh_mcb_enter, -- to mcb
SELFREFRESH_MODE => selfrefresh_mode_sig, -- to user app
MCB_UIADD => mcb_ui_add,
MCB_UISDI => mcb_ui_sdi,
MCB_UOSDO => uo_sdo_xhdl24,
MCB_UODONECAL => hard_done_cal,
MCB_UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
MCB_UICS => mcb_ui_cs,
MCB_UIDRPUPDATE => mcb_ui_drp_update,
MCB_UIBROADCAST => mcb_ui_broadcast,
MCB_UIADDR => mcb_ui_addr,
MCB_UICMDEN => mcb_ui_cmd_en,
MCB_UIDONECAL => mcb_ui_done_cal,
MCB_UIDQLOWERDEC => mcb_ui_dq_lower_dec,
MCB_UIDQLOWERINC => mcb_ui_dq_lower_inc,
MCB_UIDQUPPERDEC => mcb_ui_dq_upper_dec,
MCB_UIDQUPPERINC => mcb_ui_dq_upper_inc,
MCB_UILDQSDEC => mcb_ui_ldqs_dec,
MCB_UILDQSINC => mcb_ui_ldqs_inc,
MCB_UIREAD => mcb_ui_read,
MCB_UIUDQSDEC => mcb_ui_udqs_dec,
MCB_UIUDQSINC => mcb_ui_udqs_inc,
MCB_RECAL => mcb_recal,
MCB_SYSRST => MCB_SYSRST,
MCB_UICMD => mcb_ui_cmd,
MCB_UICMDIN => mcb_ui_cmd_in,
MCB_UIDQCOUNT => mcb_ui_dqcount,
MCB_UODATA => uo_data_int,
MCB_UODATAVALID => uo_data_valid_int,
MCB_UOCMDREADY => uo_cmd_ready_in_int,
MCB_UO_CAL_START => uo_cal_start_int,
RZQ_PIN => rzq,
ZIO_PIN => zio,
CKE_Train => cke_train
);
mcb_ui_clk <= ui_clk;
END GENERATE;
gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate
DONE_SOFTANDHARD_CAL <= '0';
MCB_SYSRST <= int_sys_rst or not(wait_200us_counter(15));
mcb_recal <= calib_recal;
mcb_ui_read <= ui_read;
mcb_ui_add <= ui_add;
mcb_ui_cs <= ui_cs;
mcb_ui_clk <= ui_clk;
mcb_ui_sdi <= ui_sdi;
mcb_ui_addr <= ui_addr;
mcb_ui_broadcast <= ui_broadcast;
mcb_ui_drp_update <= ui_drp_update;
mcb_ui_done_cal <= ui_done_cal;
mcb_ui_cmd <= ui_cmd;
mcb_ui_cmd_in <= ui_cmd_in;
mcb_ui_cmd_en <= ui_cmd_en;
mcb_ui_dqcount <= ui_dqcount;
mcb_ui_dq_lower_dec <= ui_dq_lower_dec;
mcb_ui_dq_lower_inc <= ui_dq_lower_inc;
mcb_ui_dq_upper_dec <= ui_dq_upper_dec;
mcb_ui_dq_upper_inc <= ui_dq_upper_inc;
mcb_ui_udqs_inc <= ui_udqs_inc;
mcb_ui_udqs_dec <= ui_udqs_dec;
mcb_ui_ldqs_inc <= ui_ldqs_inc;
mcb_ui_ldqs_dec <= ui_ldqs_dec;
selfrefresh_mode_sig <= '0';
-- synthesis translate_off
init_sequence: if (C_SIMULATION = "FALSE") generate
-- synthesis translate_on
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
wait_200us_counter <= (others => '0');
elsif (ui_clk'event and ui_clk = '1') then -- UI_CLK maximum is up to 100 MHz
if (wait_200us_counter(15) = '1') then
wait_200us_counter <= wait_200us_counter;
else
wait_200us_counter <= wait_200us_counter + '1';
end if;
end if;
end process;
-- synthesis translate_off
end generate;
init_sequence_skip: if (C_SIMULATION = "TRUE") generate
wait_200us_counter <= X"FFFF";
process
begin
report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
wait;
end process;
end generate;
-- synthesis translate_on
gen_cketrain_a: if (C_MEM_TYPE = "DDR2") generate
process (ui_clk)
begin
-- When wait_200us_[13] and wait_200us_[14] are both asserted,
-- 200 us wait should have been passed.
if (ui_clk'event and ui_clk = '1') then
if ((wait_200us_counter(14) and wait_200us_counter(13)) = '1') then
wait_200us_done_r1 <= '1';
else
wait_200us_done_r1 <= '0';
end if;
wait_200us_done_r2 <= wait_200us_done_r1;
end if;
end process;
process (ui_clk, int_sys_rst)
begin
if (int_sys_rst = '1') then
cke_train_reg <= '0';
elsif (ui_clk'event and ui_clk = '1') then
if ((wait_200us_done_r1 and not(wait_200us_done_r2)) = '1') then
cke_train_reg <= '1';
elsif (uo_done_cal_sig = '1') then
cke_train_reg <= '0';
end if;
end if;
end process;
cke_train <= cke_train_reg;
end generate;
gen_cketrain_b: if (NOT(C_MEM_TYPE = "DDR2")) generate
cke_train <= '0';
end generate;
end generate;
--//////////////////////////////////////////////////////
--//ODDRDES2 instantiations
--//////////////////////////////////////////////////////
--------
--ADDR
--------
gen_addr_oserdes2 : FOR addr_ioi IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
ioi_addr_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_addr(addr_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_addr(addr_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => address_90(addr_ioi),
D2 => address_90(addr_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--BA
--------
gen_ba_oserdes2 : FOR ba_ioi IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
ioi_ba_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ba(ba_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ba(ba_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ba_90(ba_ioi),
D2 => ba_90(ba_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--CAS
--------
ioi_cas_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_cas,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cas,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cas_90,
D2 => cas_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CKE
--------
ioi_cke_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 15
)
PORT MAP (
OQ => ioi_cke,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cke,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cke_90,
D2 => cke_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => cke_train
);
--------
--ODT
--------
xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE
ioi_odt_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => ioi_odt,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_odt,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => odt_90,
D2 => odt_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--RAS
--------
ioi_ras_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ras,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ras,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ras_90,
D2 => ras_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--RST
--------
xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE
ioi_rst_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_rst,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_rst,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => rst_90,
D2 => rst_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--WE
--------
ioi_we_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_we,
TQ => t_we,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => we_90,
D2 => we_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CK
--------
ioi_ck_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ck,
SHIFTOUT1 => open,--ck_shiftout0_1,
SHIFTOUT2 => open,--ck_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ck,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
--OCE => '1',
OCE => pll_lock,
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
----------
----CKN
----------
-- ioi_ckn_0 : OSERDES2
-- GENERIC MAP (
-- BYPASS_GCLK_FF => TRUE,
-- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
-- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
-- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
-- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
-- DATA_WIDTH => 2
-- )
-- PORT MAP (
-- OQ => ioi_ckn,
-- SHIFTOUT1 => open,
-- SHIFTOUT2 => open,
-- SHIFTOUT3 => open,--ck_shiftout1_3,
-- SHIFTOUT4 => open,--ck_shiftout1_4,
-- TQ => t_ckn,
-- CLK0 => ioclk0,
-- CLK1 => '0',
-- CLKDIV => '0',
-- D1 => '1',
-- D2 => '0',
-- D3 => '0',
-- D4 => '0',
-- IOCE => pll_ce_0,
-- OCE => '1',
-- RST => '0',
-- SHIFTIN1 => '0',
-- SHIFTIN2 => '0',
-- SHIFTIN3 => '0',
-- SHIFTIN4 => '0',
-- T1 => '0',
-- T2 => '0',
-- T3 => '0',
-- T4 => '0',
-- TCE => '1',
-- TRAIN => '0'
-- );
--
--------
--UDM
--------
ioi_udm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => udm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqpum,
D2 => dqnum,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--LDM
--------
ioi_ldm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ldm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => ldm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqplm,
D2 => dqnlm,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQ
--------
gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE
oserdes2_dq_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 5
)
PORT MAP (
OQ => dq_oq(dq),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dq_tq(dq),
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqo_p(dq),
D2 => dqo_n(dq),
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => ioi_drp_train
);
END GENERATE;
--------
--DQSP
--------
oserdes2_dqsp_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsp_oq,
SHIFTOUT1 => open,--dqs_shiftout0_1,
SHIFTOUT2 => open,--dqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--dqs_shiftout1_3,
SHIFTIN4 => '0',--dqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQSN
--------
oserdes2_dqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--dqs_shiftout1_3,
SHIFTOUT4 => open,--dqs_shiftout1_4,
TQ => dqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--dqs_shiftout0_1,
SHIFTIN2 => '0',--dqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--UDQSP
--------
oserdeS2_UDQSP_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsp_oq,
SHIFTOUT1 => open,--udqs_shiftout0_1,
SHIFTOUT2 => open,--udqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--udqs_shiftout1_3,
SHIFTIN4 => '0',--udqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
t2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
tce => '1',
train => '0'
);
--------
--UDQSN
--------
oserdes2_udqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--udqs_shiftout1_3,
SHIFTOUT4 => open,--udqs_shiftout1_4,
TQ => udqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--udqs_shiftout0_1,
SHIFTIN2 => '0',--udqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
------------------------------------------------------
--*********************************** OSERDES2 instantiations end *******************************************
------------------------------------------------------
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
---#####################################--X16 MEMORY WIDTH-#############################################
dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE
--////////////////////////////////////////////////
--DQ14
--////////////////////////////////////////////////
iodrp2_DQ_14 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ14_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_14,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(14),
DQSOUTN => open,
DQSOUTP => in_dq(14),
SDO => open,
TOUT => t_dq(14),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_15,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(14),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(14),
SDI => ioi_drp_sdo,
T => dq_tq(14)
);
--////////////////////////////////////////////////
--DQ15
--////////////////////////////////////////////////
iodrp2_dq_15 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ15_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_15,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(15),
DQSOUTN => open,
DQSOUTP => in_dq(15),
SDO => open,
TOUT => t_dq(15),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(15),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(15),
SDI => ioi_drp_sdo,
T => dq_tq(15)
);
--////////////////////////////////////////////////
--DQ12
--////////////////////////////////////////////////
iodrp2_DQ_12 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ12_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_12,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(12),
DQSOUTN => open,
DQSOUTP => in_dq(12),
SDO => open,
TOUT => t_dq(12),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_13,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(12),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(12),
SDI => ioi_drp_sdo,
T => dq_tq(12)
);
--////////////////////////////////////////////////
--DQ13
--////////////////////////////////////////////////
iodrp2_dq_13 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ13_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_13,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(13),
DQSOUTN => open,
DQSOUTP => in_dq(13),
SDO => open,
TOUT => t_dq(13),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_14,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(13),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(13),
SDI => ioi_drp_sdo,
T => dq_tq(13)
);
--/////////
--UDQSP
--/////////
iodrp2_UDQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqs,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_m,
SDO => open,
TOUT => t_udqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsp_oq,
SDI => ioi_drp_sdo,
T => udqsp_tq
);
--/////////
--UDQSN
--/////////
iodrp2_udqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqsn,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_s,
SDO => open,
TOUT => t_udqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_12,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsn_oq,
SDI => ioi_drp_sdo,
T => udqsn_tq
);
--/////////////////////////////////////////////////
--//DQ10
--////////////////////////////////////////////////
iodrp2_DQ_10 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ10_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_10,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(10),
DQSOUTN => open,
DQSOUTP => in_dq(10),
SDO => open,
TOUT => t_dq(10),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_11,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(10),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(10),
SDI => ioi_drp_sdo,
T => dq_tq(10)
);
--/////////////////////////////////////////////////
--//DQ11
--////////////////////////////////////////////////
iodrp2_dq_11 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ11_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_11,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(11),
DQSOUTN => open,
DQSOUTP => in_dq(11),
SDO => open,
TOUT => t_dq(11),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(11),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(11),
SDI => ioi_drp_sdo,
T => dq_tq(11)
);
--/////////////////////////////////////////////////
--//DQ8
--////////////////////////////////////////////////
iodrp2_DQ_8 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ8_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_8,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(8),
DQSOUTN => open,
DQSOUTP => in_dq(8),
SDO => open,
TOUT => t_dq(8),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_9,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(8),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(8),
SDI => ioi_drp_sdo,
T => dq_tq(8)
);
--/////////////////////////////////////////////////
--//DQ9
--////////////////////////////////////////////////
iodrp2_dq_9 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ9_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_9,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(9),
DQSOUTN => open,
DQSOUTP => in_dq(9),
SDO => open,
TOUT => t_dq(9),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_10,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(9),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(9),
SDI => ioi_drp_sdo,
T => dq_tq(9)
);
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_8,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X8 MEMORY WIDTH-#############################################
dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--NEED TO GENERATE UDM so that user won't instantiate in this location
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X4 MEMORY WIDTH-#############################################
dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--///////////////////////////////////////////////
--DQSP
--///////////////////////////////////////////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--///////////////////////////////////////////////
--DQSN
--///////////////////////////////////////////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--///////////////////////////////////////////////
--UDM
--//////////////////////////////////////////////
--NEED TO GENERATE UDM so that user won't instantiate in this location
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--///////////////////////////////////////////////
--LDM
--//////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
-------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--IOBs instantiations
-- this part need more inputs from design team
-- for now just use as listed in fpga.v
-----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- DRAM Address
gen_addr_obuft : FOR addr_i IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
iob_addr_inst : OBUFT
PORT MAP (
I => ioi_addr(addr_i),
T => t_addr(addr_i),
O => mcbx_dram_addr(addr_i)
);
END GENERATE;
gen_ba_obuft : FOR ba_i IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
iob_ba_inst : OBUFT
PORT MAP (
I => ioi_ba(ba_i),
T => t_ba(ba_i),
O => mcbx_dram_ba(ba_i)
);
END GENERATE;
-- DRAM control
--RAS
iob_ras : OBUFT
PORT MAP (
O => mcbx_dram_ras_n,
I => ioi_ras,
T => t_ras
);
--CAS
iob_cas : OBUFT
PORT MAP (
O => mcbx_dram_cas_n,
I => ioi_cas,
T => t_cas
);
--WE
iob_we : OBUFT
PORT MAP (
O => mcbx_dram_we_n,
I => ioi_we,
T => t_we
);
--CKE
iob_cke : OBUFT
PORT MAP (
O => mcbx_dram_cke,
I => ioi_cke,
T => t_cke
);
--DDR3 RST
gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE
iob_rst : OBUFT
PORT MAP (
O => mcbx_dram_ddr3_rst,
I => ioi_rst,
T => t_rst
);
END GENERATE;
--ODT
gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF")))
OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE
iob_odt : OBUFT
PORT MAP (
O => mcbx_dram_odt,
I => ioi_odt,
t => t_odt
);
END GENERATE;
--MEMORY CLOCK
iob_clk : OBUFTDS
PORT MAP (
I => ioi_ck,
T => t_ck,
O => mcbx_dram_clk,
OB => mcbx_dram_clk_n
);
--DQ
gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE
gen_iob_dq_inst : IOBUF
PORT MAP (
IO => mcbx_dram_dq(dq_i),
I => ioi_dq(dq_i),
T => t_dq(dq_i),
O => in_pre_dq(dq_i)
);
END GENERATE;
-- x4 and x8
--DQS
gen_dqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate
iob_dqs : IOBUF
PORT MAP (
IO => mcbx_dram_dqs,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
--DQSP/DQSN
gen_dqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
iob_dqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_dqs,
IOB => mcbx_dram_dqs_n,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
-- x16
--UDQS
gen_udqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUF
PORT MAP (
IO => mcbx_dram_udqs,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
----UDQSP/UDQSN
gen_udqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_udqs,
IOB => mcbx_dram_udqs_n,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
-- DQS PULLDWON
gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate
dqs_pulldown : PULLDOWN port map (O => mcbx_dram_dqs);
end generate;
gen_dqs_pullupdn_ds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs);
dqs_n_pullup : PULLUP port map (O => mcbx_dram_dqs_n);
end generate;
-- DQSN PULLUP
gen_udqs_pullupdn : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
udqs_pulldown : PULLDOWN port map (O => mcbx_dram_udqs);
end generate;
gen_udqs_pullupdn_ds : if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate
udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs);
udqs_n_pullup : PULLUP port map (O => mcbx_dram_udqs_n);
end generate;
--UDM
gen_udm : if(C_NUM_DQ_PINS = 16) generate
iob_udm : OBUFT
PORT MAP (
I => ioi_udm,
T => t_udm,
O => mcbx_dram_udm
);
end generate;
--LDM
iob_ldm : OBUFT
PORT MAP (
I => ioi_ldm,
T => t_ldm,
O => mcbx_dram_ldm
);
selfrefresh_mode <= selfrefresh_mode_sig;
end aarch;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/user_design/rtl/memc1_infrastructure.vhd
|
2
|
12267
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc1_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc1_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc1_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/example_design/rtl/memc3_tb_top.vhd
|
2
|
21803
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error;
error <= p0_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/example_design/rtl/memc3_infrastructure.vhd
|
6
|
12267
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/example_design/xilinx_pcie_1_1_ep_s6.vhd
|
1
|
31136
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : xilinx_pcie_1_1_ep_s6.vhd
-- Description: PCI Express Endpoint example FPGA design
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
library unisim;
use unisim.VCOMPONENTS.all;
entity xilinx_pcie_1_1_ep_s6 is
generic
(
FAST_TRAIN : boolean := FALSE
);
port
(
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
led_0 : out std_logic;
led_1 : out std_logic;
led_2 : out std_logic
);
end xilinx_pcie_1_1_ep_s6;
architecture rtl of xilinx_pcie_1_1_ep_s6 is
-------------------------
-- Component declarations
-------------------------
component pcie_app_s6 is
port (
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_tbuf_av : in std_logic_vector(5 downto 0);
trn_tcfg_req_n : in std_logic;
trn_terr_drop_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_terrfwd_n : out std_logic;
trn_tcfg_gnt_n : out std_logic;
trn_tstr_n : out std_logic;
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rerrfwd_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
trn_rnp_ok_n : out std_logic;
trn_fc_cpld : in std_logic_vector(11 downto 0);
trn_fc_cplh : in std_logic_vector(7 downto 0);
trn_fc_npd : in std_logic_vector(11 downto 0);
trn_fc_nph : in std_logic_vector(7 downto 0);
trn_fc_pd : in std_logic_vector(11 downto 0);
trn_fc_ph : in std_logic_vector(7 downto 0);
trn_fc_sel : out std_logic_vector(2 downto 0);
cfg_do : in std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : in std_logic;
cfg_dwaddr : out std_logic_vector(9 downto 0);
cfg_rd_en_n : out std_logic;
cfg_err_cor_n : out std_logic;
cfg_err_ur_n : out std_logic;
cfg_err_ecrc_n : out std_logic;
cfg_err_cpl_timeout_n : out std_logic;
cfg_err_cpl_abort_n : out std_logic;
cfg_err_posted_n : out std_logic;
cfg_err_locked_n : out std_logic;
cfg_err_tlp_cpl_header : out std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : in std_logic;
cfg_interrupt_n : out std_logic;
cfg_interrupt_rdy_n : in std_logic;
cfg_interrupt_assert_n : out std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_turnoff_ok_n : out std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_trn_pending_n : out std_logic;
cfg_pm_wake_n : out std_logic;
cfg_bus_number : in std_logic_vector(7 downto 0);
cfg_device_number : in std_logic_vector(4 downto 0);
cfg_function_number : in std_logic_vector(2 downto 0);
cfg_status : in std_logic_vector(15 downto 0);
cfg_command : in std_logic_vector(15 downto 0);
cfg_dstatus : in std_logic_vector(15 downto 0);
cfg_dcommand : in std_logic_vector(15 downto 0);
cfg_lstatus : in std_logic_vector(15 downto 0);
cfg_lcommand : in std_logic_vector(15 downto 0);
cfg_pcie_link_state_n : in std_logic_vector(2 downto 0);
cfg_dsn : out std_logic_vector(63 downto 0)
);
end component pcie_app_s6;
component pcie_core is
generic (
TL_TX_RAM_RADDR_LATENCY : integer := 0;
TL_TX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_RADDR_LATENCY : integer := 0;
TL_RX_RAM_RDATA_LATENCY : integer := 2;
TL_RX_RAM_WRITE_LATENCY : integer := 0;
VC0_TX_LASTPACKET : integer := 14;
VC0_RX_RAM_LIMIT : bit_vector := x"7FF";
VC0_TOTAL_CREDITS_PH : integer := 32;
VC0_TOTAL_CREDITS_PD : integer := 211;
VC0_TOTAL_CREDITS_NPH : integer := 8;
VC0_TOTAL_CREDITS_CH : integer := 40;
VC0_TOTAL_CREDITS_CD : integer := 211;
VC0_CPL_INFINITE : boolean := TRUE;
BAR0 : bit_vector := x"FFFFFC00";
BAR1 : bit_vector := x"FFFFC000";
BAR2 : bit_vector := x"FF000000";
BAR3 : bit_vector := x"00000000";
BAR4 : bit_vector := x"00000000";
BAR5 : bit_vector := x"00000000";
EXPANSION_ROM : bit_vector := "0000000000000000000000";
DISABLE_BAR_FILTERING : boolean := FALSE;
DISABLE_ID_CHECK : boolean := FALSE;
TL_TFC_DISABLE : boolean := FALSE;
TL_TX_CHECKS_DISABLE : boolean := FALSE;
USR_CFG : boolean := FALSE;
USR_EXT_CFG : boolean := FALSE;
DEV_CAP_MAX_PAYLOAD_SUPPORTED : integer := 2;
CLASS_CODE : bit_vector := x"050000";
CARDBUS_CIS_POINTER : bit_vector := x"00000000";
PCIE_CAP_CAPABILITY_VERSION : bit_vector := x"1";
PCIE_CAP_DEVICE_PORT_TYPE : bit_vector := x"0";
PCIE_CAP_SLOT_IMPLEMENTED : boolean := FALSE;
PCIE_CAP_INT_MSG_NUM : bit_vector := "00000";
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer := 0;
DEV_CAP_EXT_TAG_SUPPORTED : boolean := FALSE;
DEV_CAP_ENDPOINT_L0S_LATENCY : integer := 7;
DEV_CAP_ENDPOINT_L1_LATENCY : integer := 7;
SLOT_CAP_ATT_BUTTON_PRESENT : boolean := FALSE;
SLOT_CAP_ATT_INDICATOR_PRESENT : boolean := FALSE;
SLOT_CAP_POWER_INDICATOR_PRESENT : boolean := FALSE;
DEV_CAP_ROLE_BASED_ERROR : boolean := TRUE;
LINK_CAP_ASPM_SUPPORT : integer := 1;
LINK_CAP_L0S_EXIT_LATENCY : integer := 7;
LINK_CAP_L1_EXIT_LATENCY : integer := 7;
LL_ACK_TIMEOUT : bit_vector := x"00B7";
LL_ACK_TIMEOUT_EN : boolean := FALSE;
LL_REPLAY_TIMEOUT : bit_vector := x"0204";
LL_REPLAY_TIMEOUT_EN : boolean := FALSE;
MSI_CAP_MULTIMSGCAP : integer := 0;
MSI_CAP_MULTIMSG_EXTENSION : integer := 0;
LINK_STATUS_SLOT_CLOCK_CONFIG : boolean := FALSE;
PLM_AUTO_CONFIG : boolean := FALSE;
FAST_TRAIN : boolean := FALSE;
ENABLE_RX_TD_ECRC_TRIM : boolean := FALSE;
DISABLE_SCRAMBLING : boolean := FALSE;
PM_CAP_VERSION : integer := 3;
PM_CAP_PME_CLOCK : boolean := FALSE;
PM_CAP_DSI : boolean := FALSE;
PM_CAP_AUXCURRENT : integer := 0;
PM_CAP_D1SUPPORT : boolean := TRUE;
PM_CAP_D2SUPPORT : boolean := TRUE;
PM_CAP_PMESUPPORT : bit_vector := x"0F";
PM_DATA0 : bit_vector := x"00";
PM_DATA_SCALE0 : bit_vector := x"0";
PM_DATA1 : bit_vector := x"00";
PM_DATA_SCALE1 : bit_vector := x"0";
PM_DATA2 : bit_vector := x"00";
PM_DATA_SCALE2 : bit_vector := x"0";
PM_DATA3 : bit_vector := x"00";
PM_DATA_SCALE3 : bit_vector := x"0";
PM_DATA4 : bit_vector := x"00";
PM_DATA_SCALE4 : bit_vector := x"0";
PM_DATA5 : bit_vector := x"00";
PM_DATA_SCALE5 : bit_vector := x"0";
PM_DATA6 : bit_vector := x"00";
PM_DATA_SCALE6 : bit_vector := x"0";
PM_DATA7 : bit_vector := x"00";
PM_DATA_SCALE7 : bit_vector := x"0";
PCIE_GENERIC : bit_vector := "000011101111";
GTP_SEL : integer := 0;
CFG_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_DEV_ID : std_logic_vector(15 downto 0) := x"0007";
CFG_REV_ID : std_logic_vector(7 downto 0) := x"00";
CFG_SUBSYS_VEN_ID : std_logic_vector(15 downto 0) := x"10EE";
CFG_SUBSYS_ID : std_logic_vector(15 downto 0) := x"0007";
REF_CLK_FREQ : integer := 1
);
port (
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic;
pci_exp_txn : out std_logic;
pci_exp_rxp : in std_logic;
pci_exp_rxn : in std_logic;
-- Transaction (TRN) Interface
trn_lnk_up_n : out std_logic;
-- Tx
trn_td : in std_logic_vector(31 downto 0);
trn_tsof_n : in std_logic;
trn_teof_n : in std_logic;
trn_tsrc_rdy_n : in std_logic;
trn_tdst_rdy_n : out std_logic;
trn_terr_drop_n : out std_logic;
trn_tsrc_dsc_n : in std_logic;
trn_terrfwd_n : in std_logic;
trn_tbuf_av : out std_logic_vector(5 downto 0);
trn_tstr_n : in std_logic;
trn_tcfg_req_n : out std_logic;
trn_tcfg_gnt_n : in std_logic;
-- Rx
trn_rd : out std_logic_vector(31 downto 0);
trn_rsof_n : out std_logic;
trn_reof_n : out std_logic;
trn_rsrc_rdy_n : out std_logic;
trn_rsrc_dsc_n : out std_logic;
trn_rdst_rdy_n : in std_logic;
trn_rerrfwd_n : out std_logic;
trn_rnp_ok_n : in std_logic;
trn_rbar_hit_n : out std_logic_vector(6 downto 0);
trn_fc_sel : in std_logic_vector(2 downto 0);
trn_fc_nph : out std_logic_vector(7 downto 0);
trn_fc_npd : out std_logic_vector(11 downto 0);
trn_fc_ph : out std_logic_vector(7 downto 0);
trn_fc_pd : out std_logic_vector(11 downto 0);
trn_fc_cplh : out std_logic_vector(7 downto 0);
trn_fc_cpld : out std_logic_vector(11 downto 0);
-- Host (CFG) Interface
cfg_do : out std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : out std_logic;
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_rd_en_n : in std_logic;
cfg_err_ur_n : in std_logic;
cfg_err_cor_n : in std_logic;
cfg_err_ecrc_n : in std_logic;
cfg_err_cpl_timeout_n : in std_logic;
cfg_err_cpl_abort_n : in std_logic;
cfg_err_posted_n : in std_logic;
cfg_err_locked_n : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : out std_logic;
cfg_interrupt_n : in std_logic;
cfg_interrupt_rdy_n : out std_logic;
cfg_interrupt_assert_n : in std_logic;
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_turnoff_ok_n : in std_logic;
cfg_to_turnoff_n : out std_logic;
cfg_pm_wake_n : in std_logic;
cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
cfg_trn_pending_n : in std_logic;
cfg_dsn : in std_logic_vector(63 downto 0);
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
-- System Interface
sys_clk : in std_logic;
sys_reset_n : in std_logic;
trn_clk : out std_logic;
trn_reset_n : out std_logic;
received_hot_reset : out std_logic
);
end component pcie_core;
----------------------
-- Signal declarations
----------------------
-- Common
signal trn_clk : std_logic;
signal trn_reset_n : std_logic;
signal trn_lnk_up_n : std_logic;
-- Tx
signal trn_tbuf_av : std_logic_vector(5 downto 0);
signal trn_tcfg_req_n : std_logic;
signal trn_terr_drop_n : std_logic;
signal trn_tdst_rdy_n : std_logic;
signal trn_td : std_logic_vector(31 downto 0);
signal trn_tsof_n : std_logic;
signal trn_teof_n : std_logic;
signal trn_tsrc_rdy_n : std_logic;
signal trn_tsrc_dsc_n : std_logic;
signal trn_terrfwd_n : std_logic;
signal trn_tcfg_gnt_n : std_logic;
signal trn_tstr_n : std_logic;
-- Rx
signal trn_rd : std_logic_vector(31 downto 0);
signal trn_rsof_n : std_logic;
signal trn_reof_n : std_logic;
signal trn_rsrc_rdy_n : std_logic;
signal trn_rsrc_dsc_n : std_logic;
signal trn_rerrfwd_n : std_logic;
signal trn_rbar_hit_n : std_logic_vector(6 downto 0);
signal trn_rdst_rdy_n : std_logic;
signal trn_rnp_ok_n : std_logic;
-- Flow Control
signal trn_fc_cpld : std_logic_vector(11 downto 0);
signal trn_fc_cplh : std_logic_vector(7 downto 0);
signal trn_fc_npd : std_logic_vector(11 downto 0);
signal trn_fc_nph : std_logic_vector(7 downto 0);
signal trn_fc_pd : std_logic_vector(11 downto 0);
signal trn_fc_ph : std_logic_vector(7 downto 0);
signal trn_fc_sel : std_logic_vector(2 downto 0);
-- Config
signal cfg_dsn : std_logic_vector(63 downto 0);
signal cfg_do : std_logic_vector(31 downto 0);
signal cfg_rd_wr_done_n : std_logic;
signal cfg_dwaddr : std_logic_vector(9 downto 0);
signal cfg_rd_en_n : std_logic;
-- Error signaling
signal cfg_err_cor_n : std_logic;
signal cfg_err_ur_n : std_logic;
signal cfg_err_ecrc_n : std_logic;
signal cfg_err_cpl_timeout_n : std_logic;
signal cfg_err_cpl_abort_n : std_logic;
signal cfg_err_posted_n : std_logic;
signal cfg_err_locked_n : std_logic;
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
signal cfg_err_cpl_rdy_n : std_logic;
-- Interrupt signaling
signal cfg_interrupt_n : std_logic;
signal cfg_interrupt_rdy_n : std_logic;
signal cfg_interrupt_assert_n : std_logic;
signal cfg_interrupt_di : std_logic_vector(7 downto 0);
signal cfg_interrupt_do : std_logic_vector(7 downto 0);
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable : std_logic;
-- Power management signaling
signal cfg_turnoff_ok_n : std_logic;
signal cfg_to_turnoff_n : std_logic;
signal cfg_trn_pending_n : std_logic;
signal cfg_pm_wake_n : std_logic;
-- System configuration and status
signal cfg_bus_number : std_logic_vector(7 downto 0);
signal cfg_device_number : std_logic_vector(4 downto 0);
signal cfg_function_number : std_logic_vector(2 downto 0);
signal cfg_status : std_logic_vector(15 downto 0);
signal cfg_command : std_logic_vector(15 downto 0);
signal cfg_dstatus : std_logic_vector(15 downto 0);
signal cfg_dcommand : std_logic_vector(15 downto 0);
signal cfg_lstatus : std_logic_vector(15 downto 0);
signal cfg_lcommand : std_logic_vector(15 downto 0);
signal cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
-- System (SYS) Interface
signal sys_clk_c : std_logic;
signal sys_reset_n_c : std_logic;
begin
---------------------------------------------------------
-- Clock Input Buffer for differential system clock
---------------------------------------------------------
refclk_ibuf : IBUFDS
port map
(
O => sys_clk_c,
I => sys_clk_p,
IB => sys_clk_n
);
---------------------------------------------------------
-- Input buffer for system reset signal
---------------------------------------------------------
sys_reset_n_ibuf : IBUF
port map
(
O => sys_reset_n_c,
I => sys_reset_n
);
---------------------------------------------------------
-- Output buffers for diagnostic LEDs
---------------------------------------------------------
led_0_obuf : OBUF
port map
(
O => led_0,
I => sys_reset_n_c
);
led_1_obuf : OBUF
port map
(
O => led_1,
I => trn_reset_n
);
led_2_obuf : OBUF
port map
(
O => led_2,
I => trn_lnk_up_n
);
---------------------------------------------------------
-- User application
---------------------------------------------------------
app : pcie_app_s6
port map
(
-- Transaction (TRN) Interface
-- Common lock & reset
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
trn_lnk_up_n => trn_lnk_up_n,
-- Common flow control
trn_fc_cpld => trn_fc_cpld,
trn_fc_cplh => trn_fc_cplh,
trn_fc_npd => trn_fc_npd,
trn_fc_nph => trn_fc_nph,
trn_fc_pd => trn_fc_pd,
trn_fc_ph => trn_fc_ph,
trn_fc_sel => trn_fc_sel,
-- Transaction Tx
trn_tbuf_av => trn_tbuf_av,
trn_tcfg_req_n => trn_tcfg_req_n,
trn_terr_drop_n => trn_terr_drop_n,
trn_tdst_rdy_n => trn_tdst_rdy_n,
trn_td => trn_td,
trn_tsof_n => trn_tsof_n,
trn_teof_n => trn_teof_n,
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
trn_terrfwd_n => trn_terrfwd_n,
trn_tcfg_gnt_n => trn_tcfg_gnt_n,
trn_tstr_n => trn_tstr_n,
-- Transaction Rx
trn_rd => trn_rd,
trn_rsof_n => trn_rsof_n,
trn_reof_n => trn_reof_n,
trn_rsrc_rdy_n => trn_rsrc_rdy_n,
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
trn_rerrfwd_n => trn_rerrfwd_n,
trn_rbar_hit_n => trn_rbar_hit_n,
trn_rdst_rdy_n => trn_rdst_rdy_n,
trn_rnp_ok_n => trn_rnp_ok_n,
-- Configuration (CFG) Interface
-- Configuration space access
cfg_do => cfg_do,
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
cfg_dwaddr => cfg_dwaddr,
cfg_rd_en_n => cfg_rd_en_n,
-- Error signaling
cfg_err_cor_n => cfg_err_cor_n,
cfg_err_ur_n => cfg_err_ur_n,
cfg_err_ecrc_n => cfg_err_ecrc_n,
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
cfg_err_posted_n => cfg_err_posted_n,
cfg_err_locked_n => cfg_err_locked_n,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
-- Interrupt generation
cfg_interrupt_n => cfg_interrupt_n,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
cfg_interrupt_assert_n => cfg_interrupt_assert_n,
cfg_interrupt_di => cfg_interrupt_di,
cfg_interrupt_do => cfg_interrupt_do,
cfg_interrupt_mmenable => cfg_interrupt_mmenable,
cfg_interrupt_msienable => cfg_interrupt_msienable,
-- Power managemnt signaling
cfg_turnoff_ok_n => cfg_turnoff_ok_n,
cfg_to_turnoff_n => cfg_to_turnoff_n,
cfg_trn_pending_n => cfg_trn_pending_n,
cfg_pm_wake_n => cfg_pm_wake_n,
-- System configuration and status
cfg_bus_number => cfg_bus_number,
cfg_device_number => cfg_device_number,
cfg_function_number => cfg_function_number,
cfg_status => cfg_status,
cfg_command => cfg_command,
cfg_dstatus => cfg_dstatus,
cfg_dcommand => cfg_dcommand,
cfg_lstatus => cfg_lstatus,
cfg_lcommand => cfg_lcommand,
cfg_pcie_link_state_n => cfg_pcie_link_state_n,
cfg_dsn => cfg_dsn
);
pcie_core_i : pcie_core generic map
(
FAST_TRAIN => FAST_TRAIN
)
port map (
-- PCI Express (PCI_EXP) Fabric Interface
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
-- Transaction (TRN) Interface
-- Common clock & reset
trn_lnk_up_n => trn_lnk_up_n,
trn_clk => trn_clk,
trn_reset_n => trn_reset_n,
-- Common flow control
trn_fc_sel => trn_fc_sel,
trn_fc_nph => trn_fc_nph,
trn_fc_npd => trn_fc_npd,
trn_fc_ph => trn_fc_ph,
trn_fc_pd => trn_fc_pd,
trn_fc_cplh => trn_fc_cplh,
trn_fc_cpld => trn_fc_cpld,
-- Transaction Tx
trn_td => trn_td,
trn_tsof_n => trn_tsof_n,
trn_teof_n => trn_teof_n,
trn_tsrc_rdy_n => trn_tsrc_rdy_n,
trn_tdst_rdy_n => trn_tdst_rdy_n,
trn_terr_drop_n => trn_terr_drop_n,
trn_tsrc_dsc_n => trn_tsrc_dsc_n,
trn_terrfwd_n => trn_terrfwd_n,
trn_tbuf_av => trn_tbuf_av,
trn_tstr_n => trn_tstr_n,
trn_tcfg_req_n => trn_tcfg_req_n,
trn_tcfg_gnt_n => trn_tcfg_gnt_n,
-- Transaction Rx
trn_rd => trn_rd,
trn_rsof_n => trn_rsof_n,
trn_reof_n => trn_reof_n,
trn_rsrc_rdy_n => trn_rsrc_rdy_n,
trn_rsrc_dsc_n => trn_rsrc_dsc_n,
trn_rdst_rdy_n => trn_rdst_rdy_n,
trn_rerrfwd_n => trn_rerrfwd_n,
trn_rnp_ok_n => trn_rnp_ok_n,
trn_rbar_hit_n => trn_rbar_hit_n,
-- Configuration (CFG) Interface
-- Configuration space access
cfg_do => cfg_do,
cfg_rd_wr_done_n => cfg_rd_wr_done_n,
cfg_dwaddr => cfg_dwaddr,
cfg_rd_en_n => cfg_rd_en_n,
-- Error reporting
cfg_err_ur_n => cfg_err_ur_n,
cfg_err_cor_n => cfg_err_cor_n,
cfg_err_ecrc_n => cfg_err_ecrc_n,
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
cfg_err_posted_n => cfg_err_posted_n,
cfg_err_locked_n => cfg_err_locked_n,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
-- Interrupt generation
cfg_interrupt_n => cfg_interrupt_n,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
cfg_interrupt_assert_n => cfg_interrupt_assert_n,
cfg_interrupt_do => cfg_interrupt_do,
cfg_interrupt_di => cfg_interrupt_di,
cfg_interrupt_mmenable => cfg_interrupt_mmenable,
cfg_interrupt_msienable => cfg_interrupt_msienable,
-- Power management signaling
cfg_turnoff_ok_n => cfg_turnoff_ok_n,
cfg_to_turnoff_n => cfg_to_turnoff_n,
cfg_pm_wake_n => cfg_pm_wake_n,
cfg_pcie_link_state_n => cfg_pcie_link_state_n,
cfg_trn_pending_n => cfg_trn_pending_n,
-- System configuration and status
cfg_dsn => cfg_dsn,
cfg_bus_number => cfg_bus_number,
cfg_device_number => cfg_device_number,
cfg_function_number => cfg_function_number,
cfg_status => cfg_status,
cfg_command => cfg_command,
cfg_dstatus => cfg_dstatus,
cfg_dcommand => cfg_dcommand,
cfg_lstatus => cfg_lstatus,
cfg_lcommand => cfg_lcommand,
-- System (SYS) Interface
sys_clk => sys_clk_c,
sys_reset_n => sys_reset_n_c,
received_hot_reset => OPEN
);
end rtl;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/pcie_core/simulation/dsport/pcie_pipe_lane_v6.vhd
|
1
|
15451
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_pipe_lane_v6.vhd
-- Description: PIPE per lane module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_pipe_lane_v6 is
generic (
PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
);
port (
pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_rx_data_o : out std_logic_vector(15 downto 0);
pipe_rx_valid_o : out std_logic;
pipe_rx_chanisaligned_o : out std_logic;
pipe_rx_status_o : out std_logic_vector(2 downto 0);
pipe_rx_phy_status_o : out std_logic;
pipe_rx_elec_idle_o : out std_logic;
pipe_rx_polarity_i : in std_logic;
pipe_tx_compliance_i : in std_logic;
pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_tx_data_i : in std_logic_vector(15 downto 0);
pipe_tx_elec_idle_i : in std_logic;
pipe_tx_powerdown_i : in std_logic_vector(1 downto 0);
pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0);
pipe_rx_data_i : in std_logic_vector(15 downto 0);
pipe_rx_valid_i : in std_logic;
pipe_rx_chanisaligned_i : in std_logic;
pipe_rx_status_i : in std_logic_vector(2 downto 0);
pipe_rx_phy_status_i : in std_logic;
pipe_rx_elec_idle_i : in std_logic;
pipe_rx_polarity_o : out std_logic;
pipe_tx_compliance_o : out std_logic;
pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0);
pipe_tx_data_o : out std_logic_vector(15 downto 0);
pipe_tx_elec_idle_o : out std_logic;
pipe_tx_powerdown_o : out std_logic_vector(1 downto 0);
pipe_clk : in std_logic;
rst_n : in std_logic
);
end pcie_pipe_lane_v6;
architecture v6_pcie of pcie_pipe_lane_v6 is
--******************************************************************//
-- Reality check. //
--******************************************************************//
constant TCQ : integer := 1; -- clock to out delay model
signal pipe_rx_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_rx_data_q : std_logic_vector(15 downto 0);
signal pipe_rx_valid_q : std_logic;
signal pipe_rx_chanisaligned_q : std_logic;
signal pipe_rx_status_q : std_logic_vector(2 downto 0);
signal pipe_rx_phy_status_q : std_logic;
signal pipe_rx_elec_idle_q : std_logic;
signal pipe_rx_polarity_q : std_logic;
signal pipe_tx_compliance_q : std_logic;
signal pipe_tx_char_is_k_q : std_logic_vector(1 downto 0);
signal pipe_tx_data_q : std_logic_vector(15 downto 0);
signal pipe_tx_elec_idle_q : std_logic;
signal pipe_tx_powerdown_q : std_logic_vector(1 downto 0);
signal pipe_rx_char_is_k_qq : std_logic_vector(1 downto 0);
signal pipe_rx_data_qq : std_logic_vector(15 downto 0);
signal pipe_rx_valid_qq : std_logic;
signal pipe_rx_chanisaligned_qq : std_logic;
signal pipe_rx_status_qq : std_logic_vector(2 downto 0);
signal pipe_rx_phy_status_qq : std_logic;
signal pipe_rx_elec_idle_qq : std_logic;
signal pipe_rx_polarity_qq : std_logic;
signal pipe_tx_compliance_qq : std_logic;
signal pipe_tx_char_is_k_qq : std_logic_vector(1 downto 0);
signal pipe_tx_data_qq : std_logic_vector(15 downto 0);
signal pipe_tx_elec_idle_qq : std_logic;
signal pipe_tx_powerdown_qq : std_logic_vector(1 downto 0);
begin
v6pcie0 : if (PIPE_PIPELINE_STAGES = 0) generate
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_i;
pipe_rx_data_o <= pipe_rx_data_i;
pipe_rx_valid_o <= pipe_rx_valid_i;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_i;
pipe_rx_status_o <= pipe_rx_status_i;
pipe_rx_phy_status_o <= pipe_rx_phy_status_i;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_i;
pipe_rx_polarity_o <= pipe_rx_polarity_i;
pipe_tx_compliance_o <= pipe_tx_compliance_i;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_i;
pipe_tx_data_o <= pipe_tx_data_i;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_i;
pipe_tx_powerdown_o <= pipe_tx_powerdown_i;
end generate;
v6pcie1 : if (PIPE_PIPELINE_STAGES = 1) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
pipe_rx_status_q <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
else
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_q;
pipe_rx_data_o <= pipe_rx_data_q;
pipe_rx_valid_o <= pipe_rx_valid_q;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_q;
pipe_rx_status_o <= pipe_rx_status_q;
pipe_rx_phy_status_o <= pipe_rx_phy_status_q;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_q;
pipe_rx_polarity_o <= pipe_rx_polarity_q;
pipe_tx_compliance_o <= pipe_tx_compliance_q;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_q;
pipe_tx_data_o <= pipe_tx_data_q;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_q;
pipe_tx_powerdown_o <= pipe_tx_powerdown_q;
end generate;
v6pcie3 : if (PIPE_PIPELINE_STAGES = 2) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_rx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_rx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_rx_valid_q <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= '0' after (TCQ)*1 ps;
pipe_rx_status_q <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_q <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_q <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_q <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= "00" after (TCQ)*1 ps;
pipe_tx_data_q <= "0000000000000000" after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_q <= "10" after (TCQ)*1 ps;
pipe_rx_char_is_k_qq <= "00" after (TCQ)*1 ps;
pipe_rx_data_qq <= "0000000000000000" after (TCQ)*1 ps;
pipe_rx_valid_qq <= '0' after (TCQ)*1 ps;
pipe_rx_chanisaligned_qq <= '0' after (TCQ)*1 ps;
pipe_rx_status_qq <= "000" after (TCQ)*1 ps;
pipe_rx_phy_status_qq <= '0' after (TCQ)*1 ps;
pipe_rx_elec_idle_qq <= '0' after (TCQ)*1 ps;
pipe_rx_polarity_qq <= '0' after (TCQ)*1 ps;
pipe_tx_compliance_qq <= '0' after (TCQ)*1 ps;
pipe_tx_char_is_k_qq <= "00" after (TCQ)*1 ps;
pipe_tx_data_qq <= "0000000000000000" after (TCQ)*1 ps;
pipe_tx_elec_idle_qq <= '1' after (TCQ)*1 ps;
pipe_tx_powerdown_qq <= "10" after (TCQ)*1 ps;
else
pipe_rx_char_is_k_q <= pipe_rx_char_is_k_i after (TCQ)*1 ps;
pipe_rx_data_q <= pipe_rx_data_i after (TCQ)*1 ps;
pipe_rx_valid_q <= pipe_rx_valid_i after (TCQ)*1 ps;
pipe_rx_chanisaligned_q <= pipe_rx_chanisaligned_i after (TCQ)*1 ps;
pipe_rx_status_q <= pipe_rx_status_i after (TCQ)*1 ps;
pipe_rx_phy_status_q <= pipe_rx_phy_status_i after (TCQ)*1 ps;
pipe_rx_elec_idle_q <= pipe_rx_elec_idle_i after (TCQ)*1 ps;
pipe_rx_polarity_q <= pipe_rx_polarity_i after (TCQ)*1 ps;
pipe_tx_compliance_q <= pipe_tx_compliance_i after (TCQ)*1 ps;
pipe_tx_char_is_k_q <= pipe_tx_char_is_k_i after (TCQ)*1 ps;
pipe_tx_data_q <= pipe_tx_data_i after (TCQ)*1 ps;
pipe_tx_elec_idle_q <= pipe_tx_elec_idle_i after (TCQ)*1 ps;
pipe_tx_powerdown_q <= pipe_tx_powerdown_i after (TCQ)*1 ps;
pipe_rx_char_is_k_qq <= pipe_rx_char_is_k_q after (TCQ)*1 ps;
pipe_rx_data_qq <= pipe_rx_data_q after (TCQ)*1 ps;
pipe_rx_valid_qq <= pipe_rx_valid_q after (TCQ)*1 ps;
pipe_rx_chanisaligned_qq <= pipe_rx_chanisaligned_q after (TCQ)*1 ps;
pipe_rx_status_qq <= pipe_rx_status_q after (TCQ)*1 ps;
pipe_rx_phy_status_qq <= pipe_rx_phy_status_q after (TCQ)*1 ps;
pipe_rx_elec_idle_qq <= pipe_rx_elec_idle_q after (TCQ)*1 ps;
pipe_rx_polarity_qq <= pipe_rx_polarity_q after (TCQ)*1 ps;
pipe_tx_compliance_qq <= pipe_tx_compliance_q after (TCQ)*1 ps;
pipe_tx_char_is_k_qq <= pipe_tx_char_is_k_q after (TCQ)*1 ps;
pipe_tx_data_qq <= pipe_tx_data_q after (TCQ)*1 ps;
pipe_tx_elec_idle_qq <= pipe_tx_elec_idle_q after (TCQ)*1 ps;
pipe_tx_powerdown_qq <= pipe_tx_powerdown_q after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_rx_char_is_k_o <= pipe_rx_char_is_k_qq;
pipe_rx_data_o <= pipe_rx_data_qq;
pipe_rx_valid_o <= pipe_rx_valid_qq;
pipe_rx_chanisaligned_o <= pipe_rx_chanisaligned_qq;
pipe_rx_status_o <= pipe_rx_status_qq;
pipe_rx_phy_status_o <= pipe_rx_phy_status_qq;
pipe_rx_elec_idle_o <= pipe_rx_elec_idle_qq;
pipe_rx_polarity_o <= pipe_rx_polarity_qq;
pipe_tx_compliance_o <= pipe_tx_compliance_qq;
pipe_tx_char_is_k_o <= pipe_tx_char_is_k_qq;
pipe_tx_data_o <= pipe_tx_data_qq;
pipe_tx_elec_idle_o <= pipe_tx_elec_idle_qq;
pipe_tx_powerdown_o <= pipe_tx_powerdown_qq;
end generate;
end v6_pcie;
|
gpl-3.0
|
timofonic/PHDL
|
misc/projects/spartan_pcie_board/fpga/lx45t_pinout/ipcore_dir/ddr3_controller/example_design/rtl/traffic_gen/read_data_path.vhd
|
20
|
24605
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
gpl-3.0
|
vpereira/golden_unicorn
|
bin/fpga/ipcore_dir/mem0/user_design/rtl/memc3_wrapper.vhd
|
1
|
53552
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.5
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/06/04 11:24:37 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Wr Port signals
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0) ;
p2_wr_data : in std_logic_vector(31 downto 0) ;
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0) ;
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Rd Port signals
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0) ;
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0) ;
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
--User Port4 Interface Signals
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0) ;
p4_cmd_bl : in std_logic_vector(5 downto 0) ;
p4_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
--Data Wr Port signals
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0) ;
p4_wr_data : in std_logic_vector(31 downto 0) ;
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0) ;
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
--User Port5 Interface Signals
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0) ;
p5_cmd_bl : in std_logic_vector(5 downto 0) ;
p5_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
--Data Rd Port signals
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0) ;
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0) ;
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "111111";
constant C_PORT_CONFIG : string := "B32_B32_W32_R32_W32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_0(2 downto 0) & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(8 downto 6) & C_ARB_TIME_SLOT_0(11 downto 9) & C_ARB_TIME_SLOT_0(14 downto 12) & C_ARB_TIME_SLOT_0(17 downto 15));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_1(2 downto 0) & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(8 downto 6) & C_ARB_TIME_SLOT_1(11 downto 9) & C_ARB_TIME_SLOT_1(14 downto 12) & C_ARB_TIME_SLOT_1(17 downto 15));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_2(2 downto 0) & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(8 downto 6) & C_ARB_TIME_SLOT_2(11 downto 9) & C_ARB_TIME_SLOT_2(14 downto 12) & C_ARB_TIME_SLOT_2(17 downto 15));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_3(2 downto 0) & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(8 downto 6) & C_ARB_TIME_SLOT_3(11 downto 9) & C_ARB_TIME_SLOT_3(14 downto 12) & C_ARB_TIME_SLOT_3(17 downto 15));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_4(2 downto 0) & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(8 downto 6) & C_ARB_TIME_SLOT_4(11 downto 9) & C_ARB_TIME_SLOT_4(14 downto 12) & C_ARB_TIME_SLOT_4(17 downto 15));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_5(2 downto 0) & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(8 downto 6) & C_ARB_TIME_SLOT_5(11 downto 9) & C_ARB_TIME_SLOT_5(14 downto 12) & C_ARB_TIME_SLOT_5(17 downto 15));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_6(2 downto 0) & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(8 downto 6) & C_ARB_TIME_SLOT_6(11 downto 9) & C_ARB_TIME_SLOT_6(14 downto 12) & C_ARB_TIME_SLOT_6(17 downto 15));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_7(2 downto 0) & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(8 downto 6) & C_ARB_TIME_SLOT_7(11 downto 9) & C_ARB_TIME_SLOT_7(14 downto 12) & C_ARB_TIME_SLOT_7(17 downto 15));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_8(2 downto 0) & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(8 downto 6) & C_ARB_TIME_SLOT_8(11 downto 9) & C_ARB_TIME_SLOT_8(14 downto 12) & C_ARB_TIME_SLOT_8(17 downto 15));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_9(2 downto 0) & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(8 downto 6) & C_ARB_TIME_SLOT_9(11 downto 9) & C_ARB_TIME_SLOT_9(14 downto 12) & C_ARB_TIME_SLOT_9(17 downto 15));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_10(2 downto 0) & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(8 downto 6) & C_ARB_TIME_SLOT_10(11 downto 9) & C_ARB_TIME_SLOT_10(14 downto 12) & C_ARB_TIME_SLOT_10(17 downto 15));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_11(2 downto 0) & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(8 downto 6) & C_ARB_TIME_SLOT_11(11 downto 9) & C_ARB_TIME_SLOT_11(14 downto 12) & C_ARB_TIME_SLOT_11(17 downto 15));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000";
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb3_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_5_ddr_s6, Coregen 12.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr_s6,mig_v3_5,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR_SDRAM,CLK_PERIOD=5000, MEMORY_PART=mt46v32m16xx-5b-it, OUTPUT_DRV=FULL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1_Port2_Port3_Port4_Port5, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=UNCALIB_TERM, DATA_TERMINATION=50 Ohms, CLKFBOUT_MULT_F=4, CLKOUT_DIVIDE=2, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => open,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => open,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => open,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => p2_wr_clk,
p2_wr_en => p2_wr_en,
p2_wr_mask => p2_wr_mask,
p2_wr_data => p2_wr_data,
p2_wr_full => p2_wr_full,
p2_wr_empty => p2_wr_empty,
p2_wr_count => p2_wr_count,
p2_wr_underrun => p2_wr_underrun,
p2_wr_error => p2_wr_error,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => p3_rd_clk,
p3_rd_en => p3_rd_en,
p3_rd_data => p3_rd_data,
p3_rd_full => p3_rd_full,
p3_rd_empty => p3_rd_empty,
p3_rd_count => p3_rd_count,
p3_rd_overflow => p3_rd_overflow,
p3_rd_error => p3_rd_error,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '1',
p4_cmd_clk => p4_cmd_clk,
p4_cmd_en => p4_cmd_en,
p4_cmd_instr => p4_cmd_instr,
p4_cmd_bl => p4_cmd_bl,
p4_cmd_byte_addr => p4_cmd_byte_addr,
p4_cmd_empty => p4_cmd_empty,
p4_cmd_full => p4_cmd_full,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => p4_wr_clk,
p4_wr_en => p4_wr_en,
p4_wr_mask => p4_wr_mask,
p4_wr_data => p4_wr_data,
p4_wr_full => p4_wr_full,
p4_wr_empty => p4_wr_empty,
p4_wr_count => p4_wr_count,
p4_wr_underrun => p4_wr_underrun,
p4_wr_error => p4_wr_error,
p5_arb_en => '1',
p5_cmd_clk => p5_cmd_clk,
p5_cmd_en => p5_cmd_en,
p5_cmd_instr => p5_cmd_instr,
p5_cmd_bl => p5_cmd_bl,
p5_cmd_byte_addr => p5_cmd_byte_addr,
p5_cmd_empty => p5_cmd_empty,
p5_cmd_full => p5_cmd_full,
p5_rd_clk => p5_rd_clk,
p5_rd_en => p5_rd_en,
p5_rd_data => p5_rd_data,
p5_rd_full => p5_rd_full,
p5_rd_empty => p5_rd_empty,
p5_rd_count => p5_rd_count,
p5_rd_overflow => p5_rd_overflow,
p5_rd_error => p5_rd_error,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
|
gpl-3.0
|
jpendlum/crash
|
fpga/src/bpsk_mod/bpsk_mod.vhd
|
2
|
8635
|
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: tx_mod.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Transmit data modulator. Biphase modulates signal with
-- input binary data with option to trigger.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bpsk_mod is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Binary Data)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used (TODO: maybe use for near empty input FIFO?)
-- AXIS Stream Master Interface (Modulated complex samples)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Not used
-- Sideband signals
trigger_stb : in std_logic);
end entity;
architecture RTL of bpsk_mod is
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
type slv_256x32 is array(0 to 255) of std_logic_vector(31 downto 0);
signal ctrl_reg : slv_256x32 := (others=>(others=>'0'));
signal status_reg : slv_256x32 := (others=>(others=>'0'));
signal axis_master_tdest_hold : std_logic_vector(2 downto 0);
signal axis_master_tdest_safe : std_logic_vector(2 downto 0);
signal mod_data : std_logic_vector(63 downto 0);
signal bit_cnt : integer range 0 to 63;
signal enable : std_logic;
signal external_enable : std_logic;
signal external_trigger_enable : std_logic;
signal packet_size_cnt : integer;
signal packet_size : integer;
signal trigger_stb_reg : std_logic;
signal transmitting : std_logic;
begin
axis_slave_irq <= '0';
axis_master_irq <= '0';
axis_master_tdest <= axis_master_tdest_safe;
proc_modulate : process(clk,enable,external_enable)
begin
if (enable = '0' AND external_enable = '0') then
axis_slave_tready <= '0';
axis_master_tvalid <= '0';
axis_master_tlast <= '0';
axis_master_tdata <= (others=>'0');
packet_size_cnt <= packet_size; -- This is intentional
transmitting <= '0';
else
if rising_edge(clk) then
transmitting <= '1';
-- TODO: This code takes 65 clock cycles to transfer 64 complex samples. Should look into
-- redoing this so the single clock cycle delay is avoided.
-- Grab the AXI-Stream data when enabled
if (axis_slave_tvalid = '1' AND bit_cnt = 0) then
axis_slave_tready <= '1';
axis_master_tvalid <= '1';
mod_data <= axis_slave_tdata;
else
axis_slave_tready <= '0';
end if;
-- Count the number of data bits sent
axis_master_tlast <= '0';
if (axis_master_tready = '1') then
if (bit_cnt = 63) then
if (packet_size_cnt = 1) then
axis_master_tlast <= '1';
packet_size_cnt <= packet_size;
else
packet_size_cnt <= packet_size_cnt - 1;
end if;
axis_master_tvalid <= '0';
bit_cnt <= 0;
else
bit_cnt <= bit_cnt + 1;
end if;
end if;
-- Modulate I & Q
-- I
if (mod_data(bit_cnt) = '1') then
axis_master_tdata(31 downto 0) <= x"7FFFFFFF";
else
axis_master_tdata(31 downto 0) <= x"80000000";
end if;
-- Q
axis_master_tdata(63 downto 32) <= (others=>'0');
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Control and status registers.
-------------------------------------------------------------------------------
proc_ctrl_status_reg : process(clk,rst_n)
begin
if (rst_n = '0') then
external_enable <= '0';
ctrl_reg <= (others=>(others=>'0'));
axis_master_tdest_safe <= (others=>'0');
trigger_stb_reg <= '0';
else
if rising_edge(clk) then
-- Update control registers only when accelerator 0 is accessed
if (ctrl_stb = '1') then
ctrl_reg(to_integer(unsigned(ctrl_addr(7 downto 0)))) <= ctrl_data;
end if;
-- Output status register
if (status_stb = '1') then
status_data <= status_reg(to_integer(unsigned(status_addr(7 downto 0))));
end if;
-- The destination can only update when no data is being transmitted, i.e. FFT disabled
if (enable = '0' AND external_enable = '0') then
axis_master_tdest_safe <= axis_master_tdest_hold;
end if;
-- Register sideband signals
trigger_stb_reg <= trigger_stb;
-- Enable on trigger and disable only when external_trigger_enable is deasserted
if (trigger_stb_reg = '1' AND external_trigger_enable = '1') then
external_enable <= '1';
end if;
if (external_trigger_enable = '0') then
external_enable <= '0';
end if;
end if;
end if;
end process;
-- Control Registers
-- Bank 0 (Enable and destination)
enable <= ctrl_reg(0)(0);
external_trigger_enable <= ctrl_reg(0)(1);
axis_master_tdest_hold <= ctrl_reg(0)(31 downto 29);
-- Bank 1 (Packet size)
packet_size <= to_integer(unsigned(ctrl_reg(1)(31 downto 0)));
-- Status Registers
-- Bank 0 (Enable and destination Readback)
status_reg(0)(0) <= enable;
status_reg(0)(1) <= external_trigger_enable;
status_reg(0)(31 downto 29) <= axis_master_tdest_hold;
-- Bank 1 (Packet size Readback)
status_reg(1) <= std_logic_vector(to_unsigned(packet_size,32));
-- Bank 2
status_reg(2)(0) <= transmitting;
end architecture;
|
gpl-3.0
|
jpendlum/crash
|
fpga/src/common/synchronizer_slv.vhd
|
2
|
4207
|
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: synchronizer_slv.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Sychronizer to cross clock domains using two registers.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity synchronizer_slv is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic_vector := "0"); -- Can either set everything to the same value or individualize each bit
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic_vector; -- Asynchronous input
sync : out std_logic_vector); -- Synchronized output
end entity;
architecture RTL of synchronizer_slv is
component synchronizer is
generic (
STROBE_EDGE : string := "N"; -- "R"ising, "F"alling, "B"oth, or "N"one.
RESET_OUTPUT : std_logic := '0');
port (
clk : in std_logic;
reset : in std_logic;
async : in std_logic; -- Asynchronous input
sync : out std_logic); -- Synchronized output
end component;
begin
-- The default outputs are all the same
gen_same_default_output : if RESET_OUTPUT'length = 1 generate
gen_synchronizers : for i in 0 to async'length-1 generate
inst_synchronizer : synchronizer
generic map (
STROBE_EDGE => STROBE_EDGE,
RESET_OUTPUT => RESET_OUTPUT(0))
port map (
clk => clk,
reset => reset,
async => async(i),
sync => sync(i));
end generate;
end generate;
-- The outputs are individualized and async was declared using 'downto' orientation.
-- This kludge is necessary (as far as I know), because I could not think of another
-- way to deal with the fact that RESET_OUTPUT and async could have different
-- orientations, i.e. '0 to n' vs 'n downto 0'.
gen_individualized_default_output : if ((RESET_OUTPUT'length /= 1) AND (RESET_OUTPUT'left = async'left)) generate
gen_synchronizers : for i in 0 to async'length-1 generate
inst_synchronizer : synchronizer
generic map (
STROBE_EDGE => STROBE_EDGE,
RESET_OUTPUT => RESET_OUTPUT(i))
port map (
clk => clk,
reset => reset,
async => async(i),
sync => sync(i));
end generate;
end generate;
gen_individualized_default_output_inverted : if ((RESET_OUTPUT'length /= 1) AND (RESET_OUTPUT'left /= async'left)) generate
gen_synchronizers : for i in 0 to async'length-1 generate
inst_synchronizer : synchronizer
generic map (
STROBE_EDGE => STROBE_EDGE,
RESET_OUTPUT => RESET_OUTPUT(async'length-1-i))
port map (
clk => clk,
reset => reset,
async => async(i),
sync => sync(i));
end generate;
end generate;
end RTL;
|
gpl-3.0
|
aylons/sp601_spi_test
|
hdl/modules/master_controller/master_controller.vhd
|
1
|
1972
|
-------------------------------------------------------------------------------
-- Title : Master controller
-- Project :
-------------------------------------------------------------------------------
-- File : master_controller.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-10-23
-- Last update: 2014-10-30
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Simple controller for master SPI
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-10-23 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity master_controller is
port (
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
spi_req_i : in std_logic;
spi_wen_o : out std_logic;
count_up_o : out std_logic
);
end entity master_controller;
architecture str of master_controller is
signal wen : std_logic := '1';
begin -- architecture str
send : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
wen <= '1';
else
if spi_req_i = '1' and en_i = '1' then
wen <= '1';
if wen = '0' then
count_up_o <= '1';
else
count_up_o <= '0';
end if;
else
wen <= '0';
count_up_o <= '0';
end if;
end if;
end if;
end process;
spi_wen_o <= wen;
end architecture str;
-------------------------------------------------------------------------------
|
gpl-3.0
|
ASP-SoC/ASP-SoC
|
libASP/grpPackages/pkgFixed/src/numeric_std_additions.vhdl
|
2
|
95104
|
------------------------------------------------------------------------------
-- "numeric_std_additions" package contains the additions to the standard
-- "numeric_std" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.numeric_std_additions.all;
-- (this package is independant of "std_logic_1164_additions")
-- Last Modified: $Date: 2007/09/27 14:46:32 $
-- RCS ID: $Id: numeric_std_additions.vhdl,v 1.9 2007/09/27 14:46:32 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package numeric_std_additions is
-- Make these a subtype of "signed" and "unsigned" for compatability
-- type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
-- type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;
subtype UNRESOLVED_UNSIGNED is UNSIGNED;
subtype UNRESOLVED_SIGNED is SIGNED;
-- alias U_UNSIGNED is UNRESOLVED_UNSIGNED;
-- alias U_SIGNED is UNRESOLVED_SIGNED;
subtype U_UNSIGNED is UNSIGNED;
subtype U_SIGNED is SIGNED;
-- Id: A.3R
function "+"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.3 where R is a one bit UNSIGNED
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.4R
function "+"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.4 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.4L
function "+"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.4 where L is bit 0 of a non-negative
-- SIGNED
-- Id: A.9R
function "-"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.10R
function "-"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.10L
function "-"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: M.2B
-- %%% function "?=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic;
function \?=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- Id: M.3B
-- %%% function "?=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic;
function \?=\ (L, R : SIGNED) return STD_ULOGIC;
function \?/=\ (L, R : SIGNED) return STD_ULOGIC;
function \?>\ (L, R : SIGNED) return STD_ULOGIC;
function \?>=\ (L, R : SIGNED) return STD_ULOGIC;
function \?<\ (L, R : SIGNED) return STD_ULOGIC;
function \?<=\ (L, R : SIGNED) return STD_ULOGIC;
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
-- Result subtype: std_ulogic
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Overloaded functions from "std_logic_1164"
function To_X01 (s : UNSIGNED) return UNSIGNED;
function To_X01 (s : SIGNED) return SIGNED;
function To_X01Z (s : UNSIGNED) return UNSIGNED;
function To_X01Z (s : SIGNED) return SIGNED;
function To_UX01 (s : UNSIGNED) return UNSIGNED;
function To_UX01 (s : SIGNED) return SIGNED;
function Is_X (s : UNSIGNED) return BOOLEAN;
function Is_X (s : SIGNED) return BOOLEAN;
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit funcitons, using the local ">" operator
function maximum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l, r : SIGNED) -- inputs
return SIGNED;
function minimum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l, r : SIGNED) -- inputs
return SIGNED;
function maximum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function maximum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function minimum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function minimum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function maximum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
function minimum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
-- Finds the first "Y" in the input string. Returns an integer index
-- into that string. If "Y" does not exist in the string, then the
-- "find_rightmost" returns arg'low -1, and "find_leftmost" returns -1
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
alias TO_U_UNSIGNED is
TO_UNRESOLVED_UNSIGNED[NATURAL, NATURAL return UNRESOLVED_UNSIGNED];
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
alias TO_U_SIGNED is
TO_UNRESOLVED_SIGNED[NATURAL, NATURAL return UNRESOLVED_SIGNED];
-- L.15
function "and" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.16
function "and" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.17
function "or" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.18
function "or" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.19
function "nand" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.20
function "nand" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.21
function "nor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.22
function "nor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.23
function "xor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.24
function "xor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.25
function "xnor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.26
function "xnor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.27
function "and" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.28
function "and" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.29
function "or" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.30
function "or" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.31
function "nand" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.32
function "nand" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.33
function "nor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.34
function "nor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.35
function "xor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.36
function "xor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.37
function "xnor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.38
function "xnor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- %%% remove 12 functions (old syntax)
function and_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
function and_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( l : SIGNED ) RETURN std_ulogic;
-- function "nand" ( l : SIGNED ) RETURN std_ulogic;
-- function "or" ( l : SIGNED ) RETURN std_ulogic;
-- function "nor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : SIGNED ) RETURN std_ulogic;
-- function "and" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nand" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "or" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : UNSIGNED ) RETURN std_ulogic;
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- string functions
-------------------------------------------------------------------
function to_string (value : UNSIGNED) return STRING;
function to_string (value : SIGNED) return STRING;
-- explicitly defined operations
alias to_bstring is to_string [UNSIGNED return STRING];
alias to_bstring is to_string [SIGNED return STRING];
alias to_binary_string is to_string [UNSIGNED return STRING];
alias to_binary_string is to_string [SIGNED return STRING];
function to_ostring (value : UNSIGNED) return STRING;
function to_ostring (value : SIGNED) return STRING;
alias to_octal_string is to_ostring [UNSIGNED return STRING];
alias to_octal_string is to_ostring [SIGNED return STRING];
function to_hstring (value : UNSIGNED) return STRING;
function to_hstring (value : SIGNED) return STRING;
alias to_hex_string is to_hstring [UNSIGNED return STRING];
alias to_hex_string is to_hstring [SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNSIGNED);
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNSIGNED];
alias BREAD is READ [LINE, SIGNED];
alias BINARY_READ is READ [LINE, UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNSIGNED];
alias BINARY_READ is READ [LINE, SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out SIGNED);
alias OCTAL_READ is OREAD [LINE, UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNSIGNED];
alias OCTAL_READ is OREAD [LINE, SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out SIGNED);
alias HEX_READ is HREAD [LINE, UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNSIGNED];
alias HEX_READ is HREAD [LINE, SIGNED];
alias BWRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, SIGNED, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
end package numeric_std_additions;
package body numeric_std_additions is
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
function MAX (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end function MAX;
-- Id: A.3R
function "+"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4R
function "+"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.9R
function "-"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10R
function "-"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | X |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | W |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | H |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ ( l, r : STD_ULOGIC ) return STD_ULOGIC is
variable value : STD_ULOGIC;
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: UNSIGNED) return std_ulogic is
-- end function "?=";
-- Id: M.3B
function \?=\ (L, R: SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: signed) return std_ulogic is
-- end function "?=";
-- Id: C.75
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_UNSIGNED(L, R'length), R);
end function \?=\;
-- Id: C.76
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_SIGNED(L, R'length), R);
end function \?=\;
-- Id: C.77
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?=\ (L, TO_UNSIGNED(R, L'length));
end function \?=\;
-- Id: C.78
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?=\ (L, TO_SIGNED(R, L'length));
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?/=";
function \?/=\ (L, R : SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?/=";
-- Id: C.75
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_UNSIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.76
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_SIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.77
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?/=\ (L, TO_UNSIGNED(R, L'length));
end function \?/=\;
-- Id: C.78
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?/=\ (L, TO_SIGNED(R, L'length));
end function \?/=\;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>";
-- Id: C.57
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_UNSIGNED(L, R'length), R);
end function \?>\;
-- Id: C.58
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_SIGNED(L, R'length),R);
end function \?>\;
-- Id: C.59
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>\ (L, TO_UNSIGNED(R, L'length));
end function \?>\;
-- Id: C.60
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>\ (L, TO_SIGNED(R, L'length));
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_UNSIGNED(L, R'length), R);
end function \?>=\;
-- Id: C.64
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_SIGNED(L, R'length),R);
end function \?>=\;
-- Id: C.65
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>=\ (L, TO_UNSIGNED(R, L'length));
end function \?>=\;
-- Id: C.66
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>=\ (L, TO_SIGNED(R, L'length));
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<";
-- Id: C.57
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_UNSIGNED(L, R'length), R);
end function \?<\;
-- Id: C.58
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_SIGNED(L, R'length),R);
end function \?<\;
-- Id: C.59
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<\ (L, TO_UNSIGNED(R, L'length));
end function \?<\;
-- Id: C.60
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<\ (L, TO_SIGNED(R, L'length));
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<=";
-- Id: C.63
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_UNSIGNED(L, R'length), R);
end function \?<=\;
-- Id: C.64
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_SIGNED(L, R'length),R);
end function \?<=\;
-- Id: C.65
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<=\ (L, TO_UNSIGNED(R, L'length));
end function \?<=\;
-- Id: C.66
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<=\ (L, TO_SIGNED(R, L'length));
end function \?<=\;
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)
return SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
-- begin LCS-2006-120
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- These functions are in std_logic_1164 and are defined for
-- std_logic_vector. They are overloaded here.
function To_X01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01Z ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_X01Z ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_UX01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function To_UX01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-----------------------------------------------------------------------------
-- New/updated functions for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit functions, using the local ">" operator
-- UNSIGNED output
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- signed output
function MAXIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- UNSIGNED output
function MINIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- signed output
function MINIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(to_unsigned (arg, size));
end function TO_UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(to_signed (arg, size));
end function TO_UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
-- Performs the boolean operation on every bit in the vector
-- L.15
function "and" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.16
function "and" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.17
function "or" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.18
function "or" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.19
function "nand" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.20
function "nand" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.21
function "nor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.22
function "nor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.23
function "xor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.24
function "xor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.25
function "xnor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.26
function "xnor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-- L.27
function "and" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.28
function "and" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.29
function "or" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.30
function "or" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.31
function "nand" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.32
function "nand" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.33
function "nor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.34
function "nor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.35
function "xor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.36
function "xor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.37
function "xnor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.38
function "xnor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
--------------------------------------------------------------------------
-- Reduction operations
--------------------------------------------------------------------------
-- %%% Remove the following 12 funcitons (old syntax)
function and_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return and_reduce (UNSIGNED ( l ));
end function and_reduce;
function and_reduce ( l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '1'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "and" (BUS_int(BUS_int'right),BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "and" (Upper, Lower);
end if;
end if;
return Result;
end function and_reduce;
function nand_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce ( l ));
end function nand_reduce;
function nand_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce (l ));
end function nand_reduce;
function or_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return or_reduce (UNSIGNED ( l ));
end function or_reduce;
function or_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "or" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := or_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "or" (Upper, Lower);
end if;
end if;
return Result;
end function or_reduce;
function nor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function nor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function xor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return xor_reduce (UNSIGNED ( l ));
end function xor_reduce;
function xor_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "xor" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "xor" (Upper, Lower);
end if;
end if;
return Result;
end function xor_reduce;
function xnor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
function xnor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% Replace the above with the following 12 functions (New syntax)
-- function "and" ( l : SIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "and" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "nand" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "nand" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "or" ( l : SIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "or" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "nor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "nor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "xor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xnor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- function "xnor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- TO_STRING
-------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
function to_string (value : UNSIGNED) return STRING is
alias ivalue : UNSIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_string (value : SIGNED) return STRING is
alias ivalue : SIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_hstring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value(value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value (value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_hstring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-----------------------------------------------------------------------------
-- Read and Write routines
-----------------------------------------------------------------------------
-- Routines copied from the "std_logic_1164_additions" package
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
good := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
-- purpose: or reduction
function or_reduce (
arg : STD_ULOGIC_VECTOR)
return STD_ULOGIC is
variable uarg : UNSIGNED (arg'range);
begin
uarg := unsigned(arg);
return or_reduce (uarg);
end function or_reduce;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
-- End copied code.
procedure READ (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.OREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.HREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- rtl_synthesis on
-- pragma synthesis_on
end package body numeric_std_additions;
|
gpl-3.0
|
lvd2/ngs
|
fpga/current/dma/modelsim/T80_RegX.vhd
|
8
|
5101
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers for Xilinx Select RAM
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Removed UNISIM library and added componet declaration
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
component RAM16X1D
port(
DPO : out std_ulogic;
SPO : out std_ulogic;
A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
D : in std_ulogic;
DPRA0 : in std_ulogic;
DPRA1 : in std_ulogic;
DPRA2 : in std_ulogic;
DPRA3 : in std_ulogic;
WCLK : in std_ulogic;
WE : in std_ulogic);
end component;
signal ENH : std_logic;
signal ENL : std_logic;
begin
ENH <= CEN and WEH;
ENL <= CEN and WEL;
bG1: for I in 0 to 7 generate
begin
Reg1H : RAM16X1D
port map(
DPO => DOBH(i),
SPO => DOAH(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg1L : RAM16X1D
port map(
DPO => DOBL(i),
SPO => DOAL(i),
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrB(0),
DPRA1 => AddrB(1),
DPRA2 => AddrB(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
Reg2H : RAM16X1D
port map(
DPO => DOCH(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIH(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENH);
Reg2L : RAM16X1D
port map(
DPO => DOCL(i),
SPO => open,
A0 => AddrA(0),
A1 => AddrA(1),
A2 => AddrA(2),
A3 => '0',
D => DIL(i),
DPRA0 => AddrC(0),
DPRA1 => AddrC(1),
DPRA2 => AddrC(2),
DPRA3 => '0',
WCLK => Clk,
WE => ENL);
end generate;
end;
|
gpl-3.0
|
lvd2/ngs
|
fpga/current/dma/modelsim/T80a.vhd
|
8
|
7490
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;
|
gpl-3.0
|
ASP-SoC/ASP-SoC
|
libASP/grpPackages/pkgFixed/src/std_logic_1164_additions.vhdl
|
2
|
70414
|
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2007-09-11 14:52:13-04 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.12 2007-09-11 14:52:13-04 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
-- pragma synthesis_off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-- end Bugzilla issue #148
-------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
-- The following functions are implicity in 1076-2006
-- truth table for "?=" function
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
if ((l'length < 1) or (r'length < 1)) then
report "STD_LOGIC_1164.""?/="": null detected, returning X"
severity warning;
return 'X';
end if;
if lv'length /= rv'length then
report "STD_LOGIC_1164.""?/="": L'LENGTH /= R'LENGTH, returning X"
severity warning;
return 'X';
else
result := '0';
for i in lv'low to lv'high loop
result1 := no_match_logic_table(lv(i), rv(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx > rx then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?>="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx >= rx then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% END FUNCTION "?/>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<"": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx < rx then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% END FUNCTION "?/<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
variable lx, rx : STD_ULOGIC;
begin
if (l = '-') or (r = '-') then
report "STD_LOGIC_1164.""?<="": '-' found in compare string"
severity error;
return 'X';
else
lx := to_x01 (l);
rx := to_x01 (r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx <= rx then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END FUNCTION "?/<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-- pragma synthesis_off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
|
gpl-3.0
|
lvd2/ngs
|
fpga/current/dma/sim_models/t80_alu.vhd
|
15
|
11889
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
gpl-3.0
|
lvd2/ngs
|
fpga/current/dma/modelsim/t80_alu.vhd
|
15
|
11889
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
gpl-3.0
|
ASP-SoC/ASP-SoC
|
libASP/grpPlatform/unitPlatformHps/hdl/PlatformHps-e.vhd
|
1
|
3445
|
library ieee;
use ieee.std_logic_1164.all;
entity PlatformHps is
port(
-- Clock
CLOCK_50 : in std_logic;
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- KEY
KEY : in std_logic_vector(3 downto 0);
-- Switches
SW : in std_logic_vector(9 downto 0);
--7SEG
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : in std_logic;
AUD_BCLK : in std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : in std_logic;
AUD_XCK : out std_logic;
-- GPIOs
GPIO_1_D2 : in std_logic;
GPIO_1_D3 : in std_logic;
GPIO_1_D4 : in std_logic;
GPIO_1_D5 : in std_logic;
GPIO_1_D6 : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0) := (others => 'X');
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0) := (others => 'X');
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0) := (others => 'X');
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_RZQ : in std_logic := 'X';
HPS_KEY : inout std_logic;
HPS_LED : inout std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity PlatformHps;
|
gpl-3.0
|
lvd2/ngs
|
fpga/obsolete/fpgaE_dma/dma/modelsim/T80_Pack.vhd
|
7
|
8485
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
|
gpl-3.0
|
lvd2/ngs
|
fpga/current/tb/z80/T80.vhd
|
7
|
31904
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusB <= "--------";
end case;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
|
gpl-3.0
|
albertomg994/VHDL_Projects
|
AmgPacman/src/init_ram.vhd
|
1
|
5188
|
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: init_ram.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity init_ram is
Port ( clk_50MHz : in STD_LOGIC;
rst : in STD_LOGIC;
ini : in STD_LOGIC;
ram_addr : out std_logic_vector(5 downto 0);
ram_data : out std_logic_vector(2 downto 0);
ram_we : out std_logic;
fin : out STD_LOGIC
);
end init_ram;
architecture arq of init_ram is
type t_st is (s0, s1, s2, s3);
signal current_state, next_state : t_st; -- Estados actual y siguiente.
signal rom_out: std_logic_vector(2 downto 0);
-- Contador:
signal cntr: std_logic_vector(7 downto 0);
signal cntr_add1: std_logic_vector(7 downto 0);
signal cntr_ld: std_logic;
COMPONENT tablero_rom
PORT(
clk : IN std_logic;
x : IN std_logic_vector(2 downto 0);
y : IN std_logic_vector(2 downto 0);
rgb : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
COMPONENT incrCuenta8bits_conFin
PORT(
num_in : IN std_logic_vector(7 downto 0);
num_out : OUT std_logic_vector(7 downto 0);
fin : OUT std_logic
);
END COMPONENT;
begin
Inst_tablero_rom: tablero_rom PORT MAP(
clk => clk_50MHz,
x => cntr(2 downto 0),
y => cntr(5 downto 3),
rgb => rom_out
);
Inst_incrCuenta8bits_conFin: incrCuenta8bits_conFin PORT MAP(
num_in => cntr,
num_out => cntr_add1,
fin => open
);
---------------------------------------------------
-- Proceso de calculo del estado siguiente y salidas mealy
---------------------------------------------------
p_next_state : process (current_state, ini, cntr, cntr_add1) is
begin
case current_state is
when s0 =>
if ini = '1' then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
if cntr = "01000000" then -- Si ya hemos escrito todas las posiciones
next_state <= s3;
else
next_state <= s2;
end if;
when s2 =>
next_state <= s1;
when s3 =>
next_state <= s3;
end case;
end process p_next_state;
---------------------------------------------------
-- Proceso de asignación de valores a las salidas
---------------------------------------------------
p_outputs : process (current_state, cntr, rom_out)
begin
case current_state is
when s0 =>
ram_addr <= (others => '0');
ram_data <= (others => '0');
ram_we <= '0';
fin <= '0';
cntr_ld <= '0';
when s1 =>
ram_addr <= cntr(5 downto 0);
ram_data <= rom_out;
ram_we <= '0';
fin <= '0';
cntr_ld <= '0';
when s2 =>
ram_addr <= cntr(5 downto 0);
ram_data <= rom_out;
ram_we <= '1';
fin <= '0';
cntr_ld <= '1';
when s3 =>
ram_addr <= (others => '0');
ram_data <= (others => '0');
ram_we <= '0';
fin <= '1';
cntr_ld <= '0';
end case;
end process p_outputs;
---------------------------------------------------
-- Contador hasta 64
---------------------------------------------------
p_cntr: process (rst, clk_50MHz, ini, cntr_ld, cntr)
begin
if rst = '1' then
cntr <= (others => '0');
elsif rising_edge(clk_50MHz) then
-- Si load = 1 y cntr != 64
--if cntr = "00111111" then -- Queremos que en 64 vuelva a 0 (solo llega a 63)
if cntr = "01000000" then
cntr <= (others => '0');
elsif cntr_ld = '1' then --and cntr /= "0111111" then
cntr <= cntr_add1;
else
cntr <= cntr;
end if;
end if;
end process p_cntr;
---------------------------------------------------
-- Proceso de actualizacion del estado
---------------------------------------------------
p_update_state: process (clk_50MHz, rst) is
begin
if rst = '1' then
current_state <= s0;
elsif rising_edge(clk_50MHz) then
current_state <= next_state;
end if;
end process p_update_state;
end arq;
|
gpl-3.0
|
chronos38/DSD-Projekt
|
dezctr/dezctr.vhd
|
1
|
896
|
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity dezctr is
port (
clk50 : in std_logic; -- Takteingang
reset_n : in std_logic; -- Asynchroner Reset
sw_i : in std_logic_vector(9 downto 0); -- Schalter
pb_i : in std_logic_vector(1 downto 0); -- Buttons
ss0_o : out std_logic_vector(7 downto 0); -- Ziffer eins des BCD
ss1_o : out std_logic_vector(7 downto 0); -- Ziffer zwei des BCD
ss2_o : out std_logic_vector(7 downto 0); -- Ziffer drei des BCD
ss3_o : out std_logic_vector(7 downto 0)); -- Ziffer vier des BCD
end entity;
|
gpl-3.0
|
chronos38/DSD-Projekt
|
Testbench/tb_cntr.vhd
|
1
|
4900
|
-- David Wolf if12b096
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_cntr is
end tb_cntr;
architecture sim of tb_cntr is
component cntr
port (
clk50 : in std_logic; -- Takt
reset_n : in std_logic; -- Externer Reset
ctup_i : in std_logic; -- Zählt rauf
ctdown_i : in std_logic; -- Zahlt ab
ctreset_i : in std_logic; -- Interner Reset
cthold_i : in std_logic; -- Zählt nicht
cntr0_o : out std_logic_vector(3 downto 0); -- Erste Ziffer
cntr1_o : out std_logic_vector(3 downto 0); -- Zweite Ziffer
cntr2_o : out std_logic_vector(3 downto 0); -- Dritte Ziffer
cntr3_o : out std_logic_vector(3 downto 0)); -- Vierte Ziffer
end component;
signal s_clk50 : std_logic := '0';
signal s_reset_n : std_logic := '0';
signal s_ctup_i : std_logic := '0';
signal s_ctdown_i : std_logic := '0';
signal s_ctreset_i : std_logic := '0';
signal s_cthold_i : std_logic := '0';
signal s_cntr0_o : std_logic_vector(3 downto 0) := (others => '0');
signal s_cntr1_o : std_logic_vector(3 downto 0) := "0000";
signal s_cntr2_o : std_logic_vector(3 downto 0) := (others => '0');
signal s_cntr3_o : std_logic_vector(3 downto 0) := "0000";
begin
s_clk50 <= not s_clk50 after 20 ps;
-- Erstellt ein Testobjekt
tb_cntr : cntr
port map (
clk50 => s_clk50,
reset_n => s_reset_n,
ctup_i => s_ctup_i,
ctdown_i => s_ctdown_i,
cthold_i => s_cthold_i,
ctreset_i => s_ctreset_i,
cntr0_o => s_cntr0_o,
cntr1_o => s_cntr1_o,
cntr2_o => s_cntr2_o,
cntr3_o => s_cntr3_o);
p_test : process
begin
-- Testfall: Externer Reset
-- Externer Reset '0' der Rest deaktiviert
s_reset_n <= '0';
s_ctup_i <= '1';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: DOWN
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 17 ns;
-- Testfall: HOLD
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '1';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: HOLD auf DOWN
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: UP
-- s_ctdup_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 30 ns;
-- Testfall: HOLD
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '1';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: HOLD auf UP
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: UP auf DOWN
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: DOWN auf UP
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '1';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: RESET
-- s_ctdown_i auf '1'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '1';
wait for 1 ns;
-- Testfall: Alle Eingänge auf '1'
s_reset_n <= '1';
s_ctup_i <= '1';
s_ctdown_i <= '1';
s_cthold_i <= '1';
s_ctreset_i <= '1';
wait for 1 ns;
-- Testfall: Externer Reset
-- Alle Eingänge '0'
s_reset_n <= '0';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 1 ns;
-- Testfall: Nach Reset sollte der Zustand UP sein.
-- Alle Eingänge auf '0'
s_reset_n <= '1';
s_ctup_i <= '0';
s_ctdown_i <= '0';
s_cthold_i <= '0';
s_ctreset_i <= '0';
wait for 100 ps;
end process p_test;
end sim;
|
gpl-3.0
|
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/rom_memory/example_design/rom_memory_exdes.vhd
|
1
|
4344
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rom_memory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rom_memory_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END rom_memory_exdes;
ARCHITECTURE xilinx OF rom_memory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT rom_memory IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : rom_memory
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
gpl-3.0
|
arthurbenemann/fpga-bits
|
undocumented/DCM_clock/seven_seg.vhd
|
2
|
2084
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seven_seg is
Port ( display_hex : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
double_dot : IN STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (4 downto 0);
sevenseg : out STD_LOGIC_VECTOR (7 downto 0));
end seven_seg;
architecture Behavioral of seven_seg is
signal value : STD_LOGIC_VECTOR(4 downto 0) := (OTHERS =>'0');
signal anodes_buf : STD_LOGIC_VECTOR(4 downto 0);
begin
anodes <= anodes_buf;
display_update:process(clk) begin
if rising_edge(clk) then
CASE anodes_buf IS
WHEN "01111" =>
anodes_buf <= "10111";
value <= "0" & display_hex(3 downto 0);
WHEN "10111" =>
anodes_buf <= "11011";
value <= "0" & display_hex(7 downto 4);
WHEN "11011" =>
anodes_buf <= "11101";
value <= "0" & display_hex(11 downto 8);
WHEN "11101" =>
anodes_buf <= "11110";
value <= "0" & display_hex(15 downto 12);
WHEN OTHERS =>
anodes_buf <= "01111";
value <= "10000";
END CASE;
end if;
end process;
display_mapping:process(value, double_dot) begin
CASE value IS
WHEN "0" & x"0" => sevenseg <= NOT x"3F"; -- 0
WHEN "0" & x"1" => sevenseg <= NOT x"06"; -- 1
WHEN "0" & x"2" => sevenseg <= NOT x"5B"; -- 2
WHEN "0" & x"3" => sevenseg <= NOT x"4F"; -- 3
WHEN "0" & x"4" => sevenseg <= NOT x"66"; -- 4
WHEN "0" & x"5" => sevenseg <= NOT x"6D"; -- 5
WHEN "0" & x"6" => sevenseg <= NOT x"7D"; -- 6
WHEN "0" & x"7" => sevenseg <= NOT x"07"; -- 7
WHEN "0" & x"8" => sevenseg <= NOT x"7F"; -- 8
WHEN "0" & x"9" => sevenseg <= NOT x"6F"; -- 9
WHEN "0" & x"a" => sevenseg <= NOT x"77"; -- A
WHEN "0" & x"b" => sevenseg <= NOT x"7C"; -- b
WHEN "0" & x"c" => sevenseg <= NOT x"39"; -- C
WHEN "0" & x"d" => sevenseg <= NOT x"5E"; -- d
WHEN "0" & x"e" => sevenseg <= NOT x"79"; -- E
WHEN "0" & x"f" => sevenseg <= NOT x"71"; -- F
WHEN OTHERS => sevenseg <= "1111111" & ( NOT double_dot);
END CASE;
end process;
end Behavioral;
|
gpl-3.0
|
arthurbenemann/fpga-bits
|
undocumented/VGA1/vga800x600.vhd
|
1
|
1581
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga800x600 is Port (
clk : in std_logic; -- 40 MHz
red : out std_logic_vector(3 downto 0);
green : out std_logic_vector(3 downto 0);
blue : out std_logic_vector(3 downto 0);
hsync: out std_logic;
vsync: out std_logic;
SW : in std_logic);
end vga800x600;
architecture Behavioral of vga800x600 is
signal hcount : std_logic_vector(10 downto 0) := (others =>'0');
signal vcount : std_logic_vector(9 downto 0) := (others =>'0');
begin
counters : process(clk) begin
if rising_edge(clk) then
-- Counters
if hcount = 1055 then
hcount <= (others =>'0');
if vcount = 627 then
vcount <= (others =>'0');
else
vcount <= vcount + 1;
end if;
else
hcount <= hcount + 1;
end if;
-- Hsync
if hcount >= (800+40) and hcount < (800+40+128) then
hsync <= '0';
else
hsync <= '1';
end if;
-- Vsync
if vcount >= (600+1) and vcount < (600+1+4) then
vsync <= '0';
else
vsync <= '1';
end if;
-- Colors
if hcount < 800 and vcount < 600 then
if SW='1' then
red <= hcount(3 downto 0);
green <= "0000";
blue <= vcount(3 downto 0);
else
if (hcount(0) xor vcount(0)) = '1' then
red <= "1111";
green <= "1111";
blue <= "1111";
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
end if;
else
red <= "0000";
green <= "0000";
blue <= "0000";
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
JosiCoder/CtLab
|
FPGA/FPGA SigGen/Source/CounterClockDivider.vhd
|
1
|
5707
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generates the universal counter´s internal pulse or gate signal by dividing
-- the system clock.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library Common;
use work.Globals.all;
entity CounterClockDivider is
generic
(
-- The width of the internal clock divider.
clock_divider_width: integer := 32;
-- '0' for normal operation, '1' to ignore the real system clock
-- frequency when dividing the clock frequency.
clock_divider_test_mode: boolean := false
);
port
(
-- The system clock.
clk: in std_logic;
-- A value indicating the clock division mode.
clk_division_mode: in std_logic_vector (3 downto 0);
-- Gets active for one clock cycle every time the clock division value
-- has been reached.
divider_tick: out std_logic
);
end entity;
architecture stdarch of CounterClockDivider is
constant clock_frequency: natural := 50 * 10**6;
-- Clock divider.
type reg_type is record
division_counter: unsigned (clock_divider_width-1 downto 0);
divider_tick: std_logic;
end record;
signal state, next_state: reg_type :=
(
division_counter => (others => '0'),
divider_tick => '0'
);
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, clk_division_mode) is
variable clock_divider: unsigned (clock_divider_width-1 downto 0);
begin
-- Defaults.
next_state <= state;
next_state.divider_tick <= '0';
-- Select the clock division value.
if (clock_divider_test_mode) then
-- Special value for test purposes, don't divide by real system clock frequency.
clock_divider := to_unsigned(10, clock_divider_width);
else
case clk_division_mode is
-- Frequency measurement.
when "0000" => -- 1 s gate signal
clock_divider := to_unsigned(1 * clock_frequency, clock_divider_width);
when "0001" => -- 0.1 s gate signal
clock_divider := to_unsigned(10 * clock_frequency, clock_divider_width);
when "0010" => -- 10 s gate signal
clock_divider := to_unsigned(clock_frequency / 10, clock_divider_width);
-- Period measurement.
when "0100" => -- 10 MHz pulse signal
clock_divider := to_unsigned(clock_frequency/10**7, clock_divider_width);
when "0101" => -- 1 MHz pulse signal
clock_divider := to_unsigned(clock_frequency/10**6, clock_divider_width);
when "0110" => -- 100 kHz pulse signal
clock_divider := to_unsigned(clock_frequency/10**5, clock_divider_width);
when "0111" => -- 10 kHz pulse signal
clock_divider := to_unsigned(clock_frequency/10**4, clock_divider_width);
when others =>
clock_divider := to_unsigned(1 * clock_frequency, clock_divider_width);
end case;
end if;
-- Check the clock division counter and, if it has reached the division value, raise
-- the divider tick signal for one clock cycle. Ensure that the clock division counter
-- is reset if it reaches or exceeds the division value (exceeding might happen after
-- changing the division value).
if (state.division_counter >= clock_divider-1) then
next_state.division_counter <= (others => '0');
if (state.division_counter = clock_divider-1) then
next_state.divider_tick <= '1';
end if;
else
next_state.division_counter <= state.division_counter + 1;
end if;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
divider_tick <= state.divider_tick;
end architecture;
|
gpl-3.0
|
cvgit/vhdlParser
|
spaceinvaders.vhd
|
1
|
14000
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library lib;
use lib.controller.all;
use lib.general.all;
use lib.io.all;
entity spaceinvaders is
generic
(
rx : integer := 160; -- H resolution
ry : integer := 120; -- W resolution
cpu_num : integer := ALIENS_PER_LINE; -- aliens per line (set in io.vhd)
cpu_lines : integer := ALIEN_LINES; -- number of lines (set in io.vhd)
py : integer := 110; --
alien_w : integer := 11; -- enemy width
alien_h : integer := 8; -- enemy height
player_w : integer := 13; -- player width
player_h : integer := 6 -- player height
);
port
(
------------------------ Clock Input ------------------------
CLOCK_24 : in STD_LOGIC_VECTOR (1 downto 0); -- 24 MHz
CLOCK_50 : in STD_LOGIC; -- 50 MHz
CLOCK_27 : in STD_LOGIC; -- 27 MHz
------------------------ Push Button ------------------------
KEY : in STD_LOGIC_VECTOR (3 downto 0); -- Pushbutton[3:0]
------------------------ 7-SEG Display ------------------------
HEX0 : out STD_LOGIC_VECTOR (6 downto 0);
HEX1 : out STD_LOGIC_VECTOR (6 downto 0);
HEX2 : out STD_LOGIC_VECTOR (6 downto 0);
HEX3 : out STD_LOGIC_VECTOR (6 downto 0);
---------------------------- LED ----------------------------
LEDG : out STD_LOGIC_VECTOR (7 downto 0); -- LED Green[7:0]
------------------------ PS2 --------------------------------
PS2_DAT : inout STD_LOGIC; -- PS2 Data
PS2_CLK : inout STD_LOGIC; -- PS2 Clock
------------------------ VGA --------------------------------
VGA_R, VGA_G, VGA_B : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
VGA_HS, VGA_VS : OUT STD_LOGIC
);
end entity;
architecture Behavior of spaceinvaders is
--------------------------- CLK/RESET ------------------------------
signal clock_s,reset_s,reset: std_logic;
SIGNAL state : GAME_STATE;
------------------------ PLAYER ----------------------------
signal move_s,shot_s,shot_e_s: std_logic;
signal controls: std_logic_vector(2 downto 0);
signal position_x_s: integer range 0 to rx;
signal position_y_s: integer range 0 to ry;
signal shot_y_s: integer range 0 to ry;
signal shot_x_s: integer range 0 to rx;
signal shot_r_s: std_logic;
------------------------ CPU --------------------------------
signal cpu_arr_x: pos_arr_xt;
signal cpu_arr_y: pos_arr_yt;
signal cpu_arr_e: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_c: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_m: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_d: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_game_over: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal turn: std_logic;
signal shot_enemy_y_s: integer range 0 to ry;
signal shot_enemy_x_s: integer range 0 to rx;
signal shot_enemy_e_s: std_logic;
signal shot_enemy_r_s: std_logic;
signal enemy_shooting: std_logic;
signal clk_enemy_shoot: std_logic;
signal player_death, player_reset : std_logic;
signal player_death_by_alien : std_logic;
signal player_exploding,pc_dead_delay : std_logic;
type PC_STATE_TYPE is (ALIVE, EXPLODING, DEAD);
signal pc_state : PC_STATE_TYPE;
signal game_over,game_over_by_lives : std_logic;
signal game_win : std_logic;
------------------------ HEX --------------------------------
signal hex_s: std_logic_vector(27 downto 0);
signal rnd_s,cmb_s: integer;
signal choosen_enemy : integer;
type hex_arr_t is array(cpu_num-1 downto 0) of std_logic_vector(6 downto 0);
signal hex0_arr,hex1_arr,hex2_arr,hex3_arr: hex_arr_t;
signal lives : natural range 0 to 4 := 4;
begin
----------------------------------------------------------------
-- Game reset
----------------------------------------------------------------
reset <= not(KEY(0)); -- Push Button 0
----------------------------------------------------------------
----------------------------------------------------------------
-- Keyboard control
----------------------------------------------------------------
control: kbd_input
port map
( CLOCK_24(0), not(reset_s), KEY(1), PS2_DAT, PS2_CLK, SHOT_S, MOVE_S, CONTROLS );
----------------------------------------------------------------
----------------------------------------------------------------
-- VGA
----------------------------------------------------------------
vga: vga_module
generic map (
rx,
ry,
cpu_num*cpu_lines
)
port map
(
CLOCK_27, NOT(reset),
state,
POSITION_X_S,
POSITION_Y_S,
player_exploding,
SHOT_X_S,
SHOT_Y_S,
shot_enemy_x_s,
shot_enemy_y_s,
cpu_arr_e,
cpu_arr_d,
cpu_arr_x,
cpu_arr_y,
VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS
);
----------------------------------------------------------------
----------------------------------------------------------------
-- Player
----------------------------------------------------------------
-- Player controller
player: pc
generic map
(
clock_div => 1000000,
res_x=>rx,
res_y=>ry,
aux_x=>player_w,
aux_y=>player_h,
pos_y=>py
)
port map
( reset_s OR player_reset, move_s and not(player_exploding), controls(0), CLOCK_50, clock_s, position_x_s, position_y_s);
-- Player shot
pc_shooter: shot
generic map
(
clock_div => 500000,
res_x=>rx,
res_y=>ry,
aux_x=>player_w,
aux_y=>player_h
)
port map
(CLOCK_50, reset_s or shot_r_s, shot_s and not(player_exploding), position_x_s, position_y_s,shot_e_s,shot_x_s,shot_y_s);
-- Player dead sprite
pc_delay: clock_counter
generic map ( 18000000 )
port map ( CLOCK_27, pc_dead_delay );
process (pc_dead_delay)
begin
if reset_s = '1' or player_reset = '1' then
player_exploding <= '0';
player_reset <= '0';
pc_state <= ALIVE;
elsif player_death = '1' then
player_exploding <= '1';
pc_state <= EXPLODING;
elsif rising_edge(pc_dead_delay) then
case pc_state is
when ALIVE =>
when EXPLODING =>
pc_state <= DEAD;
when DEAD =>
player_reset <= '1';
player_exploding <= '0';
end case;
end if;
end process;
----------------------------------------------------------------
----------------------------------------------------------------
-- Aliens generator
----------------------------------------------------------------
-- Verify if any enemy reached one of the sides
turn <= '0' when cpu_arr_m = (cpu_arr_m'range => '0') else '1';
-- Generate enemies
generate_cpu:
for i in 0 to (cpu_num*cpu_lines-1) generate
cpu_x: cpu
generic map
(
res_x => rx,
res_y => ry,
pos_x => 15+(18*(i mod cpu_num)),
pos_y => 15+10*(i/cpu_num),
aux_x => alien_w,
aux_y => alien_h,
clock_div => 18000000 -- 18000000
)
port map
(reset_s,cpu_arr_c(i),CLOCK_50,turn,cpu_arr_m(i),cpu_arr_e(i),cpu_arr_x(i),cpu_arr_y(i),cpu_arr_d(i),cpu_game_over(i));
collision_x: collisor
generic map
( res_x=>rx,
res_y=>ry,
w=>alien_w,
h=>alien_h,
clock_div=>100
)
port map
(CLOCK_27, cpu_arr_e(i) and shot_e_s, shot_x_s,cpu_arr_x(i),shot_y_s,cpu_arr_y(i),cpu_arr_c(i));
end generate;
----------------------------------------------------------------
----------------------------------------------------------------
-- ALIEN SHOOTER
----------------------------------------------------------------
enemy_shot_clock: clock_counter
generic map ( 27000000 )
port map ( CLOCK_27, clk_enemy_shoot );
-- Randomly select an alive enemy to shoot
PROCESS (clk_enemy_shoot)
BEGIN
if rising_edge(clk_enemy_shoot) then
choosen_enemy <= rnd_s;
enemy_shooting <= cpu_arr_e(choosen_enemy);
end if;
end process;
cpu_x_shooter: shot
generic map
(
clock_div => 1000000, -- 2500000
res_x=>rx,
res_y=>ry,
aux_x=>alien_w,
aux_y=>0,
flag_up=>'0'
)
port map
(CLOCK_50, reset_s OR shot_enemy_r_s, enemy_shooting, cpu_arr_x(choosen_enemy), cpu_arr_y(choosen_enemy),shot_enemy_e_s,shot_enemy_x_s,shot_enemy_y_s);
-- ALIEN SHOOT COLLISION WITH PLAYER
collision_x: collisor
generic map
( res_x=>rx,
res_y=>ry,
w=>player_w,
h=>player_h,
clock_div=>100
)
port map
(CLOCK_27, shot_enemy_e_s, shot_enemy_x_s, position_x_s, shot_enemy_y_s, position_y_s, shot_enemy_r_s);
shot_r_s <= '0' when cpu_arr_c = (cpu_arr_c'range => '0') else '1';
----------------------------------------------------------------
----------------------------------------------------------------
-- GAME STATE MACHINE
----------------------------------------------------------------
spaceinvaders_fsm:
PROCESS (reset,CLOCK_27)
BEGIN
IF reset = '1' THEN
reset_s <= '1';
state <= START;
ELSIF rising_edge(CLOCK_27) THEN
CASE state IS
WHEN START =>
reset_s <= '0';
IF controls(1) = '1' THEN
reset_s <= '1';
state <= PLAYING;
END IF;
WHEN PLAYING =>
reset_s <= '0';
IF game_over = '1' THEN
state <= GAME_OVER_STATE;
ELSIF game_win = '1' THEN
state <= WIN;
END IF;
WHEN GAME_OVER_STATE | WIN =>
IF controls(1) = '1' THEN
reset_s <= '1';
state <= PLAYING;
END IF;
END CASE;
END IF;
END PROCESS;
----------------------------------------------------------------
----------------------------------------------------------------
-- Live system
----------------------------------------------------------------
-- Death verification
player_death_by_alien <= '0' when cpu_game_over = (cpu_game_over'range => '0') else '1';
player_death <= shot_enemy_r_s;
-- lives: asynchronous reverse counter
process (player_death, reset_s)
begin
if reset_s = '1' then
lives <= 4;
elsif rising_edge(player_death) then
lives <= lives - 1;
end if;
end process;
-- Game win verification
game_win <= '1' when cpu_arr_e = (cpu_arr_e'range => '0') else '0';
-- Game over verification
game_over_by_lives <= '1' when lives = 0 else '0'; -- game over when lives = 0
game_over <= (player_death_by_alien OR game_over_by_lives) and not (player_exploding); -- game over when aliens reach player
-- Lives counter (shown in LEDS)
with lives select
LEDG(0) <= '0' when 0 | 1,
'1' when others;
with lives select
LEDG(1) <= '0' when 0 | 1 | 2,
'1' when others;
with lives select
LEDG(2) <= '1' when 4,
'0' when others;
----------------------------------------------------------------
----------------------------------------------------------------
-- Random number generator
----------------------------------------------------------------
rnd: random_gen
generic map ( cpu_num*cpu_lines )
port map ( clk_enemy_shoot, clock_50, rnd_s);
----------------------------------------------------------------
-- Score system
----------------------------------------------------------------
show_score: score
port map(shot_r_s, reset_s, hex_s); -- shot_r_s as clock
HEX0 <= hex_s(6 downto 0);
HEX1 <= hex_s(13 downto 7);
HEX2 <= hex_s(20 downto 14);
HEX3 <= hex_s(27 downto 21);
----------------------------------------------------------------
end architecture;
|
gpl-3.0
|
arthurbenemann/fpga-bits
|
undocumented/audioDac/ipcore_dir/rom_memory/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
gpl-3.0
|
aospan/NetUP_Dual_Universal_CI-fpga
|
twi_master_0.vhd
|
1
|
5525
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- twi_master_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity twi_master_0 is
port (
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(15 downto 0); -- .readdata
byte_en : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
in_data : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
in_octet : in std_logic_vector(7 downto 0) := (others => '0'); -- avalon_streaming_sink.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_octet : out std_logic_vector(7 downto 0); -- avalon_streaming_source.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
scl_in : in std_logic := '0'; -- conduit_end.export
scl_act : out std_logic; -- .export
sda_in : in std_logic := '0'; -- .export
sda_act : out std_logic; -- .export
sink_irq : in std_logic := '0'; -- .export
source_irq : in std_logic := '0'; -- .export
irq : out std_logic -- .export
);
end entity twi_master_0;
architecture rtl of twi_master_0 is
component twi_master is
port (
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(15 downto 0); -- readdata
byte_en : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
in_octet : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_octet : out std_logic_vector(7 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
scl_in : in std_logic := 'X'; -- export
scl_act : out std_logic; -- export
sda_in : in std_logic := 'X'; -- export
sda_act : out std_logic; -- export
sink_irq : in std_logic := 'X'; -- export
source_irq : in std_logic := 'X'; -- export
irq : out std_logic -- export
);
end component twi_master;
begin
twi_master_0 : component twi_master
port map (
addr => addr, -- avalon_slave_0.address
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
byte_en => byte_en, -- .byteenable
in_data => in_data, -- .writedata
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
in_octet => in_octet, -- avalon_streaming_sink.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_octet => out_octet, -- avalon_streaming_source.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
scl_in => scl_in, -- conduit_end.export
scl_act => scl_act, -- .export
sda_in => sda_in, -- .export
sda_act => sda_act, -- .export
sink_irq => sink_irq, -- .export
source_irq => source_irq, -- .export
irq => irq -- .export
);
end architecture rtl; -- of twi_master_0
|
gpl-3.0
|
JosiCoder/CtLab
|
FPGA/SRAM_Controller/Source/ClockManager.vhd
|
2
|
3169
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Manages the clocks used throughout the system.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ClockManager is
port
(
-- The system clock.
clk: in std_logic;
-- The 50 MHz clock.
clk_50mhz: out std_logic;
-- The 100 MHz clock.
clk_100mhz: out std_logic
);
end entity;
architecture stdarch of ClockManager is
signal clk50_unbuf, clk50_buf: std_logic;
signal clk100_unbuf, clk100_buf: std_logic;
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
clk_50mhz <= clk;
clk_100mhz <= clk100_buf;
--------------------------------------------------------------------------------
-- Instantiate components.
--------------------------------------------------------------------------------
dcm_instance: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- DLL attributes
CLK_FEEDBACK => "1X",
DLL_FREQUENCY_MODE => "LOW",
CLKIN_DIVIDE_BY_2 => FALSE,
CLKDV_DIVIDE => 2.0,
DUTY_CYCLE_CORRECTION => TRUE,
-- DFS attributes
DFS_FREQUENCY_MODE => "LOW",
CLKFX_MULTIPLY => 2,
CLKFX_DIVIDE => 1
)
port map
(
RST => '0',
CLKIN => clk,
CLKFB => clk50_buf,
PSEN => '0',
PSCLK => '0',
PSINCDEC => '0',
CLK0 => clk50_unbuf,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKDV => open,
CLKFX => clk100_unbuf,
CLKFX180 => open,
LOCKED => open,
STATUS => open,
PSDONE => open
);
clk50_bufg: BUFG
port map
(
I => clk50_unbuf,
O => clk50_buf
);
clk100_bufg: BUFG
port map
(
I => clk100_unbuf,
O => clk100_buf
);
end architecture;
|
gpl-3.0
|
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