repo_name
stringlengths 6
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stringlengths 5
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stringclasses 54
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stringlengths 1
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stringlengths 0
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stringclasses 15
values |
|---|---|---|---|---|---|
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner
|
projects/VHDL_Xilinx_Port/uart.vhd
|
4
|
3858
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:16:44 05/29/2011
-- Design Name:
-- Module Name: uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart is
Port ( clk : in STD_LOGIC;
tx : out STD_LOGIC;
rx : in STD_LOGIC;
txdata : in STD_LOGIC_VECTOR (48 downto 0);
txwidth : in STD_LOGIC_VECTOR (5 downto 0);
txstrobe : in STD_LOGIC;
txbusy : out STD_LOGIC;
rxdata : out STD_LOGIC_VECTOR (7 downto 0);
rxstrobe : out STD_LOGIC);
end uart;
architecture Behavioral of uart is
signal txclk : std_logic := '0';
signal rxclk : std_logic := '0';
signal txclkdiv : std_logic_vector(10 downto 0);
signal rxclkdiv : std_logic_vector(10 downto 0);
signal txclksync : std_logic := '0';
signal rxclksync : std_logic := '0';
signal txdatabuf : std_logic_vector(48 downto 0) := "0000000000000000000000000000000000000000000000000";
signal txdataleft : std_logic_vector(5 downto 0) := "000000";
signal txbusy_src : std_logic := '0';
signal rxdata_src : std_logic_vector(7 downto 0);
signal rxbits : std_logic_vector(3 downto 0);
signal rxbusy : std_logic := '0';
signal rx1 : std_logic;
signal rx2 : std_logic;
begin
tx <= txdatabuf(0);
txclk <= '1' when txclkdiv = "00000000000" and txclksync = '0' else '0';
rxclk <= '1' when rxclkdiv = "00000000000" and rxclksync = '0' else '0';
txbusy_src <= '0' when txdataleft = "000000" else '1';
txbusy <= txbusy_src;
rxdata <= rxdata_src;
process(clk)
begin
if rising_edge(clk) then
rx1 <= rx;
rx2 <= rx1;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if txclksync = '1' or txclkdiv = "00000000000" then
txclkdiv <= "10000010001";
else
txclkdiv <= txclkdiv - 1;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rxclksync = '1' then
rxclkdiv <= "11000011001";
elsif rxclkdiv = "00000000000000" then
rxclkdiv <= "10000010001";
else
rxclkdiv <= rxclkdiv - 1;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if txstrobe = '1' and txbusy_src = '0' then
txdatabuf <= txdata;
txdataleft <= txwidth;
txclksync <= '1';
else
if txclk = '1' then
txdatabuf(47 downto 0) <= txdatabuf(48 downto 1);
txdatabuf(48) <= '1';
if txbusy_src = '1' then
txdataleft <= txdataleft - 1;
end if;
end if;
txclksync <= '0';
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rxbusy = '1' then
if rxclk = '1' then
if rxbits = "1000" then
rxbusy <= '0';
rxstrobe <= '1';
else
rxdata_src(6 downto 0) <= rxdata_src(7 downto 1);
rxdata_src(7) <= rx2;
rxbits <= rxbits + 1;
rxbusy <= '1';
rxstrobe <= '0';
end if;
end if;
rxclksync <= '0';
elsif rx2 = '0' then
rxbits <= "0000";
rxbusy <= '1';
rxclksync <= '1';
rxstrobe <= '0';
else
rxbusy <= '0';
rxclksync <= '0';
rxstrobe <= '0';
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
luccas641/Processador-ICMC
|
Processor_FPGA/Processor_Template_VHDL_DE115/MUX1.vhd
|
4
|
6693
|
-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_MUX
-- ============================================================
-- File Name: MUX1.vhd
-- Megafunction Name(s):
-- LPM_MUX
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY MUX1 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END MUX1;
ARCHITECTURE SYN OF mux1 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
sub_wire5 <= data0x(15 DOWNTO 0);
sub_wire4 <= data1x(15 DOWNTO 0);
sub_wire3 <= data2x(15 DOWNTO 0);
result <= sub_wire0(15 DOWNTO 0);
sub_wire1 <= data3x(15 DOWNTO 0);
sub_wire2(3, 0) <= sub_wire1(0);
sub_wire2(3, 1) <= sub_wire1(1);
sub_wire2(3, 2) <= sub_wire1(2);
sub_wire2(3, 3) <= sub_wire1(3);
sub_wire2(3, 4) <= sub_wire1(4);
sub_wire2(3, 5) <= sub_wire1(5);
sub_wire2(3, 6) <= sub_wire1(6);
sub_wire2(3, 7) <= sub_wire1(7);
sub_wire2(3, 8) <= sub_wire1(8);
sub_wire2(3, 9) <= sub_wire1(9);
sub_wire2(3, 10) <= sub_wire1(10);
sub_wire2(3, 11) <= sub_wire1(11);
sub_wire2(3, 12) <= sub_wire1(12);
sub_wire2(3, 13) <= sub_wire1(13);
sub_wire2(3, 14) <= sub_wire1(14);
sub_wire2(3, 15) <= sub_wire1(15);
sub_wire2(2, 0) <= sub_wire3(0);
sub_wire2(2, 1) <= sub_wire3(1);
sub_wire2(2, 2) <= sub_wire3(2);
sub_wire2(2, 3) <= sub_wire3(3);
sub_wire2(2, 4) <= sub_wire3(4);
sub_wire2(2, 5) <= sub_wire3(5);
sub_wire2(2, 6) <= sub_wire3(6);
sub_wire2(2, 7) <= sub_wire3(7);
sub_wire2(2, 8) <= sub_wire3(8);
sub_wire2(2, 9) <= sub_wire3(9);
sub_wire2(2, 10) <= sub_wire3(10);
sub_wire2(2, 11) <= sub_wire3(11);
sub_wire2(2, 12) <= sub_wire3(12);
sub_wire2(2, 13) <= sub_wire3(13);
sub_wire2(2, 14) <= sub_wire3(14);
sub_wire2(2, 15) <= sub_wire3(15);
sub_wire2(1, 0) <= sub_wire4(0);
sub_wire2(1, 1) <= sub_wire4(1);
sub_wire2(1, 2) <= sub_wire4(2);
sub_wire2(1, 3) <= sub_wire4(3);
sub_wire2(1, 4) <= sub_wire4(4);
sub_wire2(1, 5) <= sub_wire4(5);
sub_wire2(1, 6) <= sub_wire4(6);
sub_wire2(1, 7) <= sub_wire4(7);
sub_wire2(1, 8) <= sub_wire4(8);
sub_wire2(1, 9) <= sub_wire4(9);
sub_wire2(1, 10) <= sub_wire4(10);
sub_wire2(1, 11) <= sub_wire4(11);
sub_wire2(1, 12) <= sub_wire4(12);
sub_wire2(1, 13) <= sub_wire4(13);
sub_wire2(1, 14) <= sub_wire4(14);
sub_wire2(1, 15) <= sub_wire4(15);
sub_wire2(0, 0) <= sub_wire5(0);
sub_wire2(0, 1) <= sub_wire5(1);
sub_wire2(0, 2) <= sub_wire5(2);
sub_wire2(0, 3) <= sub_wire5(3);
sub_wire2(0, 4) <= sub_wire5(4);
sub_wire2(0, 5) <= sub_wire5(5);
sub_wire2(0, 6) <= sub_wire5(6);
sub_wire2(0, 7) <= sub_wire5(7);
sub_wire2(0, 8) <= sub_wire5(8);
sub_wire2(0, 9) <= sub_wire5(9);
sub_wire2(0, 10) <= sub_wire5(10);
sub_wire2(0, 11) <= sub_wire5(11);
sub_wire2(0, 12) <= sub_wire5(12);
sub_wire2(0, 13) <= sub_wire5(13);
sub_wire2(0, 14) <= sub_wire5(14);
sub_wire2(0, 15) <= sub_wire5(15);
LPM_MUX_component : LPM_MUX
GENERIC MAP (
lpm_size => 4,
lpm_type => "LPM_MUX",
lpm_width => 16,
lpm_widths => 2
)
PORT MAP (
data => sub_wire2,
sel => sel,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL "data0x[15..0]"
-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL "data1x[15..0]"
-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL "data2x[15..0]"
-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL "data3x[15..0]"
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL MUX1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
gpl-3.0
|
freecores/usb_fpga_2_13
|
examples/usb-fpga-2.16/2.16b/lightshow/fpga/lightshow.vhd
|
17
|
3116
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led1 : out std_logic_vector(9 downto 0); -- LED1 on debug board
led2 : out std_logic_vector(19 downto 0); -- LED2 + LED3 on debug board
sw : in std_logic_vector(3 downto 0);
fxclk : in std_logic
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern1 is array(9 downto 0) of integer range 0 to 255;
type tPattern2 is array(19 downto 0) of integer range 0 to 255;
signal pattern1 : tPattern1 := (0, 10, 41, 92, 163, 255, 163, 92, 41, 10); -- pattern for LED1
signal pattern20 : tPattern2 := (0, 1, 2, 9, 16, 25, 36, 49, 64, 81, 64, 49, 36, 25, 16, 9, 2, 1, 0, 0); -- 1st pattern for LED2
signal pattern21 : tPattern2 := (0, 19, 77, 174, 77, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); -- 2nd pattern for LED2
signal pattern2 : tPattern2; -- pattern20 + pattern21
signal cnt1,cnt20, cnt21 : std_logic_vector(22 downto 0);
signal pwm_cnt : std_logic_vector(19 downto 0);
signal pwm_cnt8 : std_logic_vector(7 downto 0);
begin
pwm_cnt8 <= pwm_cnt(19 downto 12);
dp_fxclk: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
-- pattern for led 1
if ( cnt1 >= conv_std_logic_vector(7200000,23) ) -- 1/1.5 Hz
then
if ( sw(0) = '1' )
then
pattern1(8 downto 0) <= pattern1(9 downto 1);
pattern1(9) <= pattern1(0);
else
pattern1(9 downto 1) <= pattern1(8 downto 0);
pattern1(0) <= pattern1(9);
end if;
cnt1 <= (others => '0');
else
cnt1 <= cnt1 + 1;
end if;
-- pattern for led 2
if ( ( cnt20 >= conv_std_logic_vector(4800000,23) ) or ( (sw(2)= '1') and (cnt20 >= conv_std_logic_vector(1600000,23)) ) ) -- SW1 off: 1/3Hz, SW1 on: 1Hz
then
pattern20(18 downto 0) <= pattern20(19 downto 1);
pattern20(19) <= pattern20(0);
cnt20 <= (others => '0');
else
cnt20 <= cnt20 + 1;
end if;
if ( ( cnt21 >= conv_std_logic_vector(2000000,23) ) or ( (sw(3)= '1') and (cnt21 >= conv_std_logic_vector(500000,23)) ) )
then
if ( sw(1) = '1' )
then
pattern21(18 downto 0) <= pattern21(19 downto 1);
pattern21(19) <= pattern21(0);
else
pattern21(19 downto 1) <= pattern21(18 downto 0);
pattern21(0) <= pattern21(19);
end if;
cnt21 <= (others => '0');
else
cnt21 <= cnt21 + 1;
end if;
for i in 0 to 19 loop
pattern2(i) <= pattern20(i) + pattern21(i);
end loop;
-- pwm
if ( pwm_cnt8 = conv_std_logic_vector(255,8) )
then
pwm_cnt <= ( others => '0' );
else
pwm_cnt <= pwm_cnt + 1;
end if;
-- led1
for i in 0 to 9 loop
if ( pwm_cnt8 < pattern1(i) )
then
led1(i) <= '1';
else
led1(i) <= '0';
end if;
end loop;
for i in 0 to 19 loop
if (pwm_cnt8 < pattern2(i) )
then
led2(i) <= '1';
else
led2(i) <= '0';
end if;
end loop;
end if;
end process dp_fxclk;
end RTL;
|
gpl-3.0
|
freecores/usb_fpga_2_13
|
examples/usb-fpga-2.13/2.13d/ucecho/fpga/ucecho.vhd
|
7
|
636
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
pd : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
fxclk : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
pb <= pb_buf;
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if ( pd >= 97 ) and ( pd <= 122)
then
pb_buf <= pd - 32;
else
pb_buf <= pd;
end if;
end if;
end process dpUCECHO;
end RTL;
|
gpl-3.0
|
da-steve101/binary_connect_cifar
|
src/main/vhdl/ternary_adder_xilinx.vhd
|
1
|
17993
|
---------------------------------------------------------------------------------------------
-- Author: Jens Willkomm, Martin Kumm
-- Contact: [email protected], [email protected]
-- License: LGPL
-- Date: 15.03.2013
-- Compatibility: Xilinx FPGAs of Virtex 5-7, Spartan 6 and Series 7 architectures
--
-- Description:
-- Low level implementation of a ternary adder according to U.S. Patent No 7274211
-- from Xilinx, which uses the same no of slices than a two input adder.
-- The output coresponds to sum_o = x_i + y_i + z_i, where the inputs have a word size of
-- 'input_word_size' while the output has a word size of input_word_size+2.
--
-- Flipflops at the outputs can be activated by setting 'use_output_ff' to true.
-- Signed operation is activated by using the 'is_signed' generic.
-- The inputs y_i and z_i can be negated by setting 'subtract_y' or 'subtract_z'
-- to realize sum_o = x_i +/- y_i +/- z_i. The negation requires no extra resources.
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ternary_add_sub_prim is
generic(
input_word_size : integer := 10;
subtract_y : boolean := false;
subtract_z : boolean := false;
use_output_ff : boolean := true;
is_signed : boolean := true
);
port(
clk_i : in std_logic;
x_i : in std_logic_vector((input_word_size - 1) downto 0);
y_i : in std_logic_vector((input_word_size - 1) downto 0);
z_i : in std_logic_vector((input_word_size - 1) downto 0);
sum_o : out std_logic_vector((input_word_size + 1) downto 0)
);
end entity;
architecture behavior of ternary_add_sub_prim is
-- this function calculates the initial carry bit for the bbus
function bbus_init
return std_logic is
variable result : std_logic;
begin
result := '0';
if subtract_y or subtract_z then
result := '1';
end if;
return result;
end function;
-- this function calculates the initial carry bit for the carry chain
function cc_init
return std_logic is
variable result : std_logic;
begin
result := '0';
if subtract_y and subtract_z then
result := '1';
end if;
return result;
end function;
component slice_setup
generic(
input_word_size : integer := 4;
use_output_ff : boolean := false;
is_initial_slice : boolean := true;
subtract_y : boolean := false;
subtract_z : boolean := false
);
port(
-- signals for a synchronous circuit
clock : in std_logic;
clock_enable : in std_logic;
clear : in std_logic;
-- the three addends
x_in : in std_logic_vector((input_word_size - 1) downto 0);
y_in : in std_logic_vector((input_word_size - 1) downto 0);
z_in : in std_logic_vector((input_word_size - 1) downto 0);
-- the upper entity is mapping the bbus correctly
-- in initial slice bbus(0) ^= sub / ~add
bbus_in : in std_logic_vector((input_word_size - 1) downto 0);
bbus_out : out std_logic_vector((input_word_size - 1) downto 0);
-- both carrys are for and from the carry chain
-- in the initial slice use carry_in <= '0' always
-- sub/add is done by the bbus(0) from the initial slice
carry_in : in std_logic;
carry_out : out std_logic;
-- the sum of the three addends (x_in + y_in + z_in)
sum_out : out std_logic_vector((input_word_size - 1) downto 0)
);
end component;
-- calculate the needed number of slices
constant num_slices : integer := ((input_word_size + 1) / 4) + 1;
-- defines the initial carry values
-- in the pure addition mode both constants are '0'
-- if one of the input signal is subtracted the carry_bbus is '1'
-- if two input signal are subtracted both constants are '1'
constant carry_bbus : std_logic := bbus_init;
constant carry_cc : std_logic := cc_init;
-- the input addends with sign extention
signal x : std_logic_vector((input_word_size + 1) downto 0);
signal y : std_logic_vector((input_word_size + 1) downto 0);
signal z : std_logic_vector((input_word_size + 1) downto 0);
-- the bbus that is routed around the slice
-- this bbus differs from the one in the xilinx paper,
-- per position the input is bbus(n) and the output is bbus(n + 1)
-- this is because of the sub/~add, which is bbus(0) and all the other
-- bbus signals are scrolled one position up
signal bbus : std_logic_vector(input_word_size + 2 downto 0);
-- the carry from every slice to the next one
-- the last slice gives the carry output for the adder
-- carry(n) is the carry of the carry chain of slice n
signal carry : std_logic_vector((num_slices - 1) downto 0);
begin
-- checking the parameter input_word_size
assert (input_word_size > 0) report "an adder with a bit width of "
& integer'image(input_word_size) & " is not possible." severity failure;
-- adding two bit sign extention to the input addends
extention_signed: if is_signed = true generate
x <= x_i(input_word_size - 1) & x_i(input_word_size - 1) & x_i;
y <= y_i(input_word_size - 1) & y_i(input_word_size - 1) & y_i;
z <= z_i(input_word_size - 1) & z_i(input_word_size - 1) & z_i;
end generate;
extention_unsigned: if is_signed = false generate
x <= '0' & '0' & x_i;
y <= '0' & '0' & y_i;
z <= '0' & '0' & z_i;
end generate;
-- the initial bbus carry signal
bbus(0) <= carry_bbus;
-- generating the slice setups
-- getting all signals into one slice
single_slice: if num_slices = 1 generate
slice_i: slice_setup
generic map(
input_word_size => input_word_size + 2,
use_output_ff => use_output_ff,
is_initial_slice => true,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => 0,
x_in => x,
y_in => y,
z_in => z,
bbus_in => bbus(input_word_size + 1 downto 0),
-- scrolling bbus_out one position up
bbus_out => bbus(input_word_size + 2 downto 1),
carry_in => carry_cc,
carry_out => carry(0),
sum_out => sum_o(input_word_size + 1 downto 0)
);
end generate;
-- make more slices to calculate all signals
multiple_slices: if num_slices > 1 generate
slices: for i in 0 to (num_slices - 1) generate
-- generate the first slice
first_slice: if i = 0 generate
slice_i: slice_setup
generic map(
input_word_size => 4,
use_output_ff => use_output_ff,
is_initial_slice => true,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => 0,
x_in => x(3 downto 0),
y_in => y(3 downto 0),
z_in => z(3 downto 0),
bbus_in => bbus(3 downto 0),
-- scrolling bbus_out one position upwards
bbus_out => bbus(4 downto 1),
carry_in => carry_cc,
carry_out => carry(0),
sum_out => sum_o(3 downto 0)
);
end generate;
-- generate all full slices
full_slice: if i > 0 and i < (num_slices - 1) generate
slice_i: slice_setup
generic map(
input_word_size => 4,
use_output_ff => use_output_ff,
is_initial_slice => false,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => 0,
x_in => x((4 * i) + 3 downto 4 * i),
y_in => y((4 * i) + 3 downto 4 * i),
z_in => z((4 * i) + 3 downto 4 * i),
bbus_in => bbus((4 * i) + 3 downto 4 * i),
-- scrolling bbus_out one position upwards
bbus_out => bbus((4 * i) + 4 downto (4 * i) + 1),
carry_in => carry(i - 1),
carry_out => carry(i),
sum_out => sum_o((4 * i) + 3 downto 4 * i)
);
end generate;
-- generate the last slice
last_slice: if i = (num_slices - 1) generate
slice_i: slice_setup
generic map(
input_word_size => (input_word_size + 2) - (i * 4),
use_output_ff => use_output_ff,
is_initial_slice => false,
subtract_y => subtract_y,
subtract_z => subtract_z
)
port map(
clock => clk_i,
clock_enable => '1',
clear => 0,
x_in => x(input_word_size + 1 downto 4 * i),
y_in => y(input_word_size + 1 downto 4 * i),
z_in => z(input_word_size + 1 downto 4 * i),
bbus_in => bbus(input_word_size + 1 downto 4 * i),
-- scrolling bbus_out one position up
bbus_out => bbus(input_word_size + 2 downto (4 * i) + 1),
carry_in => carry(i - 1),
carry_out => carry(i),
sum_out => sum_o(input_word_size + 1 downto 4 * i)
);
end generate;
end generate;
end generate;
end architecture;
--- Definition of the slice_setup component which configures a single slice ---
library unisim;
use unisim.vcomponents.all; -- loading xilinx primitives
library ieee;
use ieee.std_logic_1164.all; -- loading std_logic & std_logic_vector
entity slice_setup is
generic(
input_word_size : integer := 4;
use_output_ff : boolean := false;
is_initial_slice : boolean := true;
subtract_y : boolean := false;
subtract_z : boolean := false
);
port(
-- signals for a synchronous circuit
clock : in std_logic;
clock_enable : in std_logic;
clear : in std_logic;
-- the three addends
x_in : in std_logic_vector((input_word_size - 1) downto 0);
y_in : in std_logic_vector((input_word_size - 1) downto 0);
z_in : in std_logic_vector((input_word_size - 1) downto 0);
-- the upper entity is mapping the bbus correctly
-- in initial slice bbus(0) ^= sub / ~add
bbus_in : in std_logic_vector((input_word_size - 1) downto 0);
bbus_out : out std_logic_vector((input_word_size - 1) downto 0);
-- both carrys are for and from the carry chain
-- in the initial slice use carry_in <= '0' always
-- sub/add is done by the bbus(0) from the initial slice
carry_in : in std_logic;
carry_out : out std_logic;
-- the sum of the three addends (x_in + y_in + z_in)
sum_out : out std_logic_vector((input_word_size - 1) downto 0)
);
end entity;
architecture behavior of slice_setup is
-- this function returns the lut initialization
function get_lut_init
return bit_vector is
-- defines several lut configurations
-- for init calculation see "initializing_primitives.ods"
constant lut_init_no_sub : bit_vector(63 downto 0) := x"3cc3c33cfcc0fcc0";
constant lut_init_sub_y : bit_vector(63 downto 0) := x"c33c3cc3cf0ccf0c";
constant lut_init_sub_z : bit_vector(63 downto 0) := x"c33c3cc3f330f330";
constant lut_init_sub_yz : bit_vector(63 downto 0) := x"3cc3c33c3f033f03";
variable curr_lut : bit_vector(63 downto 0) := lut_init_no_sub;
begin
curr_lut := lut_init_no_sub;
if subtract_y then
curr_lut := lut_init_sub_y;
end if;
if subtract_z then
curr_lut := lut_init_sub_z;
end if;
if subtract_y and subtract_z then
curr_lut := lut_init_sub_yz;
end if;
return curr_lut;
end function;
-- calculate how many bits to fill up with zeros for the carry chain
constant fillup_width : integer := 4 - input_word_size;
-- holds the lut configuration used in this slice
constant current_lut_init : bit_vector := get_lut_init;
-- output o6 of the luts
signal lut_o6 : std_logic_vector((input_word_size - 1) downto 0);
-- the signals for and from the carry chain have to be wrapped into signals
-- with a width of four, to fill them up with zeros and prevent synthesis
-- warnings when doing this in the port map of the carry chain
-- input di of the carry chain (have to be four bits width)
signal cc_di : std_logic_vector(3 downto 0);
-- input s of the carry chain (have to be four bits width)
signal cc_s : std_logic_vector(3 downto 0);
-- output o of the carry chain (have to be four bits width)
signal cc_o : std_logic_vector(3 downto 0);
-- output co of the carry chain (have to be four bits width)
signal cc_co : std_logic_vector(3 downto 0);
begin
-- check the generic parameter
assert (input_word_size > 0 and input_word_size < 5) report "a slice with a bit width of "
& integer'image(input_word_size) & " is not possible." severity failure;
-- prepairing singals for the carry chain
full_slice_assignment: if input_word_size = 4 generate
cc_di <= bbus_in;
cc_s <= lut_o6;
end generate;
last_slice_assignment: if input_word_size < 4 generate
cc_di <= (fillup_width downto 1 => '0') & bbus_in;
cc_s <= (fillup_width downto 1 => '0') & lut_o6;
end generate;
-- creating the lookup tables
luts: for i in 0 to (input_word_size - 1) generate
-- lut6_2 primitive is described in virtex 6 user guide on page 215:
-- http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/virtex6_hdl.pdf
lut_bit_i: lut6_2
generic map(
init => current_lut_init
)
-------------------------------------------------------------------
-- table of names and connections
-- user guide us 7,274,211 usage in adder
-- ---------- ------------ --------------
-- i0 in1 gnd
-- i1 in2 z(n)
-- i2 in3 y(n)
-- i3 in4 x(n)
-- i4 in5 bbus(n-1)
-- i5 in6 vdd
-- o5 o5
-- o6 o6
-------------------------------------------------------------------
port map(
i0 => '0',
i1 => z_in(i),
i2 => y_in(i),
i3 => x_in(i),
i4 => bbus_in(i),
i5 => '1',
o5 => bbus_out(i),
o6 => lut_o6(i)
);
end generate;
-- creating the carry chain
-- carry4 primitive is described in virtex 6 user guide on page 108:
-- http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/virtex6_hdl.pdf
initial_slice: if is_initial_slice = true generate
init_cc: carry4
-------------------------------------------------------------------
-- table of names and connections
-- user guide usage in adder
-- ---------- --------------
-- co msb is carry out, rest is not connected
-- o sum
-- ci in the initial slice: not connected
-- cyinit in the initial slice: add / ~sub
-- di bbus(n-1)
-- s lut_o6(n)
-------------------------------------------------------------------
port map(
co => cc_co,
o => cc_o,
cyinit => '0',
ci => carry_in,
di => cc_di,
s => cc_s
);
end generate;
further_slice: if is_initial_slice = false generate
further_cc: carry4
-------------------------------------------------------------------
-- table of names and connections
-- user guide usage in adder
-- ---------- --------------
-- co msb is carry out, rest is not connected
-- o sum
-- ci carry from previous slice
-- cyinit in further slices: not connected
-- di bbus(n-1)
-- s lut_o6(n)
-------------------------------------------------------------------
port map(
co => cc_co,
o => cc_o,
cyinit => '0',
ci => carry_in,
di => cc_di,
s => cc_s
);
end generate;
-- connect the last used output of the carry chain to the slice output
carry_out <= cc_co(input_word_size - 1);
-- creating the flip flops
sum_register: if use_output_ff = true generate
ffs: for i in 0 to (input_word_size - 1) generate
ff_i: fdce
generic map(
-- initialize all flip flops with '0'
init => '0'
)
-------------------------------------------------------------------
-- table of names and connections
-- user guide usage in adder
-- ---------- --------------
-- clr clear
-- ce clock_enable, always '1'
-- d cc_o
-- c clock
-- q sum(n)
-------------------------------------------------------------------
port map(
clr => clear,
ce => clock_enable,
d => cc_o(i),
c => clock,
q => sum_out(i)
);
end generate;
end generate;
-- bypassing the flip flops in case of a asynchronous circuit
bypass: if use_output_ff = false generate
sum_out <= cc_o(input_word_size - 1 downto 0);
end generate;
end architecture;
|
gpl-3.0
|
hacklabmikkeli/knobs-galore
|
phase_distort.vhdl
|
2
|
6530
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity phase_distort is
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;WAVEFORM: in waveform_t
;CUTOFF: in ctl_signal
;THETA_IN: in ctl_signal
;THETA_OUT: out ctl_signal
;GAIN_IN: in ctl_signal
;GAIN_THRU: out ctl_signal
)
;
end entity;
architecture phase_distort_impl of phase_distort is
function transfer_saw
(cutoff: integer
;x: integer
)
return integer is
variable log_cutoff : integer;
variable y0 : integer;
variable y : integer;
variable k : integer;
begin
log_cutoff := integer(log2(real(cutoff+1)) * 32.0);
if log_cutoff > 255 then
log_cutoff := 255;
end if;
k := (ctl_max - log_cutoff) / 2;
y0 := (ctl_max / 2) - k;
if x < k then
y := (x * y0) / k;
else
y := y0 - ((x-k) * y0) / (ctl_max - k);
end if;
y := y + x;
if y > ctl_max - 1 then
return ctl_max - 1;
else
return y;
end if;
end function;
function transfer_sq
(cutoff: integer
;x: integer
)
return integer is
variable log_cutoff : integer;
variable k : integer;
variable y0 : integer;
variable y : integer;
begin
log_cutoff := integer(log2(real(cutoff+1)) * 32.0);
if log_cutoff > 255 then
log_cutoff := 255;
end if;
k := (ctl_max - log_cutoff) / 4;
y0 := ctl_max / 4;
if x < k then
y := (x * y0) / k;
elsif x < (ctl_max / 2) - k then
y := y0;
elsif x < (ctl_max / 2) + k then
y := y0 + (x + k - (ctl_max / 2)) * y0 / k;
elsif x < ctl_max - k then
y := (ctl_max / 2) + y0;
else
y := (ctl_max / 2) + y0 + (x + k - ctl_max) * y0 / k;
end if;
if y > ctl_max - 1 then
return ctl_max - 1;
else
return y;
end if;
end function;
function make_lut_saw return ctl_lut_t is
variable result : ctl_lut_t;
begin
for j in ctl_lut_t'low(1) to ctl_lut_t'high(1) loop
for i in ctl_lut_t'low(2) to ctl_lut_t'high(2) loop
result(j,i) := to_unsigned(transfer_saw(i*16, j),ctl_bits);
end loop;
end loop;
return result;
end function;
function make_lut_sq return ctl_lut_t is
variable result : ctl_lut_t;
begin
for j in ctl_lut_t'low(1) to ctl_lut_t'high(1) loop
for i in ctl_lut_t'low(2) to ctl_lut_t'high(2) loop
result(j,i) := to_unsigned(transfer_sq(i*16, j),ctl_bits);
end loop;
end loop;
return result;
end function;
constant lut_saw: ctl_lut_t := make_lut_saw;
constant lut_sq: ctl_lut_t := make_lut_sq;
constant zero: ctl_signal := (others => '0');
signal s1_waveform: waveform_t := waveform_saw;
signal s1_gain: ctl_signal := (others => '0');
signal s2_waveform: waveform_t := waveform_saw;
signal s2_gain: ctl_signal := (others => '0');
signal s3_waveform: waveform_t := waveform_saw;
signal s3_theta_saw: ctl_signal;
signal s3_theta_sq: ctl_signal;
signal s3_gain: ctl_signal := (others => '0');
signal s4_theta_out_buf: ctl_signal := (others => '0');
signal s4_gain_pass_buf: ctl_signal := (others => '0');
signal s5_theta_out_buf: ctl_signal := (others => '0');
signal s5_gain_pass_buf: ctl_signal := (others => '0');
begin
lookup_saw:
entity
work.lookup(lookup_impl)
generic map
(lut_saw)
port map
(EN
,CLK_EVEN
,CLK_ODD
,THETA_IN
,CUTOFF
,s3_theta_saw
);
lookup_sq:
entity
work.lookup(lookup_impl)
generic map
(lut_sq)
port map
(EN
,CLK_EVEN
,CLK_ODD
,THETA_IN
,CUTOFF
,s3_theta_sq
);
process (CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s1_waveform <= WAVEFORM;
s1_gain <= GAIN_IN;
end if;
end process;
process (CLK_ODD)
begin
if EN = '1' and rising_edge(CLK_ODD) then
s2_waveform <= s1_waveform;
s2_gain <= s1_gain;
end if;
end process;
process (CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s3_waveform <= s2_waveform;
s3_gain <= s2_gain;
end if;
end process;
process (CLK_ODD)
begin
if EN = '1' and rising_edge(CLK_ODD) then
case s3_waveform is
when waveform_saw =>
s4_theta_out_buf <= s3_theta_saw;
when waveform_sq =>
s4_theta_out_buf <= s3_theta_sq;
when others =>
s4_theta_out_buf <= (others => '0');
end case;
s4_gain_pass_buf <= s3_gain;
end if;
end process;
process (CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s5_theta_out_buf <= s4_theta_out_buf;
s5_gain_pass_buf <= s4_gain_pass_buf;
end if;
end process;
THETA_OUT <= s5_theta_out_buf;
GAIN_THRU <= s5_gain_pass_buf;
end architecture;
|
gpl-3.0
|
hacklabmikkeli/knobs-galore
|
circular_buffer_test.vhdl
|
2
|
1026
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity circular_buffer_test is
end entity;
architecture circular_buffer_test_impl of circular_buffer_test is
begin
end architecture;
|
gpl-3.0
|
hacklabmikkeli/knobs-galore
|
phase_gen.vhdl
|
2
|
1411
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity phase_gen is
port (EN: in std_logic
;CLK: in std_logic
;PHASE_IN: in time_signal
;PHASE_OUT: out time_signal
)
;
end entity;
architecture phase_gen_impl of phase_gen is
signal s1_phase_out_buf: time_signal := (others => '0');
begin
process(CLK)
begin
if EN = '1' and rising_edge(CLK) then
s1_phase_out_buf <= PHASE_IN + 1;
end if;
end process;
PHASE_OUT <= s1_phase_out_buf;
end architecture;
|
gpl-3.0
|
freecores/usb_fpga_2_13
|
examples/usb-fpga-1.15/1.15a/intraffic/fpga/intraffic.vhd
|
42
|
1939
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity intraffic is
port(
RESET : in std_logic;
CONT : in std_logic;
IFCLK : in std_logic;
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic
);
end intraffic;
architecture RTL of intraffic is
----------------------------
-- test pattern generator --
----------------------------
-- 30 bit counter
signal GEN_CNT : std_logic_vector(29 downto 0);
signal INT_CNT : std_logic_vector(6 downto 0);
signal FIFO_WORD : std_logic;
begin
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1'; -- no data alignment
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
INT_CNT <= ( others => '0' );
FIFO_WORD <= '0';
SLWR <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
if CONT = '1' or FLAGB = '1'
then
if FIFO_WORD = '0'
then
FD(14 downto 0) <= GEN_CNT(14 downto 0);
else
FD(14 downto 0) <= GEN_CNT(29 downto 15);
end if;
FD(15) <= FIFO_WORD;
if FIFO_WORD = '1'
then
GEN_CNT <= GEN_CNT + '1';
if INT_CNT = conv_std_logic_vector(99,7)
then
INT_CNT <= ( others => '0' );
else
INT_CNT <= INT_CNT + '1';
end if;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
if ( INT_CNT >= conv_std_logic_vector(90,7) ) and ( CONT = '0' )
then
SLWR <= '1';
else
SLWR <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
|
gpl-3.0
|
willprice/vhdl-computer
|
src/test/mux_2to1_tb.vhd
|
1
|
949
|
--------------------------------------------------------------------------------
-- @file mux_2to1_tb.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity mux_2to1_tb is
end;
architecture testbench of mux_2to1_tb is
-- DUT COMPONENT DECLARATION
component mux_2to1 is
generic (
PORT_WIDTH : in integer := 1
);
port(
input_0 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
input_1 : in std_logic_vector(PORT_WIDTH - 1 downto 0);
sel : in std_logic;
output : out std_logic_vector(PORT_WIDTH - 1 downto 0)
);
end component mux_2to1;
-- SIGNALS FOR DUT I/O GO HERE
begin
-- DUT INSTANCE GOES HERE
stimulus: process
begin
-- Put initialisation code here
-- Put test bench stimulus code here
wait;
end process;
end;
|
gpl-3.0
|
freecores/usb_fpga_2_13
|
examples/usb-fpga-1.11/1.11a/memtest/fpga/memtest.vhd
|
16
|
23751
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
PA3 : in std_logic;
-- errors ...
PC : out std_logic_vector(7 downto 0);
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component dcm0
port (
-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic;
CLK_VALID : out std_logic
);
end component;
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
inst_dcm0 : dcm0 port map(
-- Clock in ports
CLK_IN1 => FXCLK,
-- Clock out ports
CLK_OUT1 => MEM_CLK,
CLK_OUT2 => CLK,
-- Status and control signals
RESET => RESET_IN,
LOCKED => DCM0_LOCKED,
CLK_VALID => DCM0_CLK_VALID
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
PC(0) <= WR_UNDERRUN(0) or WR_UNDERRUN(1) or WR_UNDERRUN(2);
PC(1) <= WR_ERROR(0) or WR_ERROR(1) or WR_ERROR(2);
PC(2) <= RD_OVERFLOW(0) or RD_OVERFLOW(1) or RD_OVERFLOW(2);
PC(3) <= RD_ERROR(0) or RD_ERROR(1) or RD_ERROR(2);
PC(4) <= C3_CALIB_DONE;
PC(5) <= C3_RST0;
PC(6) <= RESET0;
PC(7) <= RESET;
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,18);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(25 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PA3 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,18);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(25 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
|
gpl-3.0
|
freecores/usb_fpga_2_13
|
examples/usb-fpga-1.11/1.11c/ucecho/fpga/ucecho.vhd
|
42
|
580
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
gpl-3.0
|
willprice/vhdl-computer
|
src/common_types.vhd
|
1
|
205
|
--
-- This is the common package file.
-- All common types, constants etc go in here.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
package common_types is
end package;
|
gpl-3.0
|
willprice/vhdl-computer
|
src/test/ff_dtype_tb.vhd
|
1
|
1686
|
--------------------------------------------------------------------------------
-- @file ff_dtype_tb.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ff_dtype_tb is
end entity ff_dtype_tb;
architecture testbench of ff_dtype_tb is
component ff_dtype is
port(
clk : in std_logic;
data : in std_logic;
reset : in std_logic;
q : buffer std_logic;
not_q : buffer std_logic
);
end component ff_dtype;
signal sig_q : std_logic := '0';
signal sig_not_q : std_logic := '1';
signal sig_clk : std_logic := '0';
signal sig_data : std_logic := '0';
signal sig_reset : std_logic := '1';
begin
sig_clk <= not sig_clk after 20 ns;
sig_reset <= '0' after 5 ns;
sig_data <= not sig_data after 13 ns;
DUT : ff_dtype port map(
q => sig_q,
not_q => sig_not_q,
clk => sig_clk,
data => sig_data,
reset => sig_reset
);
test_q_is_low_under_reset: process
begin
wait until rising_edge(sig_reset);
assert (sig_q = '0') report "Q is not zero under reset conditions" severity error;
end process;
test_q_is_equal_to_data: process
begin
wait until sig_clk'event and sig_reset='0';
wait for 1 ps;
assert (sig_data = sig_q) report "Q is not equal to sig_data." severity error;
end process;
test_q_never_equals_not_q: process(sig_q, sig_not_q)
begin
if(sig_reset = '0') then
assert (sig_q /= sig_not_q) report "Q and Q_BAR are equal." severity error;
end if;
end process;
end architecture testbench;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Segmentado/Decode.vhd
|
1
|
7067
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:32:44 11/09/2017
-- Design Name:
-- Module Name: Decode - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decode is
Port ( Instruction : in STD_LOGIC_VECTOR (31 downto 0);
posicionin : in STD_LOGIC_VECTOR (31 downto 0);
Regtomemin : in STD_LOGIC_VECTOR (31 downto 0);
cwpin : in STD_LOGIC;
iccin : in STD_LOGIC_VECTOR (3 downto 0);
Resetext : in STD_LOGIC;
ncwpout : out STD_LOGIC;
callout : out STD_LOGIC_VECTOR (31 downto 0);
ifout : out STD_LOGIC_VECTOR (31 downto 0);
rfsourceout : out STD_LOGIC_VECTOR (1 downto 0);
wrenmen : out STD_LOGIC;
RD : in STD_LOGIC_VECTOR (5 downto 0);
RDout : out STD_LOGIC_VECTOR (5 downto 0);
pcsource : out STD_LOGIC_VECTOR (1 downto 0);
Cuentrada : out STD_LOGIC_VECTOR (1 downto 0);
aluop : out STD_LOGIC_VECTOR (5 downto 0);
a18 : out STD_LOGIC_VECTOR (31 downto 0);
crs1out : out STD_LOGIC_VECTOR (31 downto 0);
op2out : out STD_LOGIC_VECTOR (31 downto 0));
end Decode;
architecture Behavioral of Decode is
COMPONENT Sumador32bit
PORT(
Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Result : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT UnidadControl
PORT(
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
op2 : in STD_LOGIC_VECTOR (2 downto 0);
cond : in STD_LOGIC_VECTOR (3 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
Reset : in STD_LOGIC;
rfDest : out STD_LOGIC;
rfSource : out STD_LOGIC_VECTOR (1 downto 0);
wrEnMem : out STD_LOGIC;
wrEnRF : out STD_LOGIC;
pcSource : out STD_LOGIC_VECTOR (1 downto 0);
AluOp : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT SEU
PORT(
Instruction : in STD_LOGIC_VECTOR (31 downto 0);
OUTSEU : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MUX32
PORT(
SEUIMM : in STD_LOGIC_VECTOR (31 downto 0);
CRS2 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : out STD_LOGIC_VECTOR (31 downto 0);
Instruction : in STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT RF
PORT(
rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
wre : in STD_LOGIC;
cRd : out STD_LOGIC_VECTOR (31 downto 0);
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT MuxRF
PORT(
Rd : in STD_LOGIC_VECTOR (5 downto 0);
O7 : in STD_LOGIC_VECTOR (5 downto 0);
RFDEST : in STD_LOGIC;
nRD : out STD_LOGIC_VECTOR (5 downto 0)
);
END COMPONENT;
COMPONENT Windowsmanager
PORT(
cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0')
);
END COMPONENT;
COMPONENT SEU_22
PORT(
Imm_22 : in STD_LOGIC_VECTOR (21 downto 0);
Imm_32 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT SEU_30
PORT(
Imm_30 : in STD_LOGIC_VECTOR (29 downto 0);
Imm_32 : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
signal a10,a20,a21,a31: std_logic_vector(31 downto 0);
--nrs1,
signal a8,a9,a26,a27: std_logic_vector(5 downto 0);
signal a1: std_logic_vector(1 downto 0);
signal a11,a12: STD_LOGIC;
begin
ints_windowsmanager: Windowsmanager PORT MAP(
cwp =>cwpin,
rs1 =>Instruction(18 downto 14),
rs2 =>Instruction(4 downto 0),
rd =>Instruction(29 downto 25),
op =>Instruction(31 downto 30),
op3 =>Instruction(24 downto 19),
cwpout=> ncwpout,
rs1out=>a9,
rs2out=> a26,
rdout=> a8
);
ints_rf: RF PORT MAP(
rs1 => a9,
rs2 => a26,
rd => RD,
dwr => Regtomemin,
rst => Resetext,
wre => a11,
cRd => a18,
crs1 => crs1out,
crs2 => a20
);
ints_muxrf: MuxRF PORT MAP(
Rd => a8,
O7 => "001111",
RFDEST => a12,
nRD => a27
);
RDout <=a27;
ints_CU: UnidadControl PORT MAP(
op =>Instruction(31 downto 30),
op3 =>Instruction(24 downto 19),
op2 =>Instruction(24 downto 22),
cond =>Instruction(28 downto 25),
icc =>iccin,
Reset =>Resetext,
rfDest =>a12,
rfSource =>rfsourceout,
wrEnMem =>wrenmen,
wrEnRF =>a11,
pcSource =>a1,
AluOp =>aluop
);
Cuentrada<=a1;
pcsource<=a1;
ints_seu: SEU PORT MAP(
Instruction =>Instruction,
OUTSEU =>a21
);
ints_mux32: MUX32 PORT MAP(
SEUIMM => a21,
CRS2 => a20,
OPER2 => op2out,
Instruction => Instruction
);
ints_seu22: SEU_22 PORT MAP(
Imm_22 => Instruction(21 downto 0),
Imm_32 => a10
);
ints_sumdisp22: Sumador32bit PORT MAP(
Oper1 => a10,
Reset => Resetext,
Oper2 => posicionin,
Result => ifout
);
ints_seu30: SEU_30 PORT MAP(
Imm_30 => Instruction(29 downto 0),
Imm_32 => a31
);
ints_sumdisp30: Sumador32bit PORT MAP(
Oper1 => a31,
Reset => Resetext,
Oper2 => posicionin,
Result => callout
);
end Behavioral;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Segmentado/tbdecode.vhd
|
1
|
4605
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:23:38 11/11/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/decode/tbdecode.vhd
-- Project Name: decode
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Decode
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbdecode IS
END tbdecode;
ARCHITECTURE behavior OF tbdecode IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Decode
PORT(
Instruction : IN std_logic_vector(31 downto 0);
posicionin : IN std_logic_vector(31 downto 0);
Regtomemin : IN std_logic_vector(31 downto 0);
cwpin : IN std_logic;
iccin : IN std_logic_vector(3 downto 0);
Resetext : IN std_logic;
ncwpout : OUT std_logic;
callout : OUT std_logic_vector(31 downto 0);
ifout : OUT std_logic_vector(31 downto 0);
rfdestout : OUT std_logic;
rfsourceout : OUT std_logic_vector(1 downto 0);
wrenmen : OUT std_logic;
pcsource : OUT std_logic_vector(1 downto 0);
aluop : OUT std_logic_vector(5 downto 0);
a18 : OUT std_logic_vector(31 downto 0);
crs1out : OUT std_logic_vector(31 downto 0);
op2out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Instruction : std_logic_vector(31 downto 0) := (others => '0');
signal posicionin : std_logic_vector(31 downto 0) := (others => '0');
signal Regtomemin : std_logic_vector(31 downto 0) := (others => '0');
signal cwpin : std_logic := '0';
signal iccin : std_logic_vector(3 downto 0) := (others => '0');
signal Resetext : std_logic := '0';
--Outputs
signal ncwpout : std_logic;
signal callout : std_logic_vector(31 downto 0);
signal ifout : std_logic_vector(31 downto 0);
signal rfdestout : std_logic;
signal rfsourceout : std_logic_vector(1 downto 0);
signal wrenmen : std_logic;
signal pcsource : std_logic_vector(1 downto 0);
signal aluop : std_logic_vector(5 downto 0);
signal a18 : std_logic_vector(31 downto 0);
signal crs1out : std_logic_vector(31 downto 0);
signal op2out : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Decode PORT MAP (
Instruction => Instruction,
posicionin => posicionin,
Regtomemin => Regtomemin,
cwpin => cwpin,
iccin => iccin,
Resetext => Resetext,
ncwpout => ncwpout,
callout => callout,
ifout => ifout,
rfdestout => rfdestout,
rfsourceout => rfsourceout,
wrenmen => wrenmen,
pcsource => pcsource,
aluop => aluop,
a18 => a18,
crs1out => crs1out,
op2out => op2out
);
-- Clock process definitions
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Instruction <= "10100100000100000010000000000101";
posicionin <= "00000000000000000000000000000001";
Regtomemin <= "00000000000000000000000000111111";
cwpin <= '0';
iccin <= "0000";
Resetext <= '1';
wait for 100 ns;
Instruction <= "10100100000100000010000000000101";
posicionin <= "00000000000000000000000000000001";
Regtomemin <= "00000000000000000000000000111111";
cwpin <= '0';
iccin <= "0000";
Resetext <= '0';
wait for 100 ns;
Instruction <= "10100100000100000010000000001111";
posicionin <= "00000000000000000000000000000010";
Regtomemin <= "00000000000000000000000000001111";
cwpin <= '0';
iccin <= "0000";
Resetext <= '0';
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Primerprocesador17octubre/ALU.vhd
|
1
|
1690
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:19:49 10/04/2017
-- Design Name:
-- Module Name: ALU - ARQALU
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( OPER1 : in STD_LOGIC_VECTOR (31 downto 0);
OPER2 : in STD_LOGIC_VECTOR (31 downto 0);
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0));
end ALU;
architecture ARQALU of ALU is
begin
process(OPER1,OPER2,ALUOP)
begin
if(ALUOP = "000010")then
ALURESULT<= OPER1 OR OPER2;
elsif(ALUOP = "000011")then
ALURESULT<= OPER1 XOR OPER2;
elsif(ALUOP = "000000")then
ALURESULT<= OPER1 + OPER2;
elsif(ALUOP = "000100")then
ALURESULT<= OPER1 - OPER2;
elsif(ALUOP = "000001")then
ALURESULT<= OPER1 AND OPER2;
elsif(ALUOP = "000101")then
ALURESULT<= OPER1 AND (not OPER2);
elsif(ALUOP = "000110")then
ALURESULT<= OPER1 NOR OPER2;
elsif(ALUOP = "000111")then
ALURESULT<= OPER1 XNOR OPER2;
end if;
end process;
end ARQALU;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Primerprocesador17octubre/TextbSumador32bit.vhd
|
3
|
2233
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:33:50 09/27/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/Procesador/TextbSumador32bit.vhd
-- Project Name: Procesador
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Sumador32bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TextbSumador32bit IS
END TextbSumador32bit;
ARCHITECTURE behavior OF TextbSumador32bit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sumador32bit
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Result : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sumador32bit PORT MAP (
Oper1 => Oper1,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Oper1 <= "00000000000000000000000000000001";
wait for 100 ns;
Oper1 <= "00000000000000000000000000000000";
wait for 100 ns;
Oper1 <= "00000000000000000000000000000100";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Primerprocesador17octubre/PC.vhd
|
2
|
1260
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:13:56 09/26/2017
-- Design Name:
-- Module Name: PC - arqPC
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC is
Port ( inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture arqPC of PC is
begin
process(Clk,Reset,inPC)
begin
if(Reset = '1')then
outPC<="00000000000000000000000000000000";
else
if(rising_edge(Clk)) then
outPC<=inPC;
end if;
end if;
end process;
end arqPC;
|
gpl-3.0
|
quicky2000/top_wireworld
|
testbench/wireworld_cell_testbench.vhd
|
1
|
3386
|
--
-- This file is part of top_wireworld
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.my_package.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY wireworld_cell_testbench IS
END wireworld_cell_testbench;
ARCHITECTURE behavior OF wireworld_cell_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wireworld_cell
generic (
init_state : state_type
);
PORT(
clk : IN std_logic;
reset : IN std_logic;
neighbours : IN std_logic_vector(7 downto 0);
electron_head : OUT std_logic;
electron_queue : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal neighbours : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal electron_head : std_logic;
signal electron_queue : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: wireworld_cell generic map(init_state=> t_electron_head) PORT MAP (
clk => clk,
reset => reset,
neighbours => neighbours,
electron_head => electron_head,
electron_queue => electron_queue
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*2;
neighbours <= (0 => '1', others => '0');
wait for clk_period;
neighbours <= (others => '0');
wait for clk_period * 2;
neighbours <= (0 to 3 => '1', others => '0');
wait for clk_period;
neighbours <= (others => '0');
wait for clk_period * 2;
neighbours <= (0 to 1 => '1', others => '0');
wait for clk_period;
neighbours <= (others => '0');
wait for clk_period * 2;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
makestuff/s3b_sdram
|
try1/memctrl/hexutil.vhdl
|
1
|
2992
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package hexutil is
function to_1(c : character) return std_logic;
function to_2(c : character) return std_logic_vector;
function to_3(c : character) return std_logic_vector;
function to_4(c : character) return std_logic_vector;
end package;
package body hexutil is
-- Return the bits of the supplied hex nibble
function to_4(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
case c is
when '0' =>
nibble := "0000";
when '1' =>
nibble := "0001";
when '2' =>
nibble := "0010";
when '3' =>
nibble := "0011";
when '4' =>
nibble := "0100";
when '5' =>
nibble := "0101";
when '6' =>
nibble := "0110";
when '7' =>
nibble := "0111";
when '8' =>
nibble := "1000";
when '9' =>
nibble := "1001";
when 'a' =>
nibble := "1010";
when 'A' =>
nibble := "1010";
when 'b' =>
nibble := "1011";
when 'B' =>
nibble := "1011";
when 'c' =>
nibble := "1100";
when 'C' =>
nibble := "1100";
when 'd' =>
nibble := "1101";
when 'D' =>
nibble := "1101";
when 'e' =>
nibble := "1110";
when 'E' =>
nibble := "1110";
when 'f' =>
nibble := "1111";
when 'F' =>
nibble := "1111";
when 'X' =>
nibble := "XXXX";
when 'x' =>
nibble := "XXXX";
when 'Z' =>
nibble := "ZZZZ";
when 'z' =>
nibble := "ZZZZ";
when others =>
nibble := "UUUU";
end case;
return nibble;
end function;
-- Return the least-significant bit of the supplied hex nibble
function to_1(c : character) return std_logic is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(0);
end function;
-- Return two least-significant bits of the supplied hex nibble
function to_2(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(1 downto 0);
end function;
-- Return three least-significant bits of the supplied hex nibble
function to_3(c : character) return std_logic_vector is
variable nibble : std_logic_vector(3 downto 0);
begin
nibble := to_4(c);
return nibble(2 downto 0);
end function;
end package body;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Terceryfullprocesador/Tbtercerprocesaor.vhd
|
1
|
2982
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:42:42 10/22/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesador3full/Tbtercerprocesaor.vhd
-- Project Name: procesador3full
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: firstrpart
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tbtercerprocesaor IS
END Tbtercerprocesaor;
ARCHITECTURE behavior OF Tbtercerprocesaor IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT firstrpart
PORT(
Resetext : IN std_logic;
Clkinext : IN std_logic;
Adressext : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Resetext : std_logic := '0';
signal Clkinext : std_logic := '0';
--Outputs
signal Adressext : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clkinext_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: firstrpart PORT MAP (
Resetext => Resetext,
Clkinext => Clkinext,
Adressext => Adressext
);
-- Clock process definitions
Clkinext_process :process
begin
Clkinext <= '0';
wait for Clkinext_period/2;
Clkinext <= '1';
wait for Clkinext_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Resetext <= '0';
wait for 100 ns;
Resetext <= '1';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Segmentado/Sumador32bit.vhd
|
1
|
1308
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:19:18 09/27/2017
-- Design Name:
-- Module Name: Sumador32bit - Arq_Sumador32bit
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sumador32bit is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Result : out STD_LOGIC_VECTOR (31 downto 0));
end Sumador32bit;
architecture arq_Sumador32bit of Sumador32bit is
begin
process(Oper1,Oper2,Reset)
begin
if reset='1' then
Result<= "00000000000000000000000000000000";
else
Result<= Oper1 + Oper2;
end if;
end process;
end arq_Sumador32bit;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Segmentado/PSR_Modifier.vhd
|
3
|
2095
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity PSR_Modifier is
Port ( oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0));
end PSR_Modifier;
architecture Behavioral of PSR_Modifier is
begin
process(aluop,oper1,oper2,aluResult)
begin
if (aluop="010001" or aluop="010101" or aluop="010010" or aluop="010110" or aluop="010011" or aluop="010111") then -- ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<= '0'; --V
conditionalCodes(0)<= '0'; --C
elsif (aluop="010000" or aluop="011000") then --ADDcc, ADDXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and oper2(31) and (not aluResult(31))) or ((not oper1(31)) and (not oper2(31)) and aluResult(31));
conditionalCodes(0)<=(oper1(31) and oper2(31)) or ((not aluResult(31)) and (oper1(31) or oper2(31)));
elsif (aluop="010100" or aluop="011100") then --SUBcc, SUBXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and (not oper2(31)) and (not aluResult(31))) or ((not oper1(31)) and oper2(31) and aluResult(31));
conditionalCodes(0)<=((not oper1(31)) and oper2(31)) or (aluResult(31) and ((not oper1(31)) or oper2(31)));
end if;
end process;
end Behavioral;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Terceryfullprocesador/TbPSRNEW.vhd
|
2
|
2444
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:06:56 10/18/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/TbPSRNEW.vhd
-- Project Name: secondooooooooo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PSR
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TbPSRNEW IS
END TbPSRNEW;
ARCHITECTURE behavior OF TbPSRNEW IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PSR
PORT(
nzvc : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
cwp : OUT std_logic;
ncwp : IN std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal nzvc : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal ncwp : std_logic := '0';
--Outputs
signal cwp : std_logic;
signal c : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PSR PORT MAP (
nzvc => nzvc,
clk => clk,
cwp => cwp,
ncwp => ncwp,
c => c
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
nzvc<="1111";
ncwp<='0';
wait for 100 ns;
nzvc<="1100";
ncwp<='1';
wait for 100 ns;
nzvc<="1101";
ncwp<='0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
gpl-3.0
|
Kalugy/Procesadorarquitectura
|
Terceryfullprocesador/PC.vhd
|
2
|
1246
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:13:56 09/26/2017
-- Design Name:
-- Module Name: PC - arqPC
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC is
Port ( inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture arqPC of PC is
begin
process(Clk,Reset,inPC)
begin
if(Reset = '1')then
outPC<="00000000000000000000000000000000";
elsif(rising_edge(Clk)) then
outPC<=inPC;
end if;
end process;
end arqPC;
|
gpl-3.0
|
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_131.vhd
|
1
|
17856
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- x^131 + x^8 + x^3 + x^2 + 1
entity serial_multiplier_131 is
generic (
NUM_BITS : positive := 131 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_131;
-----------------------------------------------------------
architecture behave of serial_multiplier_131 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
signal xor_2 : std_logic;
signal xor_3 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(1) xor Cx_int(NUM_BITS-1);
xor_2 <= Cx_int(2) xor Cx_int(NUM_BITS-1);
xor_3 <= Cx_int(7) xor Cx_int(NUM_BITS-1);
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
CELL_0: ENTITY work.basic_cell(behave)
PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0));
CELL_1: ENTITY work.basic_cell(behave)
PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1));
CELL_2: ENTITY work.basic_cell(behave)
PORT MAP(Ax(2),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(2));
CELL_3: ENTITY work.basic_cell(behave)
PORT MAP(Ax(3),Bx_int(NUM_BITS-1),xor_2,clk,reset,Cx_int(3));
CELL_4: ENTITY work.basic_cell(behave)
PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4));
CELL_5: ENTITY work.basic_cell(behave)
PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5));
CELL_6: ENTITY work.basic_cell(behave)
PORT MAP(Ax(6),Bx_int(NUM_BITS-1),Cx_int(5),clk,reset,Cx_int(6));
CELL_7: ENTITY work.basic_cell(behave)
PORT MAP(Ax(7),Bx_int(NUM_BITS-1),Cx_int(6),clk,reset,Cx_int(7));
CELL_8: ENTITY work.basic_cell(behave)
PORT MAP(Ax(8),Bx_int(NUM_BITS-1),xor_3,clk,reset,Cx_int(8));
CELL_9: ENTITY work.basic_cell(behave)
PORT MAP(Ax(9),Bx_int(NUM_BITS-1),Cx_int(8),clk,reset,Cx_int(9));
CELL_10: ENTITY work.basic_cell(behave)
PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10));
CELL_11: ENTITY work.basic_cell(behave)
PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11));
CELL_12: ENTITY work.basic_cell(behave)
PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12));
CELL_13: ENTITY work.basic_cell(behave)
PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13));
CELL_14: ENTITY work.basic_cell(behave)
PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14));
CELL_15: ENTITY work.basic_cell(behave)
PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15));
CELL_16: ENTITY work.basic_cell(behave)
PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16));
CELL_17: ENTITY work.basic_cell(behave)
PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17));
CELL_18: ENTITY work.basic_cell(behave)
PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18));
CELL_19: ENTITY work.basic_cell(behave)
PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19));
CELL_20: ENTITY work.basic_cell(behave)
PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20));
CELL_21: ENTITY work.basic_cell(behave)
PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21));
CELL_22: ENTITY work.basic_cell(behave)
PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22));
CELL_23: ENTITY work.basic_cell(behave)
PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23));
CELL_24: ENTITY work.basic_cell(behave)
PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24));
CELL_25: ENTITY work.basic_cell(behave)
PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25));
CELL_26: ENTITY work.basic_cell(behave)
PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26));
CELL_27: ENTITY work.basic_cell(behave)
PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27));
CELL_28: ENTITY work.basic_cell(behave)
PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28));
CELL_29: ENTITY work.basic_cell(behave)
PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29));
CELL_30: ENTITY work.basic_cell(behave)
PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30));
CELL_31: ENTITY work.basic_cell(behave)
PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31));
CELL_32: ENTITY work.basic_cell(behave)
PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32));
CELL_33: ENTITY work.basic_cell(behave)
PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33));
CELL_34: ENTITY work.basic_cell(behave)
PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34));
CELL_35: ENTITY work.basic_cell(behave)
PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35));
CELL_36: ENTITY work.basic_cell(behave)
PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36));
CELL_37: ENTITY work.basic_cell(behave)
PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37));
CELL_38: ENTITY work.basic_cell(behave)
PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38));
CELL_39: ENTITY work.basic_cell(behave)
PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39));
CELL_40: ENTITY work.basic_cell(behave)
PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40));
CELL_41: ENTITY work.basic_cell(behave)
PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41));
CELL_42: ENTITY work.basic_cell(behave)
PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42));
CELL_43: ENTITY work.basic_cell(behave)
PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43));
CELL_44: ENTITY work.basic_cell(behave)
PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44));
CELL_45: ENTITY work.basic_cell(behave)
PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45));
CELL_46: ENTITY work.basic_cell(behave)
PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46));
CELL_47: ENTITY work.basic_cell(behave)
PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47));
CELL_48: ENTITY work.basic_cell(behave)
PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48));
CELL_49: ENTITY work.basic_cell(behave)
PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49));
CELL_50: ENTITY work.basic_cell(behave)
PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50));
CELL_51: ENTITY work.basic_cell(behave)
PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51));
CELL_52: ENTITY work.basic_cell(behave)
PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52));
CELL_53: ENTITY work.basic_cell(behave)
PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53));
CELL_54: ENTITY work.basic_cell(behave)
PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54));
CELL_55: ENTITY work.basic_cell(behave)
PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55));
CELL_56: ENTITY work.basic_cell(behave)
PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56));
CELL_57: ENTITY work.basic_cell(behave)
PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57));
CELL_58: ENTITY work.basic_cell(behave)
PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58));
CELL_59: ENTITY work.basic_cell(behave)
PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59));
CELL_60: ENTITY work.basic_cell(behave)
PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60));
CELL_61: ENTITY work.basic_cell(behave)
PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61));
CELL_62: ENTITY work.basic_cell(behave)
PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62));
CELL_63: ENTITY work.basic_cell(behave)
PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63));
CELL_64: ENTITY work.basic_cell(behave)
PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64));
CELL_65: ENTITY work.basic_cell(behave)
PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65));
CELL_66: ENTITY work.basic_cell(behave)
PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66));
CELL_67: ENTITY work.basic_cell(behave)
PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67));
CELL_68: ENTITY work.basic_cell(behave)
PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68));
CELL_69: ENTITY work.basic_cell(behave)
PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69));
CELL_70: ENTITY work.basic_cell(behave)
PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70));
CELL_71: ENTITY work.basic_cell(behave)
PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71));
CELL_72: ENTITY work.basic_cell(behave)
PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72));
CELL_73: ENTITY work.basic_cell(behave)
PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73));
CELL_74: ENTITY work.basic_cell(behave)
PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74));
CELL_75: ENTITY work.basic_cell(behave)
PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75));
CELL_76: ENTITY work.basic_cell(behave)
PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76));
CELL_77: ENTITY work.basic_cell(behave)
PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77));
CELL_78: ENTITY work.basic_cell(behave)
PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78));
CELL_79: ENTITY work.basic_cell(behave)
PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79));
CELL_80: ENTITY work.basic_cell(behave)
PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80));
CELL_81: ENTITY work.basic_cell(behave)
PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81));
CELL_82: ENTITY work.basic_cell(behave)
PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82));
CELL_83: ENTITY work.basic_cell(behave)
PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83));
CELL_84: ENTITY work.basic_cell(behave)
PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84));
CELL_85: ENTITY work.basic_cell(behave)
PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85));
CELL_86: ENTITY work.basic_cell(behave)
PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86));
CELL_87: ENTITY work.basic_cell(behave)
PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87));
CELL_88: ENTITY work.basic_cell(behave)
PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88));
CELL_89: ENTITY work.basic_cell(behave)
PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89));
CELL_90: ENTITY work.basic_cell(behave)
PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90));
CELL_91: ENTITY work.basic_cell(behave)
PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91));
CELL_92: ENTITY work.basic_cell(behave)
PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92));
CELL_93: ENTITY work.basic_cell(behave)
PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93));
CELL_94: ENTITY work.basic_cell(behave)
PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94));
CELL_95: ENTITY work.basic_cell(behave)
PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95));
CELL_96: ENTITY work.basic_cell(behave)
PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96));
CELL_97: ENTITY work.basic_cell(behave)
PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97));
CELL_98: ENTITY work.basic_cell(behave)
PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98));
CELL_99: ENTITY work.basic_cell(behave)
PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99));
CELL_100: ENTITY work.basic_cell(behave)
PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100));
CELL_101: ENTITY work.basic_cell(behave)
PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101));
CELL_102: ENTITY work.basic_cell(behave)
PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102));
CELL_103: ENTITY work.basic_cell(behave)
PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103));
CELL_104: ENTITY work.basic_cell(behave)
PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104));
CELL_105: ENTITY work.basic_cell(behave)
PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105));
CELL_106: ENTITY work.basic_cell(behave)
PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106));
CELL_107: ENTITY work.basic_cell(behave)
PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107));
CELL_108: ENTITY work.basic_cell(behave)
PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108));
CELL_109: ENTITY work.basic_cell(behave)
PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109));
CELL_110: ENTITY work.basic_cell(behave)
PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110));
CELL_111: ENTITY work.basic_cell(behave)
PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111));
CELL_112: ENTITY work.basic_cell(behave)
PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112));
CELL_113: ENTITY work.basic_cell(behave)
PORT MAP(Ax(113),Bx_int(NUM_BITS-1),Cx_int(112),clk,reset,Cx_int(113));
CELL_114: ENTITY work.basic_cell(behave)
PORT MAP(Ax(114),Bx_int(NUM_BITS-1),Cx_int(113),clk,reset,Cx_int(114));
CELL_115: ENTITY work.basic_cell(behave)
PORT MAP(Ax(115),Bx_int(NUM_BITS-1),Cx_int(114),clk,reset,Cx_int(115));
CELL_116: ENTITY work.basic_cell(behave)
PORT MAP(Ax(116),Bx_int(NUM_BITS-1),Cx_int(115),clk,reset,Cx_int(116));
CELL_117: ENTITY work.basic_cell(behave)
PORT MAP(Ax(117),Bx_int(NUM_BITS-1),Cx_int(116),clk,reset,Cx_int(117));
CELL_118: ENTITY work.basic_cell(behave)
PORT MAP(Ax(118),Bx_int(NUM_BITS-1),Cx_int(117),clk,reset,Cx_int(118));
CELL_119: ENTITY work.basic_cell(behave)
PORT MAP(Ax(119),Bx_int(NUM_BITS-1),Cx_int(118),clk,reset,Cx_int(119));
CELL_120: ENTITY work.basic_cell(behave)
PORT MAP(Ax(120),Bx_int(NUM_BITS-1),Cx_int(119),clk,reset,Cx_int(120));
CELL_121: ENTITY work.basic_cell(behave)
PORT MAP(Ax(121),Bx_int(NUM_BITS-1),Cx_int(120),clk,reset,Cx_int(121));
CELL_122: ENTITY work.basic_cell(behave)
PORT MAP(Ax(122),Bx_int(NUM_BITS-1),Cx_int(121),clk,reset,Cx_int(122));
CELL_123: ENTITY work.basic_cell(behave)
PORT MAP(Ax(123),Bx_int(NUM_BITS-1),Cx_int(122),clk,reset,Cx_int(123));
CELL_124: ENTITY work.basic_cell(behave)
PORT MAP(Ax(124),Bx_int(NUM_BITS-1),Cx_int(123),clk,reset,Cx_int(124));
CELL_125: ENTITY work.basic_cell(behave)
PORT MAP(Ax(125),Bx_int(NUM_BITS-1),Cx_int(124),clk,reset,Cx_int(125));
CELL_126: ENTITY work.basic_cell(behave)
PORT MAP(Ax(126),Bx_int(NUM_BITS-1),Cx_int(125),clk,reset,Cx_int(126));
CELL_127: ENTITY work.basic_cell(behave)
PORT MAP(Ax(127),Bx_int(NUM_BITS-1),Cx_int(126),clk,reset,Cx_int(127));
CELL_128: ENTITY work.basic_cell(behave)
PORT MAP(Ax(128),Bx_int(NUM_BITS-1),Cx_int(127),clk,reset,Cx_int(128));
CELL_129: ENTITY work.basic_cell(behave)
PORT MAP(Ax(129),Bx_int(NUM_BITS-1),Cx_int(128),clk,reset,Cx_int(129));
CELL_130: ENTITY work.basic_cell(behave)
PORT MAP(Ax(130),Bx_int(NUM_BITS-1),Cx_int(129),clk,reset,Cx_int(130));
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10000010"; -- m-1 value, in this case, it is 112, be sure to set the correct value
bx_int <= bx;
cx <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
counter <= counter - 1;
if counter = "0000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
else
bx_int <= bx_shift;
end if;
when END_STATE =>
Cx <= Cx_int;
Done <= '1';
CurrentState <= NOTHING;
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Guerric/Modular/guerric_modular.vhd
|
1
|
5662
|
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- control signals
signal en_VS, C_0, C_1, C_2, C_3, ISPos: std_logic;
signal V, S,X2, Y2, u_pad, r_pad : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, R : STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal u_div_2, v_div_2, r_div_2, s_div_2, p_div_2: STD_LOGIC_VECTOR(NUM_BITS-1 downto 0); -- Internal registers
signal D: STD_LOGIC_VECTOR(3 downto 0); -- Internal registers
signal counter: STD_LOGIC_VECTOR(8 downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, LOAD2, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
u_pad <= '0' & U;
R_pad <= '0' & R;
U_div_2 <= '0' & U(NUM_BITS-1 downto 1);
R_div_2 <= '0' & R(NUM_BITS-1 downto 1);
P_div_2 <= p(NUM_BITS downto 1);
S_div_2 <= S(NUM_BITS downto 1);
V_div_2 <= V(NUM_BITS downto 1);
--carga 2x, 2y --carga p, 0 carga U, R
en_VS <= '1' when rst = '1' or CurrentState = LOAD1 or (U(0) = '1' and IsPos = '0') else
'0';
c_0 <= '1' when CurrentState = LOAD1 or U(0) = '1' else
'0';
c_2 <= '0' when rst = '1' else
'1';
c_1 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c_3 <= '0' when (CurrentState = LOAD1 or R(0) = '0') else
'1';
celda_reg_u: entity work.celda_u(behave)
port map( V_div_2,U_div_2,c_0,clk,rst,U);
celda_reg_r: entity work.celda_r(behave)
port map(R_div_2, P_div_2, S_div_2, c_3, c_0, clk, rst, R);
celda_reg_v: entity work.celda_v(behave)
port map(u_pad,P,Y2,c_1,c_2,en_VS,clk,V);
celda_reg_s: entity work.celda_s(behave)
port map(R_pad,X2,c_1,c_2,en_VS,clk,S);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
x_div_y <= (others => '0');
done <= '0';
counter <= "101001000"; --2*m - 2
IsPos <= '0';
D <= "0001";
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
currentState <= Cycle;
when CYCLE =>
counter <= counter - 1;
if U(0) = '0' then
if IsPos = '0' then D <= D + 1;
elsif D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
elsif IsPos = '1' then
if D = "0000" then
D <= D + 1;
IsPos <= '0';
else
D <= D - 1;
end if;
else
D <= D - 1;
IsPos <= '1';
end if;
if counter = "000000000" then
done <= '1';
x_div_y <= S(NUM_BITS-1 downto 0);
CurrentState <= END_STATE;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
mmoraless/ecc_vhdl
|
ecc_add/NewECCADD_131.vhd
|
1
|
6089
|
------------------------------------------------------------------------
--Nueva implementacion ADD y Double en una misma arquitectura
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity ECC_add_serial_131 is
generic(
-- 163, 233, 277, 283, 409, 571
NUM_BITS : positive := 131
);
port(
xP: in std_logic_vector(NUM_BITS-1 downto 0);
yP: in std_logic_vector(NUM_BITS-1 downto 0);
xQ: in std_logic_vector(NUM_BITS-1 downto 0);
yQ: in std_logic_vector(NUM_BITS-1 downto 0);
---------------------------------------------
clk: in std_logic;
rst: in std_logic;
s0: in std_logic; -- 1 = Suma, 0 = Double
---------------------------------------------
X: out std_logic_vector(NUM_BITS-1 downto 0);
Y: out std_logic_vector(NUM_BITS-1 downto 0);
done: out std_logic
);
end;
------------------------------------------------------
architecture behave of ECC_add_serial_131 is
type CurrentState_type is (END_STATE, CHECK_INPUT, SPEND_CYCLE1, SPEND_CYCLE2,CALC_INV, CALC_MUL);
signal CurrentState : CurrentState_type;
constant cero : std_logic_vector(NUM_BITS-1 downto 0):= (others => '0');
--
signal S1 : std_logic_vector(NUM_BITS-1 downto 0);
signal not_s0 : std_logic;
-- 4 multiplexores
signal L3 : std_logic_vector(NUM_BITS-1 downto 0);
signal SQRin : std_logic_vector(NUM_BITS-1 downto 0);
signal Div1 : std_logic_vector(NUM_BITS-1 downto 0);
signal Div2 : std_logic_vector(NUM_BITS-1 downto 0);
--- interface con el inversor
signal rstInv : std_logic;
signal Division : std_logic_vector(NUM_BITS-1 downto 0);
signal doneInv : std_logic;
--- interface del multiplicador
signal rstMul : std_logic;
signal Multiplication : std_logic_vector(NUM_BITS-1 downto 0);
signal doneMul : std_logic;
--- interface del squarer
signal SQR : std_logic_vector(NUM_BITS-1 downto 0);
---------------------------------------------------------------
begin
---------------------------------------------------------------
-- Componentes
---------------------------------------------------------------
SQUARER_1 : entity squarer_131(behave)
--generic map (D, NUM2_BITS, NUM_BITS)
generic map (NUM_BITS)
port map(SQRin, SQR);
---------------------------------------------------------------
MUL_1: entity serial_multiplier_131(behave)
generic map (NUM_BITS)
port map(S1, SQRin, Multiplication,rstMul,clk,doneMul);
---------------------------------------------------------------
INV_1: entity f2m_divider_131(behave)
generic map (NUM_BITS)
port map(Div1, Div2, clk, rstInv, doneInv, Division);
---------------------------------------------------------------
---------------------------------------------------------------
LUT31: entity lut_3in(behave)
generic map (NUM_BITS)
port map(yQ, s0, yP, Div1);
---------------------------------------------------------------
---------------------------------------------------------------
LUT32: entity lut_3in(behave)
generic map (NUM_BITS)
port map(xQ, s0, xP, Div2);
---------------------------------------------------------------
---------------------------------------------------------------
LUT33: entity lut_3in(behave)
generic map (NUM_BITS)
port map(xP, not_s0, Division,SQRin);
---------------------------------------------------------------
---------------------------------------------------------------
LUT41: entity lut_3inadd(behave)
generic map (NUM_BITS)
port map(SQR, Division, Div2, L3);
---------------------------------------------------------------
-- Operaciones combinacionales (Sumas)
S1 <= L3 xor xP;
not_s0 <= not s0;
---------------------------------------------------------------
ADD_FSM: process (CLK)
Begin
if CLK'event and CLK = '1' then
-- Los datos de entrada deben estar presentes al llegar la señal de reset,
-- Si la señal Rst de entrada es síncrona con un reloj (i.e. es proporcionada
-- por un control en la subida del reloj), los datos a la entrada deben asignarse
-- junto con la señal de Rst o al momento de que Rst regrese a '0'
if Rst = '1' then
CurrentState <= CHECK_INPUT;
Done <= '0';
X <= (others =>'0');
Y <= (others =>'0');
rstInv <= '0';
rstMul <= '0';
else
case CurrentState is
when CHECK_INPUT =>
if (xP = cero) and (yP = cero) and s0 = '1' then -- add
X <= xQ;
Y <= yQ;
Done <= '1';
CurrentState <= END_STATE;
elsif (xQ = cero) and (yQ = cero) and s0 = '1' then -- Add
X <= xP;
Y <= yP;
Done <= '1';
CurrentState <= END_STATE;
elsif (xP = cero) and s0 = '0' then -- Double
Done <= '1';
CurrentState <= END_STATE;
else
rstInv <= '1'; -- calcular la division primero.
CurrentState <= SPEND_CYCLE1;
end if;
when SPEND_CYCLE1 => -- Provoca el pulso RST al modulo de inversion.
rstInv <= '0';
CurrentState <= CALC_INV;
when CALC_INV => -- Una vez que termina de calcular la division,
if doneInv = '1' then -- comienza con la multiplicación.
X <= L3;
rstMul <= '1';
CurrentState <= SPEND_CYCLE2;
end if;
when SPEND_CYCLE2 => -- Provoca el pulso RST en el multiplicador
rstMul <= '0';
CurrentState <= CALC_MUL;
when CALC_MUL => -- Espera que el multiplicador termine
if doneMul = '1' then
Y <= Multiplication xor L3 xor yP;
Done <= '1';
CurrentState <= END_STATE; -- Operación ADD terminada
end if;
when END_STATE =>
CurrentState <= END_STATE;
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/serialMul/serial_multiplier_233.vhd
|
1
|
4719
|
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_233 is
generic (
NUM_BITS : positive := 233 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_233;
-----------------------------------------------------------
architecture behave of serial_multiplier_233 is
-----------------------------------------------------------
-- m = 233 x233 + x74 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "11101000"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_divider/Gura/Modular/gura_modular_131.vhd
|
1
|
5438
|
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_131 is
generic(
NUM_BITS : positive := 131
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_131 is
----------------------------------------------------------------------------------------------------
-- m = 131, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101";
-- control signals
signal CASO: std_logic_vector(1 downto 0);
signal c_4, c_5,c_6,a_greater_b,a_eq_b: std_logic;
signal CA, CB : STD_LOGIC_VECTOR(7 downto 0);
signal U, A, V, B,X2, Y2, temp1, toA, toB, toU, toV: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
caso <= "01" when (A(0) = '1' and B(0) = '0') or CurrentState = LOAD1 else
"10" when A(0) = '0' else
"11";
c_5 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c_6 <= '1' when CurrentState = LOAD1 else
'0';
a_greater_b <= '1' when CA > CB else
'0';
a_eq_b <= '1' when A = B else
'0';
--a_eq_b <= '1' when CA = "00000000" else
-- '0';
c_4 <= '0' when CurrentState = Load1 or temp1(0) = '0' else
'1';
celda_reg_A: entity celda_a(behave)
generic map (NUM_BITS)
port map( A, B,caso(1), caso(0), toA);
celda_reg_U: entity celda_U(behave)
generic map (NUM_BITS)
port map(U, V, caso(1), caso(0), temp1);
celda_reg_mod_P: entity mod_P(behave)
generic map (NUM_BITS)
port map(temp1, P, c_4, toU);
celda_reg_B: entity celda_B(behave)
generic map (NUM_BITS)
port map(toA,P,Y2,c_5,c_6, toB);
celda_reg_V: entity celda_v(behave)
generic map (NUM_BITS)
port map(toU,X2,c_5,c_6,toV);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= (others => '0');
U <= (others => '0');
B <= toB;
V <= toV;
CA <= "10000010" ;
CB <= "10000001" ;
x_div_y <= (others => '0');
done <= '0';
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
A <= toA;
U <= toU;
B <= toB;
V <= toV;
currentState <= Cycle;
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
elsif CASO = "10" then
A <= toA;
CA <= CA-1;
U <= toU;
elsif CASO = "01" then
B <= toB;
CB <= CB -1;
V <= toV;
elsif a_greater_b = '1' then
A <= toA;
CA <= CA-1;
U <= toU;
else
B <= toB;
CB <= CB-1;
V <= toV;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
mmoraless/ecc_vhdl
|
F2mArithmetic/F2m_Multiplication/Serial_Mul_Paar/multiplier_163_3.vhd
|
1
|
14764
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Sin celda y sin maquina de estados
--------------------------------------------------------
-- x^163 + x^7 + x^6 + x^3 + 1
entity serial_multiplier_163 is
generic (
NUM_BITS : positive := 163 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_163;
-----------------------------------------------------------
architecture behave of serial_multiplier_163 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
signal xor_2 : std_logic;
signal xor_3 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
--type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
--signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(2) xor Cx_int(NUM_BITS-1);
xor_2 <= Cx_int(5) xor Cx_int(NUM_BITS-1);
xor_3 <= Cx_int(6) xor Cx_int(NUM_BITS-1);
--Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
bx_int <= Bx_shift; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
done <= done_int;
cx <= cx_int;
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "00000000"; -- m-1 value, in this case, it is 112, be sure to set the correct value
cx_int <= (others => '0');
Done_int <= '0';
else
if done_int = '0' then
counter <= counter + 1;
Cx_int(0) <= ( Ax(0) and Bx_int(NUM_BITS-1) ) xor Cx_int(NUM_BITS-1);
Cx_int(1) <= ( Ax(1) and Bx_int(NUM_BITS-1) ) xor Cx_int(0);
Cx_int(2) <= ( Ax(2) and Bx_int(NUM_BITS-1) ) xor Cx_int(1);
Cx_int(3) <= ( Ax(3) and Bx_int(NUM_BITS-1) ) xor xor_1;
Cx_int(4) <= ( Ax(4) and Bx_int(NUM_BITS-1) ) xor Cx_int(3);
Cx_int(5) <= ( Ax(5) and Bx_int(NUM_BITS-1) ) xor Cx_int(4);
Cx_int(6) <= ( Ax(6) and Bx_int(NUM_BITS-1) ) xor xor_2;
Cx_int(7) <= ( Ax(7) and Bx_int(NUM_BITS-1) ) xor xor_3;
Cx_int(8) <= ( Ax(8) and Bx_int(NUM_BITS-1) ) xor Cx_int(7);
Cx_int(9) <= ( Ax(9) and Bx_int(NUM_BITS-1) ) xor Cx_int(8);
Cx_int(10) <= ( Ax(10) and Bx_int(NUM_BITS-1) ) xor Cx_int(9);
Cx_int(11) <= ( Ax(11) and Bx_int(NUM_BITS-1) ) xor Cx_int(10);
Cx_int(12) <= ( Ax(12) and Bx_int(NUM_BITS-1) ) xor Cx_int(11);
Cx_int(13) <= ( Ax(13) and Bx_int(NUM_BITS-1) ) xor Cx_int(12);
Cx_int(14) <= ( Ax(14) and Bx_int(NUM_BITS-1) ) xor Cx_int(13);
Cx_int(15) <= ( Ax(15) and Bx_int(NUM_BITS-1) ) xor Cx_int(14);
Cx_int(16) <= ( Ax(16) and Bx_int(NUM_BITS-1) ) xor Cx_int(15);
Cx_int(17) <= ( Ax(17) and Bx_int(NUM_BITS-1) ) xor Cx_int(16);
Cx_int(18) <= ( Ax(18) and Bx_int(NUM_BITS-1) ) xor Cx_int(17);
Cx_int(19) <= ( Ax(19) and Bx_int(NUM_BITS-1) ) xor Cx_int(18);
Cx_int(20) <= ( Ax(20) and Bx_int(NUM_BITS-1) ) xor Cx_int(19);
Cx_int(21) <= ( Ax(21) and Bx_int(NUM_BITS-1) ) xor Cx_int(20);
Cx_int(22) <= ( Ax(22) and Bx_int(NUM_BITS-1) ) xor Cx_int(21);
Cx_int(23) <= ( Ax(23) and Bx_int(NUM_BITS-1) ) xor Cx_int(22);
Cx_int(24) <= ( Ax(24) and Bx_int(NUM_BITS-1) ) xor Cx_int(23);
Cx_int(25) <= ( Ax(25) and Bx_int(NUM_BITS-1) ) xor Cx_int(24);
Cx_int(26) <= ( Ax(26) and Bx_int(NUM_BITS-1) ) xor Cx_int(25);
Cx_int(27) <= ( Ax(27) and Bx_int(NUM_BITS-1) ) xor Cx_int(26);
Cx_int(28) <= ( Ax(28) and Bx_int(NUM_BITS-1) ) xor Cx_int(27);
Cx_int(29) <= ( Ax(29) and Bx_int(NUM_BITS-1) ) xor Cx_int(28);
Cx_int(30) <= ( Ax(30) and Bx_int(NUM_BITS-1) ) xor Cx_int(29);
Cx_int(31) <= ( Ax(31) and Bx_int(NUM_BITS-1) ) xor Cx_int(30);
Cx_int(32) <= ( Ax(32) and Bx_int(NUM_BITS-1) ) xor Cx_int(31);
Cx_int(33) <= ( Ax(33) and Bx_int(NUM_BITS-1) ) xor Cx_int(32);
Cx_int(34) <= ( Ax(34) and Bx_int(NUM_BITS-1) ) xor Cx_int(33);
Cx_int(35) <= ( Ax(35) and Bx_int(NUM_BITS-1) ) xor Cx_int(34);
Cx_int(36) <= ( Ax(36) and Bx_int(NUM_BITS-1) ) xor Cx_int(35);
Cx_int(37) <= ( Ax(37) and Bx_int(NUM_BITS-1) ) xor Cx_int(36);
Cx_int(38) <= ( Ax(38) and Bx_int(NUM_BITS-1) ) xor Cx_int(37);
Cx_int(39) <= ( Ax(39) and Bx_int(NUM_BITS-1) ) xor Cx_int(38);
Cx_int(40) <= ( Ax(40) and Bx_int(NUM_BITS-1) ) xor Cx_int(39);
Cx_int(41) <= ( Ax(41) and Bx_int(NUM_BITS-1) ) xor Cx_int(40);
Cx_int(42) <= ( Ax(42) and Bx_int(NUM_BITS-1) ) xor Cx_int(41);
Cx_int(43) <= ( Ax(43) and Bx_int(NUM_BITS-1) ) xor Cx_int(42);
Cx_int(44) <= ( Ax(44) and Bx_int(NUM_BITS-1) ) xor Cx_int(43);
Cx_int(45) <= ( Ax(45) and Bx_int(NUM_BITS-1) ) xor Cx_int(44);
Cx_int(46) <= ( Ax(46) and Bx_int(NUM_BITS-1) ) xor Cx_int(45);
Cx_int(47) <= ( Ax(47) and Bx_int(NUM_BITS-1) ) xor Cx_int(46);
Cx_int(48) <= ( Ax(48) and Bx_int(NUM_BITS-1) ) xor Cx_int(47);
Cx_int(49) <= ( Ax(49) and Bx_int(NUM_BITS-1) ) xor Cx_int(48);
Cx_int(50) <= ( Ax(50) and Bx_int(NUM_BITS-1) ) xor Cx_int(49);
Cx_int(51) <= ( Ax(51) and Bx_int(NUM_BITS-1) ) xor Cx_int(50);
Cx_int(52) <= ( Ax(52) and Bx_int(NUM_BITS-1) ) xor Cx_int(51);
Cx_int(53) <= ( Ax(53) and Bx_int(NUM_BITS-1) ) xor Cx_int(52);
Cx_int(54) <= ( Ax(54) and Bx_int(NUM_BITS-1) ) xor Cx_int(53);
Cx_int(55) <= ( Ax(55) and Bx_int(NUM_BITS-1) ) xor Cx_int(54);
Cx_int(56) <= ( Ax(56) and Bx_int(NUM_BITS-1) ) xor Cx_int(55);
Cx_int(57) <= ( Ax(57) and Bx_int(NUM_BITS-1) ) xor Cx_int(56);
Cx_int(58) <= ( Ax(58) and Bx_int(NUM_BITS-1) ) xor Cx_int(57);
Cx_int(59) <= ( Ax(59) and Bx_int(NUM_BITS-1) ) xor Cx_int(58);
Cx_int(60) <= ( Ax(60) and Bx_int(NUM_BITS-1) ) xor Cx_int(59);
Cx_int(61) <= ( Ax(61) and Bx_int(NUM_BITS-1) ) xor Cx_int(60);
Cx_int(62) <= ( Ax(62) and Bx_int(NUM_BITS-1) ) xor Cx_int(61);
Cx_int(63) <= ( Ax(63) and Bx_int(NUM_BITS-1) ) xor Cx_int(62);
Cx_int(64) <= ( Ax(64) and Bx_int(NUM_BITS-1) ) xor Cx_int(63);
Cx_int(65) <= ( Ax(65) and Bx_int(NUM_BITS-1) ) xor Cx_int(64);
Cx_int(66) <= ( Ax(66) and Bx_int(NUM_BITS-1) ) xor Cx_int(65);
Cx_int(67) <= ( Ax(67) and Bx_int(NUM_BITS-1) ) xor Cx_int(66);
Cx_int(68) <= ( Ax(68) and Bx_int(NUM_BITS-1) ) xor Cx_int(67);
Cx_int(69) <= ( Ax(69) and Bx_int(NUM_BITS-1) ) xor Cx_int(68);
Cx_int(70) <= ( Ax(70) and Bx_int(NUM_BITS-1) ) xor Cx_int(69);
Cx_int(71) <= ( Ax(71) and Bx_int(NUM_BITS-1) ) xor Cx_int(70);
Cx_int(72) <= ( Ax(72) and Bx_int(NUM_BITS-1) ) xor Cx_int(71);
Cx_int(73) <= ( Ax(73) and Bx_int(NUM_BITS-1) ) xor Cx_int(72);
Cx_int(74) <= ( Ax(74) and Bx_int(NUM_BITS-1) ) xor Cx_int(73);
Cx_int(75) <= ( Ax(75) and Bx_int(NUM_BITS-1) ) xor Cx_int(74);
Cx_int(76) <= ( Ax(76) and Bx_int(NUM_BITS-1) ) xor Cx_int(75);
Cx_int(77) <= ( Ax(77) and Bx_int(NUM_BITS-1) ) xor Cx_int(76);
Cx_int(78) <= ( Ax(78) and Bx_int(NUM_BITS-1) ) xor Cx_int(77);
Cx_int(79) <= ( Ax(79) and Bx_int(NUM_BITS-1) ) xor Cx_int(78);
Cx_int(80) <= ( Ax(80) and Bx_int(NUM_BITS-1) ) xor Cx_int(79);
Cx_int(81) <= ( Ax(81) and Bx_int(NUM_BITS-1) ) xor Cx_int(80);
Cx_int(82) <= ( Ax(82) and Bx_int(NUM_BITS-1) ) xor Cx_int(81);
Cx_int(83) <= ( Ax(83) and Bx_int(NUM_BITS-1) ) xor Cx_int(82);
Cx_int(84) <= ( Ax(84) and Bx_int(NUM_BITS-1) ) xor Cx_int(83);
Cx_int(85) <= ( Ax(85) and Bx_int(NUM_BITS-1) ) xor Cx_int(84);
Cx_int(86) <= ( Ax(86) and Bx_int(NUM_BITS-1) ) xor Cx_int(85);
Cx_int(87) <= ( Ax(87) and Bx_int(NUM_BITS-1) ) xor Cx_int(86);
Cx_int(88) <= ( Ax(88) and Bx_int(NUM_BITS-1) ) xor Cx_int(87);
Cx_int(89) <= ( Ax(89) and Bx_int(NUM_BITS-1) ) xor Cx_int(88);
Cx_int(90) <= ( Ax(90) and Bx_int(NUM_BITS-1) ) xor Cx_int(89);
Cx_int(91) <= ( Ax(91) and Bx_int(NUM_BITS-1) ) xor Cx_int(90);
Cx_int(92) <= ( Ax(92) and Bx_int(NUM_BITS-1) ) xor Cx_int(91);
Cx_int(93) <= ( Ax(93) and Bx_int(NUM_BITS-1) ) xor Cx_int(92);
Cx_int(94) <= ( Ax(94) and Bx_int(NUM_BITS-1) ) xor Cx_int(93);
Cx_int(95) <= ( Ax(95) and Bx_int(NUM_BITS-1) ) xor Cx_int(94);
Cx_int(96) <= ( Ax(96) and Bx_int(NUM_BITS-1) ) xor Cx_int(95);
Cx_int(97) <= ( Ax(97) and Bx_int(NUM_BITS-1) ) xor Cx_int(96);
Cx_int(98) <= ( Ax(98) and Bx_int(NUM_BITS-1) ) xor Cx_int(97);
Cx_int(99) <= ( Ax(99) and Bx_int(NUM_BITS-1) ) xor Cx_int(98);
Cx_int(100) <= ( Ax(100) and Bx_int(NUM_BITS-1) ) xor Cx_int(99);
Cx_int(101) <= ( Ax(101) and Bx_int(NUM_BITS-1) ) xor Cx_int(100);
Cx_int(102) <= ( Ax(102) and Bx_int(NUM_BITS-1) ) xor Cx_int(101);
Cx_int(103) <= ( Ax(103) and Bx_int(NUM_BITS-1) ) xor Cx_int(102);
Cx_int(104) <= ( Ax(104) and Bx_int(NUM_BITS-1) ) xor Cx_int(103);
Cx_int(105) <= ( Ax(105) and Bx_int(NUM_BITS-1) ) xor Cx_int(104);
Cx_int(106) <= ( Ax(106) and Bx_int(NUM_BITS-1) ) xor Cx_int(105);
Cx_int(107) <= ( Ax(107) and Bx_int(NUM_BITS-1) ) xor Cx_int(106);
Cx_int(108) <= ( Ax(108) and Bx_int(NUM_BITS-1) ) xor Cx_int(107);
Cx_int(109) <= ( Ax(109) and Bx_int(NUM_BITS-1) ) xor Cx_int(108);
Cx_int(110) <= ( Ax(110) and Bx_int(NUM_BITS-1) ) xor Cx_int(109);
Cx_int(111) <= ( Ax(111) and Bx_int(NUM_BITS-1) ) xor Cx_int(110);
Cx_int(112) <= ( Ax(112) and Bx_int(NUM_BITS-1) ) xor Cx_int(111);
Cx_int(113) <= ( Ax(113) and Bx_int(NUM_BITS-1) ) xor Cx_int(112);
Cx_int(114) <= ( Ax(114) and Bx_int(NUM_BITS-1) ) xor Cx_int(113);
Cx_int(115) <= ( Ax(115) and Bx_int(NUM_BITS-1) ) xor Cx_int(114);
Cx_int(116) <= ( Ax(116) and Bx_int(NUM_BITS-1) ) xor Cx_int(115);
Cx_int(117) <= ( Ax(117) and Bx_int(NUM_BITS-1) ) xor Cx_int(116);
Cx_int(118) <= ( Ax(118) and Bx_int(NUM_BITS-1) ) xor Cx_int(117);
Cx_int(119) <= ( Ax(119) and Bx_int(NUM_BITS-1) ) xor Cx_int(118);
Cx_int(120) <= ( Ax(120) and Bx_int(NUM_BITS-1) ) xor Cx_int(119);
Cx_int(121) <= ( Ax(121) and Bx_int(NUM_BITS-1) ) xor Cx_int(120);
Cx_int(122) <= ( Ax(122) and Bx_int(NUM_BITS-1) ) xor Cx_int(121);
Cx_int(123) <= ( Ax(123) and Bx_int(NUM_BITS-1) ) xor Cx_int(122);
Cx_int(124) <= ( Ax(124) and Bx_int(NUM_BITS-1) ) xor Cx_int(123);
Cx_int(125) <= ( Ax(125) and Bx_int(NUM_BITS-1) ) xor Cx_int(124);
Cx_int(126) <= ( Ax(126) and Bx_int(NUM_BITS-1) ) xor Cx_int(125);
Cx_int(127) <= ( Ax(127) and Bx_int(NUM_BITS-1) ) xor Cx_int(126);
Cx_int(128) <= ( Ax(128) and Bx_int(NUM_BITS-1) ) xor Cx_int(127);
Cx_int(129) <= ( Ax(129) and Bx_int(NUM_BITS-1) ) xor Cx_int(128);
Cx_int(130) <= ( Ax(130) and Bx_int(NUM_BITS-1) ) xor Cx_int(129);
Cx_int(131) <= ( Ax(131) and Bx_int(NUM_BITS-1) ) xor Cx_int(130);
Cx_int(132) <= ( Ax(132) and Bx_int(NUM_BITS-1) ) xor Cx_int(131);
Cx_int(133) <= ( Ax(133) and Bx_int(NUM_BITS-1) ) xor Cx_int(132);
Cx_int(134) <= ( Ax(134) and Bx_int(NUM_BITS-1) ) xor Cx_int(133);
Cx_int(135) <= ( Ax(135) and Bx_int(NUM_BITS-1) ) xor Cx_int(134);
Cx_int(136) <= ( Ax(136) and Bx_int(NUM_BITS-1) ) xor Cx_int(135);
Cx_int(137) <= ( Ax(137) and Bx_int(NUM_BITS-1) ) xor Cx_int(136);
Cx_int(138) <= ( Ax(138) and Bx_int(NUM_BITS-1) ) xor Cx_int(137);
Cx_int(139) <= ( Ax(139) and Bx_int(NUM_BITS-1) ) xor Cx_int(138);
Cx_int(140) <= ( Ax(140) and Bx_int(NUM_BITS-1) ) xor Cx_int(139);
Cx_int(141) <= ( Ax(141) and Bx_int(NUM_BITS-1) ) xor Cx_int(140);
Cx_int(142) <= ( Ax(142) and Bx_int(NUM_BITS-1) ) xor Cx_int(141);
Cx_int(143) <= ( Ax(143) and Bx_int(NUM_BITS-1) ) xor Cx_int(142);
Cx_int(144) <= ( Ax(144) and Bx_int(NUM_BITS-1) ) xor Cx_int(143);
Cx_int(145) <= ( Ax(145) and Bx_int(NUM_BITS-1) ) xor Cx_int(144);
Cx_int(146) <= ( Ax(146) and Bx_int(NUM_BITS-1) ) xor Cx_int(145);
Cx_int(147) <= ( Ax(147) and Bx_int(NUM_BITS-1) ) xor Cx_int(146);
Cx_int(148) <= ( Ax(148) and Bx_int(NUM_BITS-1) ) xor Cx_int(147);
Cx_int(149) <= ( Ax(149) and Bx_int(NUM_BITS-1) ) xor Cx_int(148);
Cx_int(150) <= ( Ax(150) and Bx_int(NUM_BITS-1) ) xor Cx_int(149);
Cx_int(151) <= ( Ax(151) and Bx_int(NUM_BITS-1) ) xor Cx_int(150);
Cx_int(152) <= ( Ax(152) and Bx_int(NUM_BITS-1) ) xor Cx_int(151);
Cx_int(153) <= ( Ax(153) and Bx_int(NUM_BITS-1) ) xor Cx_int(152);
Cx_int(154) <= ( Ax(154) and Bx_int(NUM_BITS-1) ) xor Cx_int(153);
Cx_int(155) <= ( Ax(155) and Bx_int(NUM_BITS-1) ) xor Cx_int(154);
Cx_int(156) <= ( Ax(156) and Bx_int(NUM_BITS-1) ) xor Cx_int(155);
Cx_int(157) <= ( Ax(157) and Bx_int(NUM_BITS-1) ) xor Cx_int(156);
Cx_int(158) <= ( Ax(158) and Bx_int(NUM_BITS-1) ) xor Cx_int(157);
Cx_int(159) <= ( Ax(159) and Bx_int(NUM_BITS-1) ) xor Cx_int(158);
Cx_int(160) <= ( Ax(160) and Bx_int(NUM_BITS-1) ) xor Cx_int(159);
Cx_int(161) <= ( Ax(161) and Bx_int(NUM_BITS-1) ) xor Cx_int(160);
Cx_int(162) <= ( Ax(162) and Bx_int(NUM_BITS-1) ) xor Cx_int(161);
end if;
if counter = "10100010" then
done_int <= '1';
end if;
end if;
end if;
end process;
SHIFT_REGISTER: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
Bx_shift <= Bx;
else
Bx_shift <= Bx_shift(NUM_BITS-2 downto 0) & '0'; -- carga paralela
end if;
end if;
end process;
end behave;
|
gpl-3.0
|
siavooshpayandehazad/high_level_test_pattern_gen
|
Test/AP_Alu.vhd
|
1
|
4627
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.LIB.ALL;
ENTITY AP_Alu IS
PORT(
clock : IN std_logic;
rst : IN std_logic;
OP_A : IN AP_data_width;
OP_B : IN AP_data_width;
ALU_OP : IN std_logic_vector(3 downto 0);
RESULT : OUT AP_data_width;
carry_out : OUT std_logic;
zero_out : OUT std_logic;
sign_out : OUT std_logic;
overflow_out : OUT std_logic
);
END AP_Alu;
ARCHITECTURE behave OF AP_Alu IS
signal carry, zero, sign, overflow : std_logic;
signal carry_new, zero_new, sign_new, overflow_new : std_logic;
BEGIN
alu_process : process(OP_A, OP_B, ALU_OP)
variable RESULT_INTERN : AP_data_width;
variable RESULT_TEMP : std_logic_vector(AP_WIDTH downto 0);
begin
RESULT_INTERN := (others => '0');
carry_new <= carry;
zero_new <= zero;
sign_new <= sign;
overflow_new <= overflow;
case ALU_OP is
when "0000" => -- mov
RESULT_INTERN := OP_B;
when "0001" => -- add
RESULT_TEMP := ('0' & OP_A) + OP_B;
carry_new <= RESULT_TEMP(AP_WIDTH);
sign_new <= RESULT_TEMP(AP_WIDTH-1);
overflow_new <= (not(OP_A(AP_WIDTH-1) XOR OP_B(AP_WIDTH-1)))
AND (OP_A(AP_WIDTH-1) XOR RESULT_TEMP(AP_WIDTH-1));
if RESULT_TEMP(AP_WIDTH - 1 downto 0) = "00000000" then
zero_new <= '1';
else
zero_new <= '0';
end if;
RESULT_INTERN := RESULT_TEMP(AP_WIDTH-1 downto 0);
when "0010" | "0011" => -- sub, cmp
RESULT_TEMP := ('0' & OP_A) - OP_B;
carry_new <= RESULT_TEMP(AP_WIDTH);
sign_new <= RESULT_TEMP(AP_WIDTH-1);
overflow_new <= (OP_A(AP_WIDTH-1) XOR OP_B(AP_WIDTH-1))
AND (OP_A(AP_WIDTH-1) XOR RESULT_TEMP(AP_WIDTH-1));
if RESULT_TEMP(AP_WIDTH - 1 downto 0) = "00000000" then
zero_new <= '1';
else
zero_new <= '0';
end if;
if ALU_OP = "0010" then
RESULT_INTERN := RESULT_TEMP(AP_WIDTH-1 downto 0);
else
RESULT_INTERN := OP_A; -- bei Alu-Ops ist RF_en immer gesetzt
end if;
when "0100" => -- and
RESULT_INTERN := OP_A AND OP_B;
when "0101" => -- or
RESULT_INTERN := OP_A OR OP_B;
when "0110" => -- xor
RESULT_INTERN := OP_A XOR OP_B;
when "0111" => -- not
RESULT_INTERN := NOT OP_B;
when "1000" => -- shl
RESULT_INTERN := OP_A(AP_WIDTH-2 downto 0) & carry;
carry_new <= OP_A(AP_WIDTH-1);
when "1001" => -- shr
RESULT_INTERN := carry & OP_A(AP_WIDTH-1 downto 1);
carry_new <= OP_A(0);
when "1010" => -- asr
RESULT_INTERN := OP_A(AP_WIDTH-1) & OP_A(AP_WIDTH-1 downto 1);
carry_new <= OP_A(0);
when "1011" => -- inc
RESULT_TEMP := ('0' & OP_A) + 1;
carry_new <= RESULT_TEMP(AP_WIDTH);
sign_new <= RESULT_TEMP(AP_WIDTH-1);
overflow_new <= (not(OP_A(AP_WIDTH-1) XOR OP_B(AP_WIDTH-1)))
AND (OP_A(AP_WIDTH-1) XOR RESULT_TEMP(AP_WIDTH-1));
if RESULT_TEMP(AP_WIDTH - 1 downto 0) = "00000000" then
zero_new <= '1';
else
zero_new <= '0';
end if;
RESULT_INTERN := RESULT_TEMP(AP_WIDTH-1 downto 0);
when "1100" => -- dec
RESULT_TEMP := ('0' & OP_A) - 1;
carry_new <= RESULT_TEMP(AP_WIDTH);
sign_new <= RESULT_TEMP(AP_WIDTH-1);
overflow_new <= (OP_A(AP_WIDTH-1) XOR OP_B(AP_WIDTH-1))
AND (OP_A(AP_WIDTH-1) XOR RESULT_TEMP(AP_WIDTH-1));
if RESULT_TEMP(AP_WIDTH - 1 downto 0) = "00000000" then
zero_new <= '1';
else
zero_new <= '0';
end if;
RESULT_INTERN := RESULT_TEMP(AP_WIDTH-1 downto 0);
when "1101" =>
carry_new <= '1';
RESULT_INTERN := OP_A;
when "1110" =>
carry_new <= '0';
RESULT_INTERN := OP_A;
-- when "1111" =>
when others =>
end case;
RESULT <= RESULT_INTERN;
end process;
flag_process : process(clock, rst)
begin
if (rst = '1') then
carry <= '0';
zero <= '0';
sign <= '0';
overflow <= '0';
elsif (clock'event and clock = '1') then
carry <= carry_new;
zero <= zero_new;
sign <= sign_new;
overflow <= overflow_new;
end if;
end process;
carry_out <= carry;
zero_out <= zero;
sign_out <= sign;
overflow_out <= overflow;
END behave;
|
gpl-3.0
|
xcthulhu/lambda-geda
|
top_mod.vhdl
|
1
|
5690
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.common_decs.all;
use work.clocksim_decs.all;
library unisim;
use unisim.Vcomponents.all;
entity top_mod is
port
(
-- External Clock
clk : in std_logic;
-- Interupt
irq : out std_logic;
-- Armadeus handshaking
imx_data : inout imx_chan;
imx_address : in std_logic_vector(11 downto 0); -- LSB not used
imx_cs_n : in std_logic;
imx_oe_n : in std_logic;
imx_eb3_n : in std_logic;
-- External pins
---- Inputs
a_in, a_inb,
b_in, b_inb : in std_logic;
SCLK_in, SCLK_inb : in std_logic;
STROBE_in, STROBE_inb : in std_logic;
---- Outputs
a_out, a_outb,
b_out, b_outb : out std_logic;
SCLK_out, SCLK_outb : out std_logic;
STROBE_out, STROBE_outb : out std_logic
);
end entity;
architecture RTL of top_mod is
-- Components
component rstgen_syscon
generic (invert_reset : std_logic := '0');
port (
clk : in std_logic;
sysc : out syscon
);
end component;
component wishbone_wrapper
port (
sysc : in syscon;
imx_data : inout imx_chan;
imx : in imx_in;
wbr : in wbrs;
wbw : out wbws
);
end component;
component irq_mngr
generic(
id : device_id := x"1009";
irq_level : std_logic := '1'
);
port (
sysc : in syscon;
wbw : in wbws;
wbr : out wbrs;
irqport : in write_chan;
irq : out std_logic
);
end component;
component intercon
port (
sysc : in syscon;
irq_wbr, fifo_wbr : in wbrs;
irq_wbw, fifo_wbw : out wbws;
irq_sysc, fifo_sysc,
wsysc : out syscon;
wwbr : out wbrs;
wwbw : in wbws
);
end component;
component wb_fifo_chain is
generic (id : device_id := x"0523";
addrdepth : integer := 9
);
port
(
sysc : in syscon;
a_in, b_in,
SCLK, STROBE : in std_logic;
irqport : out write_chan;
wbw : in wbws;
wbr : out wbrs
);
end component;
component clocksim is
generic (div : natural := 100);
port (sysc : in syscon;
SCLK, STROBE, A, B : out std_logic);
end component;
-- External Pins
signal xa_in, xb_in, xSCLK_in, xSTROBE_in : std_logic;
signal xa_out, xb_out, xSCLK_out, xSTROBE_out : std_logic;
-- IRQ communication
signal irqport : write_chan;
---- Intercon
signal sysc, irq_sysc, fifo_sysc, wsysc : syscon;
signal wwbr, irq_wbr, fifo_wbr : wbrs;
signal wwbw, irq_wbw, fifo_wbw : wbws;
signal imx : imx_in;
begin
imx.address <= imx_address;
imx.cs_n <= imx_cs_n;
imx.oe_n <= imx_oe_n;
imx.eb3_n <= imx_eb3_n;
IO_L01X_0 : IBUFDS
port map ( I => a_in,
IB => a_inb,
O => xa_in);
IO_L03X_0 : IBUFDS
port map ( I => b_in,
IB => b_inb,
O => xb_in);
IO_L07X_0 : IBUFDS
port map ( I => SCLK_in,
IB => SCLK_inb,
O => xSCLK_in);
IO_L15X_0 : IBUFDS
port map ( I => STROBE_in,
IB => STROBE_inb,
O => xSTROBE_in);
rstgen00 : rstgen_syscon
generic map (invert_reset => '0')
port map ( clk => clk,
sysc => sysc);
intercon00 : intercon
port map ( sysc => sysc,
irq_wbr => irq_wbr,
irq_wbw => irq_wbw,
irq_sysc => irq_sysc,
fifo_wbr => fifo_wbr,
fifo_wbw => fifo_wbw,
fifo_sysc => fifo_sysc,
wwbr => wwbr,
wwbw => wwbw,
wsysc => wsysc);
wrapper : wishbone_wrapper
port map ( sysc => wsysc,
imx_data => imx_data,
imx => imx,
wbw => wwbw,
wbr => wwbr);
irq_mngr00 : irq_mngr
generic map ( id => x"1009",
irq_level => '1')
port map ( sysc => irq_sysc,
wbr => irq_wbr,
wbw => irq_wbw,
irqport => irqport,
irq => irq);
wb_fifo_chain00 : wb_fifo_chain
generic map (
id => x"0523",
addrdepth => 9
)
port map (
sysc => fifo_sysc,
a_in => xa_in,
b_in => xb_in,
STROBE => xSTROBE_in,
SCLK => xSCLK_in,
irqport => irqport,
wbw => fifo_wbw,
wbr => fifo_wbr
);
-- Output System
SCLK_LVDS_OUT : OBUFDS
port map (I => xSCLK_out,
O => SCLK_out,
OB => SCLK_outb);
STROBE_LVDS_OUT : OBUFDS
port map (I => xSTROBE_out,
O => STROBE_out,
OB => STROBE_outb);
A_LVDS_OUT : OBUFDS
port map (I => xa_out,
O => a_out,
OB => a_outb);
B_LVDS_OUT : OBUFDS
port map (I => xb_out,
O => b_out,
OB => b_outb);
CLOCKSIMULATOR : clocksim
generic map (div => 100000000)
port map (sysc => sysc,
SCLK => xSCLK_out,
STROBE => xSTROBE_out,
A => xa_out,
B => xb_out);
end architecture;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TP4/normalizer/normalizer.vhd
|
1
|
2848
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--This component normalizes the vector components according to the steps used in cordic algorithm
entity normalizer is
generic(TOTAL_BITS: integer := 32; FRACTIONAL_BITS: integer := 16);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
steps_applied : in integer := 0;
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end normalizer;
architecture normalizer_arq of normalizer is
signal lut_index : integer := 0;
signal scaling_values_lut_value : std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
component scaling_values_lut is
generic(TOTAL_BITS: integer := 32);
port(
steps: in integer := 0;
scaling_value: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
begin
scaling_values_lut_0 : scaling_values_lut
generic map(TOTAL_BITS => 32)
port map(
steps => lut_index,
scaling_value => scaling_values_lut_value
);
process (x_in, y_in, steps_applied, lut_index, scaling_values_lut_value) is
variable x_signed : signed(TOTAL_BITS - 1 downto 0) := (others => '0');
variable y_signed : signed(TOTAL_BITS - 1 downto 0) := (others => '0');
variable scaling_value_signed : signed(TOTAL_BITS - 1 downto 0) := (others => '0');
variable scaled_x : signed(TOTAL_BITS * 2 - 1 downto 0) := (others => '0');
variable scaled_y : signed(TOTAL_BITS * 2 - 1 downto 0) := (others => '0');
variable shifted_x : signed(TOTAL_BITS * 2 - 1 downto 0) := (others => '0');
variable shifted_y : signed(TOTAL_BITS * 2 - 1 downto 0) := (others => '0');
begin
lut_index <= steps_applied;
x_signed := signed(x_in);
y_signed := signed(y_in);
scaling_value_signed := signed(scaling_values_lut_value);
--report "X: " & integer'image(x_integer);
--report "Y: " & integer'image(y_integer);
--report "SV: " & integer'image(scaling_value_integer);
scaled_x := x_signed * scaling_value_signed;
scaled_y := y_signed * scaling_value_signed;
shifted_x := shift_right(scaled_x,FRACTIONAL_BITS);
shifted_y := shift_right(scaled_y,FRACTIONAL_BITS);
x_out <= std_logic_vector(shifted_x(TOTAL_BITS - 1 downto 0));
y_out <= std_logic_vector(shifted_y(TOTAL_BITS - 1 downto 0));
end process;
end architecture;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TP4/angle_step_applier/angle_step_applier_tb.vhd
|
1
|
3287
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity angle_step_applier_tb is
end entity;
architecture angle_step_applier_tb_arq of angle_step_applier_tb is
signal x_in: std_logic_vector(31 downto 0) := (others => '0');
signal y_in: std_logic_vector(31 downto 0) := (others => '0');
signal z_in: std_logic_vector(31 downto 0) := (others => '0');
signal step_index : integer := 0;
signal x_out : std_logic_vector(31 downto 0) := (others => '0');
signal y_out : std_logic_vector(31 downto 0) := (others => '0');
signal z_out : std_logic_vector(31 downto 0) := (others => '0');
component angle_step_applier is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
z_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
step_index : in integer := 0;
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
z_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for angle_step_applier_0 : angle_step_applier use entity work.angle_step_applier;
begin
angle_step_applier_0 : angle_step_applier
port map(
x_in => x_in,
y_in => y_in,
z_in => z_in,
step_index => step_index,
x_out => x_out,
y_out => y_out,
z_out => z_out
);
process
type pattern_type is record
si : integer;
xi : std_logic_vector(31 downto 0);
yi : std_logic_vector(31 downto 0);
zi : std_logic_vector(31 downto 0);
xo : std_logic_vector(31 downto 0);
yo : std_logic_vector(31 downto 0);
zo : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
(0,
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000001011010000000000000000"),
(0,
"00000000000000010000000000000000",
"00000000000000000000000000000000",
"00000000001011010000000000000000",
"00000000000000010000000000000000",
"00000000000000010000000000000000",
"00000000000000000000000000000000"),
(0,
"00000000000000010000000000000000",
"00000000000000010000000000000000",
"00000000001011010000000000000000",
"00000000000000000000000000000000",
"00000000000000100000000000000000",
"00000000000000000000000000000000")
);
begin
for i in patterns'range loop
-- Set the inputs.
x_in <= patterns(i).xi;
y_in <= patterns(i).yi;
z_in <= patterns(i).zi;
step_index <= patterns(i).si;
wait for 1 ns;
assert patterns(i).xo = x_out report "BAD X, GOT: " & integer'image(to_integer(signed(x_out)));
assert patterns(i).yo = y_out report "BAD Y, GOT: " & integer'image(to_integer(signed(y_out)));
assert patterns(i).zo = z_out report "BAD Z, GOT: " & integer'image(to_integer(signed(z_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/biaser/biaser_tb.vhd
|
1
|
1535
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity biaser_tb is
end entity;
architecture biaser_tb_arq of biaser_tb is
signal operation : std_logic := '0';
signal exp_in: std_logic_vector(2 downto 0) := (others => '0');
signal exp_out: std_logic_vector(2 downto 0) := (others => '0');
component biaser is
generic(
EXP_BITS: natural := 6
);
port (
operation : in std_logic;
exp_in: in std_logic_vector(EXP_BITS - 1 downto 0);
exp_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
for biaser_0: biaser use entity work.biaser;
begin
biaser_0: biaser
generic map(EXP_BITS => 3)
port map(
operation => operation,
exp_in => exp_in,
exp_out => exp_out
);
process
type pattern_type is record
o : std_logic;
ei : std_logic_vector(2 downto 0);
eo : std_logic_vector(2 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
('1',"000","101"),
('1',"001","110"),
('0',"000","011")
);
begin
for i in patterns'range loop
-- Set the inputs.
operation <= patterns(i).o;
exp_in <= patterns(i).ei;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert exp_out = patterns(i).eo report "BAD EXPONENT: " & integer'image(to_integer(unsigned(exp_out))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
pwuertz/digitizer2fw
|
sim/ft2232fifo_tb.vhd
|
1
|
5528
|
-------------------------------------------------------------------------------
-- FT2232H Sync FIFO Interface test bench
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
entity ft2232fifo_tb is
end ft2232fifo_tb;
architecture ft2232fifo_tb_arch of ft2232fifo_tb is
component ft2232fifo
port (
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0);
-- application/fifo interface
rst: in std_logic;
fifo_in_wr_en: out std_logic;
fifo_in_full: in std_logic;
fifo_in_data: out std_logic_vector(7 downto 0);
fifo_out_rd_en: out std_logic;
fifo_out_empty: in std_logic;
fifo_out_data: in std_logic_vector(7 downto 0)
);
end component;
signal usb_clk: std_logic := '0';
signal usb_oe_n: std_logic;
signal usb_rd_n: std_logic;
signal usb_wr_n: std_logic;
signal usb_rxf_n: std_logic := '1';
signal usb_txe_n: std_logic := '1';
signal usb_d: std_logic_vector(7 downto 0) := (others => '0');
signal usb_d_out: std_logic_vector(7 downto 0) := (others => '0');
signal rst: std_logic := '0';
signal fifo_in_wr_en: std_logic;
signal fifo_in_full: std_logic := '1';
signal fifo_in_data: std_logic_vector(7 downto 0);
signal fifo_out_rd_en: std_logic;
signal fifo_out_empty: std_logic := '1';
signal fifo_out_data: std_logic_vector(7 downto 0) := (others => '0');
constant clk_period : time := 16 ns;
begin
ft2232fifo_inst: ft2232fifo
port map (
-- ftdi interface
usb_clk => usb_clk,
usb_oe_n => usb_oe_n,
usb_rd_n => usb_rd_n,
usb_wr_n => usb_wr_n,
usb_rxf_n => usb_rxf_n,
usb_txe_n => usb_txe_n,
usb_d => usb_d,
-- application/fifo interface
rst => rst,
fifo_in_wr_en => fifo_in_wr_en,
fifo_in_full => fifo_in_full,
fifo_in_data => fifo_in_data,
fifo_out_rd_en => fifo_out_rd_en,
fifo_out_empty => fifo_out_empty,
fifo_out_data => fifo_out_data
);
clk_process: process
begin
usb_clk <= '0';
wait for clk_period/2;
usb_clk <= '1';
wait for clk_period/2;
end process;
process(usb_oe_n, usb_d_out, usb_rxf_n)
begin
usb_d <= (others => 'Z');
if (usb_oe_n = '0') then
if (usb_rxf_n = '1') then
usb_d <= (others => 'X');
else
usb_d <= usb_d_out;
end if;
end if;
end process;
data_from_usb: process(usb_clk)
begin
if rising_edge(usb_clk) then
if (usb_rd_n = '0') and (usb_rxf_n = '0') then
usb_d_out <= std_logic_vector(unsigned(usb_d_out) + 1);
end if;
end if;
end process;
data_received: process(usb_clk)
variable data_expected: integer := 0;
variable data_received: integer;
begin
if rising_edge(usb_clk) then
if (fifo_in_wr_en = '1') and (fifo_in_full = '0') then
data_received := to_integer(unsigned(fifo_in_data));
report "RX: " & integer'image(data_received);
assert (data_received = data_expected) report "recieved bad data" severity failure;
data_expected := data_expected + 1;
end if;
end if;
end process;
data_from_fifo: process(usb_clk)
begin
if rising_edge(usb_clk) then
if (fifo_out_rd_en = '1') and (fifo_out_empty = '0') then
fifo_out_data <= std_logic_vector(unsigned(fifo_out_data) + 1);
end if;
end if;
end process;
data_transmitted: process(usb_clk)
variable data_expected: integer := 0;
variable data_transmitted: integer;
begin
if rising_edge(usb_clk) then
if (usb_wr_n = '0') and (usb_txe_n = '0') then
data_transmitted := to_integer(unsigned(usb_d));
report "TX: " & integer'image(data_transmitted);
assert (data_transmitted = data_expected) report "transmitted bad data" severity failure;
data_expected := data_expected + 1;
end if;
end if;
end process;
stimulus: process
constant usb_txe_n_pattern: std_logic_vector := "111100000011111111110000000000000000000000";
constant usb_rxf_n_pattern: std_logic_vector := "111111111111111111111110000000000000001111";
constant fifo_in_full_pattern: std_logic_vector := "000000000000000000000000000000000000000000";
constant fifo_out_empty_pattern: std_logic_vector := "000000000000000000000000000111000000000000";
begin
usb_txe_n <= usb_txe_n_pattern(0);
usb_rxf_n <= usb_rxf_n_pattern(0);
fifo_in_full <= fifo_in_full_pattern(0);
fifo_out_empty <= fifo_out_empty_pattern(0);
for i in usb_txe_n_pattern'range loop
wait for clk_period;
usb_txe_n <= usb_txe_n_pattern(i);
usb_rxf_n <= usb_rxf_n_pattern(i);
fifo_in_full <= fifo_in_full_pattern(i);
fifo_out_empty <= fifo_out_empty_pattern(i);
end loop;
assert false report "Stimulus finished" severity note;
wait;
end process;
end ft2232fifo_tb_arch;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TP3/addition/class_adder/class_adder.vhd
|
1
|
689
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity class_adder is
generic(N: integer:= 4);
port(
number1_in: in std_logic_vector(N-1 downto 0);
number2_in: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
result: out std_logic_vector(N-1 downto 0);
cout: out std_logic
);
end;
architecture class_adder_arq of class_adder is
signal aux: unsigned (N+1 downto 0) := to_unsigned(0, N+2);
begin
aux <= ('0' & unsigned(number1_in) & cin) + ('0' & unsigned(number2_in) & '1');
result <= std_logic_vector( aux (N downto 1) );
cout <= aux (N+1);
end;
|
gpl-3.0
|
ruygargar/LCSE_lab
|
rs232/rs232_top.vhd
|
1
|
4558
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RS232top is
port (
Reset : in std_logic; -- Low_level-active asynchronous reset
Clk : in std_logic; -- System clock (20MHz), rising edge used
Data_in : in std_logic_vector(7 downto 0); -- Data to be sent
Valid_D : in std_logic; -- Handshake signal
-- from guest system, low when data is valid
Ack_in : out std_logic; -- ACK for data received, low once data
-- has been stored
TX_RDY : out std_logic; -- System ready to transmit
TD : out std_logic; -- RS232 Transmission line
RD : in std_logic; -- RS232 Reception line
Data_out : out std_logic_vector(7 downto 0); -- Received data
Data_read : in std_logic; -- Data read for guest system
Full : out std_logic; -- Full internal memory
Empty : out std_logic); -- Empty internal memory
end RS232top;
architecture RTL of RS232top is
------------------------------------------------------------------------
-- Components for Transmitter Block
------------------------------------------------------------------------
component RS232_TX
port (
Clk : in std_logic;
Reset : in std_logic;
Start : in std_logic;
Data : in std_logic_vector(7 downto 0);
EOT : out std_logic;
TX : out std_logic);
end component;
------------------------------------------------------------------------
-- Components for Receiver Block
------------------------------------------------------------------------
component ShiftRegister
port (
Reset : in std_logic;
Clk : in std_logic;
Enable : in std_logic;
D : in std_logic;
Q : out std_logic_vector(7 downto 0));
end component;
component RS232_RX
port (
Clk : in std_logic;
Reset : in std_logic;
LineRD_in : in std_logic;
Valid_out : out std_logic;
Code_out : out std_logic;
Store_out : out std_logic);
end component;
component fifo
port (
clk : IN std_logic;
rst : IN std_logic;
din : IN std_logic_VECTOR(7 downto 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(7 downto 0);
full : OUT std_logic;
empty : OUT std_logic);
end component;
------------------------------------------------------------------------
-- Internal Signals
------------------------------------------------------------------------
signal Data_FF : std_logic_vector(7 downto 0);
signal StartTX : std_logic; -- start signal for transmitter
signal LineRD_in : std_logic; -- internal RX line
signal Valid_out : std_logic; -- valid bit @ receiver
signal Code_out : std_logic; -- bit @ receiver output
signal sinit : std_logic; -- fifo reset
signal Fifo_in : std_logic_vector(7 downto 0);
signal Fifo_write : std_logic;
signal TX_RDY_i : std_logic;
begin -- RTL
Transmitter: RS232_TX
port map (
Clk => Clk,
Reset => Reset,
Start => StartTX,
Data => Data_FF,
EOT => TX_RDY_i,
TX => TD);
Receiver: RS232_RX
port map (
Clk => Clk,
Reset => Reset,
LineRD_in => LineRD_in,
Valid_out => Valid_out,
Code_out => Code_out,
Store_out => Fifo_write);
Shift: ShiftRegister
port map (
Reset => Reset,
Clk => Clk,
Enable => Valid_Out,
D => Code_Out,
Q => Fifo_in);
sinit <= not reset;
Internal_memory: fifo
port map (
clk => clk,
rst => sinit,
din => Fifo_in,
wr_en => Fifo_write,
rd_en => Data_read,
dout => Data_out,
full => Full,
empty => Empty);
-- purpose: Clocking process for input protocol
Clocking : process (Clk, Reset)
begin
if Reset = '0' then -- asynchronous reset (active low)
Data_FF <= (others => '0');
LineRD_in <= '1';
Ack_in <= '1';
elsif Clk'event and Clk = '1' then -- rising edge clock
LineRD_in <= RD;
if Valid_D = '0' and TX_RDY_i = '1' then
Data_FF <= Data_in;
Ack_in <= '0';
StartTX <= '1';
else
Ack_in <= '1';
StartTX <= '0';
end if;
end if;
end process Clocking;
TX_RDY <= TX_RDY_i;
end RTL;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TP3/multiplication/class_adder/class_adder.vhd
|
1
|
681
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity class_adder is
generic(N: integer:= 4);
port(
number1_in: in std_logic_vector(N-1 downto 0);
number2_in: in std_logic_vector(N-1 downto 0);
cin: in std_logic;
result: out std_logic_vector(N-1 downto 0);
cout: out std_logic
);
end;
architecture class_adder_arq of class_adder is
signal aux: signed (N+1 downto 0) := to_signed(0, N+2);
begin
aux <= ('0' & signed(number1_in) & cin) + ('0' & signed(number2_in) & '1');
result <= std_logic_vector( aux (N downto 1) );
cout <= aux (N+1);
end;
|
gpl-3.0
|
ruygargar/LCSE_lab
|
doc/PIC/PICtop.vhd
|
1
|
1635
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity PICtop is
port (
Reset : in std_logic; -- Asynchronous, active low
Clk : in std_logic; -- System clock, 20 MHz, rising_edge
RS232_RX : in std_logic; -- RS232 RX line
RS232_TX : out std_logic; -- RS232 TX line
switches : out std_logic_vector(7 downto 0); -- Switch status bargraph
Temp_L : out std_logic_vector(6 downto 0); -- Less significant figure of T_STAT
Temp_H : out std_logic_vector(6 downto 0)); -- Most significant figure of T_STAT
end PICtop;
architecture behavior of PICtop is
component RS232top
port (
Reset : in std_logic;
Clk : in std_logic;
Data_in : in std_logic_vector(7 downto 0);
Valid_D : in std_logic;
Ack_in : out std_logic;
TX_RDY : out std_logic;
TD : out std_logic;
RD : in std_logic;
Data_out : out std_logic_vector(7 downto 0);
Data_read : in std_logic;
Full : out std_logic;
Empty : out std_logic);
end component;
begin -- behavior
RS232_PHY: RS232top
port map (
Reset => Reset,
Clk => Clk,
Data_in => TX_Data,
Valid_D => Valid_D,
Ack_in => Ack_out,
TX_RDY => TX_RDY,
TD => RS232_TX,
RD => RS232_RX,
Data_out => RCVD_Data,
Data_read => Data_read,
Full => RX_Full,
Empty => RX_Empty);
end behavior;
|
gpl-3.0
|
pwuertz/digitizer2fw
|
src/rtl/ft2232_communication.vhd
|
1
|
5720
|
-------------------------------------------------------------------------------
-- FT2232 Communication Interface
--
-- (De)serializes data to/from USB interface for writing/reading registers
--
-- Author: Peter Würtz, TU Kaiserslautern (2016)
-- Distributed under the terms of the GNU General Public License Version 3.
-- The full license is in the file COPYING.txt, distributed with this software.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.communication_pkg.all;
entity ft2232_communication is
port (
clk: in std_logic;
rst: in std_logic;
error: out std_logic;
-- application bus interface
slave_addr: out unsigned(5 downto 0);
slave_port: out unsigned(5 downto 0);
comm_to_slave: out comm_to_slave_t;
comm_from_slave: in comm_from_slave_t;
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0)
);
end ft2232_communication;
architecture ft2232_communication_arch of ft2232_communication is
component ft2232fifo
port (
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0);
-- application/fifo interface
rst: in std_logic;
fifo_in_wr_en: out std_logic;
fifo_in_full: in std_logic;
fifo_in_data: out std_logic_vector(7 downto 0);
fifo_out_rd_en: out std_logic;
fifo_out_empty: in std_logic;
fifo_out_data: in std_logic_vector(7 downto 0)
);
end component;
component fifo_16_to_8
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(15 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
dout: out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component;
component fifo_8_to_16
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(7 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
dout: out std_logic_vector(15 downto 0);
full: out std_logic;
empty: out std_logic
);
end component;
component communication
port (
clk: in std_logic;
rst: in std_logic;
error: out std_logic;
-- application bus interface
slave_addr: out unsigned(5 downto 0);
slave_port: out unsigned(5 downto 0);
comm_to_slave: out comm_to_slave_t;
comm_from_slave: in comm_from_slave_t;
-- fifo interface
fifo_out_wr_en: out std_logic;
fifo_out_full: in std_logic;
fifo_out_data: out std_logic_vector(COMM_BUS_WIDTH-1 downto 0);
fifo_in_rd_en: out std_logic;
fifo_in_empty: in std_logic;
fifo_in_data: in std_logic_vector(COMM_BUS_WIDTH-1 downto 0)
);
end component;
signal fifo_from_usb_rd, fifo_from_usb_empty: std_logic;
signal fifo_from_usb_wr, fifo_from_usb_full: std_logic;
signal fifo_to_usb_rd, fifo_to_usb_empty: std_logic;
signal fifo_to_usb_wr, fifo_to_usb_full: std_logic;
signal fifo_to_usb_dout, fifo_from_usb_din: std_logic_vector(7 downto 0);
signal fifo_to_usb_din, fifo_from_usb_dout: std_logic_vector(15 downto 0);
begin
communication_inst: communication
port map (
clk => clk,
rst => rst,
error => error,
-- application register interface
slave_addr => slave_addr,
slave_port => slave_port,
comm_to_slave => comm_to_slave,
comm_from_slave => comm_from_slave,
-- fifo interface
fifo_out_wr_en => fifo_to_usb_wr,
fifo_out_full => fifo_to_usb_full,
fifo_out_data => fifo_to_usb_din,
fifo_in_rd_en => fifo_from_usb_rd,
fifo_in_empty => fifo_from_usb_empty,
fifo_in_data => fifo_from_usb_dout
);
ft2232fifo_inst: ft2232fifo
port map (
-- ftdi interface
usb_clk => usb_clk,
usb_oe_n => usb_oe_n,
usb_rd_n => usb_rd_n,
usb_wr_n => usb_wr_n,
usb_rxf_n => usb_rxf_n,
usb_txe_n => usb_txe_n,
usb_d => usb_d,
-- application/fifo interface
rst => rst,
fifo_in_wr_en => fifo_from_usb_wr,
fifo_in_full => fifo_from_usb_full,
fifo_in_data => fifo_from_usb_din,
fifo_out_rd_en => fifo_to_usb_rd,
fifo_out_empty => fifo_to_usb_empty,
fifo_out_data => fifo_to_usb_dout
);
fifo_to_usb: fifo_16_to_8
port map (
rst => rst,
wr_clk => clk,
rd_clk => usb_clk,
din => fifo_to_usb_din,
wr_en => fifo_to_usb_wr,
rd_en => fifo_to_usb_rd,
dout => fifo_to_usb_dout,
full => fifo_to_usb_full,
empty => fifo_to_usb_empty
);
fifo_from_usb: fifo_8_to_16
port map (
rst => rst,
wr_clk => usb_clk,
rd_clk => clk,
din => fifo_from_usb_din,
wr_en => fifo_from_usb_wr,
rd_en => fifo_from_usb_rd,
dout => fifo_from_usb_dout,
full => fifo_from_usb_full,
empty => fifo_from_usb_empty
);
end ft2232_communication_arch;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-Lucho/TP1-Contador/decoBCD/contbcd.vhd
|
3
|
810
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity contBCD is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic
);
end;
architecture contBCD_arq of contBCD is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk,rst)
variable count: integer range 0 to 10;
begin
if rst = '1' then
s <= (others => '0');
co <= '0';
elsif rising_edge(clk) then
if ena = '1' then
count:=count + 1;
if count = 9 then
co <= '1';
elsif count = 10 then
count := 0;
co <= '0';
else
co <= '0';
end if;
end if;
end if;
s <= std_logic_vector(TO_UNSIGNED(count,4));
end process;
end;
|
gpl-3.0
|
ruygargar/LCSE_lab
|
dma/dma_tx.vhd
|
1
|
4538
|
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma_tx.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dma_tx is
Port ( Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Señales procedentes del bus del uP.
Databus : in STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : out STD_LOGIC;
WriteEnable : out STD_LOGIC;
OutputEnable : out STD_LOGIC;
-- Señales procedentes de la FSM del Controlador de Bus.
Start_TX : in STD_LOGIC;
Ready_TX : out STD_LOGIC;
End_TX : out STD_LOGIC;
-- Bus de datos y señales de handshake orientadas al transmisor del
-- RS232.
DataOut : out STD_LOGIC_VECTOR(7 downto 0);
Valid_DO : out STD_LOGIC;
Ack_DO : in STD_LOGIC);
end dma_tx;
architecture Behavioral of dma_tx is
-- Definición de los posibles estados de la FSM del Transmisor:
type Transmitter_ST is (idle, CPY_REG0, CPY_REG1, SND_REG0, SND_REG1);
signal TX_now, TX_next : Transmitter_ST;
-- Señales usadas para inferir los biestables necesarios para cada uno de
-- los registros de copia de los datos a envíar.
signal REG0, REG1 : std_logic_vector(7 downto 0);
-- Señal de enable de cada uno de los registros anteriores.
signal R0_enable, R1_enable : std_logic;
-- Tabla de direcciones:
-- El valor contenido en cada uno de los registros anteriores será recibido
-- desde su respectiva dirección de memoria.
constant R0_address : std_logic_vector(7 downto 0) := X"04";
constant R1_address : std_logic_vector(7 downto 0) := X"05";
begin
-- El Transmisor nunca modificará un valor de memoria. Únicamente lee los
-- datos necesarios de ella.
WriteEnable <= '0';
-- Proceso secuencial de la máquina de estados del Transmisor.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo. Mientras que
-- esta señal se mantenga activa, la FSM se mantiene en el estado de 'Idle',
-- y los registros se inicializan a 0.
process(Clk, Reset)
begin
if (Reset = '0') then
TX_now <= idle;
REG0 <= X"00";
REG1 <= X"00";
elsif Clk'event and Clk = '1' then
TX_now <= TX_next;
if R0_enable = '1' then
REG0 <= Databus;
end if;
if R1_enable = '1' then
REG1 <= Databus;
end if;
end if;
end process;
-- Proceso combinacional de la máquina de estados.
process(TX_now, Start_TX, REG0, REG1, Ack_DO)
begin
-- Valores preasignados por defecto.
Address <= X"00";
ChipSelect <= '0';
OutputEnable <= '0';
Ready_TX <= '0';
End_TX <= '0';
DataOut <= X"00";
Valid_DO <= '1';
R0_enable <= '0';
R1_enable <= '0';
case TX_now is
when idle =>
Ready_TX <= '1';
-- Si el Controlador de Bus da permiso para iniciar una nueva
-- transmisión...
if Start_TX = '1' then
TX_next <= CPY_REG0;
else
TX_next <= idle;
end if;
when CPY_REG0 =>
Address <= R0_address;
ChipSelect <= '1';
OutputEnable <= '1';
R0_enable <= '1';
-- Las lecturas desde memoria se realizan en un único ciclo de
-- reloj. Por tanto en el siguiente flanco de reloj, R0 habrá
-- almacenado su dato, y se debe pedir a la memoria el siguiente
-- valor.
TX_next <= CPY_REG1;
when CPY_REG1 =>
Address <= R1_address;
ChipSelect <= '1';
OutputEnable <= '1';
R1_enable <= '1';
-- Las lecturas desde memoria se realizan en un único ciclo de
-- reloj. Por tanto en el siguiente flanco de reloj, R1 habrá
-- almacenado su dato, terminando así el uso de los buses del uP,
-- pudiendo devolver su control e iniciando la tranferencia con el
-- RS232.
End_TX <= '1';
TX_next <= SND_REG0;
when SND_REG0 =>
DataOut <= REG0;
Valid_DO <= '0';
-- Si el RS232 ha aceptado el dato...
if Ack_DO = '0' then
Valid_DO <= '1';
TX_next <= SND_REG1;
else
TX_next <= SND_REG0;
end if;
when SND_REG1 =>
DataOut <= REG1;
Valid_DO <= '0';
-- Si el RS232 ha aceptado el dato...
if Ack_DO = '0' then
Valid_DO <= '1';
TX_next <= idle;
else
TX_next <= SND_REG1;
end if;
end case;
end process;
end Behavioral;
|
gpl-3.0
|
pwuertz/digitizer2fw
|
src/rtl/maxfinder_pkg.vhd
|
1
|
1352
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package maxfinder_pkg is
function log2ceil(x: natural) return natural;
component maxfinder_base
generic (
N_WINDOW_LENGTH : natural;
N_OUTPUTS : natural;
N_SAMPLE_BITS : natural;
SYNC_STAGE1: boolean := FALSE;
SYNC_STAGE2: boolean := TRUE;
SYNC_STAGE3: boolean := TRUE
);
port (
clk : in std_logic;
samples : in std_logic_vector( N_WINDOW_LENGTH * N_SAMPLE_BITS - 1 downto 0 );
threshold : in std_logic_vector( N_SAMPLE_BITS - 1 downto 0 );
max_found : out std_logic_vector( N_OUTPUTS - 1 downto 0 );
max_pos : out std_logic_vector( N_OUTPUTS * log2ceil( N_WINDOW_LENGTH / N_OUTPUTS )- 1 downto 0 );
max_adiff0 : out std_logic_vector( N_OUTPUTS * N_SAMPLE_BITS - 1 downto 0 );
max_adiff1 : out std_logic_vector( N_OUTPUTS * N_SAMPLE_BITS - 1 downto 0 );
max_sample0 : out std_logic_vector( N_OUTPUTS * N_SAMPLE_BITS - 1 downto 0 );
max_sample1 : out std_logic_vector( N_OUTPUTS * N_SAMPLE_BITS - 1 downto 0 )
);
end component;
end maxfinder_pkg;
package body maxfinder_pkg is
function log2ceil(x: natural) return natural is
begin
return natural(ceil(log2(real(x))));
end log2ceil;
end maxfinder_pkg;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TPS-2016/tps-LuGus/TP2-Voltimetro/voltage_registry_enabler.vhd
|
1
|
1037
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utility.all;
entity voltage_registry_enabler is
port (
clk_in: in std_logic;
rst_in: in std_logic;
ena_in: in std_logic;
out_1: out std_logic;
out_2: out std_logic
);
end;
architecture voltage_registry_enabler_arq of voltage_registry_enabler is
begin
--El comportamiento se puede hacer de forma logica o por diagrama karnaugh.
process(clk_in,rst_in)
variable tmp_count: integer range 0 to 33099;
begin
if rst_in = '1' then
tmp_count := 0;
elsif rising_edge(clk_in) then
if ena_in = '1' then
tmp_count:=tmp_count + 1;
if tmp_count = 33000 then
out_1 <= '1';
out_2 <= '0';
elsif tmp_count = 33001 then
out_1 <= '0';
out_2 <= '1';
elsif tmp_count = 33002 then
tmp_count := 0;
out_1 <= '0';
out_2 <= '0';
else
out_1 <= '0';
out_2 <= '0';
end if;
end if;
end if;
end process;
end;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
ghdl/lib/ghdl/src/std/env_body.vhdl
|
5
|
2191
|
-- Std.Env package declaration. This file is part of GHDL.
-- This file was written from the clause 14.3 of the VHDL LRM.
-- Copyright (C) 2014 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING. If not, write to the Free
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
package body Env is
procedure control_simulation (Is_Stop : Boolean;
Has_Status : Boolean;
Status : Integer);
attribute foreign of control_simulation : procedure is "GHDL intrinsic";
procedure control_simulation (Is_Stop : Boolean;
Has_Status : Boolean;
Status : Integer) is
begin
assert false report "must not be called" severity failure;
end control_simulation;
procedure Stop (Status : Integer) is
begin
control_simulation (True, True, Status);
end Stop;
procedure Stop is
begin
control_simulation (True, False, -1);
end Stop;
procedure Finish (status : integer) is
begin
control_simulation (False, True, Status);
end Finish;
procedure Finish is
begin
control_simulation (False, False, -1);
end Finish;
function Get_Resolution_Limit return Delay_Length;
attribute foreign of Get_Resolution_Limit : function is "GHDL intrinsic";
function Get_Resolution_Limit return Delay_Length is
begin
assert false report "must not be called" severity failure;
end Get_Resolution_Limit;
function Resolution_Limit return Delay_Length is
begin
return Get_Resolution_Limit;
end Resolution_Limit;
end package body Env;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TPS-2016/relocate/Contador_vector.vhd
|
2
|
983
|
library IEEE;
use IEEE.std_logic_1164.all;
entity contador_vector is
port(
rst_c: in std_logic;
clk_c: in std_logic;
enable_c: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end;
architecture contador_func of contador_vector is
component FFD is
port(
enable: in std_logic;
reset: in std_logic;
clk: in std_logic;
Q: out std_logic;
D: in std_logic
);
end component;
signal q0_c_aux,q1_c_aux,d0_c_aux,d1_c_aux:std_logic;
begin
ffd0: FFD port map( --nombres del FFD : enable,reset,clk,Q,D
clk => clk_c,
enable => enable_c,
reset => rst_c, --Siempre van a la izquierda los puertos de los componentes
D => d0_c_aux,
Q => q0_c_aux
);
Q(0) <= q0_c_aux;
ffd1: FFD port map(
clk=> clk_c,
enable => enable_c,
reset => rst_c,
D => d1_c_aux,
Q => q1_c_aux
);
Q(1) <= q1_c_aux;
d0_c_aux <= not(q0_c_aux);
d1_c_aux <= q1_c_aux xor q0_c_aux;
end architecture;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
ghdl/lib/ghdl/src/ieee2008/ieee_bit_context.vhdl
|
5
|
102
|
context IEEE_BIT_CONTEXT is
library IEEE;
use IEEE.NUMERIC_BIT.all;
end context IEEE_BIT_CONTEXT;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
ghdl/lib/ghdl/src/synopsys/std_logic_textio.vhdl
|
9
|
17971
|
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s);
for i in integer range 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in integer range 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in integer range 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in integer range 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
gpl-3.0
|
ruygargar/LCSE_lab
|
rs232/tb_RS232_TX.vhd
|
1
|
2660
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:22:02 11/10/2013
-- Design Name:
-- Module Name: C:/Users/Silvia/Desktop/RS232 project/RS232/tb_RS232_TX.vhd
-- Project Name: RS232
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RS232_TX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_RS232_TX IS
END tb_RS232_TX;
ARCHITECTURE behavior OF tb_RS232_TX IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RS232_TX
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
Start : IN std_logic;
Data : IN std_logic_vector(7 downto 0);
EOT : OUT std_logic;
TX : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal Start : std_logic := '0';
signal Data : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal EOT : std_logic;
signal TX : std_logic;
-- Clock period definitions
constant Clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RS232_TX PORT MAP (
Clk => Clk,
Reset => Reset,
Start => Start,
Data => Data,
EOT => EOT,
TX => TX
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
reset <= '1';
wait for Clk_period*10;
data <= "10101010";
start <= '1';
wait until EOT = '0';
start <= '0';
wait for 10 us;
data <= "00000000";
start <= '1';
wait for 10 us;
start <= '0';
wait for 110 us;
data <= "11001100";
start <= '1';
wait until EOT = '0';
start <= '0';
wait;
end process;
END;
|
gpl-3.0
|
pwuertz/digitizer2fw
|
src/rtl/sampling_pkg.vhd
|
1
|
1876
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sampling_pkg is
constant ADC_SAMPLE_BITS: integer := 12;
subtype a_sample_t is signed(ADC_SAMPLE_BITS-1 downto 0);
type adc_sample_t is
record
data: a_sample_t;
ovfl: std_logic;
end record;
function to_std_logic_vector(x: adc_sample_t) return std_logic_vector;
function to_adc_sample_t(x: std_logic_vector) return adc_sample_t;
type a_samples_t is array (natural range <>) of a_sample_t;
type adc_samples_t is array (natural range <>) of adc_sample_t;
type din_samples_t is array (natural range <>) of std_logic_vector(1 downto 0);
component sampling
port (
-- data in from pins
DIN_P: in std_logic_vector(1 downto 0);
DIN_N: in std_logic_vector(1 downto 0);
ADC_DA_P: in std_logic_vector(12 downto 0);
ADC_DA_N: in std_logic_vector(12 downto 0);
ADC_DACLK_P: in std_logic;
ADC_DACLK_N: in std_logic;
-- data in to device
app_clk: out std_logic;
samples_d: out din_samples_t(0 to 3);
samples_a: out adc_samples_t(0 to 1);
-- control
rst: in std_logic
);
end component;
end sampling_pkg;
package body sampling_pkg is
function to_std_logic_vector(x: adc_sample_t) return std_logic_vector is
variable result: std_logic_vector(ADC_SAMPLE_BITS downto 0);
begin
result(ADC_SAMPLE_BITS) := x.ovfl;
result(ADC_SAMPLE_BITS-1 downto 0) := std_logic_vector(x.data);
return result;
end to_std_logic_vector;
function to_adc_sample_t(x: std_logic_vector) return adc_sample_t is
variable result: adc_sample_t;
begin
result.ovfl := x(x'low + ADC_SAMPLE_BITS);
result.data := signed(x(x'low + ADC_SAMPLE_BITS-1 downto x'low));
return result;
end to_adc_sample_t;
end sampling_pkg;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TP3/addition/number_splitter/number_splitter_tb.vhd
|
2
|
2135
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter_tb is
end entity;
architecture number_splitter_tb_arq of number_splitter_tb is
signal number_in: std_logic_vector(22 downto 0);
signal sign_out: std_logic;
signal exp_out: std_logic_vector(5 downto 0);
signal mant_out: std_logic_vector(15 downto 0);
component number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out: out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0)
);
end component;
for number_splitter_0: number_splitter use entity work.number_splitter;
begin
number_splitter_0: number_splitter port map(
number_in => number_in,
sign_out => sign_out,
exp_out => exp_out,
mant_out => mant_out
);
process
type pattern_type is record
n : std_logic_vector(22 downto 0); --input number
s : std_logic; --output sign
m : std_logic_vector(15 downto 0); --output mantisa
e : std_logic_vector(5 downto 0); --output exponent
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
("11111111111111111111111", '1', "1111111111111111", "111111"),
("00000000000000000000000", '0', "0000000000000000", "000000"),
("10101010101010101010101", '1', "0101010101010101", "010101")
);
begin
for i in patterns'range loop
-- Set the inputs.
number_in <= patterns(i).n;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert sign_out = patterns(i).s report "BAD SIGN: " & std_logic'image(sign_out) severity error;
assert mant_out = patterns(i).m report "BAD MANTISSA: " & integer'image(to_integer(unsigned(mant_out))) severity error;
assert exp_out = patterns(i).e report "BAD EXP: " & integer'image(to_integer(unsigned(exp_out))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TP3/addition/number_swapper/number_swapper_tb.vhd
|
1
|
3865
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_swapper_tb is
end entity;
architecture number_swapper_tb_arq of number_swapper_tb is
signal man_1_in : std_logic_vector(15 downto 0) := (others => '0');
signal exp_1_in : std_logic_vector(5 downto 0) := (others => '0');
signal man_2_in : std_logic_vector(15 downto 0) := (others => '0');
signal exp_2_in : std_logic_vector(5 downto 0) := (others => '0');
signal man_greater_out : std_logic_vector(15 downto 0) := (others => '0');
signal man_smaller_out : std_logic_vector(15 downto 0) := (others => '0');
signal exp_greater_out : std_logic_vector(5 downto 0) := (others => '0');
signal exp_smaller_out : std_logic_vector(5 downto 0) := (others => '0');
component number_swapper is
generic(
TOTAL_BITS : natural := 23;
EXP_BITS : natural := 6
);
port(
man_1_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_1_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_2_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_2_in : in std_logic_vector(EXP_BITS - 1 downto 0);
man_greater_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
man_smaller_out : out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0);
exp_greater_out : out std_logic_vector(EXP_BITS - 1 downto 0);
exp_smaller_out : out std_logic_vector(EXP_BITS - 1 downto 0)
);
end component;
for number_swapper_0 : number_swapper use entity work.number_swapper;
begin
number_swapper_0 : number_swapper
generic map(TOTAL_BITS => 23, EXP_BITS => 6)
port map(
exp_1_in => exp_1_in,
exp_2_in => exp_2_in,
man_1_in => man_1_in,
man_2_in => man_2_in,
exp_greater_out => exp_greater_out,
exp_smaller_out => exp_smaller_out,
man_greater_out => man_greater_out,
man_smaller_out => man_smaller_out
);
process
type pattern_type is record
m1 : std_logic_vector(15 downto 0);
e1 : std_logic_vector(5 downto 0);
m2 : std_logic_vector(15 downto 0);
e2 : std_logic_vector(5 downto 0);
mg : std_logic_vector(15 downto 0);
ms : std_logic_vector(15 downto 0);
eg : std_logic_vector(5 downto 0);
es : std_logic_vector(5 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
("0000000000000001", "000000", "0000000000000001", "000000", "0000000000000001", "0000000000000001", "000000","000000"),
("0000000000000001", "000100", "0000000000000001", "000000", "0000000000000001", "0000000000000001", "000100","000000"),
("0000000110000000", "000011", "0000000000000001", "000001", "0000000110000000", "0000000000000001", "000011","000001"),
("0000000000000001", "000001", "0000000011000000", "000011", "0000000011000000", "0000000000000001", "000011","000001"),
("1111111111111111", "111110", "0000000000000000", "111111", "0000000000000000", "1111111111111111", "111111","111110")
);
begin
for i in patterns'range loop
-- Set the inputs.
exp_1_in <= patterns(i).e1;
exp_2_in <= patterns(i).e2;
man_1_in <= patterns(i).m1;
man_2_in <= patterns(i).m2;
wait for 1 ns;
assert patterns(i).mg = man_greater_out report "BAD MANTISSA G, GOT: " & integer'image(to_integer(unsigned(man_greater_out)));
assert patterns(i).ms = man_smaller_out report "BAD MANTISSA S, GOT: " & integer'image(to_integer(unsigned(man_smaller_out)));
assert patterns(i).eg = exp_greater_out report "BAD EXP G, GOT: " & integer'image(to_integer(unsigned(exp_greater_out)));
assert patterns(i).es = exp_smaller_out report "BAD EXP S, GOT: " & integer'image(to_integer(unsigned(exp_smaller_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
ghdl/lib/ghdl/src/vital95/vital_primitives.vhdl
|
6
|
68265
|
-- -----------------------------------------------------------------------------
-- Title : Standard VITAL_Primitives Package
-- : $Revision$
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers : IEEE DASC Timing Working Group (TWG), PAR 1076.4
-- :
-- Purpose : This packages defines standard types, constants, functions
-- : and procedures for use in developing ASIC models.
-- : Specifically a set of logic primitives are defined.
-- :
-- Known Errors :
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the objects (types, subtypes, constants, functions,
-- : procedures ... etc.) that can be used by a user. The package
-- : body shall be considered the formal definition of the
-- : semantics of this package. Tool developers may choose to
-- : implement the package body in the most efficient manner
-- : available to them.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Acknowledgments:
-- This code was originally developed under the "VHDL Initiative Toward ASIC
-- Libraries" (VITAL), an industry sponsored initiative. Technical
-- Director: William Billowitch, VHDL Technology Group; U.S. Coordinator:
-- Steve Schultz; Steering Committee Members: Victor Berman, Cadence Design
-- Systems; Oz Levia, Synopsys Inc.; Ray Ryan, Ryan & Ryan; Herman van Beek,
-- Texas Instruments; Victor Martin, Hewlett-Packard Company.
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- Modification History :
-- ----------------------------------------------------------------------------
-- Version No:|Auth:| Mod.Date:| Changes Made:
-- v95.0 A | | 06/02/95 | Initial ballot draft 1995
-- ----------------------------------------------------------------------------
--
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
PACKAGE VITAL_Primitives IS
-- ------------------------------------------------------------------------
-- Type and Subtype Declarations
-- ------------------------------------------------------------------------
-- For Truth and State Tables
SUBTYPE VitalTruthSymbolType IS VitalTableSymbolType RANGE 'X' TO 'Z';
SUBTYPE VitalStateSymbolType IS VitalTableSymbolType RANGE '/' TO 'S';
TYPE VitalTruthTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalTruthSymbolType;
TYPE VitalStateTableType IS ARRAY ( NATURAL RANGE <>, NATURAL RANGE <> )
OF VitalStateSymbolType;
-- ---------------------------------
-- Default values used by primitives
-- ---------------------------------
CONSTANT VitalDefDelay01 : VitalDelayType01; -- Propagation delays
CONSTANT VitalDefDelay01Z : VitalDelayType01Z;
-- ------------------------------------------------------------------------
-- VITAL Primitives
--
-- The primitives packages contains a collections of common gates,
-- including AND, OR, XOR, NAND, NOR, XNOR, BUF, INV, MUX and DECODER
-- functions. In addition, for sequential devices, a STATE TABLE construct
-- is provided. For complex functions a modeler may wish to use either
-- a collection of connected VITAL primitives, or a TRUTH TABLE construct.
--
-- For each primitive a Function and Procedure is provided. The primitive
-- functions are provided to support behavioral modeling styles. The
-- primitive procedures are provided to support structural modeling styles.
--
-- The procedures wait internally for an event on an input signal, compute
-- the new result, perform glitch handling, schedule transaction on the
-- output signals, and wait for future input events. All of the functional
-- (logic) input or output parameters of the primitive procedures are
-- signals. All the other parameters are constants.
--
-- The procedure primitives are parameterized for separate path delays
-- from each input signal. All path delays default to 0 ns.
--
-- The sequential primitive functions compute the defined function and
-- return a value of type std_ulogic or std_logic_vector. All parameters
-- of the primitive functions are constants of mode IN.
--
-- The primitives are based on 1164 operators. The user may also elect to
-- express functions using the 1164 operators as well. These styles are
-- all equally acceptable methods for device modeling.
--
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: N-input logic device function calls:
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The function calls return the evaluated logic function
-- corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-bit
-- wide logic functions.
-- ResultMap VitalResultMapType The output signal strength
-- result map to modify default
-- result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The evaluated logic function of
-- the n-bit wide primitives.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR (
CONSTANT Data : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType := VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: N-input logic device concurrent procedure calls.
-- VitalAND VitalOR VitalXOR
-- VitalNAND VitalNOR VitalXNOR
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delay form data to q is a
-- a parameter to the procedure. A vector of delay values
-- for inputs to output are provided. It is noted that
-- limitations in SDF make the back annotation of the delay
-- array difficult.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector The input signals for the n-
-- bit wide logic functions.
-- tpd_data_q VitalDelayArrayType01 The propagation delay from
-- the data inputs to the output
-- q.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the
-- evaluated logic function.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: 2,3 and 4 input logic device function calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The function calls return the evaluated 2, 3 or 4 input
-- logic function corresponding to the function name.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The result of the evaluated logic
-- function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR2 (
CONSTANT a, b : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR3 (
CONSTANT a, b, c : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNAND4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalXNOR4 (
CONSTANT a, b, c, d : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: 2, 3 and 4 input logic device concurrent procedure
-- calls.
--
-- VitalAND2 VitalOR2 VitalXOR2
-- VitalAND3 VitalOR3 VitalXOR3
-- VitalAND4 VitalOR4 VitalXOR4
--
-- VitalNAND2 VitalNOR2 VitalXNOR2
-- VitalNAND3 VitalNOR3 VitalXNOR3
-- VitalNAND4 VitalNOR4 VitalXNOR4
--
-- Description: The procedure calls return the evaluated logic function
-- corresponding to the function name as a parameter to the
-- procedure. Propagation delays from a and b to q are
-- a parameter to the procedure. The default propagation
-- delay is 0 ns.
--
-- Arguments:
--
-- IN Type Description
-- a, b, c, d std_ulogic 2 input devices have a and b as
-- inputs. 3 input devices have a, b
-- and c as inputs. 4 input devices
-- have a, b, c and d as inputs.
-- tpd_a_q VitalDelayType01 The propagation delay from the a
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_b_q VitalDelayType01 The propagation delay from the b
-- input to output q for 2, 3 and 4
-- input devices.
-- tpd_c_q VitalDelayType01 The propagation delay from the c
-- input to output q for 3 and 4 input
-- devices.
-- tpd_d_q VitalDelayType01 The propagation delay from the d
-- input to output q for 4 input
-- devices.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The output signal of the evaluated
-- logic function.
--
-- Returns
-- none
-- -------------------------------------------------------------------------
PROCEDURE VitalAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR2 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR3 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNAND4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalXNOR4 (
SIGNAL q : OUT std_ulogic;
SIGNAL a, b, c, d : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_b_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_c_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: Buffer logic device concurrent procedure calls.
--
-- Description: Four buffer sequential primitive function calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the four permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the buffers
-- Enable std_ulogic Enable for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The output signal of the evaluated
-- buffer function.
--
-- -------------------------------------------------------------------------
FUNCTION VitalBUF (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalBUFIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalIDENT (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: Buffer device procedure calls.
--
-- Description: Four buffer concurrent primitive procedure calls are
-- provided. One is a simple buffer and the others
-- offer high and low enables and the fourth permits
-- propagation of Z as shown below:
--
-- VitalBUF Standard non-inverting buffer
-- VitalBUFIF0 Non-inverting buffer with Enable low
-- VitalBUFIF1 Non-inverting buffer with Enable high
-- VitalIDENT Pass buffer capable of propagating Z
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal to the buffers
-- Enable std_ulogic Enable signal for the enable high and
-- low buffers.
-- tpd_a_q VitalDelayType01 Propagation delay from input to
-- output for the simple buffer.
-- VitalDelayType01Z Propagation delay from input to
-- to output for the enable high and low
-- and identity buffers.
-- tpd_enable_q VitalDelayType01Z Propagation delay from enable to
-- output for the enable high and low
-- buffers.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple buffer.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low and
-- identity buffers.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output of the buffers.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalBUF (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalBUFIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalBUFIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalIDENT (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: Inverter functions which return the inverted signal
-- value. Inverters with enable low and high are provided
-- which can drive high impedance when inactive.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input to the inverter
-- Enable std_ulogic Enable to the enable high and low
-- inverters.
-- ResultMap VitalResultMap The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic Output of the inverter
--
-- -------------------------------------------------------------------------
FUNCTION VitalINV (
CONSTANT Data : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalINVIF0 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
FUNCTION VitalINVIF1 (
CONSTANT Data, Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalINV, VitalINVIF0, VitalINVIF1
--
-- Description: The concurrent primitive procedure calls implement a
-- signal inversion function. The output is a parameter to
-- the procedure. The path delay information is passed as
-- a parameter to the call.
--
-- Arguments:
--
-- IN Type Description
-- a std_ulogic Input signal for the simple inverter
-- Data std_ulogic Input signal for the enable high and
-- low inverters.
-- Enable std_ulogic Enable signal for the enable high and
-- low inverters.
-- tpd_a_q VitalDelayType01 Propagation delay from input a to
-- output q for the simple inverter.
-- tpd_data_q VitalDelayType01 Propagation delay from input data to
-- output q for the enable high and low
-- inverters.
-- tpd_enable_q VitalDelayType01Z Propagation delay from input enable
-- to output q for the enable high and
-- low inverters.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- simple inverter.
-- VitalResultZMapType The output signal strength result map
-- to modify default result mapping
-- which has high impedance capability
-- for the enable high, enable low
-- inverters.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal of the inverter.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalINV (
SIGNAL q : OUT std_ulogic;
SIGNAL a : IN std_ulogic;
CONSTANT tpd_a_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalINVIF0 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
PROCEDURE VitalINVIF1 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01Z := VitalDefDelay01Z;
CONSTANT ResultMap : IN VitalResultZMapType
:= VitalDefaultResultZMap);
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX functions return the selected data bit
-- based on the value of dSelect. For MUX2, the function
-- returns data0 when dselect is 0 and returns data1 when
-- dselect is 1. When dselect is X, result is X for MUX2
-- when data0 /= data1. X propagation is reduced when the
-- dselect signal is X and both data signals are identical.
-- When this is the case, the result returned is the value
-- of the data signals.
--
-- For the N input device:
--
-- N must equal 2**(bits of dSelect)
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Input signal for the N-bit, 4-bit and
-- 8-bit mux.
-- Data1,Data0 std_ulogic Input signals for the 2-bit mux.
-- dSelect std_ulogic Select signal for 2-bit mux
-- std_logic_vector2 Select signal for 4-bit mux
-- std_logic_vector3 Select signal for 8-bit mux
-- std_logic_vector Select signal for N-Bit mux
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all muxes.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_ulogic The value of the selected bit is
-- returned.
--
-- -------------------------------------------------------------------------
FUNCTION VitalMUX (
CONSTANT Data : IN std_logic_vector;
CONSTANT dSelect : IN std_logic_vector;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX2 (
CONSTANT Data1, Data0 : IN std_ulogic;
CONSTANT dSelect : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX4 (
CONSTANT Data : IN std_logic_vector4;
CONSTANT dSelect : IN std_logic_vector2;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
FUNCTION VitalMUX8 (
CONSTANT Data : IN std_logic_vector8;
CONSTANT dSelect : IN std_logic_vector3;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_ulogic;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalMUX, VitalMUX2, VitalMUX4, VitalMUX8
--
-- Description: The VitalMUX concurrent primitive procedures calls
-- return in the output q the value of the selected data
-- bit based on the value of dsel. For the two bit mux,
-- the data returned is either d0 or d1, the data input.
-- For 4, 8 and N-bit functions, data is the input and is
-- of type std_logic_vector. For the 2-bit mux, if d0 or
-- d1 are X, the output is X only when d0 do not equal d1.
-- When d0 and d1 are equal, the return value is this value
-- to reduce X propagation.
--
-- Propagation delay information is passed as a parameter
-- to the procedure call for delays from data to output and
-- select to output. For 2-bit muxes, the propagation
-- delays from data are provided for d0 and d1 to output.
--
--
-- Arguments:
--
-- IN Type Description
-- d1,d0 std_ulogic Input signals for the 2-bit mux.
-- Data std_logic_vector4 Input signals for the 4-bit mux.
-- std_logic_vector8 Input signals for the 8-bit mux.
-- std_logic_vector Input signals for the N-bit mux.
-- dsel std_ulogic Select signal for the 2-bit mux.
-- std_logic_vector2 Select signals for the 4-bit mux.
-- std_logic_vector3 Select signals for the 8-bit mux.
-- std_logic_vector Select signals for the N-bit mux.
-- tpd_d1_q VitalDelayType01 Propagation delay from input d1 to
-- output q for 2-bit mux.
-- tpd_d0_q VitalDelayType01 Propagation delay from input d0 to
-- output q for 2-bit mux.
-- tpd_data_q VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- tpd_dsel_q VitalDelayType01 Propagation delay from input dsel
-- to output q for 2-bit mux.
-- VitalDelayArrayType01 Propagation delay from input dsel
-- to output q for 4-bit, 8-bit and
-- N-bit muxes.
-- ResultMap VitalResultMapType The output signal strength result
-- map to modify default result
-- mapping for all muxes.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic The value of the selected signal.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalMUX (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector;
SIGNAL dSel : IN std_logic_vector;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX2 (
SIGNAL q : OUT std_ulogic;
SIGNAL d1, d0 : IN std_ulogic;
SIGNAL dSel : IN std_ulogic;
CONSTANT tpd_d1_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_d0_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_dsel_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX4 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector4;
SIGNAL dSel : IN std_logic_vector2;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalMUX8 (
SIGNAL q : OUT std_ulogic;
SIGNAL Data : IN std_logic_vector8;
SIGNAL dSel : IN std_logic_vector3;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_dsel_q : IN VitalDelayArrayType01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- ------------------------------------------------------------------------
--
-- Sequential
-- Primitive
-- Function Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER functions are the sequential primitive
-- calls for decoder logic. The functions are provided
-- for N, 2, 4 and 8-bit outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The VitalDECODER returns 0 if enable is 0.
-- The VitalDECODER returns the result bit set to 1 if
-- enable is 1. All other bits of returned result are
-- set to 0.
--
-- The returned array is in descending order:
-- (n-1 downto 0).
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- Enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- ResultMap VitalResultMapType The output signal strength result map
-- to modify default result mapping for
-- all output signals of the decoders.
--
-- INOUT
-- none
--
-- OUT
-- none
--
-- Returns
-- std_logic_vector2 The output of the 2-bit decoder.
-- std_logic_vector4 The output of the 4-bit decoder.
-- std_logic_vector8 The output of the 8-bit decoder.
-- std_logic_vector The output of the n-bit decoder.
--
-- -------------------------------------------------------------------------
FUNCTION VitalDECODER (
CONSTANT Data : IN std_logic_vector;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector;
FUNCTION VitalDECODER2 (
CONSTANT Data : IN std_ulogic;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector2;
FUNCTION VitalDECODER4 (
CONSTANT Data : IN std_logic_vector2;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector4;
FUNCTION VitalDECODER8 (
CONSTANT Data : IN std_logic_vector3;
CONSTANT Enable : IN std_ulogic;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap
) RETURN std_logic_vector8;
-- -------------------------------------------------------------------------
--
-- Concurrent
-- Primitive
-- Procedure Name: VitalDECODER, VitalDECODER2, VitalDECODER4,
-- VitalDECODER8
--
-- Description: The VitalDECODER procedures are the concurrent primitive
-- procedure calls for decoder functions. The procedures
-- are provided for N, 2, 4 and 8 outputs.
--
-- The N-bit decoder is (2**(bits of data)) wide.
--
-- The procedural form of the decoder is used for
-- distributed delay modeling. The delay information for
-- each path is passed as an argument to the procedure.
--
-- Result is set to 0 if enable is 0.
-- The result bit represented by data is set to 1 if
-- enable is 1. All other bits of result are set to 0.
--
-- The result array is in descending order: (n-1 downto 0).
--
-- For the N-bit decoder, the delay path is a vector of
-- delays from inputs to outputs.
--
-- Arguments:
--
-- IN Type Description
-- Data std_ulogic Input signal for 2-bit decoder.
-- std_logic_vector2 Input signals for 4-bit decoder.
-- std_logic_vector3 Input signals for 8-bit decoder.
-- std_logic_vector Input signals for N-bit decoder.
-- enable std_ulogic Enable input signal. The result is
-- output when enable is high.
-- tpd_data_q VitalDelayType01 Propagation delay from input data
-- to output q for 2-bit decoder.
-- VitalDelayArrayType01 Propagation delay from input data
-- to output q for 4, 8 and n-bit
-- decoders.
-- tpd_enable_q VitalDelayType01 Propagation delay from input enable
-- to output q for 2, 4, 8 and n-bit
-- decoders.
--
-- INOUT
-- none
--
-- OUT
-- q std_logic_vector2 Output signals for 2-bit decoder.
-- std_logic_vector4 Output signals for 4-bit decoder.
-- std_logic_vector8 Output signals for 8-bit decoder.
-- std_logic_vector Output signals for n-bit decoder.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalDECODER (
SIGNAL q : OUT std_logic_vector;
SIGNAL Data : IN std_logic_vector;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER2 (
SIGNAL q : OUT std_logic_vector2;
SIGNAL Data : IN std_ulogic;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER4 (
SIGNAL q : OUT std_logic_vector4;
SIGNAL Data : IN std_logic_vector2;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
PROCEDURE VitalDECODER8 (
SIGNAL q : OUT std_logic_vector8;
SIGNAL Data : IN std_logic_vector3;
SIGNAL Enable : IN std_ulogic;
CONSTANT tpd_data_q : IN VitalDelayArrayType01;
CONSTANT tpd_enable_q : IN VitalDelayType01 := VitalDefDelay01;
CONSTANT ResultMap : IN VitalResultMapType
:= VitalDefaultResultMap );
-- -------------------------------------------------------------------------
-- Function Name: VitalTruthTable
--
-- Description: VitalTruthTable implements a truth table. Given
-- a set of inputs, a sequential search is performed
-- to match the input. If a match is found, the output
-- is set based on the contents of the CONSTANT TruthTable.
-- If there is no match, all X's are returned. There is
-- no limit to the size of the table.
--
-- There is a procedure and function for VitalTruthTable.
-- For each of these, a single value output (std_logic) and
-- a multi-value output (std_logic_vector) are provided.
--
-- The first dimension of the table is for number of
-- entries in the truth table and second dimension is for
-- the number of elements in a row. The number of inputs
-- in the row should be Data'LENGTH plus result'LENGTH.
--
-- Elements is a row will be interpreted as
-- Input(NumInputs - 1),.., Input(0),
-- Result(NumOutputs - 1),.., Result(0)
--
-- All inputs will be mapped to the X01 subtype
--
-- If the value of Result is not in the range 'X' to 'Z'
-- then an error will be reported. Also, the Result is
-- always given either as a 0, 1, X or Z value.
--
-- Arguments:
--
-- IN Type Description
-- TruthTable The input constant which defines the
-- behavior in truth table form.
-- DataIn The inputs to the truth table used to
-- perform input match to select
-- output(s) to value(s) to drive.
--
-- INOUT
-- none
--
-- OUT
-- Result std_logic Concurrent procedure version scalar
-- output.
-- std_logic_vector Concurrent procedure version vector
-- output.
--
-- Returns
-- Result std_logic Function version scalar output.
-- std_logic_vector Function version vector output.
--
-- -------------------------------------------------------------------------
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic_vector;
FUNCTION VitalTruthTable (
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
) RETURN std_logic;
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic_vector;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalTruthTable (
SIGNAL Result : OUT std_logic;
CONSTANT TruthTable : IN VitalTruthTableType;
CONSTANT DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalStateTable
--
-- Description: VitalStateTable is a non-concurrent implementation of a
-- state machine (Moore Machine). It is used to model
-- sequential devices and devices with internal states.
--
-- The procedure takes the value of the state table
-- data set and performs a sequential search of the
-- CONSTANT StateTable until a match is found. Once a
-- match is found, the result of that match is applied
-- to Result. If there is no match, all X's are returned.
-- The resultant output becomes the input for the next
-- state.
--
-- The first dimension of the table is the number of
-- entries in the state table and second dimension is the
-- number of elements in a row of the table. The number of
-- inputs in the row should be DataIn'LENGTH. Result should
-- contain the current state (which will become the next
-- state) as well as the outputs
--
-- Elements is a row of the table will be interpreted as
-- Input(NumInputs-1),.., Input(0), State(NumStates-1),
-- ..., State(0),Output(NumOutputs-1),.., Output(0)
--
-- where State(numStates-1) DOWNTO State(0) represent the
-- present state and Output(NumOutputs - 1) DOWNTO
-- Outputs(NumOutputs - NumStates) represent the new
-- values of the state variables (i.e. the next state).
-- Also, Output(NumOutputs - NumStates - 1)
--
-- This procedure returns the next state and the new
-- outputs when a match is made between the present state
-- and present inputs and the state table. A search is
-- made starting at the top of the state table and
-- terminates with the first match. If no match is found
-- then the next state and new outputs are set to all 'X's.
--
-- (Asynchronous inputs (i.e. resets and clears) must be
-- handled by placing the corresponding entries at the top
-- of the table. )
--
-- All inputs will be mapped to the X01 subtype.
--
-- NOTE: Edge transitions should not be used as values
-- for the state variables in the present state
-- portion of the state table. The only valid
-- values that can be used for the present state
-- portion of the state table are:
-- 'X', '0', '1', 'B', '-'
--
-- Arguments:
--
-- IN Type Description
-- StateTable VitalStateTableType The input constant which defines
-- the behavior in state table form.
-- DataIn std_logic_vector The current state inputs to the
-- state table used to perform input
-- matches and transition
-- calculations.
-- NumStates NATURAL Number of state variables
--
-- INOUT
-- Result std_logic Output signal for scalar version of
-- the concurrent procedure call.
-- std_logic_vector Output signals for vector version
-- of the concurrent procedure call.
-- PreviousDataIn std_logic_vector The previous inputs and states used
-- in transition calculations and to
-- set outputs for steady state cases.
--
-- OUT
-- none
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic_vector;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
VARIABLE Result : INOUT std_logic;
VARIABLE PreviousDataIn : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
CONSTANT DataIn : IN std_logic_vector
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic_vector;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector;
CONSTANT NumStates : IN NATURAL
);
PROCEDURE VitalStateTable (
SIGNAL Result : INOUT std_logic;
CONSTANT StateTable : IN VitalStateTableType;
SIGNAL DataIn : IN std_logic_vector
);
-- -------------------------------------------------------------------------
--
-- Function Name: VitalResolve
--
-- Description: VitalResolve takes a vector of signals and resolves
-- them to a std_ulogic value. This procedure can be used
-- to resolve multiple drivers in a single model.
--
-- Arguments:
--
-- IN Type Description
-- Data std_logic_vector Set of input signals which drive a
-- common signal.
--
-- INOUT
-- none
--
-- OUT
-- q std_ulogic Output signal which is the resolved
-- value being driven by the collection of
-- input signals.
--
-- Returns
-- none
--
-- -------------------------------------------------------------------------
PROCEDURE VitalResolve (
SIGNAL q : OUT std_ulogic;
CONSTANT Data : IN std_logic_vector);
END VITAL_Primitives;
|
gpl-3.0
|
Xero-Hige/LuGus-VHDL
|
TPS-2016/components/genericCounter/generic_counter_tb.vhd
|
2
|
916
|
library ieee;
use ieee.std_logic_1164.all;
entity genericCounter_tb is
end;
architecture genericCounter_tb_func of genericCounter_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal n_out: std_logic_vector(3 downto 0);
signal c_out: std_logic:='0';
component genericCounter is
generic (
BITS:natural := 4;
MAX_COUNT:natural := 15);
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
count: out std_logic_vector(BITS-1 downto 0);
carry_o: out std_logic
);
end component;
begin
clk_in <= not(clk_in) after 20 ns;
rst_in <= '0' after 50 ns;
enable_in <= '1' after 60 ns;
genericCounterMap: genericCounter generic map (4,10)
port map(
clk => clk_in,
rst => rst_in,
ena => enable_in,
count => n_out,
carry_o => c_out
);
end architecture;
|
gpl-3.0
|
zhangry868/MIPSCPU
|
PipelineTimeSimulation/simulation/modelsim/rtl_work/@a@l@u_@controller/_primary.vhd
|
2
|
228
|
library verilog;
use verilog.vl_types.all;
entity ALU_Controller is
port(
ALU_op : in vl_logic_vector(3 downto 0);
ALU_ctr : out vl_logic_vector(2 downto 0)
);
end ALU_Controller;
|
gpl-3.0
|
INTI-CMNB-FPGA/fpga_helpers
|
test/fake-project/FPGA/top.vhdl
|
1
|
312
|
library IEEE;
use IEEE.std_logic_1164.all;
entity top is
port (
data_i : in std_logic;
data_o : out std_logic
);
end entity top;
architecture RTL of top is
begin
inst: entity work.core
port map (
data_i => data_i,
data_o => data_o
);
end architecture RTL;
|
gpl-3.0
|
zhangry868/MIPSCPU
|
PipelineTimeSimulation/simulation/modelsim/rtl_work/@data@memory/_primary.vhd
|
1
|
633
|
library verilog;
use verilog.vl_types.all;
entity DataMemory is
generic(
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 32
);
port(
data : in vl_logic_vector;
addr : in vl_logic_vector;
we : in vl_logic_vector(3 downto 0);
clk : in vl_logic;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of ADDR_WIDTH : constant is 1;
end DataMemory;
|
gpl-3.0
|
INTI-CMNB-FPGA/fpga_helpers
|
test/fake-project/lib2/pkg1_lib2.vhdl
|
1
|
303
|
library IEEE;
use IEEE.std_logic_1164.all;
package pkg1_lib2 is
component com1_pkg1_lib2 is
generic (
WITH_GENERIC: boolean:=TRUE
);
port (
data_i : in std_logic;
data_o : out std_logic
);
end component com1_pkg1_lib2;
end package pkg1_lib2;
|
gpl-3.0
|
behzady/ManoBasicComputer
|
Parts/Multiplexer.vhd
|
1
|
1449
|
--Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Multipelexer
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity Multiplexer is
generic(N: integer:=3);
port(
Q: out std_logic;
E: in std_logic:= '1';
S: in std_logic_vector(n-1 downto 0);
I: in std_logic_vector(2**n-1 downto 0)
);
end Multiplexer;
architecture Structure of Multiplexer is
signal ou: std_logic_vector(1 downto 0);
component multiplexerBasic is
port(
Q: out std_logic;
E: in std_logic;
S: in std_logic;
I: in std_logic_vector(1 downto 0)
);
end component;
component Multiplexer is
generic(N: integer:=3);
port(
Q: out std_logic;
E: in std_logic;
S: in std_logic_vector(n-1 downto 0);
I: in std_logic_vector(2**n-1 downto 0)
);
end component;
begin
mul0: multiplexerBasic port map(I=>ou, S=>S(n-1), E=>E, Q=>Q);
cond: if n = 1 generate
ou <= I;
end generate cond;
Build: if n>1 generate
mulN0:component Multiplexer
generic map(N=>n-1)
port map(I=>I(2**(n-1)-1 downto 0), E=>E, S=>S(n-2 downto 0), Q=>ou(0));
mulN1:component Multiplexer
generic map(N=>n-1)
port map(I=>I(2**n-1 downto 2**(n-1)), E=>E, S=>S(n-2 downto 0), Q=>ou(1));
end generate Build;
end Structure;
|
gpl-3.0
|
INTI-CMNB-FPGA/fpga_helpers
|
test/fake-project/core/core.vhdl
|
1
|
643
|
library IEEE;
use IEEE.std_logic_1164.all;
library LIB1;
use LIB1.pkg1_lib1.all;
library LIB2;
use LIB2.pkg1_lib2.all;
entity core is
generic (
WITH_GENERIC: boolean:=TRUE
);
port (
data_i : in std_logic;
data_o : out std_logic
);
end entity core;
architecture RTL of core is
signal data : std_logic;
begin
com2_pkg1_lib1_inst: com2_pkg1_lib1
port map (
data_i => data_i,
data_o => data
);
com1_pkg1_lib2_inst: com1_pkg1_lib2
generic map (WITH_GENERIC => FALSE)
port map (
data_i => data,
data_o => data_o
);
end architecture RTL;
|
gpl-3.0
|
INTI-CMNB-FPGA/fpga_helpers
|
test/fake-project/lib3/pkg1_lib3.vhdl
|
1
|
303
|
library IEEE;
use IEEE.std_logic_1164.all;
package pkg1_lib3 is
component com1_pkg1_lib3 is
generic (
WITH_GENERIC: boolean:=TRUE
);
port (
data_i : in std_logic;
data_o : out std_logic
);
end component com1_pkg1_lib3;
end package pkg1_lib3;
|
gpl-3.0
|
INTI-CMNB-FPGA/fpga_helpers
|
test/fpga_deps/lib2_pkg1.vhdl
|
1
|
181
|
library IEEE;
use IEEE.std_logic_1164.all;
package pkg1 is
component com1 is
--
end component com1;
component com4 is
--
end component com4;
end package pkg1;
|
gpl-3.0
|
behzady/ManoBasicComputer
|
Parts/BUS.vhd
|
1
|
757
|
--Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--BUS
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity busLine is
port(
Ar: in adr;
PC: in word;
DR: in word;
AC: in word;
IR: in word;
TR: in word;
Mm: in word;
S: in ctrlBUS;
Q: out word
);
end busLine;
architecture Structure of busLine is
begin
Q <= "0000"&Ar when S = busAR
else PC when S = busPC
else DR when S = busDR
else AC when S = busAC
else IR when S = busIR
else TR when S = busTR
else Mm when S = busMm
else (Others => '0');
end Structure;
|
gpl-3.0
|
behzady/ManoBasicComputer
|
Parts/basicRegister.vhd
|
1
|
839
|
--Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--RegisterBasic
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity registerBasic is
port(
INC :in std_logic := '0';
LD :in std_logic := '0';
CLR :in std_logic := '1';
CLK :in std_logic := '0';
Di :in std_logic := '0';
Do :buffer std_logic := '0';
Dno :buffer std_logic;
Co :out std_logic := '0'
);
end registerBasic;
architecture Structure of registerBasic is
signal j,k: std_logic;
begin
j <= INC or (Di and LD);
k <= INC or ((not Di) and LD);
flp0: flipflopJK port map(CLR=>CLR, CLK=>CLK, J=>j, K=>k, Q=>Do, nQ=>Dno);
Co <= INC and Do;
end Structure;
|
gpl-3.0
|
ARC-Lab-UF/window_gen
|
src/window_gen_pkg.vhd
|
1
|
5927
|
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- This package provides helper functions for accessing windows that have been
-- represented as a large std_logic_vector.
--
-- NOTE: This package will become largely unnecessary after using VHDL 2008.
-- VHDL 93 does not support arrays of unconstrained types, so creating a
-- completely generic window is not possible without representing it as a huge
-- std_logic_vector. In 2008, that vector would be replaced by a 2D array of an
-- unconstrained width. The width would be specified by the DATA_WIDTH
-- parameter when the window generator is instantiated.
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
package window_gen_pkg is
-----------------------------------------------------------------------
-- Function getVectorElement
-- Description: For a vectorized 2D array, this function returns the
-- element at the specified row and col.
--
-- Parameters:
-- vector : The 1D-vectorized version of the 2D array, stored in row-major
-- order. Index (0,0) starts at the MSB in the vector, with the
-- LSB storing the end of index (total_rows-1, total_cols-1)
-- row : the row of the element to return
-- col : the column of the element to return
-- total_rows : the total number of rows in the 2D array (and 1D vectorized
-- version)
-- total_cols : the total number of cols in the 2D array (and 1D vectorized
-- version)
-- element_width : the width in bits of each array element
-- Preconditions: row < total_rows, col < total_cols, vector must be the
-- appropriate size with data stored as described above.
-----------------------------------------------------------------------
function getVectorElement(vector : std_logic_vector;
row, col : natural;
total_rows, total_cols : positive;
element_width : positive) return std_logic_vector;
-----------------------------------------------------------------------
-- Function setVectorElement
-- Description: For a vectorized 2D array, this function set the
-- element at the specified row and col with the specified
-- value.
--
-- Parameters:
-- input : The element-width value to store into the window.
-- vector : The 1D-vectorized version of the 2D array, stored in row-major
-- order. Index (0,0) starts at the MSB in the vector, with the
-- LSB storing the end of index (total_rows-1, total_cols-1).
-- The procedure takes the vector as input and modifies the
-- corresponding element.
-- row : the row of the element to set
-- col : the column of the element to set
-- total_rows : the total number of rows in the 2D array (and 1D vectorized
-- version)
-- total_cols : the total number of cols in the 2D array (and 1D vectorized
-- version)
-- element_width : the width in bits of each array element
-- Preconditions: row < total_rows, col < total_cols, vector must be the
-- appropriate size as described above.
-----------------------------------------------------------------------
procedure setVectorElement(input : std_logic_vector;
vector : inout std_logic_vector;
row, col : natural;
total_rows, total_cols : positive;
element_width : positive);
end window_gen_pkg;
package body window_gen_pkg is
function getVectorElement(vector : std_logic_vector;
row, col : natural;
total_rows, total_cols : positive;
element_width : positive) return std_logic_vector is
variable top : natural;
begin
assert(row < total_rows);
assert(col < total_cols);
top := ((total_rows-row) * total_cols - col) * element_width;
return vector(top-1 downto top-element_width);
end getVectorElement;
procedure setVectorElement(input : std_logic_vector;
vector : inout std_logic_vector;
row, col : natural;
total_rows, total_cols : positive;
element_width : positive) is
variable top : natural;
begin
assert(row < total_rows);
assert(col < total_cols);
top := ((total_rows-row) * total_cols - col) * element_width;
vector(top-1 downto top-element_width) := input;
end setVectorElement;
end package body;
|
gpl-3.0
|
shibumi/University
|
VHDL/Aufgabe4.4.vhdl
|
2
|
573
|
--Aufgabe 4.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_STD.all;
entity Aufgabe4_4 is
port(x: in STD_LOGIC_VECTOR(4 downto 1);
y: out STD_LOGIC);
end entity;
architecture test of Aufgabe4_4 is
begin
process(x)
variable z: STD_LOGIC_VECTOR(2 DOWNTO 0);
begin
--Bereich links oben
z(0) := x(1) and x(2);
z(1) := x(1) or x(2);
if x(3) = '0' then
z(2) := z(0);
else
z(2) := z(1);
end if;
--Abtastregister
if RISING_EDGE(x(4)) then
y <= z(2);
end if;
end process;
end architecture;
|
gpl-3.0
|
ARC-Lab-UF/window_gen
|
src/wg_fifo.vhd
|
1
|
7265
|
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description: This entity maintains the FIFO used in each row of a
-- window buffer. This FIFO differs from others by having a read option and a
-- pop option, which are maintained by different pointers. The read option
-- simply scans through the FIFO contents without removing any data.
-- This functionality is needed because the window buffer will read the same
-- FIFO data multiple times before popping data out of the buffer.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- DATA_WIDTH : The width of each element in the FIFO.
-- ADDR_WIDTH : The address width of the FIFO. This defines the number of
-- maximum number of words in the FIFO as 2**ADDR_WIDTH.
-- SIZE_WIDTH : The width of the size input.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Descriptions (all control signals are active high)
-- clk: Clock
-- rst: Asynchronous reset
-- wen : '1' to write current input into fifo
-- wdata : Write data
-- ren : '1' to read from the current read pointer without removing data from
-- the FIFO.
-- pop : '1' to pop data from from fifo (i.e. a traditional FIFO read)
-- read_reset : Resets read pointer to back to actual front of FIFO
-- read_empty : '1' if nothing to read
-- rdata : Data read/output from the fifo
-- empty : '1' if empty for popping
-- full : '1' if full
-- size : The size of the fifo. This can be any value from 1 to 2**ADDR_WIDTH.
-- The size is used to determine when full should be asserted.
-------------------------------------------------------------------------------
entity wg_fifo is
generic (
DATA_WIDTH : positive;
ADDR_WIDTH : positive;
SIZE_WIDTH : positive);
port (
clk : in std_logic;
rst : in std_logic;
wen : in std_logic;
wdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
ren : in std_logic; -- doesn't decrement count
pop : in std_logic; -- decrements count
read_reset : in std_logic;
read_empty : out std_logic; -- similar to empty, but for reads
rdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
empty : out std_logic;
full : out std_logic;
size : in std_logic_vector(SIZE_WIDTH-1 downto 0)
);
end wg_fifo;
architecture RTL of wg_fifo is
signal front, next_front : unsigned(ADDR_WIDTH-1 downto 0);
signal back, next_back : unsigned(ADDR_WIDTH-1 downto 0);
signal read_ptr, next_read_ptr : unsigned(ADDR_WIDTH-1 downto 0);
signal count, next_count : unsigned(SIZE_WIDTH-1 downto 0);
signal read_count, next_read_count : unsigned(SIZE_WIDTH-1 downto 0);
signal wen_ram : std_logic;
signal full_s : std_logic;
signal empty_s : std_logic;
signal read_empty_s : std_logic;
begin
-- instantiate RAM uses for FIFO storage
U_RAM : entity work.ram(SYNC_READ_DURING_WRITE)
generic map (
NUM_WORDS => 2**ADDR_WIDTH,
WORD_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH)
port map (
clk => clk,
wen => wen_ram,
waddr => std_logic_vector(back),
wdata => wdata,
raddr => std_logic_vector(next_read_ptr),
rdata => rdata);
-- create necessary registers
process(clk, rst)
begin
if (rst = '1') then
front <= (others => '0');
back <= (others => '0');
read_ptr <= (others => '0');
count <= (others => '0');
read_count <= (others => '0');
elsif(clk'event and clk = '1') then
count <= next_count;
read_count <= next_read_count;
back <= next_back;
front <= next_front;
read_ptr <= next_read_ptr;
end if;
end process;
-- combinational logic for maintaining FIFO
process (front, back, read_ptr, count, read_count,
wen, ren, pop, read_reset,
full_s, read_empty_s, empty_s)
variable temp_count : unsigned(SIZE_WIDTH-1 downto 0);
variable temp_read_count : unsigned(SIZE_WIDTH-1 downto 0);
begin
temp_count := count;
temp_read_count := read_count;
-- if data is pushed in, move back and increment counts
if (wen = '1' and full_s = '0') then
next_back <= back + 1;
temp_count := temp_count + 1;
temp_read_count := temp_read_count + 1;
else
next_back <= back;
end if;
-- read_reset resets the read_ptr to the front pointer
if (read_reset = '1') then
next_read_ptr <= front;
temp_read_count := temp_count;
elsif (ren = '1' and read_empty_s = '0') then
-- if a read, advance the read pointer, but do not move front
next_read_ptr <= read_ptr + 1;
temp_read_count := temp_read_count - 1;
else
next_read_ptr <= read_ptr;
end if;
-- a pop moves front and updates the count, and resets the read_ptr
if (pop = '1' and empty_s = '0') then
next_front <= front + 1;
next_read_ptr <= front + 1;
temp_count := temp_count - 1;
temp_read_count := temp_count;
else
next_front <= front;
end if;
next_count <= temp_count;
next_read_count <= temp_read_count;
end process;
full_s <= '1' when count = unsigned(size) else '0';
empty_s <= '1' when count = 0 else '0';
read_empty_s <= '1' when read_count = 0 else '0';
full <= full_s;
empty <= empty_s;
read_empty <= read_empty_s;
-- protect against writes when full
wen_ram <= '1' when wen = '1' and full_s = '0' else '0';
end RTL;
|
gpl-3.0
|
shibumi/University
|
VHDL/Aufgabe4.3.vhdl
|
2
|
740
|
--Aufgabe 4.3
library ieee;
use ieee.std_logic_1164.all;
use ieee.Numeric_STD.all;
entity Aufgabe4_3 is
port(a: in UNSIGNED(3 downto 0);
b: in UNSIGNED(3 downto 0);
s: in STD_LOGIC_VECTOR(1 DOWNTO 0);
y: out UNSIGNED(3 downto 0));
end entity;
architecture test of Aufgabe4_3 is
begin
process(a,b,s)
variable v0,v1,v2,v3,v4: UNSIGNED(3 downto 0);
begin
--Linker Bereich + Oben Rechts
v0 := a and b;
v1 := a or b;
if s(0) = '0' then
v2 := v0;
v3 := a;
else
v2 := v1;
v3 := not(a);
end if;
--Addierer / Links Unten
v4 := v3 + b;
if s(1) = '0' then
y <= v2;
else
y <= v4;
end if;
end process;
end architecture;
|
gpl-3.0
|
rcook/ElectronFpga
|
src/DCM/dcm4.vhd
|
1
|
2046
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dcm4 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end dcm4;
architecture BEHAVIORAL of dcm4 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 40.00 = 32 * 5 / 4
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
gpl-3.0
|
JavierReyes945/microelectronics-project
|
VHDL/enc/shift_reg.vhd
|
1
|
1181
|
-- Company: Fachhochschule Dortmund
-- Engineer: Javier Reyes
--
-- Create Date: 06/16/2017 04:49:58 PM
-- Design Name: Shift register for Convolutional Codes example project
-- Module Name: shift_reg - Behavioral
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
use work.conf_pkg.all;
entity shift_reg is
port (sr_clk : in std_logic;
sr_rst : in std_logic;
sr_in : in std_logic_vector(k-1 downto 0);
sr_data : out std_logic_vector(m-1 downto 0));
-- MSB is data, LSB is data at t-3
end shift_reg;
architecture Behavioral of shift_reg is
-- Signals declaration
signal data : std_logic_vector(m-1 downto 0) := (others => '0');
begin
-- Shifting the bits inside signal 'data'
sr_data <= data;
-- Shifting process with asynchronous reset
process (sr_clk, sr_rst)
begin
if (sr_rst = '1') then
-- If 'reset' is true, output is zero
data <= (others => '0');
elsif (rising_edge(sr_clk)) then
data(0) <= data(1);
data(1) <= data(2);
data(2) <= data(3);
data(3) <= sr_in(0);
end if;
end process;
end Behavioral;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/debug.vhd
|
2
|
28553
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Package: debug
-- File: debug.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: This package implements a SPARC disassembler and LEON
-- trace function.
------------------------------------------------------------------------------
-- Version control:
-- 17-12-1998: : First implemetation
-- 27-08-1999: : Moved trace function from iu
-- 26-09-1999: : Release 1.0
------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned."+";
use IEEE.Std_Logic_arith.all;
use IEEE.std_logic_unsigned.conv_integer;
use work.target.all;
use work.config.all;
use work.sparcv8.all;
use work.iface.all;
use STD.TEXTIO.all;
package debug is
type debug_info is record
op : std_logic_vector(31 downto 0);
pc : std_logic_vector(31 downto 0);
end record;
type base_type is (hex, dec);
subtype nibble is std_logic_vector(3 downto 0);
function disas(insn : debug_info) return string;
procedure trace(signal debug : in iu_debug_type; DISASS : boolean);
function tost(v:std_logic_vector) return string;
function tostd(v:std_logic_vector) return string;
function tosth(v:std_logic_vector) return string;
function tostf(v:std_logic_vector) return string;
function tostring(n:integer) return string;
procedure print(s : string);
end debug;
package body debug is
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
type carr is array (0 to 9) of character;
constant darr : carr := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
function tostd(v:std_logic_vector) return string is
variable s : string(1 to 2);
variable val : integer;
begin
val := conv_integer(v); s(1) := darr(val / 10); s(2) := darr(val mod 10);
return(s);
end;
function tosth(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return(s);
end;
function tostf(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(vlen-1 downto 0);
variable s : string(1 to slen);
begin
vv := v;
for i in slen downto 1 loop
s(i) := tohex(vv(3 downto 0));
vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
end loop;
return("0x" & s);
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := true;
variable index : integer := -1;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tostring(n:integer) return string is
variable len : natural := 1;
variable tmp : string(1 to 32);
variable v : integer := n;
begin
for i in 31 downto 0 loop
if v>(2**i) then
tmp(i) := '1'; v := v - (2**i);
if i>len then len := i; end if;
else
tmp(i) := '0';
end if;
end loop;
return(tmp(32-len to 32));
end;
function regdec(v : std_logic_vector) return string is
variable t : std_logic_vector(4 downto 0);
variable rt : character;
begin
t := v;
case t(4 downto 3) is
when "00" => rt := 'g';
when "01" => rt := 'o';
when "10" => rt := 'l';
when "11" => rt := 'i';
when others => rt := 'X';
end case;
if v(4 downto 0) = "11110" then
return("%fp");
elsif v(4 downto 0) = "01110" then
return("%sp");
else
return('%' & rt & tost('0' & t(2 downto 0)));
end if;
end;
function simm13dec(insn : debug_info; base : base_type; merge : boolean) return string is
variable simm : std_logic_vector(12 downto 0) := insn.op(12 downto 0);
variable rs1 : std_logic_vector(4 downto 0) := insn.op(18 downto 14);
variable i : std_logic := insn.op(13);
variable sig : character;
variable fill : std_logic_vector(31 downto 13) := (others => simm(12));
begin
if i = '0' then
return("");
else
if (simm(12) = '1') and (base = dec) then
sig := '-'; simm := (not simm) + 1;
else
sig := '+';
end if;
if base = dec then
if merge then
if rs1 = "00000" then
return(tost(simm));
else
return(sig & tost(simm));
end if;
else
if rs1 = "00000" then
return(tost(simm));
else
if sig = '-' then
return(", " & sig & tost(simm));
else
return(", " & tost(simm));
end if;
end if;
end if;
else
if rs1 = "00000" then
if simm(12) = '1' then return(tost(fill & simm));
else return(tost(simm)); end if;
else
if simm(12) = '1' then return(", " & tost(fill & simm));
else return(", " & tost(simm)); end if;
end if;
end if;
end if;
end;
function freg2(insn : debug_info) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_logic;
begin
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs2) &
", %f" & tostd(rd));
end;
function creg3(insn : debug_info) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_logic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%c" & tostd(rs1) & ", %c" & tostd(rs2) & ", %c" & tostd(rd));
end;
function freg3(insn : debug_info) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_logic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2) & ", %f" & tostd(rd));
end;
function fregc(insn : debug_info) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_logic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
return("%f" & tostd(rs1) & ", %f" & tostd(rs2));
end;
function regimm(insn : debug_info; base : base_type; merge : boolean) return string is
variable rs1, rs2 : std_logic_vector(4 downto 0);
variable i : std_logic;
begin
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
i := insn.op(13);
if i = '0' then
if (rs1 = "00000") then
if (rs2 = "00000") then
return("0");
else
return(regdec(rs2));
end if;
else
if (rs2 = "00000") then
return(regdec(rs1));
elsif merge then
return(regdec(rs1) & " + " & regdec(rs2));
else
return(regdec(rs1) & ", " & regdec(rs2));
end if;
end if;
else
if (rs1 = "00000") then
return(simm13dec(insn, base, merge));
elsif insn.op(12 downto 0) = "0000000000000" then
return(regdec(rs1));
else
return(regdec(rs1) & simm13dec(insn, base, merge));
end if;
end if;
end;
function regres(insn : debug_info; base : base_type) return string is
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable i : std_logic;
begin
rd := insn.op(29 downto 25);
return(regimm(insn, base,false) & ", " & regdec(rd ));
end;
function branchop(insn : debug_info) return string is
variable simm : std_logic_vector(31 downto 0);
begin
case insn.op(28 downto 25) is
when "0000" => return("n");
when "0001" => return("e");
when "0010" => return("le");
when "0011" => return("l");
when "0100" => return("lue");
when "0101" => return("cs");
when "0110" => return("neg");
when "0111" => return("vs");
when "1000" => return("a");
when "1001" => return("ne");
when "1010" => return("g");
when "1011" => return("ge");
when "1100" => return("gu");
when "1101" => return("cc");
when "1110" => return("pos");
when "1111" => return("vc");
when others => return("XXX");
end case;
end;
function fbranchop(insn : debug_info) return string is
variable simm : std_logic_vector(31 downto 0);
begin
case insn.op(28 downto 25) is
when "0000" => return("n");
when "0001" => return("ne");
when "0010" => return("lg");
when "0011" => return("ul");
when "0100" => return("l");
when "0101" => return("ug");
when "0110" => return("g");
when "0111" => return("u");
when "1000" => return("a");
when "1001" => return("e");
when "1010" => return("ue");
when "1011" => return("ge");
when "1100" => return("uge");
when "1101" => return("le");
when "1110" => return("ule");
when "1111" => return("o");
when others => return("XXX");
end case;
end;
function ldparcp(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%c" & tost(rd));
end;
function ldparf(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & "%f" & tostd(rd));
end;
function ldpar(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & ", " & regdec(rd));
end;
function ldpara(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
begin
return("[" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)) & ", " & regdec(rd));
end;
function stparc(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
begin
if rd = "00000" then
return("[" & regimm(insn,dec,true) & "]");
else
return(regdec(rd) & ", [" & regimm(insn,dec,true) & "]");
end if;
end;
function stparcp(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
begin
return("%c" & tost(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stparf(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
begin
return("%f" & tostd(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpar(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
begin
return(regdec(rd) & ", [" & regimm(insn,dec,true) & "]");
end;
function stpara(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
begin
return(regdec(rd) & ", [" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)));
end;
function disas(insn : debug_info) return string is
constant STMAX : natural := 9;
constant bl2 : string(1 to 2) := (others => ' ');
constant bb : string(1 to (4)) := (others => ' ');
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable opf : std_logic_vector(8 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable addr : std_logic_vector(31 downto 0);
variable annul : std_logic;
variable i : std_logic;
variable simm : std_logic_vector(12 downto 0);
variable disen : boolean := true;
begin
if disen then
op := insn.op(31 downto 30);
op2 := insn.op(24 downto 22);
op3 := insn.op(24 downto 19);
opf := insn.op(13 downto 5);
cond := insn.op(28 downto 25);
annul := insn.op(29);
rs1 := insn.op(18 downto 14);
rs2 := insn.op(4 downto 0);
rd := insn.op(29 downto 25);
i := insn.op(13);
simm := insn.op(12 downto 0);
case op is
when CALL =>
addr := insn.pc + (insn.op(29 downto 0) & "00");
return(tostf(insn.pc) & bb & "call" & bl2 & tost(addr));
when FMT2 =>
case op2 is
when UNIMP => return(tostf(insn.pc) & bb & "unimp");
when SETHI =>
if rd = "00000" then
return(tostf(insn.pc) & bb & "nop");
else
return(tostf(insn.pc) & bb & "sethi" & bl2 & "%hi(" &
tost(insn.op(21 downto 0) & "0000000000") & "), " & regdec(rd));
end if;
when BICC | FBFCC =>
addr(31 downto 24) := (others => '0');
addr(1 downto 0) := (others => '0');
addr(23 downto 2) := insn.op(21 downto 0);
if addr(23) = '1' then
addr(31 downto 24) := (others => '1');
else
addr(31 downto 24) := (others => '0');
end if;
addr := addr + insn.pc;
if op2 = BICC then
if insn.op(29) = '1' then
return(tostf(insn.pc) & bb & 'b' & branchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(insn.pc) & bb & 'b' & branchop(insn) & bl2 &
tost(addr));
end if;
else
if insn.op(29) = '1' then
return(tostf(insn.pc) & bb & "fb" & fbranchop(insn) & ",a" & bl2 &
tost(addr));
else
return(tostf(insn.pc) & bb & "fb" & fbranchop(insn) & bl2 &
tost(addr));
end if;
end if;
-- when CBCCC => cptrap := '1';
when others => return(tostf(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
end case;
when FMT3 =>
case op3 is
when IAND => return(tostf(insn.pc) & bb & "and" & bl2 & regres(insn,hex));
when IADD => return(tostf(insn.pc) & bb & "add" & bl2 & regres(insn,dec));
when IOR =>
if ((i = '0') and (rs1 = "00000") and (rs2 = "00000")) then
return(tostf(insn.pc) & bb & "clr" & bl2 & regdec(rd));
elsif ((i = '1') and (simm = "0000000000000")) or (rs1 = "00000") then
return(tostf(insn.pc) & bb & "mov" & bl2 & regres(insn,hex));
else
return(tostf(insn.pc) & bb & "or " & bl2 & regres(insn,hex));
end if;
when IXOR => return(tostf(insn.pc) & bb & "xor" & bl2 & regres(insn,hex));
when ISUB => return(tostf(insn.pc) & bb & "sub" & bl2 & regres(insn,dec));
when ANDN => return(tostf(insn.pc) & bb & "andn" & bl2 & regres(insn,hex));
when ORN => return(tostf(insn.pc) & bb & "orn" & bl2 & regres(insn,hex));
when IXNOR =>
if ((i = '0') and ((rs1 = rd) or (rs2 = "00000"))) then
return(tostf(insn.pc) & bb & "not" & bl2 & regdec(rd));
else
return(tostf(insn.pc) & bb & "xnor" & bl2 & regdec(rd));
end if;
when ADDX => return(tostf(insn.pc) & bb & "addx" & bl2 & regres(insn,dec));
when SUBX => return(tostf(insn.pc) & bb & "subx" & bl2 & regres(insn,dec));
when ADDCC => return(tostf(insn.pc) & bb & "addcc" & bl2 & regres(insn,dec));
when ANDCC => return(tostf(insn.pc) & bb & "andcc" & bl2 & regres(insn,hex));
when ORCC => return(tostf(insn.pc) & bb & "orcc" & bl2 & regres(insn,hex));
when XORCC => return(tostf(insn.pc) & bb & "xorcc" & bl2 & regres(insn,hex));
when SUBCC => return(tostf(insn.pc) & bb & "subcc" & bl2 & regres(insn,dec));
when ANDNCC => return(tostf(insn.pc) & bb & "andncc" & bl2 & regres(insn,hex));
when ORNCC => return(tostf(insn.pc) & bb & "orncc" & bl2 & regres(insn,hex));
when XNORCC => return(tostf(insn.pc) & bb & "xnorcc" & bl2 & regres(insn,hex));
when ADDXCC => return(tostf(insn.pc) & bb & "addxcc" & bl2 & regres(insn,hex));
when UMAC => return(tostf(insn.pc) & bb & "umac" & bl2 & regres(insn,dec));
when SMAC => return(tostf(insn.pc) & bb & "smac" & bl2 & regres(insn,dec));
when UMUL => return(tostf(insn.pc) & bb & "umul" & bl2 & regres(insn,dec));
when SMUL => return(tostf(insn.pc) & bb & "smul" & bl2 & regres(insn,dec));
when UMULCC => return(tostf(insn.pc) & bb & "umulcc" & bl2 & regres(insn,dec));
when SMULCC => return(tostf(insn.pc) & bb & "smulcc" & bl2 & regres(insn,dec));
when SUBXCC => return(tostf(insn.pc) & bb & "subxcc" & bl2 & regres(insn,dec));
when UDIV => return(tostf(insn.pc) & bb & "udiv" & bl2 & regres(insn,dec));
when SDIV => return(tostf(insn.pc) & bb & "sdiv" & bl2 & regres(insn,dec));
when UDIVCC => return(tostf(insn.pc) & bb & "udivcc" & bl2 & regres(insn,dec));
when SDIVCC => return(tostf(insn.pc) & bb & "sdivcc" & bl2 & regres(insn,dec));
when TADDCC => return(tostf(insn.pc) & bb & "taddcc" & bl2 & regres(insn,dec));
when TSUBCC => return(tostf(insn.pc) & bb & "tsubcc" & bl2 & regres(insn,dec));
when TADDCCTV => return(tostf(insn.pc) & bb & "taddcctv" & bl2 & regres(insn,dec));
when TSUBCCTV => return(tostf(insn.pc) & bb & "tsubcctv" & bl2 & regres(insn,dec));
when MULSCC => return(tostf(insn.pc) & bb & "mulscc" & bl2 & regres(insn,dec));
when ISLL => return(tostf(insn.pc) & bb & "sll" & bl2 & regres(insn,dec));
when ISRL => return(tostf(insn.pc) & bb & "srl" & bl2 & regres(insn,dec));
when ISRA => return(tostf(insn.pc) & bb & "sra" & bl2 & regres(insn,dec));
when RDY =>
if rs1 /= "00000" then
return(tostf(insn.pc) & bb & "mov" & bl2 & "%asr" &
tost(rs1) & ", " & regdec(rd));
else
return(tostf(insn.pc) & bb & "mov" & bl2 & "%y, " & regdec(rd));
end if;
when RDPSR => return(tostf(insn.pc) & bb & "mov" & bl2 & "%psr, " & regdec(rd));
when RDWIM => return(tostf(insn.pc) & bb & "mov" & bl2 & "%wim, " & regdec(rd));
when RDTBR => return(tostf(insn.pc) & bb & "mov" & bl2 & "%tbr, " & regdec(rd));
when WRY =>
if (rs1 = "00000") or (rs2 = "00000") then
if rd /= "00000" then
return(tostf(insn.pc) & bb & "mov" & bl2
& regimm(insn,hex,false) & ", %asr" & tost(rd));
else
return(tostf(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %y");
end if;
else
if rd /= "00000" then
return(tostf(insn.pc) & bb & "wr " & bl2 & "%asr"
& regimm(insn,hex,false) & ", %asr" & tost(rd));
else
return(tostf(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %y");
end if;
end if;
when WRPSR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %psr");
else
return(tostf(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %psr");
end if;
when WRWIM =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %wim");
else
return(tostf(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %wim");
end if;
when WRTBR =>
if (rs1 = "00000") or (rs2 = "00000") then
return(tostf(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %tbr");
else
return(tostf(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %tbr");
end if;
when JMPL =>
if (rd = "00000") then
if (i = '1') and (simm = "0000000001000") then
if (rs1 = "11111") then
return(tostf(insn.pc) & bb & "ret");
elsif (rs1 = "01111") then
return(tostf(insn.pc) & bb & "retl");
else
return(tostf(insn.pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else
return(tostf(insn.pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
end if;
else
return(tostf(insn.pc) & bb & "jmpl" & bl2 & regres(insn,dec));
end if;
when TICC =>
return(tostf(insn.pc) & bb & 't' & branchop(insn) & bl2 & regimm(insn,hex,false));
when FLUSH =>
return(tostf(insn.pc) & bb & "flush" & bl2 & regimm(insn,hex,false));
when RETT =>
return(tostf(insn.pc) & bb & "rett" & bl2 & regimm(insn,dec,false));
when RESTORE =>
if (rd = "00000") then
return(tostf(insn.pc) & bb & "restore");
else
return(tostf(insn.pc) & bb & "restore" & bl2 & regres(insn,hex));
end if;
when SAVE =>
if (rd = "00000") then
return(tostf(insn.pc) & bb & "save");
else
return(tostf(insn.pc) & bb & "save" & bl2 & regres(insn,dec));
end if;
when FPOP1 =>
case opf is
when FITOS => return(tostf(insn.pc) & bb & "fitos" & bl2 & freg2(insn));
when FITOD => return(tostf(insn.pc) & bb & "fitod" & bl2 & freg2(insn));
when FDTOI => return(tostf(insn.pc) & bb & "fdtoi" & bl2 & freg2(insn));
when FSTOD => return(tostf(insn.pc) & bb & "fstod" & bl2 & freg2(insn));
when FDTOS => return(tostf(insn.pc) & bb & "fdtos" & bl2 & freg2(insn));
when FMOVS => return(tostf(insn.pc) & bb & "fmovs" & bl2 & freg2(insn));
when FNEGS => return(tostf(insn.pc) & bb & "fnegs" & bl2 & freg2(insn));
when FABSS => return(tostf(insn.pc) & bb & "fabss" & bl2 & freg2(insn));
when FSQRTS => return(tostf(insn.pc) & bb & "fsqrts" & bl2 & freg2(insn));
when FSQRTD => return(tostf(insn.pc) & bb & "fsqrtd" & bl2 & freg2(insn));
when FADDS => return(tostf(insn.pc) & bb & "fadds" & bl2 & freg3(insn));
when FADDD => return(tostf(insn.pc) & bb & "faddd" & bl2 & freg3(insn));
when FSUBS => return(tostf(insn.pc) & bb & "fsubs" & bl2 & freg3(insn));
when FSUBD => return(tostf(insn.pc) & bb & "fsubd" & bl2 & freg3(insn));
when FMULS => return(tostf(insn.pc) & bb & "fmuls" & bl2 & freg3(insn));
when FMULD => return(tostf(insn.pc) & bb & "fmuld" & bl2 & freg3(insn));
when FSMULD => return(tostf(insn.pc) & bb & "fsmuld" & bl2 & freg3(insn));
when FDIVS => return(tostf(insn.pc) & bb & "fdivs" & bl2 & freg3(insn));
when FDIVD => return(tostf(insn.pc) & bb & "fdivd" & bl2 & freg3(insn));
when others => return(tostf(insn.pc) & bb & "unknown Fopcode: " & tost(insn.op));
end case;
when FPOP2 =>
case opf is
when FCMPS => return(tostf(insn.pc) & bb & "fcmps" & bl2 & fregc(insn));
when FCMPD => return(tostf(insn.pc) & bb & "fcmpd" & bl2 & fregc(insn));
when FCMPES => return(tostf(insn.pc) & bb & "fcmpes" & bl2 & fregc(insn));
when FCMPED => return(tostf(insn.pc) & bb & "fcmped" & bl2 & fregc(insn));
when others => return(tostf(insn.pc) & bb & "unknown Fopcode: " & tost(insn.op));
end case;
when CPOP1 =>
return(tostf(insn.pc) & bb & "cpop1" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when CPOP2 =>
return(tostf(insn.pc) & bb & "cpop2" & bl2 & tost("000"&opf) & ", " &creg3(insn));
when others => return(tostf(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
end case;
when LDST =>
case op3 is
when STC =>
return(tostf(insn.pc) & bb & "st" & bl2 & stparcp(insn, rd, dec));
when STF =>
return(tostf(insn.pc) & bb & "st" & bl2 & stparf(insn, rd, dec));
when ST =>
if rd = "00000" then
return(tostf(insn.pc) & bb & "clr" & bl2 & stparc(insn, rd, dec));
else
return(tostf(insn.pc) & bb & "st" & bl2 & stpar(insn, rd, dec));
end if;
when STB =>
if rd = "00000" then
return(tostf(insn.pc) & bb & "clrb" & bl2 & stparc(insn, rd, dec));
else
return(tostf(insn.pc) & bb & "stb" & bl2 & stpar(insn, rd, dec));
end if;
when STH =>
if rd = "00000" then
return(tostf(insn.pc) & bb & "clrh" & bl2 & stparc(insn, rd, dec));
else
return(tostf(insn.pc) & bb & "sth" & bl2 & stpar(insn, rd, dec));
end if;
when STDC =>
return(tostf(insn.pc) & bb & "std" & bl2 & stparcp(insn, rd, dec));
when STDF =>
return(tostf(insn.pc) & bb & "std" & bl2 & stparf(insn, rd, dec));
when STCSR =>
return(tostf(insn.pc) & bb & "st" & bl2 & "%csr, [" & regimm(insn,dec,true) & "]");
when STFSR =>
return(tostf(insn.pc) & bb & "st" & bl2 & "%fsr, [" & regimm(insn,dec,true) & "]");
when STDCQ =>
return(tostf(insn.pc) & bb & "std" & bl2 & "%cq, [" & regimm(insn,dec,true) & "]");
when STDFQ =>
return(tostf(insn.pc) & bb & "std" & bl2 & "%fq, [" & regimm(insn,dec,true) & "]");
when ISTD =>
return(tostf(insn.pc) & bb & "std" & bl2 & stpar(insn, rd, dec));
when STA =>
return(tostf(insn.pc) & bb & "sta" & bl2 & stpara(insn, rd, dec));
when STBA =>
return(tostf(insn.pc) & bb & "stba" & bl2 & stpara(insn, rd, dec));
when STHA =>
return(tostf(insn.pc) & bb & "stha" & bl2 & stpara(insn, rd, dec));
when STDA =>
return(tostf(insn.pc) & bb & "stda" & bl2 & stpara(insn, rd, dec));
when LDC =>
return(tostf(insn.pc) & bb & "ld" & bl2 & ldparcp(insn, rd, dec));
when LDF =>
return(tostf(insn.pc) & bb & "ld" & bl2 & ldparf(insn, rd, dec));
when LDCSR =>
return(tostf(insn.pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %csr");
when LDFSR =>
return(tostf(insn.pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %fsr");
when LD =>
return(tostf(insn.pc) & bb & "ld" & bl2 & ldpar(insn, rd, dec));
when LDUB =>
return(tostf(insn.pc) & bb & "ldub" & bl2 & ldpar(insn, rd, dec));
when LDUH =>
return(tostf(insn.pc) & bb & "lduh" & bl2 & ldpar(insn, rd, dec));
when LDDC =>
return(tostf(insn.pc) & bb & "ldd" & bl2 & ldparcp(insn, rd, dec));
when LDDF =>
return(tostf(insn.pc) & bb & "ldd" & bl2 & ldparf(insn, rd, dec));
when LDD =>
return(tostf(insn.pc) & bb & "ldd" & bl2 & ldpar(insn, rd, dec));
when LDSB =>
return(tostf(insn.pc) & bb & "ldsb" & bl2 & ldpar(insn, rd, dec));
when LDSH =>
return(tostf(insn.pc) & bb & "ldsh" & bl2 & ldpar(insn, rd, dec));
when LDSTUB =>
return(tostf(insn.pc) & bb & "ldstub" & bl2 & ldpar(insn, rd, dec));
when SWAP =>
return(tostf(insn.pc) & bb & "swap" & bl2 & ldpar(insn, rd, dec));
when LDA =>
return(tostf(insn.pc) & bb & "lda" & bl2 & ldpara(insn, rd, dec));
when LDUBA =>
return(tostf(insn.pc) & bb & "lduba" & bl2 & ldpara(insn, rd, dec));
when LDUHA =>
return(tostf(insn.pc) & bb & "lduha" & bl2 & ldpara(insn, rd, dec));
when LDDA =>
return(tostf(insn.pc) & bb & "ldda" & bl2 & ldpara(insn, rd, dec));
when LDSBA =>
return(tostf(insn.pc) & bb & "ldsba" & bl2 & ldpara(insn, rd, dec));
when LDSHA =>
return(tostf(insn.pc) & bb & "ldsha" & bl2 & ldpara(insn, rd, dec));
when LDSTUBA =>
return(tostf(insn.pc) & bb & "ldstuba" & bl2 & ldpara(insn, rd, dec));
when SWAPA =>
return(tostf(insn.pc) & bb & "swapa" & bl2 & ldpara(insn, rd, dec));
when others => return(tostf(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
end case;
when others => return(tostf(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
end case;
end if;
end;
procedure print(s : string) is
variable L1 : line;
begin
L1:= new string'(s); --'
-- write(L1, s);
writeline(output,L1);
end;
procedure trace(signal debug : in iu_debug_type; DISASS : boolean) is
variable insn : debug_info;
begin
if DISASS or DEBUGFPU then
if (debug.rst = '1') and debug.clk'event and (debug.clk = '1') and ((debug.holdn = '1') or GATEDCLK) then --'
insn.op := debug.wr.inst;
insn.pc := debug.wr.pc(31 downto 2) & "00";
if (debug.wr.annul or not debug.wr.pv) = '0' then
if DISASS then
if debug.trap = '1' then
print (disas(insn) & " (trapped, tt = " & tostf(debug.tt) & ")");
else
print (disas(insn));
end if;
end if;
end if;
if debug.wr.annul = '0' then
if DEBUGIURF then
if (debug.write_reg = '1') then
print(tostf(insn.pc) & ": %r" & tost(debug.wr.rd) & " = " & tost(debug.result));
end if;
end if;
if DEBUGFPU and (FPTYPE = meiko) then
if (debug.write_reg = '1') and (debug.wr.rd(7 downto 5) = "100") then
print(tosth(insn.pc) & ": %f" & tostd(debug.wr.rd(4 downto 0)) &
" = " & tosth(debug.result));
end if;
end if;
end if;
end if;
end if;
end;
end debug;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/uart.vhd
|
1
|
11604
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: uart
-- File: uart.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Asynchronous UART. Implements 8-bit data frame with one
-- stop-bit. Programmable options:
-- * parity bit (on/off)
-- * parity polarity (odd/even)
-- * baud-rate (12-bit programmable divider)
-- * hardware flow-control (CTS/RTS)
-- * Loop-back testing
-- Error-detection in receiver detects parity, framing
-- break and overrun errors.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.target.all;
use work.config.all;
use work.iface.all;
use work.macro.all;
use work.amba.all;
--pragma translate_off
use ieee.std_logic_unsigned.conv_integer;
use STD.TEXTIO.all;
--pragma translate_on
entity uart is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type
);
end;
architecture rtl of uart is
type rxfsmtype is (idle, startbit, data, parity, stopbit);
type txfsmtype is (idle, data, parity, stopbit);
type uartregs is record
rxen : std_logic; -- receiver enabled
txen : std_logic; -- transmitter enabled
rirqen : std_logic; -- receiver irq enable
tirqen : std_logic; -- transmitter irq enable
parsel : std_logic; -- parity select
paren : std_logic; -- parity select
flow : std_logic; -- flow control enable
loopb : std_logic; -- loop back mode enable
dready : std_logic; -- data ready
rsempty : std_logic; -- receiver shift register empty (internal)
tsempty : std_logic; -- transmitter shift register empty
thempty : std_logic; -- transmitter hold register empty
break : std_logic; -- break detected
ovf : std_logic; -- receiver overflow
parerr : std_logic; -- parity error
frame : std_logic; -- framing error
rtsn : std_logic; -- request to send
extclken : std_logic; -- use external baud rate clock
extclk : std_logic; -- rising edge detect register
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : std_logic_vector(7 downto 0);
irq : std_logic; -- tx/rx interrupt (internal)
tpar : std_logic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_logic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(2 downto 0); -- rx data filtering buffer
dpar : std_logic; -- rx data parity (internal)
rxtick : std_logic; -- rx clock (internal)
tick : std_logic; -- rx clock (internal)
scaler : std_logic_vector(11 downto 0);
brate : std_logic_vector(11 downto 0);
end record;
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(11 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd : std_logic;
variable v : uartregs;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(2 downto 1) := r.rxdb(1 downto 0);
-- scaler
-- pragma translate_off
if not is_x(r.scaler) then -- avoid warnings at reset time
-- pragma translate_on
scaler := r.scaler - 1;
-- pragma translate_off
end if;
-- pragma translate_on
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(11) and not r.scaler(11);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.scaler(3);
if r.extclken = '1' then v.tick := r.extclk and not uarti.scaler(3); end if;
-- read/write registers
case apbi.paddr(3 downto 2) is
when "00" =>
rdata(7 downto 0) := r.rhold;
if (apbi.psel and apbi.penable and (not apbi.pwrite)) = '1' then
v.dready := '0';
end if;
when "01" =>
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
--pragma translate_off
if DEBUGUART then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "10" =>
rdata(8 downto 0) := r.extclken & r.loopb & r.flow & r.paren & r.parsel &
r.tirqen & r.rirqen & r.txen & r.rxen;
when others =>
rdata(11 downto 0) := r.brate;
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(11 downto 0);
v.scaler := apbi.pwdata(11 downto 0);
when others =>
end case;
end if;
-- tx clock
-- pragma translate_off
if not is_x(r.txclk) then -- avoid warnings at reset time
-- pragma translate_on
txclk := r.txclk + 1;
-- pragma translate_off
else
txclk := (others => 'X');
end if;
-- pragma translate_on
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
-- pragma translate_off
if not is_x(r.rxclk) then -- avoid warnings at reset time
-- pragma translate_on
rxclk := r.rxclk + 1;
-- pragma translate_off
else
rxclk := (others => 'X');
end if;
-- pragma translate_on
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
if r.loopb = '1' then v.rxdb(0) := r.tshift(0);
else v.rxdb(0) := uarti.rxd; end if;
rxd := r.rxdb(1);
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((r.txen and (not r.thempty) and r.txtick) and
((not uarti.ctsn) or not r.flow)) = '1' then
v.tshift := "10" & r.thold & '0'; v.txstate := data;
v.tpar := r.parsel; v.irq := r.tirqen; v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmitt data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := parity;
else
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
end if;
when parity => -- transmitt parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := stopbit;
end if;
when stopbit => -- transmitt stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
v.thold := apbi.pwdata(7 downto 0); v.thempty := '0';
--pragma translate_off
if DEBUGUART then
if first then L1:= new string'(""); first := false; end if; --'
if (pt + 20 ns) < now then
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb(2) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := parity;
else
v.rxstate := stopbit; v.dpar := '0';
end if;
end if;
end if;
when parity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
if rxd = '1' then
v.parerr := r.dpar; v.dready := not r.dpar;
v.rsempty := r.dpar;
if (v.dready and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then v.rtsn := r.dready and not r.rsempty; end if;
-- reset operation
if rst = '0' then
v.frame := '0'; v.rsempty := '1';
v.parerr := '0'; v.ovf := '0'; v.break := '0'; v.thempty := '1';
v.tsempty := '1'; v.dready := '0'; v.txen := '0'; v.rxen := '0';
v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
v.extclken := '0';
if BOOTOPT /= memory then
if EXTBAUD then v.brate := "0000" & uarti.scaler;
else v.brate := std_logic_vector(UPRESC(11 downto 0)); end if;
v.scaler := v.brate;
-- else
-- v.brate := (others => '0');
end if;
-- pragma translate_off
-- v.scaler := (others => '0'); -- only need this for simulation
-- pragma translate_on
v.rtsn := '1'; v.flow := '0';
v.txclk := (others => '0'); v.rxclk := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.tshift(0) or r.loopb;
uarto.irq <= r.irq;
uarto.flow <= r.flow;
uarto.rtsn <= r.rtsn;
uarto.txen <= r.txen;
uarto.rxen <= r.rxen;
apbo.prdata <= rdata;
end process;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/MILK_2007/src/cop_rfile3.vhd
|
1
|
13533
|
-----------------------------------------------------------------------------------------------------------
--
-- REGISTER FILE
--
-- The register file is a read/write memory, made up of 8 32-bit general purpose registers.
-- It can be addressed by different resources in a concurrent enviroment.
-- This model is a 3-read and 11-write ports
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------------
--Copyright (c) 2004, Tampere University of Technology.
--All rights reserved.
--Redistribution and use in source and binary forms, with or without modification,
--are permitted provided that the following conditions are met:
--* Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--* Neither the name of Tampere University of Technology nor the names of its
-- contributors may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
--CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND
--FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
--OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
--EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
--PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN
--IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
package milk_regfile is
component Milk_RFile
port( clk : in Std_logic;
reset : in Std_logic;
enable : in Std_logic;
coffee_out : out std_logic_vector(word_width-1 downto 0);
rs1 : in rf_addr;
rs1_out : out std_logic_vector(word_width-1 downto 0);
rs2 : in rf_addr;
rs2_out : out std_logic_vector(word_width-1 downto 0);
rcoffee_we : in std_logic;
rcoffee_in : in rf_addr;
coffee_in : in std_logic_vector(word_width-1 downto 0);
rd_we_1 : in std_logic;
rd_1 : in rf_addr;
d1_in : in std_logic_vector(word_width-1 downto 0);
rd_we_2 : in std_logic;
rd_2 : in rf_addr;
d2_in : in std_logic_vector(word_width-1 downto 0);
rd_we_3 : in std_logic;
rd_3 : in rf_addr;
d3_in : in std_logic_vector(word_width-1 downto 0);
rd_we_4 : in std_logic;
rd_4 : in rf_addr;
d4_in : in std_logic_vector(word_width-1 downto 0);
rd_we_5 : in std_logic;
rd_5 : in rf_addr;
d5_in : in std_logic_vector(word_width-1 downto 0);
rd_we_6 : in std_logic;
rd_6 : in rf_addr;
d6_in : in std_logic_vector(word_width-1 downto 0);
rd_we_7 : in std_logic;
rd_7 : in rf_addr;
d7_in : in std_logic_vector(word_width-1 downto 0);
rd_we_8 : in std_logic;
rd_8 : in rf_addr;
d8_in : in std_logic_vector(word_width-1 downto 0);
rd_we_9 : in std_logic;
rd_9 : in rf_addr;
d9_in : in std_logic_vector(word_width-1 downto 0);
next_lock_vector : in Std_logic_vector(RF_width-1 downto 0);
exc_doublewrite : out std_logic);
end component;
end milk_regfile;
package body milk_regfile is
end milk_regfile;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
use work.cop_components.all;
use work.milk_regfile.all;
entity Milk_Rfile is
port( clk : in Std_logic;
reset : in Std_logic;
enable : in Std_logic;
coffee_out : out std_logic_vector(word_width-1 downto 0);
rs1 : in rf_addr;
rs1_out : out std_logic_vector(word_width-1 downto 0);
rs2 : in rf_addr;
rs2_out : out std_logic_vector(word_width-1 downto 0);
rcoffee_we : in std_logic;
rcoffee_in : in rf_addr;
coffee_in : in std_logic_vector(word_width-1 downto 0);
rd_we_1 : in std_logic;
rd_1 : in rf_addr;
d1_in : in std_logic_vector(word_width-1 downto 0);
rd_we_2 : in std_logic;
rd_2 : in rf_addr;
d2_in : in std_logic_vector(word_width-1 downto 0);
rd_we_3 : in std_logic;
rd_3 : in rf_addr;
d3_in : in std_logic_vector(word_width-1 downto 0);
rd_we_4 : in std_logic;
rd_4 : in rf_addr;
d4_in : in std_logic_vector(word_width-1 downto 0);
rd_we_5 : in std_logic;
rd_5 : in rf_addr;
d5_in : in std_logic_vector(word_width-1 downto 0);
rd_we_6 : in std_logic;
rd_6 : in rf_addr;
d6_in : in std_logic_vector(word_width-1 downto 0);
rd_we_7 : in std_logic;
rd_7 : in rf_addr;
d7_in : in std_logic_vector(word_width-1 downto 0);
rd_we_8 : in std_logic;
rd_8 : in rf_addr;
d8_in : in std_logic_vector(word_width-1 downto 0);
rd_we_9 : in std_logic;
rd_9 : in rf_addr;
d9_in : in std_logic_vector(word_width-1 downto 0);
next_lock_vector : in Std_logic_vector(RF_width-1 downto 0);
exc_doublewrite : out std_logic );
end Milk_Rfile;
-----------------------------------------------------------------------------------
architecture rtl of Milk_Rfile is
type bus32x8 is array (7 downto 0) of Std_logic_vector(31 downto 0);
signal reg_in,reg_out : bus32x8;
signal coffeeout3,rs1out3,rs2out3 : std_logic_vector(word_width-1 downto 0);
signal wrbck_enabled_1,wrbck_enabled_2,wrbck_enabled_3,wrbck_enabled_4,
wrbck_enabled_5,wrbck_enabled_6,wrbck_enabled_7,wrbck_enabled_8,
wrbck_enabled_9,coffee_wr_enabled,
rd_8_1,rd_8_2,rd_8_3,rd_8_4,rd_8_5,rd_8_6,rd_8_7,rd_8_8,rd_8_9,rcoffee_in_8,
reg_we,wr_enable : std_logic_vector(RF_width-1 downto 0);
begin
----------------------------------------------------------
REGISTERS:for i in 0 to 7 generate
rx : we_register port map (clk => clk,reset => reset,we => wr_enable(i),
data_in => reg_in(i),data_out => reg_out(i) );
end generate Registers;
----------------------------------------------------------
-- Reg_file Reads from 3state busses
coffee_out <= coffeeout3;
rs1_out <= rs1out3;
rs2_out <= rs2out3;
----------------------------------------------------------
-- 3state bus handling:
COFFEEOUT_3STATEBUS: for i in 0 to 7 generate
process(rcoffee_in,reg_out,reg_in,reg_we,next_lock_vector)
begin
if ((i = Conv_integer(unsigned(rcoffee_in))) and (next_lock_vector(i) = '0')) then
if (reg_we(i) = '1') then
coffeeout3 <= reg_in(i);
else
coffeeout3 <= reg_out(i);
end if;
else
coffeeout3 <= (others => 'Z');
end if;
end process;
end generate COFFEEOUT_3STATEBUS;
RS1_3STATEBUS: for i in 0 to 7 generate
process(rs1,reg_out)
begin
if i = Conv_integer(unsigned(rs1)) then
rs1out3 <= reg_out(i);
else
rs1out3 <= (others => 'Z');
end if;
end process;
end generate RS1_3STATEBUS;
RS2_3STATEBUS: for i in 0 to 7 generate
process(rs2,reg_out)
begin
if i = Conv_integer(unsigned(rs2)) then
rs2out3 <= reg_out(i);
else
rs2out3 <= (others => 'Z');
end if;
end process;
end generate RS2_3STATEBUS;
----------------------------------------------------------
-- Reg_file writes. One is coming from the milk datapath
-- and one from Coffee
WRBCK_DATA_DEC_1: decoder3_8 port map(dec_addr => rd_1,dec_out => rd_8_1);
WRBCK_DATA_DEC_2: decoder3_8 port map(dec_addr => rd_2,dec_out => rd_8_2);
WRBCK_DATA_DEC_3: decoder3_8 port map(dec_addr => rd_3,dec_out => rd_8_3);
WRBCK_DATA_DEC_4: decoder3_8 port map(dec_addr => rd_4,dec_out => rd_8_4);
WRBCK_DATA_DEC_5: decoder3_8 port map(dec_addr => rd_5,dec_out => rd_8_5);
WRBCK_DATA_DEC_6: decoder3_8 port map(dec_addr => rd_6,dec_out => rd_8_6);
WRBCK_DATA_DEC_7: decoder3_8 port map(dec_addr => rd_7,dec_out => rd_8_7);
WRBCK_DATA_DEC_8: decoder3_8 port map(dec_addr => rd_8,dec_out => rd_8_8);
WRBCK_DATA_DEC_9: decoder3_8 port map(dec_addr => rd_9,dec_out => rd_8_9);
COFFEE_IN_DEC : decoder3_8 port map(dec_addr => rcoffee_in,dec_out => rcoffee_in_8);
REGFILE_WRITE : process(rd_8_1,rd_8_2,rd_8_3,rd_8_4,rd_8_5,rd_8_6,rd_8_7,rd_8_8,rd_8_9,rcoffee_in_8,
d1_in,d2_in,d3_in,d4_in,d5_in,d6_in,d7_in,d8_in,d9_in,coffee_in,
rd_we_1,rd_we_2,rd_we_3,rd_we_4,rd_we_5,rd_we_6,rd_we_7,rd_we_8,rd_we_9,rcoffee_we,
wrbck_enabled_1,wrbck_enabled_2,wrbck_enabled_3,wrbck_enabled_4,wrbck_enabled_5,wrbck_enabled_6,
wrbck_enabled_7,wrbck_enabled_8,wrbck_enabled_9,coffee_wr_enabled,
reg_we,enable)
begin
for i in 0 to 7 loop
wrbck_enabled_1(i) <= (rd_8_1(i) and rd_we_1);
wrbck_enabled_2(i) <= (rd_8_2(i) and rd_we_2);
wrbck_enabled_3(i) <= (rd_8_3(i) and rd_we_3);
wrbck_enabled_4(i) <= (rd_8_4(i) and rd_we_4);
wrbck_enabled_5(i) <= (rd_8_5(i) and rd_we_5);
wrbck_enabled_6(i) <= (rd_8_6(i) and rd_we_6);
wrbck_enabled_7(i) <= (rd_8_7(i) and rd_we_7);
wrbck_enabled_8(i) <= (rd_8_8(i) and rd_we_8);
wrbck_enabled_9(i) <= (rd_8_9(i) and rd_we_9);
coffee_wr_enabled(i) <= (rcoffee_in_8(i) and rcoffee_we);
reg_we(i) <= ( coffee_wr_enabled(i) or wrbck_enabled_1(i) or wrbck_enabled_2(i) or wrbck_enabled_3(i) or
wrbck_enabled_4(i) or wrbck_enabled_5(i) or wrbck_enabled_6(i) or wrbck_enabled_7(i)
or wrbck_enabled_8(i) or wrbck_enabled_9(i));
wr_enable(i) <= ( enable and reg_we(i) );
if ( wrbck_enabled_1(i) = '1' ) then
reg_in(i) <= d1_in;
elsif ( wrbck_enabled_2(i) = '1' ) then
reg_in(i) <= d2_in;
elsif ( wrbck_enabled_3(i) = '1' ) then
reg_in(i) <= d3_in;
elsif ( wrbck_enabled_4(i) = '1' ) then
reg_in(i) <= d4_in;
elsif ( wrbck_enabled_5(i) = '1' ) then
reg_in(i) <= d5_in;
elsif ( wrbck_enabled_6(i) = '1' ) then
reg_in(i) <= d6_in;
elsif ( wrbck_enabled_7(i) = '1' ) then
reg_in(i) <= d7_in;
elsif ( wrbck_enabled_8(i) = '1' ) then
reg_in(i) <= d8_in;
elsif ( wrbck_enabled_9(i) = '1' ) then
reg_in(i) <= d9_in;
else
reg_in(i) <= coffee_in;
end if;
end loop;
end process;
exc_doublewrite <= '0';
end rtl;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature_KOA/gen_hdl_multiplier-master/example/smul_lib.vhdl
|
1
|
4253
|
--
-- Flip-flop.
--
library ieee;
use ieee.std_logic_1164.all;
entity smul_flipflop is
port (
clk: in std_ulogic;
clken: in std_ulogic;
d: in std_ulogic;
q: out std_ulogic );
end entity;
architecture smul_flipflop_arch of smul_flipflop is
begin
process (clk) is
begin
if rising_edge(clk) then
if to_x01(clken) = '1' then
q <= d;
end if;
end if;
end process;
end architecture;
--
-- Inverter.
--
library ieee;
use ieee.std_logic_1164.all;
entity smul_inverter is
port (
d: in std_ulogic;
q: out std_ulogic );
end entity;
architecture smul_inverter_arch of smul_inverter is
begin
q <= not d;
end architecture;
--
-- Half-adder.
--
library ieee;
use ieee.std_logic_1164.all;
entity smul_half_add is
port (
x: in std_ulogic;
y: in std_ulogic;
d: out std_ulogic;
c: out std_ulogic );
end entity;
architecture smul_half_add_arch of smul_half_add is
begin
d <= x xor y;
c <= x and y;
end architecture;
--
-- Full-adder.
--
library ieee;
use ieee.std_logic_1164.all;
entity smul_full_add is
port (
x: in std_ulogic;
y: in std_ulogic;
z: in std_ulogic;
d: out std_ulogic;
c: out std_ulogic );
end entity;
architecture smul_full_add_arch of smul_full_add is
begin
d <= x xor y xor z;
c <= (x and y) or (y and z) or (x and z);
end architecture;
--
-- Booth negative flag.
--
library ieee;
use ieee.std_logic_1164.all;
entity smul_booth_neg is
port (
p0: in std_ulogic;
p1: in std_ulogic;
p2: in std_ulogic;
f: out std_ulogic );
end entity;
architecture smul_booth_neg_arch of smul_booth_neg is
begin
f <= p2 and ((not p1) or (not p0));
end architecture;
--
-- Booth partial product generation.
--
library ieee;
use ieee.std_logic_1164.all;
entity smul_booth_prod is
port (
p0: in std_ulogic;
p1: in std_ulogic;
p2: in std_ulogic;
b0: in std_ulogic;
b1: in std_ulogic;
y: out std_ulogic );
end entity;
architecture smul_booth_prod_arch of smul_booth_prod is
begin
process (p0, p1, p2, b0, b1) is
variable p: std_ulogic_vector(2 downto 0);
begin
p := (p2, p1, p0);
case p is
when "000" => y <= '0'; -- factor 0
when "001" => y <= b1; -- factor 1
when "010" => y <= b1; -- factor 1
when "011" => y <= b0; -- factor 2
when "100" => y <= not b0; -- factor -2
when "101" => y <= not b1; -- factor -1
when "110" => y <= not b1; -- factor -1
when others => y <= '0'; -- factor 0
end case;
end process;
end architecture;
--
-- Determine carry generate and carry propagate.
--
library ieee;
use ieee.std_logic_1164.all;
entity smul_carry_prop is
port (
a: in std_ulogic;
b: in std_ulogic;
g: out std_ulogic;
p: out std_ulogic );
end entity;
architecture smul_carry_prop of smul_carry_prop is
begin
g <= a and b;
p <= a xor b;
end architecture;
--
-- Merge two carry propagation trees.
--
library ieee;
use ieee.std_logic_1164.all;
entity smul_carry_merge is
port (
g0: in std_ulogic;
p0: in std_ulogic;
g1: in std_ulogic;
p1: in std_ulogic;
g: out std_ulogic;
p: out std_ulogic );
end entity;
architecture smul_carry_merge of smul_carry_merge is
begin
g <= g1 or (g0 and p1);
p <= p0 and p1;
end architecture;
--
-- Calculate carry-out through a carry propagation tree.
--
library ieee;
use ieee.std_logic_1164.all;
entity smul_carry_eval is
port (
g: in std_ulogic;
p: in std_ulogic;
cin: in std_ulogic;
cout: out std_ulogic );
end entity;
architecture smul_carry_eval of smul_carry_eval is
begin
cout <= g or (p and cin);
end architecture;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/tech_generic.vhd
|
3
|
17873
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: tech_generic
-- File: tech_generic.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Contains behavioural pads and ram generators
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package tech_generic is
-- generic sync ram
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_logic;
write : in std_logic
);
end component;
-- regfile generator
component generic_regfile_iu
generic (
rftype : integer := 1;
abits : integer := 8; dbits : integer := 32; words : integer := 128
);
port (
rst : in std_logic;
clk : in std_logic;
clkn : in std_logic;
rfi : in rf_in_type;
rfo : out rf_out_type);
end component;
component generic_regfile_cp
generic (
abits : integer := 4; dbits : integer := 32; words : integer := 16
);
port (
rst : in std_logic;
clk : in std_logic;
rfi : in rf_cp_in_type;
rfo : out rf_cp_out_type);
end component;
-- bypass logic for async-read/sync-write regfiles
component rfbypass
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
clk : in clk_type;
write : in std_logic;
datain: in std_logic_vector (dbits -1 downto 0);
raddr1: in std_logic_vector (abits -1 downto 0);
raddr2: in std_logic_vector (abits -1 downto 0);
waddr : in std_logic_vector (abits -1 downto 0);
q1 : in std_logic_vector (dbits -1 downto 0);
q2 : in std_logic_vector (dbits -1 downto 0);
dataout1 : out std_logic_vector (dbits -1 downto 0);
dataout2 : out std_logic_vector (dbits -1 downto 0)
);
end component;
-- generic multipler
component generic_smult
generic ( abits : integer := 10; bbits : integer := 8 );
port (
a : in std_logic_vector(abits-1 downto 0);
b : in std_logic_vector(bbits-1 downto 0);
c : out std_logic_vector(abits+bbits-1 downto 0)
);
end component;
-- pads
component geninpad port (pad : in std_logic; q : out std_logic); end component;
component gensmpad port (pad : in std_logic; q : out std_logic); end component;
component genoutpad port (d : in std_logic; pad : out std_logic); end component;
component gentoutpadu port (d, en : in std_logic; pad : out std_logic); end component;
component geniopad
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component geniodpad
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end component;
component genodpad port ( d : in std_logic; pad : out std_logic); end component;
end;
library IEEE;
use IEEE.std_logic_1164.all;
------------------------------------------------------------------
-- behavioural ram models --------------------------------------------
------------------------------------------------------------------
-- synchronous ram for direct interference
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.iface.all;
entity generic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_logic;
write : in std_logic
);
end;
architecture behavioral of generic_syncram is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of memarr: signal is "block_ram";
-- pragma translate_off
signal rw : std_logic;
-- pragma translate_on
begin
main : process(clk, memarr, ra)
begin
if rising_edge(clk) then
if write = '1' then
-- pragma translate_off
if not is_x(address) then
-- pragma translate_on
memarr(conv_integer(unsigned(address))) <= datain;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
ra <= address;
-- pragma translate_off
rw <= write;
-- pragma translate_on
end if;
end process;
-- pragma translate_off
readport : process(memarr, ra, rw)
begin
if not (is_x(ra) or (rw = '1')) then
-- pragma translate_on
dataout <= memarr(conv_integer(unsigned(ra)));
-- pragma translate_off
else
dataout <= (others => 'X');
end if;
end process;
-- pragma translate_on
end;
-- synchronous dpram for direct instantiation
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.iface.all;
entity generic_dpram_ss is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
clk : in std_logic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_dpram_ss is
type dregtype is array (0 to words - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
signal wa, ra : std_logic_vector (abits -1 downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of rfd: signal is "block_ram";
-- pragma translate_off
signal drivex : boolean;
-- pragma translate_on
begin
rp : process(clk)
begin
if rising_edge(clk) then
if wren = '1' then
-- pragma translate_off
if not ( is_x(wraddress) or
(conv_integer(unsigned(wraddress)) >= words))
then
-- pragma translate_on
rfd(conv_integer(unsigned(wraddress))) <= data;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
-- pragma translate_off
drivex <= (wren = '1') and (wraddress = rdaddress);
-- pragma translate_on
ra <= rdaddress;
end if;
end process;
-- pragma translate_off
readport : process(rfd, ra, drivex)
begin
if not (is_x(ra) or (conv_integer(unsigned(ra)) >= words) or drivex)
then
-- pragma translate_on
q <= rfd(conv_integer(unsigned(ra)));
-- pragma translate_off
else
q <= (others => 'X');
end if;
end process;
-- pragma translate_on
end;
-- async dpram for direct instantiation
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.iface.all;
entity generic_dpram_as is
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
clk : in std_logic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_dpram_as is
type dregtype is array (0 to words - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
signal wa : std_logic_vector (abits -1 downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of rfd: signal is "block_ram";
begin
rp : process(clk)
begin
if rising_edge(clk) then
if wren = '1' then
-- pragma translate_off
if not ( is_x(wraddress) or
(conv_integer(unsigned(wraddress)) >= words))
then
-- pragma translate_on
rfd(conv_integer(unsigned(wraddress))) <= data;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
-- wa <= wraddress;
end if;
end process;
-- pragma translate_off
comb : process(rdaddress, rfd)
begin
if not (is_x(rdaddress) or (conv_integer(unsigned(rdaddress)) >= words))
then
-- pragma translate_on
q <= rfd(conv_integer(unsigned(rdaddress)));
-- pragma translate_off
else
q <= (others => 'X');
end if;
end process;
-- pragma translate_on
end;
-- Bypass logic for async regfiles with delayed (synchronous) write
-- Bypass written data to read port if write enabled
-- and read and write address are equal.
library IEEE;
use IEEE.std_logic_1164.all;
use work.iface.all;
entity rfbypass is
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
clk : in clk_type;
write : in std_logic;
datain: in std_logic_vector (dbits -1 downto 0);
raddr1: in std_logic_vector (abits -1 downto 0);
raddr2: in std_logic_vector (abits -1 downto 0);
waddr : in std_logic_vector (abits -1 downto 0);
q1 : in std_logic_vector (dbits -1 downto 0);
q2 : in std_logic_vector (dbits -1 downto 0);
dataout1 : out std_logic_vector (dbits -1 downto 0);
dataout2 : out std_logic_vector (dbits -1 downto 0)
);
end;
architecture rtl of rfbypass is
type wbypass_type is record
wraddr : std_logic_vector(abits-1 downto 0);
wrdata : std_logic_vector(dbits-1 downto 0);
wren : std_logic;
end record;
signal wbpr : wbypass_type;
begin
wbp_comb : process(q1, q2, wbpr, raddr1, raddr2)
begin
if (wbpr.wren = '1') and (wbpr.wraddr = raddr1) then
dataout1 <= wbpr.wrdata;
else dataout1 <= q1(dbits-1 downto 0); end if;
if (wbpr.wren = '1') and (wbpr.wraddr = raddr2) then
dataout2 <= wbpr.wrdata;
else dataout2 <= q2(dbits-1 downto 0); end if;
end process;
wbp_reg : process(clk)
begin
if rising_edge(clk) then
wbpr.wraddr <= waddr;
wbpr.wrdata <= datain;
wbpr.wren <= write;
end if;
end process;
end;
--------------------------------------------------------------------
-- regfile generators
--------------------------------------------------------------------
-- integer unit regfile
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;
entity generic_regfile_iu is
generic (
rftype : integer := 1;
abits : integer := 8; dbits : integer := 32; words : integer := 128
);
port (
rst : in std_logic;
clk : in std_logic;
clkn : in std_logic;
rfi : in rf_in_type;
rfo : out rf_out_type);
end;
architecture rtl of generic_regfile_iu is
component generic_dpram_ss
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
clk : in std_logic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
component generic_dpram_as
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
clk : in std_logic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
component rfbypass
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
clk : in clk_type;
write : in std_logic;
datain: in std_logic_vector (dbits -1 downto 0);
raddr1: in std_logic_vector (abits -1 downto 0);
raddr2: in std_logic_vector (abits -1 downto 0);
waddr : in std_logic_vector (abits -1 downto 0);
q1 : in std_logic_vector (dbits -1 downto 0);
q2 : in std_logic_vector (dbits -1 downto 0);
dataout1 : out std_logic_vector (dbits -1 downto 0);
dataout2 : out std_logic_vector (dbits -1 downto 0)
);
end component;
signal qq1, qq2 : std_logic_vector (dbits -1 downto 0);
begin
rfss : if rftype = 1 generate
u0 : generic_dpram_ss
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clkn, rdaddress => rfi.rd1addr, wraddress => rfi.wraddr,
data => rfi.wrdata, wren => rfi.wren, q => rfo.data1);
u1 : generic_dpram_ss
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clkn, rdaddress => rfi.rd2addr, wraddress => rfi.wraddr,
data => rfi.wrdata, wren => rfi.wren, q => rfo.data2);
end generate;
rfas : if rftype = 2 generate
u0 : generic_dpram_as
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clk, rdaddress => rfi.rd1addr, wraddress => rfi.wraddr,
data => rfi.wrdata, wren => rfi.wren, q => qq1);
u1 : generic_dpram_as
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clk, rdaddress => rfi.rd1addr, wraddress => rfi.wraddr,
data => rfi.wrdata, wren => rfi.wren, q => qq2);
wb : rfbypass generic map (abits, dbits)
port map ( clk => clk,
write => rfi.wren, datain => rfi.wrdata, raddr1 => rfi.rd1addr,
raddr2 => rfi.rd2addr, waddr => rfi.wraddr, q1 => qq1, q2 => qq2,
dataout1 => rfo.data1, dataout2 => rfo.data2);
end generate;
end;
-- co-processor regfile
-- synchronous operation without write-through support
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;
entity generic_regfile_cp is
generic (
abits : integer := 4; dbits : integer := 32; words : integer := 16
);
port (
rst : in std_logic;
clk : in std_logic;
rfi : in rf_cp_in_type;
rfo : out rf_cp_out_type);
end;
architecture rtl of generic_regfile_cp is
component generic_dpram_ss
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
clk : in std_logic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_logic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
begin
u0 : generic_dpram_ss
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clk, rdaddress => rfi.rd1addr, wraddress => rfi.wraddr,
data => rfi.wrdata, wren => rfi.wren, q => rfo.data1);
u1 : generic_dpram_ss
generic map (abits => abits, dbits => dbits, words => words)
port map (clk => clk, rdaddress => rfi.rd2addr, wraddress => rfi.wraddr,
data => rfi.wrdata, wren => rfi.wren, q => rfo.data2);
end;
------------------------------------------------------------------
-- multiplier ----------------------------------------------------
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity generic_smult is
generic ( abits : integer := 10; bbits : integer := 8 );
port (
a : in std_logic_vector(abits-1 downto 0);
b : in std_logic_vector(bbits-1 downto 0);
c : out std_logic_vector(abits+bbits-1 downto 0)
);
end;
architecture rtl of generic_smult is
begin
m: process(a, b)
variable w : std_logic_vector(abits+bbits-1 downto 0);
begin
-- pragma translate_off
if is_x(a) or is_x(b) then
w := (others => 'X');
else
-- pragma translate_on
w := std_logic_vector'(signed(a) * signed(b)); --'
-- pragma translate_off
end if;
-- pragma translate_on
c <= w;
end process;
end;
------------------------------------------------------------------
-- behavioural pad models --------------------------------------------
------------------------------------------------------------------
-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
entity geninpad is port (pad : in std_logic; q : out std_logic); end;
architecture rtl of geninpad is begin q <= to_x01(pad); end;
-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
entity gensmpad is port (pad : in std_logic; q : out std_logic); end;
architecture rtl of gensmpad is begin q <= to_x01(pad); end;
-- output pad
library IEEE;
use IEEE.std_logic_1164.all;
entity genoutpad is port (d : in std_logic; pad : out std_logic); end;
architecture rtl of genoutpad is begin pad <= to_x01(d); end;
-- tri-state outpad with pull-up pad
library IEEE;
use IEEE.std_logic_1164.all;
entity gentoutpadu is port (d, en : in std_logic; pad : out std_logic); end;
architecture rtl of gentoutpadu is
begin pad <= to_x01(d) when en = '0' else 'H'; end;
-- bidirectional pad
library IEEE;
use IEEE.std_logic_1164.all;
entity geniopad is
port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture rtl of geniopad is
begin pad <= to_x01(d) when en = '0' else 'Z'; q <= to_x01(pad); end;
-- bidirectional open-drain pad
library IEEE;
use IEEE.std_logic_1164.all;
entity geniodpad is
port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
end;
architecture rtl of geniodpad is
begin pad <= '0' when d = '0' else 'Z'; q <= to_x01(pad); end;
-- open-drain pad
library IEEE;
use IEEE.std_logic_1164.all;
entity genodpad is port ( d : in std_logic; pad : out std_logic); end;
architecture rtl of genodpad is begin pad <= '0' when d = '0' else 'Z'; end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/amba.vhd
|
2
|
14969
|
--============================================================================--
-- Design unit : AMBA (Package declaration)
--
-- File name : amba.vhd
--
-- Purpose : This package declares types to be used with the
-- Advanced Microcontroller Bus Architecture (AMBA).
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
--
-- The document can be retrieved from http://www.arm.com
--
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case n in the name indicates that the signal is
-- active low. A lower case x in the name suffix indicates that
-- the signal is unique to a module. Constant names are in upper
-- case.
--
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Library : AMBA_Lib {recommended}
--
-- Author : European Space Agency (ESA)
-- P.O. Box 299
-- NL-2200 AG Noordwijk ZH
-- The Netherlands
--
-- Contact : mailto:[email protected]
-- http://www.estec.esa.nl/microelectronics
--
-- Copyright (C): European Space Agency (ESA) 2000. This source code may be
-- redistributed provided that the source code and this notice
-- remain intact. This source code may not under any
-- circumstances be resold or redistributed for compensation
-- of any kind without prior written permission.
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit. This information does not
-- necessarily reflect the policy of the European Space Agency.
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.2 ESA 5 Jul 2000 Package created
-- 0.3 ESA 10 Jul 2000 Additional HREADY slave input,
-- Std_ULogic usage for non-array signals,
-- Additional comments on casing and addressing
-- 0.4 ESA 14 Jul 2000 HRESETn removed from AHB Slave input record
-- Additional comments on clocking and reset
-- Additional comments on AHB endianness
-- Additional comments on APB addressing
-- 0.5 ESA 18 Jul 2000 Re-defined vector types for AHB arbiter
-- and APB master
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
package AMBA is
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) Advanced High-performance Bus (AHB)
-----------------------------------------------------------------------------
-- Records are defined for the input and output of an AHB Master, as well as
-- for an AHB Slave. These records are grouped in arrays, for scalability,
-- and new records using these arrays are defined for the input and output of
-- an AHB Arbiter/Decoder.
--
-- The routing of the clock and reset signals defined in the AMBA(TM)
-- Specification is not covered in this package, since being dependent on
-- the clock and reset conventions defined at system level.
--
-- The HCLK and HRESETn signals are routed separately:
-- HCLK: Std_ULogic; -- rising edge
-- HRESETn: Std_ULogic; -- active low reset
--
-- The address bus HADDR contains byte addresses. The relation between the
-- byte address and the n-byte data bus HDATA can either be little-endian or
-- big-endian according to the AMBA(TM) Specification.
--
-- It is recommended that only big-endian modules are implemented using
-- this package.
--
-----------------------------------------------------------------------------
-- Constant definitions for AMBA(TM) AHB
-----------------------------------------------------------------------------
constant HDMAX: Positive range 32 to 1024 := 32; -- data width
constant HAMAX: Positive range 32 to 32 := 32; -- address width
-- constant HMMAX: Positive range 1 to 16 := 16; -- number of masters
-- constant HSMAX: Positive := 16; -- number of slaves
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) AHB Masters
-----------------------------------------------------------------------------
-- AHB master inputs (HCLK and HRESETn routed separately)
type AHB_Mst_In_Type is
record
HGRANT: Std_ULogic; -- bus grant
HREADY: Std_ULogic; -- transfer done
HRESP: Std_Logic_Vector(1 downto 0); -- response type
HRDATA: Std_Logic_Vector(HDMAX-1 downto 0); -- read data bus
HCACHE: Std_ULogic; -- cacheable data
end record;
-- AHB master outputs
type AHB_Mst_Out_Type is
record
HBUSREQ: Std_ULogic; -- bus request
HLOCK: Std_ULogic; -- lock request
HTRANS: Std_Logic_Vector(1 downto 0); -- transfer type
HADDR: Std_Logic_Vector(HAMAX-1 downto 0); -- address bus (byte)
HWRITE: Std_ULogic; -- read/write
HSIZE: Std_Logic_Vector(2 downto 0); -- transfer size
HBURST: Std_Logic_Vector(2 downto 0); -- burst type
HPROT: Std_Logic_Vector(3 downto 0); -- protection control
HWDATA: Std_Logic_Vector(HDMAX-1 downto 0); -- write data bus
end record;
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) AHB Slaves
-----------------------------------------------------------------------------
-- AHB slave inputs (HCLK and HRESETn routed separately)
type AHB_Slv_In_Type is
record
HSEL: Std_ULogic; -- slave select
HADDR: Std_Logic_Vector(HAMAX-1 downto 0); -- address bus (byte)
HWRITE: Std_ULogic; -- read/write
HTRANS: Std_Logic_Vector(1 downto 0); -- transfer type
HSIZE: Std_Logic_Vector(2 downto 0); -- transfer size
HBURST: Std_Logic_Vector(2 downto 0); -- burst type
HWDATA: Std_Logic_Vector(HDMAX-1 downto 0); -- write data bus
HPROT: Std_Logic_Vector(3 downto 0); -- protection control
HREADY: Std_ULogic; -- transfer done
HMASTER: Std_Logic_Vector(3 downto 0); -- current master
HMASTLOCK: Std_ULogic; -- locked access
end record;
-- AHB slave outputs
type AHB_Slv_Out_Type is
record
HREADY: Std_ULogic; -- transfer done
HRESP: Std_Logic_Vector(1 downto 0); -- response type
HRDATA: Std_Logic_Vector(HDMAX-1 downto 0); -- read data bus
HSPLIT: Std_Logic_Vector(15 downto 0); -- split completion
end record;
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) AHB Arbiter/Decoder
-----------------------------------------------------------------------------
-- supporting array types
type AHB_Mst_In_Vector is array (Natural Range <> ) of AHB_Mst_In_Type;
type AHB_Mst_Out_Vector is array (Natural Range <> ) of AHB_Mst_Out_Type;
type AHB_Slv_In_Vector is array (Natural Range <> ) of AHB_Slv_In_Type;
type AHB_Slv_Out_Vector is array (Natural Range <> ) of AHB_Slv_Out_Type;
-- An AHB arbiter could be defined as follows:
-- entity AHBarbiter is
-- generic (
-- masters : integer := 2; -- number of masters
-- slaves : integer := 2; -- number of slaves
-- );
-- port (
-- clk : in std_ulogic;
-- rst : in std_ulogic;
-- msti : out ahb_mst_in_vector(0 to masters-1);
-- msto : in ahb_mst_out_vector(0 to masters-1);
-- slvi : out ahb_slv_in_vector(0 to slaves-1);
-- slvo : in ahb_slv_out_vector(0 to slaves-1)
-- );
-- end;
-----------------------------------------------------------------------------
-- Auxiliary constant definitions for AMBA(TM) AHB
-----------------------------------------------------------------------------
-- constants for HTRANS (transition type, slave output)
constant HTRANS_IDLE: Std_Logic_Vector(1 downto 0) := "00";
constant HTRANS_BUSY: Std_Logic_Vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: Std_Logic_Vector(1 downto 0) := "10";
constant HTRANS_SEQ: Std_Logic_Vector(1 downto 0) := "11";
-- constants for HBURST (burst type, master output)
constant HBURST_SINGLE: Std_Logic_Vector(2 downto 0) := "000";
constant HBURST_INCR: Std_Logic_Vector(2 downto 0) := "001";
constant HBURST_WRAP4: Std_Logic_Vector(2 downto 0) := "010";
constant HBURST_INCR4: Std_Logic_Vector(2 downto 0) := "011";
constant HBURST_WRAP8: Std_Logic_Vector(2 downto 0) := "100";
constant HBURST_INCR8: Std_Logic_Vector(2 downto 0) := "101";
constant HBURST_WRAP16: Std_Logic_Vector(2 downto 0) := "110";
constant HBURST_INCR16: Std_Logic_Vector(2 downto 0) := "111";
-- constants for HSIZE (transfer size, master output)
constant HSIZE_BYTE: Std_Logic_Vector(2 downto 0) := "000";
constant HSIZE_HWORD: Std_Logic_Vector(2 downto 0) := "001";
constant HSIZE_WORD: Std_Logic_Vector(2 downto 0) := "010";
constant HSIZE_DWORD: Std_Logic_Vector(2 downto 0) := "011";
constant HSIZE_4WORD: Std_Logic_Vector(2 downto 0) := "100";
constant HSIZE_8WORD: Std_Logic_Vector(2 downto 0) := "101";
constant HSIZE_16WORD: Std_Logic_Vector(2 downto 0) := "110";
constant HSIZE_32WORD: Std_Logic_Vector(2 downto 0) := "111";
-- constants for HRESP (response, slave output)
constant HRESP_OKAY: Std_Logic_Vector(1 downto 0) := "00";
constant HRESP_ERROR: Std_Logic_Vector(1 downto 0) := "01";
constant HRESP_RETRY: Std_Logic_Vector(1 downto 0) := "10";
constant HRESP_SPLIT: Std_Logic_Vector(1 downto 0) := "11";
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) Advanced Peripheral Bus (APB)
-----------------------------------------------------------------------------
-- Records are defined for the input and output of an APB Slave. These
-- records are grouped in arrays, for scalability, and new records using
-- these arrays are defined for the input and output of an APB Bridge.
--
-- The routing of the clock and reset signals defined in the AMBA(TM)
-- Specification is not covered in this package, since being dependent on
-- the clock and reset conventions defined at system level.
--
-- The PCLK and PRESETn signals are routed separately:
-- PCLK: Std_ULogic; -- rising edge
-- PRESETn: Std_ULogic; -- active low reset
--
-- The characteristics of the address bus PADDR are undefined in the
-- AMBA(TM) Specification.
--
-- When implementing modules with this package, it is recommended that the
-- information on the address bus PADDR is interpreted as byte addresses, but
-- it should only be used for 32-bit word addressing, i.e. the value of
-- address bits 0 and 1 should always be logical 0. For modules not
-- supporting full 32-bit words on the data bus PDATA, e.g. only supporting
-- 16-bit halfwords or 8-bit bytes, the addressing will still be word based.
-- Consequently, one halfword or byte will be accessed for each word address.
-- Modules only supporting byte sized data should exchange data on bit 7 to 0
-- on the PDATA data bus. Modules only supporting halfword sized data should
-- exchange data on bit 15 to 0 on the PDATA data bus. Modules supporting
-- word sized data should exchange data on bit 31 to 0 on the PDATA data bus.
--
-----------------------------------------------------------------------------
-- Constant definitions for AMBA(TM) APB
-----------------------------------------------------------------------------
constant PDMAX: Positive range 8 to 32 := 32; -- data width
constant PAMAX: Positive range 8 to 32 := 32; -- address width
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) APB Slaves
-----------------------------------------------------------------------------
-- APB slave inputs (PCLK and PRESETn routed separately)
type APB_Slv_In_Type is
record
PSEL: Std_ULogic; -- slave select
PENABLE: Std_ULogic; -- strobe
PADDR: Std_Logic_Vector(PAMAX-1 downto 0); -- address bus (byte)
PWRITE: Std_ULogic; -- write
PWDATA: Std_Logic_Vector(PDMAX-1 downto 0); -- write data bus
end record;
-- APB slave outputs
type APB_Slv_Out_Type is
record
PRDATA: Std_Logic_Vector(PDMAX-1 downto 0); -- read data bus
end record;
-----------------------------------------------------------------------------
-- Definitions for AMBA(TM) APB Bridge
-----------------------------------------------------------------------------
-- supporting array types
type APB_Slv_In_Vector is array (Natural Range <> ) of APB_Slv_In_Type;
type APB_Slv_Out_Vector is array (Natural Range <> ) of APB_Slv_Out_Type;
-- An AHB/APB bridge could be defined as follows:
-- entity apbmst is
-- generic (slaves : natural := 32);
-- port (
-- clk : in std_ulogic;
-- rst : in std_ulogic;
-- ahbi : in ahb_slv_in_type;
-- ahbo : out ahb_slv_out_type;
-- apbi : in apb_slv_out_vector(0 to slaves-1);
-- apbo : out apb_slv_in_vector(0 to slaves-1)
-- );
-- end;
end AMBA; --==================================================================--
|
gpl-3.0
|
freecores/layer2
|
vhdl/rs232/rtl/uartt.vhd
|
1
|
5305
|
--------------------------------------------------------------------------------
-- UART Transmitter 19200/8N1 --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iwb.all;
use work.iuart.all;
entity uartt is
port(
si : in slave_in_t;
so : out slave_out_t;
-- Non-Wishbone Signals
RS232_DCE_TXD : out std_logic
);
end uartt;
architecture rtl of uartt is
type state_t is (Idle, Start, Data, Stop, Ack);
type sender_t is record
s : state_t; -- Sender state.
n : natural range 0 to 15; -- Tick counter.
m : natural range 0 to 7; -- Data bits counter.
d : std_logic_vector(7 downto 0); -- Data bits shift register.
end record;
type tx_t is record
tick : std_logic;
rst : std_logic;
ack : std_logic;
end record;
signal snd, sndin : sender_t;
signal tx : tx_t;
begin
-----------------------------------------------------------------------------
-- Transmitter Rate Generator --
-----------------------------------------------------------------------------
tx_rate : counter
generic map(
FREQ => 50,
RATE => 19200
)
port map(
clk => si.clk,
rst => tx.rst,
tick => tx.tick
);
-----------------------------------------------------------------------------
-- Transmitter Controller --
-----------------------------------------------------------------------------
receiver : process(snd, tx.tick, si)
begin
sndin <= snd;
tx.rst <= '0';
tx.ack <= '0';
RS232_DCE_TXD <= '1'; -- Idle line is alwasys '1'.
case snd.s is
when Idle =>
tx.rst <= '1';
if wb_write(si) then
sndin.n <= 0;
sndin.d <= si.dat(7 downto 0);
sndin.s <= Start;
end if;
when Start =>
RS232_DCE_TXD <= '0';
if tx.tick = '1' then
if snd.n = 15 then
sndin.n <= 0;
sndin.m <= 0;
sndin.s <= Data;
else
sndin.n <= snd.n + 1;
end if;
end if;
when Data =>
RS232_DCE_TXD <= snd.d(0);
if tx.tick = '1' then
if snd.n = 15 then
sndin.n <= 0;
sndin.d <= '0' & snd.d(7 downto 1);
if snd.m = 7 then
sndin.s <= Stop;
else
sndin.m <= snd.m + 1;
end if;
else
sndin.n <= snd.n + 1;
end if;
end if;
when Stop =>
if tx.tick = '1' then
if snd.n = 15 then
sndin.s <= Ack;
else
sndin.n <= snd.n + 1;
end if;
end if;
when Ack =>
tx.ack <= '1';
if si.stb = '0' then
sndin.s <= Idle;
end if;
end case;
end process;
so.dat <= (others => '-');
so.ack <= tx.ack;
-----------------------------------------------------------------------------
-- Registers --
-----------------------------------------------------------------------------
reg : process(si.clk)
begin
if rising_edge(si.clk) then
snd <= sndin;
if si.rst = '1' then
snd.s <= Idle;
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/mctrl.vhd
|
2
|
23333
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned.conv_integer;
use IEEE.std_logic_arith.conv_unsigned;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.sparcv8.all;
use work.macro.all;
use work.tech_map.all;
use work.amba.all;
entity mctrl is
port (
rst : in rst_type;
clk : in clk_type;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
pioo : in pio_out_type;
wpo : in wprot_out_type;
mctrlo : out mctrl_out_type
);
end;
architecture rtl of mctrl is
type areatype is (rom, io, ram);
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
extlatch : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
wren : std_logic;
bdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(3 downto 0);
ramoen : std_logic_vector(3 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
psel : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : areatype;
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
rmw : std_logic;
brmw : std_logic;
hsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
end record;
signal r, ri : reg_type;
signal wrnout : std_logic_vector(3 downto 0);
signal promdata : std_logic_vector(31 downto 0); -- data from boot-prom
begin
ctrl : process(rst, ahbsi, apbi, memi, r, pioo, promdata, wpo
)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(3 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : areatype;
variable bdrive, ramsn : std_logic_vector(3 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bpsel : std_logic;
variable psel : std_logic;
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.wren := '0'; v.echeck := '0'; bpsel := '0';
v.rmw := '0'; merrtype := "---"; bready := '1';
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((not r.brdyn) or not r.mcfg1.brdyen) = '1') or (r.area /= io) then
bready := '1';
else bready := '0'; end if;
v.hresp := HRESP_OKAY;
-- decode memory area parameters
case ahbsi.haddr(30 downto 28) is
when "000" | "001" => area := rom;
when "010" | "011" => area := io;
when others => area := ram;
end case;
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
case area is
when rom =>
busw := r.mcfg1.romwidth;
when ram =>
adec := genmux(r.mcfg2.rambanksz, ahbsi.haddr(29 downto 14)) &
genmux(r.mcfg2.rambanksz, ahbsi.haddr(28 downto 13));
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and ahbsi.hwrite) = '1') and
((BUS16EN and (busw = "01") and (ahbsi.hsize(1 downto 0) = "00")) or
((busw(1) = '1') and (ahbsi.hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
when io =>
leadin := '1';
busw := r.mcfg1.iowidth;
when others =>
end case;
-- decode waitstates and illegal access
case r.area is
when rom =>
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
when ram =>
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
when io =>
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
when others => null;
end case;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := decode(adec);
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
psel := '1'; v.psel(1) := r.psel(0);
case area is
when rom =>
if ((BOOTOPT = memory) or ((BOOTOPT = dual) and (pioo.io8lsb(4) = '0'))) then
romsn(0) := ahbsi.haddr(28);
else psel := ahbsi.haddr(28); end if;
romsn(1) := not ahbsi.haddr(28);
when ram => ramsn := not rams;
when io => iosn := '0';
when others => null;
end case;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area = ram) then wrn := not bdrive; end if;
if ((ahbsi.hready and ahbsi.hsel) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.area := area;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
v.address := ahbsi.haddr; v.psel(0) := psel;
if (busw = "00") and (ahbsi.hwrite = '0') and (area /= io) and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (ahbsi.hwrite = '0') and (area /= io) and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not ahbsi.hwrite; end if;
v.hwrite := ahbsi.hwrite;
v.busw := busw; v.brmw := brmw;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbsi.hwdata;
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '0' then
if r.busw(1) = '1' then v.writedata := writedata;
else
v.writedata(31 downto 16) := writedata(31 downto 16);
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if r.hsel = '1' then
wprothitx := wpo.wprothit and not r.read;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr;
elsif r.read = '0' then
if (r.busw = "00") and (r.area /= io) and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area /= io) and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area /= io) and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area /= io) and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; v.hsel := '0'; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.psel(0) := '1';
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or (r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.hsel := '0'; v.psel(0) := '1';
else v.echeck := '1'; end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '0'); v.bstate := idle; v.hsel := '0';
v.psel(0) := '1';
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.hsel := '0';
v.psel(0) := '1';
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '0'); v.bstate := idle; v.hsel := '0';
v.psel(0) := '1';
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
-- v.writedata(31 downto 8) := r.writedata(23 downto 0);
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.hsel := '0';
v.psel(0) := '1';
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '0'); v.bstate := idle; v.hsel := '0';
v.psel(0) := '1';
end if;
if (r.ws = "0000") and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '0'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel;
v.psel(0) := '1';
elsif ahbsi.hsel = '1' then
v.romsn := romsn; v.ramsn := ramsn; v.iosn := iosn & '1'; v.hsel := '1';
v.psel(0) := psel;
if v.read = '1' then v.ramoen := ramsn; v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR;
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
r.mcfg1.extlatch &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
regsd(12 downto 0) := r.mcfg2.rambanksz & "00" & r.mcfg2.rmw &
r.mcfg2.ramwidth & r.mcfg2.ramwws & r.mcfg2.ramrws;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.extlatch := apbi.pwdata(18);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
when others => null;
end case;
end if;
-- select appropriate data during reads
case r.area is
when rom | ram =>
dataout := memdata;
if (r.area = rom) and (BOOTOPT /= memory) then
if (r.psel(0) = '0') then v.readdata := promdata; end if;
if r.psel(1) = '0' then dataout := r.readdata; end if;
end if;
when others =>
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end case;
v.ready := ready;
-- generate memory address
if RAWADDR and (r.mcfg1.extlatch = '1') then
memo.address <= v.address(27 downto 0);
else
memo.address <= r.address(27 downto 0);
end if;
-- use d(15:0) as I/O ports (only usefull in 8/16-bit mode)
if BUS8EN or BUS16EN then
mctrlo.pioh <= r.data(15 downto 0);
if (r.mcfg1.romwidth(1) or r.mcfg1.iowidth(1) or r.mcfg2.ramwidth(1)) = '0' then
v.writedata(15 downto 0) := r.writedata(15 downto 0);
if pioo.wrio = '1' then
v.writedata(15 downto 0) := pioo.piol(31 downto 16);
end if;
v.wrn(3 downto 2) := "11";
v.bdrive(3 downto 2) := not pioo.piodir(17 downto 16);
end if;
else mctrlo.pioh <= (others => '0'); end if;
-- reset
if rst.syncrst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.extlatch := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
if ((BOOTOPT = memory) or ((BOOTOPT = dual) and (pioo.io8lsb(4) = '0')))
then
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := pioo.io8lsb(1 downto 0);
else
v.mcfg2.ramrws := std_logic_vector(BRAMRWS(1 downto 0));
v.mcfg2.ramwws := std_logic_vector(BRAMWWS(1 downto 0));
v.mcfg1.romrws := "0001";
v.mcfg1.romwws := "0001";
v.mcfg1.romwidth := "11";
end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
-- drive various register inputs and external outputs
ri <= v;
memo.ramsn <= r.ramsn;
memo.ramoen <= r.ramoen;
memo.romsn <= r.romsn;
memo.oen <= r.oen;
memo.iosn <= r.iosn(0);
memo.read <= r.read;
memo.wrn <= r.wrn;
memo.writen <= r.writen;
memo.bdrive <= (not r.bdrive) and memi.wrn;
memo.data <= r.writedata;
ahbso.hrdata <= dataout;
ahbso.hready <= r.ready and noerror;
ahbso.hresp <= r.hresp;
ahbso.hsplit <= (others => '0');
end process;
stdregs : process(clk,rst)
begin
if rising_edge(clk) then r <= ri; end if;
if rst.rawrst = '0' then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.bdrive <= (others => '0');
r.iosn <= "11"; r.ramoen <= (others => '1');
end if;
end process;
-- optional boot-prom
promgen : if (BOOTOPT /= memory) generate
bprom0 : bprom port map
(clk => clk, cs => r.psel(0), addr => r.address, data => promdata);
end generate;
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/dsu.vhd
|
1
|
18774
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Debug support unit.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
use work.tech_map.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
entity dsu is
generic (cfgindex : integer := def_cfgindex);
port (
rst : in std_logic;
clk : in clk_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
dbgi : in iu_debug_out_type;
dbgo : out iu_debug_in_type;
irqo : in irq_out_type;
dmi : out dsumem_in_type;
dmo : in dsumem_out_type
);
end;
architecture rtl of dsu is
-- constant dsuconfig : debug_config_type := leon_config_table(cfgindex).debug;
constant TTIMEBITS : integer := 30; -- timer bits
type dsu_config_reg is record
tenable : std_logic; -- trace enable
tmode : std_logic; -- trace delay counter mode
btrapa : std_logic; -- break on any IU trap
btrape : std_logic; -- break on all IU traps but 3,4,5,6,0x11-0x1f
berror : std_logic; -- break on IU error mode
bwatch : std_logic; -- break on IU watchpoint
bsoft : std_logic; -- break on software breakpoint (TA 1)
bahb : std_logic; -- break on AHB watchpoint hit
btrace : std_logic; -- break on trace freeze
ftimer : std_logic; -- freeze timer on break
rerror : std_logic; -- reset error mode
step : std_logic; -- single step
lresp : std_logic; -- link response enable
dresp : std_logic; -- debug response enable
dbreak : std_logic; -- force CPU in debug mode (write-only)
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
end record;
type trace_ctrl_reg is record
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
pindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
tproc : std_logic; -- trace processor enable
tahb : std_logic; -- trace AHB enable
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
exec : std_logic;
end record;
type regtype is record
-- AHB signals
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
hresp : std_logic_vector(1 downto 0);
hsel : std_logic;
hready : std_logic;
hready2 : std_logic;
hready3 : std_logic;
ahbactive : std_logic;
timer : std_logic_vector(TTIMEBITS - 1 downto 0); -- timer
dsubre : std_logic_vector(2 downto 0); -- external DSUBRE signal
dsuen : std_logic_vector(2 downto 0); -- external DSUBRE signal
dsuact : std_logic;
dsucfg : dsu_config_reg;
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
tctrl : trace_ctrl_reg;
end record;
signal r, rin : regtype;
constant zero30 : std_logic_vector(29 downto 0) := (others => '0');
begin
ctrl : process(rst, ahbmi, ahbsi, dsui, irqo, dbgi, r, dmo)
variable v : regtype;
variable vpbufi, vabufi : tracebuf_in_type;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable pindex, aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable denable, ldst_cycle, bphit, bphit2 : std_logic;
variable bufdata : std_logic_vector(127 downto 0);
variable pbufo, abufo : tracebuf_out_type;
begin
v := r; regsd := (others => '0'); vpbufi.enable := '0'; vabufi.enable := '0';
vpbufi.data := (others => '0'); vabufi.data := (others => '0');
vpbufi.addr := (others => '0'); vabufi.addr := (others => '0');
vpbufi.write := (others => '0'); vabufi.write := (others => '0');
denable := '0'; bphit := '0'; bphit2 := '0';
v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
pbufo := dmo.pbufo; abufo := dmo.abufo;
bufdata := pbufo.data;
ldst_cycle := dbgi.wr.inst(31) and dbgi.wr.inst(30);
v.dsubre := r.dsubre(1 downto 0) & dsui.dsubre;
v.dsuen := r.dsuen(1 downto 0) & dsui.dsuen;
v.dsucfg.dbreak := r.dsucfg.dbreak or
(r.dsubre(1) and not r.dsubre(2)) or dbgi.dmode;
v.dsuact := dbgi.dmode; v.dsucfg.rerror := '0';
-- trace buffer index and delay counters
if DSUTRACE then
-- pragma translate_off
if not is_x(r.timer) then
-- pragma translate_on
if (r.dsucfg.tenable and not dbgi.dmode2) = '1' then
v.timer := r.timer + 1;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
-- pragma translate_off
if not is_x(r.tctrl.pindex) then
-- pragma translate_on
pindex := r.tctrl.pindex + 1;
-- pragma translate_off
end if;
-- pragma translate_on
if DSUMIXED then
-- pragma translate_off
if not is_x(r.tctrl.aindex) then
-- pragma translate_on
aindex := r.tctrl.aindex + 1;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
end if;
-- check for AHB watchpoints
if (ahbsi.hready and r.ahbactive ) = '1' then
if ((((r.tbreg1.addr xor r.haddr(31 downto 2)) and r.tbreg1.mask) = zero30) and
(((r.tbreg1.read and not r.hwrite) or (r.tbreg1.write and r.hwrite)) = '1'))
or ((((r.tbreg2.addr xor r.haddr(31 downto 2)) and r.tbreg2.mask) = zero30) and
(((r.tbreg2.read and not r.hwrite) or (r.tbreg2.write and r.hwrite)) = '1'))
then
bphit := '1';
if (r.dsucfg.dcnten = '0') and ((r.tctrl.tahb or r.tctrl.tproc) = '1') and
(r.dsucfg.delaycnt /= zero30(TBUFABITS-1 downto 0))
then v.dsucfg.dcnten := '1'; end if;
if r.dsucfg.bahb = '1' then v.dsucfg.dbreak := '1'; end if;
end if;
end if;
-- check for IU trace breakpoints
if (dbgi.holdn and dbgi.wr.pv and
not dbgi.wr.annul) = '1'
then
if ((((r.tbreg1.addr xor dbgi.wr.pc(31 downto 2)) and r.tbreg1.mask) = zero30) and
(r.tbreg1.exec = '1'))
or ((((r.tbreg2.addr xor dbgi.wr.pc(31 downto 2)) and r.tbreg2.mask) = zero30) and
(r.tbreg2.exec = '1'))
then
bphit2 := '1';
if (r.dsucfg.tenable = '1') and (r.dsucfg.dcnten = '0') and
(r.dsucfg.delaycnt /= zero30(TBUFABITS-1 downto 0))
then v.dsucfg.dcnten := '1'; end if;
if r.dsucfg.bahb = '1' then v.dsucfg.dbreak := '1'; end if;
end if;
end if;
-- generate buffer inputs
if DSUTRACE then
vpbufi.write := "0000"; vabufi.write := "0000";
if r.dsucfg.tenable = '1' then
vpbufi.addr := '0' & r.tctrl.pindex;
vabufi.addr := '0' & r.tctrl.aindex;
vabufi.data(125 downto 96) := r.timer;
vpbufi.data(125 downto 96) := r.timer;
vabufi.data(127) := bphit;
vabufi.data(95 downto 92) := irqo.irl;
vabufi.data(91 downto 88) := dbgi.psrpil;
vabufi.data(87 downto 80) := dbgi.psrtt;
vabufi.data(79) := r.hwrite;
vabufi.data(78 downto 77) := r.htrans;
vabufi.data(76 downto 74) := r.hsize;
vabufi.data(73 downto 71) := r.hburst;
vabufi.data(70 downto 67) := r.hmaster;
vabufi.data(66) := r.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if r.hwrite = '1' then
vabufi.data(63 downto 32) := ahbsi.hwdata;
else
vabufi.data(63 downto 32) := ahbmi.hrdata;
end if;
vabufi.data(31 downto 0) := r.haddr;
vpbufi.data(127) := bphit2;
vpbufi.data(126) := not dbgi.wr.pv;
vpbufi.data(95 downto 64) := dbgi.result;
vpbufi.data(63 downto 32) := dbgi.wr.pc(31 downto 2) &
dbgi.trap & dbgi.error;
vpbufi.data(31 downto 0) := dbgi.wr.inst;
else
vpbufi.addr := '0' & r.haddr(TBUFABITS+3 downto 4);
vabufi.addr := '1' & r.haddr(TBUFABITS+3 downto 4);
vpbufi.data := ahbsi.hwdata & ahbsi.hwdata & ahbsi.hwdata & ahbsi.hwdata;
vabufi.data := vpbufi.data;
end if;
-- write trace buffer
if r.dsucfg.tenable = '1' then
if (r.tctrl.tahb and r.ahbactive and ahbsi.hready) = '1' then
if DSUMIXED then
v.tctrl.aindex := aindex;
vabufi.enable := '1'; vabufi.write := "1111";
elsif (r.tctrl.tproc = '0') then
v.tctrl.pindex := pindex;
vpbufi.enable := '1'; vpbufi.write := "1111";
end if;
end if;
if (r.tctrl.tproc and dbgi.holdn and
(dbgi.wr.pv or dbgi.write_reg or ldst_cycle)
and (not dbgi.vdmode) and not dbgi.wr.annul) = '1'
then
vpbufi.enable := '1'; vpbufi.write := "1111";
v.tctrl.pindex := pindex;
end if;
if ((r.tctrl.tahb xor r.tctrl.tproc) = '1') and
DSUMIXED and not DSUDPRAM
then
if r.tctrl.tahb = '1' then vpbufi := vabufi;
else vabufi := vpbufi; end if;
vabufi.enable := vabufi.enable and vabufi.addr(TBUFABITS-1);
vpbufi.enable := vpbufi.enable and not vpbufi.addr(TBUFABITS-1);
end if;
if ((r.tctrl.tahb and not r.tctrl.tproc) = '1') and not DSUMIXED then
vpbufi.data := vabufi.data;
end if;
end if;
end if;
-- trace buffer delay counter handling
if (r.dsucfg.dcnten = '1') then
if (r.dsucfg.delaycnt = zero30(TBUFABITS-1 downto 0)) then
v.dsucfg.tenable := '0'; v.dsucfg.dcnten := '0';
v.dsucfg.dbreak := v.dsucfg.dbreak or r.dsucfg.btrace;
end if;
-- pragma translate_off
if not is_x(r.dsucfg.delaycnt) then
-- pragma translate_on
if ((vpbufi.enable and not r.dsucfg.tmode) or
(vabufi.enable and r.dsucfg.tmode)) = '1'
then
v.dsucfg.delaycnt := r.dsucfg.delaycnt - 1;
end if;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
-- save AHB transfer parameters
if (ahbsi.hready = '1' ) and ((ahbsi.hsel = '1') or
(DSUTRACE and ((r.tctrl.tahb and r.dsucfg.tenable) = '1')))
then
v.haddr := ahbsi.haddr; v.hwrite := ahbsi.hwrite; v.htrans := ahbsi.htrans;
v.hsize := ahbsi.hsize; v.hburst := ahbsi.hburst;
v.hmaster := ahbsi.hmaster; v.hmastlock := ahbsi.hmastlock;
end if;
if r.hsel = '1' then v.hwdata := ahbsi.hwdata; end if;
if ahbsi.hready = '1' then
v.hresp := ahbmi.hresp; v.hsel := ahbsi.hsel;
v.ahbactive := ahbsi.htrans(1);
end if;
-- AHB slave access to DSU registers and trace buffers
if (r.hsel and not r.hready) = '1' then
case r.haddr(20 downto 16) is
when "00000" => -- DSU control register access
v.hready := '1';
case r.haddr(4 downto 2) is
when "000" =>
regsd((TBUFABITS + 19) downto 20) := r.dsucfg.delaycnt;
regsd(18 downto 1) :=
r.dsucfg.dresp & r.dsucfg.lresp &
r.dsucfg.step & dbgi.error &
r.dsuen(2) & r.dsubre(2) & r.dsuact &
r.dsucfg.dcnten & r.dsucfg.btrape & r.dsucfg.btrapa &
r.dsucfg.bahb & r.dsucfg.dbreak & r.dsucfg.bsoft &
r.dsucfg.bwatch & r.dsucfg.berror & r.dsucfg.ftimer &
r.dsucfg.btrace & r.dsucfg.tmode;
if DSUTRACE then regsd(0) := r.dsucfg.tenable;
end if;
if r.hwrite = '1' then
v.dsucfg.delaycnt := ahbsi.hwdata((TBUFABITS+ 19) downto 20);
v.dsucfg.rerror := ahbsi.hwdata(19);
v.dsucfg.dresp := ahbsi.hwdata(18);
v.dsucfg.lresp := ahbsi.hwdata(17);
v.dsucfg.step := ahbsi.hwdata(16);
v.dsucfg.dcnten := ahbsi.hwdata(11);
v.dsucfg.btrape := ahbsi.hwdata(10);
v.dsucfg.btrapa := ahbsi.hwdata(9);
v.dsucfg.bahb := ahbsi.hwdata(8);
v.dsucfg.dbreak := ahbsi.hwdata(7);
v.dsucfg.bsoft := ahbsi.hwdata(6);
v.dsucfg.bwatch := ahbsi.hwdata(5);
v.dsucfg.berror := ahbsi.hwdata(4);
v.dsucfg.ftimer := ahbsi.hwdata(3);
v.dsucfg.btrace := ahbsi.hwdata(2);
v.dsucfg.tmode := ahbsi.hwdata(1);
if DSUTRACE then
v.dsucfg.tenable := ahbsi.hwdata(0);
end if;
end if;
when "001" =>
if DSUTRACE then
regsd((TBUFABITS - 1) downto 0) := r.tctrl.pindex;
if DSUMIXED then
regsd((TBUFABITS - 1 + 12) downto 12) := r.tctrl.aindex;
end if;
regsd(24) := r.tctrl.tproc; regsd(25) := r.tctrl.tahb;
if r.hwrite = '1' then
v.tctrl.pindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
if DSUMIXED then
v.tctrl.aindex := ahbsi.hwdata((TBUFABITS- 1 + 12) downto 12);
end if;
v.tctrl.tproc := ahbsi.hwdata(24);
v.tctrl.tahb := ahbsi.hwdata(25);
end if;
end if;
when "010" =>
if DSUTRACE then
regsd((TTIMEBITS - 1) downto 0) := r.timer;
if r.hwrite = '1' then
v.timer := ahbsi.hwdata((TTIMEBITS- 1) downto 0);
end if;
end if;
when "100" =>
regsd(31 downto 2) := r.tbreg1.addr;
if r.hwrite = '1' then
v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
v.tbreg1.exec := ahbsi.hwdata(0);
end if;
when "101" =>
regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
if r.hwrite = '1' then
v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
v.tbreg1.read := ahbsi.hwdata(1);
v.tbreg1.write := ahbsi.hwdata(0);
end if;
when "110" =>
regsd(31 downto 2) := r.tbreg2.addr;
if r.hwrite = '1' then
v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
v.tbreg2.exec := ahbsi.hwdata(0);
end if;
when others =>
regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
if r.hwrite = '1' then
v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
v.tbreg2.read := ahbsi.hwdata(1);
v.tbreg2.write := ahbsi.hwdata(0);
end if;
end case;
v.hwdata := regsd;
when "00001" => -- read/write access to trace buffer
if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
if DSUTRACE then
if DSUMIXED and not DSUDPRAM then
vabufi.enable := (not r.dsucfg.tenable) and r.haddr(TBUFABITS+3);
vpbufi.enable := (not r.dsucfg.tenable) and not r.haddr(TBUFABITS+3);
if r.haddr(TBUFABITS+3) = '1' then bufdata := abufo.data;
else bufdata := pbufo.data; end if;
else
vpbufi.enable := not r.dsucfg.tenable;
if not DSUMIXED then vabufi.enable := vpbufi.enable; end if;
end if;
case r.haddr(3 downto 2) is
when "00" =>
v.hwdata := bufdata(127 downto 96);
if r.hwrite = '1' then
vpbufi.write(3) := vpbufi.enable;
vabufi.write(3) := vabufi.enable;
end if;
when "01" =>
v.hwdata := bufdata(95 downto 64);
if r.hwrite = '1' then
vpbufi.write(2) := vpbufi.enable;
vabufi.write(2) := vabufi.enable;
end if;
when "10" =>
v.hwdata := bufdata(63 downto 32);
if r.hwrite = '1' then
vpbufi.write(1) := vpbufi.enable;
vabufi.write(1) := vabufi.enable;
end if;
when others =>
v.hwdata := bufdata(31 downto 0);
if r.hwrite = '1' then
vpbufi.write(0) := vpbufi.enable;
vabufi.write(0) := vabufi.enable;
end if;
end case;
end if;
when others => -- IU/cache diagnostic access
if r.hwrite = '0' then v.hwdata := dbgi.ddata(31 downto 0); end if;
if r.haddr(20) = '0' then -- IU registers
v.hready3 := not (r.hready2 or r.hready3);
denable := r.hready2 or r.hready3;
else
denable := '1';
if r.haddr(19) = '0' then -- icache
if r.hwrite = '0' then v.hready := dbgi.diagrdy and not r.hready;
else v.hready2 := not (r.hready2 or r.hready); end if;
else -- dcache
if r.hwrite = '1' then v.hready2 := not (r.hready2 or r.hready);
else
v.hready2 := not r.hready2; v.hready3 := r.hready2 or r.hready3;
v.hready := r.hready2 and r.hready3;
if v.hready = '1' then v.hready2 := '0'; v.hready3 := '0'; end if;
end if;
end if;
end if;
end case;
end if;
if DSUMIXED then
if ((r.tctrl.tahb and r.tctrl.tproc and r.dsucfg.tenable) = '1') then
v.tctrl.aindex(TBUFABITS-1) := '1'; v.tctrl.pindex(TBUFABITS-1) := '0';
end if;
else vabufi := vpbufi; end if;
vpbufi.addr(TBUFABITS) := '0'; vabufi.addr(TBUFABITS) := '1';
dsuo.freezetime <= r.dsucfg.ftimer and dbgi.dmode2;
dsuo.ntrace <= r.dsucfg.tenable and not v.dsucfg.tenable;
dsuo.dsuact <= r.dsuact;
dsuo.dsuen <= r.dsuen(2);
dsuo.dsubre <= r.dsubre(2);
dsuo.lresp <= r.dsucfg.lresp;
dsuo.dresp <= r.dsucfg.dresp;
if rst = '0' then
v.ahbactive := '0'; v.dsucfg.tenable := '0';
v.timer := (others => '0');
v.hsel := '0'; v.dsucfg.dcnten := '0'; v.dsucfg.dbreak := r.dsubre(2);
v.dsucfg.btrape := r.dsubre(2); v.dsucfg.berror := r.dsubre(2);
v.dsucfg.bwatch := r.dsubre(2); v.dsucfg.bsoft := '0';
v.dsucfg.btrapa := r.dsubre(2); v.dsucfg.lresp := '0';
v.dsucfg.step := '0';
v.dsucfg.dresp := '0'; v.dsucfg.ftimer := '0'; v.dsucfg.btrace := '0';
v.dsucfg.bahb := '0';
v.tbreg1.read := '0'; v.tbreg1.write := '0'; v.tbreg1.exec := '0';
v.tbreg2.read := '0'; v.tbreg2.write := '0'; v.tbreg2.exec := '0';
end if;
rin <= v;
dmi.pbufi <= vpbufi;
dmi.abufi <= vabufi;
ahbso.hrdata <= r.hwdata;
ahbso.hready <= r.hready;
dbgo.btrapa <= r.dsucfg.btrapa;
dbgo.btrape <= r.dsucfg.btrape;
dbgo.berror <= r.dsucfg.berror;
dbgo.bwatch <= r.dsucfg.bwatch;
dbgo.bsoft <= r.dsucfg.bsoft;
dbgo.dbreak <= r.dsucfg.dbreak;
dbgo.rerror <= r.dsucfg.rerror;
dbgo.dsuen <= r.dsuen(2);
dbgo.daddr <= r.haddr(20 downto 2);
dbgo.dwrite <= r.hwrite;
dbgo.ddata <= r.hwdata;
dbgo.denable <= denable;
dbgo.step <= r.dsucfg.step ;
end process;
ahbso.hresp <= HRESP_OKAY;
memstatregs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/VFLOAT_2015/General Modules/parameterized modules/parameterized_variable_shifter/parameterized_variable_shifter_row.vhd
|
4
|
6272
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized variable shifter row --
----------------------------------------------------------
entity parameterized_variable_shifter_row is
generic
(
bits : integer := 0;
row_number : integer := 0;
direction : std_logic := '0' --0=right,1=left
);
port
(
--inputs
I : in std_logic_vector(bits-1 downto 0);
S : in std_logic;
FILL : in std_logic;
--outputs
O : out std_logic_vector(bits-1 downto 0)
);
end parameterized_variable_shifter_row;
----------------------------------------------------------
-- Parameterized variable shifter row --
----------------------------------------------------------
--architecture parameterized_variable_shifter_row_arch of parameterized_variable_shifter_row is
-- --CONSTANTS
-- constant shift : integer := 2**row_number;
--begin
-- right : if(direction='0') generate --right shift logic
-- shift_right : for x in 0 to bits-shift-1 generate
-- sr : mux2
-- port map
-- (
-- --inputs
-- A => I(x+shift),
-- B => I(x),
-- S => S,
-- --outputs
-- O => O(x)
-- );
-- end generate;--x
-- zero_fill : for y in bits-shift to bits-1 generate
-- zf : mux2
-- port map
-- (
-- --inputs
-- A => '0',
-- B => I(y),
-- S => S,
-- --outputs
-- O => O(y)
-- );
-- end generate;--y
-- end generate;--right
-- left : if(direction='1') generate --left shift logic
-- shift_left : for x in shift to bits-1 generate
-- sl : mux2
-- port map
-- (
-- --inputs
-- A => I(x-shift),
-- B => I(x),
-- S => S,
-- --outputs
-- O => O(x)
-- );
-- end generate;--x
-- zero_fill : for y in 0 to shift-1 generate
-- zf : mux2
-- port map
-- (
-- --inputs
-- A => '0',
-- B => I(y),
-- S => S,
-- --outputs
-- O => O(y)
-- );
-- end generate;--y
-- end generate;--left
--end parameterized_variable_shifter_row_arch; -- end of architecture
----------------------------------------------------------
-- Haiqian's shifter, change the mux2 part --
----------------------------------------------------------
architecture parameterized_variable_shifter_row_arch of parameterized_variable_shifter_row is
--CONSTANTS
constant shift : integer := 2**row_number;
begin
right : if(direction='0') generate --right shift logic
shift_right : for x in 0 to bits-shift-1 generate
O(x) <= I(x+shift) when (S='1') else I(x);
end generate;--x
zero_fill : for y in bits-shift to bits-1 generate
-- O(y) <= '0' when (S = '1') else I(y);
O(y) <= FILL when (S = '1') else I(y);
end generate;--y
end generate;--right
left : if(direction='1') generate --left shift logic
shift_left : for x in shift to bits-1 generate
O(x) <= I(x-shift) when (S = '1') else I(x);
end generate;--x
zero_fill : for y in 0 to shift-1 generate
-- O(y) <= '0' when (S = '1') else I(y);
O(y) <= FILL when (S = '1') else I(y);
end generate;--y
end generate;--left
end parameterized_variable_shifter_row_arch; -- end of architecture
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon2-1.0.2a/leon/icache.vhd
|
1
|
11351
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: icache
-- File: icache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implements the instruction cache controller.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.config.all;
use work.sparcv8.all; -- ASI declarations
use work.iface.all;
use work.macro.all; -- xorv()
use work.amba.all;
entity icache is
port (
rst : in std_logic;
clk : in clk_type;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_logic
);
end;
architecture rtl of icache is
constant TAG_HIGH : integer := ITAG_HIGH;
constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant OFFSET_HIGH: integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := ILINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others=>'1');
type rdatatype is (itag, idata, memory); -- sources during cache read
type icache_control_type is record -- all registers
req, burst, mds, holdn : std_logic;
overrun : std_logic; --
underrun : std_logic; --
istate : std_logic_vector(1 downto 0); -- FSM vector
write : std_logic; -- icache I/F strobes
branch : std_logic;
waddress : std_logic_vector(31 downto PCLOW); -- write address buffer
valid : std_logic_vector(ILINE_SIZE-1 downto 0); -- valid bits
hit : std_logic;
su : std_logic;
flush : std_logic; -- flush in progress
flush2 : std_logic; -- flush in progress
faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address
diagrdy : std_logic;
end record;
signal r, c : icache_control_type; -- r is registers, c is combinational
begin
ictrl : process(rst, r, mcio, ici, dci, dco, icramo, fpuholdn)
variable rdatasel : rdatatype;
variable faddress : std_logic_vector(31 downto PCLOW);
variable twrite, diagen, dwrite : std_logic;
variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address
variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable diagdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((ILINE_SIZE -1) downto 0);
variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0);
variable lastline, nlastline, nnlastline : std_logic;
variable enable : std_logic;
variable error : std_logic;
variable whit, cachable, hit, valid : std_logic;
variable cacheon : std_logic;
variable v : icache_control_type;
variable branch : std_logic;
variable eholdn : std_logic;
variable tparerr, dparerr : std_logic;
variable memaddr : std_logic_vector(31 downto PCLOW);
begin
-- init local variables
v := r;
v.mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0';
v.write := mcio.ready; v.diagrdy := '0'; v.holdn := '1';
cacheon := mcio.ics(0) and not r.flush;
enable := '1'; branch := '0';
eholdn := dco.hold and fpuholdn;
rdatasel := idata; -- read data from cache as default
ddatain := mcio.data; -- load full word from memory
wtag := r.waddress(TAG_HIGH downto TAG_LOW);
tparerr := '0'; dparerr := '0';
-- generate access parameters during pipeline stall
if r.overrun = '1' then faddress := ici.dpc;
else faddress := ici.fpc; end if;
-- generate cache hit and valid bits
if (faddress(31) = '0') and (faddress(30 downto 29) /= "01") then
cachable := not r.flush;
else cachable := '0'; end if;
if (icramo.itramout.tag = ici.fpc(TAG_HIGH downto TAG_LOW)) then
hit := cachable and not tparerr;
else hit := '0'; end if;
if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1';
else lastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then
nlastline := '1';
else nlastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then
nnlastline := '1';
else nnlastline := '0'; end if;
-- pragma translate_off
if not is_x(faddress(LINE_HIGH downto LINE_LOW)) then
-- pragma translate_on
valid := genmux(ici.fpc(LINE_HIGH downto LINE_LOW), icramo.itramout.valid);
-- pragma translate_off
end if;
-- pragma translate_on
-- pragma translate_off
if not is_x(r.waddress) then
-- pragma translate_on
xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1;
-- pragma translate_off
end if;
-- pragma translate_on
if mcio.ready = '1' then
v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
taddr := ici.rpc(TAG_HIGH downto LINE_LOW);
-- main Icache state machine
case r.istate is
when "00" => -- main state and cache hit
v.valid := icramo.itramout.valid;
v.hit := hit; v.su := ici.su;
if (ici.nullify or eholdn) = '0' then
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
v.burst := mcio.burst and not lastline;
if (eholdn and not ici.nullify ) = '1' then
if not ((cacheon and hit and valid) and not dparerr) = '1' then
v.istate := "01"; v.req := '1';
v.holdn := '0'; v.overrun := '1';
end if;
v.waddress := ici.fpc(31 downto PCLOW);
end if;
if dco.icdiag.enable = '1' then
diagen := '1';
end if;
ddatain := dci.maddress;
when "01" => -- streaming: update cache and send data to IU
rdatasel := memory;
taddr(TAG_HIGH downto LINE_LOW) := r.waddress(TAG_HIGH downto LINE_LOW);
branch := (ici.fbranch and r.overrun) or
(ici.rbranch and (not r.overrun));
v.underrun := r.underrun or
(v.write and ((ici.nullify or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun))));
v.overrun := (r.overrun or (eholdn and not ici.nullify)) and
not (v.write or r.underrun);
if mcio.ready = '1' then
-- v.mds := not (v.overrun and not r.underrun);
v.mds := not (r.overrun and not r.underrun);
-- v.req := r.burst;
v.burst := v.req and not nnlastline;
end if;
if mcio.grant = '1' then
v.req := mcio.burst and r.burst and
(not (nnlastline and mcio.ready)) and (not branch) and
not (v.underrun and not cacheon);
v.burst := v.req and not nnlastline;
end if;
v.underrun := (v.underrun or branch) and not v.overrun;
v.holdn := not (v.overrun or v.underrun);
if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then
v.underrun := '0'; v.overrun := '0';
if (mcio.ics(0) and not r.flush2) = '1' then
v.istate := "10"; v.holdn := '0';
else
v.istate := "00"; v.flush := r.flush2; v.holdn := '1';
if r.overrun = '1' then taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
end if;
end if;
when "10" => -- return to main
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
v.istate := "00"; v.flush := r.flush2;
when others => v.istate := "00";
end case;
if mcio.retry = '1' then v.req := '1'; end if;
-- Generate new valid bits write strobe
vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW));
twrite := v.write;
if cacheon = '0' then
twrite := '0'; vmask := (others => '0');
elsif (mcio.ics = "01") then
twrite := twrite and r.hit;
vmask := icramo.itramout.valid or vmaskraw;
else
if r.hit = '1' then vmask := r.valid or vmaskraw;
else vmask := vmaskraw; end if;
end if;
if (mcio.mexc or not mcio.cache) = '1' then
twrite := '0'; dwrite := '0';
else dwrite := twrite; end if;
if twrite = '1' then v.valid := vmask; v.hit := '1'; end if;
-- diagnostic cache access
diagdata := icramo.idramout.data;
if diagen = '1' then -- diagnostic access
taddr(OFFSET_HIGH downto LINE_LOW) := dco.icdiag.addr(OFFSET_HIGH downto LINE_LOW);
wtag := dci.maddress(TAG_HIGH downto TAG_LOW);
if dco.icdiag.tag = '1' then
twrite := not dco.icdiag.read; dwrite := '0';
diagdata := (others => '0');
diagdata(TAG_HIGH downto TAG_LOW) := icramo.itramout.tag;
diagdata(ILINE_SIZE -1 downto 0) := icramo.itramout.valid;
else
dwrite := not dco.icdiag.read; twrite := '0';
end if;
vmask := dci.maddress(ILINE_SIZE -1 downto 0);
v.diagrdy := '1';
end if;
-- select data to return on read access
case rdatasel is
when memory => rdata := mcio.data;
when others => rdata := icramo.idramout.data;
end case;
-- cache flush
if (ici.flush or dco.icdiag.flush) = '1' then
v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0');
end if;
if r.flush2 = '1' then
twrite := '1'; vmask := (others => '0'); v.faddr := r.faddr +1;
taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
if (r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1)) = '1' then
v.flush2 := '0';
end if;
end if;
-- reset
if rst = '0' then
v.istate := "00"; v.req := '0'; v.burst := '0'; v.holdn := '1';
v.flush := '0'; v.flush2 := '0';
v.overrun := '0'; v.branch := '0'; v.underrun := '0';
end if;
-- Drive signals
c <= v; -- register inputs
-- tag ram inputs
icrami.itramin.valid <= vmask;
icrami.itramin.tag <= wtag;
icrami.itramin.enable <= enable;
icrami.itramin.write <= twrite;
-- data ram inputs
icrami.idramin.enable <= enable;
icrami.idramin.address <= taddr(OFFSET_HIGH downto LINE_LOW);
icrami.idramin.data <= ddatain;
icrami.idramin.write <= dwrite;
-- memory controller inputs
mcii.address(31 downto 2) <= r.waddress(31 downto 2);
mcii.address(1 downto 0) <= "00";
mcii.su <= r.su;
mcii.burst <= r.burst;
mcii.req <= r.req;
mcii.flush <= r.flush;
-- IU data cache inputs
ico.data <= rdata;
ico.exception <= mcio.mexc or error;
ico.hold <= r.holdn;
ico.mds <= v.mds;
ico.flush <= r.flush;
ico.diagdata <= diagdata;
ico.diagrdy <= r.diagrdy;
end process;
-- Local registers
regs1 : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
end ;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/vhdl_designs/tbamba.vhd
|
1
|
3782
|
-- Test Bench for cores using AMBA Bus signals
-- LA 6.03.02
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.iface.all;
use work.amba.all;
entity tbamba is
generic (
doit : std_logic :='1'
);
end tbamba;
architecture behav of tbamba is
--component ddm
-- port (
-- rst : in std_logic;
-- clk : in std_logic;
-- apbi : in apb_slv_in_type;
-- apbo : out apb_slv_out_type;
-- ahbi : in ahb_mst_in_type;
-- ahbo : out ahb_mst_out_type;
-- ddmi : in ddm_in_type;
-- ddmo : out ddm_out_type;
-- irq : out std_logic );
--end component;
component mdct
port (
rst : in std_logic;
clk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
irq : out std_logic );
end component;
signal clk : std_logic := '0';
signal rst : std_logic := '0'; -- Reset
constant ct : integer := 40/2;
signal audioout : std_logic;
signal lr_out : std_logic;
signal shift_clk : std_logic;
signal mclk : std_logic;
signal apbi : APB_Slv_In_Type;
signal apbo : apb_slv_out_type;
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
signal ddmi : ddm_in_type;
signal ddmo : ddm_out_type;
signal irq : std_logic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
-- rst <= '0', '1' after 40*10 * 1 ns;
rst <= '0', '1' after 250 ns;
-- **********************************************
-- APB control registers
-- **********************************************
-- conditions for writing memory mapped registers. Signals from APB master allowing write
apbi.psel<='1' after 350 ns;
apbi.penable<='1' after 350 ns;
apbi.pwrite<='1' after 350 ns;
-- Data Bus activity
-- apbi.pwdata<="00000000000000001111100000000110" after 500 ns; -- disable mdct after process all elements
-- "00000000000000001111100000000001" after 460 ns; -- enable mdct
-- Address bus activity
apbi.paddr(31 downto 5)<="000000000000000000000000000" after 440 ns;
apbi.paddr(4 downto 0)<="01000" after 440 ns, --- address of size data array
"00100" after 480 ns, -- address of start read address register
"01100" after 520 ns, -- address of start write address register
"00000" after 680 ns; -- address of mdct control register
-- set dma start address
-- set dma stop address
-- apbi.pwdata<="00000000000000001111111100000011" after 460 ns;
-- **********************************************
-- AHB transfers
-- **********************************************
-- AHB bus is granted and ready after requesting. Action by arbitrer.
ahbi.hgrant<='1' after 600 ns;
ahbi.hready<='1' after 620 ns;
--APB dat bus activity for memory mapped registers
apbi.pwdata<="00000000000000001111100000000110" after 300 ns, -- set number of elements in array elements
"00000000000000001111100000011000" after 460 ns, -- start read address
"00000000000000001111100000110000" after 500 ns, -- start write address
"00000000000000001111100000000001" after 660 ns; -- enable mdct
--"00000000000000001111100000000110" after 1450 ns; -- disable mdct
-- Data from memory on the bus
ahbi.hrdata<="11001100110010101011000000000000" after 740 ns,
"11001100110010101011000000000001" after 790 ns,
"11001100110010101011000000000010" after 840 ns,
"11001100110010101011000000000011" after 890 ns,
"11001100110010101011000000010011" after 940 ns,
ahbo.hwdata after 990 ns, -- in the last two values the result is the input
ahbo.hwdata after 1040 ns;
-- amba0 : ddm -- core using amba
-- port map (rst,clk,apbi,apbo,ahbi,ahbo,ddmi,ddmo,irq);
amba1 : mdct
port map (rst,clk,apbi,apbo,ahbi,ahbo,irq);
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/VFLOAT_2015/General Modules/round to normal wrapper/round_add.vhd
|
1
|
6373
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- RAPID PROTOTYPING LABORATORY --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | Nov. 2014 --
--======================================================--
--**********************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--**********************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Rounding addition --
----------------------------------------------------------
entity round_add is
generic
(
exp_bits : integer := 0;
man_bits_in : integer := 0;
man_bits_out : integer := 0
);
port
(
--inputs
CLK : in std_logic;
RESET : in std_logic;
STALL : in std_logic;
SIGN_IN : in std_logic;
EXP_IN : in std_logic_vector(exp_bits-1 downto 0);
MAN_IN : in std_logic_vector(man_bits_in-1 downto 0);
READY : in std_logic;
ENABLE : in std_logic;
EXCEPTION_IN : in std_logic;
--outputs
DONE : out std_logic;
SIGN_OUT : out std_logic;
EXP_OUT : out std_logic_vector(exp_bits-1 downto 0);
MAN_OUT : out std_logic_vector(man_bits_out-1 downto 0);
EXCEPTION_OUT : out std_logic
);
end round_add;
----------------------------------------------------------
-- Rounding addition --
----------------------------------------------------------
architecture round_add_arch of round_add is
--SIGNALS
signal exponent : std_logic_vector(exp_bits-1 downto 0) := (others=>'0');
signal slice : std_logic_vector(man_bits_out downto 0) := (others=>'0');
signal exp_int : std_logic_vector(exp_bits-1 downto 0) := (others=>'0');
signal man_int : std_logic_vector(man_bits_out downto 0) := (others=>'0');
signal man_carry: std_logic := '0';
signal exc_int : std_logic := '0';
signal exc_pa : std_logic := '0';
signal zeros : std_logic_vector(man_bits_out downto 0) := (others=>'0');
signal zeros_exp: std_logic_vector(exp_bits-1 downto 0) := (others=>'0');
signal int : integer;
signal ifzero : std_logic_vector(man_bits_in-man_bits_out-3 downto 0) := (others => '0');
begin
--ASYNCHRONOUS
--component instantiation
pa : parameterized_adder
generic map
(
bits => man_bits_out+1
)
port map
(
A => slice,
B => zeros,
CIN => ENABLE,
S => man_int,
--COUT => exc_pa
COUT => man_carry
);
pe : parameterized_adder
generic map
(
bits => exp_bits
)
port map
(
A => exponent,
B => zeros_exp,
CIN => man_carry,
S => exp_int,
COUT => exc_pa
);
--signal connections
exponent <= EXP_IN;
slice <= MAN_IN(man_bits_in-2 downto man_bits_in-man_bits_out-2);
exc_int <= exc_pa OR EXCEPTION_IN;
ifzero <= MAN_IN(man_bits_in-man_bits_out-3 downto 0);
int <= conv_integer(ifzero);
--SYNCHRONOUS
main: process (CLK,RESET,STALL) is
begin
if (RESET = '1') then
SIGN_OUT <= '0';
EXP_OUT <= (others=>'0');
MAN_OUT <= (others=>'0');
EXCEPTION_OUT <= '0';
DONE <= '0';
elsif(rising_edge(CLK) and STALL = '0') then
if(int = 0 and MAN_IN(man_bits_in-man_bits_out-2) = '1' and ENABLE = '1') then
SIGN_OUT <= SIGN_IN;
EXP_OUT <= exp_int;
MAN_OUT <= man_int(man_bits_out downto 2)&'0';
EXCEPTION_OUT <= exc_int;
DONE <= READY;
else
SIGN_OUT <= SIGN_IN;
EXP_OUT <= exp_int;
MAN_OUT <= man_int(man_bits_out downto 1);
EXCEPTION_OUT <= exc_int;
DONE <= READY;
end if;
end if; --CLK
end process; --main
end round_add_arch; -- end of architecture
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/MILK_2007/src/cop_components.vhd
|
1
|
30058
|
-----------------------------------------------------------------------------------------------------------
--
-- COMPONENTS PACKAGE
--
-- This package contains several frequently used basic cop_components.
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------------
--Copyright (c) 2004, Tampere University of Technology.
--All rights reserved.
--Redistribution and use in source and binary forms, with or without modification,
--are permitted provided that the following conditions are met:
--* Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--* Neither the name of Tampere University of Technology nor the names of its
-- contributors may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
--CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND
--FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
--OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
--EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
--PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN
--IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------------------------------------
--
-- OE_register
--
-- General purpose register, "reg_width" wide. WRITE ENABLE, OUTPUT ENABLE and RESET commands are provided.
-- Default content at RESET is "zero". WRITE ENABLE, OUTPUT ENABLE and RESET commands polarity are
-- specified by dedicated constants defined in "cop_definitions" package.
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity OE_register is
generic(reg_width: Integer := word_width);
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
oe : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end OE_register;
architecture rtl of OE_register is
signal regout: std_logic_vector(reg_width-1 downto 0);
begin
process(clk, reset)
begin
if reset = reset_active then
regout <= Conv_std_logic_vector(0, reg_width);
elsif CLK'EVENT and CLK='1' then
if we = we_active then
regout <= data_in;
end if;
end if;
end process;
process (oe, regout)
begin
if oe = oe_active then
data_out <= regout;
else
data_out <= (others => 'Z');
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- WE_register
--
-- General purpose register, "reg_width" wide. WRITE ENABLE and RESET commands are provided.
-- Default content at RESET is "zero". WRITE ENABLE and RESET commands polarity are
-- specified by dedicated constants defined in "cop_definitions" package.
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity WE_register is
generic(reg_width: Integer := word_width);
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end WE_register;
architecture rtl of WE_register is
begin
process(clk, reset)
begin
if reset = reset_active then
data_out <= Conv_std_logic_vector(0, reg_width);
elsif CLK'EVENT and CLK='1' then
if we = we_active then data_out <= data_in;
end if;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- SIMPLE DATA REGISTER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity data_register is
generic(reg_width: integer :=8);
port(
clk : in Std_logic;
reset : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0)
);
end data_register;
architecture rtl of data_register is
begin
process(clk, reset)
begin
if reset = reset_active then
data_out <= Conv_std_logic_vector(0,reg_width);
elsif CLK'EVENT and CLK='1' then
data_out <= data_in;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- NOP REGISTER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity nop_register is
generic(reg_width: integer :=word_width);
port(
clk : in Std_logic;
reset : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0)
);
end nop_register;
architecture rtl of nop_register is
begin
process(clk, reset)
begin
if reset = reset_active then
data_out <= "00000000000000000000000000001000"; -- NOP configuration
elsif CLK'EVENT and CLK='1' then
data_out <= data_in;
end if;
end process;
end rtl;
----------------------------------------------------------------------------------------------------------
--
-- D-type Flip-Flop provided with Write Enable command
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity WEDFF is
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end WEDFF;
architecture rtl of WEDFF is
begin
process(clk, reset)
begin
if reset = reset_active then
q <= '0';
elsif CLK'EVENT and CLK='1' then
if we = we_active then
q <= d;
end if;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- D-type Flip-Flop reset
-- value ='0'
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity data_ff is
port( clk : in Std_logic;
reset : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end data_ff;
architecture rtl of data_ff is
begin
process(clk, reset)
begin
if reset = reset_active then
q <= '0';
elsif CLK'EVENT and CLK='1' then
q <= d;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- D-type Flip-Flop reset value = '1'
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity data_ff_1 is
port( clk : in Std_logic;
reset : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end data_ff_1;
architecture rtl of data_ff_1 is
begin
process(clk, reset)
begin
if reset = reset_active then
q <= '1';
elsif CLK'EVENT and CLK='1' then
q <= d;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- DECODER 3:8
--
-- The output addressed by dec_addr is the only one to get an "high" logic value
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity decoder3_8 is
port( dec_addr : in std_logic_vector(2 downto 0);
dec_out : out std_logic_vector(7 downto 0) );
end decoder3_8;
architecture rtl of decoder3_8 is
begin
process(dec_addr)
begin
dec_out(7) <= (dec_addr(2) and dec_addr(1) and dec_addr(0));
dec_out(6) <= (dec_addr(2) and dec_addr(1) and not (dec_addr(0)));
dec_out(5) <= (dec_addr(2) and not (dec_addr(1)) and dec_addr(0));
dec_out(4) <= (dec_addr(2) and not (dec_addr(1)) and not (dec_addr(0)));
dec_out(3) <= (not(dec_addr(2)) and dec_addr(1) and dec_addr(0));
dec_out(2) <= (not(dec_addr(2)) and dec_addr(1) and not(dec_addr(0)));
dec_out(1) <= (not(dec_addr(2)) and not(dec_addr(1)) and dec_addr(0));
dec_out(0) <= (not(dec_addr(2)) and not(dec_addr(1)) and not(dec_addr(0)));
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- TRISTATE BUFFER
--
-- It's a tristate buffer which is "buffer_width" wide. Output is set to Hi-Z value when its output enable
-- control pin is set to "oe_active" value.
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity tristate_buffer is
generic(width : integer := buffer_width);
port(
tristate_buffer_oe : in std_logic;
tristate_buffer_data_in : in std_logic_vector(buffer_width-1 downto 0);
tristate_buffer_data_out : out std_logic_vector(buffer_width-1 downto 0)
);
end tristate_buffer ;
architecture rtl of tristate_buffer is
begin
process (tristate_buffer_oe, tristate_buffer_data_in)
begin
if tristate_buffer_oe = oe_active then
tristate_buffer_data_out <= tristate_buffer_data_in;
else
tristate_buffer_data_out <= (others => 'Z');
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- 8_INPUTS MULTIPLEXER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
entity MY_8IN_MUX is
generic (width : integer :=word_width);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
in_c : in Std_logic_vector(width-1 downto 0);
in_d : in Std_logic_vector(width-1 downto 0);
in_e : in Std_logic_vector(width-1 downto 0);
in_f : in Std_logic_vector(width-1 downto 0);
in_g : in Std_logic_vector(width-1 downto 0);
in_h : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic_vector(2 downto 0);
output : out Std_logic_vector(width-1 downto 0) );
end MY_8IN_MUX;
architecture rtl of MY_8IN_MUX is
begin
process(in_a,in_b,in_c,in_d,in_e,in_f,in_g,in_h,sel)
begin
if sel = "000" then
output <= in_a;
elsif sel = "001" then
output <= in_b;
elsif sel = "010" then
output <= in_c;
elsif sel = "011" then
output <= in_d;
elsif sel = "100" then
output <= in_e;
elsif sel = "101" then
output <= in_f;
elsif sel = "110" then
output <= in_g;
else
output <= in_h;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- CTRL_LOGIC MULTIPLEXER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
entity DELAY_SELECT_MUX is
generic (width : integer := 8);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
in_c : in Std_logic_vector(width-1 downto 0);
in_d : in Std_logic_vector(width-1 downto 0);
in_e : in Std_logic_vector(width-1 downto 0);
in_f : in Std_logic_vector(width-1 downto 0);
in_g : in Std_logic_vector(width-1 downto 0);
in_h : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic_vector(6 downto 0);
output : out Std_logic_vector(width-1 downto 0)
);
end DELAY_SELECT_MUX;
architecture rtl of DELAY_SELECT_MUX is
begin
process(in_a,in_b,in_c,in_d,in_e,in_f,in_g,in_h,sel)
begin
if sel = "0000001" then
output <= in_b;
elsif sel = "0000010" then
output <= in_c;
elsif sel = "0000100" then
output <= in_d;
elsif sel = "0001000" then
output <= in_e;
elsif sel = "0010000" then
output <= in_f;
elsif sel = "0100000" then
output <= in_g;
elsif sel = "1000000" then
output <= in_h;
else
output <= in_a;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- 2_INPUTS MULTIPLEXER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
entity MY_MUX is
generic (width : integer :=8);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic;
output : out Std_logic_vector(width-1 downto 0) );
end MY_MUX;
architecture rtl of MY_MUX is
begin
process(in_a,in_b,sel)
begin
if sel = '0' then
output <= in_a;
else
output <= in_b;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- 2_INPUTS MULTIPLEXER (1 bit-wide inputs)
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
entity SIMPLE_MUX_2 is
port( in_a : in Std_logic;
in_b : in Std_logic;
sel : in Std_logic;
output : out Std_logic );
end SIMPLE_MUX_2;
architecture rtl of SIMPLE_MUX_2 is
begin
process(in_a,in_b,sel)
begin
if sel = '0' then
output <= in_a;
else
output <= in_b;
end if;
end process;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- REGISTER DELAY CHAIN (ctrl_logic)
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity register_chain is
generic ( length : integer := m;
width : integer := n );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
reg_chain_in : in Std_logic_vector(width-1 downto 0);
reg_chain_out : out bus_mxn );
end register_chain;
architecture rtl of register_chain is
signal ctrl_internal_bus : bus_mxn;
begin
ctrl_internal_bus(0) <= reg_chain_in;
WRBCK_DELAY_CHAIN: for i in 0 to (length-1) generate
process(clk, reset)
begin
if reset = reset_active then
ctrl_internal_bus(i+1) <= conv_std_logic_vector(0, width);
elsif CLK'EVENT and CLK='1' then
if enable = we_active then
ctrl_internal_bus(i+1) <= ctrl_internal_bus(i);
end if;
end if;
end process;
end generate WRBCK_DELAY_CHAIN;
reg_chain_out <= ctrl_internal_bus;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- SIMPLE REGISTER DELAY CHAIN
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity simple_register_chain is
generic ( length : integer := m;
width : integer := n );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
reg_chain_in : in Std_logic_vector(width-1 downto 0);
reg_chain_out : out Std_logic_vector(width-1 downto 0) );
end simple_register_chain;
architecture rtl of simple_register_chain is
type bus_lengthXwidth is array (length downto 0) of std_logic_vector(width-1 downto 0);
signal ctrl_internal_bus : bus_lengthXwidth;
begin
ctrl_internal_bus(0) <= reg_chain_in;
WRBCK_DELAY_CHAIN: for i in 0 to (length-1) generate
process(clk, reset)
begin
if reset = reset_active then
ctrl_internal_bus(i+1) <= conv_std_logic_vector(0, width);
elsif CLK'EVENT and CLK='1' then
if enable = we_active then
ctrl_internal_bus(i+1) <= ctrl_internal_bus(i);
end if;
end if;
end process;
end generate WRBCK_DELAY_CHAIN;
reg_chain_out <= ctrl_internal_bus(length);
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- FF DELAY CHAIN
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity ff_variable_chain is
generic ( length : integer := m);
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
ff_chain_in : in Std_logic;
ff_chain_out : out Std_logic_vector(length downto 0) );
end ff_variable_chain;
architecture rtl of ff_variable_chain is
signal ctrl_internal_bus : Std_logic_vector(length downto 0);
begin
ctrl_internal_bus(0) <= ff_chain_in;
VARIABLE_DELAY_CHAIN: for i in 0 to (length-1) generate
process(clk, reset)
begin
if reset = reset_active then
ctrl_internal_bus(i+1) <= '0';
elsif CLK'EVENT and CLK='1' then
if enable = we_active then
ctrl_internal_bus(i+1) <= ctrl_internal_bus(i);
end if;
end if;
end process;
end generate VARIABLE_DELAY_CHAIN;
ff_chain_out <= ctrl_internal_bus;
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- SIMPLE FF DELAY CHAIN
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
entity ff_chain is
generic ( length : integer := m );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
ff_chain_in : in Std_logic;
ff_chain_out : out std_logic );
end ff_chain;
architecture rtl of ff_chain is
signal ff_chain_internal_signals : std_logic_vector(length downto 0);
begin
ff_chain_internal_signals(0) <= ff_chain_in;
WRBCK_DELAY_CHAIN: for i in 0 to (length-1) generate
process(clk, reset)
begin
if reset = reset_active then
ff_chain_internal_signals(i+1) <= '0';
elsif CLK'EVENT and CLK='1' then
if enable = we_active then
ff_chain_internal_signals(i+1) <= ff_chain_internal_signals(i);
end if;
end if;
end process;
end generate WRBCK_DELAY_CHAIN;
ff_chain_out <= ff_chain_internal_signals(length);
end rtl;
-----------------------------------------------------------------------------------------------------------
--
-- PACKAGE HEADER
--
-----------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
package cop_components is
component OE_register
generic(reg_width: Integer := word_width);
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
oe : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end component;
component WE_register
generic(reg_width: Integer := word_width);
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end component;
component data_register
generic(reg_width: Integer);
port( clk : in Std_logic;
reset : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0) );
end component;
component nop_register
generic(reg_width: integer :=word_width);
port(
clk : in Std_logic;
reset : in Std_logic;
data_in : in Std_logic_vector(reg_width-1 downto 0);
data_out : out Std_logic_vector(reg_width-1 downto 0)
);
end component;
component WEDFF
port( clk : in Std_logic;
reset : in Std_logic;
we : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end component;
component data_ff
port( clk : in Std_logic;
reset : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end component;
component data_ff_1
port( clk : in Std_logic;
reset : in Std_logic;
d : in Std_logic;
q : out Std_logic );
end component;
component decoder3_8
port( dec_addr : in std_logic_vector(2 downto 0);
dec_out : out std_logic_vector(7 downto 0) );
end component;
component tristate_buffer
generic(width : integer := buffer_width);
port( tristate_buffer_oe : in std_logic;
tristate_buffer_data_in : in std_logic_vector(buffer_width-1 downto 0);
tristate_buffer_data_out : out std_logic_vector(buffer_width-1 downto 0) );
end component;
component MY_8IN_MUX
generic (width : integer :=word_width);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
in_c : in Std_logic_vector(width-1 downto 0);
in_d : in Std_logic_vector(width-1 downto 0);
in_e : in Std_logic_vector(width-1 downto 0);
in_f : in Std_logic_vector(width-1 downto 0);
in_g : in Std_logic_vector(width-1 downto 0);
in_h : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic_vector(2 downto 0);
output : out Std_logic_vector(width-1 downto 0) );
end component;
component DELAY_SELECT_MUX
generic (width : integer := 8);
port( in_a : in Std_logic_vector(width-1 downto 0);
in_b : in Std_logic_vector(width-1 downto 0);
in_c : in Std_logic_vector(width-1 downto 0);
in_d : in Std_logic_vector(width-1 downto 0);
in_e : in Std_logic_vector(width-1 downto 0);
in_f : in Std_logic_vector(width-1 downto 0);
in_g : in Std_logic_vector(width-1 downto 0);
in_h : in Std_logic_vector(width-1 downto 0);
sel : in Std_logic_vector(6 downto 0);
output : out Std_logic_vector(width-1 downto 0)
);
end component;
component MY_MUX
generic ( width : integer);
port(in_a : in Std_logic_vector(word_width-1 downto 0);
in_b : in Std_logic_vector(word_width-1 downto 0);
sel : in Std_logic;
output : out Std_logic_vector(word_width-1 downto 0) );
end component;
component SIMPLE_MUX_2
port( in_a : in Std_logic;
in_b : in Std_logic;
sel : in Std_logic;
output : out Std_logic );
end component;
component register_chain
generic ( length : integer := m;
width : integer := n );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
reg_chain_in : in Std_logic_vector(n-1 downto 0);
reg_chain_out : out bus_mxn );
end component;
component simple_register_chain
generic ( length : integer := m;
width : integer := n );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
reg_chain_in : in Std_logic_vector(width-1 downto 0);
reg_chain_out : out Std_logic_vector(width-1 downto 0) );
end component;
component ff_variable_chain
generic ( length : integer := m);
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
ff_chain_in : in Std_logic;
ff_chain_out : out Std_logic_vector(length downto 0) );
end component;
component ff_chain
generic ( length : integer := m );
port( clk : in std_logic;
reset : in std_logic;
enable : in Std_logic;
ff_chain_in : in Std_logic;
ff_chain_out : out std_logic );
end component;
end cop_components;
package body cop_components is
end cop_components;
|
gpl-3.0
|
freecores/layer2
|
vhdl/ddr/rtl/ddr_init.vhd
|
1
|
12530
|
--------------------------------------------------------------------------------
-- Mycron® DDR SDRAM - MT46V32M16 - 8 Meg x 16 x 4 banks --
--------------------------------------------------------------------------------
-- Copyright (C)2012 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ddr_init is
port (
clk0 : in std_logic;
rst : in std_logic;
SD_CKE : out std_logic;
SD_BA : out std_logic_vector(1 downto 0);
SD_A : out std_logic_vector(12 downto 0);
SD_CMD : out std_logic_vector(3 downto 0);
init_done : out boolean
);
end ddr_init;
architecture rtl of ddr_init is
-----------------------------------------------------------------------------
-- Controller Commands --
-----------------------------------------------------------------------------
constant CMD_LMR : std_logic_vector(3 downto 0) := "0000";
constant CMD_AUTO_REFRESH : std_logic_vector(3 downto 0) := "0001";
constant CMD_PRECHARGE : std_logic_vector(3 downto 0) := "0010";
constant CMD_NOP : std_logic_vector(3 downto 0) := "0111";
-----------------------------------------------------------------------------
-- Mode Rgister Addresses --
-----------------------------------------------------------------------------
-- Addresses for the two mode registers, selected via SD_BA.
constant BMR_ADDR : std_logic_vector(1 downto 0) := "00";
constant EMR_ADDR : std_logic_vector(1 downto 0) := "01";
-----------------------------------------------------------------------------
-- Base Mode Rgister --
-----------------------------------------------------------------------------
-- Operating modes.
constant OP_NORMAL : std_logic_vector(5 downto 0) := "000000";
constant OP_DLL_RST : std_logic_vector(5 downto 0) := "000010";
-- CAS latency.
constant CAS_2 : std_logic_vector(2 downto 0) := "010";
-- Burst type.
constant BT_S : std_logic := '0'; -- Sequential.
-- Burst lengths.
constant BL_2 : std_logic_vector(2 downto 0) := "001";
-----------------------------------------------------------------------------
-- Extended Mode Rgister --
-----------------------------------------------------------------------------
-- DLL.
constant DLL_ENABLE : std_logic := '0';
constant DLL_DISABLE : std_logic := '1';
-- Drive strength.
constant DS_NORMAL : std_logic := '0';
-----------------------------------------------------------------------------
-- Initialization --
-----------------------------------------------------------------------------
type init_state_t is (
Wait20000, -- Wait for 200µs.
CKE_High, -- Assert CKE.
Precharge0, Precharge0Wait, -- First precharge.
ProgramEMR, ProgramEMRWait, -- Set Extended Mode Register.
ProgramMR, ProgramMRWait, -- Set Base Mode Register.
Precharge1, Precharge1Wait, -- second precharge.
AutoRefresh0, AutoRefresh0Wait, -- First autorefresh.
AutoRefresh1, AutoRefresh1Wait, -- Second autorefresh.
ProgramMR1, ProgramMR1Wait, -- Set Base Mode Register.
Wait200, -- Wait for 200 cycles.
Done -- Initialization done!
);
type init_t is record
s : init_state_t;
c : natural range 0 to 19999;
end record;
constant init_d : init_t := init_t'( Wait20000, 0);
signal i, iin : init_t := init_d;
begin
-----------------------------------------------------------------------------
-- Initialization --
-----------------------------------------------------------------------------
initial : process(i)
begin
iin <= i;
SD_CKE <= '1';
SD_BA <= "00";
SD_CMD <= CMD_NOP;
SD_A <= (others => '0');
init_done <= false;
case i.s is
-----------------------------------------------------------------------
-- 5. Wait for 200µs. --
-----------------------------------------------------------------------
when Wait20000 =>
SD_CKE <= '0';
if i.c = 19999 then
iin.c <= 0;
iin.s <= CKE_High;
else
iin.c <= i.c + 1;
end if;
-----------------------------------------------------------------------
-- 6. Bring CKE high. --
-----------------------------------------------------------------------
when CKE_High =>
iin.s <= Precharge0;
-----------------------------------------------------------------------
-- 7. Precharge all banks. --
-----------------------------------------------------------------------
when Precharge0 =>
SD_CMD <= CMD_PRECHARGE;
SD_A(10) <= '1'; -- Precharge all operation.
iin.s <= Precharge0Wait;
-- PRECHARGE command period tRP: 15ns
when Precharge0Wait =>
if i.c = 1 then
iin.c <= 0;
iin.s <= ProgramEMR;
else
iin.c <= i.c + 1;
end if;
-----------------------------------------------------------------------
-- 9. Program the Extended Mode Register. --
-----------------------------------------------------------------------
when ProgramEMR =>
SD_CMD <= CMD_LMR;
SD_BA <= EMR_ADDR; -- Select Extended Mode Register.
SD_A <= "00000000000" & DS_NORMAL & DLL_DISABLE;
iin.s <= ProgramEMRWait;
-- LOAD MODE REGISTER command cycle time tMRD: 12ns
when ProgramEMRWait =>
if i.c = 1 then
iin.c <= 0;
iin.s <= ProgramMR;
else
iin.c <= i.c + 1;
end if;
-----------------------------------------------------------------------
-- 11. Program the Mode Rgister --
-----------------------------------------------------------------------
when ProgramMR =>
SD_CMD <= CMD_LMR;
SD_BA <= BMR_ADDR; -- Select Base Mode Register.
SD_A <= OP_NORMAL & CAS_2 & BT_S & BL_2;
iin.s <= ProgramMRWait;
-- LOAD MODE REGISTER command cycle time tMRD: 12ns
when ProgramMRWait =>
if i.c = 1 then
iin.c <= 0;
iin.s <= Precharge1;
else
iin.c <= i.c + 1;
end if;
-----------------------------------------------------------------------
-- 13. Precharge all banks. --
-----------------------------------------------------------------------
when Precharge1 =>
SD_CMD <= CMD_PRECHARGE;
SD_A(10) <= '1'; -- Precharge all operation.
iin.s <= Precharge1Wait;
-- PRECHARGE command period tRP: 15ns
when Precharge1Wait =>
if i.c = 1 then
iin.c <= 0;
iin.s <= AutoRefresh0;
else
iin.c <= i.c + 1;
end if;
-----------------------------------------------------------------------
-- 15. Auto Refresh. --
-----------------------------------------------------------------------
when AutoRefresh0 =>
SD_CMD <= CMD_AUTO_REFRESH;
iin.s <= AutoRefresh0Wait;
-- AUTO REFRESH command period tRFC: 72ns
when AutoRefresh0Wait =>
if i.c = 7 then
iin.c <= 0;
iin.s <= AutoRefresh1;
else
iin.c <= i.c + 1;
end if;
-----------------------------------------------------------------------
-- 17. Auto Refresh. --
-----------------------------------------------------------------------
when AutoRefresh1 =>
SD_CMD <= CMD_AUTO_REFRESH;
iin.s <= AutoRefresh1Wait;
-- AUTO REFRESH command period tRFC: 72ns
when AutoRefresh1Wait =>
if i.c = 7 then
iin.c <= 0;
iin.s <= ProgramMR1;
else
iin.c <= i.c + 1;
end if;
-----------------------------------------------------------------------
-- 19. Program the Mode Rgister (Clear DLL Bit) --
-----------------------------------------------------------------------
when ProgramMR1 =>
SD_CMD <= CMD_LMR;
SD_BA <= BMR_ADDR; -- Select Base Mode Register.
SD_A <= OP_NORMAL & CAS_2 & BT_S & BL_2;
iin.s <= ProgramMR1Wait;
-- LOAD MODE REGISTER command cycle time tMRD: 12ns
when ProgramMR1Wait =>
if i.c = 1 then
iin.c <= 0;
iin.s <= Wait200;
else
iin.c <= i.c + 1;
end if;
-----------------------------------------------------------------------
-- 21. Wait for 200 cycles. --
-----------------------------------------------------------------------
when Wait200 =>
if i.c = 199 then
iin.c <= 0;
iin.s <= Done;
else
iin.c <= i.c + 1;
end if;
-----------------------------------------------------------------------
-- Initialization done. --
-----------------------------------------------------------------------
when Done =>
init_done <= true;
end case;
end process;
-----------------------------------------------------------------------------
-- Register --
-----------------------------------------------------------------------------
reg : process(clk0)
begin
if rising_edge(clk0) then
if rst = '1' then i <= init_d; else i <= iin; end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Jidan FPU/tags/arelease/post_norm_addsub.vhd
|
2
|
8048
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: post-normalization entity for the addition/subtraction unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.fpupack.all;
entity post_norm_addsub is
port(
clk_i : in std_logic;
opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
fract_28_i : in std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
sign_i : in std_logic;
fpu_op_i : in std_logic;
rmode_i : in std_logic_vector(1 downto 0);
output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
ine_o : out std_logic
);
end post_norm_addsub;
architecture rtl of post_norm_addsub is
signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_fract_28_i : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_exp_i : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_sign_i : std_logic;
signal s_fpu_op_i : std_logic;
signal s_rmode_i : std_logic_vector(1 downto 0);
signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
signal s_ine_o : std_logic;
signal s_overflow : std_logic;
signal s_shr1, s_shr2, s_shl : std_logic;
signal s_expr1_9, s_expr2_9, s_expl_9 : std_logic_vector(EXP_WIDTH downto 0);
signal s_exp_shr1, s_exp_shr2, s_exp_shl : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fract_shr1, s_fract_shr2, s_fract_shl : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_zeros : std_logic_vector(5 downto 0);
signal shl_pos: std_logic_vector(5 downto 0);
signal s_fract_1, s_fract_2 : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_exp_1, s_exp_2 : std_logic_vector(EXP_WIDTH-1 downto 0);
signal s_fract_rnd : std_logic_vector(FRAC_WIDTH+4 downto 0);
signal s_roundup : std_logic;
signal s_sticky : std_logic;
signal s_zero_fract : std_logic;
signal s_lost : std_logic;
signal s_infa, s_infb : std_logic;
signal s_nan_in, s_nan_op, s_nan_a, s_nan_b, s_nan_sign : std_logic;
begin
-- Input Register
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
s_opa_i <= opa_i;
s_opb_i <= opb_i;
s_fract_28_i <= fract_28_i;
s_exp_i <= exp_i;
s_sign_i <= sign_i;
s_fpu_op_i <= fpu_op_i;
s_rmode_i <= rmode_i;
-- end if;
--end process;
-- Output Register
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
output_o <= s_output_o;
ine_o <= s_ine_o;
-- end if;
--end process;
-- check if shifting is needed
s_shr1 <= s_fract_28_i(27);
s_shl <= '1' when s_fract_28_i(27 downto 26)="00" and s_exp_i /= "00000000" else '0';
-- stage 1a: right-shift (when necessary)
s_expr1_9 <= "0"&s_exp_i + "000000001";
s_fract_shr1 <= shr(s_fract_28_i, "1");
s_exp_shr1 <= s_expr1_9(7 downto 0);
-- stage 1b: left-shift (when necessary)
process(clk_i)
begin
if rising_edge(clk_i) then
-- count the leading zero's of fraction, needed for left-shift
s_zeros <= count_l_zeros(s_fract_28_i(26 downto 0));
end if;
end process;
s_expl_9 <= ("0"&s_exp_i) - ("000"&s_zeros);
shl_pos <= "000000" when s_exp_i="00000001" else s_zeros;
s_fract_shl <= shl(s_fract_28_i, shl_pos);
s_exp_shl <= "00000000" when s_exp_i="00000001" else s_exp_i - ("00"&shl_pos);
process(clk_i)
begin
if rising_edge(clk_i) then
if s_shr1='1' then
s_fract_1 <= s_fract_shr1;
elsif s_shl='1' then
s_fract_1 <= s_fract_shl;
else
s_fract_1 <= s_fract_28_i;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if s_shr1='1' then
s_exp_1 <= s_exp_shr1;
elsif s_shl='1' then
s_exp_1 <= s_exp_shl;
else
s_exp_1 <= s_exp_i;
end if;
end if;
end process;
-- round
s_sticky <='1' when s_fract_1(0)='1' or (s_fract_28_i(0) and s_fract_28_i(27))='1' else '0'; --check last bit, before and after right-shift
s_roundup <= s_fract_1(2) and ((s_fract_1(1) or s_sticky)or s_fract_1(3)) when s_rmode_i="00" else -- round to nearset even
(s_fract_1(2) or s_fract_1(1) or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
(s_fract_1(2) or s_fract_1(1) or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
'0'; -- round to zero(truncate = no rounding)
s_fract_rnd <= s_fract_1 + "0000000000000000000000001000" when s_roundup='1' else s_fract_1;
-- stage 2: right-shift after rounding (when necessary)
s_shr2 <= s_fract_rnd(27);
s_expr2_9 <= ("0"&s_exp_1) + "000000001";
s_fract_shr2 <= shr(s_fract_rnd, "1");
s_exp_shr2 <= s_expr2_9(7 downto 0);
s_fract_2 <= s_fract_shr2 when s_shr2='1' else s_fract_rnd;
s_exp_2 <= s_exp_shr2 when s_shr2='1' else s_exp_1;
-------------
s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0';
s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0';
s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
s_nan_b <= '1' when (s_infb='1' and or_reduce (s_opb_i(22 downto 0))='1') else '0';
s_nan_in <= '1' when s_nan_a='1' or s_nan_b='1' else '0';
s_nan_op <= '1' when (s_infa and s_infb)='1' and (s_opa_i(31) xor (s_fpu_op_i xor s_opb_i(31)) )='1' else '0'; -- inf-inf=Nan
s_nan_sign <= s_sign_i when (s_nan_a and s_nan_b)='1' else
s_opa_i(31) when s_nan_a='1' else
s_opb_i(31);
-- check if result is inexact;
s_lost <= or_reduce(s_fract_28_i(2 downto 0)) or or_reduce(s_fract_1(2 downto 0)) or or_reduce(s_fract_2(2 downto 0));
s_ine_o <= '1' when (s_lost or s_overflow)='1' and (s_infa or s_infb)='0' else '0';
s_overflow <='1' when (s_expr1_9(8) or s_expr2_9(8))='1' and (s_infa or s_infb)='0' else '0';
s_zero_fract <= '1' when s_zeros=27 and s_fract_28_i(27)='0' else '0'; -- '1' if fraction result is zero
process(s_sign_i, s_exp_2, s_fract_2, s_nan_in, s_nan_op, s_nan_sign, s_infa, s_infb, s_overflow, s_zero_fract)
begin
if (s_nan_in or s_nan_op)='1' then
s_output_o <= s_nan_sign & QNAN;
elsif (s_infa or s_infb)='1' or s_overflow='1' then
s_output_o <= s_sign_i & INF;
elsif s_zero_fract='1' then
s_output_o <= s_sign_i & ZERO_VECTOR;
else
s_output_o <= s_sign_i & s_exp_2 & s_fract_2(25 downto 3);
end if;
end process;
end rtl;
|
gpl-3.0
|
freecores/layer2
|
vhdl/cpu/rtl/mips1.vhd
|
1
|
10143
|
--------------------------------------------------------------------------------
-- MIPS I CPU - Instruction Set --
--------------------------------------------------------------------------------
-- Type definitions of the MIPS I instruction (sub-)set and some convenience --
-- functions to convert binary operation representations to symbolic --
-- equivalents. --
-- --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mips1 is
-----------------------------------------------------------------------------
-- OP Codes --
-----------------------------------------------------------------------------
type op_t is (
AD, -- Operations with AluOp
RI, -- Additional Branches
J, -- Jump
JAL, -- Jump And Link to $ra
BEQ, -- Branch On Equal
BNE, -- Branch On Not Equal
BLEZ, -- Branch Less Equal Zero
BGTZ, -- Branch Greater Than Zero
ADDI, -- Add Immediate
ADDIU, -- Add Immediate Unsigned
SLTI, -- SLT Immediate
SLTIU, -- SLT Immediate Unsigned
ANDI, -- And Immediate
ORI, -- Or Immediate
XORI, -- Xor Immediate
LUI, -- Load Upper Immediate
LB, -- Load Byte
LH, -- Load Half Word
LW, -- Load Word
LBU, -- Load Byte Unsigned
LHU, -- Load Half Word Unsigned
SB, -- Store Byte
SH, -- Store Half Word
SW, -- Store Word
CP0, -- Co-Processor 0 Operations
ERR -- Unknown OP
);
function op(i : std_logic_vector) return op_t;
-----------------------------------------------------------------------------
-- ALU OP Codes --
-----------------------------------------------------------------------------
-- In this implementation of the MIPS I instruction set, ADD, ADDU and --
-- SUB, SUBU cause indentical behaviour. This means that ADDU and SUBU do --
-- NOT trap on overflow. --
-----------------------------------------------------------------------------
type alu_op_t is (
ADD, -- Addition
ADDU, -- Add Unsigned
SUB, -- Subtraction
SUBU, -- Subtract Unsigned
AND0, -- Logic and
OR0, -- Logic or
NOR0, -- Logic nor
XOR0, -- Logic xor
SLT, -- Set On Less Than
SLTU, -- SLT Unsigned
SLL0, -- Shift Left Logical
SLLV, -- SLL Variable
SRA0, -- Shift Right Arith
SRAV, -- SRA Variable
SRL0, -- Shift Right Logical
SRLV, -- SRL Variable
JALR, -- Jump And Link Reg
JR, -- Jump Reg
MFCP0, -- Move From Co-Processor 0
MTCP0, -- Move To Co-Processor 0
RFE, -- Restore From Exception
ERR -- Unknown ALU OP
);
-- Convert ALU Op bit pattern into its symbolic representation.
function aluop(i : std_logic_vector) return alu_op_t;
-----------------------------------------------------------------------------
-- REGIMM Codes --
-----------------------------------------------------------------------------
type rimm_op_t is (
BGEZ, -- Branch Greater Equal 0
BGEZAL, -- BGEZ And Link
BLTZ, -- Branch Less Than 0
BLTZAL, -- BLTZ And Link
ERR -- Unknown RIMM OP
);
-- Convert Reg Immediate Op bit pattern into its symbolic representation.
function rimmop(i : std_logic_vector) return rimm_op_t;
-----------------------------------------------------------------------------
-- CP0 Codes --
-----------------------------------------------------------------------------
type cp0_op_t is (
MFCP0, -- Move From Co-Processor 0
MTCP0, -- Move To Co-Processor 0
RFE, -- Restore From Exception
ERR -- Unknown CP0 OP
);
type cp0_reg_t is (
SR, -- Status Register
CAUSE, -- Cause Register
EPC, -- EPC
ERR -- Unknown CP0 REG
);
-- Convert CP0 Op and Reg Addresses bit patterns into its symbolic
-- representation.
function cp0op(i : std_logic_vector) return cp0_op_t;
function cp0reg(i : std_logic_vector) return cp0_reg_t;
end mips1;
package body mips1 is
function op(i : std_logic_vector) return op_t is
begin
case i(31 downto 26) is
when "000000" => return AD; -- Operations with AluOp
when "000001" => return RI; -- Additional Branches
when "000010" => return J; -- Jump
when "000011" => return JAL; -- Jump And Link to $ra
when "000100" => return BEQ; -- Branch On Equal
when "000101" => return BNE; -- Branch On Not Equal
when "000110" => return BLEZ; -- Branch Less Equal Zero
when "000111" => return BGTZ; -- Branch Greater Than Zero
when "001000" => return ADDI; -- Add Immediate
when "001001" => return ADDIU; -- Add Immediate Unsigned
when "001010" => return SLTI; -- SLT Immediate
when "001011" => return SLTIU; -- SLT Immediate Unsigned
when "001100" => return ANDI; -- And Immediate
when "001101" => return ORI; -- Or Immediate
when "001110" => return XORI; -- Xor Immediate
when "001111" => return LUI; -- Load Upper Immediate
when "100000" => return LB; -- Load Byte
when "100001" => return LH; -- Load Half Word
when "100011" => return LW; -- Load Word
when "100100" => return LBU; -- Load Byte Unsigned
when "100101" => return LHU; -- Load Half Word Unsigned
when "101000" => return SB; -- Store Byte
when "101001" => return SH; -- Store Half Word
when "101011" => return SW; -- Store Word
when "010000" => return CP0; -- Co-Processor 0 Operations
when others => return ERR; -- Unknown OP
end case;
end op;
function aluop(i : std_logic_vector) return alu_op_t is
begin
case i(5 downto 0) is
when "100000" => return ADD; -- Addition
when "100001" => return ADDU; -- Add Unsigned
when "100010" => return SUB; -- Subtract
when "100011" => return SUBU; -- Subtract Unsigned
when "100100" => return AND0; -- Logic and
when "100101" => return OR0; -- Logic or
when "100111" => return NOR0; -- Logic nor
when "100110" => return XOR0; -- Logic xor
when "101010" => return SLT; -- Set On Less Than
when "101011" => return SLTU; -- SLT Unsigned
when "000000" => return SLL0; -- Shift Left Logical
when "000100" => return SLLV; -- SLL Variable
when "000011" => return SRA0; -- Shift Right Arith
when "000111" => return SRAV; -- SRA Variable
when "000010" => return SRL0; -- Shift Right Logical
when "000110" => return SRLV; -- SRL Variable
when "001001" => return JALR; -- Jump And Link Reg
when "001000" => return JR; -- Jump Reg
when others => return ERR; -- Unknown ALU OP
end case;
end aluop;
function rimmop(i : std_logic_vector) return rimm_op_t is
begin
case i(20 downto 16) is
when "00001" => return BGEZ; -- Branch Greater Equal 0
when "10001" => return BGEZAL; -- BGEZ And Link
when "00000" => return BLTZ; -- Branch Less Than 0
when "10000" => return BLTZAL; -- BLTZ And Link
when others => return ERR; -- Unknown RIMM OP
end case;
end rimmop;
function cp0op(i : std_logic_vector) return cp0_op_t is
begin
case i(25 downto 21) is
when "00000" => return MFCP0; -- Move From Co-Processor 0
when "00100" => return MTCP0; -- Move To Co-Processor 0
when "10000" => return RFE; -- Restore From Exception
when others => return ERR; -- Unknown CP0 OP
end case;
end cp0op;
function cp0reg(i : std_logic_vector) return cp0_reg_t is
begin
case i(4 downto 0) is
when "01100" => return SR; -- Status Register
when "01101" => return CAUSE; -- Cause Register
when "01110" => return EPC; -- EPC
when others => return ERR; -- Unknown CP0 REG
end case;
end cp0reg;
end mips1;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/fpulib.vhd
|
2
|
1833
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: fpulib
-- File: fpulib.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: package containing LEON
------------------------------------------------------------------------------
-- Version control:
-- 16-08-1999: First implemetation
-- 26-09-1999: Release 1.0
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package fpulib is
component fpu
port (
ss_clock : in clk_type;
FpInst : in std_logic_vector(9 downto 0);
FpOp : in std_logic;
FpLd : in std_logic;
Reset : in std_logic;
fprf_dout1 : in std_logic_vector(63 downto 0);
fprf_dout2 : in std_logic_vector(63 downto 0);
RoundingMode : in std_logic_vector(1 downto 0);
FpBusy : out std_logic;
FracResult : out std_logic_vector(54 downto 3);
ExpResult : out std_logic_vector(10 downto 0);
SignResult : out std_logic;
SNnotDB : out std_logic;
Excep : out std_logic_vector(5 downto 0);
ConditionCodes : out std_logic_vector(1 downto 0);
ss_scan_mode : in std_logic;
fp_ctl_scan_in : in std_logic;
fp_ctl_scan_out : out std_logic
);
end component;
end;
|
gpl-3.0
|
freecores/layer2
|
vhdl/intercon/rtl/intercon.vhd
|
1
|
7991
|
--------------------------------------------------------------------------------
-- Wishbone Shared Bus Intercon --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.icon.all;
use work.iwb.all;
entity intercon is
port(
CLK50_I : in std_logic;
CLK25_I : in std_logic;
RST_I : in std_logic;
mi : out master_in_t;
mo : in master_out_t;
brami : out slave_in_t;
bramo : in slave_out_t;
flasi : out slave_in_t;
flaso : in slave_out_t;
ddri : out slave_in_t;
ddro : in slave_out_t;
dispi : out slave_in_t;
dispo : in slave_out_t;
keybi : out slave_in_t;
keybo : in slave_out_t;
piti : out slave_in_t;
pito : in slave_out_t;
uartri : out slave_in_t;
uartro : in slave_out_t;
uartti : out slave_in_t;
uartto : in slave_out_t
);
end intercon;
architecture sbus of intercon is
-- Set default slave signals.
function setDefault(mo : master_out_t; CLK, RST : std_logic)
return slave_in_t is
variable v : slave_in_t;
begin
v.clk := CLK;
v.rst := RST;
v.stb := '0';
v.we := '0';
v.dat := mo.dat;
v.sel := mo.sel;
v.adr := mo.adr;
return v;
end setDefault;
begin
mux : process(CLK50_I, RST_I, mo, bramo, dispo, keybo, pito, flaso, uartro,
uartto, ddro, CLK25_I)
variable padr : std_logic_vector(27 downto 0);
begin
mi.clk <= CLK50_I;
mi.rst <= RST_I;
mi.dat <= (others => '0');
-- NOTE: Set mi.ack = '1' if you want to continue execution outside the
-- valid address space. If set to zero and your programm reads or
-- writes outside the specified addresses the cpu waits infinitly
-- for an acknolege.
mi.ack <= '0';
brami <= setDefault(mo, CLK50_I, RST_I);
flasi <= setDefault(mo, CLK50_I, RST_I);
ddri <= setDefault(mo, CLK50_I, RST_I);
dispi <= setDefault(mo, CLK50_I, RST_I);
keybi <= setDefault(mo, CLK50_I, RST_I);
piti <= setDefault(mo, CLK50_I, RST_I);
uartri <= setDefault(mo, CLK50_I, RST_I);
uartti <= setDefault(mo, CLK50_I, RST_I);
padr := mo.adr(27 downto 0);
case mo.adr(31 downto 28) is
-----------------------------------------------------------------------
-- Block Memory --
-----------------------------------------------------------------------
when X"0" =>
-- if (padr >= X"0000000") and (padr < X"0004000") then
brami.stb <= mo.stb;
brami.we <= mo.we;
mi.dat <= bramo.dat;
mi.ack <= bramo.ack;
-- end if;
-----------------------------------------------------------------------
-- Flash Memory --
-----------------------------------------------------------------------
when X"1" =>
--if (padr >= X"0000000") and (padr < X"1000000") then
flasi.stb <= mo.stb;
flasi.we <= mo.we;
mi.dat <= flaso.dat;
mi.ack <= flaso.ack;
--end if;
-----------------------------------------------------------------------
-- DDR2 Memory --
-----------------------------------------------------------------------
when x"2" =>
ddri.stb <= mo.stb;
ddri.we <= mo.we;
mi.dat <= ddro.dat;
mi.ack <= ddro.ack;
-----------------------------------------------------------------------
-- Peripheral IO --
-----------------------------------------------------------------------
when X"F" =>
--------------------------------------------------------------------
-- Display --
--------------------------------------------------------------------
-- 4096 blocks, 16bit per block = 8192 (0x2000)
if (padr >= X"FFF0000") and (padr < X"FFF2000") then
dispi.stb <= mo.stb;
dispi.we <= mo.we;
mi.dat <= dispo.dat;
mi.ack <= dispo.ack;
-- NOTE: The following addresses are strict. If you try to load or
-- store a halfword or a byte, the addresses obviously do NOT
-- match.
--------------------------------------------------------------------
-- Keyboard --
--------------------------------------------------------------------
-- 1 block, 32bit, read only
elsif padr = X"FFF3000" then
keybi.stb <= mo.stb;
keybi.we <= mo.we;
mi.dat <= keybo.dat;
mi.ack <= keybo.ack;
--------------------------------------------------------------------
-- RS-232 Serial Port --
--------------------------------------------------------------------
-- 1 block, 32bit, read only
elsif padr = X"FFF4000" then
uartri.stb <= mo.stb;
uartri.we <= mo.we;
mi.dat <= uartro.dat;
mi.ack <= uartro.ack;
-- 1 block, 32bit, write only
elsif padr = X"FFF4004" then
uartti.stb <= mo.stb;
uartti.we <= mo.we;
mi.dat <= uartto.dat;
mi.ack <= uartto.ack;
--------------------------------------------------------------------
-- Timer --
--------------------------------------------------------------------
-- 1 block, 32bit, r/w
elsif padr = X"FFFF000" then
piti.stb <= mo.stb;
piti.we <= mo.we;
mi.dat <= pito.dat;
mi.ack <= pito.ack;
end if;
when others =>
end case;
end process;
end sbus;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/VFLOAT_2015/General Modules/parameterized modules/parameterized_absolute_value/parameterized_absolute_value.vhd
|
1
|
4625
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- RAPID PROTOTYPING LABORATORY --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 29 Sep. 2013 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized Absolute Value --
----------------------------------------------------------
entity parameterized_absolute_value is
generic
(
bits : integer:= 0
);
port
(
--inputs
IN1 : in std_logic_vector(bits-1 downto 0);
--outputs
EXC : out std_logic:= '0';
OUT1 : out std_logic_vector(bits-1 downto 0):= (others=>'0')
);
end parameterized_absolute_value;
----------------------------------------------------------
-- Parameterized Absolute Value --
----------------------------------------------------------
architecture parameterized_absolute_value_arch of parameterized_absolute_value is
signal not_in1 : std_logic_vector(bits-1 downto 0) := (others=>'0');
signal sum : std_logic_vector(bits-1 downto 0) := (others=>'0');
signal one : std_logic_vector(bits-1 downto 0) := (others=>'0');
signal cout : std_logic := '0';
begin
--set up signals
one(0) <= '1';
one(bits-1 downto 1) <= (others=>'0');
not_in1 <= NOT(IN1);
--adder
adder : parameterized_adder
generic map
(
bits => bits
)
port map
(
A => not_in1,
B => one,
CIN => '0',
S => sum,
COUT => cout
);
--AND
EXC <= IN1(bits-1) AND sum(bits-1);
--output mux
mux : parameterized_mux
generic map
(
bits => bits
)
port map
(
A => sum,
B => IN1,
S => IN1(bits-1),
O => OUT1
);
end parameterized_absolute_value_arch; -- end of architecture
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/div.vhd
|
3
|
5282
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: div
-- File: div.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a divide unit to execute the
-- UDIV/SDIV instructions. Divide leaves Y
-- register intact but does not produce a remainder.
-- Overflow detection is performed according to the
-- SPARC V8 manual, method B (page 116)
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.config.all;
use work.iface.all;
entity div is
port (
rst : in std_logic;
clk : in clk_type;
holdn : in std_logic;
divi : in div_in_type;
divo : out div_out_type
);
end;
architecture rtl of div is
type div_regtype is record
x : std_logic_vector(64 downto 0);
state : std_logic_vector(2 downto 0);
zero : std_logic;
zero2 : std_logic;
qzero : std_logic;
qmsb : std_logic;
ovf : std_logic;
neg : std_logic;
cnt : std_logic_vector(4 downto 0);
end record;
signal r, rin : div_regtype;
signal addin1, addin2, addout: std_logic_vector(32 downto 0);
signal addsub : std_logic;
begin
divcomb : process (r, rst, divi, addout)
variable v : div_regtype;
variable vready : std_logic;
variable vaddin1, vaddin2, vaddout: std_logic_vector(32 downto 0);
variable vaddsub, ymsb, remsign : std_logic;
constant Zero: std_logic_vector(32 downto 0) := "000000000000000000000000000000000";
begin
vready := '0'; v := r;
if addout = Zero then v.zero := '1'; else v.zero := '0'; end if;
v.zero2 := r.zero;
remsign := '0';
vaddin1 := r.x(63 downto 31); vaddin2 := divi.op2;
vaddsub := not (divi.op2(32) xor r.x(64));
case r.state is
when "000" =>
v.cnt := "00000";
if (divi.start = '1') then
v.x(64) := divi.y(32); v.state := "001";
end if;
when "001" =>
v.x := divi.y & divi.op1(31 downto 0);
v.neg := divi.op2(32) xor divi.y(32);
if divi.signed = '1' then
vaddin1 := divi.y(31 downto 0) & divi.op1(31);
v.ovf := not (addout(32) xor divi.y(32));
else
vaddin1 := divi.y; vaddsub := '1';
v.ovf := not addout(32);
end if;
v.state := "010";
when "010" =>
if ((divi.signed and r.neg and r.zero) = '1') and (divi.op1 = Zero) then v.ovf := '0'; end if;
v.qmsb := vaddsub; v.qzero := '1';
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
v.state := "011";
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
when "011" =>
v.qzero := r.qzero and (vaddsub xor r.qmsb);
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
if (r.cnt = "11111") then v.state := "100"; else
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
when others =>
vaddin1 := ((not r.x(31)) & r.x(30 downto 0) & '1');
vaddsub := r.x(31); vaddin2 := (others => '0'); vaddin2(0) := '1';
remsign := r.x(64) xor divi.op2(32);
if (r.zero = '0') and ( ((divi.signed = '0') and (r.x(64) /= r.neg)) or
((divi.signed = '1') and (remsign /= r.neg)) or (r.zero2 = '1'))
then
v.x(64 downto 32) := addout;
else
v.x(64 downto 32) := vaddin1; v.qzero := '0';
end if;
if (r.ovf = '1') then
v.x(63 downto 32) := (others => '1');
if divi.signed = '1' then
if r.neg = '1' then v.x(62 downto 32) := (others => '0');
else v.x(63) := '0'; end if;
end if;
end if;
vready := '1';
v.state := "000";
end case;
divo.icc <= r.x(63) & r.qzero & r.ovf & '0';
if (rst = '0') or (divi.flush = '1') then v.state := "000"; end if;
rin <= v;
divo.ready <= vready;
divo.result(31 downto 0) <= r.x(63 downto 32);
addin1 <= vaddin1; addin2 <= vaddin2; addsub <= vaddsub;
end process;
divadd : process(addin1, addin2, addsub)
variable b : std_logic_vector(32 downto 0);
begin
if addsub = '1' then b := not addin2; else b := addin2; end if;
-- pragma translate_off
if not (is_x(addin1 & b & addsub)) then
-- pragma translate_on
addout <= addin1 + b + addsub;
-- pragma translate_off
else
addout <= (others => 'X');
end if;
-- pragma translate_on
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then r <= rin; end if;
end if;
end process;
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/div.vhd
|
3
|
5282
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: div
-- File: div.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: This unit implemets a divide unit to execute the
-- UDIV/SDIV instructions. Divide leaves Y
-- register intact but does not produce a remainder.
-- Overflow detection is performed according to the
-- SPARC V8 manual, method B (page 116)
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use work.config.all;
use work.iface.all;
entity div is
port (
rst : in std_logic;
clk : in clk_type;
holdn : in std_logic;
divi : in div_in_type;
divo : out div_out_type
);
end;
architecture rtl of div is
type div_regtype is record
x : std_logic_vector(64 downto 0);
state : std_logic_vector(2 downto 0);
zero : std_logic;
zero2 : std_logic;
qzero : std_logic;
qmsb : std_logic;
ovf : std_logic;
neg : std_logic;
cnt : std_logic_vector(4 downto 0);
end record;
signal r, rin : div_regtype;
signal addin1, addin2, addout: std_logic_vector(32 downto 0);
signal addsub : std_logic;
begin
divcomb : process (r, rst, divi, addout)
variable v : div_regtype;
variable vready : std_logic;
variable vaddin1, vaddin2, vaddout: std_logic_vector(32 downto 0);
variable vaddsub, ymsb, remsign : std_logic;
constant Zero: std_logic_vector(32 downto 0) := "000000000000000000000000000000000";
begin
vready := '0'; v := r;
if addout = Zero then v.zero := '1'; else v.zero := '0'; end if;
v.zero2 := r.zero;
remsign := '0';
vaddin1 := r.x(63 downto 31); vaddin2 := divi.op2;
vaddsub := not (divi.op2(32) xor r.x(64));
case r.state is
when "000" =>
v.cnt := "00000";
if (divi.start = '1') then
v.x(64) := divi.y(32); v.state := "001";
end if;
when "001" =>
v.x := divi.y & divi.op1(31 downto 0);
v.neg := divi.op2(32) xor divi.y(32);
if divi.signed = '1' then
vaddin1 := divi.y(31 downto 0) & divi.op1(31);
v.ovf := not (addout(32) xor divi.y(32));
else
vaddin1 := divi.y; vaddsub := '1';
v.ovf := not addout(32);
end if;
v.state := "010";
when "010" =>
if ((divi.signed and r.neg and r.zero) = '1') and (divi.op1 = Zero) then v.ovf := '0'; end if;
v.qmsb := vaddsub; v.qzero := '1';
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
v.state := "011";
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
when "011" =>
v.qzero := r.qzero and (vaddsub xor r.qmsb);
v.x(64 downto 32) := addout;
v.x(31 downto 0) := r.x(30 downto 0) & vaddsub;
if (r.cnt = "11111") then v.state := "100"; else
-- pragma translate_off
if not is_x(r.cnt) then
-- pragma translate_on
v.cnt := r.cnt + 1;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
when others =>
vaddin1 := ((not r.x(31)) & r.x(30 downto 0) & '1');
vaddsub := r.x(31); vaddin2 := (others => '0'); vaddin2(0) := '1';
remsign := r.x(64) xor divi.op2(32);
if (r.zero = '0') and ( ((divi.signed = '0') and (r.x(64) /= r.neg)) or
((divi.signed = '1') and (remsign /= r.neg)) or (r.zero2 = '1'))
then
v.x(64 downto 32) := addout;
else
v.x(64 downto 32) := vaddin1; v.qzero := '0';
end if;
if (r.ovf = '1') then
v.x(63 downto 32) := (others => '1');
if divi.signed = '1' then
if r.neg = '1' then v.x(62 downto 32) := (others => '0');
else v.x(63) := '0'; end if;
end if;
end if;
vready := '1';
v.state := "000";
end case;
divo.icc <= r.x(63) & r.qzero & r.ovf & '0';
if (rst = '0') or (divi.flush = '1') then v.state := "000"; end if;
rin <= v;
divo.ready <= vready;
divo.result(31 downto 0) <= r.x(63 downto 32);
addin1 <= vaddin1; addin2 <= vaddin2; addsub <= vaddsub;
end process;
divadd : process(addin1, addin2, addsub)
variable b : std_logic_vector(32 downto 0);
begin
if addsub = '1' then b := not addin2; else b := addin2; end if;
-- pragma translate_off
if not (is_x(addin1 & b & addsub)) then
-- pragma translate_on
addout <= addin1 + b + addsub;
-- pragma translate_off
else
addout <= (others => 'X');
end if;
-- pragma translate_on
end process;
reg : process(clk)
begin
if rising_edge(clk) then
if (holdn = '1') or GATEDCLK then r <= rin; end if;
end if;
end process;
end;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/VFLOAT_2015/General Modules/parameterized modules/parameterized_subtractor.vhd
|
3
|
3962
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
entity parameterized_subtractor is
generic
(
bits : integer := 0
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
B : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic_vector(bits-1 downto 0) := (others=>'0')
);
end parameterized_subtractor;
----------------------------------------------------------
-- Parameterized subtractor --
----------------------------------------------------------
architecture parameterized_subtractor_arch of parameterized_subtractor is
begin
--subtraction
O <= A - B;
end parameterized_subtractor_arch; -- end of architecture
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/MILK_2007/src/cop_definitions.vhd
|
1
|
10454
|
-----------------------------------------------------------------------------------------------------------
--
-- MILK COPROCESSOR BASIC DEFINITIONS
--
-- This file contains basic parameters definitions.
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------------
--Copyright (c) 2004, Tampere University of Technology.
--All rights reserved.
--Redistribution and use in source and binary forms, with or without modification,
--are permitted provided that the following conditions are met:
--* Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--* Neither the name of Tampere University of Technology nor the names of its
-- contributors may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
--CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND
--FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
--OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
--EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
--PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN
--IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package cop_definitions is
-----------------------------------------------------------------------------------------------------------
--
-- bus width configuration
--
-----------------------------------------------------------------------------------------------------------
constant word_width : positive := 32; -- data bus width
constant sreg_width : positive := 14; -- status register width
constant buffer_width : positive := 32; -- RF output tristate buffers width
constant RF_width : positive := 8; -- number of general purpose registers
constant instr_word_width : positive := 24; -- amount of significative bits loaded in control register
constant exceptions_amount : positive := 22; -- overall number of "internal" exceptions
constant RF_exceptions_amount : positive := 1; -- number of "internal" exceptions related to the register file
constant flags_amount : positive := 7; -- number of status flag bits
constant cop_opcode_width : positive := 6; -- amount of bits of the "opcode" field of the instruction word
-----------------------------------------------------------------------------------------------------------
--
-- ctrl_logic configuration
--
-----------------------------------------------------------------------------------------------------------
constant wrbck_sgls_width : positive := 8; -- wrbck signals set in ctrl_logic
constant m : positive := 12; -- amount of sub-buses in the register delay chain (ctrl_logic)
constant n : positive := 3; -- width of sub-buses in the register delay chain (ctrl_logic)
constant conv_clk_cycles : positive := 2; -- latency (in clk cycles) required by conv
constant trunc_clk_cycles : positive := 2; -- latency (in clk cycles) required by trunc
constant mul_clk_cycles : positive := 3; -- latency (in clk cycles) required by mul
constant div_clk_cycles : positive := 12; -- latency (in clk cycles) required by div
constant add_clk_cycles : positive := 5; -- latency (in clk cycles) required by add
constant sqrt_clk_cycles : positive := 8; -- latency (in clk cycles) required by sqrt
-----------------------------------------------------------------------------------------------------------
--
-- main constants
--
-----------------------------------------------------------------------------------------------------------
constant reset_active : Std_logic := '1'; -- '1' -> positive logic
constant we_active : Std_logic := '1';
constant oe_active : Std_logic := '1';
constant ovfw_active : Std_logic := '1';
constant underfw_active : Std_logic := '1';
-----------------------------------------------------------------------------------------------------------
--
-- FUs insertion generics' boolean values
--
-----------------------------------------------------------------------------------------------------------
constant conv_flag_value : integer := 1;
constant trunc_flag_value : integer := 1;
constant mul_flag_value : integer := 1;
constant div_flag_value : integer := 1;
constant add_flag_value : integer := 1;
constant sqrt_flag_value : integer := 1;
constant compare_flag_value : integer := 1;
-----------------------------------------------------------------------------------------------------------
--
-- "integer_sqrt" block configuration constants
--
-----------------------------------------------------------------------------------------------------------
constant radicand_width : positive := 52; -- operand width
constant sqrt_width : positive := 26; -- result width
constant rem_width : positive := 28; -- remainder width
constant k_max : positive := 26; -- number of "iterations" in the algorithm
-----------------------------------------------------------------------------------------------------------
--
-- "integer_divider" block configuration constants
--
-----------------------------------------------------------------------------------------------------------
constant dividend_width : positive := 24; -- operand width
constant divisor_width : positive := 24; -- operand width
constant quotient_width : positive := 25; -- result width
constant division_rem_width : positive := 25; -- remainder width
constant div_k_max : positive := 25; -- number of "iterations" in the algorithm
type bus_8Xd is array (8 downto 0) of std_logic_vector(divisor_width+1 downto 0);
-----------------------------------------------------------------------------------------------------------
--
-- user defined types
--
-----------------------------------------------------------------------------------------------------------
type bus8X32 is array (RF_width-1 downto 0) of std_logic_vector(word_width-1 downto 0);
type bus_mXn is array (m downto 0) of std_logic_vector(n-1 downto 0);
subtype rf_addr is std_logic_vector(2 downto 0); -- RF registers' address bits
subtype wb_code is std_logic_vector(3 downto 0); -- result writeback logic's "indexing" bits
subtype cop_opcode is std_logic_vector(cop_opcode_width-1 downto 0); -- opcode specification bits
-----------------------------------------------------------------------------------------------------------
--
-- instruction set mnemonics
--
-----------------------------------------------------------------------------------------------------------
-- opcodes are the same as those in the MIPS' coprocessor instruction set
constant cop_add_s : cop_opcode := "000000"; -- adds two FP single precision numbers : ADD.S
constant cop_sub_s : cop_opcode := "000001"; -- subtracts two FP single precision numbers : SUB.S
constant cop_mul_s : cop_opcode := "000010"; -- multiplies two FP single precision numbers : MUL.S
constant cop_div_s : cop_opcode := "000011"; -- divides two FP single precision numbers : DIV.S
constant cop_sqrt_s : cop_opcode := "000100"; -- extracts the square root of a FP single precision number : SQRT.S
constant cop_abs_s : cop_opcode := "000101"; -- extracts the absolute value of a FP single precision number : ABS.S
constant cop_mov_s : cop_opcode := "000110"; -- moves a value from a register to another : MOV.S
constant cop_neg_s : cop_opcode := "000111"; -- inverts the sign of a single precision FP number : NEG.S
constant nop : cop_opcode := "001000"; -- no operation executed : NOP.S
constant cop_trunc_w : cop_opcode := "001101";
constant cop_cvt_s : cop_opcode := "100000"; -- converts an integer into a single precision FP : CVT.S
constant cop_cvt_w : cop_opcode := "100100"; -- converts a single precision FP into an integer : CVT.W
-- Note: the comparison is obtained through a set of 16 sub-instructions whose opcodes are charaterized by the two
-- most-significant bits set
------------------------------------------------------------------------------------------------------------
--
-- result writeback selection signals
--
------------------------------------------------------------------------------------------------------------
constant wb_cvt_s : wb_code := "0000";
constant wb_trunc_w : wb_code := "0001";
constant wb_mul_s : wb_code := "0010";
constant wb_div_s : wb_code := "0011";
constant wb_addsub_s : wb_code := "0100";
constant wb_sqrt_s : wb_code := "0101";
constant wb_abs_s : wb_code := "0110";
constant wb_mov_s : wb_code := "0111";
constant wb_neg_s : wb_code := "1000";
constant wb_compare_s : wb_code := "1001";
end cop_definitions ;
package body cop_definitions is
end cop_definitions;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.3.7/leon/pci_arb.vhd
|
3
|
18377
|
--============================================================================--
-- Design unit : Package pci_arb_pkg, entity pci_arb
--
-- File name : pci_arb.vhd
--
-- Purpose : Arbiter for the PCI bus
-- - configurable size: 4, 8, 16, 32 agents
-- - round-robbing in configurable (up to 4) priority levels
-- - priority assignment hard-coded or APB-programmable
--
--
-- Reference : PCI Local Bus Specification, Revision 2.1,
-- PCI Special Interest Group, 1st June 1995
-- (for information: http:
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http:
--
-- Note : All the numbering referring to the different PCI agents,
-- such as arrays for req_n, gnt_n, or priority levels is in
-- increasing order <0 = left> to <NUMBER-1 = right>.
-- APB data/address arrays are in the conventional order:
-- The least significant bit is located to the
-- right, carrying the lower index number (usually 0).
--
-- Configuration: The arbiter is configurable by the constants ARB_SIZE and
-- ARB_LEVELS in pci_arb_pkg. ARB_SIZE is the log dualis (ld)
-- of the number of agents, which can be connected to the bus.
-- Values 2, 3, 4, 5 result in NB_AGENTS = 4, 8, 16 or 32.
-- ARB_LEVELS specifies the number of arbitration levels,
-- according to algorithm described below. The value should
-- not exceed 4, to prevent excessive synthesis areas.
-- The priority levels are hard-coded, when APB_PRIOS = false.
-- In this case, the APB ports (pbi/pbo) are unconnected.
-- When APB_PRIOS = true, the levels are programmable via APB.
-- Note: The combination of ARB_LEVELS = 4, ARB_SIZE = 5 with
-- programmable priorities leads to an excessively large
-- arbiter and problems making timing - it should be avoided.
--
-- Algorithm : The algorithm is described in the implementation note of
-- section 3.4 of the PCI standard:
-- The bus is granted by a configurable multi-level and round-
-- robbing algorithm. An agent number and an arbitration level
-- is assigned to each agent. The agent number determines,
-- which pair of req_n/gnt_n lines the agent uses. Agents
-- are counted from 0 to NB_AGENTS-1.
-- All agents in one level have equal access to the bus
-- (round-robbing); all agents of level N+1 as a group have
-- equal access as each agent of the next higher level N.
-- Re-arbitration occurs, when frame_n is asserted, as soon
-- as any other master has requested the bus, but only
-- once per transaction.
--
-- Prioriy levels: Priority levels are numbered starting from 0 (highest
-- priority) to ARB_LEVELS-1 (lowest priority).
-- Agent NB_AGENTS-1 is always in the group ARB_LEVELS-1.
-- Agents 0 to NB_AGENTS-2 can be assigned in any order to a
-- level between 0 and ARB_LEVELS-1, fixed or programmable:
-- a) APB_PRIOS = false: Fixed, hard-coded priorities for the
-- different devices. A priority level is assigned to each
-- device by the constant ARB_LVL_C in pci_arb_pkg.
-- b) With programmable priorities. The priority level of all
-- agents (except NB_AGENTS-1) is programmable via APB.
-- In a 256 byte APB address range, the priority level of
-- agent N is accessed via the address 0x80 + 4*N. The APB
-- slave returns 0 on all non-implemented addresses, the
-- address bits (1:0) are not decoded. Since only addresses
-- >= 0x80 are occupied, it can be used in parallel (ored
-- read data) with our PCI interface (uses <= 0x78).
-- The constant ARB_LVL_C in pci_arb_pkg is the reset value.
--
-- Timeout: The "broken master" timeout is another reason for
-- re-arbitration (section 3.4.1 of the standard). Grant is
-- removed from an agent, which has not started a cycle
-- within 16 cycles after request (and grant). Reporting of
-- such a 'broken' master is not implemented.
--
-- Turnover: A turnover cycle is required by the standard, when re-
-- arbitration occurs during idle state of the bus.
-- Notwithstanding to the standard, "idle state" is assumed,
-- when frame_n is high for more than 1 cycle.
--
-- Bus parking : The bus is parked to agent 0 after reset, it remains granted
-- to the last owner, if no other agent requests the bus.
-- When another request is asserted, re-arbitration occurs
-- after one turnover cycle.
--
-- Lock : Lock is defined as a resource lock by the PCI standard.
-- The optional bus lock mentioned in the standard is not
-- considered here and there are no special conditions to
-- handle when lock_n is active.
-- in arbitration.
--
-- Latency : Latency control in PCI is via the latency counters of each
-- agent. The arbiter does not perform any latency check and
-- a once granted agent continues its transaction until its
-- grant is removed AND its own latency counter has expired.
-- Even though, a bus re-arbitration occurs during a
-- transaction, the hand-over only becomes effective,
-- when the current owner deasserts frame_n.
--
-- Limitations : [add here known bugs and limitations]
--
-- Library : work
--
-- Dependencies : package pci_arb_pkg (contained in this file)
-- package amba, can be retrieved from:
-- http:
--
-- Author : Roland Weigand <[email protected]>
-- European Space Agency (ESA)
-- Microelectronics Section (TOS-ESM)
-- P.O. Box 299
-- NL-2200 AG Noordwijk ZH
-- The Netherlands
--
-- Contact : mailto:[email protected]
-- http:
--
-- Copyright (C): European Space Agency (ESA) 2000.
-- This source code is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2 of the License, or (at your option) any
-- later version. For full details of the license see file
-- http:
--
-- It is recommended that any use of this VHDL source code is
-- reported to the European Space Agency. It is also recommended
-- that any use of the VHDL source code properly acknowledges the
-- European Space Agency as originator.
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit. This information does not
-- necessarily reflect the policy of the European Space Agency.
--
-- Simulator : Modelsim 5.4 on PC + Windows 95
--
-- Synthesis : Synopsys Version 1999.10 on Sparc + Solaris 5.5.1
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.0 R.Weigand 2000/11/02 File created
-- 0.1 J.Gaisler 2001/04/10 Integrated in LEON
-- 0.2 R. Weigand 2001/04/25 Connect arb_lvl reg to AMBA clock/reset
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
package pci_arb_pkg is
-- The number of agents can be only 4, 8, 16, 32
-- constant ARB_SIZE : natural range 2 to 5 := 2; -- (4, 8, 16, 32) devices
-- constant ARB_LEVELS : positive range 1 to 4 := 2; -- arbitration levels
-- constant APB_PRIOS : boolean := true; -- true: levels programmable via APB
-- constant NB_AGENTS : natural range 3 to 32 := 2**ARB_SIZE; -- Nb. of PCI agents
subtype agent_t is natural range 0 to NB_AGENTS-1;
subtype level_t is natural range 0 to ARB_LEVELS-1;
type owner_t is array (0 to ARB_LEVELS-1) of agent_t; -- last owner of each level
type arb_lvl_t is array (0 to NB_AGENTS-2) of level_t;
-- Note: the agent with the highest index (3, 7, 15, 31) is always in the
-- arbitration level with the highest index!!
constant ARB_LVL_C : arb_lvl_t := ( -- default values for arb-level
others => 0 -- default is zero
);
constant all_ones : std_logic_vector(0 to NB_AGENTS-1) := (others => '1');
end pci_arb_pkg;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.conv_integer;
use IEEE.std_logic_arith.all;
use work.pci_arb_pkg.all;
use work.config.all;
use work.amba.all;
use work.iface.all;
entity pci_arb is
port (clk : in std_logic ; -- clock
rst_n : in std_logic; -- async reset active low
req_n : in std_logic_vector(0 to NB_AGENTS-1); -- bus request
frame_n : in std_logic;
gnt_n : out std_logic_vector(0 to NB_AGENTS-1); -- bus grant
pclk : in clk_type; -- APB clock
prst_n : in std_logic; -- APB reset
pbi : in APB_Slv_In_Type; -- APB inputs
pbo : out APB_Slv_Out_Type -- APB outputs
);
end pci_arb;
-- purpose: PCI arbiter
architecture rtl of pci_arb is
signal owner, owneri : owner_t; -- current owner per level
signal cown, cowni : agent_t; -- current level
signal rearb, rearbi : std_logic; -- re-arbitration flag
signal tout, touti : natural range 0 to 15 := 0; -- timeout counter
signal turn, turni : std_logic; -- turnaround cycle
signal arb_lvl, arb_lvli : arb_lvl_t := ARB_LVL_C; -- level registers
begin -- rtl
----------------------------------------------------------------------------
-- PCI ARBITER
----------------------------------------------------------------------------
-- purpose: Grants the bus depending on the request signals. All agents have
-- equal priority, if another request occurs during a transaction, the bus is
-- granted to the new agent. However, PCI protocol specifies that the master
-- can finish the current transaction within the limit of its latency timer.
arbiter : process(cown, owner, req_n, rearb, tout, turn, frame_n, arb_lvl)
variable new_request : integer := 0; -- detected request
-- Find the next request to be serviced (found)
-- + update the current owner array (owneri)
-- If no request is asserted, found := NB_AGENTS
procedure find_next (signal owner : in owner_t;
level : in level_t;
signal req_n : in std_logic_vector(0 to NB_AGENTS-1);
signal owneri : out owner_t;
variable found : out natural range 0 to NB_AGENTS
) is
variable higher, lower: natural range 0 to NB_AGENTS;
begin -- find_next
higher := NB_AGENTS;
lower := NB_AGENTS;
rob : for i in 0 to NB_AGENTS-2 loop
-- find next request with index > current owner, same prio level
if i > owner(level) then
if higher = NB_AGENTS and req_n(i) = '0' and arb_lvl(i) = level then
higher := i; -- select new agent > current
found := i;
owneri(level) <= i;
end if;
-- find next request with index <= current owner
else
if lower = NB_AGENTS and req_n(i) = '0' and arb_lvl(i) = level then
lower := i; -- select new agent <= current
found := i; -- overridden, if a 'higher' is foun
owneri(level) <= i; -- overridden, if a 'higher' is found
end if;
end if;
end loop rob;
-- different processing for the last device (NB_AGENTS-1):
-- If not in leaf level: step down to next level
if higher = NB_AGENTS and owner(level) /= NB_AGENTS-1 then
-- If Not in leaf level: step down to next level
if level < ARB_LEVELS-1 then
find_next(owner, level+1, req_n, owneri, higher);
if higher /= NB_AGENTS then
owneri(level) <= NB_AGENTS-1; -- found in next level
end if;
elsif req_n(NB_AGENTS-1) = '0' then
-- NB_AGENTS-1 has automatically the lowest prio level
found := NB_AGENTS-1; -- select new agent > current
owneri(level) <= NB_AGENTS-1;
end if;
end if;
if higher = NB_AGENTS then -- round robbing wrapped
found := lower;
else
found := higher; -- next in line
end if;
end find_next;
begin -- process arbiter
-- default assignments
rearbi <= rearb;
owneri <= owner;
cowni <= cown;
touti <= tout;
turni <= '0'; -- no turnaround
-- re-arbitrate once during the transaction,
-- or when timeout counter expired (bus idle).
if (frame_n = '0' and rearb = '0') or turn = '1' then
-- determine next owner: recursive procedure,
-- start search at arbitration level 0
find_next(owner, 0, req_n, owneri, new_request);
-- rearbitration if any request asserted & different from current owner
if new_request /= NB_AGENTS and cown /= new_request then
-- if idle state: turnaround cycle required by PCI standard
cowni <= new_request;
touti <= 0; -- reset timeout counter
if turn = '0' then
rearbi <= '1'; -- only one re-arbitration
end if;
end if;
elsif frame_n = '1' then
rearbi <= '0';
end if;
-- if frame deasserted, but request asserted: count timeout
if req_n = all_ones then -- no request: prepare timeout counter
touti <= 15;
elsif frame_n = '1' then -- request, but no transaction
if tout = 15 then -- timeout expired, re-arbitrate
turni <= '1'; -- remove grant, turnaround cycle
touti <= 0; -- next cycle re-arbitrate
else
touti <= tout + 1;
end if;
end if;
grant : for i in 0 to NB_AGENTS-1 loop
if i = cown and turn = '0' then
gnt_n(i) <= '0';
else
gnt_n(i) <= '1';
end if;
end loop grant;
end process arbiter;
fixed_prios : if not APB_PRIOS generate
arb_lvl <= ARB_LVL_C; -- assign constant value
end generate fixed_prios;
-- Generate APB regs and APB slave
apbgen : if APB_PRIOS generate
-- purpose: APB read and write of arb_lvl configuration registers
-- type: memoryless
-- inputs: pbi, arb_lvl
-- outputs: pbo, arb_lvli
config : process (pbi, arb_lvl)
variable arblvl : unsigned(31 downto 0);
begin -- process config
arb_lvli <= arb_lvl;
pbo.PRDATA <= (others => '0'); -- default for unimplemented addresses
-- register select at (byte-) addresses 0x80 + 4*i
if pbi.PADDR(7) = '1' and pbi.PSEL = '1' then -- address select
wrloop : for i in 0 to NB_AGENTS-2 loop
if (pbi.PWRITE and pbi.PENABLE) = '1' and -- APB write
i = conv_integer(pbi.PADDR(6 downto 2)) then
arb_lvli(i) <= conv_integer(pbi.PWDATA(1 downto 0));
end if;
end loop wrloop;
rdloop : for i in 0 to NB_AGENTS-2 loop
if i = conv_integer(pbi.PADDR(6 downto 2)) then
arblvl := conv_unsigned(arb_lvl(i), 32);
pbo.PRDATA <= std_logic_vector(arblvl);
end if;
end loop rdloop;
end if;
end process config;
-- purpose: registers
-- type: memorizing
apb_regs : process (pclk, prst_n)
begin -- process regs
-- activities triggered by asynchronous reset (active low)
if prst_n = '0' then
arb_lvl <= ARB_LVL_C; -- assign default value
-- activities triggered by rising edge of clock
elsif pclk'event and pclk = '1' then -- '
arb_lvl <= arb_lvli;
end if;
end process apb_regs;
end generate apbgen;
-- purpose: registers
-- type: memorizing
regs0 : process (clk, rst_n)
begin -- process regs
-- activities triggered by asynchronous reset (active low)
if rst_n = '0' then
tout <= 0;
cown <= 0;
owner <= (others => 0);
rearb <= '0';
turn <= '0';
-- activities triggered by rising edge of clock
elsif clk'event and clk = '1' then -- '
tout <= touti;
owner <= owneri;
cown <= cowni;
rearb <= rearbi;
turn <= turni;
end if;
end process regs0;
end rtl;
|
gpl-3.0
|
freecores/layer2
|
vhdl/rs232/rtl/iuart.vhd
|
1
|
3367
|
--------------------------------------------------------------------------------
-- UART Transceiver 19200/8N1 --
--------------------------------------------------------------------------------
-- This minimal implementation of an Universal Asynchronous Receiver and --
-- Transmitter (UART) suits a baud rate of 19200 baud/sec as well as 8 bits --
-- of data, no parity bit and one stop bit configuration only. It comprises --
-- two seperate baud generators to receive and transmit simultanously. --
-- --
-- REFERENCES --
-- --
-- [1] Chu Pong P., FPGA Prototyping By VHDL Examples, --
-- John Wiley & Sons Inc., Hoboken, New Jersy, 2008, --
-- ISBN: 978-0470185315 --
-- --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iwb.all;
package iuart is
component uartr is
port(
si : in slave_in_t;
so : out slave_out_t;
-- Non-Wishbone Signals
RS232_DCE_RXD : in std_logic
);
end component;
component uartt is
port(
si : in slave_in_t;
so : out slave_out_t;
-- Non-Wishbone Signals
RS232_DCE_TXD : out std_logic
);
end component;
component counter is
generic(
FREQ : positive := 50; -- Clock frequency in MHz.
RATE : positive := 19200 -- Baud rate.
);
port(
clk : in std_logic;
rst : in std_logic;
tick : out std_logic
);
end component;
end iuart;
|
gpl-3.0
|
GSejas/Dise-o-ASIC-FPGA-FPU
|
Literature FPUs/Oggona(Meiko)/oggonachip-hardware-v1.0/leon/leon1-2.4.0/leon/wprot.vhd
|
3
|
4127
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: wprot
-- File: wprot.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: RAM write protection
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
entity wprot is
port (
rst : in rst_type;
clk : in clk_type;
wpo : out wprot_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of wprot is
type wprottype is record
addr : std_logic_vector(14 downto 0);
mask : std_logic_vector(14 downto 0);
enable : std_logic;
ablock : std_logic;
end record;
type wprotregs is record
wprot1, wprot2 : wprottype;
haddr : std_logic_vector(31 downto 15);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
end record;
signal r, rin : wprotregs;
begin
ctrl : process(rst, ahbsi, apbi, r)
variable wprothit, wprothit1, wprothit2 : std_logic;
variable wprothitx : std_logic;
variable aprot : std_logic_vector(14 downto 0); --
variable v : wprotregs;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
begin
v := r; regsd := (others => '0');
if (ahbsi.hready = '1') then
v.hwrite := ahbsi.hwrite; v.htrans := ahbsi.htrans;
v.haddr := ahbsi.haddr(31 downto 15);
end if;
wprothit := '0'; wprothit1 := '0'; wprothit2 := '0';
if WPROTEN then
aprot := (r.haddr(29 downto 15) xor r.wprot1.addr) and r.wprot1.mask;
if (aprot = "000000000000000") then wprothit1 := '1'; end if;
aprot := (r.haddr(29 downto 15) xor r.wprot2.addr) and r.wprot2.mask;
if (aprot = "000000000000000") then wprothit2 := '1'; end if;
if (r.hwrite = '1') and (r.haddr(31 downto 30) = "01") then
wprothit :=
((r.wprot1.enable and (not wprothit1) and (not r.wprot1.ablock)) or
(r.wprot2.enable and (not wprothit2) and (not r.wprot2.ablock))) or
(((r.wprot1.enable and wprothit1 and r.wprot1.ablock) or
(r.wprot2.enable and wprothit2 and r.wprot2.ablock)) and not
((r.wprot1.enable and wprothit1 and (not r.wprot1.ablock)) or
(r.wprot2.enable and wprothit2 and (not r.wprot2.ablock))));
end if;
end if;
case apbi.paddr(2 downto 2) is
when "1" =>
if WPROTEN then
regsd := r.wprot1.enable & r.wprot1.ablock &
r.wprot1.addr & r.wprot1.mask;
end if;
when "0" =>
if WPROTEN then
regsd := r.wprot2.enable & r.wprot2.ablock &
r.wprot2.addr & r.wprot2.mask;
end if;
when others => null;
end case;
apbo.prdata <= regsd;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2 downto 2) is
when "1" =>
v.wprot1.enable := apbi.pwdata(31);
v.wprot1.ablock := apbi.pwdata(30);
v.wprot1.addr := apbi.pwdata(29 downto 15);
v.wprot1.mask := apbi.pwdata(14 downto 0);
when "0" =>
v.wprot2.enable := apbi.pwdata(31);
v.wprot2.ablock := apbi.pwdata(30);
v.wprot2.addr := apbi.pwdata(29 downto 15);
v.wprot2.mask := apbi.pwdata(14 downto 0);
when others => null;
end case;
end if;
if rst.syncrst = '0' then
v.wprot1.enable := '0';
v.wprot2.enable := '0';
end if;
rin <= v;
wpo.wprothit <= wprothit;
end process;
wpreggen : if WPROTEN generate
wpregs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end generate;
end;
|
gpl-3.0
|
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