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AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/synth/design_1_lmb_bram_0.vhd
|
2
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15379
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-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY design_1_lmb_bram_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_lmb_bram_0;
ARCHITECTURE design_1_lmb_bram_0_arch OF design_1_lmb_bram_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_lmb_bram_0_arch : ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=design_1_lmb_bram_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=8192,C_READ_DEPTH_A=8192,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=8192,C_READ_DEPTH_B=8192,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "design_1_lmb_bram_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 8192,
C_READ_DEPTH_A => 8192,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 8192,
C_READ_DEPTH_B => 8192,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 20.388 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_lmb_bram_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/a3d1bdff/hdl/src/vhdl/uartlite_core.vhd
|
6
|
21364
|
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0;
-- baudrate refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/a3d1bdff/hdl/src/vhdl/uartlite_core.vhd
|
6
|
21364
|
-------------------------------------------------------------------------------
-- uartlite_core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2012] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_core.vhd
-- Version: v2.0
-- Description: UART Lite core for implementing UART logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_uartlite_v2_0;
-- baudrate refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.baudrate;
-- uartlite_rx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_rx;
-- uartlite_tx refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_tx;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- Slave attachment interface
-- bus2ip_data -- bus2ip data signal
-- bus2ip_rdce -- bus2ip read CE
-- bus2ip_wrce -- bus2ip write CE
-- ip2bus_rdack -- ip2bus read acknowledgement
-- ip2bus_wrack -- ip2bus write acknowledgement
-- ip2bus_error -- ip2bus error
-- SIn_DBus -- ip2bus data
-- UART Lite interface
-- RX -- Receive Data
-- TX -- Transmit Data
-- Interrupt -- UART Interrupt
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_core is
generic
(
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ: integer := 100_000_000;
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
-- IPIF signals
bus2ip_data : in std_logic_vector(0 to 7);
bus2ip_rdce : in std_logic_vector(0 to 3);
bus2ip_wrce : in std_logic_vector(0 to 3);
bus2ip_cs : in std_logic;
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
ip2bus_error : out std_logic;
SIn_DBus : out std_logic_vector(0 to 7);
-- UART signals
RX : in std_logic;
TX : out std_logic;
Interrupt : out std_logic
);
end entity uartlite_core;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
---------------------------------------------------------------------------
-- function declarations
---------------------------------------------------------------------------
function CALC_RATIO ( C_S_AXI_ACLK_FREQ_HZ : integer;
C_BAUDRATE : integer ) return Integer is
constant C_BAUDRATE_16_BY_2: integer := (16 * C_BAUDRATE) / 2;
constant REMAINDER : integer :=
C_S_AXI_ACLK_FREQ_HZ rem (16 * C_BAUDRATE);
constant RATIO : integer :=
C_S_AXI_ACLK_FREQ_HZ / (16 * C_BAUDRATE);
begin
if (C_BAUDRATE_16_BY_2 < REMAINDER) then
return (RATIO + 1);
else
return RATIO;
end if;
end function CALC_RATIO;
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant RATIO : integer := CALC_RATIO( C_S_AXI_ACLK_FREQ_HZ, C_BAUDRATE);
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
-- Read Only
signal status_reg : std_logic_vector(0 to 7) := (others => '0');
-- bit 7 rx_Data_Present
-- bit 6 rx_Buffer_Full
-- bit 5 tx_Buffer_Empty
-- bit 4 tx_Buffer_Full
-- bit 3 enable_interrupts
-- bit 2 Overrun Error
-- bit 1 Frame Error
-- bit 0 Parity Error (If C_USE_PARITY is true, otherwise '0')
-- Write Only
-- Below mentioned bits belong to Control Register and are declared as
-- signals below
-- bit 0-2 Dont'Care
-- bit 3 enable_interrupts
-- bit 4-5 Dont'Care
-- bit 6 Reset_RX_FIFO
-- bit 7 Reset_TX_FIFO
signal en_16x_Baud : std_logic;
signal enable_interrupts : std_logic;
signal reset_RX_FIFO : std_logic;
signal rx_Data : std_logic_vector(0 to C_DATA_BITS-1);
signal rx_Data_Present : std_logic;
signal rx_Buffer_Full : std_logic;
signal rx_Frame_Error : std_logic;
signal rx_Overrun_Error : std_logic;
signal rx_Parity_Error : std_logic;
signal clr_Status : std_logic;
signal reset_TX_FIFO : std_logic;
signal tx_Buffer_Full : std_logic;
signal tx_Buffer_Empty : std_logic;
signal tx_Buffer_Empty_Pre : std_logic;
signal rx_Data_Present_Pre : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
-- Generating the acknowledgement and error signals
---------------------------------------------------------------------------
ip2bus_rdack <= bus2ip_rdce(0) or bus2ip_rdce(2) or bus2ip_rdce(1)
or bus2ip_rdce(3);
ip2bus_wrack <= bus2ip_wrce(1) or bus2ip_wrce(3) or bus2ip_wrce(0)
or bus2ip_wrce(2);
ip2bus_error <= ((bus2ip_rdce(0) and not rx_Data_Present) or
(bus2ip_wrce(1) and tx_Buffer_Full) );
-------------------------------------------------------------------------
-- BAUD_RATE_I : Instansiating the baudrate module
-------------------------------------------------------------------------
BAUD_RATE_I : entity axi_uartlite_v2_0.baudrate
generic map
(
C_RATIO => RATIO
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud
);
-------------------------------------------------------------------------
-- Status register handling
-------------------------------------------------------------------------
status_reg(7) <= rx_Data_Present;
status_reg(6) <= rx_Buffer_Full;
status_reg(5) <= tx_Buffer_Empty;
status_reg(4) <= tx_Buffer_Full;
status_reg(3) <= enable_interrupts;
-------------------------------------------------------------------------
-- CLEAR_STATUS_REG : Process to clear status register
-------------------------------------------------------------------------
CLEAR_STATUS_REG : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then
if Reset = '1' then
clr_Status <= '0';
else
clr_Status <= bus2ip_rdce(2);
end if;
end if;
end process CLEAR_STATUS_REG;
-------------------------------------------------------------------------
-- Process to register rx_Overrun_Error
-------------------------------------------------------------------------
RX_OVERRUN_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if ((Reset = '1') or (clr_Status = '1')) then
status_reg(2) <= '0';
elsif (rx_Overrun_Error = '1') then
status_reg(2) <= '1';
end if;
end if;
end process RX_OVERRUN_ERROR_DFF;
-------------------------------------------------------------------------
-- Process to register rx_Frame_Error
-------------------------------------------------------------------------
RX_FRAME_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(1) <= '0';
else
if (clr_Status = '1') then
status_reg(1) <= '0';
elsif (rx_Frame_Error = '1') then
status_reg(1) <= '1';
end if;
end if;
end if;
end process RX_FRAME_ERROR_DFF;
-------------------------------------------------------------------------
-- If C_USE_PARITY = 1, register rx_Parity_Error
-------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
RX_PARITY_ERROR_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
status_reg(0) <= '0';
else
if (clr_Status = '1') then
status_reg(0) <= '0';
elsif (rx_Parity_Error = '1') then
status_reg(0) <= '1';
end if;
end if;
end if;
end process RX_PARITY_ERROR_DFF;
end generate USING_PARITY;
-------------------------------------------------------------------------
-- NO_PARITY : If C_USE_PARITY = 0, rx_Parity_Error bit is not present
-------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
status_reg(0) <= '0';
end generate NO_PARITY;
-------------------------------------------------------------------------
-- CTRL_REG_DFF : Control Register Handling
-------------------------------------------------------------------------
CTRL_REG_DFF : process (Clk) is
begin -- process Ctrl_Reg_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
reset_TX_FIFO <= '1';
reset_RX_FIFO <= '1';
enable_interrupts <= '0';
elsif (bus2ip_wrce(3) = '1') then
reset_RX_FIFO <= bus2ip_data(6);
reset_TX_FIFO <= bus2ip_data(7);
enable_interrupts <= bus2ip_data(3);
else
reset_TX_FIFO <= '0';
reset_RX_FIFO <= '0';
end if;
end if;
end process CTRL_REG_DFF;
-------------------------------------------------------------------------
-- Tx Fifo Interrupt handling
-------------------------------------------------------------------------
TX_BUFFER_EMPTY_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Buffer_Empty_Pre <= '0';
else
if (bus2ip_wrce(1) = '1') then
tx_Buffer_Empty_Pre <= '0';
else
tx_Buffer_Empty_Pre <= tx_Buffer_Empty;
end if;
end if;
end if;
end process TX_BUFFER_EMPTY_DFF_I;
-------------------------------------------------------------------------
-- Rx Fifo Interrupt handling
-------------------------------------------------------------------------
RX_BUFFER_DATA_DFF_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
rx_Data_Present_Pre <= '0';
else
if (bus2ip_rdce(0) = '1') then
rx_Data_Present_Pre <= '0';
else
rx_Data_Present_Pre <= rx_Data_Present;
end if;
end if;
end if;
end process RX_BUFFER_DATA_DFF_I;
-------------------------------------------------------------------------
-- Interrupt register handling
-------------------------------------------------------------------------
INTERRUPT_DFF: process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then -- synchronous reset (active high)
Interrupt <= '0';
else
Interrupt <= enable_interrupts and
((rx_Data_Present and not rx_Data_Present_Pre) or
(tx_Buffer_Empty and not tx_Buffer_Empty_Pre));
end if;
end if;
end process INTERRUPT_DFF;
-------------------------------------------------------------------------
-- READ_MUX : Read bus interface handling
-------------------------------------------------------------------------
READ_MUX : process (status_reg, bus2ip_rdce(2), bus2ip_rdce(0), rx_Data) is
begin -- process Read_Mux
if (bus2ip_rdce(2) = '1') then
SIn_DBus <= status_reg;
elsif (bus2ip_rdce(0) = '1') then
SIn_DBus((8-C_DATA_BITS) to 7) <= rx_Data;
SIn_DBus(0 to (7-C_DATA_BITS)) <= (others => '0');
else
SIn_DBus <= (others => '0');
end if;
end process READ_MUX;
-------------------------------------------------------------------------
-- UARTLITE_RX_I : Instansiating the receive module
-------------------------------------------------------------------------
UARTLITE_RX_I : entity axi_uartlite_v2_0.uartlite_rx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
RX => RX,
Read_RX_FIFO => bus2ip_rdce(0),
Reset_RX_FIFO => reset_RX_FIFO,
RX_Data => rx_Data,
RX_Data_Present => rx_Data_Present,
RX_Buffer_Full => rx_Buffer_Full,
RX_Frame_Error => rx_Frame_Error,
RX_Overrun_Error => rx_Overrun_Error,
RX_Parity_Error => rx_Parity_Error
);
-------------------------------------------------------------------------
-- UARTLITE_TX_I : Instansiating the transmit module
-------------------------------------------------------------------------
UARTLITE_TX_I : entity axi_uartlite_v2_0.uartlite_tx
generic map
(
C_FAMILY => C_FAMILY,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => Clk,
Reset => Reset,
EN_16x_Baud => en_16x_Baud,
TX => TX,
Write_TX_FIFO => bus2ip_wrce(1),
Reset_TX_FIFO => reset_TX_FIFO,
TX_Data => bus2ip_data(8-C_DATA_BITS to 7),
TX_Buffer_Full => tx_Buffer_Full,
TX_Buffer_Empty => tx_Buffer_Empty
);
end architecture RTL;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_emc_0_0/synth/design_1_axi_emc_0_0.vhd
|
2
|
25548
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_emc:3.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_emc_v3_0;
USE axi_emc_v3_0.axi_emc;
ENTITY design_1_axi_emc_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
rdclk : IN STD_LOGIC;
s_axi_mem_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_awlock : IN STD_LOGIC;
s_axi_mem_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awvalid : IN STD_LOGIC;
s_axi_mem_awready : OUT STD_LOGIC;
s_axi_mem_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_wlast : IN STD_LOGIC;
s_axi_mem_wvalid : IN STD_LOGIC;
s_axi_mem_wready : OUT STD_LOGIC;
s_axi_mem_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_bvalid : OUT STD_LOGIC;
s_axi_mem_bready : IN STD_LOGIC;
s_axi_mem_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_arlock : IN STD_LOGIC;
s_axi_mem_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arvalid : IN STD_LOGIC;
s_axi_mem_arready : OUT STD_LOGIC;
s_axi_mem_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_rlast : OUT STD_LOGIC;
s_axi_mem_rvalid : OUT STD_LOGIC;
s_axi_mem_rready : IN STD_LOGIC;
mem_dq_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_ce : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_cen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_oen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_wen : OUT STD_LOGIC;
mem_ben : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_qwen : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_rpn : OUT STD_LOGIC;
mem_adv_ldn : OUT STD_LOGIC;
mem_lbon : OUT STD_LOGIC;
mem_cken : OUT STD_LOGIC;
mem_rnw : OUT STD_LOGIC;
mem_cre : OUT STD_LOGIC;
mem_wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_axi_emc_0_0;
ARCHITECTURE design_1_axi_emc_0_0_arch OF design_1_axi_emc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_emc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_AXI_CLK_PERIOD_PS : INTEGER;
C_LFLASH_PERIOD_PS : INTEGER;
C_LINEAR_FLASH_SYNC_BURST : INTEGER;
C_S_AXI_REG_ADDR_WIDTH : INTEGER;
C_S_AXI_REG_DATA_WIDTH : INTEGER;
C_S_AXI_EN_REG : INTEGER;
C_S_AXI_MEM_ADDR_WIDTH : INTEGER;
C_S_AXI_MEM_DATA_WIDTH : INTEGER;
C_S_AXI_MEM_ID_WIDTH : INTEGER;
C_S_AXI_MEM0_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM0_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM1_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM1_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM2_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM2_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM3_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM3_HIGHADDR : STD_LOGIC_VECTOR;
C_INCLUDE_NEGEDGE_IOREGS : INTEGER;
C_NUM_BANKS_MEM : INTEGER;
C_MEM0_TYPE : INTEGER;
C_MEM1_TYPE : INTEGER;
C_MEM2_TYPE : INTEGER;
C_MEM3_TYPE : INTEGER;
C_MEM0_WIDTH : INTEGER;
C_MEM1_WIDTH : INTEGER;
C_MEM2_WIDTH : INTEGER;
C_MEM3_WIDTH : INTEGER;
C_MAX_MEM_WIDTH : INTEGER;
C_PARITY_TYPE_MEM_0 : INTEGER;
C_PARITY_TYPE_MEM_1 : INTEGER;
C_PARITY_TYPE_MEM_2 : INTEGER;
C_PARITY_TYPE_MEM_3 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER;
C_SYNCH_PIPEDELAY_0 : INTEGER;
C_TCEDV_PS_MEM_0 : INTEGER;
C_TAVDV_PS_MEM_0 : INTEGER;
C_TPACC_PS_FLASH_0 : INTEGER;
C_THZCE_PS_MEM_0 : INTEGER;
C_THZOE_PS_MEM_0 : INTEGER;
C_TWC_PS_MEM_0 : INTEGER;
C_TWP_PS_MEM_0 : INTEGER;
C_TWPH_PS_MEM_0 : INTEGER;
C_TLZWE_PS_MEM_0 : INTEGER;
C_WR_REC_TIME_MEM_0 : INTEGER;
C_SYNCH_PIPEDELAY_1 : INTEGER;
C_TCEDV_PS_MEM_1 : INTEGER;
C_TAVDV_PS_MEM_1 : INTEGER;
C_TPACC_PS_FLASH_1 : INTEGER;
C_THZCE_PS_MEM_1 : INTEGER;
C_THZOE_PS_MEM_1 : INTEGER;
C_TWC_PS_MEM_1 : INTEGER;
C_TWP_PS_MEM_1 : INTEGER;
C_TWPH_PS_MEM_1 : INTEGER;
C_TLZWE_PS_MEM_1 : INTEGER;
C_WR_REC_TIME_MEM_1 : INTEGER;
C_SYNCH_PIPEDELAY_2 : INTEGER;
C_TCEDV_PS_MEM_2 : INTEGER;
C_TAVDV_PS_MEM_2 : INTEGER;
C_TPACC_PS_FLASH_2 : INTEGER;
C_THZCE_PS_MEM_2 : INTEGER;
C_THZOE_PS_MEM_2 : INTEGER;
C_TWC_PS_MEM_2 : INTEGER;
C_TWP_PS_MEM_2 : INTEGER;
C_TWPH_PS_MEM_2 : INTEGER;
C_TLZWE_PS_MEM_2 : INTEGER;
C_WR_REC_TIME_MEM_2 : INTEGER;
C_SYNCH_PIPEDELAY_3 : INTEGER;
C_TCEDV_PS_MEM_3 : INTEGER;
C_TAVDV_PS_MEM_3 : INTEGER;
C_TPACC_PS_FLASH_3 : INTEGER;
C_THZCE_PS_MEM_3 : INTEGER;
C_THZOE_PS_MEM_3 : INTEGER;
C_TWC_PS_MEM_3 : INTEGER;
C_TWP_PS_MEM_3 : INTEGER;
C_TWPH_PS_MEM_3 : INTEGER;
C_TLZWE_PS_MEM_3 : INTEGER;
C_WR_REC_TIME_MEM_3 : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
rdclk : IN STD_LOGIC;
s_axi_reg_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_reg_awvalid : IN STD_LOGIC;
s_axi_reg_awready : OUT STD_LOGIC;
s_axi_reg_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_reg_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_reg_wvalid : IN STD_LOGIC;
s_axi_reg_wready : OUT STD_LOGIC;
s_axi_reg_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_reg_bvalid : OUT STD_LOGIC;
s_axi_reg_bready : IN STD_LOGIC;
s_axi_reg_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_reg_arvalid : IN STD_LOGIC;
s_axi_reg_arready : OUT STD_LOGIC;
s_axi_reg_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_reg_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_reg_rvalid : OUT STD_LOGIC;
s_axi_reg_rready : IN STD_LOGIC;
s_axi_mem_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_awlock : IN STD_LOGIC;
s_axi_mem_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awvalid : IN STD_LOGIC;
s_axi_mem_awready : OUT STD_LOGIC;
s_axi_mem_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_wlast : IN STD_LOGIC;
s_axi_mem_wvalid : IN STD_LOGIC;
s_axi_mem_wready : OUT STD_LOGIC;
s_axi_mem_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_bvalid : OUT STD_LOGIC;
s_axi_mem_bready : IN STD_LOGIC;
s_axi_mem_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_arlock : IN STD_LOGIC;
s_axi_mem_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arvalid : IN STD_LOGIC;
s_axi_mem_arready : OUT STD_LOGIC;
s_axi_mem_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_rlast : OUT STD_LOGIC;
s_axi_mem_rvalid : OUT STD_LOGIC;
s_axi_mem_rready : IN STD_LOGIC;
mem_dq_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_parity_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_dq_parity_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_dq_parity_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_ce : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_cen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_oen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_wen : OUT STD_LOGIC;
mem_ben : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_qwen : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_rpn : OUT STD_LOGIC;
mem_adv_ldn : OUT STD_LOGIC;
mem_lbon : OUT STD_LOGIC;
mem_cken : OUT STD_LOGIC;
mem_rnw : OUT STD_LOGIC;
mem_cre : OUT STD_LOGIC;
mem_wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_emc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "axi_emc,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_emc_0_0_arch : ARCHITECTURE IS "design_1_axi_emc_0_0,axi_emc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "design_1_axi_emc_0_0,axi_emc,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_emc,x_ipVersion=3.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_emc_inst,C_AXI_CLK_PERIOD_PS=10000,C_LFLASH_PERIOD_PS=10000,C_LINEAR_FLASH_SYNC_BURST=0,C_S_AXI_REG_ADDR_WIDTH=5,C_S_AXI_REG_DATA_WIDTH=32,C_S_AXI_EN_REG=0,C_S_AXI_MEM_ADDR_WIDTH=32,C_S_AXI_MEM_DATA_WIDTH=32,C_S_AXI_MEM_ID_WIDTH=1,C_S_AXI_MEM0_BASEADDR=0x60000000,C_S_AXI_MEM0_HIGHADDR=0x60FFFFFF,C_S_AXI_MEM1_BASEADDR=0xB0000000,C_S_AXI_MEM1_HIGHADDR=0xBFFFFFFF,C_S_AXI_MEM2_BASEADDR=0xC0000000,C_S_AXI_MEM2_HIGHADDR=0xCFFFFFFF,C_S_AXI_MEM3_BASEADDR=0xD0000000,C_S_AXI_MEM3_HIGHADDR=0xDFFFFFFF,C_INCLUDE_NEGEDGE_IOREGS=0,C_NUM_BANKS_MEM=1,C_MEM0_TYPE=1,C_MEM1_TYPE=0,C_MEM2_TYPE=0,C_MEM3_TYPE=0,C_MEM0_WIDTH=16,C_MEM1_WIDTH=16,C_MEM2_WIDTH=16,C_MEM3_WIDTH=16,C_MAX_MEM_WIDTH=16,C_PARITY_TYPE_MEM_0=0,C_PARITY_TYPE_MEM_1=0,C_PARITY_TYPE_MEM_2=0,C_PARITY_TYPE_MEM_3=0,C_INCLUDE_DATAWIDTH_MATCHING_0=1,C_INCLUDE_DATAWIDTH_MATCHING_1=1,C_INCLUDE_DATAWIDTH_MATCHING_2=1,C_INCLUDE_DATAWIDTH_MATCHING_3=1,C_SYNCH_PIPEDELAY_0=1,C_TCEDV_PS_MEM_0=70000,C_TAVDV_PS_MEM_0=70000,C_TPACC_PS_FLASH_0=70000,C_THZCE_PS_MEM_0=8000,C_THZOE_PS_MEM_0=8000,C_TWC_PS_MEM_0=85000,C_TWP_PS_MEM_0=55000,C_TWPH_PS_MEM_0=10000,C_TLZWE_PS_MEM_0=0,C_WR_REC_TIME_MEM_0=27000,C_SYNCH_PIPEDELAY_1=1,C_TCEDV_PS_MEM_1=15000,C_TAVDV_PS_MEM_1=15000,C_TPACC_PS_FLASH_1=25000,C_THZCE_PS_MEM_1=7000,C_THZOE_PS_MEM_1=7000,C_TWC_PS_MEM_1=15000,C_TWP_PS_MEM_1=12000,C_TWPH_PS_MEM_1=12000,C_TLZWE_PS_MEM_1=0,C_WR_REC_TIME_MEM_1=27000,C_SYNCH_PIPEDELAY_2=1,C_TCEDV_PS_MEM_2=15000,C_TAVDV_PS_MEM_2=15000,C_TPACC_PS_FLASH_2=25000,C_THZCE_PS_MEM_2=7000,C_THZOE_PS_MEM_2=7000,C_TWC_PS_MEM_2=15000,C_TWP_PS_MEM_2=12000,C_TWPH_PS_MEM_2=12000,C_TLZWE_PS_MEM_2=0,C_WR_REC_TIME_MEM_2=27000,C_SYNCH_PIPEDELAY_3=1,C_TCEDV_PS_MEM_3=15000,C_TAVDV_PS_MEM_3=15000,C_TPACC_PS_FLASH_3=25000,C_THZCE_PS_MEM_3=7000,C_THZOE_PS_MEM_3=7000,C_TWC_PS_MEM_3=15000,C_TWP_PS_MEM_3=12000,C_TWPH_PS_MEM_3=12000,C_TLZWE_PS_MEM_3=0,C_WR_REC_TIME_MEM_3=27000}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF rdclk: SIGNAL IS "xilinx.com:signal:clock:1.0 rdclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_i: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_I";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_o: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_O";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_t: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_T";
ATTRIBUTE X_INTERFACE_INFO OF mem_a: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF ADDR";
ATTRIBUTE X_INTERFACE_INFO OF mem_ce: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CE";
ATTRIBUTE X_INTERFACE_INFO OF mem_cen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CE_N";
ATTRIBUTE X_INTERFACE_INFO OF mem_oen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF OEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_wen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF WEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_ben: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF BEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_qwen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF QWEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_rpn: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF RPN";
ATTRIBUTE X_INTERFACE_INFO OF mem_adv_ldn: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF ADV_LDN";
ATTRIBUTE X_INTERFACE_INFO OF mem_lbon: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF LBON";
ATTRIBUTE X_INTERFACE_INFO OF mem_cken: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CLKEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_rnw: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF RNW";
ATTRIBUTE X_INTERFACE_INFO OF mem_cre: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CRE";
ATTRIBUTE X_INTERFACE_INFO OF mem_wait: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF WAIT";
BEGIN
U0 : axi_emc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_emc_inst",
C_AXI_CLK_PERIOD_PS => 10000,
C_LFLASH_PERIOD_PS => 10000,
C_LINEAR_FLASH_SYNC_BURST => 0,
C_S_AXI_REG_ADDR_WIDTH => 5,
C_S_AXI_REG_DATA_WIDTH => 32,
C_S_AXI_EN_REG => 0,
C_S_AXI_MEM_ADDR_WIDTH => 32,
C_S_AXI_MEM_DATA_WIDTH => 32,
C_S_AXI_MEM_ID_WIDTH => 1,
C_S_AXI_MEM0_BASEADDR => X"60000000",
C_S_AXI_MEM0_HIGHADDR => X"60FFFFFF",
C_S_AXI_MEM1_BASEADDR => X"B0000000",
C_S_AXI_MEM1_HIGHADDR => X"BFFFFFFF",
C_S_AXI_MEM2_BASEADDR => X"C0000000",
C_S_AXI_MEM2_HIGHADDR => X"CFFFFFFF",
C_S_AXI_MEM3_BASEADDR => X"D0000000",
C_S_AXI_MEM3_HIGHADDR => X"DFFFFFFF",
C_INCLUDE_NEGEDGE_IOREGS => 0,
C_NUM_BANKS_MEM => 1,
C_MEM0_TYPE => 1,
C_MEM1_TYPE => 0,
C_MEM2_TYPE => 0,
C_MEM3_TYPE => 0,
C_MEM0_WIDTH => 16,
C_MEM1_WIDTH => 16,
C_MEM2_WIDTH => 16,
C_MEM3_WIDTH => 16,
C_MAX_MEM_WIDTH => 16,
C_PARITY_TYPE_MEM_0 => 0,
C_PARITY_TYPE_MEM_1 => 0,
C_PARITY_TYPE_MEM_2 => 0,
C_PARITY_TYPE_MEM_3 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_0 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_1 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_3 => 1,
C_SYNCH_PIPEDELAY_0 => 1,
C_TCEDV_PS_MEM_0 => 70000,
C_TAVDV_PS_MEM_0 => 70000,
C_TPACC_PS_FLASH_0 => 70000,
C_THZCE_PS_MEM_0 => 8000,
C_THZOE_PS_MEM_0 => 8000,
C_TWC_PS_MEM_0 => 85000,
C_TWP_PS_MEM_0 => 55000,
C_TWPH_PS_MEM_0 => 10000,
C_TLZWE_PS_MEM_0 => 0,
C_WR_REC_TIME_MEM_0 => 27000,
C_SYNCH_PIPEDELAY_1 => 1,
C_TCEDV_PS_MEM_1 => 15000,
C_TAVDV_PS_MEM_1 => 15000,
C_TPACC_PS_FLASH_1 => 25000,
C_THZCE_PS_MEM_1 => 7000,
C_THZOE_PS_MEM_1 => 7000,
C_TWC_PS_MEM_1 => 15000,
C_TWP_PS_MEM_1 => 12000,
C_TWPH_PS_MEM_1 => 12000,
C_TLZWE_PS_MEM_1 => 0,
C_WR_REC_TIME_MEM_1 => 27000,
C_SYNCH_PIPEDELAY_2 => 1,
C_TCEDV_PS_MEM_2 => 15000,
C_TAVDV_PS_MEM_2 => 15000,
C_TPACC_PS_FLASH_2 => 25000,
C_THZCE_PS_MEM_2 => 7000,
C_THZOE_PS_MEM_2 => 7000,
C_TWC_PS_MEM_2 => 15000,
C_TWP_PS_MEM_2 => 12000,
C_TWPH_PS_MEM_2 => 12000,
C_TLZWE_PS_MEM_2 => 0,
C_WR_REC_TIME_MEM_2 => 27000,
C_SYNCH_PIPEDELAY_3 => 1,
C_TCEDV_PS_MEM_3 => 15000,
C_TAVDV_PS_MEM_3 => 15000,
C_TPACC_PS_FLASH_3 => 25000,
C_THZCE_PS_MEM_3 => 7000,
C_THZOE_PS_MEM_3 => 7000,
C_TWC_PS_MEM_3 => 15000,
C_TWP_PS_MEM_3 => 12000,
C_TWPH_PS_MEM_3 => 12000,
C_TLZWE_PS_MEM_3 => 0,
C_WR_REC_TIME_MEM_3 => 27000
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
rdclk => rdclk,
s_axi_reg_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axi_reg_awvalid => '0',
s_axi_reg_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_reg_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_reg_wvalid => '0',
s_axi_reg_bready => '0',
s_axi_reg_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axi_reg_arvalid => '0',
s_axi_reg_rready => '0',
s_axi_mem_awid => s_axi_mem_awid,
s_axi_mem_awaddr => s_axi_mem_awaddr,
s_axi_mem_awlen => s_axi_mem_awlen,
s_axi_mem_awsize => s_axi_mem_awsize,
s_axi_mem_awburst => s_axi_mem_awburst,
s_axi_mem_awlock => s_axi_mem_awlock,
s_axi_mem_awcache => s_axi_mem_awcache,
s_axi_mem_awprot => s_axi_mem_awprot,
s_axi_mem_awvalid => s_axi_mem_awvalid,
s_axi_mem_awready => s_axi_mem_awready,
s_axi_mem_wdata => s_axi_mem_wdata,
s_axi_mem_wstrb => s_axi_mem_wstrb,
s_axi_mem_wlast => s_axi_mem_wlast,
s_axi_mem_wvalid => s_axi_mem_wvalid,
s_axi_mem_wready => s_axi_mem_wready,
s_axi_mem_bid => s_axi_mem_bid,
s_axi_mem_bresp => s_axi_mem_bresp,
s_axi_mem_bvalid => s_axi_mem_bvalid,
s_axi_mem_bready => s_axi_mem_bready,
s_axi_mem_arid => s_axi_mem_arid,
s_axi_mem_araddr => s_axi_mem_araddr,
s_axi_mem_arlen => s_axi_mem_arlen,
s_axi_mem_arsize => s_axi_mem_arsize,
s_axi_mem_arburst => s_axi_mem_arburst,
s_axi_mem_arlock => s_axi_mem_arlock,
s_axi_mem_arcache => s_axi_mem_arcache,
s_axi_mem_arprot => s_axi_mem_arprot,
s_axi_mem_arvalid => s_axi_mem_arvalid,
s_axi_mem_arready => s_axi_mem_arready,
s_axi_mem_rid => s_axi_mem_rid,
s_axi_mem_rdata => s_axi_mem_rdata,
s_axi_mem_rresp => s_axi_mem_rresp,
s_axi_mem_rlast => s_axi_mem_rlast,
s_axi_mem_rvalid => s_axi_mem_rvalid,
s_axi_mem_rready => s_axi_mem_rready,
mem_dq_i => mem_dq_i,
mem_dq_o => mem_dq_o,
mem_dq_t => mem_dq_t,
mem_dq_parity_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
mem_a => mem_a,
mem_ce => mem_ce,
mem_cen => mem_cen,
mem_oen => mem_oen,
mem_wen => mem_wen,
mem_ben => mem_ben,
mem_qwen => mem_qwen,
mem_rpn => mem_rpn,
mem_adv_ldn => mem_adv_ldn,
mem_lbon => mem_lbon,
mem_cken => mem_cken,
mem_rnw => mem_rnw,
mem_cre => mem_cre,
mem_wait => mem_wait
);
END design_1_axi_emc_0_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc_native_interface.vhd
|
4
|
62797
|
-------------------------------------------------------------------------------
-- axi_emc_native_interface - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc_native_interface.vhd
-- Version: v2.0
-- Description: Native AXI interface to the EMC core.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- ~~~~~~
-- SK 09/20/10
-- ^^^^^^
-- -- Designed the native interface for AXI to reduce the utilization of core.
-- -- Added "enable_rdce_cmb <= '0'; in the default signal lists in state machine.
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library lib_srl_fifo_v1_0;
use lib_srl_fifo_v1_0.all;
library axi_emc_v3_0;
use axi_emc_v3_0.all;
use axi_emc_v3_0.emc_pkg.all;
----------------------------------------------------------------------------
entity axi_emc_native_interface is
-- Generics to be set by user
generic (
C_FAMILY : string := "virtex6";
---- AXI MEM Parameters
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer := 32;--8,16,32,64
C_S_AXI_MEM_ID_WIDTH : integer range 1 to 16 := 4;
C_S_AXI_MEM0_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM0_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM1_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM1_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM2_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM2_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM3_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM3_HIGHADDR : std_logic_vector := x"00000000";
AXI_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
AXI_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number -- only 1 is supported per addr range
1 -- User1 CE Number -- only 1 is supported per addr range
);
C_NUM_BANKS_MEM : integer
);
port(
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- -- AXI Write Address Channel Signals
S_AXI_MEM_AWID : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
S_AXI_MEM_AWADDR : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)
downto 0);
S_AXI_MEM_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_MEM_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_MEM_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_MEM_AWLOCK : in std_logic;
S_AXI_MEM_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_MEM_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_MEM_AWVALID : in std_logic;
S_AXI_MEM_AWREADY : out std_logic;
-- -- AXI Write Channel Signals
S_AXI_MEM_WDATA : in std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
S_AXI_MEM_WSTRB : in std_logic_vector
(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0);
S_AXI_MEM_WLAST : in std_logic;
S_AXI_MEM_WVALID : in std_logic;
S_AXI_MEM_WREADY : out std_logic;
-- -- AXI Write Response Channel Signals
S_AXI_MEM_BID : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
S_AXI_MEM_BRESP : out std_logic_vector(1 downto 0);
S_AXI_MEM_BVALID : out std_logic;
S_AXI_MEM_BREADY : in std_logic;
-- -- AXI Read Address Channel Signals
S_AXI_MEM_ARID : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1) downto 0);
S_AXI_MEM_ARADDR : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
S_AXI_MEM_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_MEM_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_MEM_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_MEM_ARLOCK : in std_logic;
S_AXI_MEM_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_MEM_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_MEM_ARVALID : in std_logic;
S_AXI_MEM_ARREADY : out std_logic;
-- -- AXI Read Data Channel Signals
S_AXI_MEM_RID : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
S_AXI_MEM_RDATA : out std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
S_AXI_MEM_RRESP : out std_logic_vector(1 downto 0);
S_AXI_MEM_RLAST : out std_logic;
S_AXI_MEM_RVALID : out std_logic;
S_AXI_MEM_RREADY : in std_logic;
-- IP Interconnect (IPIC) port signals ------------------------------------
-- Controls to the IP/IPIF modules
-- IP Interconnect (IPIC) port signals
IP2Bus_Data : in std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_AddrAck : in std_logic;
IP2Bus_Error : in std_logic;
-- these signals are generate little endian but reveresed in the top level file
Bus2IP_Addr : out std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
Bus2IP_Data : out std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1)downto 0);
Bus2IP_Burst : out std_logic;
Bus2IP_BurstLength : out std_logic_vector(7 downto 0);
Bus2IP_RdReq : out std_logic;
Bus2IP_WrReq : out std_logic;
Bus2IP_CS : out std_logic_vector
(((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
Bus2IP_RdCE : out std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
Type_of_xfer : out std_logic;
Cre_reg_en : in std_logic;
synch_mem : in std_logic ;
last_addr1 : out std_logic; -- 11-12-2012
pr_idle : in std_logic;
axi_sm_ns_IDLE : out std_logic; -- 17-12-2012
axi_trans_size_reg : out std_logic_vector(1 downto 0)--1/3/2013
);
end axi_emc_native_interface;
-----------------------------------------------------------------------------
architecture imp of axi_emc_native_interface is
----------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant NEW_LOGIC : integer := 0;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
function get_fifo_width(NEW_LOGIC : integer;
C_S_AXI_MEM_DATA_WIDTH : integer)
return integer is
begin
if(NEW_LOGIC = 1)then
return C_S_AXI_MEM_DATA_WIDTH + 2;
else
return C_S_AXI_MEM_DATA_WIDTH + 1;
end if;
end function get_fifo_width;
constant ACTIVE_LOW_RESET : integer := 0;
constant C_RDATA_FIFO_DEPTH : integer := 256;
constant COUNTER_WIDTH : integer := clog2(C_RDATA_FIFO_DEPTH);
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_S_AXI_MEM_ADDR_WIDTH-1)
:= (others => '0');
constant RD_DATA_FIFO_DWIDTH : integer := get_fifo_width(NEW_LOGIC,C_S_AXI_MEM_DATA_WIDTH) ; -- (C_S_AXI_MEM_DATA_WIDTH+2);
constant ALL_1 : std_logic_vector(0 to COUNTER_WIDTH-1)
:= (others => '1');
constant ZEROES : std_logic_vector(0 to clog2(C_RDATA_FIFO_DEPTH)-1)
:= (others => '0');
-- local type declarations
type decode_bit_array_type is Array(natural range 0 to (
(AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
AXI_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to(C_S_AXI_MEM_ADDR_WIDTH-1));
-----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
----------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
--coverage off
return(slv_array);
--coverage on
end function slv64_2_slv_awidth;
----------------------------------------------------------------------------
-------------------------------------------------------------------------------
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(AXI_ARD_NUM_CE_ARRAY);
signal pselect_hit_i : std_logic_vector
(0 to ((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal cs_reg : std_logic_vector
(0 to ((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1)
:=(others => '0');
signal rd_data_fifo_error : std_logic;
signal last_rd_data_cmb : std_logic;
signal rd_fifo_full : std_logic;
signal fifo_empty : std_logic;
signal last_fifo_data : std_logic;
signal rd_fifo_out : std_logic_vector(RD_DATA_FIFO_DWIDTH-1 downto 0);
signal rd_data_count : std_logic_vector(7 downto 0);
signal ORed_cs : std_logic;
---------------------------------------
type STATE_TYPE is
(IDLE,
RD,
RD_LAST,
WR,
WR_WAIT,
WR_RESP,
WR_LAST,
RESP);
signal emc_addr_ps: STATE_TYPE;
signal emc_addr_ns: STATE_TYPE;
-----------------------------------------
signal single_transfer_cmb : std_logic;
signal addr_sm_ps_IDLE_reg : std_logic;
signal addr_sm_ns_IDLE_cmb : std_logic;
signal wr_transaction : std_logic;
signal wr_addr_transaction : std_logic;
signal fifo_full : std_logic;
signal bvalid_cmb : std_logic;
signal enable_cs_cmb : std_logic;
signal rst_wrce_cmb : std_logic;
signal rst_rdce_cmb : std_logic;
signal rd_fifo_wr_en : std_logic;
signal rd_fifo_rd_en : std_logic;
signal type_of_xfer_reg : std_logic;
signal Type_of_xfer_cmb : std_logic;
signal addr_sm_ps_idle_cmb : std_logic;
signal last_burst_cnt : std_logic;
--IPIC request qualifier signals
signal ip2bus_errack : std_logic;
signal rd_fifo_data_in : std_logic_vector(RD_DATA_FIFO_DWIDTH-1 downto 0);-- (C_S_AXI_MEM_DATA_WIDTH downto 0);
signal rd_fifo_data_out : std_logic_vector(RD_DATA_FIFO_DWIDTH-1 downto 0);-- (C_S_AXI_MEM_DATA_WIDTH downto 0);
signal burst_length_cmb : std_logic_vector(7 downto 0);
signal addr_int_cmb : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal bus2ip_addr_i : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal derived_len_reg : std_logic_vector (3 downto 0);
signal size_cmb : std_logic_vector (1 downto 0);
signal bus2ip_data_reg : std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal bus2ip_BE_reg : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1)downto 0);
signal Bus2ip_BE_cmb : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1)downto 0);
signal s_axi_mem_awready_reg : std_logic;
signal s_axi_mem_wready_reg : std_logic;
signal s_axi_mem_bid_reg : std_logic_vector (C_S_AXI_MEM_ID_WIDTH-1 downto 0);
signal s_axi_mem_bresp_reg : std_logic_vector (1 downto 0);
signal s_axi_mem_bvalid_reg : std_logic;
signal s_axi_mem_arready_reg : std_logic;
signal s_axi_mem_rid_reg : std_logic_vector (C_S_AXI_MEM_ID_WIDTH-1 downto 0);
signal s_axi_mem_rresp_reg : std_logic_vector (1 downto 0);
signal s_axi_mem_rlast_reg : std_logic;
signal s_axi_mem_rvalid_reg : std_logic;
signal s_axi_mem_rdata_i : std_logic_vector(C_S_AXI_MEM_DATA_WIDTH-1 downto 0);
signal s_axi_mem_rdata_reg : std_logic_vector(C_S_AXI_MEM_DATA_WIDTH-1 downto 0);
signal arready_cmb : std_logic;
signal awready_cmb : std_logic;
signal rw_flag_reg : std_logic;
signal wready_cmb : std_logic;
signal bus2ip_burst_reg : std_logic ;
signal rnw_reg : std_logic ;
signal rnw_cmb : std_logic ;
signal store_addr_info_cmb : std_logic ;
signal last_len_cmb : std_logic ;
signal second_last_cnt : std_logic;
signal bus2ip_wr_req_reg : std_logic;
signal bus2ip_rd_req_reg : std_logic;
signal burstlength_reg : std_logic_vector(7 downto 0);
signal bus2ip_wrreq_reg : std_logic;
signal burst_data_cnt : std_logic_vector(7 downto 0); -- is not declared.
signal derived_size_reg : std_logic_vector(1 downto 0); -- is not declared.
signal temp_single_0 : std_logic;
signal temp_single_1 : std_logic;
signal bus2ip_addr_cmb : std_logic_vector(1 to 2);
signal bus2ip_addr_int : std_logic_vector(0 to 31);
signal bus2ip_resetn : std_logic;
signal last_data_cmb : std_logic;
signal combine_ack : std_logic;
signal wready_reg : std_logic;
signal bus2ip_wr_req_cmb : std_logic;
signal bus2ip_rd_req_cmb : std_logic;
signal derived_burst_reg : std_logic_vector(1 downto 0);
signal bus2ip_rnw_i : std_logic;
signal temp_ip2bus_data: std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal updn_cnt_en : std_logic;
signal rd_fifo_empty : std_logic;
signal active_high_rst : std_logic;
signal burst_addr_cnt : std_logic_vector(7 downto 0);
signal second_last_addr : std_logic;
signal last_addr : std_logic;
signal stop_addr_incr : std_logic;
signal last_rd_reg : std_logic;
signal last_rd_data_reg : std_logic;
signal enable_rdce_cmb : std_logic;
signal enable_wrce_combo: std_logic;
signal enable_wrce_cmb : std_logic;
signal enable_rdce_combo: std_logic;
signal addr_sm_ps_WR_cmb: std_logic;
signal addr_sm_ps_WR_WAIT_cmb: std_logic;
signal rst_cs_cmb : std_logic;
signal single_transfer_reg : std_logic;
signal last_data_acked : std_logic;
signal cnt : std_logic_vector((COUNTER_WIDTH-1) downto 0);
signal RdFIFO_Space_two_int : std_logic;
signal no_space_in_fifo : std_logic;
signal last_write : std_logic;
-----------------------------------
begin
------
--OLD_LOGIC_GEN: if NEW_LOGIC = 0 generate
-----
--begin
-----
ACTIVE_HIGH_RST_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
active_high_rst <= not(S_AXI_ARESETN);
end if;
end process ACTIVE_HIGH_RST_P;
-----------------------------------
-- AXI Side interface
---------------------
S_AXI_MEM_AWREADY <= awready_cmb;
S_AXI_MEM_WREADY <= wready_cmb;
S_AXI_MEM_BID <= s_axi_mem_bid_reg;
S_AXI_MEM_BRESP <= s_axi_mem_bresp_reg;
S_AXI_MEM_BVALID <= s_axi_mem_bvalid_reg;
S_AXI_MEM_ARREADY <= arready_cmb;
S_AXI_MEM_RID <= s_axi_mem_rid_reg;
S_AXI_MEM_RRESP <= s_axi_mem_rresp_reg;
S_AXI_MEM_RLAST <= s_axi_mem_rlast_reg;
S_AXI_MEM_RVALID <= s_axi_mem_rvalid_reg;
S_AXI_MEM_RDATA <= s_axi_mem_rdata_reg;
last_write <= (S_AXI_MEM_WLAST and S_AXI_MEM_WVALID and wready_cmb);
-----------------------
-- REG_BID_P,REG_RID_P: Below process makes the RID and BID '0' at POR and
-- : generate proper values based upon read/write
-- transaction
-----------------------
S_AXI_MEM_RID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
s_axi_mem_rid_reg <= (others=> '0');
elsif(arready_cmb='1')then
s_axi_mem_rid_reg <= S_AXI_MEM_ARID;
end if;
end if;
end process S_AXI_MEM_RID_P;
----------------------
S_AXI_MEM_BID_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
s_axi_mem_bid_reg <= (others=> '0');
elsif(awready_cmb='1')then
s_axi_mem_bid_reg <= S_AXI_MEM_AWID;
end if;
end if;
end process S_AXI_MEM_BID_P;
-----------------------
AXI_MEM_BRESP_P: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK='1')then
if (addr_sm_ps_IDLE_cmb='1')then
s_axi_mem_bresp_reg <= (others => '0');
elsif(ip2bus_wrack = '1') and (IP2Bus_Error='1') then
s_axi_mem_bresp_reg <= "10";
end if;
end if;
end process AXI_MEM_BRESP_P;
-----------------------
AXI_MEM_BVALID_P: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK='1')then
if (addr_sm_ps_IDLE_cmb='1')then
s_axi_mem_bvalid_reg <= '0';
--elsif(last_write_reg = '1') and (last_addr = '1') then
elsif(last_addr = '1') and (IP2Bus_WrAck='1') then
s_axi_mem_bvalid_reg <= '1';
elsif(S_AXI_MEM_BREADY='1') then
s_axi_mem_bvalid_reg <= '0';
end if;
end if;
end process AXI_MEM_BVALID_P;
-----------------------
s_axi_mem_rresp_reg <= (rd_data_fifo_error & '0')
when (rnw_reg='1')
else
(others => '0');
-----------------------
s_axi_mem_rlast_reg <= last_rd_data_cmb and
last_data_acked;
-----------------------
s_axi_mem_rvalid_reg <= not fifo_empty;
-----------------------
s_axi_mem_rdata_reg <= s_axi_mem_rdata_i;
-----------------------
arready_cmb <= -- below logic is useful in idle state only
S_AXI_MEM_ARVALID and
addr_sm_ps_IDLE_cmb and
(not(rw_flag_reg) or
not(S_AXI_MEM_AWVALID)
) and S_AXI_ARESETN
and pr_idle;
awready_cmb <= -- below logic is useful in idle state only
(wr_transaction) and
addr_sm_ps_IDLE_cmb and
(rw_flag_reg or
(not S_AXI_MEM_ARVALID)
) and
S_AXI_ARESETN
and pr_idle;
-----------------------------------------------------------------------------
----------------------
-- IPIC Side interface
----------------------
Type_of_xfer <= type_of_xfer_reg;
bus2ip_Addr <= bus2ip_addr_int;
Bus2ip_BE <= bus2ip_BE_reg;
Bus2IP_Data <= bus2ip_data_reg;
Bus2IP_Burst <= bus2ip_burst_reg;
Bus2ip_RNW <= rnw_reg;
Bus2IP_RdReq <= bus2ip_rd_req_reg;
Bus2IP_WrReq <= bus2ip_wr_req_reg;
Bus2IP_BurstLength <= burstlength_reg;
--------------
BUS2IP_DATA_P: process (S_AXI_ACLK) is
--------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if ((S_AXI_ARESETN='0')) then
bus2ip_data_reg <= (others => '0');
elsif (((S_AXI_MEM_WVALID='1') and (wready_cmb='1'))
) then
bus2ip_data_reg <= S_AXI_MEM_WDATA;
end if;
end if;
end process BUS2IP_DATA_P;
-------------------------
------------------------
-- BUS2IP_BE_P:Register Bus2IP_BE for write strobe during write mode else '1'.
------------------------
BUS2IP_BE_P: process (S_AXI_ACLK) is
------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if ((S_AXI_ARESETN='0')) then
bus2ip_BE_reg <= (others => '0');
elsif ((rnw_cmb='0') and (wready_cmb='1') and (S_AXI_MEM_WVALID ='1')) then
bus2ip_BE_reg <= S_AXI_MEM_WSTRB;
elsif(store_addr_info_cmb = '1')or (rnw_cmb='1') then
bus2ip_BE_reg <= Bus2ip_BE_cmb;
end if;
end if;
end process BUS2IP_BE_P;
------------------------
-------------- bus2ip_burst should be active till last but one transaction data ack
BUS2IP_BURST_P: process (S_AXI_ACLK) is
--------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0')then
bus2ip_burst_reg <= '0';
elsif(store_addr_info_cmb='1') then
bus2ip_burst_reg <= last_len_cmb;
elsif(last_data_cmb='1') then
bus2ip_burst_reg <= '0';
end if;
end if;
end process BUS2IP_BURST_P;
---------------------------
------------------
BUS2IP_BURST_REG_P1: process (S_AXI_ACLK) is
------------------
begin
if S_AXI_ACLK'event and S_AXI_ACLK='1' then
if (S_AXI_ARESETN='0') then
burstlength_reg <= (others => '0');
elsif(store_addr_info_cmb='1')then
burstlength_reg <= burst_length_cmb;
end if;
end if;
end process BUS2IP_BURST_REG_P1;
--------------------------------------
------------------
AXI_TRANS_SIZE_REG_P1: process (S_AXI_ACLK) is
------------------
begin
if S_AXI_ACLK'event and S_AXI_ACLK='1' then
if (S_AXI_ARESETN='0') then
axi_trans_size_reg <= (others => '0');
elsif(store_addr_info_cmb='1' and rnw_cmb = '1')then
axi_trans_size_reg <= S_AXI_MEM_ARSIZE(1 downto 0);
end if;
end if;
end process AXI_TRANS_SIZE_REG_P1;
--------------------------------------
----------------------
-- internal signals
----------------------
second_last_cnt <= not(or_reduce(burst_data_cnt(7 downto 1)))
and burst_data_cnt(0);
addr_sm_ns_IDLE_cmb <= '1' when (emc_addr_ns=IDLE) else '0';
addr_sm_ps_IDLE_cmb <= '1' when (emc_addr_ps=IDLE) else '0';
axi_sm_ns_IDLE <= '1' when (emc_addr_ns=IDLE) else '0';-- 17-dec-2012
addr_sm_ps_WR_cmb <= '1' when (emc_addr_ps=WR) else '0';
addr_sm_ps_WR_WAIT_cmb <= '1' when (emc_addr_ps=WR_WAIT) else '0';
wr_transaction <= S_AXI_MEM_AWVALID and (S_AXI_MEM_WVALID);
wr_addr_transaction <= S_AXI_MEM_AWVALID and (not S_AXI_MEM_WVALID);
---------------------------
addr_int_cmb <= S_AXI_MEM_ARADDR when(rnw_cmb = '1')
else
S_AXI_MEM_AWADDR;
-------------------
size_cmb <= S_AXI_MEM_ARSIZE(1 downto 0) when (rnw_cmb = '1') else
S_AXI_MEM_AWSIZE(1 downto 0);
-------------------
burst_length_cmb <= S_AXI_MEM_ARLEN when (rnw_cmb = '1')
else
S_AXI_MEM_AWLEN;
-------------------
single_transfer_cmb <= not(or_reduce(burst_length_cmb));
-------------------
last_len_cmb <= or_reduce(burst_length_cmb);
-------------------
Type_of_xfer_cmb <= or_reduce(S_AXI_MEM_ARBURST) when (rnw_cmb = '1')
else
or_reduce(S_AXI_MEM_AWBURST);
-------------------
Bus2IP_Resetn <= S_AXI_ARESETN;
-------------------
combine_ack <= --IP2Bus_WrAck or IP2Bus_RdAck;
IP2Bus_RdAck;
-----------------
BURST_DATA_CNT_P: process (S_AXI_ACLK) is
-----------------
begin
-----
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
burst_data_cnt <= (others => '0');
elsif(store_addr_info_cmb='1') then
burst_data_cnt <= burst_length_cmb;
elsif((combine_ack='1') and (last_data_cmb='0')
)then
burst_data_cnt <= burst_data_cnt - '1';
end if;
end if;
end process BURST_DATA_CNT_P;
-----------------------------
last_data_cmb <= not(or_reduce(burst_data_cnt));
LAST_DATA_ACKED_P: process (S_AXI_ACLK) is
-----------------
begin
-----
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if(addr_sm_ps_IDLE_cmb='1') then
last_data_acked <= '0';
elsif(synch_mem = '0' and last_rd_data_cmb= '1' and IP2Bus_RdAck = '1') then
last_data_acked <= '1';
elsif (last_data_cmb= '1' and IP2Bus_RdAck = '1') then
last_data_acked <= '1';
end if;
end if;
end process LAST_DATA_ACKED_P;
-----------------
BURST_ADDR_CNT_P: process(S_AXI_ACLK) is
-----------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (store_addr_info_cmb='1') then
burst_addr_cnt <= burst_length_cmb;
elsif ((IP2Bus_AddrAck='1')and
((last_addr='0'))
) then
burst_addr_cnt <= burst_addr_cnt - '1';
end if;
end if;
end process BURST_ADDR_CNT_P;
-----------------------------
second_last_addr <= not(or_reduce(burst_addr_cnt(7 downto 1))) and
burst_addr_cnt(0);
last_addr <= not(or_reduce(burst_addr_cnt));
last_addr1 <= last_addr;
stop_addr_incr <= last_addr;
--------------------------------------------------------------------------
--Generate burst length for WRAP xfer when C_S_AXI_MEM_DATA_WIDTH = 32.
--------------------------------------------------------------------------
LEN_GEN_32 : if ( C_S_AXI_MEM_DATA_WIDTH = 32 ) generate
------------
begin
-----
-- ----------------------------------------------------------------------
-- Process DERIVED_LEN_P to find the burst length translate from byte,
-- Half word and word transfer types.
-- Logic - convert the number of data beat transfers in the equivalent words
-- ex - Wrap transfer, byte size of length = Words
-- AXI Data 10 00 2 0001 = 0000
-- AXI Data 10 00 4 0011 = 0001
-- AXI Data 10 00 8 0111 = 0010
-- AXI Data 10 00 16 1111 = 0100
-- So pick the 3:2 bits from AXI Size
-- ----------------------------------------------------------------------
DERIVED_LEN_P: process (S_AXI_ACLK) is
--------------
begin
-----
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (store_addr_info_cmb='1') then
case size_cmb is
when "00" => derived_len_reg <= ("00" & burst_length_cmb(3 downto 2));
when "01" => derived_len_reg <= ('0' & burst_length_cmb(3 downto 1));
-- coverage off
when others => derived_len_reg <= burst_length_cmb(3 downto 0);
-- coverage on
end case;
end if;
end if;
end process DERIVED_LEN_P;
--------------------------
end generate LEN_GEN_32;
-- --------------------------------------------------------------------------
-- Generate burst length for WRAP xfer when C_S_AXI_DATA_WIDTH = 64.
-- --------------------------------------------------------------------------
LEN_GEN_64 : if ( C_S_AXI_MEM_DATA_WIDTH = 64 ) generate
------------
begin
-- ----------------------------------------------------------------------
-- Process DERIVED_LEN_P to find the burst length translate from byte,
-- Half word and word transfer types.
-- ----------------------------------------------------------------------
DERIVED_LEN_P: process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (store_addr_info_cmb='1') then
case size_cmb is
when "00" =>derived_len_reg <=("000" & burst_length_cmb(3));
when "01" =>derived_len_reg <=("00" & burst_length_cmb(3 downto 2));
when "10" =>derived_len_reg <=('0' & burst_length_cmb(3 downto 1));
-- coverage off
when others => derived_len_reg <= burst_length_cmb(3 downto 0);
-- coverage on
end case;
end if;
end if;
end process DERIVED_LEN_P;
--------------------------
end generate LEN_GEN_64;
------------------------
---------------------------
REG_P: process (S_AXI_ACLK) is
begin
-----
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
emc_addr_ps <= IDLE;
addr_sm_ps_IDLE_reg <= '1';
rnw_reg <= '0';
bus2ip_wr_req_reg <= '0';
bus2ip_rd_req_reg <= '0';
last_rd_data_reg <= '0';
else
emc_addr_ps <= emc_addr_ns;
addr_sm_ps_IDLE_reg <= addr_sm_ns_IDLE_cmb;
rnw_reg <= rnw_cmb;
bus2ip_wr_req_reg <= bus2ip_wr_req_cmb;
bus2ip_rd_req_reg <= bus2ip_rd_req_cmb;
last_rd_data_reg <= last_rd_data_cmb;
end if;
end if;
end process REG_P;
-------------------------------------------------------
REG_CONDITION_P: process (S_AXI_ACLK) is
----------------
begin
if (S_AXI_ACLK'event and S_AXI_ACLK='1') then
if (S_AXI_ARESETN='0') then
type_of_xfer_reg <= '0'; -- default
single_transfer_reg <= '0';
elsif(store_addr_info_cmb='1') then
single_transfer_reg <= single_transfer_cmb;
type_of_xfer_reg <= Type_of_xfer_cmb;
derived_size_reg <= size_cmb;
if(rnw_cmb = '1') then
derived_burst_reg <= S_AXI_MEM_ARBURST;
else
derived_burst_reg <= S_AXI_MEM_AWBURST;
end if;
end if;
end if;
end process REG_CONDITION_P;
-------------------------------------------------------
--------------------------------------------------
-- RW_FLAG_P: Round robin logic for read and write
--------------------------------------------------
RW_FLAG_P: process(S_AXI_ACLK)is
----------
begin
if(S_AXI_ACLK'event and S_AXI_ACLK='1')then
if (S_AXI_ARESETN='0')then
rw_flag_reg <= '0';
elsif((addr_sm_ps_IDLE_reg='1' and pr_idle = '1'))then
rw_flag_reg <= (rw_flag_reg and not(S_AXI_MEM_AWVALID))
or
((not rw_flag_reg)and S_AXI_MEM_ARVALID);
end if;
end if;
end process RW_FLAG_P;
--------------------------------------------------
process (
-- axi signals
S_AXI_MEM_ARVALID,
S_AXI_MEM_AWVALID,
S_AXI_MEM_WVALID,
S_AXI_MEM_WLAST,
S_AXI_MEM_RREADY,
S_AXI_MEM_BREADY,
-- internal signals
emc_addr_ps,
single_transfer_cmb,
wr_transaction,
last_addr,
last_rd_data_cmb,
second_last_addr,
last_data_cmb,
IP2Bus_AddrAck,
IP2Bus_RdAck,
IP2Bus_WrAck,
rd_fifo_full,
fifo_empty,
single_transfer_cmb,
-- registered signals
single_transfer_reg,
rw_flag_reg,
rnw_reg,
bus2ip_wr_req_reg,
bus2ip_rd_req_reg,
last_data_acked,
s_axi_mem_rlast_reg,
addr_sm_ps_IDLE_cmb,
s_axi_mem_bvalid_reg,
pr_idle, -- 11-12-2012
S_AXI_MEM_AWBURST,
S_AXI_MEM_ARBURST
)is
begin -- default states
rnw_cmb <= rnw_reg;
bus2ip_wr_req_cmb <= bus2ip_wr_req_reg;
bus2ip_rd_req_cmb <= bus2ip_rd_req_reg;
enable_cs_cmb <= '0';
rst_rdce_cmb <= '0';
rst_wrce_cmb <= '0';
rst_cs_cmb <= '0';
enable_wrce_cmb <= '0';
enable_rdce_cmb <= '0';
store_addr_info_cmb <= '0';
wready_cmb <= '0';
case emc_addr_ps is
-------------------------------
when IDLE => if ( (S_AXI_MEM_ARVALID='1') and
((rw_flag_reg='0' ) or
(S_AXI_MEM_AWVALID='0')
)
) and (pr_idle = '1') and (or_reduce(S_AXI_MEM_ARBURST) = '1')then
enable_cs_cmb <= '1';
store_addr_info_cmb <= '1';
if(single_transfer_cmb='1')then
enable_rdce_cmb <= '1';
emc_addr_ns <= RD_LAST;
else
emc_addr_ns <= RD;
end if;
elsif( (wr_transaction = '1') and
((rw_flag_reg='1' ) or
(S_AXI_MEM_ARVALID='0')
)
) and (pr_idle = '1') and (or_reduce(S_AXI_MEM_AWBURST) = '1') then
enable_cs_cmb <= '1';
store_addr_info_cmb <= '1';
if(single_transfer_cmb='1')then
emc_addr_ns <= WR_LAST;
else
emc_addr_ns <= WR;
end if;
else
emc_addr_ns <= IDLE;
end if;
wready_cmb <= pr_idle and -- 11-12-2012
(wr_transaction) and
addr_sm_ps_IDLE_cmb and
(rw_flag_reg or
(not S_AXI_MEM_ARVALID)
);
-- priority is given for read over write
rnw_cmb <= S_AXI_MEM_ARVALID and
( not(rw_flag_reg) or
not(S_AXI_MEM_AWVALID)
);
bus2ip_rd_req_cmb <= S_AXI_MEM_ARVALID and
(not(rw_flag_reg)
or
not(S_AXI_MEM_AWVALID)
);
bus2ip_wr_req_cmb <= wr_transaction and
(rw_flag_reg or (not S_AXI_MEM_ARVALID) );
-------------------------------
when RD => if(s_axi_mem_rlast_reg='1' and S_AXI_MEM_RREADY='1')then
rst_cs_cmb <= '1';
rst_rdce_cmb <= '1';
rnw_cmb <= '0';
emc_addr_ns <= IDLE;
else
emc_addr_ns <= RD;
end if;
rst_cs_cmb <= (last_data_cmb and IP2Bus_RdAck);
rst_rdce_cmb <= rd_fifo_full or
(last_data_cmb and IP2Bus_RdAck);--1/17/2013
--(last_rd_data_cmb and IP2Bus_RdAck);
enable_rdce_cmb <= fifo_empty and (not last_data_cmb);
bus2ip_rd_req_cmb <= not(last_addr and IP2Bus_AddrAck)
and
bus2ip_rd_req_reg;
-------------------------------
when RD_LAST => --if(IP2Bus_RdAck='1')then
if(s_axi_mem_rlast_reg='1' and S_AXI_MEM_RREADY='1')then
rnw_cmb <= '0';
rst_cs_cmb <= '1';
emc_addr_ns <= IDLE;
else
emc_addr_ns <= RD_LAST;
end if;
--bus2ip_rd_req_cmb <= not IP2Bus_RdAck;
rst_cs_cmb <= IP2Bus_RdAck;
rst_rdce_cmb <= IP2Bus_RdAck;--rd_fifo_full
--or
--((last_data_cmb or
-- single_transfer_reg)
-- and
-- IP2Bus_RdAck
-- );
--enable_rdce_cmb <= not (fifo_empty or
-- (last_data_cmb and
-- IP2Bus_RdAck
-- )
-- );
-------------------------------
when WR => if ((IP2Bus_WrAck='1')) then
if (S_AXI_MEM_WVALID='0') then
emc_addr_ns <= WR_WAIT;
elsif (second_last_addr='1') then
emc_addr_ns <= WR_LAST;
else
emc_addr_ns <= WR;
end if;
else
emc_addr_ns <= WR;
end if;
bus2ip_wr_req_cmb <= '1';
wready_cmb <= IP2Bus_WrAck;
rst_wrce_cmb <= IP2Bus_WrAck and
(not S_AXI_MEM_WVALID);
-------------------------------
when WR_WAIT => if (S_AXI_MEM_WVALID='0') then
rst_wrce_cmb <= '1';
emc_addr_ns <= WR_WAIT;
elsif(last_addr='1') then
emc_addr_ns <= WR_LAST;
else
emc_addr_ns <= WR;
end if;
bus2ip_wr_req_cmb <= '1';
wready_cmb <= '1';
enable_wrce_cmb <= S_AXI_MEM_WVALID;
-------------------------------
when WR_LAST => if (last_addr='1') then
if ((IP2Bus_AddrAck='1'))then
wready_cmb <= '0';
emc_addr_ns <= RESP;
else
emc_addr_ns <= WR_LAST;
end if;
else
emc_addr_ns <= WR_LAST;
end if;
bus2ip_wr_req_cmb <= not(IP2Bus_WrAck);
rst_cs_cmb <= IP2Bus_WrAck;
rst_wrce_cmb <= IP2Bus_WrAck;
enable_wrce_cmb <= S_AXI_MEM_WVALID;
-------------------------------
when RESP => rst_cs_cmb <= '1';
rst_wrce_cmb <= '1';
if((S_AXI_MEM_BREADY='1') and (s_axi_mem_bvalid_reg='1')) then
emc_addr_ns <= IDLE;
--rst_wrce_cmb <= '1';
--rst_cs_cmb <= '1';
else
emc_addr_ns <= RESP;
end if;
-------------------------------
-- coverage off
when others => emc_addr_ns <= IDLE;
-- coverage on
-------------------------------
end case;
end process;
-----------------------
------------------------------------------------------------------------------
AXI_EMC_ADDR_GEN_INSTANCE_I:entity axi_emc_v3_0.axi_emc_addr_gen
generic map
(
C_S_AXI_MEM_ADDR_WIDTH => C_S_AXI_MEM_ADDR_WIDTH,
C_S_AXI_MEM_DATA_WIDTH => C_S_AXI_MEM_DATA_WIDTH
)
port map
(
Bus2IP_Clk => S_AXI_ACLK , -- in std_logic
Bus2IP_Resetn => Bus2IP_Resetn , -- in std_logic
-- combo I/P signals
stop_addr_incr => stop_addr_incr,
Store_addr_info_cmb => Store_addr_info_cmb, -- in std_logic;
Addr_int_cmb => Addr_int_cmb , -- in std_logic_vector((C_S_AXI_ADDR_WIDTH-1)downto 0);
Ip2Bus_Addr_ack => IP2Bus_AddrAck , -- in std_logic;
Fifo_full_1 => rst_rdce_cmb, --Fifo_full , -- in std_logic;
Rst_Rd_CE => rst_rdce_cmb , -- : in std_logic;
-- registered signals
derived_len_reg => derived_len_reg , -- in std_logic_vector(3 downto 0);
Derived_burst_reg => Derived_burst_reg , -- in std_logic_vector(1 downto 0);
Derived_size_reg => Derived_size_reg , -- in std_logic_vector(1 downto 0);
-- registered O/P signals
Bus2IP_Addr => bus2ip_addr_int , -- out std_logic_vector((C_S_AXI_ADDR_WIDTH-1)downto 0)
Cre_reg_en => Cre_reg_en -- enable the lower address bits to pass - support un-aligned address
);
------------------------------------------------------------------------------
enable_rdce_combo <= enable_rdce_cmb;
enable_wrce_combo <= enable_wrce_cmb;
AXI_EMC_ADDRESS_DECODE_INSTANCE_I:entity axi_emc_v3_0.axi_emc_address_decode
generic map(
C_S_AXI_ADDR_WIDTH => C_S_AXI_MEM_ADDR_WIDTH ,
C_ARD_ADDR_RANGE_ARRAY => AXI_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => AXI_ARD_NUM_CE_ARRAY ,
C_FAMILY => C_FAMILY ,
C_ADDR_DECODE_BITS => C_S_AXI_MEM_ADDR_WIDTH
)
port map(
Bus2IP_Clk => S_AXI_ACLK , -- : in std_logic;
Bus2IP_Resetn => Bus2IP_Resetn , -- : in std_logic;
Enable_CS => enable_cs_cmb , -- : in std_logic;
Enable_RdCE => enable_rdce_combo , --Store_addr_info_cmb , -- : in std_logic;
Enable_WrCE => enable_wrce_combo , --Store_addr_info_cmb , -- : in std_logic;
Rst_CS => rst_cs_cmb , -- : in std_logic;
Rst_Wr_CE => rst_wrce_cmb , -- : in std_logic;
Rst_Rd_CE => rst_rdce_cmb , -- : in std_logic;
Addr_SM_PS_IDLE => addr_sm_ps_IDLE_cmb , -- : in std_logic;
Addr_int => Addr_int_cmb , -- : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
RNW => rnw_cmb , -- : in std_logic;
RdFIFO_Space_two_int => RdFIFO_Space_two_int,
Bus2IP_CS => bus2ip_cs , -- out std_logic_vector((((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1)downto 0);
Bus2IP_RdCE => bus2ip_rdce , -- out std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)downto 0);
Bus2IP_WrCE => bus2ip_wrce , -- out std_logic_vector((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)downto 0);
ORed_cs => ORed_cs
);
-----------------------------------------------------------------------------
rd_fifo_data_in <= (IP2Bus_Data & (IP2Bus_Error and IP2Bus_RdAck)); -- & (last_data_cmb and IP2Bus_RdAck);
rd_fifo_wr_en <= (IP2Bus_RdAck and ORed_cs);
rd_fifo_rd_en <= (not fifo_empty) and S_AXI_MEM_RREADY;
rd_fifo_empty <= fifo_empty or (s_axi_mem_rvalid_reg and
S_AXI_MEM_RREADY and
last_fifo_data);
------------------------
-- RDATA_FIFO_I : read buffer
-----------------
RDATA_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_rbu_f
generic map (
C_DWIDTH => RD_DATA_FIFO_DWIDTH,
C_DEPTH => C_RDATA_FIFO_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => S_AXI_ACLK, -- in
--------------
Reset => active_high_rst, -- in
--------------
FIFO_Write => rd_fifo_wr_en, --IP2Bus_RdAck, -- rd_fifo_wr_en, -- in
Data_In => rd_fifo_data_in, -- in std_logic_vector
FIFO_Read => rd_fifo_rd_en, -- in
Data_Out => rd_fifo_out, -- out std_logic_vector
FIFO_Full => rd_fifo_full, -- out
FIFO_Empty => fifo_empty, -- out
Addr => open, -- out std_logic_vector
Num_To_Reread => ZEROES, -- in std_logic_vector
Underflow => open, -- out
Overflow => open -- out
);
rd_data_fifo_error <= rd_fifo_out(0);
s_axi_mem_rdata_i <= rd_fifo_out(RD_DATA_FIFO_DWIDTH-1 downto 1);
---------------
updn_cnt_en <= rd_fifo_rd_en xor rd_fifo_wr_en;
------------------------
-- UPDN_COUNTER_I : The below counter used to keep track of FIFO rd/wr
-- The counter is loaded with the max. value at reset
-------------------
UPDN_COUNTER_I : entity axi_emc_v3_0.counter_f
generic map(
C_NUM_BITS => COUNTER_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => S_AXI_ACLK, -- in
Rst => '0', -- in
Load_In => ALL_1, -- in
Count_Enable => updn_cnt_en, -- in
----------------
Count_Load => active_high_rst, -- in
----------------
Count_Down => rd_fifo_wr_en, -- in
Count_Out => cnt, -- out std_logic_vector
Carry_Out => open -- out
);
------------------------
no_space_in_fifo <= (or_reduce(cnt(COUNTER_WIDTH-1 downto 3)));
RDDATA_CNT_P1: process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK='1' then
if (S_AXI_ARESETN='0') then
RdFIFO_Space_two_int <= '1';
elsif (cnt(COUNTER_WIDTH-1)='0' and
cnt(COUNTER_WIDTH-2)='1' and
cnt(COUNTER_WIDTH-3)='0' and
cnt(COUNTER_WIDTH-4)='0' and
cnt(COUNTER_WIDTH-5)='0'
)then
RdFIFO_Space_two_int <= '0';
elsif(cnt(COUNTER_WIDTH-1)='1' and
cnt(COUNTER_WIDTH-2)='0' and
cnt(COUNTER_WIDTH-3)='0' and
cnt(COUNTER_WIDTH-4)='0' and
cnt(COUNTER_WIDTH-5)='0'
)then
RdFIFO_Space_two_int <= '1';
end if;
end if;
end process RDDATA_CNT_P1;
---------------
------------------------
-- RDDATA_CNT_P : read data counter from AXI side
------------------------
RDDATA_CNT_P: process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK='1' then
if (S_AXI_ARESETN='0') then
rd_data_count <= (others => '0');
elsif (store_addr_info_cmb='1') then
rd_data_count <= S_AXI_MEM_ARLEN;
elsif ((s_axi_mem_rvalid_reg='1') and (S_AXI_MEM_RREADY='1')) then
rd_data_count <= (rd_data_count - '1');
end if;
end if;
end process RDDATA_CNT_P;
last_rd_data_cmb <= not(or_reduce(rd_data_count));
-----------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ALIGN_BYTE_ENABLE_DWTH_32_GEN: Generate the below logic for 32 bit dwidth
----------------------------------
ALIGN_BYTE_ENABLE_DWTH_32_GEN: if (C_S_AXI_MEM_DATA_WIDTH = 32) generate
------------------------------
----------------------------------------------------------------------------
-- be_generate_32 : This function returns byte_enables for the 32 bit dwidth
----------------------------------------------------------------------------
function be_generate_32 (addr_bits : std_logic_vector(1 downto 0);
size : std_logic_vector(1 downto 0))
return std_logic_vector is
variable int_bus2ip_be : std_logic_vector(3 downto 0):= (others => '0');
-----
begin
-----
int_bus2ip_be(0) := size(1) or
(
((not addr_bits(1)) and (not size(1)))
and
(not addr_bits(0) or size(0))
);
int_bus2ip_be(1) := size(1) or
(
((not addr_bits(1)) and (not size(1)))
and
(addr_bits(0) or size(0))
);
int_bus2ip_be(2) := size(1) or
(
(addr_bits(1) and (not size(1)))
and
((not addr_bits(0)) or size(0))
);
int_bus2ip_be(3) := size(1) or
(
(addr_bits(1) and (not size(1)))
and
(addr_bits(0) or size(0))
);
-- coverage off
return int_bus2ip_be;
-- coverage on
end function be_generate_32;
-----------------------------------------------------------------------------
------------------------------
begin
-------------------------
-- RD_ADDR_ALIGN_BE_32_P: the below logic generates the byte enables for
-- 32 bit data width
-------------------------
RD_ADDR_ALIGN_BE_32_P: process(store_addr_info_cmb,
size_cmb,
S_AXI_MEM_ARADDR(1 downto 0),
IP2Bus_AddrAck,
derived_size_reg,
bus2ip_BE_reg
)is
begin
if(store_addr_info_cmb = '1')then
Bus2ip_BE_cmb <= be_generate_32(S_AXI_MEM_ARADDR(1 downto 0),size_cmb);
elsif (IP2Bus_AddrAck = '1')then
case derived_size_reg is
when "00" => -- byte
Bus2ip_BE_cmb <= bus2ip_BE_reg(2 downto 0) & bus2ip_BE_reg(3);
when "01" => -- half word
Bus2ip_BE_cmb <= bus2ip_BE_reg(1 downto 0) &
bus2ip_BE_reg(3 downto 2);
-- coverage off
when others => Bus2ip_BE_cmb <= "1111";
-- coverage on
end case;
else
Bus2ip_BE_cmb <= bus2ip_BE_reg;
end if;
end process RD_ADDR_ALIGN_BE_32_P;
----------------------------------
end generate ALIGN_BYTE_ENABLE_DWTH_32_GEN;
------------------------------- ------------
------------------------------------------------------------------------------
-- ALIGN_BYTE_ENABLE_DWTH_64_GEN: Generate the below logic for 32 bit dwidth
----------------------------------
ALIGN_BYTE_ENABLE_DWTH_64_GEN: if (C_S_AXI_MEM_DATA_WIDTH = 64) generate
-------------------------
-- function declaration
---------------------------------------------------------------------------
-- be_generate_64 : To generate the Byte Enable w.r.t size and address
---------------------------------------------------------------------------
function be_generate_64 (addr_bits : std_logic_vector(2 downto 0);
size : std_logic_vector(1 downto 0))
return std_logic_vector is
variable int_bus2ip_be : std_logic_vector(7 downto 0):= (others => '0');
-----
begin
-----
int_bus2ip_be(0) :=(size(1) and (size(0) or ((not size(0)) and
(not addr_bits(2))))) or
((not size(1)) and
(not addr_bits(2)) and
(not addr_bits(1)) and
(size(0) or ((not size(0)) and (not addr_bits(0))))
);
int_bus2ip_be(1) :=(size(1) and (size(0) or ((not size(0)) and
(not addr_bits(2))))) or
((not size(1)) and
(not addr_bits(2)) and
(not addr_bits(1)) and
(size(0) or ((not size(0)) and addr_bits(0)))
);
int_bus2ip_be(2) := (size(1) and (size(0) or ((not size(0)) and
(not addr_bits(2))))) or
((not size(1)) and
(not addr_bits(2)) and
addr_bits(1) and
(size(0) or ((not size(0)) and (not addr_bits(0))))
);
int_bus2ip_be(3) := (size(1) and (size(0) or ((not size(0)) and
(not addr_bits(2))))) or
((not size(1)) and
(not addr_bits(2)) and
addr_bits(1) and
(size(0) or ((not size(0)) and addr_bits(0)))
);
int_bus2ip_be(4) := (size(1) and (size(0) or ((not size(0)) and
addr_bits(2)))) or
((not size(1)) and
(not addr_bits(1)) and
addr_bits(2) and
(size(0) or ((not size(0)) and (not addr_bits(0))))
);
int_bus2ip_be(5) := (size(1) and (size(0) or ((not size(0)) and
addr_bits(2)))) or
((not size(1)) and
(not addr_bits(1)) and
addr_bits(2) and
(size(0) or ((not size(0)) and addr_bits(0)))
);
int_bus2ip_be(6) := (size(1) and (size(0) or ((not size(0)) and
addr_bits(2)))) or
((not size(1)) and
addr_bits(1) and
addr_bits(2) and
(size(0) or ((not size(0)) and (not addr_bits(0))))
);
int_bus2ip_be(7) := (size(1) and (size(0) or ((not size(0)) and
addr_bits(2)))) or
((not size(1)) and
addr_bits(1) and
addr_bits(2) and
(size(0) or ((not size(0)) and addr_bits(0)))
);
-- coverage off
return int_bus2ip_be;
-- coverage on
end function be_generate_64;
-----------------------------------------------------------------------------
-----
begin
-----
-- RD_ADDR_ALIGN_BE_64_P: The below logic generates the byte enables for
-- 64 bit data width
-------------------------
RD_ADDR_ALIGN_BE_64_P: process(store_addr_info_cmb,
size_cmb,
S_AXI_MEM_ARADDR(2 downto 0),
IP2Bus_AddrAck,
derived_size_reg,
Bus2ip_BE_reg
)is
begin
if(store_addr_info_cmb = '1')then
Bus2ip_BE_cmb <= be_generate_64(S_AXI_MEM_ARADDR(2 downto 0),size_cmb);
elsif (IP2Bus_AddrAck = '1')then
case derived_size_reg is
when "00" => -- byte
Bus2ip_BE_cmb <= bus2ip_BE_reg(6 downto 0) & bus2ip_BE_reg(7);
when "01" => -- half word
Bus2ip_BE_cmb <= bus2ip_BE_reg(5 downto 0) &
bus2ip_BE_reg(7 downto 6);
when "10" => -- half word
Bus2ip_BE_cmb <= bus2ip_BE_reg(3 downto 0) &
bus2ip_BE_reg(7 downto 4);
-- coverage off
when others => Bus2ip_BE_cmb <= (others => '1');
-- coverage on
end case;
else
Bus2ip_BE_cmb <= bus2ip_BE_reg;
end if;
end process RD_ADDR_ALIGN_BE_64_P;
-------------------------------
end generate ALIGN_BYTE_ENABLE_DWTH_64_GEN;
------------------------
--end generate OLD_LOGIC_GEN;
end architecture imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/msh_cnt.vhd
|
4
|
15466
|
-------------------------------------------------------------------------------
-- msh_cnt - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : msh_cnt.vhd
-- Version : v2.0
-- Description : A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the Rst signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_ADD_SUB_NOT -- 1 = Arith Add, 0 = Arith Substract
-- C_REG_WIDTH -- Width of data
-- C_RESET_VALUE -- Default value for the operation. Must be specified.
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Q -- Counter data out
-- Z -- Indicates '0' when decrementing
-- LD -- Counter load data
-- AD -- Counter load arithmatic data
-- LOAD -- Counter load enable
-- OP -- Counter arith operation enable
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity msh_cnt is
generic
(
-----------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
-----------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
-----------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector
-----------------------------------------------------------------------
);
port
(
Clk : in std_logic;
Rst : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
Z : out std_logic; -- indicates 0 when decrementing
LD : in std_logic_vector(0 to C_REG_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_REG_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end msh_cnt;
architecture imp of msh_cnt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MULT_AND
port
(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic
);
end component;
component MUXCY_L is
port
(
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic
);
end component MUXCY_L;
component XORCY is
port
(
LI : in std_logic;
CI : in std_logic;
O : out std_logic
);
end component XORCY;
component FDRE is
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i : std_logic_vector(0 to C_REG_WIDTH-1);
signal q_i_ns : std_logic_vector(0 to C_REG_WIDTH-1);
signal xorcy_out : std_logic_vector(0 to C_REG_WIDTH-1);
signal gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
signal z_i : std_logic;
begin
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, ClkEn : std_logic;
begin
-----------------------------------------------------------------------
-- Assign to load_bit the bit from input port LD.
-----------------------------------------------------------------------
load_bit <= LD(j);
-----------------------------------------------------------------------
-- Assign to arith_bit the bit from input port AD.
-----------------------------------------------------------------------
arith_bit <= AD(j);
-----------------------------------------------------------------------
-- LUT output generation.
-- Adder case
-----------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
-----------------------------------------------------------------------
-- Subtractor case
-----------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
-----------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
-----------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map
(
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
-----------------------------------------------------------------------
-- Propagate the carry (borrow) out.
-----------------------------------------------------------------------
MUXCY_L_i1: MUXCY_L
port map
(
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
LO => cry(j)
);
-----------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
-----------------------------------------------------------------------
XORCY_i1: XORCY
port map
(
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
STOP_AT_0_SUB: if not C_ADD_SUB_NOT generate
ClkEn <= (LOAD or OP) when (not (conv_integer(q_i) = 0)) else '0';
end generate STOP_AT_0_SUB;
STOP_AT_MSB_ADD : if C_ADD_SUB_NOT generate
ClkEn <= LOAD or OP;
end generate STOP_AT_MSB_ADD;
-----------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
-----------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map
(
Q => q_i(j),
C => Clk,
CE => ClkEn,
D => xorcy_out(j),
R => Rst
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map
(
Q => q_i(j),
C => Clk,
CE => ClkEn,
D => xorcy_out(j),
S => Rst
);
end generate;
end generate;
z_i <= '1' when ((conv_integer(q_i) = 1)) else '0';
z_ff: FDSE
port map
(
Q => Z,
C => Clk,
CE => '1',
D => z_i,
S => Rst
);
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/deferral.vhd
|
4
|
10729
|
-------------------------------------------------------------------------------
-- deferral - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : deferral.vhd
-- Version : v2.0
-- Description : This file contains the transmit deferral control.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- TxEn -- Transmit enable
-- Txrst -- Transmit reset
-- Tx_clk_en -- Transmit clock enable
-- BackingOff -- Backing off
-- Crs -- Carrier sense
-- Full_half_n -- Full/Half duplex indicator
-- Ifgp1 -- Interframe gap delay
-- Ifgp2 -- Interframe gap delay
-- Deferring -- Deffering for the tx data
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity deferral is
port
(
Clk : in std_logic;
Rst : in std_logic;
TxEn : in std_logic;
Txrst : in std_logic;
Tx_clk_en : in std_logic;
BackingOff : in std_logic;
Crs : in std_logic;
Full_half_n : in std_logic;
Ifgp1 : in std_logic_vector(0 to 4);
Ifgp2 : in std_logic_vector(0 to 4);
Deferring : out std_logic
);
end deferral;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of deferral is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal cntrLd_i : std_logic;
signal cntrEn : std_logic;
signal comboCntrEn : std_logic;
signal comboCntrEn2 : std_logic;
signal ifgp1_zero : std_logic;
signal ifgp2_zero : std_logic;
signal comboRst : std_logic;
begin
comboRst <= Rst or Txrst;
comboCntrEn <= Tx_clk_en and cntrEn;
comboCntrEn2 <= Tx_clk_en and cntrEn and ifgp1_zero;
-------------------------------------------------------------------------------
-- Ifgp1 counter
-------------------------------------------------------------------------------
inst_ifgp1_count: entity axi_ethernetlite_v3_0.cntr5bit
port map
(
Clk => Clk,
Rst => comboRst,
En => comboCntrEn,
Ld => cntrLd_i,
Load_in => Ifgp1,
Zero => ifgp1_zero
);
-------------------------------------------------------------------------------
-- Ifgp2 counter
-------------------------------------------------------------------------------
inst_ifgp2_count: entity axi_ethernetlite_v3_0.cntr5bit
port map
(
Clk => Clk,
Rst => comboRst,
En => comboCntrEn2,
Ld => cntrLd_i,
Load_in => Ifgp2,
Zero => ifgp2_zero
);
-------------------------------------------------------------------------------
-- deferral state machine
-------------------------------------------------------------------------------
inst_deferral_state: entity axi_ethernetlite_v3_0.defer_state
port map
(
Clk => Clk,
Rst => Rst,
TxEn => TxEn,
Txrst => Txrst,
Ifgp2Done => ifgp2_zero,
Ifgp1Done => ifgp1_zero,
BackingOff => BackingOff,
Crs => Crs,
Full_half_n => Full_half_n,
Deferring => Deferring,
CntrEnbl => cntrEn,
CntrLd => cntrLd_i
);
end implementation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_axi_emc_0_0/synth/design_1_axi_emc_0_0.vhd
|
2
|
25551
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_emc:3.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_emc_v3_0;
USE axi_emc_v3_0.axi_emc;
ENTITY design_1_axi_emc_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
rdclk : IN STD_LOGIC;
s_axi_mem_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_awlock : IN STD_LOGIC;
s_axi_mem_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awvalid : IN STD_LOGIC;
s_axi_mem_awready : OUT STD_LOGIC;
s_axi_mem_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_wlast : IN STD_LOGIC;
s_axi_mem_wvalid : IN STD_LOGIC;
s_axi_mem_wready : OUT STD_LOGIC;
s_axi_mem_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_bvalid : OUT STD_LOGIC;
s_axi_mem_bready : IN STD_LOGIC;
s_axi_mem_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_arlock : IN STD_LOGIC;
s_axi_mem_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arvalid : IN STD_LOGIC;
s_axi_mem_arready : OUT STD_LOGIC;
s_axi_mem_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_rlast : OUT STD_LOGIC;
s_axi_mem_rvalid : OUT STD_LOGIC;
s_axi_mem_rready : IN STD_LOGIC;
mem_dq_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_ce : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_cen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_oen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_wen : OUT STD_LOGIC;
mem_ben : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_qwen : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_rpn : OUT STD_LOGIC;
mem_adv_ldn : OUT STD_LOGIC;
mem_lbon : OUT STD_LOGIC;
mem_cken : OUT STD_LOGIC;
mem_rnw : OUT STD_LOGIC;
mem_cre : OUT STD_LOGIC;
mem_wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_axi_emc_0_0;
ARCHITECTURE design_1_axi_emc_0_0_arch OF design_1_axi_emc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_emc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_AXI_CLK_PERIOD_PS : INTEGER;
C_LFLASH_PERIOD_PS : INTEGER;
C_LINEAR_FLASH_SYNC_BURST : INTEGER;
C_S_AXI_REG_ADDR_WIDTH : INTEGER;
C_S_AXI_REG_DATA_WIDTH : INTEGER;
C_S_AXI_EN_REG : INTEGER;
C_S_AXI_MEM_ADDR_WIDTH : INTEGER;
C_S_AXI_MEM_DATA_WIDTH : INTEGER;
C_S_AXI_MEM_ID_WIDTH : INTEGER;
C_S_AXI_MEM0_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM0_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM1_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM1_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM2_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM2_HIGHADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM3_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI_MEM3_HIGHADDR : STD_LOGIC_VECTOR;
C_INCLUDE_NEGEDGE_IOREGS : INTEGER;
C_NUM_BANKS_MEM : INTEGER;
C_MEM0_TYPE : INTEGER;
C_MEM1_TYPE : INTEGER;
C_MEM2_TYPE : INTEGER;
C_MEM3_TYPE : INTEGER;
C_MEM0_WIDTH : INTEGER;
C_MEM1_WIDTH : INTEGER;
C_MEM2_WIDTH : INTEGER;
C_MEM3_WIDTH : INTEGER;
C_MAX_MEM_WIDTH : INTEGER;
C_PARITY_TYPE_MEM_0 : INTEGER;
C_PARITY_TYPE_MEM_1 : INTEGER;
C_PARITY_TYPE_MEM_2 : INTEGER;
C_PARITY_TYPE_MEM_3 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_0 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_1 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_2 : INTEGER;
C_INCLUDE_DATAWIDTH_MATCHING_3 : INTEGER;
C_SYNCH_PIPEDELAY_0 : INTEGER;
C_TCEDV_PS_MEM_0 : INTEGER;
C_TAVDV_PS_MEM_0 : INTEGER;
C_TPACC_PS_FLASH_0 : INTEGER;
C_THZCE_PS_MEM_0 : INTEGER;
C_THZOE_PS_MEM_0 : INTEGER;
C_TWC_PS_MEM_0 : INTEGER;
C_TWP_PS_MEM_0 : INTEGER;
C_TWPH_PS_MEM_0 : INTEGER;
C_TLZWE_PS_MEM_0 : INTEGER;
C_WR_REC_TIME_MEM_0 : INTEGER;
C_SYNCH_PIPEDELAY_1 : INTEGER;
C_TCEDV_PS_MEM_1 : INTEGER;
C_TAVDV_PS_MEM_1 : INTEGER;
C_TPACC_PS_FLASH_1 : INTEGER;
C_THZCE_PS_MEM_1 : INTEGER;
C_THZOE_PS_MEM_1 : INTEGER;
C_TWC_PS_MEM_1 : INTEGER;
C_TWP_PS_MEM_1 : INTEGER;
C_TWPH_PS_MEM_1 : INTEGER;
C_TLZWE_PS_MEM_1 : INTEGER;
C_WR_REC_TIME_MEM_1 : INTEGER;
C_SYNCH_PIPEDELAY_2 : INTEGER;
C_TCEDV_PS_MEM_2 : INTEGER;
C_TAVDV_PS_MEM_2 : INTEGER;
C_TPACC_PS_FLASH_2 : INTEGER;
C_THZCE_PS_MEM_2 : INTEGER;
C_THZOE_PS_MEM_2 : INTEGER;
C_TWC_PS_MEM_2 : INTEGER;
C_TWP_PS_MEM_2 : INTEGER;
C_TWPH_PS_MEM_2 : INTEGER;
C_TLZWE_PS_MEM_2 : INTEGER;
C_WR_REC_TIME_MEM_2 : INTEGER;
C_SYNCH_PIPEDELAY_3 : INTEGER;
C_TCEDV_PS_MEM_3 : INTEGER;
C_TAVDV_PS_MEM_3 : INTEGER;
C_TPACC_PS_FLASH_3 : INTEGER;
C_THZCE_PS_MEM_3 : INTEGER;
C_THZOE_PS_MEM_3 : INTEGER;
C_TWC_PS_MEM_3 : INTEGER;
C_TWP_PS_MEM_3 : INTEGER;
C_TWPH_PS_MEM_3 : INTEGER;
C_TLZWE_PS_MEM_3 : INTEGER;
C_WR_REC_TIME_MEM_3 : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
rdclk : IN STD_LOGIC;
s_axi_reg_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_reg_awvalid : IN STD_LOGIC;
s_axi_reg_awready : OUT STD_LOGIC;
s_axi_reg_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_reg_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_reg_wvalid : IN STD_LOGIC;
s_axi_reg_wready : OUT STD_LOGIC;
s_axi_reg_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_reg_bvalid : OUT STD_LOGIC;
s_axi_reg_bready : IN STD_LOGIC;
s_axi_reg_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_reg_arvalid : IN STD_LOGIC;
s_axi_reg_arready : OUT STD_LOGIC;
s_axi_reg_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_reg_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_reg_rvalid : OUT STD_LOGIC;
s_axi_reg_rready : IN STD_LOGIC;
s_axi_mem_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_awlock : IN STD_LOGIC;
s_axi_mem_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_awvalid : IN STD_LOGIC;
s_axi_mem_awready : OUT STD_LOGIC;
s_axi_mem_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_wlast : IN STD_LOGIC;
s_axi_mem_wvalid : IN STD_LOGIC;
s_axi_mem_wready : OUT STD_LOGIC;
s_axi_mem_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_bvalid : OUT STD_LOGIC;
s_axi_mem_bready : IN STD_LOGIC;
s_axi_mem_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_mem_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_arlock : IN STD_LOGIC;
s_axi_mem_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_mem_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_mem_arvalid : IN STD_LOGIC;
s_axi_mem_arready : OUT STD_LOGIC;
s_axi_mem_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_mem_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_mem_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_mem_rlast : OUT STD_LOGIC;
s_axi_mem_rvalid : OUT STD_LOGIC;
s_axi_mem_rready : IN STD_LOGIC;
mem_dq_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
mem_dq_parity_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_dq_parity_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_dq_parity_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
mem_ce : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_cen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_oen : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
mem_wen : OUT STD_LOGIC;
mem_ben : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_qwen : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mem_rpn : OUT STD_LOGIC;
mem_adv_ldn : OUT STD_LOGIC;
mem_lbon : OUT STD_LOGIC;
mem_cken : OUT STD_LOGIC;
mem_rnw : OUT STD_LOGIC;
mem_cre : OUT STD_LOGIC;
mem_wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_emc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "axi_emc,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_emc_0_0_arch : ARCHITECTURE IS "design_1_axi_emc_0_0,axi_emc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_emc_0_0_arch: ARCHITECTURE IS "design_1_axi_emc_0_0,axi_emc,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_emc,x_ipVersion=3.0,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_emc_inst,C_AXI_CLK_PERIOD_PS=10000,C_LFLASH_PERIOD_PS=10000,C_LINEAR_FLASH_SYNC_BURST=0,C_S_AXI_REG_ADDR_WIDTH=5,C_S_AXI_REG_DATA_WIDTH=32,C_S_AXI_EN_REG=0,C_S_AXI_MEM_ADDR_WIDTH=32,C_S_AXI_MEM_DATA_WIDTH=32,C_S_AXI_MEM_ID_WIDTH=1,C_S_AXI_MEM0_BASEADDR=0x60000000,C_S_AXI_MEM0_HIGHADDR=0x60FFFFFF,C_S_AXI_MEM1_BASEADDR=0xB0000000,C_S_AXI_MEM1_HIGHADDR=0xBFFFFFFF,C_S_AXI_MEM2_BASEADDR=0xC0000000,C_S_AXI_MEM2_HIGHADDR=0xCFFFFFFF,C_S_AXI_MEM3_BASEADDR=0xD0000000,C_S_AXI_MEM3_HIGHADDR=0xDFFFFFFF,C_INCLUDE_NEGEDGE_IOREGS=0,C_NUM_BANKS_MEM=1,C_MEM0_TYPE=1,C_MEM1_TYPE=0,C_MEM2_TYPE=0,C_MEM3_TYPE=0,C_MEM0_WIDTH=16,C_MEM1_WIDTH=16,C_MEM2_WIDTH=16,C_MEM3_WIDTH=16,C_MAX_MEM_WIDTH=16,C_PARITY_TYPE_MEM_0=0,C_PARITY_TYPE_MEM_1=0,C_PARITY_TYPE_MEM_2=0,C_PARITY_TYPE_MEM_3=0,C_INCLUDE_DATAWIDTH_MATCHING_0=1,C_INCLUDE_DATAWIDTH_MATCHING_1=1,C_INCLUDE_DATAWIDTH_MATCHING_2=1,C_INCLUDE_DATAWIDTH_MATCHING_3=1,C_SYNCH_PIPEDELAY_0=1,C_TCEDV_PS_MEM_0=70000,C_TAVDV_PS_MEM_0=70000,C_TPACC_PS_FLASH_0=70000,C_THZCE_PS_MEM_0=8000,C_THZOE_PS_MEM_0=8000,C_TWC_PS_MEM_0=85000,C_TWP_PS_MEM_0=55000,C_TWPH_PS_MEM_0=10000,C_TLZWE_PS_MEM_0=0,C_WR_REC_TIME_MEM_0=27000,C_SYNCH_PIPEDELAY_1=1,C_TCEDV_PS_MEM_1=15000,C_TAVDV_PS_MEM_1=15000,C_TPACC_PS_FLASH_1=25000,C_THZCE_PS_MEM_1=7000,C_THZOE_PS_MEM_1=7000,C_TWC_PS_MEM_1=15000,C_TWP_PS_MEM_1=12000,C_TWPH_PS_MEM_1=12000,C_TLZWE_PS_MEM_1=0,C_WR_REC_TIME_MEM_1=27000,C_SYNCH_PIPEDELAY_2=1,C_TCEDV_PS_MEM_2=15000,C_TAVDV_PS_MEM_2=15000,C_TPACC_PS_FLASH_2=25000,C_THZCE_PS_MEM_2=7000,C_THZOE_PS_MEM_2=7000,C_TWC_PS_MEM_2=15000,C_TWP_PS_MEM_2=12000,C_TWPH_PS_MEM_2=12000,C_TLZWE_PS_MEM_2=0,C_WR_REC_TIME_MEM_2=27000,C_SYNCH_PIPEDELAY_3=1,C_TCEDV_PS_MEM_3=15000,C_TAVDV_PS_MEM_3=15000,C_TPACC_PS_FLASH_3=25000,C_THZCE_PS_MEM_3=7000,C_THZOE_PS_MEM_3=7000,C_TWC_PS_MEM_3=15000,C_TWP_PS_MEM_3=12000,C_TWPH_PS_MEM_3=12000,C_TLZWE_PS_MEM_3=0,C_WR_REC_TIME_MEM_3=27000}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF rdclk: SIGNAL IS "xilinx.com:signal:clock:1.0 rdclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_mem_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_MEM RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_i: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_I";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_o: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_O";
ATTRIBUTE X_INTERFACE_INFO OF mem_dq_t: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF DQ_T";
ATTRIBUTE X_INTERFACE_INFO OF mem_a: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF ADDR";
ATTRIBUTE X_INTERFACE_INFO OF mem_ce: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CE";
ATTRIBUTE X_INTERFACE_INFO OF mem_cen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CE_N";
ATTRIBUTE X_INTERFACE_INFO OF mem_oen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF OEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_wen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF WEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_ben: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF BEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_qwen: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF QWEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_rpn: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF RPN";
ATTRIBUTE X_INTERFACE_INFO OF mem_adv_ldn: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF ADV_LDN";
ATTRIBUTE X_INTERFACE_INFO OF mem_lbon: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF LBON";
ATTRIBUTE X_INTERFACE_INFO OF mem_cken: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CLKEN";
ATTRIBUTE X_INTERFACE_INFO OF mem_rnw: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF RNW";
ATTRIBUTE X_INTERFACE_INFO OF mem_cre: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF CRE";
ATTRIBUTE X_INTERFACE_INFO OF mem_wait: SIGNAL IS "xilinx.com:interface:emc:1.0 EMC_INTF WAIT";
BEGIN
U0 : axi_emc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_emc_inst",
C_AXI_CLK_PERIOD_PS => 10000,
C_LFLASH_PERIOD_PS => 10000,
C_LINEAR_FLASH_SYNC_BURST => 0,
C_S_AXI_REG_ADDR_WIDTH => 5,
C_S_AXI_REG_DATA_WIDTH => 32,
C_S_AXI_EN_REG => 0,
C_S_AXI_MEM_ADDR_WIDTH => 32,
C_S_AXI_MEM_DATA_WIDTH => 32,
C_S_AXI_MEM_ID_WIDTH => 1,
C_S_AXI_MEM0_BASEADDR => X"60000000",
C_S_AXI_MEM0_HIGHADDR => X"60FFFFFF",
C_S_AXI_MEM1_BASEADDR => X"B0000000",
C_S_AXI_MEM1_HIGHADDR => X"BFFFFFFF",
C_S_AXI_MEM2_BASEADDR => X"C0000000",
C_S_AXI_MEM2_HIGHADDR => X"CFFFFFFF",
C_S_AXI_MEM3_BASEADDR => X"D0000000",
C_S_AXI_MEM3_HIGHADDR => X"DFFFFFFF",
C_INCLUDE_NEGEDGE_IOREGS => 0,
C_NUM_BANKS_MEM => 1,
C_MEM0_TYPE => 1,
C_MEM1_TYPE => 0,
C_MEM2_TYPE => 0,
C_MEM3_TYPE => 0,
C_MEM0_WIDTH => 16,
C_MEM1_WIDTH => 16,
C_MEM2_WIDTH => 16,
C_MEM3_WIDTH => 16,
C_MAX_MEM_WIDTH => 16,
C_PARITY_TYPE_MEM_0 => 0,
C_PARITY_TYPE_MEM_1 => 0,
C_PARITY_TYPE_MEM_2 => 0,
C_PARITY_TYPE_MEM_3 => 0,
C_INCLUDE_DATAWIDTH_MATCHING_0 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_1 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => 1,
C_INCLUDE_DATAWIDTH_MATCHING_3 => 1,
C_SYNCH_PIPEDELAY_0 => 1,
C_TCEDV_PS_MEM_0 => 70000,
C_TAVDV_PS_MEM_0 => 70000,
C_TPACC_PS_FLASH_0 => 70000,
C_THZCE_PS_MEM_0 => 8000,
C_THZOE_PS_MEM_0 => 8000,
C_TWC_PS_MEM_0 => 85000,
C_TWP_PS_MEM_0 => 55000,
C_TWPH_PS_MEM_0 => 10000,
C_TLZWE_PS_MEM_0 => 0,
C_WR_REC_TIME_MEM_0 => 27000,
C_SYNCH_PIPEDELAY_1 => 1,
C_TCEDV_PS_MEM_1 => 15000,
C_TAVDV_PS_MEM_1 => 15000,
C_TPACC_PS_FLASH_1 => 25000,
C_THZCE_PS_MEM_1 => 7000,
C_THZOE_PS_MEM_1 => 7000,
C_TWC_PS_MEM_1 => 15000,
C_TWP_PS_MEM_1 => 12000,
C_TWPH_PS_MEM_1 => 12000,
C_TLZWE_PS_MEM_1 => 0,
C_WR_REC_TIME_MEM_1 => 27000,
C_SYNCH_PIPEDELAY_2 => 1,
C_TCEDV_PS_MEM_2 => 15000,
C_TAVDV_PS_MEM_2 => 15000,
C_TPACC_PS_FLASH_2 => 25000,
C_THZCE_PS_MEM_2 => 7000,
C_THZOE_PS_MEM_2 => 7000,
C_TWC_PS_MEM_2 => 15000,
C_TWP_PS_MEM_2 => 12000,
C_TWPH_PS_MEM_2 => 12000,
C_TLZWE_PS_MEM_2 => 0,
C_WR_REC_TIME_MEM_2 => 27000,
C_SYNCH_PIPEDELAY_3 => 1,
C_TCEDV_PS_MEM_3 => 15000,
C_TAVDV_PS_MEM_3 => 15000,
C_TPACC_PS_FLASH_3 => 25000,
C_THZCE_PS_MEM_3 => 7000,
C_THZOE_PS_MEM_3 => 7000,
C_TWC_PS_MEM_3 => 15000,
C_TWP_PS_MEM_3 => 12000,
C_TWPH_PS_MEM_3 => 12000,
C_TLZWE_PS_MEM_3 => 0,
C_WR_REC_TIME_MEM_3 => 27000
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
rdclk => rdclk,
s_axi_reg_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axi_reg_awvalid => '0',
s_axi_reg_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_reg_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_reg_wvalid => '0',
s_axi_reg_bready => '0',
s_axi_reg_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axi_reg_arvalid => '0',
s_axi_reg_rready => '0',
s_axi_mem_awid => s_axi_mem_awid,
s_axi_mem_awaddr => s_axi_mem_awaddr,
s_axi_mem_awlen => s_axi_mem_awlen,
s_axi_mem_awsize => s_axi_mem_awsize,
s_axi_mem_awburst => s_axi_mem_awburst,
s_axi_mem_awlock => s_axi_mem_awlock,
s_axi_mem_awcache => s_axi_mem_awcache,
s_axi_mem_awprot => s_axi_mem_awprot,
s_axi_mem_awvalid => s_axi_mem_awvalid,
s_axi_mem_awready => s_axi_mem_awready,
s_axi_mem_wdata => s_axi_mem_wdata,
s_axi_mem_wstrb => s_axi_mem_wstrb,
s_axi_mem_wlast => s_axi_mem_wlast,
s_axi_mem_wvalid => s_axi_mem_wvalid,
s_axi_mem_wready => s_axi_mem_wready,
s_axi_mem_bid => s_axi_mem_bid,
s_axi_mem_bresp => s_axi_mem_bresp,
s_axi_mem_bvalid => s_axi_mem_bvalid,
s_axi_mem_bready => s_axi_mem_bready,
s_axi_mem_arid => s_axi_mem_arid,
s_axi_mem_araddr => s_axi_mem_araddr,
s_axi_mem_arlen => s_axi_mem_arlen,
s_axi_mem_arsize => s_axi_mem_arsize,
s_axi_mem_arburst => s_axi_mem_arburst,
s_axi_mem_arlock => s_axi_mem_arlock,
s_axi_mem_arcache => s_axi_mem_arcache,
s_axi_mem_arprot => s_axi_mem_arprot,
s_axi_mem_arvalid => s_axi_mem_arvalid,
s_axi_mem_arready => s_axi_mem_arready,
s_axi_mem_rid => s_axi_mem_rid,
s_axi_mem_rdata => s_axi_mem_rdata,
s_axi_mem_rresp => s_axi_mem_rresp,
s_axi_mem_rlast => s_axi_mem_rlast,
s_axi_mem_rvalid => s_axi_mem_rvalid,
s_axi_mem_rready => s_axi_mem_rready,
mem_dq_i => mem_dq_i,
mem_dq_o => mem_dq_o,
mem_dq_t => mem_dq_t,
mem_dq_parity_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
mem_a => mem_a,
mem_ce => mem_ce,
mem_cen => mem_cen,
mem_oen => mem_oen,
mem_wen => mem_wen,
mem_ben => mem_ben,
mem_qwen => mem_qwen,
mem_rpn => mem_rpn,
mem_adv_ldn => mem_adv_ldn,
mem_lbon => mem_lbon,
mem_cken => mem_cken,
mem_rnw => mem_rnw,
mem_cre => mem_cre,
mem_wait => mem_wait
);
END design_1_axi_emc_0_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/e1d42edc/hdl/src/vhdl/double_synchronizer.vhd
|
5
|
6181
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename : double_synchronizer.vhd
-- Version : v3.0
-- Description: The double_synchronizer is having the double flop synchronization logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author: NLR
-- History:
-- NLR 3/21/2011 Initial version
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*N"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- RESET_2 signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- counter signals: "*cntr*", "*count*"
-- ports: - Names in Uppercase
-- processes: "*_REG", "*_CMB"
-- component instantiations: "<ENTITY_>MODULE<#|_FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
library unisim;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity double_synchronizer is
generic (
C_DWIDTH : integer range 1 to 32 := 1
);
port (
CLK_2 : in std_logic;
RESET_2_n : in std_logic; -- active_low
DATA_IN : in std_logic_vector(C_DWIDTH-1 downto 0);
SYNC_DATA_OUT : out std_logic_vector(C_DWIDTH-1 downto 0)
);
end entity;
-------------------------------------------------------------------------------
architecture RTL of double_synchronizer is
signal RESET_2_p : std_logic;
signal data_in_d1 : std_logic_vector(C_DWIDTH-1 downto 0);
-----
begin
-----
-- active high Reset
RESET_2_p <= not RESET_2_n;
REG_GEN : for i in 0 to (C_DWIDTH - 1) generate
BLOCK_GEN: block
attribute ASYNC_REG : string;
attribute ASYNC_REG of FIRST_FLOP_i : label is "TRUE";
begin
FIRST_FLOP_i: component FDR
port map (
Q => data_in_d1(i),
C => CLK_2,
D => DATA_IN(i),
R => RESET_2_p
);
SECOND_FLOP_i: component FDR
port map (
Q => SYNC_DATA_OUT(i),
C => CLK_2,
D => data_in_d1(i),
R => RESET_2_p
);
end block BLOCK_GEN;
end generate REG_GEN;
-------------------------------------------------------------------------------
end RTL;
-------------------------------------------------------------------------------
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/876b8fe4/hdl/src/vhdl/axi_lite_ipif.vhd
|
16
|
14520
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/parity.vhd
|
4
|
10694
|
-------------------------------------------------------------------------------
-- parity.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
architecture IMP of Parity is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
component MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF8;
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_FPGA : if (C_TARGET /= RTL) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MB_MUXF8
generic map(
C_TARGET => C_TARGET)
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/synth/design_1_ilmb_bram_if_cntlr_0.vhd
|
2
|
13327
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_bram_if_cntlr_v4_0;
USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr;
ENTITY design_1_ilmb_bram_if_cntlr_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
);
END design_1_ilmb_bram_if_cntlr_0;
ARCHITECTURE design_1_ilmb_bram_if_cntlr_0_arch OF design_1_ilmb_bram_if_cntlr_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_bram_if_cntlr IS
GENERIC (
C_FAMILY : STRING;
C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_NUM_LMB : INTEGER;
C_MASK : STD_LOGIC_VECTOR(0 TO 31);
C_MASK1 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK2 : STD_LOGIC_VECTOR(0 TO 31);
C_MASK3 : STD_LOGIC_VECTOR(0 TO 31);
C_LMB_AWIDTH : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_ECC : INTEGER;
C_INTERCONNECT : INTEGER;
C_FAULT_INJECT : INTEGER;
C_CE_FAILING_REGISTERS : INTEGER;
C_UE_FAILING_REGISTERS : INTEGER;
C_ECC_STATUS_REGISTERS : INTEGER;
C_ECC_ONOFF_REGISTER : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER;
C_CE_COUNTER_WIDTH : INTEGER;
C_WRITE_ACCESS : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
LMB_Rst : IN STD_LOGIC;
LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_AddrStrobe : IN STD_LOGIC;
LMB_ReadStrobe : IN STD_LOGIC;
LMB_WriteStrobe : IN STD_LOGIC;
LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : OUT STD_LOGIC;
Sl_Wait : OUT STD_LOGIC;
Sl_UE : OUT STD_LOGIC;
Sl_CE : OUT STD_LOGIC;
LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB1_AddrStrobe : IN STD_LOGIC;
LMB1_ReadStrobe : IN STD_LOGIC;
LMB1_WriteStrobe : IN STD_LOGIC;
LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl1_Ready : OUT STD_LOGIC;
Sl1_Wait : OUT STD_LOGIC;
Sl1_UE : OUT STD_LOGIC;
Sl1_CE : OUT STD_LOGIC;
LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB2_AddrStrobe : IN STD_LOGIC;
LMB2_ReadStrobe : IN STD_LOGIC;
LMB2_WriteStrobe : IN STD_LOGIC;
LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl2_Ready : OUT STD_LOGIC;
Sl2_Wait : OUT STD_LOGIC;
Sl2_UE : OUT STD_LOGIC;
Sl2_CE : OUT STD_LOGIC;
LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
LMB3_AddrStrobe : IN STD_LOGIC;
LMB3_ReadStrobe : IN STD_LOGIC;
LMB3_WriteStrobe : IN STD_LOGIC;
LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
Sl3_Ready : OUT STD_LOGIC;
Sl3_Wait : OUT STD_LOGIC;
Sl3_UE : OUT STD_LOGIC;
Sl3_CE : OUT STD_LOGIC;
BRAM_Rst_A : OUT STD_LOGIC;
BRAM_Clk_A : OUT STD_LOGIC;
BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_EN_A : OUT STD_LOGIC;
BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
S_AXI_CTRL_ACLK : IN STD_LOGIC;
S_AXI_CTRL_ARESETN : IN STD_LOGIC;
S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_AWVALID : IN STD_LOGIC;
S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_CTRL_WVALID : IN STD_LOGIC;
S_AXI_CTRL_WREADY : OUT STD_LOGIC;
S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_BVALID : OUT STD_LOGIC;
S_AXI_CTRL_BREADY : IN STD_LOGIC;
S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_ARVALID : IN STD_LOGIC;
S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_CTRL_RVALID : OUT STD_LOGIC;
S_AXI_CTRL_RREADY : IN STD_LOGIC;
UE : OUT STD_LOGIC;
CE : OUT STD_LOGIC;
Interrupt : OUT STD_LOGIC
);
END COMPONENT lmb_bram_if_cntlr;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x20000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
BEGIN
U0 : lmb_bram_if_cntlr
GENERIC MAP (
C_FAMILY => "artix7",
C_HIGHADDR => X"00007FFF",
C_BASEADDR => X"00000000",
C_NUM_LMB => 1,
C_MASK => X"20000000",
C_MASK1 => X"00800000",
C_MASK2 => X"00800000",
C_MASK3 => X"00800000",
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_ECC => 0,
C_INTERCONNECT => 0,
C_FAULT_INJECT => 0,
C_CE_FAILING_REGISTERS => 0,
C_UE_FAILING_REGISTERS => 0,
C_ECC_STATUS_REGISTERS => 0,
C_ECC_ONOFF_REGISTER => 0,
C_ECC_ONOFF_RESET_VALUE => 1,
C_CE_COUNTER_WIDTH => 0,
C_WRITE_ACCESS => 2,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32
)
PORT MAP (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB_ABus => LMB_ABus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_BE => LMB_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB1_AddrStrobe => '0',
LMB1_ReadStrobe => '0',
LMB1_WriteStrobe => '0',
LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB2_AddrStrobe => '0',
LMB2_ReadStrobe => '0',
LMB2_WriteStrobe => '0',
LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB3_AddrStrobe => '0',
LMB3_ReadStrobe => '0',
LMB3_WriteStrobe => '0',
LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Din_A => BRAM_Din_A,
S_AXI_CTRL_ACLK => '0',
S_AXI_CTRL_ARESETN => '0',
S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_AWVALID => '0',
S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_CTRL_WVALID => '0',
S_AXI_CTRL_BREADY => '0',
S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_CTRL_ARVALID => '0',
S_AXI_CTRL_RREADY => '0'
);
END design_1_ilmb_bram_if_cntlr_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/e1d42edc/hdl/src/vhdl/shared_ram_ivar.vhd
|
4
|
8678
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/tx_statemachine.vhd
|
4
|
61222
|
-------------------------------------------------------------------------------
-- tx_statemachine - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : tx_statemachine.vhd
-- Version : v2.0
-- Description : This file contains the transmit control state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- TxClkEn -- Transmit clocl enable
-- Jam_rst -- Jam reset
-- TxRst -- Transmit reset
-- Deferring -- Deffering
-- ColRetryCnt -- Collision retry coun
-- ColWindowNibCnt -- Collision window nibble count
-- JamTxNibCnt -- TX Jam nibble count
-- TxNibbleCnt -- TX Nibble count
-- BusFifoWrNibbleCnt -- Bus FIFO write nibble count
-- CrcCnt -- CRC count
-- BusFifoFull -- Bus FIFO full
-- BusFifoEmpty -- Bus FIFO empty
-- PhyCollision -- Phy collision
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- InitBackoff -- Initialize back off
-- TxRetryRst -- TX retry reset
-- TxExcessDefrlRst -- TX excess defer reset
-- TxLateColnRst -- TX late collision reset
-- TxColRetryCntRst_n -- TX collision retry counter reset
-- TxColRetryCntEnbl -- TX collision retry counter enable
-- TxNibbleCntRst -- TX nibble counter reset
-- TxEnNibbleCnt -- TX nibble count
-- TxNibbleCntLd -- TX nibble counter load
-- BusFifoWrCntRst -- Bus FIFO write counter reset
-- BusFifoWrCntEn -- Bus FIFO write counter enable
-- EnblPre -- Enable Preamble
-- EnblSFD -- Enable SFD
-- EnblData -- Enable Data
-- EnblJam -- Enable Jam
-- EnblCRC -- Enable CRC
-- BusFifoWr -- Bus FIFO write enable
-- Phytx_en -- PHY transmit enable
-- TxCrcEn -- TX CRC enable
-- TxCrcShftOutEn -- TX CRC shift out enable
-- Tx_addr_en -- TX buffer address enable
-- Tx_start -- Trasnmit start
-- Tx_done -- Transmit done
-- Tx_idle -- Transmit idle
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Enblclear -- Enable clear
-- Transmit_start -- Transmit start
-- Mac_program_start -- MAC Program start
-- Mac_addr_ram_we -- MAC Address RAM write enable
-- Mac_addr_ram_addr_wr -- MAC Address RAM write address
-- Pre_sfd_done -- Pre SFD done
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity tx_statemachine is
generic
(
C_DUPLEX : integer := 1
-- 1 = full duplex, 0 = half duplex
);
port
(
Clk : in std_logic;
Rst : in std_logic;
TxClkEn : in std_logic;
Jam_rst : out std_logic;
TxRst : in std_logic;
Deferring : in std_logic;
ColRetryCnt : in std_logic_vector (0 to 4);
ColWindowNibCnt : in std_logic_vector (0 to 7);
JamTxNibCnt : in std_logic_vector (0 to 3);
TxNibbleCnt : in std_logic_vector (0 to 11);
BusFifoWrNibbleCnt : in std_logic_vector (0 to 11);
CrcCnt : in std_logic_vector (0 to 3);
BusFifoFull : in std_logic;
BusFifoEmpty : in std_logic;
PhyCollision : in std_logic;
Tx_pong_ping_l : in std_logic;
InitBackoff : out std_logic;
TxRetryRst : out std_logic;
TxExcessDefrlRst : out std_logic;
TxLateColnRst : out std_logic;
TxColRetryCntRst_n : out std_logic;
TxColRetryCntEnbl : out std_logic;
TxNibbleCntRst : out std_logic;
TxEnNibbleCnt : out std_logic;
TxNibbleCntLd : out std_logic;
BusFifoWrCntRst : out std_logic;
BusFifoWrCntEn : out std_logic;
EnblPre : out std_logic;
EnblSFD : out std_logic;
EnblData : out std_logic;
EnblJam : out std_logic;
EnblCRC : out std_logic;
BusFifoWr : out std_logic;
Phytx_en : out std_logic;
TxCrcEn : out std_logic;
TxCrcShftOutEn : out std_logic;
Tx_addr_en : out std_logic;
Tx_start : out std_logic;
Tx_done : out std_logic;
Tx_idle : out std_logic;
Tx_DPM_ce : out std_logic;
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Enblclear : out std_logic;
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Mac_addr_ram_we : out std_logic;
Mac_addr_ram_addr_wr : out std_logic_vector(0 to 3);
Pre_sfd_done : out std_logic
);
end tx_statemachine;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture implementation of tx_statemachine is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal idle : std_logic; -- state 0
signal lngthDelay1 : std_logic; -- state 5
signal lngthDelay2 : std_logic; -- state 6
signal ldLngthCntr : std_logic; -- state 7
signal preamble : std_logic; -- state 8
signal checkBusFifoFullSFD : std_logic; -- state 9
signal SFD : std_logic; -- state 10
signal checkBusFifoFull : std_logic; -- state 11
signal loadBusFifo : std_logic; -- state 12
signal checkCrc : std_logic; -- state 13
signal checkBusFifoFullCrc : std_logic; -- state 14
signal loadBusFifoCrc : std_logic; -- state 15
signal waitFifoEmpty : std_logic; -- state 16
signal txDone : std_logic; -- state 17
signal checkBusFifoFullJam : std_logic; -- state 18
signal loadBusFifoJam : std_logic; -- state 19
signal half_dup_error : std_logic; -- state 20
signal collisionRetry : std_logic; -- state 21
signal retryWaitFifoEmpty : std_logic; -- state 22
signal retryReset : std_logic; -- state 23
signal txDone2 : std_logic; -- state 24
signal txDonePause : std_logic; -- state 25
signal chgMacAdr1 : std_logic; -- state 26
signal chgMacAdr2 : std_logic; -- state 27
signal chgMacAdr3 : std_logic; -- state 28
signal chgMacAdr4 : std_logic; -- state 29
signal chgMacAdr5 : std_logic; -- state 30
signal chgMacAdr6 : std_logic; -- state 31
signal chgMacAdr7 : std_logic; -- state 32
signal chgMacAdr8 : std_logic; -- state 33
signal chgMacAdr9 : std_logic; -- state 34
signal chgMacAdr10 : std_logic; -- state 35
signal chgMacAdr11 : std_logic; -- state 36
signal chgMacAdr12 : std_logic; -- state 37
signal chgMacAdr13 : std_logic; -- state 38
signal chgMacAdr14 : std_logic; -- state 39
signal idle_D : std_logic; -- state 0
signal txLngthRdNib1_D : std_logic; -- state 1
signal lngthDelay1_D : std_logic; -- state 5
signal lngthDelay2_D : std_logic; -- state 6
signal ldLngthCntr_D : std_logic; -- state 7
signal preamble_D : std_logic; -- state 8
signal checkBusFifoFullSFD_D : std_logic; -- state 9
signal SFD_D : std_logic; -- state 10
signal checkBusFifoFull_D : std_logic; -- state 11
signal loadBusFifo_D : std_logic; -- state 12
signal checkCrc_D : std_logic; -- state 13
signal checkBusFifoFullCrc_D : std_logic; -- state 14
signal loadBusFifoCrc_D : std_logic; -- state 15
signal waitFifoEmpty_D : std_logic; -- state 16
signal txDone_D : std_logic; -- state 17
signal checkBusFifoFullJam_D : std_logic; -- state 18
signal loadBusFifoJam_D : std_logic; -- state 19
signal half_dup_error_D : std_logic; -- state 20
signal collisionRetry_D : std_logic; -- state 21
signal retryWaitFifoEmpty_D : std_logic; -- state 22
signal retryReset_D : std_logic; -- state 23
signal txDone2_D : std_logic; -- state 24
signal txDonePause_D : std_logic; -- state 25
signal chgMacAdr1_D : std_logic; -- state 26
signal chgMacAdr2_D : std_logic; -- state 27
signal chgMacAdr3_D : std_logic; -- state 28
signal chgMacAdr4_D : std_logic; -- state 29
signal chgMacAdr5_D : std_logic; -- state 30
signal chgMacAdr6_D : std_logic; -- state 31
signal chgMacAdr7_D : std_logic; -- state 32
signal chgMacAdr8_D : std_logic; -- state 33
signal chgMacAdr9_D : std_logic; -- state 34
signal chgMacAdr10_D : std_logic; -- state 35
signal chgMacAdr11_D : std_logic; -- state 36
signal chgMacAdr12_D : std_logic; -- state 37
signal chgMacAdr13_D : std_logic; -- state 38
signal chgMacAdr14_D : std_logic; -- state 39
signal txNibbleCntRst_i : std_logic;
signal txEnNibbleCnt_i : std_logic;
signal txNibbleCntLd_i : std_logic;
signal busFifoWr_i : std_logic;
signal phytx_en_i : std_logic;
signal phytx_en_i_n : std_logic;
signal txCrcEn_i : std_logic;
signal retrying_i : std_logic;
signal phytx_en_reg : std_logic;
signal busFifoWrCntRst_reg : std_logic;
signal retrying_reg : std_logic;
signal txCrcEn_reg : std_logic;
signal busFifoWrCntRst_i : std_logic;
signal state_machine_rst : std_logic;
signal full_half_n : std_logic;
signal goto_idle : std_logic; -- state 0
signal stay_idle : std_logic; -- state 0
signal goto_txLngthRdNib1_1 : std_logic; -- state 1
signal goto_txLngthRdNib1_2 : std_logic; -- state 1
signal goto_lngthDelay1 : std_logic; -- state 5
signal goto_lngthDelay2 : std_logic; -- state 6
signal goto_ldLngthCntr : std_logic; -- state 7
signal stay_ldLngthCntr : std_logic; -- state 7
signal goto_preamble : std_logic; -- state 8
signal stay_preamble : std_logic; -- state 8
signal goto_checkBusFifoFullSFD : std_logic; -- state 9
signal stay_checkBusFifoFullSFD : std_logic; -- state 9
signal goto_SFD : std_logic; -- state 10
signal stay_SFD : std_logic; -- state 10
signal goto_checkBusFifoFull_1 : std_logic; -- state 11
signal goto_checkBusFifoFull_2 : std_logic; -- state 11
signal stay_checkBusFifoFull : std_logic; -- state 11
signal goto_loadBusFifo : std_logic; -- state 12
signal goto_checkCrc : std_logic; -- state 13
signal goto_checkBusFifoFullCrc_1 : std_logic; -- state 14
signal goto_checkBusFifoFullCrc_2 : std_logic; -- state 14
signal stay_checkBusFifoFullCrc : std_logic; -- state 14
signal goto_loadBusFifoCrc_1 : std_logic; -- state 15
signal goto_waitFifoEmpty_2 : std_logic; -- state 16
signal stay_waitFifoEmpty : std_logic; -- state 16
signal goto_txDone_1 : std_logic; -- state 17
signal goto_txDone_2 : std_logic; -- state 17
signal goto_checkBusFifoFullJam_1 : std_logic; -- state 18
signal goto_checkBusFifoFullJam_2 : std_logic; -- state 18
signal stay_checkBusFifoFullJam : std_logic; -- state 18
signal goto_loadBusFifoJam : std_logic; -- state 19
signal goto_half_dup_error_1 : std_logic; -- state 20
signal goto_half_dup_error_2 : std_logic; -- state 20
signal goto_collisionRetry : std_logic; -- state 21
signal goto_retryWaitFifoEmpty : std_logic; -- state 22
signal stay_retryWaitFifoEmpty : std_logic; -- state 22
signal goto_retryReset : std_logic; -- state 23
signal goto_txDone2 : std_logic; -- state 24
signal goto_txDonePause : std_logic; -- state 25
signal goto_chgMacAdr1 : std_logic; -- state 26
signal goto_chgMacAdr2 : std_logic; -- state 27
signal goto_chgMacAdr3 : std_logic; -- state 28
signal goto_chgMacAdr4 : std_logic; -- state 29
signal goto_chgMacAdr5 : std_logic; -- state 30
signal goto_chgMacAdr6 : std_logic; -- state 31
signal goto_chgMacAdr7 : std_logic; -- state 32
signal goto_chgMacAdr8 : std_logic; -- state 33
signal goto_chgMacAdr9 : std_logic; -- state 34
signal goto_chgMacAdr10 : std_logic; -- state 35
signal goto_chgMacAdr11 : std_logic; -- state 36
signal goto_chgMacAdr12 : std_logic; -- state 37
signal goto_chgMacAdr13 : std_logic; -- state 38
signal goto_chgMacAdr14 : std_logic; -- state 39
signal txNibbleCnt_is_1 : std_logic;
signal busFifoWrNibbleCnt_is_14 : std_logic;
signal busFifoWrNibbleCnt_not_14 : std_logic;
signal busFifoWrNibbleCnt_is_15 : std_logic;
signal busFifoWrNibbleCnt_not_15 : std_logic;
signal crcCnt_not_0 : std_logic;
signal crcCnt_is_0 : std_logic;
signal jamTxNibCnt_not_0 : std_logic;
signal jamTxNibCnt_is_0 : std_logic;
signal colWindowNibCnt_not_0 : std_logic;
signal colWindowNibCnt_is_0 : std_logic;
signal colRetryCnt_is_15 : std_logic;
signal pre_SFD_zero : std_logic;
signal waitdone_pre_sfd : std_logic;
signal transmit_start_reg : std_logic;
signal mac_program_start_reg : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the tx state machine
component FDR
port
(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDS
port
(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
component FDRE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
Tx_DPM_wr_data <= (others => '0');
-- Trnasmit Done indicator
-- added txDone for ping pong control
Tx_done <= txDone and not retrying_reg;
-- Full/Half duplex indicator
full_half_n <= '1'when C_DUPLEX = 1 else '0';
-- Wait for Pre SFD
--waitdone_pre_sfd <= PhyCollision and not(full_half_n) and not(pre_sfd_zero);
Pre_sfd_done <= pre_SFD_zero;
-- PHY tx enable
phytx_en_i_n <= not(phytx_en_i);
----------------------------------------------------------------------------
-- Signal Assignment
----------------------------------------------------------------------------
TxNibbleCntRst <= txNibbleCntRst_i;
TxEnNibbleCnt <= txEnNibbleCnt_i;
TxNibbleCntLd <= txNibbleCntLd_i;
BusFifoWr <= busFifoWr_i;
Phytx_en <= phytx_en_i;
TxCrcEn <= txCrcEn_i;
BusFifoWrCntRst <= busFifoWrCntRst_i;
----------------------------------------------------------------------------
-- Pre SFD Counter
----------------------------------------------------------------------------
PRE_SFD_count: entity axi_ethernetlite_v3_0.cntr5bit
port map
(
cntout => open,
Clk => Clk,
Rst => Rst,
en => TxClkEn,
ld => phytx_en_i_n,
load_in => "10011",
zero => pre_SFD_zero
);
-- State machine reset
state_machine_rst <= Rst;
----------------------------------------------------------------------------
-- Counter enable generation
----------------------------------------------------------------------------
-- Transmit Nibble Counte=1
txNibbleCnt_is_1 <= not(TxNibbleCnt(0)) and not(TxNibbleCnt(1)) and
not(TxNibbleCnt(2)) and not(TxNibbleCnt(3)) and
not(TxNibbleCnt(4)) and not(TxNibbleCnt(5)) and
not(TxNibbleCnt(6)) and not(TxNibbleCnt(7)) and
not(TxNibbleCnt(8)) and not(TxNibbleCnt(9)) and
not(TxNibbleCnt(10))and TxNibbleCnt(11);
-- Bus FIFO write Nibble Counte=14
busFifoWrNibbleCnt_is_14 <= BusFifoWrNibbleCnt(8) and
BusFifoWrNibbleCnt(9) and
BusFifoWrNibbleCnt(10) and
not(BusFifoWrNibbleCnt(11));
-- Bus FIFO write Nibble Counte/=14
busFifoWrNibbleCnt_not_14 <= not(busFifoWrNibbleCnt_is_14);
-- Bus FIFO write Nibble Counte=15
busFifoWrNibbleCnt_is_15 <= (BusFifoWrNibbleCnt(8) and
BusFifoWrNibbleCnt(9) and
BusFifoWrNibbleCnt(10) and
BusFifoWrNibbleCnt(11));
-- Bus FIFO write Nibble Counte/=15
busFifoWrNibbleCnt_not_15 <= not(busFifoWrNibbleCnt_is_15);
-- CRC Count/=0
crcCnt_not_0 <= CrcCnt(0) or CrcCnt(1) or CrcCnt(2) or CrcCnt(3);
-- CRC Count=0
crcCnt_is_0 <= not crcCnt_not_0;
-- Jam Transmit Nibble count/=0
jamTxNibCnt_not_0 <= JamTxNibCnt(0) or JamTxNibCnt(1) or JamTxNibCnt(2) or
JamTxNibCnt(3);
-- Jam Transmit Nibble count=0
jamTxNibCnt_is_0 <= not(jamTxNibCnt_not_0);
-- Collision windo Nibble count/=0
colWindowNibCnt_not_0 <= ColWindowNibCnt(0) or ColWindowNibCnt(1) or
ColWindowNibCnt(2) or ColWindowNibCnt(3) or
ColWindowNibCnt(4) or ColWindowNibCnt(5) or
ColWindowNibCnt(6) or ColWindowNibCnt(7);
-- Collision windo Nibble count=0
colWindowNibCnt_is_0 <= not(colWindowNibCnt_not_0);
-- Collision retry count=15
colRetryCnt_is_15 <= not(ColRetryCnt(0)) and ColRetryCnt(1) and
ColRetryCnt(2) and ColRetryCnt(3) and
ColRetryCnt(4);
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
goto_idle <= txDonePause;
stay_idle <= idle and not(Transmit_start) and not Mac_program_start;
idle_D <= goto_idle or stay_idle;
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
STATE0A: FDS
port map
(
Q => idle, --[out]
C => Clk, --[in]
D => idle_D, --[in]
S => state_machine_rst --[in]
);
Tx_idle <= idle;
----------------------------------------------------------------------------
-- txLngthRdNib1 state
----------------------------------------------------------------------------
--goto_txLngthRdNib1_1 <= idle and Transmit_start and not transmit_start_reg;
goto_txLngthRdNib1_1 <= idle and
((transmit_start and not transmit_start_reg)
or
(transmit_start and retrying_reg));
goto_txLngthRdNib1_2 <= retryReset;
txLngthRdNib1_D <= goto_txLngthRdNib1_1 or goto_txLngthRdNib1_2;
goto_lngthDelay1 <= txLngthRdNib1_D;
----------------------------------------------------------------------------
-- lngthDelay1 state
----------------------------------------------------------------------------
lngthDelay1_D <= goto_lngthDelay1;
STATE5A: FDR
port map
(
Q => lngthDelay1, --[out]
C => Clk, --[in]
D => lngthDelay1_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- lngthDelay2 state
----------------------------------------------------------------------------
goto_lngthDelay2 <= lngthDelay1;
lngthDelay2_D <= goto_lngthDelay2;
STATE6A: FDR
port map
(
Q => lngthDelay2, --[out]
C => Clk, --[in]
D => lngthDelay2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- ldLngthCntr state
----------------------------------------------------------------------------
goto_ldLngthCntr <= lngthDelay1;
stay_ldLngthCntr <= ldLngthCntr and Deferring;
ldLngthCntr_D <= goto_ldLngthCntr or stay_ldLngthCntr;
STATE7A: FDR
port map
(
Q => ldLngthCntr, --[out]
C => Clk, --[in]
D => ldLngthCntr_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- preamble state
----------------------------------------------------------------------------
goto_preamble <= (ldLngthCntr and (not(Deferring)));
stay_preamble <= preamble and busFifoWrNibbleCnt_not_14;
preamble_D <= goto_preamble or stay_preamble;
STATE8A: FDR
port map
(
Q => preamble, --[out]
C => Clk, --[in]
D => preamble_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFullSFD state
----------------------------------------------------------------------------
goto_checkBusFifoFullSFD <= preamble and busFifoWrNibbleCnt_is_14;
stay_checkBusFifoFullSFD <= checkBusFifoFullSFD and BusFifoFull;
checkBusFifoFullSFD_D <= goto_checkBusFifoFullSFD or
stay_checkBusFifoFullSFD;
STATE9A: FDR
port map
(
Q => checkBusFifoFullSFD, --[out]
C => Clk, --[in]
D => checkBusFifoFullSFD_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- SFD state
----------------------------------------------------------------------------
goto_SFD <= checkBusFifoFullSFD and not (BusFifoFull);
stay_SFD <= SFD and busFifoWrNibbleCnt_not_15;
SFD_D <= goto_SFD or stay_SFD;
STATE10A: FDR
port map
(
Q => SFD, --[out]
C => Clk, --[in]
D => SFD_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFull state
----------------------------------------------------------------------------
goto_checkBusFifoFull_1 <= loadBusFifo and not(goto_checkCrc) and
not(goto_checkBusFifoFullJam_1);
goto_checkBusFifoFull_2 <= SFD and busFifoWrNibbleCnt_is_15;
stay_checkBusFifoFull <= checkBusFifoFull and BusFifoFull and
not (goto_checkBusFifoFullJam_1);
checkBusFifoFull_D <= goto_checkBusFifoFull_1 or
goto_checkBusFifoFull_2 or
stay_checkBusFifoFull;
STATE11A: FDR
port map
(
Q => checkBusFifoFull, --[out]
C => Clk, --[in]
D => checkBusFifoFull_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- loadBusFifo state
----------------------------------------------------------------------------
goto_loadBusFifo <= checkBusFifoFull and not(BusFifoFull) and
not(goto_checkCrc) and not(goto_checkBusFifoFullJam_1);
loadBusFifo_D <= goto_loadBusFifo;
STATE12A: FDR
port map
(
Q => loadBusFifo, --[out]
C => Clk, --[in]
D => loadBusFifo_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkCrc state
----------------------------------------------------------------------------
goto_checkCrc <= loadBusFifo and txNibbleCnt_is_1 and
not(goto_checkBusFifoFullJam_1);
checkCrc_D <= goto_checkCrc;
STATE13A: FDR
port map
(
Q => checkCrc, --[out]
C => Clk, --[in]
D => checkCrc_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFullCrc state
----------------------------------------------------------------------------
goto_checkBusFifoFullCrc_1 <= checkCrc and not(goto_checkBusFifoFullJam_1);
goto_checkBusFifoFullCrc_2 <= loadBusFifoCrc and
not(goto_checkBusFifoFullJam_1);
stay_checkBusFifoFullCrc <= checkBusFifoFullCrc and BusFifoFull and
not(goto_checkBusFifoFullJam_1);
checkBusFifoFullCrc_D <= goto_checkBusFifoFullCrc_1 or
goto_checkBusFifoFullCrc_2 or
stay_checkBusFifoFullCrc;
STATE14A: FDR
port map
(
Q => checkBusFifoFullCrc, --[out]
C => Clk, --[in]
D => checkBusFifoFullCrc_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- loadBusFifoCrc state
----------------------------------------------------------------------------
goto_loadBusFifoCrc_1 <= checkBusFifoFullCrc and not(BusFifoFull) and
crcCnt_not_0 and not(goto_checkBusFifoFullJam_1);
loadBusFifoCrc_D <= goto_loadBusFifoCrc_1;
STATE15A: FDR
port map
(
Q => loadBusFifoCrc, --[out]
C => Clk, --[in]
D => loadBusFifoCrc_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitFifoEmpty state
----------------------------------------------------------------------------
goto_waitFifoEmpty_2 <= checkBusFifoFullCrc and crcCnt_is_0 and
not(BusFifoFull) and not(goto_checkBusFifoFullJam_1);
stay_waitFifoEmpty <= waitFifoEmpty and not(BusFifoEmpty) and
not(goto_checkBusFifoFullJam_1);
waitFifoEmpty_D <= goto_waitFifoEmpty_2 or stay_waitFifoEmpty;
STATE16A: FDR
port map
(
Q => waitFifoEmpty, --[out]
C => Clk, --[in]
D => waitFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- txDone state
----------------------------------------------------------------------------
goto_txDone_1 <= waitFifoEmpty and BusFifoEmpty and
not(goto_checkBusFifoFullJam_1);
goto_txDone_2 <= half_dup_error or chgMacAdr14;
txDone_D <= goto_txDone_1 or goto_txDone_2;
STATE17A: FDR
port map
(
Q => txDone, --[out]
C => Clk, --[in]
D => txDone_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- checkBusFifoFullJam state
----------------------------------------------------------------------------
goto_checkBusFifoFullJam_1 <= (checkBusFifoFull or loadBusFifo or checkCrc
or checkBusFifoFullCrc or waitFifoEmpty) and
PhyCollision and not(full_half_n);
goto_checkBusFifoFullJam_2 <= loadBusFifoJam;
stay_checkBusFifoFullJam <= checkBusFifoFullJam and (BusFifoFull or
not(pre_SFD_zero));
checkBusFifoFullJam_D <= goto_checkBusFifoFullJam_1 or
goto_checkBusFifoFullJam_2 or
stay_checkBusFifoFullJam;
STATE18A: FDR
port map
(
Q => checkBusFifoFullJam, --[out]
C => Clk, --[in]
D => checkBusFifoFullJam_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- loadBusFifoJam state
----------------------------------------------------------------------------
goto_loadBusFifoJam <= checkBusFifoFullJam and
not(stay_checkBusFifoFullJam) and
jamTxNibCnt_not_0;
loadBusFifoJam_D <= goto_loadBusFifoJam;
STATE19A: FDR
port map
(
Q => loadBusFifoJam, --[out]
C => Clk, --[in]
D => loadBusFifoJam_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- half_dup_error state
----------------------------------------------------------------------------
goto_half_dup_error_1 <= checkBusFifoFullJam and not(BusFifoFull or
not(pre_SFD_zero)) and jamTxNibCnt_is_0 and
colWindowNibCnt_not_0 and colRetryCnt_is_15;
goto_half_dup_error_2 <= checkBusFifoFullJam and not(BusFifoFull or
not(pre_SFD_zero)) and jamTxNibCnt_is_0 and
colWindowNibCnt_is_0;
half_dup_error_D <= goto_half_dup_error_1 or goto_half_dup_error_2;
STATE20A: FDR
port map
(
Q => half_dup_error, --[out]
C => Clk, --[in]
D => half_dup_error_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- collisionRetry state
----------------------------------------------------------------------------
goto_collisionRetry <= checkBusFifoFullJam and not(stay_checkBusFifoFullJam)
and not(goto_half_dup_error_1) and
not(goto_half_dup_error_2) and
not(goto_loadBusFifoJam);
collisionRetry_D <= goto_collisionRetry;
STATE21A: FDR
port map
(
Q => collisionRetry, --[out]
C => Clk, --[in]
D => collisionRetry_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- retryWaitFifoEmpty state
----------------------------------------------------------------------------
goto_retryWaitFifoEmpty <= collisionRetry;
stay_retryWaitFifoEmpty <= retryWaitFifoEmpty and not(BusFifoEmpty);
retryWaitFifoEmpty_D <= goto_retryWaitFifoEmpty or stay_retryWaitFifoEmpty;
STATE22A: FDR
port map
(
Q => retryWaitFifoEmpty, --[out]
C => Clk, --[in]
D => retryWaitFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- retryReset state
----------------------------------------------------------------------------
goto_retryReset <= retryWaitFifoEmpty and BusFifoEmpty;
retryReset_D <= goto_retryReset;
STATE23A: FDR
port map
(
Q => retryReset, --[out]
C => Clk, --[in]
D => retryReset_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- txDone2 state
----------------------------------------------------------------------------
goto_txDone2 <= txDone;
txDone2_D <= goto_txDone2;
STATE24A: FDR
port map
(
Q => txDone2, --[out]
C => Clk, --[in]
D => txDone2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- txDonePause state
----------------------------------------------------------------------------
goto_txDonePause <= txDone2;
txDonePause_D <= goto_txDonePause;
STATE25A: FDR
port map
(
Q => txDonePause, --[out]
C => Clk, --[in]
D => txDonePause_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr1 state
----------------------------------------------------------------------------
goto_chgMacAdr1 <= idle and Mac_program_start and not mac_program_start_reg;
chgMacAdr1_D <= goto_chgMacAdr1 ;
STATE26A: FDR
port map
(
Q => chgMacAdr1, --[out]
C => Clk, --[in]
D => chgMacAdr1_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr2 state
----------------------------------------------------------------------------
goto_chgMacAdr2 <= chgMacAdr1;
chgMacAdr2_D <= goto_chgMacAdr2 ;
STATE27A: FDR
port map
(
Q => chgMacAdr2, --[out]
C => Clk, --[in]
D => chgMacAdr2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr3 state
----------------------------------------------------------------------------
goto_chgMacAdr3 <= chgMacAdr2;
chgMacAdr3_D <= goto_chgMacAdr3 ;
STATE28A: FDR
port map
(
Q => chgMacAdr3, --[out]
C => Clk, --[in]
D => chgMacAdr3_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr4 state
----------------------------------------------------------------------------
goto_chgMacAdr4 <= chgMacAdr3;
chgMacAdr4_D <= goto_chgMacAdr4 ;
STATE29A: FDR
port map
(
Q => chgMacAdr4, --[out]
C => Clk, --[in]
D => chgMacAdr4_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr5 state
----------------------------------------------------------------------------
goto_chgMacAdr5 <= chgMacAdr4;
chgMacAdr5_D <= goto_chgMacAdr5 ;
STATE30A: FDR
port map
(
Q => chgMacAdr5, --[out]
C => Clk, --[in]
D => chgMacAdr5_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr6 state
----------------------------------------------------------------------------
goto_chgMacAdr6 <= chgMacAdr5;
chgMacAdr6_D <= goto_chgMacAdr6 ;
STATE31A: FDR
port map
(
Q => chgMacAdr6, --[out]
C => Clk, --[in]
D => chgMacAdr6_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr7 state
----------------------------------------------------------------------------
goto_chgMacAdr7 <= chgMacAdr6;
chgMacAdr7_D <= goto_chgMacAdr7 ;
STATE32A: FDR
port map
(
Q => chgMacAdr7, --[out]
C => Clk, --[in]
D => chgMacAdr7_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr8 state
----------------------------------------------------------------------------
goto_chgMacAdr8 <= chgMacAdr7;
chgMacAdr8_D <= goto_chgMacAdr8 ;
STATE33A: FDR
port map
(
Q => chgMacAdr8, --[out]
C => Clk, --[in]
D => chgMacAdr8_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr9 state
----------------------------------------------------------------------------
goto_chgMacAdr9 <= chgMacAdr8;
chgMacAdr9_D <= goto_chgMacAdr9 ;
STATE34A: FDR
port map
(
Q => chgMacAdr9, --[out]
C => Clk, --[in]
D => chgMacAdr9_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr10 state
----------------------------------------------------------------------------
goto_chgMacAdr10 <= chgMacAdr9;
chgMacAdr10_D <= goto_chgMacAdr10 ;
STATE35A: FDR
port map
(
Q => chgMacAdr10, --[out]
C => Clk, --[in]
D => chgMacAdr10_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr11 state
----------------------------------------------------------------------------
goto_chgMacAdr11 <= chgMacAdr10;
chgMacAdr11_D <= goto_chgMacAdr11 ;
STATE36A: FDR
port map
(
Q => chgMacAdr11, --[out]
C => Clk, --[in]
D => chgMacAdr11_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr12 state
----------------------------------------------------------------------------
goto_chgMacAdr12 <= chgMacAdr11;
chgMacAdr12_D <= goto_chgMacAdr12 ;
STATE37A: FDR
port map
(
Q => chgMacAdr12, --[out]
C => Clk, --[in]
D => chgMacAdr12_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr13 state
----------------------------------------------------------------------------
goto_chgMacAdr13 <= chgMacAdr12;
chgMacAdr13_D <= goto_chgMacAdr13 ;
STATE38A: FDR
port map
(
Q => chgMacAdr13, --[out]
C => Clk, --[in]
D => chgMacAdr13_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- chgMacAdr14 state
----------------------------------------------------------------------------
goto_chgMacAdr14 <= chgMacAdr13;
chgMacAdr14_D <= goto_chgMacAdr14 ;
STATE39A: FDR
port map
(
Q => chgMacAdr14, --[out]
C => Clk, --[in]
D => chgMacAdr14_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- end of states
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- REG_PROCESS
----------------------------------------------------------------------------
-- This process registers all the signals on the bus clock.
----------------------------------------------------------------------------
REG_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
phytx_en_reg <= '0';
busFifoWrCntRst_reg <= '0';
retrying_reg <= '0';
txCrcEn_reg <= '0';
transmit_start_reg <= '0';
mac_program_start_reg <= '0';
else
phytx_en_reg <= phytx_en_i;
busFifoWrCntRst_reg <= busFifoWrCntRst_i;
retrying_reg <= retrying_i;
txCrcEn_reg <= txCrcEn_i;
transmit_start_reg <= Transmit_start;
mac_program_start_reg <= Mac_program_start;
end if;
end if;
end process REG_PROCESS;
----------------------------------------------------------------------------
-- COMB_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
COMB_PROCESS : process (phytx_en_reg, busFifoWrCntRst_reg,
txCrcEn_reg, txDone, idle, preamble,
half_dup_error, checkBusFifoFull,
collisionRetry, retrying_reg,
checkBusFifoFullCrc, SFD, loadBusFifoCrc,
checkBusFifoFullSFD)
begin
-- Generate PHY Tx Enable
if (txDone='1' or idle='1') then
phytx_en_i <= '0';
elsif (preamble = '1') then
phytx_en_i <= '1';
else
phytx_en_i <= phytx_en_reg;
end if;
-- Generate BusFifo Write Counter reset
if (half_dup_error='1' or txDone='1' or idle='1') then
busFifoWrCntRst_i <= '1';
elsif (preamble = '1') then
busFifoWrCntRst_i <= '0';
else
busFifoWrCntRst_i <= busFifoWrCntRst_reg;
end if;
-- Generate retry signal in case of collision
if (collisionRetry='1') then
retrying_i <= '1';
elsif (idle = '1') then
retrying_i <= '0';
else
retrying_i <= retrying_reg;
end if;
-- Generate transmit CRC enable
if (checkBusFifoFull='1') then
txCrcEn_i <= '1';
elsif (checkBusFifoFullSFD='1' or checkBusFifoFullCRC='1' or SFD='1' or
idle='1' or loadBusFifoCrc='1' or preamble='1') then
txCrcEn_i <= '0';
else
txCrcEn_i <= txCrcEn_reg;
end if;
end process COMB_PROCESS;
----------------------------------------------------------------------------
-- FSMD_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine for
-- transmit operation
----------------------------------------------------------------------------
FSMD_PROCESS : process(crcCnt_is_0, JamTxNibCnt, goto_checkBusFifoFullCrc_1,
pre_SFD_zero, checkBusFifoFullJam, full_half_n,
retryReset, txDonePause, loadBusFifo, loadBusFifoJam,
checkCrc, txDone2, chgMacAdr2, chgMacAdr3,
chgMacAdr4, chgMacAdr5, chgMacAdr6, chgMacAdr7,
chgMacAdr8, chgMacAdr9, chgMacAdr10, chgMacAdr11,
chgMacAdr12, chgMacAdr13, chgMacAdr14, chgMacAdr1,
lngthDelay1, lngthDelay2, idle, checkBusFifoFull,
txDone, ldLngthCntr,half_dup_error, collisionRetry,
checkBusFifoFullCrc, loadBusFifoCrc, retrying_reg,
preamble, SFD)
begin
-- Enable JAM reset
if (checkBusFifoFullJam = '1' and pre_SFD_zero = '1' and
full_half_n = '0' and (JamTxNibCnt = "0111")) then
Jam_rst <= '1';
else
Jam_rst <= '0';
end if;
-- Bus FIFO write counte enable
BusFifoWrCntEn <= '1'; -- temp
-- Enable TX late collision reset
TxLateColnRst <= '0';
-- Enable TX deffer reset
TxExcessDefrlRst <= '0';
-- Enable back off and TX collision retry counter
if (collisionRetry = '1') then
InitBackoff <= '1';
TxColRetryCntEnbl <= '1';
else
InitBackoff <= '0';
TxColRetryCntEnbl <= '0';
end if;
-- Enable TX retry reset
if (retryReset = '1') or
(txDonePause = '1') then -- clear up any built up garbage in async
-- FIFOs at the end of a packet
TxRetryRst <= '1';
else
TxRetryRst <= '0';
end if;
-- Enable TX nibble counter reset
if (idle = '1') then
txNibbleCntRst_i <= '1';
else
txNibbleCntRst_i <= '0';
end if;
-- Enable TX collision retry reset
if (idle = '1' and retrying_reg = '0') then
TxColRetryCntRst_n <= '0';
else
TxColRetryCntRst_n <= '1';
end if;
-- Enable TX CRC counter shift
if ((checkBusFifoFullCrc = '1') or (loadBusFifoCrc = '1')) then
TxCrcShftOutEn <= '1';
else
TxCrcShftOutEn <= '0';
end if;
-- Enable Preamble in the frame
if (preamble = '1') then
EnblPre <= '1';
else
EnblPre <= '0';
end if;
-- Enable SFD in the frame
if (SFD = '1') then
EnblSFD <= '1';
else
EnblSFD <= '0';
end if;
-- Enable Data in the frame
if (loadBusFifo = '1') then
EnblData <= '1';
else
EnblData <= '0';
end if;
-- Enable CRC
if (loadBusFifoCrc = '1') then
EnblCRC <= '1';
else
EnblCRC <= '0';
end if;
-- Enable TX nibble counter load
if (SFD = '1') then
txNibbleCntLd_i <= '1';
else
txNibbleCntLd_i <= '0';
end if;
-- Enable clear for TX interface FIFO
if (checkBusFifoFullCrc = '1' and crcCnt_is_0 = '1') or
((checkBusFifoFullJam='1' or loadBusFifoJam='1')
and pre_SFD_zero = '1' and full_half_n = '0') or
(collisionRetry = '1' ) or (half_dup_error = '1') or
(checkCrc = '1' and goto_checkBusFifoFullCrc_1 = '0') then
Enblclear <= '1';
else
Enblclear <= '0';
end if;
-- Enable Bus FIFO write
if ((loadBusFifo = '1') or
(preamble = '1') or
(SFD = '1') or
(loadBusFifoCrc = '1')
) then
busFifoWr_i <= '1';
else
busFifoWr_i <= '0';
end if;
-- Enable JAM TX nibble
if (loadBusFifo = '1') then
txEnNibbleCnt_i <= '1';
else
txEnNibbleCnt_i <= '0';
end if;
-- Enable TX buffer address increment
if (loadBusFifo = '1') or (chgMacAdr2 = '1') or (chgMacAdr3 = '1') or
(chgMacAdr4 = '1') or (chgMacAdr5 = '1') or (chgMacAdr6 = '1') or
(chgMacAdr7 = '1') or (chgMacAdr8 = '1') or (chgMacAdr9 = '1') or
(chgMacAdr10 = '1') or (chgMacAdr11 = '1') or (chgMacAdr12 = '1') or
(chgMacAdr13 = '1') or (chgMacAdr14 = '1') then
Tx_addr_en <= '1';
else
Tx_addr_en <= '0';
end if;
-- Generate TX start after preamble
if (preamble = '1') or
(chgMacAdr1 = '1') then
Tx_start <= '1'; -- reset address to 0 for start of transmit
else
Tx_start <= '0';
end if;
-- TX DPM buffer CE
if (idle = '1') or
(lngthDelay1 = '1') or (lngthDelay2 = '1') or
(checkBusFifoFull = '1') or (ldLngthCntr = '1') or
(txDone = '1') or (txDone2 = '1') or (txDonePause = '1') or
(chgMacAdr1 = '1') or (chgMacAdr2 = '1') or (chgMacAdr3 = '1') or
(chgMacAdr4 = '1') or (chgMacAdr5 = '1') or (chgMacAdr6 = '1') or
(chgMacAdr7 = '1') or (chgMacAdr8 = '1') or (chgMacAdr9 = '1') or
(chgMacAdr10 = '1') or (chgMacAdr11 = '1') or (chgMacAdr12 = '1') or
(chgMacAdr13 = '1') or (chgMacAdr14 = '1') then
Tx_DPM_ce <= '1';
else
Tx_DPM_ce <= '0';
end if;
-- Enable JAM
if (loadBusFifoJam = '1') then
EnblJam <= '1';
else
EnblJam <= '0';
end if;
-- TX DPM write enable
Tx_DPM_wr_rd_n <= '0';
end process FSMD_PROCESS;
----------------------------------------------------------------------------
-- OUTPUT_REG1
----------------------------------------------------------------------------
-- This process generate mack address RAM write enable
----------------------------------------------------------------------------
OUTPUT_REG1:process (Clk)
begin
if (Clk'event and Clk='1') then
if (Rst = '1') then
Mac_addr_ram_we <= '0';
elsif (idle_D = '1') then
Mac_addr_ram_we <= '0';
elsif (chgMacAdr3_D = '1') or
(chgMacAdr4_D = '1') or
(chgMacAdr5_D = '1') or
(chgMacAdr6_D = '1') or
(chgMacAdr7_D = '1') or
(chgMacAdr8_D = '1') or
(chgMacAdr9_D = '1') or
(chgMacAdr10_D = '1') or
(chgMacAdr11_D = '1') or
(chgMacAdr12_D = '1') or
(chgMacAdr13_D = '1') or
(chgMacAdr14_D = '1') then
Mac_addr_ram_we <= '1';
else
Mac_addr_ram_we <= '0';
end if;
end if;
end process OUTPUT_REG1;
----------------------------------------------------------------------------
-- OUTPUT_REG2
----------------------------------------------------------------------------
-- This process MAC Addr RAM write Adrress to update the MAC address of
-- EMACLite Core.
----------------------------------------------------------------------------
OUTPUT_REG2:process (Clk)
begin
if (Clk'event and Clk='1') then
if (Rst = '1') then
Mac_addr_ram_addr_wr <= x"0";
else
if idle_D = '1' then
Mac_addr_ram_addr_wr <= x"0";
elsif chgMacAdr3_D = '1' then
Mac_addr_ram_addr_wr <= x"0";
elsif chgMacAdr4_D = '1' then
Mac_addr_ram_addr_wr <= x"1";
elsif chgMacAdr5_D = '1' then
Mac_addr_ram_addr_wr <= x"2";
elsif chgMacAdr6_D = '1' then
Mac_addr_ram_addr_wr <= x"3";
elsif chgMacAdr7_D = '1' then
Mac_addr_ram_addr_wr <= x"4";
elsif chgMacAdr8_D = '1' then
Mac_addr_ram_addr_wr <= x"5";
elsif chgMacAdr9_D = '1' then
Mac_addr_ram_addr_wr <= x"6";
elsif chgMacAdr10_D = '1' then
Mac_addr_ram_addr_wr <= x"7";
elsif chgMacAdr11_D = '1' then
Mac_addr_ram_addr_wr <= x"8";
elsif chgMacAdr12_D = '1' then
Mac_addr_ram_addr_wr <= x"9";
elsif chgMacAdr13_D = '1' then
Mac_addr_ram_addr_wr <= x"a";
elsif chgMacAdr14_D = '1' then
Mac_addr_ram_addr_wr <= x"b";
else
Mac_addr_ram_addr_wr <= x"0";
end if;
end if;
end if;
end process OUTPUT_REG2;
end implementation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/876b8fe4/hdl/src/vhdl/slave_attachment.vhd
|
6
|
24067
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/synth/design_1_lmb_bram_0.vhd
|
2
|
15376
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY design_1_lmb_bram_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_lmb_bram_0;
ARCHITECTURE design_1_lmb_bram_0_arch OF design_1_lmb_bram_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_lmb_bram_0_arch : ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_lmb_bram_0_arch: ARCHITECTURE IS "design_1_lmb_bram_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=design_1_lmb_bram_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=8192,C_READ_DEPTH_A=8192,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=8192,C_READ_DEPTH_B=8192,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=8,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "design_1_lmb_bram_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 8192,
C_READ_DEPTH_A => 8192,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 8192,
C_READ_DEPTH_B => 8192,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "8",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 20.388 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_lmb_bram_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/synth/design_1_microblaze_0_0.vhd
|
2
|
64533
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:microblaze:9.5
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY microblaze_v9_5;
USE microblaze_v9_5.MicroBlaze;
ENTITY design_1_microblaze_0_0 IS
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC
);
END design_1_microblaze_0_0;
ARCHITECTURE design_1_microblaze_0_0_arch OF design_1_microblaze_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT MicroBlaze IS
GENERIC (
C_SCO : INTEGER;
C_FREQ : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_NUM_SYNC_FF_CLK : INTEGER;
C_NUM_SYNC_FF_CLK_IRQ : INTEGER;
C_NUM_SYNC_FF_CLK_DEBUG : INTEGER;
C_NUM_SYNC_FF_DBG_CLK : INTEGER;
C_FAULT_TOLERANT : INTEGER;
C_ECC_USE_CE_EXCEPTION : INTEGER;
C_LOCKSTEP_SLAVE : INTEGER;
C_ENDIANNESS : INTEGER;
C_FAMILY : STRING;
C_DATA_SIZE : INTEGER;
C_INSTANCE : STRING;
C_AVOID_PRIMITIVES : INTEGER;
C_AREA_OPTIMIZED : INTEGER;
C_OPTIMIZATION : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASE_VECTORS : STD_LOGIC_VECTOR;
C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DP_DATA_WIDTH : INTEGER;
C_M_AXI_DP_ADDR_WIDTH : INTEGER;
C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_D_BUS_EXCEPTION : INTEGER;
C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IP_DATA_WIDTH : INTEGER;
C_M_AXI_IP_ADDR_WIDTH : INTEGER;
C_M_AXI_I_BUS_EXCEPTION : INTEGER;
C_D_LMB : INTEGER;
C_D_AXI : INTEGER;
C_I_LMB : INTEGER;
C_I_AXI : INTEGER;
C_USE_MSR_INSTR : INTEGER;
C_USE_PCMP_INSTR : INTEGER;
C_USE_BARREL : INTEGER;
C_USE_DIV : INTEGER;
C_USE_HW_MUL : INTEGER;
C_USE_FPU : INTEGER;
C_USE_REORDER_INSTR : INTEGER;
C_UNALIGNED_EXCEPTIONS : INTEGER;
C_ILL_OPCODE_EXCEPTION : INTEGER;
C_DIV_ZERO_EXCEPTION : INTEGER;
C_FPU_EXCEPTION : INTEGER;
C_FSL_LINKS : INTEGER;
C_USE_EXTENDED_FSL_INSTR : INTEGER;
C_FSL_EXCEPTION : INTEGER;
C_USE_STACK_PROTECTION : INTEGER;
C_IMPRECISE_EXCEPTIONS : INTEGER;
C_USE_INTERRUPT : INTEGER;
C_USE_EXT_BRK : INTEGER;
C_USE_EXT_NM_BRK : INTEGER;
C_USE_MMU : INTEGER;
C_MMU_DTLB_SIZE : INTEGER;
C_MMU_ITLB_SIZE : INTEGER;
C_MMU_TLB_ACCESS : INTEGER;
C_MMU_ZONES : INTEGER;
C_MMU_PRIVILEGED_INSTR : INTEGER;
C_USE_BRANCH_TARGET_CACHE : INTEGER;
C_BRANCH_TARGET_CACHE_SIZE : INTEGER;
C_PC_WIDTH : INTEGER;
C_PVR : INTEGER;
C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7);
C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31);
C_DYNAMIC_BUS_SIZING : INTEGER;
C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31);
C_OPCODE_0x0_ILLEGAL : INTEGER;
C_DEBUG_ENABLED : INTEGER;
C_NUMBER_OF_PC_BRK : INTEGER;
C_NUMBER_OF_RD_ADDR_BRK : INTEGER;
C_NUMBER_OF_WR_ADDR_BRK : INTEGER;
C_DEBUG_EVENT_COUNTERS : INTEGER;
C_DEBUG_LATENCY_COUNTERS : INTEGER;
C_DEBUG_COUNTER_WIDTH : INTEGER;
C_DEBUG_TRACE_SIZE : INTEGER;
C_DEBUG_EXTERNAL_TRACE : INTEGER;
C_DEBUG_PROFILE_SIZE : INTEGER;
C_INTERRUPT_IS_EDGE : INTEGER;
C_EDGE_IS_POSITIVE : INTEGER;
C_ASYNC_INTERRUPT : INTEGER;
C_M0_AXIS_DATA_WIDTH : INTEGER;
C_S0_AXIS_DATA_WIDTH : INTEGER;
C_M1_AXIS_DATA_WIDTH : INTEGER;
C_S1_AXIS_DATA_WIDTH : INTEGER;
C_M2_AXIS_DATA_WIDTH : INTEGER;
C_S2_AXIS_DATA_WIDTH : INTEGER;
C_M3_AXIS_DATA_WIDTH : INTEGER;
C_S3_AXIS_DATA_WIDTH : INTEGER;
C_M4_AXIS_DATA_WIDTH : INTEGER;
C_S4_AXIS_DATA_WIDTH : INTEGER;
C_M5_AXIS_DATA_WIDTH : INTEGER;
C_S5_AXIS_DATA_WIDTH : INTEGER;
C_M6_AXIS_DATA_WIDTH : INTEGER;
C_S6_AXIS_DATA_WIDTH : INTEGER;
C_M7_AXIS_DATA_WIDTH : INTEGER;
C_S7_AXIS_DATA_WIDTH : INTEGER;
C_M8_AXIS_DATA_WIDTH : INTEGER;
C_S8_AXIS_DATA_WIDTH : INTEGER;
C_M9_AXIS_DATA_WIDTH : INTEGER;
C_S9_AXIS_DATA_WIDTH : INTEGER;
C_M10_AXIS_DATA_WIDTH : INTEGER;
C_S10_AXIS_DATA_WIDTH : INTEGER;
C_M11_AXIS_DATA_WIDTH : INTEGER;
C_S11_AXIS_DATA_WIDTH : INTEGER;
C_M12_AXIS_DATA_WIDTH : INTEGER;
C_S12_AXIS_DATA_WIDTH : INTEGER;
C_M13_AXIS_DATA_WIDTH : INTEGER;
C_S13_AXIS_DATA_WIDTH : INTEGER;
C_M14_AXIS_DATA_WIDTH : INTEGER;
C_S14_AXIS_DATA_WIDTH : INTEGER;
C_M15_AXIS_DATA_WIDTH : INTEGER;
C_S15_AXIS_DATA_WIDTH : INTEGER;
C_ICACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_ICACHE : INTEGER;
C_ALLOW_ICACHE_WR : INTEGER;
C_ADDR_TAG_BITS : INTEGER;
C_CACHE_BYTE_SIZE : INTEGER;
C_ICACHE_LINE_LEN : INTEGER;
C_ICACHE_ALWAYS_USED : INTEGER;
C_ICACHE_STREAMS : INTEGER;
C_ICACHE_VICTIMS : INTEGER;
C_ICACHE_FORCE_TAG_LUTRAM : INTEGER;
C_ICACHE_DATA_WIDTH : INTEGER;
C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IC_DATA_WIDTH : INTEGER;
C_M_AXI_IC_ADDR_WIDTH : INTEGER;
C_M_AXI_IC_USER_VALUE : INTEGER;
C_M_AXI_IC_AWUSER_WIDTH : INTEGER;
C_M_AXI_IC_ARUSER_WIDTH : INTEGER;
C_M_AXI_IC_WUSER_WIDTH : INTEGER;
C_M_AXI_IC_RUSER_WIDTH : INTEGER;
C_M_AXI_IC_BUSER_WIDTH : INTEGER;
C_DCACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_DCACHE : INTEGER;
C_ALLOW_DCACHE_WR : INTEGER;
C_DCACHE_ADDR_TAG : INTEGER;
C_DCACHE_BYTE_SIZE : INTEGER;
C_DCACHE_LINE_LEN : INTEGER;
C_DCACHE_ALWAYS_USED : INTEGER;
C_DCACHE_USE_WRITEBACK : INTEGER;
C_DCACHE_VICTIMS : INTEGER;
C_DCACHE_FORCE_TAG_LUTRAM : INTEGER;
C_DCACHE_DATA_WIDTH : INTEGER;
C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DC_DATA_WIDTH : INTEGER;
C_M_AXI_DC_ADDR_WIDTH : INTEGER;
C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_DC_USER_VALUE : INTEGER;
C_M_AXI_DC_AWUSER_WIDTH : INTEGER;
C_M_AXI_DC_ARUSER_WIDTH : INTEGER;
C_M_AXI_DC_WUSER_WIDTH : INTEGER;
C_M_AXI_DC_RUSER_WIDTH : INTEGER;
C_M_AXI_DC_BUSER_WIDTH : INTEGER
);
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Mb_Reset : IN STD_LOGIC;
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Ext_BRK : IN STD_LOGIC;
Ext_NM_BRK : IN STD_LOGIC;
Dbg_Stop : IN STD_LOGIC;
Dbg_Intr : OUT STD_LOGIC;
MB_Halted : OUT STD_LOGIC;
MB_Error : OUT STD_LOGIC;
Wakeup : IN STD_LOGIC_VECTOR(0 TO 1);
Sleep : OUT STD_LOGIC;
Dbg_Wakeup : OUT STD_LOGIC;
Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1);
LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_AWLOCK : OUT STD_LOGIC;
M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWVALID : OUT STD_LOGIC;
M_AXI_IP_AWREADY : IN STD_LOGIC;
M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_WLAST : OUT STD_LOGIC;
M_AXI_IP_WVALID : OUT STD_LOGIC;
M_AXI_IP_WREADY : IN STD_LOGIC;
M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_BVALID : IN STD_LOGIC;
M_AXI_IP_BREADY : OUT STD_LOGIC;
M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_ARLOCK : OUT STD_LOGIC;
M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARVALID : OUT STD_LOGIC;
M_AXI_IP_ARREADY : IN STD_LOGIC;
M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_RLAST : IN STD_LOGIC;
M_AXI_IP_RVALID : IN STD_LOGIC;
M_AXI_IP_RREADY : OUT STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_AWLOCK : OUT STD_LOGIC;
M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WLAST : OUT STD_LOGIC;
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_ARLOCK : OUT STD_LOGIC;
M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RLAST : IN STD_LOGIC;
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trace_Clk : IN STD_LOGIC;
Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35);
Dbg_Trace_Ready : IN STD_LOGIC;
Dbg_Trace_Valid : OUT STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Valid_Instr : OUT STD_LOGIC;
Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Reg_Write : OUT STD_LOGIC;
Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14);
Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7);
Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Exception_Taken : OUT STD_LOGIC;
Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_Jump_Taken : OUT STD_LOGIC;
Trace_Delay_Slot : OUT STD_LOGIC;
Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
Trace_Data_Access : OUT STD_LOGIC;
Trace_Data_Read : OUT STD_LOGIC;
Trace_Data_Write : OUT STD_LOGIC;
Trace_DCache_Req : OUT STD_LOGIC;
Trace_DCache_Hit : OUT STD_LOGIC;
Trace_DCache_Rdy : OUT STD_LOGIC;
Trace_DCache_Read : OUT STD_LOGIC;
Trace_ICache_Req : OUT STD_LOGIC;
Trace_ICache_Hit : OUT STD_LOGIC;
Trace_ICache_Rdy : OUT STD_LOGIC;
Trace_OF_PipeRun : OUT STD_LOGIC;
Trace_EX_PipeRun : OUT STD_LOGIC;
Trace_MEM_PipeRun : OUT STD_LOGIC;
Trace_MB_Halted : OUT STD_LOGIC;
Trace_Jump_Hit : OUT STD_LOGIC;
M0_AXIS_TLAST : OUT STD_LOGIC;
M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M0_AXIS_TVALID : OUT STD_LOGIC;
M0_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TREADY : IN STD_LOGIC;
M3_AXIS_TLAST : OUT STD_LOGIC;
M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M3_AXIS_TVALID : OUT STD_LOGIC;
M3_AXIS_TREADY : IN STD_LOGIC;
M4_AXIS_TLAST : OUT STD_LOGIC;
M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M4_AXIS_TVALID : OUT STD_LOGIC;
M4_AXIS_TREADY : IN STD_LOGIC;
M5_AXIS_TLAST : OUT STD_LOGIC;
M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M5_AXIS_TVALID : OUT STD_LOGIC;
M5_AXIS_TREADY : IN STD_LOGIC;
M6_AXIS_TLAST : OUT STD_LOGIC;
M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M6_AXIS_TVALID : OUT STD_LOGIC;
M6_AXIS_TREADY : IN STD_LOGIC;
M7_AXIS_TLAST : OUT STD_LOGIC;
M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M7_AXIS_TVALID : OUT STD_LOGIC;
M7_AXIS_TREADY : IN STD_LOGIC;
M8_AXIS_TLAST : OUT STD_LOGIC;
M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M8_AXIS_TVALID : OUT STD_LOGIC;
M8_AXIS_TREADY : IN STD_LOGIC;
M9_AXIS_TLAST : OUT STD_LOGIC;
M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M9_AXIS_TVALID : OUT STD_LOGIC;
M9_AXIS_TREADY : IN STD_LOGIC;
M10_AXIS_TLAST : OUT STD_LOGIC;
M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M10_AXIS_TVALID : OUT STD_LOGIC;
M10_AXIS_TREADY : IN STD_LOGIC;
M11_AXIS_TLAST : OUT STD_LOGIC;
M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M11_AXIS_TVALID : OUT STD_LOGIC;
M11_AXIS_TREADY : IN STD_LOGIC;
M12_AXIS_TLAST : OUT STD_LOGIC;
M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M12_AXIS_TVALID : OUT STD_LOGIC;
M12_AXIS_TREADY : IN STD_LOGIC;
M13_AXIS_TLAST : OUT STD_LOGIC;
M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M13_AXIS_TVALID : OUT STD_LOGIC;
M13_AXIS_TREADY : IN STD_LOGIC;
M14_AXIS_TLAST : OUT STD_LOGIC;
M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M14_AXIS_TVALID : OUT STD_LOGIC;
M14_AXIS_TREADY : IN STD_LOGIC;
M15_AXIS_TLAST : OUT STD_LOGIC;
M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M15_AXIS_TVALID : OUT STD_LOGIC;
M15_AXIS_TREADY : IN STD_LOGIC;
S0_AXIS_TLAST : IN STD_LOGIC;
S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXIS_TVALID : IN STD_LOGIC;
S0_AXIS_TREADY : OUT STD_LOGIC;
S1_AXIS_TLAST : IN STD_LOGIC;
S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXIS_TVALID : IN STD_LOGIC;
S1_AXIS_TREADY : OUT STD_LOGIC;
S2_AXIS_TLAST : IN STD_LOGIC;
S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXIS_TVALID : IN STD_LOGIC;
S2_AXIS_TREADY : OUT STD_LOGIC;
S3_AXIS_TLAST : IN STD_LOGIC;
S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXIS_TVALID : IN STD_LOGIC;
S3_AXIS_TREADY : OUT STD_LOGIC;
S4_AXIS_TLAST : IN STD_LOGIC;
S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXIS_TVALID : IN STD_LOGIC;
S4_AXIS_TREADY : OUT STD_LOGIC;
S5_AXIS_TLAST : IN STD_LOGIC;
S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXIS_TVALID : IN STD_LOGIC;
S5_AXIS_TREADY : OUT STD_LOGIC;
S6_AXIS_TLAST : IN STD_LOGIC;
S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXIS_TVALID : IN STD_LOGIC;
S6_AXIS_TREADY : OUT STD_LOGIC;
S7_AXIS_TLAST : IN STD_LOGIC;
S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXIS_TVALID : IN STD_LOGIC;
S7_AXIS_TREADY : OUT STD_LOGIC;
S8_AXIS_TLAST : IN STD_LOGIC;
S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S8_AXIS_TVALID : IN STD_LOGIC;
S8_AXIS_TREADY : OUT STD_LOGIC;
S9_AXIS_TLAST : IN STD_LOGIC;
S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S9_AXIS_TVALID : IN STD_LOGIC;
S9_AXIS_TREADY : OUT STD_LOGIC;
S10_AXIS_TLAST : IN STD_LOGIC;
S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S10_AXIS_TVALID : IN STD_LOGIC;
S10_AXIS_TREADY : OUT STD_LOGIC;
S11_AXIS_TLAST : IN STD_LOGIC;
S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S11_AXIS_TVALID : IN STD_LOGIC;
S11_AXIS_TREADY : OUT STD_LOGIC;
S12_AXIS_TLAST : IN STD_LOGIC;
S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S12_AXIS_TVALID : IN STD_LOGIC;
S12_AXIS_TREADY : OUT STD_LOGIC;
S13_AXIS_TLAST : IN STD_LOGIC;
S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S13_AXIS_TVALID : IN STD_LOGIC;
S13_AXIS_TREADY : OUT STD_LOGIC;
S14_AXIS_TLAST : IN STD_LOGIC;
S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S14_AXIS_TVALID : IN STD_LOGIC;
S14_AXIS_TREADY : OUT STD_LOGIC;
S15_AXIS_TLAST : IN STD_LOGIC;
S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S15_AXIS_TVALID : IN STD_LOGIC;
S15_AXIS_TREADY : OUT STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_WACK : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RACK : OUT STD_LOGIC;
M_AXI_IC_ACVALID : IN STD_LOGIC;
M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ACREADY : OUT STD_LOGIC;
M_AXI_IC_CRVALID : OUT STD_LOGIC;
M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_CRREADY : IN STD_LOGIC;
M_AXI_IC_CDVALID : OUT STD_LOGIC;
M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_CDLAST : OUT STD_LOGIC;
M_AXI_IC_CDREADY : IN STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_WACK : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC;
M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RACK : OUT STD_LOGIC;
M_AXI_DC_ACVALID : IN STD_LOGIC;
M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ACREADY : OUT STD_LOGIC;
M_AXI_DC_CRVALID : OUT STD_LOGIC;
M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_CRREADY : IN STD_LOGIC;
M_AXI_DC_CDVALID : OUT STD_LOGIC;
M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_CDLAST : OUT STD_LOGIC;
M_AXI_DC_CDREADY : IN STD_LOGIC
);
END COMPONENT MicroBlaze;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "MicroBlaze,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_0_arch : ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze,x_ipVersion=9.5,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_SCO=0,C_FREQ=100000000,C_USE_CONFIG_RESET=0,C_NUM_SYNC_FF_CLK=2,C_NUM_SYNC_FF_CLK_IRQ=1,C_NUM_SYNC_FF_CLK_DEBUG=2,C_NUM_SYNC_FF_DBG_CLK=1,C_FAULT_TOLERANT=0,C_ECC_USE_CE_EXCEPTION=0,C_LOCKSTEP_SLAVE=0,C_ENDIANNESS=1,C_FAMILY=artix7,C_DATA_SIZE=32,C_INSTANCE=design_1_microblaze_0_0,C_AVOID_PRIMITIVES=0,C_AREA_OPTIMIZED=0,C_OPTIMIZATION=0,C_INTERCONNECT=2,C_BASE_VECTORS=0x00000000,C_M_AXI_DP_THREAD_ID_WIDTH=1,C_M_AXI_DP_DATA_WIDTH=32,C_M_AXI_DP_ADDR_WIDTH=32,C_M_AXI_DP_EXCLUSIVE_ACCESS=0,C_M_AXI_D_BUS_EXCEPTION=0,C_M_AXI_IP_THREAD_ID_WIDTH=1,C_M_AXI_IP_DATA_WIDTH=32,C_M_AXI_IP_ADDR_WIDTH=32,C_M_AXI_I_BUS_EXCEPTION=0,C_D_LMB=1,C_D_AXI=1,C_I_LMB=1,C_I_AXI=0,C_USE_MSR_INSTR=0,C_USE_PCMP_INSTR=0,C_USE_BARREL=0,C_USE_DIV=0,C_USE_HW_MUL=0,C_USE_FPU=0,C_USE_REORDER_INSTR=1,C_UNALIGNED_EXCEPTIONS=0,C_ILL_OPCODE_EXCEPTION=0,C_DIV_ZERO_EXCEPTION=0,C_FPU_EXCEPTION=0,C_FSL_LINKS=0,C_USE_EXTENDED_FSL_INSTR=0,C_FSL_EXCEPTION=0,C_USE_STACK_PROTECTION=0,C_IMPRECISE_EXCEPTIONS=0,C_USE_INTERRUPT=2,C_USE_EXT_BRK=0,C_USE_EXT_NM_BRK=0,C_USE_MMU=0,C_MMU_DTLB_SIZE=4,C_MMU_ITLB_SIZE=2,C_MMU_TLB_ACCESS=3,C_MMU_ZONES=16,C_MMU_PRIVILEGED_INSTR=0,C_USE_BRANCH_TARGET_CACHE=0,C_BRANCH_TARGET_CACHE_SIZE=0,C_PC_WIDTH=32,C_PVR=0,C_PVR_USER1=0x00,C_PVR_USER2=0x00000000,C_DYNAMIC_BUS_SIZING=0,C_RESET_MSR=0x00000000,C_OPCODE_0x0_ILLEGAL=0,C_DEBUG_ENABLED=1,C_NUMBER_OF_PC_BRK=1,C_NUMBER_OF_RD_ADDR_BRK=0,C_NUMBER_OF_WR_ADDR_BRK=0,C_DEBUG_EVENT_COUNTERS=5,C_DEBUG_LATENCY_COUNTERS=1,C_DEBUG_COUNTER_WIDTH=32,C_DEBUG_TRACE_SIZE=8192,C_DEBUG_EXTERNAL_TRACE=0,C_DEBUG_PROFILE_SIZE=0,C_INTERRUPT_IS_EDGE=0,C_EDGE_IS_POSITIVE=1,C_ASYNC_INTERRUPT=1,C_M0_AXIS_DATA_WIDTH=32,C_S0_AXIS_DATA_WIDTH=32,C_M1_AXIS_DATA_WIDTH=32,C_S1_AXIS_DATA_WIDTH=32,C_M2_AXIS_DATA_WIDTH=32,C_S2_AXIS_DATA_WIDTH=32,C_M3_AXIS_DATA_WIDTH=32,C_S3_AXIS_DATA_WIDTH=32,C_M4_AXIS_DATA_WIDTH=32,C_S4_AXIS_DATA_WIDTH=32,C_M5_AXIS_DATA_WIDTH=32,C_S5_AXIS_DATA_WIDTH=32,C_M6_AXIS_DATA_WIDTH=32,C_S6_AXIS_DATA_WIDTH=32,C_M7_AXIS_DATA_WIDTH=32,C_S7_AXIS_DATA_WIDTH=32,C_M8_AXIS_DATA_WIDTH=32,C_S8_AXIS_DATA_WIDTH=32,C_M9_AXIS_DATA_WIDTH=32,C_S9_AXIS_DATA_WIDTH=32,C_M10_AXIS_DATA_WIDTH=32,C_S10_AXIS_DATA_WIDTH=32,C_M11_AXIS_DATA_WIDTH=32,C_S11_AXIS_DATA_WIDTH=32,C_M12_AXIS_DATA_WIDTH=32,C_S12_AXIS_DATA_WIDTH=32,C_M13_AXIS_DATA_WIDTH=32,C_S13_AXIS_DATA_WIDTH=32,C_M14_AXIS_DATA_WIDTH=32,C_S14_AXIS_DATA_WIDTH=32,C_M15_AXIS_DATA_WIDTH=32,C_S15_AXIS_DATA_WIDTH=32,C_ICACHE_BASEADDR=0x60000000,C_ICACHE_HIGHADDR=0x60ffffff,C_USE_ICACHE=1,C_ALLOW_ICACHE_WR=1,C_ADDR_TAG_BITS=10,C_CACHE_BYTE_SIZE=16384,C_ICACHE_LINE_LEN=4,C_ICACHE_ALWAYS_USED=1,C_ICACHE_STREAMS=0,C_ICACHE_VICTIMS=0,C_ICACHE_FORCE_TAG_LUTRAM=0,C_ICACHE_DATA_WIDTH=0,C_M_AXI_IC_THREAD_ID_WIDTH=1,C_M_AXI_IC_DATA_WIDTH=32,C_M_AXI_IC_ADDR_WIDTH=32,C_M_AXI_IC_USER_VALUE=31,C_M_AXI_IC_AWUSER_WIDTH=5,C_M_AXI_IC_ARUSER_WIDTH=5,C_M_AXI_IC_WUSER_WIDTH=1,C_M_AXI_IC_RUSER_WIDTH=1,C_M_AXI_IC_BUSER_WIDTH=1,C_DCACHE_BASEADDR=0x60000000,C_DCACHE_HIGHADDR=0x60ffffff,C_USE_DCACHE=1,C_ALLOW_DCACHE_WR=1,C_DCACHE_ADDR_TAG=10,C_DCACHE_BYTE_SIZE=16384,C_DCACHE_LINE_LEN=4,C_DCACHE_ALWAYS_USED=1,C_DCACHE_USE_WRITEBACK=0,C_DCACHE_VICTIMS=0,C_DCACHE_FORCE_TAG_LUTRAM=0,C_DCACHE_DATA_WIDTH=0,C_M_AXI_DC_THREAD_ID_WIDTH=1,C_M_AXI_DC_DATA_WIDTH=32,C_M_AXI_DC_ADDR_WIDTH=32,C_M_AXI_DC_EXCLUSIVE_ACCESS=0,C_M_AXI_DC_USER_VALUE=31,C_M_AXI_DC_AWUSER_WIDTH=5,C_M_AXI_DC_ARUSER_WIDTH=5,C_M_AXI_DC_WUSER_WIDTH=1,C_M_AXI_DC_RUSER_WIDTH=1,C_M_AXI_DC_BUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY";
ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE";
ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY";
BEGIN
U0 : MicroBlaze
GENERIC MAP (
C_SCO => 0,
C_FREQ => 100000000,
C_USE_CONFIG_RESET => 0,
C_NUM_SYNC_FF_CLK => 2,
C_NUM_SYNC_FF_CLK_IRQ => 1,
C_NUM_SYNC_FF_CLK_DEBUG => 2,
C_NUM_SYNC_FF_DBG_CLK => 1,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 1,
C_FAMILY => "artix7",
C_DATA_SIZE => 32,
C_INSTANCE => "design_1_microblaze_0_0",
C_AVOID_PRIMITIVES => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_BASE_VECTORS => X"00000000",
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_D_LMB => 1,
C_D_AXI => 1,
C_I_LMB => 1,
C_I_AXI => 0,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_LINKS => 0,
C_USE_EXTENDED_FSL_INSTR => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_IMPRECISE_EXCEPTIONS => 0,
C_USE_INTERRUPT => 2,
C_USE_EXT_BRK => 0,
C_USE_EXT_NM_BRK => 0,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DYNAMIC_BUS_SIZING => 0,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_DEBUG_EVENT_COUNTERS => 5,
C_DEBUG_LATENCY_COUNTERS => 1,
C_DEBUG_COUNTER_WIDTH => 32,
C_DEBUG_TRACE_SIZE => 8192,
C_DEBUG_EXTERNAL_TRACE => 0,
C_DEBUG_PROFILE_SIZE => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_ASYNC_INTERRUPT => 1,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"60000000",
C_ICACHE_HIGHADDR => X"60ffffff",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 10,
C_CACHE_BYTE_SIZE => 16384,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_STREAMS => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 31,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"60000000",
C_DCACHE_HIGHADDR => X"60ffffff",
C_USE_DCACHE => 1,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 10,
C_DCACHE_BYTE_SIZE => 16384,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 1,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 31,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1
)
PORT MAP (
Clk => Clk,
Reset => Reset,
Mb_Reset => '0',
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
Dbg_Disable => '0',
Interrupt => Interrupt,
Interrupt_Address => Interrupt_Address,
Interrupt_Ack => Interrupt_Ack,
Ext_BRK => '0',
Ext_NM_BRK => '0',
Dbg_Stop => '0',
Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)),
Instr_Addr => Instr_Addr,
Instr => Instr,
IFetch => IFetch,
I_AS => I_AS,
IReady => IReady,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
M_AXI_IP_AWREADY => '0',
M_AXI_IP_WREADY => '0',
M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_BVALID => '0',
M_AXI_IP_ARREADY => '0',
M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_RLAST => '0',
M_AXI_IP_RVALID => '0',
Data_Addr => Data_Addr,
Data_Read => Data_Read,
Data_Write => Data_Write,
D_AS => D_AS,
Read_Strobe => Read_Strobe,
Write_Strobe => Write_Strobe,
DReady => DReady,
DWait => DWait,
DCE => DCE,
DUE => DUE,
Byte_Enable => Byte_Enable,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => '0',
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
Dbg_Clk => Dbg_Clk,
Dbg_TDI => Dbg_TDI,
Dbg_TDO => Dbg_TDO,
Dbg_Reg_En => Dbg_Reg_En,
Dbg_Shift => Dbg_Shift,
Dbg_Capture => Dbg_Capture,
Dbg_Update => Dbg_Update,
Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trace_Clk => '0',
Dbg_Trace_Ready => '0',
Debug_Rst => Debug_Rst,
M0_AXIS_TREADY => '0',
M1_AXIS_TREADY => '0',
M2_AXIS_TREADY => '0',
M3_AXIS_TREADY => '0',
M4_AXIS_TREADY => '0',
M5_AXIS_TREADY => '0',
M6_AXIS_TREADY => '0',
M7_AXIS_TREADY => '0',
M8_AXIS_TREADY => '0',
M9_AXIS_TREADY => '0',
M10_AXIS_TREADY => '0',
M11_AXIS_TREADY => '0',
M12_AXIS_TREADY => '0',
M13_AXIS_TREADY => '0',
M14_AXIS_TREADY => '0',
M15_AXIS_TREADY => '0',
S0_AXIS_TLAST => '0',
S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S0_AXIS_TVALID => '0',
S1_AXIS_TLAST => '0',
S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S1_AXIS_TVALID => '0',
S2_AXIS_TLAST => '0',
S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S2_AXIS_TVALID => '0',
S3_AXIS_TLAST => '0',
S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXIS_TVALID => '0',
S4_AXIS_TLAST => '0',
S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXIS_TVALID => '0',
S5_AXIS_TLAST => '0',
S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXIS_TVALID => '0',
S6_AXIS_TLAST => '0',
S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXIS_TVALID => '0',
S7_AXIS_TLAST => '0',
S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXIS_TVALID => '0',
S8_AXIS_TLAST => '0',
S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S8_AXIS_TVALID => '0',
S9_AXIS_TLAST => '0',
S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S9_AXIS_TVALID => '0',
S10_AXIS_TLAST => '0',
S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S10_AXIS_TVALID => '0',
S11_AXIS_TLAST => '0',
S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S11_AXIS_TVALID => '0',
S12_AXIS_TLAST => '0',
S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S12_AXIS_TVALID => '0',
S13_AXIS_TLAST => '0',
S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S13_AXIS_TVALID => '0',
S14_AXIS_TLAST => '0',
S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S14_AXIS_TVALID => '0',
S15_AXIS_TLAST => '0',
S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S15_AXIS_TVALID => '0',
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ACVALID => '0',
M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_IC_CRREADY => '0',
M_AXI_IC_CDREADY => '0',
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ACVALID => '0',
M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_DC_CRREADY => '0',
M_AXI_DC_CDREADY => '0'
);
END design_1_microblaze_0_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/synth/design_1_microblaze_0_0.vhd
|
2
|
64536
|
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-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:microblaze:9.5
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY microblaze_v9_5;
USE microblaze_v9_5.MicroBlaze;
ENTITY design_1_microblaze_0_0 IS
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC
);
END design_1_microblaze_0_0;
ARCHITECTURE design_1_microblaze_0_0_arch OF design_1_microblaze_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT MicroBlaze IS
GENERIC (
C_SCO : INTEGER;
C_FREQ : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_NUM_SYNC_FF_CLK : INTEGER;
C_NUM_SYNC_FF_CLK_IRQ : INTEGER;
C_NUM_SYNC_FF_CLK_DEBUG : INTEGER;
C_NUM_SYNC_FF_DBG_CLK : INTEGER;
C_FAULT_TOLERANT : INTEGER;
C_ECC_USE_CE_EXCEPTION : INTEGER;
C_LOCKSTEP_SLAVE : INTEGER;
C_ENDIANNESS : INTEGER;
C_FAMILY : STRING;
C_DATA_SIZE : INTEGER;
C_INSTANCE : STRING;
C_AVOID_PRIMITIVES : INTEGER;
C_AREA_OPTIMIZED : INTEGER;
C_OPTIMIZATION : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASE_VECTORS : STD_LOGIC_VECTOR;
C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DP_DATA_WIDTH : INTEGER;
C_M_AXI_DP_ADDR_WIDTH : INTEGER;
C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_D_BUS_EXCEPTION : INTEGER;
C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IP_DATA_WIDTH : INTEGER;
C_M_AXI_IP_ADDR_WIDTH : INTEGER;
C_M_AXI_I_BUS_EXCEPTION : INTEGER;
C_D_LMB : INTEGER;
C_D_AXI : INTEGER;
C_I_LMB : INTEGER;
C_I_AXI : INTEGER;
C_USE_MSR_INSTR : INTEGER;
C_USE_PCMP_INSTR : INTEGER;
C_USE_BARREL : INTEGER;
C_USE_DIV : INTEGER;
C_USE_HW_MUL : INTEGER;
C_USE_FPU : INTEGER;
C_USE_REORDER_INSTR : INTEGER;
C_UNALIGNED_EXCEPTIONS : INTEGER;
C_ILL_OPCODE_EXCEPTION : INTEGER;
C_DIV_ZERO_EXCEPTION : INTEGER;
C_FPU_EXCEPTION : INTEGER;
C_FSL_LINKS : INTEGER;
C_USE_EXTENDED_FSL_INSTR : INTEGER;
C_FSL_EXCEPTION : INTEGER;
C_USE_STACK_PROTECTION : INTEGER;
C_IMPRECISE_EXCEPTIONS : INTEGER;
C_USE_INTERRUPT : INTEGER;
C_USE_EXT_BRK : INTEGER;
C_USE_EXT_NM_BRK : INTEGER;
C_USE_MMU : INTEGER;
C_MMU_DTLB_SIZE : INTEGER;
C_MMU_ITLB_SIZE : INTEGER;
C_MMU_TLB_ACCESS : INTEGER;
C_MMU_ZONES : INTEGER;
C_MMU_PRIVILEGED_INSTR : INTEGER;
C_USE_BRANCH_TARGET_CACHE : INTEGER;
C_BRANCH_TARGET_CACHE_SIZE : INTEGER;
C_PC_WIDTH : INTEGER;
C_PVR : INTEGER;
C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7);
C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31);
C_DYNAMIC_BUS_SIZING : INTEGER;
C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31);
C_OPCODE_0x0_ILLEGAL : INTEGER;
C_DEBUG_ENABLED : INTEGER;
C_NUMBER_OF_PC_BRK : INTEGER;
C_NUMBER_OF_RD_ADDR_BRK : INTEGER;
C_NUMBER_OF_WR_ADDR_BRK : INTEGER;
C_DEBUG_EVENT_COUNTERS : INTEGER;
C_DEBUG_LATENCY_COUNTERS : INTEGER;
C_DEBUG_COUNTER_WIDTH : INTEGER;
C_DEBUG_TRACE_SIZE : INTEGER;
C_DEBUG_EXTERNAL_TRACE : INTEGER;
C_DEBUG_PROFILE_SIZE : INTEGER;
C_INTERRUPT_IS_EDGE : INTEGER;
C_EDGE_IS_POSITIVE : INTEGER;
C_ASYNC_INTERRUPT : INTEGER;
C_M0_AXIS_DATA_WIDTH : INTEGER;
C_S0_AXIS_DATA_WIDTH : INTEGER;
C_M1_AXIS_DATA_WIDTH : INTEGER;
C_S1_AXIS_DATA_WIDTH : INTEGER;
C_M2_AXIS_DATA_WIDTH : INTEGER;
C_S2_AXIS_DATA_WIDTH : INTEGER;
C_M3_AXIS_DATA_WIDTH : INTEGER;
C_S3_AXIS_DATA_WIDTH : INTEGER;
C_M4_AXIS_DATA_WIDTH : INTEGER;
C_S4_AXIS_DATA_WIDTH : INTEGER;
C_M5_AXIS_DATA_WIDTH : INTEGER;
C_S5_AXIS_DATA_WIDTH : INTEGER;
C_M6_AXIS_DATA_WIDTH : INTEGER;
C_S6_AXIS_DATA_WIDTH : INTEGER;
C_M7_AXIS_DATA_WIDTH : INTEGER;
C_S7_AXIS_DATA_WIDTH : INTEGER;
C_M8_AXIS_DATA_WIDTH : INTEGER;
C_S8_AXIS_DATA_WIDTH : INTEGER;
C_M9_AXIS_DATA_WIDTH : INTEGER;
C_S9_AXIS_DATA_WIDTH : INTEGER;
C_M10_AXIS_DATA_WIDTH : INTEGER;
C_S10_AXIS_DATA_WIDTH : INTEGER;
C_M11_AXIS_DATA_WIDTH : INTEGER;
C_S11_AXIS_DATA_WIDTH : INTEGER;
C_M12_AXIS_DATA_WIDTH : INTEGER;
C_S12_AXIS_DATA_WIDTH : INTEGER;
C_M13_AXIS_DATA_WIDTH : INTEGER;
C_S13_AXIS_DATA_WIDTH : INTEGER;
C_M14_AXIS_DATA_WIDTH : INTEGER;
C_S14_AXIS_DATA_WIDTH : INTEGER;
C_M15_AXIS_DATA_WIDTH : INTEGER;
C_S15_AXIS_DATA_WIDTH : INTEGER;
C_ICACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_ICACHE : INTEGER;
C_ALLOW_ICACHE_WR : INTEGER;
C_ADDR_TAG_BITS : INTEGER;
C_CACHE_BYTE_SIZE : INTEGER;
C_ICACHE_LINE_LEN : INTEGER;
C_ICACHE_ALWAYS_USED : INTEGER;
C_ICACHE_STREAMS : INTEGER;
C_ICACHE_VICTIMS : INTEGER;
C_ICACHE_FORCE_TAG_LUTRAM : INTEGER;
C_ICACHE_DATA_WIDTH : INTEGER;
C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IC_DATA_WIDTH : INTEGER;
C_M_AXI_IC_ADDR_WIDTH : INTEGER;
C_M_AXI_IC_USER_VALUE : INTEGER;
C_M_AXI_IC_AWUSER_WIDTH : INTEGER;
C_M_AXI_IC_ARUSER_WIDTH : INTEGER;
C_M_AXI_IC_WUSER_WIDTH : INTEGER;
C_M_AXI_IC_RUSER_WIDTH : INTEGER;
C_M_AXI_IC_BUSER_WIDTH : INTEGER;
C_DCACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_DCACHE : INTEGER;
C_ALLOW_DCACHE_WR : INTEGER;
C_DCACHE_ADDR_TAG : INTEGER;
C_DCACHE_BYTE_SIZE : INTEGER;
C_DCACHE_LINE_LEN : INTEGER;
C_DCACHE_ALWAYS_USED : INTEGER;
C_DCACHE_USE_WRITEBACK : INTEGER;
C_DCACHE_VICTIMS : INTEGER;
C_DCACHE_FORCE_TAG_LUTRAM : INTEGER;
C_DCACHE_DATA_WIDTH : INTEGER;
C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DC_DATA_WIDTH : INTEGER;
C_M_AXI_DC_ADDR_WIDTH : INTEGER;
C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_DC_USER_VALUE : INTEGER;
C_M_AXI_DC_AWUSER_WIDTH : INTEGER;
C_M_AXI_DC_ARUSER_WIDTH : INTEGER;
C_M_AXI_DC_WUSER_WIDTH : INTEGER;
C_M_AXI_DC_RUSER_WIDTH : INTEGER;
C_M_AXI_DC_BUSER_WIDTH : INTEGER
);
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Mb_Reset : IN STD_LOGIC;
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Ext_BRK : IN STD_LOGIC;
Ext_NM_BRK : IN STD_LOGIC;
Dbg_Stop : IN STD_LOGIC;
Dbg_Intr : OUT STD_LOGIC;
MB_Halted : OUT STD_LOGIC;
MB_Error : OUT STD_LOGIC;
Wakeup : IN STD_LOGIC_VECTOR(0 TO 1);
Sleep : OUT STD_LOGIC;
Dbg_Wakeup : OUT STD_LOGIC;
Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1);
LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_AWLOCK : OUT STD_LOGIC;
M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWVALID : OUT STD_LOGIC;
M_AXI_IP_AWREADY : IN STD_LOGIC;
M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_WLAST : OUT STD_LOGIC;
M_AXI_IP_WVALID : OUT STD_LOGIC;
M_AXI_IP_WREADY : IN STD_LOGIC;
M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_BVALID : IN STD_LOGIC;
M_AXI_IP_BREADY : OUT STD_LOGIC;
M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_ARLOCK : OUT STD_LOGIC;
M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARVALID : OUT STD_LOGIC;
M_AXI_IP_ARREADY : IN STD_LOGIC;
M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_RLAST : IN STD_LOGIC;
M_AXI_IP_RVALID : IN STD_LOGIC;
M_AXI_IP_RREADY : OUT STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_AWLOCK : OUT STD_LOGIC;
M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WLAST : OUT STD_LOGIC;
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_ARLOCK : OUT STD_LOGIC;
M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RLAST : IN STD_LOGIC;
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trace_Clk : IN STD_LOGIC;
Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35);
Dbg_Trace_Ready : IN STD_LOGIC;
Dbg_Trace_Valid : OUT STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Valid_Instr : OUT STD_LOGIC;
Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Reg_Write : OUT STD_LOGIC;
Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14);
Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7);
Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Exception_Taken : OUT STD_LOGIC;
Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_Jump_Taken : OUT STD_LOGIC;
Trace_Delay_Slot : OUT STD_LOGIC;
Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
Trace_Data_Access : OUT STD_LOGIC;
Trace_Data_Read : OUT STD_LOGIC;
Trace_Data_Write : OUT STD_LOGIC;
Trace_DCache_Req : OUT STD_LOGIC;
Trace_DCache_Hit : OUT STD_LOGIC;
Trace_DCache_Rdy : OUT STD_LOGIC;
Trace_DCache_Read : OUT STD_LOGIC;
Trace_ICache_Req : OUT STD_LOGIC;
Trace_ICache_Hit : OUT STD_LOGIC;
Trace_ICache_Rdy : OUT STD_LOGIC;
Trace_OF_PipeRun : OUT STD_LOGIC;
Trace_EX_PipeRun : OUT STD_LOGIC;
Trace_MEM_PipeRun : OUT STD_LOGIC;
Trace_MB_Halted : OUT STD_LOGIC;
Trace_Jump_Hit : OUT STD_LOGIC;
M0_AXIS_TLAST : OUT STD_LOGIC;
M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M0_AXIS_TVALID : OUT STD_LOGIC;
M0_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TREADY : IN STD_LOGIC;
M3_AXIS_TLAST : OUT STD_LOGIC;
M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M3_AXIS_TVALID : OUT STD_LOGIC;
M3_AXIS_TREADY : IN STD_LOGIC;
M4_AXIS_TLAST : OUT STD_LOGIC;
M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M4_AXIS_TVALID : OUT STD_LOGIC;
M4_AXIS_TREADY : IN STD_LOGIC;
M5_AXIS_TLAST : OUT STD_LOGIC;
M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M5_AXIS_TVALID : OUT STD_LOGIC;
M5_AXIS_TREADY : IN STD_LOGIC;
M6_AXIS_TLAST : OUT STD_LOGIC;
M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M6_AXIS_TVALID : OUT STD_LOGIC;
M6_AXIS_TREADY : IN STD_LOGIC;
M7_AXIS_TLAST : OUT STD_LOGIC;
M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M7_AXIS_TVALID : OUT STD_LOGIC;
M7_AXIS_TREADY : IN STD_LOGIC;
M8_AXIS_TLAST : OUT STD_LOGIC;
M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M8_AXIS_TVALID : OUT STD_LOGIC;
M8_AXIS_TREADY : IN STD_LOGIC;
M9_AXIS_TLAST : OUT STD_LOGIC;
M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M9_AXIS_TVALID : OUT STD_LOGIC;
M9_AXIS_TREADY : IN STD_LOGIC;
M10_AXIS_TLAST : OUT STD_LOGIC;
M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M10_AXIS_TVALID : OUT STD_LOGIC;
M10_AXIS_TREADY : IN STD_LOGIC;
M11_AXIS_TLAST : OUT STD_LOGIC;
M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M11_AXIS_TVALID : OUT STD_LOGIC;
M11_AXIS_TREADY : IN STD_LOGIC;
M12_AXIS_TLAST : OUT STD_LOGIC;
M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M12_AXIS_TVALID : OUT STD_LOGIC;
M12_AXIS_TREADY : IN STD_LOGIC;
M13_AXIS_TLAST : OUT STD_LOGIC;
M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M13_AXIS_TVALID : OUT STD_LOGIC;
M13_AXIS_TREADY : IN STD_LOGIC;
M14_AXIS_TLAST : OUT STD_LOGIC;
M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M14_AXIS_TVALID : OUT STD_LOGIC;
M14_AXIS_TREADY : IN STD_LOGIC;
M15_AXIS_TLAST : OUT STD_LOGIC;
M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M15_AXIS_TVALID : OUT STD_LOGIC;
M15_AXIS_TREADY : IN STD_LOGIC;
S0_AXIS_TLAST : IN STD_LOGIC;
S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXIS_TVALID : IN STD_LOGIC;
S0_AXIS_TREADY : OUT STD_LOGIC;
S1_AXIS_TLAST : IN STD_LOGIC;
S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXIS_TVALID : IN STD_LOGIC;
S1_AXIS_TREADY : OUT STD_LOGIC;
S2_AXIS_TLAST : IN STD_LOGIC;
S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXIS_TVALID : IN STD_LOGIC;
S2_AXIS_TREADY : OUT STD_LOGIC;
S3_AXIS_TLAST : IN STD_LOGIC;
S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXIS_TVALID : IN STD_LOGIC;
S3_AXIS_TREADY : OUT STD_LOGIC;
S4_AXIS_TLAST : IN STD_LOGIC;
S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXIS_TVALID : IN STD_LOGIC;
S4_AXIS_TREADY : OUT STD_LOGIC;
S5_AXIS_TLAST : IN STD_LOGIC;
S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXIS_TVALID : IN STD_LOGIC;
S5_AXIS_TREADY : OUT STD_LOGIC;
S6_AXIS_TLAST : IN STD_LOGIC;
S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXIS_TVALID : IN STD_LOGIC;
S6_AXIS_TREADY : OUT STD_LOGIC;
S7_AXIS_TLAST : IN STD_LOGIC;
S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXIS_TVALID : IN STD_LOGIC;
S7_AXIS_TREADY : OUT STD_LOGIC;
S8_AXIS_TLAST : IN STD_LOGIC;
S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S8_AXIS_TVALID : IN STD_LOGIC;
S8_AXIS_TREADY : OUT STD_LOGIC;
S9_AXIS_TLAST : IN STD_LOGIC;
S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S9_AXIS_TVALID : IN STD_LOGIC;
S9_AXIS_TREADY : OUT STD_LOGIC;
S10_AXIS_TLAST : IN STD_LOGIC;
S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S10_AXIS_TVALID : IN STD_LOGIC;
S10_AXIS_TREADY : OUT STD_LOGIC;
S11_AXIS_TLAST : IN STD_LOGIC;
S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S11_AXIS_TVALID : IN STD_LOGIC;
S11_AXIS_TREADY : OUT STD_LOGIC;
S12_AXIS_TLAST : IN STD_LOGIC;
S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S12_AXIS_TVALID : IN STD_LOGIC;
S12_AXIS_TREADY : OUT STD_LOGIC;
S13_AXIS_TLAST : IN STD_LOGIC;
S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S13_AXIS_TVALID : IN STD_LOGIC;
S13_AXIS_TREADY : OUT STD_LOGIC;
S14_AXIS_TLAST : IN STD_LOGIC;
S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S14_AXIS_TVALID : IN STD_LOGIC;
S14_AXIS_TREADY : OUT STD_LOGIC;
S15_AXIS_TLAST : IN STD_LOGIC;
S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S15_AXIS_TVALID : IN STD_LOGIC;
S15_AXIS_TREADY : OUT STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_WACK : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RACK : OUT STD_LOGIC;
M_AXI_IC_ACVALID : IN STD_LOGIC;
M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ACREADY : OUT STD_LOGIC;
M_AXI_IC_CRVALID : OUT STD_LOGIC;
M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_CRREADY : IN STD_LOGIC;
M_AXI_IC_CDVALID : OUT STD_LOGIC;
M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_CDLAST : OUT STD_LOGIC;
M_AXI_IC_CDREADY : IN STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_WACK : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC;
M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RACK : OUT STD_LOGIC;
M_AXI_DC_ACVALID : IN STD_LOGIC;
M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ACREADY : OUT STD_LOGIC;
M_AXI_DC_CRVALID : OUT STD_LOGIC;
M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_CRREADY : IN STD_LOGIC;
M_AXI_DC_CDVALID : OUT STD_LOGIC;
M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_CDLAST : OUT STD_LOGIC;
M_AXI_DC_CDREADY : IN STD_LOGIC
);
END COMPONENT MicroBlaze;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "MicroBlaze,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_0_arch : ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze,x_ipVersion=9.5,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_SCO=0,C_FREQ=100000000,C_USE_CONFIG_RESET=0,C_NUM_SYNC_FF_CLK=2,C_NUM_SYNC_FF_CLK_IRQ=1,C_NUM_SYNC_FF_CLK_DEBUG=2,C_NUM_SYNC_FF_DBG_CLK=1,C_FAULT_TOLERANT=0,C_ECC_USE_CE_EXCEPTION=0,C_LOCKSTEP_SLAVE=0,C_ENDIANNESS=1,C_FAMILY=artix7,C_DATA_SIZE=32,C_INSTANCE=design_1_microblaze_0_0,C_AVOID_PRIMITIVES=0,C_AREA_OPTIMIZED=0,C_OPTIMIZATION=0,C_INTERCONNECT=2,C_BASE_VECTORS=0x00000000,C_M_AXI_DP_THREAD_ID_WIDTH=1,C_M_AXI_DP_DATA_WIDTH=32,C_M_AXI_DP_ADDR_WIDTH=32,C_M_AXI_DP_EXCLUSIVE_ACCESS=0,C_M_AXI_D_BUS_EXCEPTION=0,C_M_AXI_IP_THREAD_ID_WIDTH=1,C_M_AXI_IP_DATA_WIDTH=32,C_M_AXI_IP_ADDR_WIDTH=32,C_M_AXI_I_BUS_EXCEPTION=0,C_D_LMB=1,C_D_AXI=1,C_I_LMB=1,C_I_AXI=0,C_USE_MSR_INSTR=0,C_USE_PCMP_INSTR=0,C_USE_BARREL=0,C_USE_DIV=0,C_USE_HW_MUL=0,C_USE_FPU=0,C_USE_REORDER_INSTR=1,C_UNALIGNED_EXCEPTIONS=0,C_ILL_OPCODE_EXCEPTION=0,C_DIV_ZERO_EXCEPTION=0,C_FPU_EXCEPTION=0,C_FSL_LINKS=0,C_USE_EXTENDED_FSL_INSTR=0,C_FSL_EXCEPTION=0,C_USE_STACK_PROTECTION=0,C_IMPRECISE_EXCEPTIONS=0,C_USE_INTERRUPT=2,C_USE_EXT_BRK=0,C_USE_EXT_NM_BRK=0,C_USE_MMU=0,C_MMU_DTLB_SIZE=4,C_MMU_ITLB_SIZE=2,C_MMU_TLB_ACCESS=3,C_MMU_ZONES=16,C_MMU_PRIVILEGED_INSTR=0,C_USE_BRANCH_TARGET_CACHE=0,C_BRANCH_TARGET_CACHE_SIZE=0,C_PC_WIDTH=32,C_PVR=0,C_PVR_USER1=0x00,C_PVR_USER2=0x00000000,C_DYNAMIC_BUS_SIZING=0,C_RESET_MSR=0x00000000,C_OPCODE_0x0_ILLEGAL=0,C_DEBUG_ENABLED=1,C_NUMBER_OF_PC_BRK=1,C_NUMBER_OF_RD_ADDR_BRK=0,C_NUMBER_OF_WR_ADDR_BRK=0,C_DEBUG_EVENT_COUNTERS=5,C_DEBUG_LATENCY_COUNTERS=1,C_DEBUG_COUNTER_WIDTH=32,C_DEBUG_TRACE_SIZE=8192,C_DEBUG_EXTERNAL_TRACE=0,C_DEBUG_PROFILE_SIZE=0,C_INTERRUPT_IS_EDGE=0,C_EDGE_IS_POSITIVE=1,C_ASYNC_INTERRUPT=1,C_M0_AXIS_DATA_WIDTH=32,C_S0_AXIS_DATA_WIDTH=32,C_M1_AXIS_DATA_WIDTH=32,C_S1_AXIS_DATA_WIDTH=32,C_M2_AXIS_DATA_WIDTH=32,C_S2_AXIS_DATA_WIDTH=32,C_M3_AXIS_DATA_WIDTH=32,C_S3_AXIS_DATA_WIDTH=32,C_M4_AXIS_DATA_WIDTH=32,C_S4_AXIS_DATA_WIDTH=32,C_M5_AXIS_DATA_WIDTH=32,C_S5_AXIS_DATA_WIDTH=32,C_M6_AXIS_DATA_WIDTH=32,C_S6_AXIS_DATA_WIDTH=32,C_M7_AXIS_DATA_WIDTH=32,C_S7_AXIS_DATA_WIDTH=32,C_M8_AXIS_DATA_WIDTH=32,C_S8_AXIS_DATA_WIDTH=32,C_M9_AXIS_DATA_WIDTH=32,C_S9_AXIS_DATA_WIDTH=32,C_M10_AXIS_DATA_WIDTH=32,C_S10_AXIS_DATA_WIDTH=32,C_M11_AXIS_DATA_WIDTH=32,C_S11_AXIS_DATA_WIDTH=32,C_M12_AXIS_DATA_WIDTH=32,C_S12_AXIS_DATA_WIDTH=32,C_M13_AXIS_DATA_WIDTH=32,C_S13_AXIS_DATA_WIDTH=32,C_M14_AXIS_DATA_WIDTH=32,C_S14_AXIS_DATA_WIDTH=32,C_M15_AXIS_DATA_WIDTH=32,C_S15_AXIS_DATA_WIDTH=32,C_ICACHE_BASEADDR=0x60000000,C_ICACHE_HIGHADDR=0x60ffffff,C_USE_ICACHE=1,C_ALLOW_ICACHE_WR=1,C_ADDR_TAG_BITS=10,C_CACHE_BYTE_SIZE=16384,C_ICACHE_LINE_LEN=4,C_ICACHE_ALWAYS_USED=1,C_ICACHE_STREAMS=0,C_ICACHE_VICTIMS=0,C_ICACHE_FORCE_TAG_LUTRAM=0,C_ICACHE_DATA_WIDTH=0,C_M_AXI_IC_THREAD_ID_WIDTH=1,C_M_AXI_IC_DATA_WIDTH=32,C_M_AXI_IC_ADDR_WIDTH=32,C_M_AXI_IC_USER_VALUE=31,C_M_AXI_IC_AWUSER_WIDTH=5,C_M_AXI_IC_ARUSER_WIDTH=5,C_M_AXI_IC_WUSER_WIDTH=1,C_M_AXI_IC_RUSER_WIDTH=1,C_M_AXI_IC_BUSER_WIDTH=1,C_DCACHE_BASEADDR=0x60000000,C_DCACHE_HIGHADDR=0x60ffffff,C_USE_DCACHE=1,C_ALLOW_DCACHE_WR=1,C_DCACHE_ADDR_TAG=10,C_DCACHE_BYTE_SIZE=16384,C_DCACHE_LINE_LEN=4,C_DCACHE_ALWAYS_USED=1,C_DCACHE_USE_WRITEBACK=0,C_DCACHE_VICTIMS=0,C_DCACHE_FORCE_TAG_LUTRAM=0,C_DCACHE_DATA_WIDTH=0,C_M_AXI_DC_THREAD_ID_WIDTH=1,C_M_AXI_DC_DATA_WIDTH=32,C_M_AXI_DC_ADDR_WIDTH=32,C_M_AXI_DC_EXCLUSIVE_ACCESS=0,C_M_AXI_DC_USER_VALUE=31,C_M_AXI_DC_AWUSER_WIDTH=5,C_M_AXI_DC_ARUSER_WIDTH=5,C_M_AXI_DC_WUSER_WIDTH=1,C_M_AXI_DC_RUSER_WIDTH=1,C_M_AXI_DC_BUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY";
ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE";
ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY";
BEGIN
U0 : MicroBlaze
GENERIC MAP (
C_SCO => 0,
C_FREQ => 100000000,
C_USE_CONFIG_RESET => 0,
C_NUM_SYNC_FF_CLK => 2,
C_NUM_SYNC_FF_CLK_IRQ => 1,
C_NUM_SYNC_FF_CLK_DEBUG => 2,
C_NUM_SYNC_FF_DBG_CLK => 1,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 1,
C_FAMILY => "artix7",
C_DATA_SIZE => 32,
C_INSTANCE => "design_1_microblaze_0_0",
C_AVOID_PRIMITIVES => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_BASE_VECTORS => X"00000000",
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_D_LMB => 1,
C_D_AXI => 1,
C_I_LMB => 1,
C_I_AXI => 0,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_LINKS => 0,
C_USE_EXTENDED_FSL_INSTR => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_IMPRECISE_EXCEPTIONS => 0,
C_USE_INTERRUPT => 2,
C_USE_EXT_BRK => 0,
C_USE_EXT_NM_BRK => 0,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DYNAMIC_BUS_SIZING => 0,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_DEBUG_EVENT_COUNTERS => 5,
C_DEBUG_LATENCY_COUNTERS => 1,
C_DEBUG_COUNTER_WIDTH => 32,
C_DEBUG_TRACE_SIZE => 8192,
C_DEBUG_EXTERNAL_TRACE => 0,
C_DEBUG_PROFILE_SIZE => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_ASYNC_INTERRUPT => 1,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"60000000",
C_ICACHE_HIGHADDR => X"60ffffff",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 10,
C_CACHE_BYTE_SIZE => 16384,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_STREAMS => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 31,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"60000000",
C_DCACHE_HIGHADDR => X"60ffffff",
C_USE_DCACHE => 1,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 10,
C_DCACHE_BYTE_SIZE => 16384,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 1,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 31,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1
)
PORT MAP (
Clk => Clk,
Reset => Reset,
Mb_Reset => '0',
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
Dbg_Disable => '0',
Interrupt => Interrupt,
Interrupt_Address => Interrupt_Address,
Interrupt_Ack => Interrupt_Ack,
Ext_BRK => '0',
Ext_NM_BRK => '0',
Dbg_Stop => '0',
Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)),
Instr_Addr => Instr_Addr,
Instr => Instr,
IFetch => IFetch,
I_AS => I_AS,
IReady => IReady,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
M_AXI_IP_AWREADY => '0',
M_AXI_IP_WREADY => '0',
M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_BVALID => '0',
M_AXI_IP_ARREADY => '0',
M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_RLAST => '0',
M_AXI_IP_RVALID => '0',
Data_Addr => Data_Addr,
Data_Read => Data_Read,
Data_Write => Data_Write,
D_AS => D_AS,
Read_Strobe => Read_Strobe,
Write_Strobe => Write_Strobe,
DReady => DReady,
DWait => DWait,
DCE => DCE,
DUE => DUE,
Byte_Enable => Byte_Enable,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => '0',
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
Dbg_Clk => Dbg_Clk,
Dbg_TDI => Dbg_TDI,
Dbg_TDO => Dbg_TDO,
Dbg_Reg_En => Dbg_Reg_En,
Dbg_Shift => Dbg_Shift,
Dbg_Capture => Dbg_Capture,
Dbg_Update => Dbg_Update,
Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trace_Clk => '0',
Dbg_Trace_Ready => '0',
Debug_Rst => Debug_Rst,
M0_AXIS_TREADY => '0',
M1_AXIS_TREADY => '0',
M2_AXIS_TREADY => '0',
M3_AXIS_TREADY => '0',
M4_AXIS_TREADY => '0',
M5_AXIS_TREADY => '0',
M6_AXIS_TREADY => '0',
M7_AXIS_TREADY => '0',
M8_AXIS_TREADY => '0',
M9_AXIS_TREADY => '0',
M10_AXIS_TREADY => '0',
M11_AXIS_TREADY => '0',
M12_AXIS_TREADY => '0',
M13_AXIS_TREADY => '0',
M14_AXIS_TREADY => '0',
M15_AXIS_TREADY => '0',
S0_AXIS_TLAST => '0',
S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S0_AXIS_TVALID => '0',
S1_AXIS_TLAST => '0',
S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S1_AXIS_TVALID => '0',
S2_AXIS_TLAST => '0',
S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S2_AXIS_TVALID => '0',
S3_AXIS_TLAST => '0',
S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXIS_TVALID => '0',
S4_AXIS_TLAST => '0',
S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXIS_TVALID => '0',
S5_AXIS_TLAST => '0',
S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXIS_TVALID => '0',
S6_AXIS_TLAST => '0',
S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXIS_TVALID => '0',
S7_AXIS_TLAST => '0',
S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXIS_TVALID => '0',
S8_AXIS_TLAST => '0',
S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S8_AXIS_TVALID => '0',
S9_AXIS_TLAST => '0',
S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S9_AXIS_TVALID => '0',
S10_AXIS_TLAST => '0',
S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S10_AXIS_TVALID => '0',
S11_AXIS_TLAST => '0',
S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S11_AXIS_TVALID => '0',
S12_AXIS_TLAST => '0',
S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S12_AXIS_TVALID => '0',
S13_AXIS_TLAST => '0',
S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S13_AXIS_TVALID => '0',
S14_AXIS_TLAST => '0',
S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S14_AXIS_TVALID => '0',
S15_AXIS_TLAST => '0',
S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S15_AXIS_TVALID => '0',
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ACVALID => '0',
M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_IC_CRREADY => '0',
M_AXI_IC_CDREADY => '0',
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ACVALID => '0',
M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_DC_CRREADY => '0',
M_AXI_DC_CDREADY => '0'
);
END design_1_microblaze_0_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/a3d1bdff/hdl/src/vhdl/uartlite_tx.vhd
|
6
|
22859
|
-------------------------------------------------------------------------------
-- uartlite_tx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_tx.vhd
-- Version: v2.0
-- Description: UART Lite Transmit Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.UNSIGNED;
use IEEE.numeric_std.to_unsigned;
use IEEE.numeric_std."-";
library lib_srl_fifo_v1_0;
-- dynshreg_i_f refered from proc_common_v4_00_a
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-- srl_fifo_f refered from proc_common_v4_00_a
use lib_srl_fifo_v1_0.srl_fifo_f;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- TX -- Transmit Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Write_TX_FIFO -- Write transmit FIFO
-- Reset_TX_FIFO -- Reset transmit FIFO
-- TX_Data -- Transmit data input
-- TX_Buffer_Full -- Transmit buffer full
-- TX_Buffer_Empty -- Transmit buffer empty
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_tx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
TX : out std_logic;
Write_TX_FIFO : in std_logic;
Reset_TX_FIFO : in std_logic;
TX_Data : in std_logic_vector(0 to C_DATA_BITS-1);
TX_Buffer_Full : out std_logic;
TX_Buffer_Empty : out std_logic
);
end entity uartlite_tx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_tx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
-------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------
constant MUX_SEL_INIT : std_logic_vector(0 to 2) :=
std_logic_vector(to_unsigned(C_DATA_BITS-1, 3));
-------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------
signal parity : std_logic;
signal tx_Run1 : std_logic;
signal select_Parity : std_logic;
signal data_to_transfer : std_logic_vector(0 to C_DATA_BITS-1);
signal div16 : std_logic;
signal tx_Data_Enable : std_logic;
signal tx_Start : std_logic;
signal tx_DataBits : std_logic;
signal tx_Run : std_logic;
signal mux_sel : std_logic_vector(0 to 2);
signal mux_sel_is_zero : std_logic;
signal mux_01 : std_logic;
signal mux_23 : std_logic;
signal mux_45 : std_logic;
signal mux_67 : std_logic;
signal mux_0123 : std_logic;
signal mux_4567 : std_logic;
signal mux_Out : std_logic;
signal serial_Data : std_logic;
signal fifo_Read : std_logic;
signal fifo_Data_Present : std_logic := '0';
signal fifo_Data_Empty : std_logic;
signal fifo_DOut : std_logic_vector(0 to C_DATA_BITS-1);
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal tx_buffer_full_i : std_logic;
signal TX_FIFO_Reset : std_logic;
begin -- architecture IMP
---------------------------------------------------------------------------
--MID_START_BIT_SRL16_I : Shift register is used to generate div16 that
-- gets shifted for 16 times(as Addr = 15) when
-- EN_16x_Baud is high.
---------------------------------------------------------------------------
MID_START_BIT_SRL16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_INIT_VALUE => X"8000",
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => div16,
Dout(0) => div16
);
------------------------------------------------------------------------
-- TX_DATA_ENABLE_DFF : tx_Data_Enable is '1' when div16 is 1 and
-- EN_16x_Baud is 1. It will deasserted in the
-- next clock cycle.
------------------------------------------------------------------------
TX_DATA_ENABLE_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Data_Enable <= '0';
else
if (tx_Data_Enable = '1') then
tx_Data_Enable <= '0';
elsif (EN_16x_Baud = '1') then
tx_Data_Enable <= div16;
end if;
end if;
end if;
end process TX_DATA_ENABLE_DFF;
------------------------------------------------------------------------
-- TX_START_DFF : tx_start is '1' for the start bit in a transmission
------------------------------------------------------------------------
TX_START_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Start <= '0';
else
tx_Start <= (not(tx_Run) and (tx_Start or
(fifo_Data_Present and tx_Data_Enable)));
end if;
end if;
end process TX_START_DFF;
--------------------------------------------------------------------------
-- TX_DATA_DFF : tx_DataBits is '1' during all databits transmission
--------------------------------------------------------------------------
TX_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_DataBits <= '0';
else
tx_DataBits <= (not(fifo_Read) and (tx_DataBits or
(tx_Start and tx_Data_Enable)));
end if;
end if;
end process TX_DATA_DFF;
-------------------------------------------------------------------------
-- COUNTER : If mux_sel is zero then reload with the init value else if
-- tx_DataBits = '1', decrement
-------------------------------------------------------------------------
COUNTER : process (Clk) is
begin -- process Mux_Addr_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
mux_sel <= std_logic_vector(to_unsigned(C_DATA_BITS-1,
mux_sel'length));
elsif (tx_Data_Enable = '1') then
if (mux_sel_is_zero = '1') then
mux_sel <= MUX_SEL_INIT;
elsif (tx_DataBits = '1') then
mux_sel <= std_logic_vector(UNSIGNED(mux_sel) - 1);
end if;
end if;
end if;
end process COUNTER;
------------------------------------------------------------------------
-- Detecting when mux_sel is zero, i.e. all data bits are transfered
------------------------------------------------------------------------
mux_sel_is_zero <= '1' when mux_sel = "000" else '0';
--------------------------------------------------------------------------
-- FIFO_READ_DFF : Read out the next data from the transmit fifo when the
-- data has been transmitted
--------------------------------------------------------------------------
FIFO_READ_DFF : process (Clk) is
begin -- process FIFO_Read_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Read <= '0';
else
fifo_Read <= tx_Data_Enable and mux_sel_is_zero;
end if;
end if;
end process FIFO_READ_DFF;
--------------------------------------------------------------------------
-- Select which bit within the data word to transmit
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- PARITY_BIT_INSERTION : Need special treatment for inserting the parity
-- bit because of parity generation
--------------------------------------------------------------------------
data_to_transfer(0 to C_DATA_BITS-2) <= fifo_DOut(0 to C_DATA_BITS-2);
data_to_transfer(C_DATA_BITS-1) <= parity when select_Parity = '1' else
fifo_DOut(C_DATA_BITS-1);
mux_01 <= data_to_transfer(1) when mux_sel(2) = '1' else
data_to_transfer(0);
mux_23 <= data_to_transfer(3) when mux_sel(2) = '1' else
data_to_transfer(2);
--------------------------------------------------------------------------
-- DATA_BITS_IS_5 : Select total 5 data bits when C_DATA_BITS = 5
--------------------------------------------------------------------------
DATA_BITS_IS_5 : if (C_DATA_BITS = 5) generate
mux_45 <= data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_5;
--------------------------------------------------------------------------
-- DATA_BITS_IS_6 : Select total 6 data bits when C_DATA_BITS = 6
--------------------------------------------------------------------------
DATA_BITS_IS_6 : if (C_DATA_BITS = 6) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= '0';
end generate DATA_BITS_IS_6;
--------------------------------------------------------------------------
-- DATA_BITS_IS_7 : Select total 7 data bits when C_DATA_BITS = 7
--------------------------------------------------------------------------
DATA_BITS_IS_7 : if (C_DATA_BITS = 7) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(6);
end generate DATA_BITS_IS_7;
--------------------------------------------------------------------------
-- DATA_BITS_IS_8 : Select total 8 data bits when C_DATA_BITS = 8
--------------------------------------------------------------------------
DATA_BITS_IS_8 : if (C_DATA_BITS = 8) generate
mux_45 <= data_to_transfer(5) when mux_sel(2) = '1' else
data_to_transfer(4);
mux_67 <= data_to_transfer(7) when mux_sel(2) = '1' else
data_to_transfer(6);
end generate DATA_BITS_IS_8;
mux_0123 <= mux_23 when mux_sel(1) = '1' else mux_01;
mux_4567 <= mux_67 when mux_sel(1) = '1' else mux_45;
mux_Out <= mux_4567 when mux_sel(0) = '1' else mux_0123;
--------------------------------------------------------------------------
-- SERIAL_DATA_DFF : Register the mux_Out
--------------------------------------------------------------------------
SERIAL_DATA_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
serial_Data <= '0';
else
serial_Data <= mux_Out;
end if;
end if;
end process SERIAL_DATA_DFF;
--------------------------------------------------------------------------
-- SERIAL_OUT_DFF :Force a '0' when tx_start is '1', Start_bit
-- Force a '1' when tx_run is '0', Idle
-- otherwise put out the serial_data
--------------------------------------------------------------------------
SERIAL_OUT_DFF : process (Clk) is
begin -- process Serial_Out_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
TX <= '1';
else
TX <= (not(tx_Run) or serial_Data) and (not(tx_Start));
end if;
end if;
end process SERIAL_OUT_DFF;
--------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
--------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (tx_Start = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (tx_Data_Enable = '1') then
parity <= parity xor serial_Data;
end if;
end if;
end process PARITY_DFF;
TX_RUN1_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
tx_Run1 <= '0';
elsif (tx_Data_Enable = '1') then
tx_Run1 <= tx_DataBits;
end if;
end if;
end process TX_RUN1_DFF;
tx_Run <= tx_Run1 or tx_DataBits;
SELECT_PARITY_DFF : process (Clk) is
begin
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
select_Parity <= '0';
elsif (tx_Data_Enable = '1') then
select_Parity <= mux_sel_is_zero;
end if;
end if;
end process SELECT_PARITY_DFF;
end generate USING_PARITY;
--------------------------------------------------------------------------
-- NO_PARITY : When C_USE_PARITY = 0 select parity as '0'
--------------------------------------------------------------------------
NO_PARITY : if (C_USE_PARITY = 0) generate
tx_Run <= tx_DataBits;
select_Parity <= '0';
end generate NO_PARITY;
--------------------------------------------------------------------------
-- Write TX FIFO when FIFO is not full when AXI writes data in TX FIFO
--------------------------------------------------------------------------
fifo_wr <= Write_TX_FIFO and (not tx_buffer_full_i);
--------------------------------------------------------------------------
-- Read TX FIFO when FIFO is not empty when AXI reads data from TX FIFO
--------------------------------------------------------------------------
fifo_rd <= fifo_Read and (not fifo_Data_Empty);
--------------------------------------------------------------------------
-- Reset TX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
TX_FIFO_Reset <= Reset_TX_FIFO or Reset;
--------------------------------------------------------------------------
-- SRL_FIFO_I : Transmit FIFO Interface
--------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => TX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => TX_Data,
FIFO_Read => fifo_rd,
Data_Out => fifo_DOut,
FIFO_Full => tx_buffer_full_i,
FIFO_Empty => fifo_Data_Empty
);
TX_Buffer_Full <= tx_buffer_full_i;
TX_Buffer_Empty <= fifo_Data_Empty;
fifo_Data_Present <= not fifo_Data_Empty;
end architecture RTL;
|
gpl-3.0
|
FOSSEE/eSim
|
Examples/Mixed_Signal/custom_mixed_signal/customblock.vhdl
|
1
|
1276
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity customblock is
port(C : in std_logic;
D : in std_logic;
Q : out std_logic);
end customblock;
architecture bhv of customblock is
signal count: integer:=1; --counts number of CLOCK cycles
signal period: integer:=10; --PWM signal period is 10 times of clock period
signal boost : integer:=9; --number of clock pulses during T_ON
signal buck : integer:=1; --number of clock pulses during T_OFF
begin
process (C,D)
begin
if(C='1' and C'event) then
count<=count+1;
if(count=period)then -- resets count for period
count<=1;
end if;
if(D='1') then --boost duty cycle when compartor output is high--
if(count<=boost)then
Q<='1';
elsif(count>boost) then
Q<='0';
end if;
end if;
if(D='0')then --buck duty cycle when compartor output is low--
if(count<=buck)then --
Q<='1';
elsif(count>buck)then
Q<='0';
end if;
end if;
end if;
end process;
end bhv;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/a3d1bdff/hdl/src/vhdl/dynshreg_i_f.vhd
|
6
|
12363
|
-- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0;
use lib_pkg_v1_0.all;
use lib_pkg_v1_0.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/cdd36762/hdl/vhdl/checkbit_handler.vhd
|
4
|
22860
|
-------------------------------------------------------------------------------
-- checkbit_handler.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: gen_checkbits.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- gen_checkbits.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity checkbit_handler is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_ENCODE : boolean := true);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
architecture IMP of checkbit_handler is
component XOR18 is
generic (
C_TARGET : TARGET_FAMILY_TYPE);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
component ParityEnable
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic);
end component ParityEnable;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_TARGET => C_TARGET)
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (
C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_TARGET => C_TARGET) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
-- Unused
Syndrome <= (others => '0');
UE <= '0';
CE <= '0';
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6);
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_3_to_5 : std_logic_vector(3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
Parity_chk3_3 : ParityEnable
generic map (C_TARGET => C_TARGET, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
Parity_chk4_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 2)
port map (
InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
Parity_chk6_7 : Parity
generic map (C_TARGET => C_TARGET, C_SIZE => 6)
port map (
InA => chk6_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(6)); -- [out std_logic]
Syndrome <= syndrome_i;
syndrome_3_to_5 <= (chk3_1(0) xor chk3_1(1)) & (chk4_1(0) xor chk4_1(1)) & syndrome_i(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101") else
'0';
CE <= '0' when (Enable_ECC = '0') else
(syndrome_i(6) or CE_Q) when (syndrome_3_to_5_multi = '0') else
CE_Q;
ue_i_0 <= '0' when (Enable_ECC = '0') else
'1' when (syndrome_3_to_5_zero = '0') or (syndrome_i(0 to 2) /= "000") else
UE_Q;
ue_i_1 <= '0' when (Enable_ECC = '0') else
(syndrome_3_to_5_multi or UE_Q);
Use_FPGA: if (C_TARGET /= RTL) generate
UE_MUXF7 : MB_MUXF7
generic map (
C_TARGET => C_TARGET)
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => syndrome_i(6),
O => UE);
end generate Use_FPGA;
Use_RTL: if (C_TARGET = RTL) generate
UE <= ue_i_1 when syndrome_i(6) = '1' else ue_i_0;
end generate Use_RTL;
-- Unused
CheckOut <= (others => '0');
end generate Decode_Bits;
end architecture IMP;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_timer_v2_0/de85f913/hdl/src/vhdl/count_module.vhd
|
7
|
9603
|
-------------------------------------------------------------------------------
-- count_module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: count_module.vhd
-- Version: v2.0
-- Description: Module with one counter and load register
--
-------------------------------------------------------------------------------
-- Structure:
--
-- count_module.vhd
-- -- counter_f.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_COUNT_WIDTH -- Width of the counter
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- clock
-- Reset -- reset
-- Load_DBus -- Count Load bus
-- Load_Counter_Reg -- Counter load control
-- Load_Load_Reg -- Load register control
-- Write_Load_Reg -- Write Control of TLR reg
-- CaptGen_Mux_Sel -- Mux select for capture and generate data
-- Counter_En -- Counter enable
-- Count_Down -- Count down
-- BE -- Byte enable
-- LoadReg_DBus -- Load reg bus
-- CounterReg_DBus -- Counter reg bus
-- Counter_TC -- counter Carry out signal
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.FDRE;
library axi_timer_v2_0;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity count_module is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32
);
port (
Clk : in std_logic;
Reset : in std_logic;
Load_DBus : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Load_Counter_Reg : in std_logic;
Load_Load_Reg : in std_logic;
Write_Load_Reg : in std_logic;
CaptGen_Mux_Sel : in std_logic;
Counter_En : in std_logic;
Count_Down : in std_logic;
BE : in std_Logic_vector(0 to 3);
LoadReg_DBus : out std_logic_vector(0 to C_COUNT_WIDTH-1);
CounterReg_DBus : out std_logic_vector(0 to C_COUNT_WIDTH-1);
Counter_TC : out std_logic
);
end entity count_module;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of count_module is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Signal Declaration
signal iCounterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal loadRegIn : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal load_Reg : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal load_load_reg_be : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal carry_out : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- Architecture imp
-------------------------------------------------------------------------------
--CAPTGEN_MUX_PROCESS : Process to implement mux the Load_DBus and
--iCounterReg_DBus
-------------------------------------------------------------------------------
CAPTGEN_MUX_PROCESS: process (CaptGen_Mux_Sel,Load_DBus,iCounterReg_DBus ) is
begin
if CaptGen_Mux_Sel='1' then
loadRegIn <= Load_DBus;
else
loadRegIn <= iCounterReg_DBus;
end if;
end process CAPTGEN_MUX_PROCESS;
-------------------------------------------------------------------------------
--LOAD_REG_GEN: To generate load register
-------------------------------------------------------------------------------
LOAD_REG_GEN: for i in 0 to C_COUNT_WIDTH-1 generate
load_load_reg_be(i) <= Load_Load_Reg or
(Write_Load_Reg and BE((i-C_COUNT_WIDTH+32)/8));
LOAD_REG_I: component FDRE
port map (
Q => load_Reg(i), -- [out]
C => Clk, -- [in]
CE => load_load_reg_be(i), -- [in]
D => loadRegIn(i), -- [in]
R => Reset -- [in]
);
end generate LOAD_REG_GEN;
-------------------------------------------------------------------------------
--counter_f module is instantiated
-------------------------------------------------------------------------------
COUNTER_I: entity axi_timer_v2_0.counter_f
generic map (
C_NUM_BITS => C_COUNT_WIDTH, -- [integer]
C_FAMILY => C_FAMILY -- [string]
)
port map(
Clk => Clk, -- [in std_logic]
Rst => Reset, -- [in std_logic]
Load_In => load_Reg, -- [in std_logic_vector]
Count_Enable => Counter_En, -- [in std_logic]
Count_Load => Load_Counter_Reg, -- [in std_logic]
Count_Down => Count_Down, -- [in std_logic]
Count_Out => iCounterReg_DBus, -- [out std_logic_vector]
Carry_Out => carry_out -- [out std_logic]
);
Counter_TC <= carry_out;
LoadReg_DBus <= load_Reg;
CounterReg_DBus <= iCounterReg_DBus;
end architecture imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rx_fifo_disposer.vhd
|
4
|
28176
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo_disposer.vhd
--
-- Version: v1.01.a
-- Description: This
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo_disposer is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end rx_fifo_disposer;
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_ACTIVE -- Assertion level for Reset signal.
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo_disposer is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
-- Signal names begin with a lowercase letter. User defined types and the
-- enumerated values with a type are all uppercase letters.
-- Signals of a user-defined type should be declared after the type declaration
-- Group signals by interfaces
------------------------------------------------------------------------------
type STATES_TYPE is (
IDLE_ClK_L,
IDLE_ClK_H,
RX_100_RD_FIFO_ClK_L,
RX_100_NIB_0_CLK_L,
RX_100_NIB_0_CLK_H,
RX_100_NIB_1_CLK_L,
RX_100_NIB_1_CLK_H,
RX_100_NIB_1_RD_FIFO_CLK_H,
RX_10_RD_FIFO_CLK_L,
RX_10_NIB_0_00_CLK_L,
RX_10_NIB_0_01_CLK_L,
RX_10_NIB_0_02_CLK_L,
RX_10_NIB_0_03_CLK_L,
RX_10_NIB_0_04_CLK_L,
RX_10_NIB_0_05_CLK_L,
RX_10_NIB_0_06_CLK_L,
RX_10_NIB_0_07_CLK_L,
RX_10_NIB_0_08_CLK_L,
RX_10_NIB_0_09_CLK_L,
RX_10_NIB_0_00_CLK_H,
RX_10_NIB_0_01_CLK_H,
RX_10_NIB_0_02_CLK_H,
RX_10_NIB_0_03_CLK_H,
RX_10_NIB_0_04_CLK_H,
RX_10_NIB_0_05_CLK_H,
RX_10_NIB_0_06_CLK_H,
RX_10_NIB_0_07_CLK_H,
RX_10_NIB_0_08_CLK_H,
RX_10_NIB_0_09_CLK_H,
RX_10_NIB_1_00_CLK_L,
RX_10_NIB_1_01_CLK_L,
RX_10_NIB_1_02_CLK_L,
RX_10_NIB_1_03_CLK_L,
RX_10_NIB_1_04_CLK_L,
RX_10_NIB_1_05_CLK_L,
RX_10_NIB_1_06_CLK_L,
RX_10_NIB_1_07_CLK_L,
RX_10_NIB_1_08_CLK_L,
RX_10_NIB_1_09_CLK_L,
RX_10_NIB_1_00_CLK_H,
RX_10_NIB_1_01_CLK_H,
RX_10_NIB_1_02_CLK_H,
RX_10_NIB_1_03_CLK_H,
RX_10_NIB_1_04_CLK_H,
RX_10_NIB_1_05_CLK_H,
RX_10_NIB_1_06_CLK_H,
RX_10_NIB_1_07_CLK_H,
RX_10_NIB_1_08_CLK_H,
RX_10_NIB_1_09_CLK_H,
RX_10_NIB_1_09_RD_FIFO_CLK_H
);
signal present_state : STATES_TYPE;
signal next_state : STATES_TYPE;
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
-- No Concurrent Signal Assignments
------------------------------------------------------------------------------
-- State Machine SYNC_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
present_state <= IDLE_ClK_L;
else
present_state <= next_state;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- State Machine NEXT_STATE_PROCESS
------------------------------------------------------------------------------
NEXT_STATE_PROCESS : process (
present_state,
Rx_100,
Rx_10,
RMII_rx_EOP,
Rmii_rx_er,
Rmii_rx_crs,
Rmii_rx_dv,
Rmii_rx_data,
Rx_fifo_mt_n--new addition of signal
)
begin
case present_state is
when IDLE_ClK_L =>
if (Rx_100 = '1') then
next_state <= RX_100_RD_FIFO_ClK_L;
elsif (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when IDLE_ClK_H =>
if (Rx_10 = '1') then
next_state <= RX_10_RD_FIFO_CLK_L;
else
next_state <= IDLE_ClK_L;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_RD_FIFO_ClK_L =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_100_NIB_0_CLK_L =>
next_state <= RX_100_NIB_0_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_0_CLK_H =>
next_state <= RX_100_NIB_1_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_100_NIB_1_CLK_L =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1')) then
next_state <= RX_100_NIB_1_CLK_H;
else
next_state <= RX_100_NIB_1_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_100_NIB_1_RD_FIFO_CLK_H =>
next_state <= RX_100_NIB_0_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_RD_FIFO_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= '0';
Rmii2mac_crs <= '0';
Rmii2mac_rx_dv <= '0';
Rmii2mac_rxd <= (others => '0');
when RX_10_NIB_0_00_CLK_L =>
next_state <= RX_10_NIB_0_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_L =>
next_state <= RX_10_NIB_0_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_L =>
next_state <= RX_10_NIB_0_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_L =>
next_state <= RX_10_NIB_0_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_L =>
next_state <= RX_10_NIB_0_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_L =>
next_state <= RX_10_NIB_0_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_L =>
next_state <= RX_10_NIB_0_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_L =>
next_state <= RX_10_NIB_0_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_L =>
next_state <= RX_10_NIB_0_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_L =>
next_state <= RX_10_NIB_0_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_00_CLK_H =>
next_state <= RX_10_NIB_0_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_01_CLK_H =>
next_state <= RX_10_NIB_0_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_02_CLK_H =>
next_state <= RX_10_NIB_0_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_03_CLK_H =>
next_state <= RX_10_NIB_0_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_04_CLK_H =>
next_state <= RX_10_NIB_0_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_05_CLK_H =>
next_state <= RX_10_NIB_0_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_06_CLK_H =>
next_state <= RX_10_NIB_0_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_07_CLK_H =>
next_state <= RX_10_NIB_0_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_08_CLK_H =>
next_state <= RX_10_NIB_0_09_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_0_09_CLK_H =>
next_state <= RX_10_NIB_1_00_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(0);
Rmii2mac_crs <= Rmii_rx_crs(0);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(3 downto 0);
when RX_10_NIB_1_00_CLK_L =>
next_state <= RX_10_NIB_1_01_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_L =>
next_state <= RX_10_NIB_1_02_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_L =>
next_state <= RX_10_NIB_1_03_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_L =>
next_state <= RX_10_NIB_1_04_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_L =>
next_state <= RX_10_NIB_1_05_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_L =>
next_state <= RX_10_NIB_1_06_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_L =>
next_state <= RX_10_NIB_1_07_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_L =>
next_state <= RX_10_NIB_1_08_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_L =>
next_state <= RX_10_NIB_1_09_CLK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_L =>
next_state <= RX_10_NIB_1_00_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '0';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_00_CLK_H =>
next_state <= RX_10_NIB_1_01_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_01_CLK_H =>
next_state <= RX_10_NIB_1_02_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_02_CLK_H =>
next_state <= RX_10_NIB_1_03_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_03_CLK_H =>
next_state <= RX_10_NIB_1_04_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_04_CLK_H =>
next_state <= RX_10_NIB_1_05_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_05_CLK_H =>
next_state <= RX_10_NIB_1_06_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_06_CLK_H =>
next_state <= RX_10_NIB_1_07_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_07_CLK_H =>
next_state <= RX_10_NIB_1_08_CLK_H;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_08_CLK_H =>
if ((RMII_rx_EOP(0) = '1') or (RMII_rx_EOP(1) = '1') or (Rx_fifo_mt_n = '0')) then
next_state <= RX_10_NIB_1_09_CLK_H;
else
next_state <= RX_10_NIB_1_09_RD_FIFO_CLK_H;
end if;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_CLK_H =>
next_state <= IDLE_ClK_L;
Rx_fifo_rd_en <= '0';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
when RX_10_NIB_1_09_RD_FIFO_CLK_H =>
next_state <= RX_10_NIB_0_00_CLK_L;
Rx_fifo_rd_en <= '1';
Rmii2Mac_rx_clk <= '1';
Rmii2mac_rx_er <= Rmii_rx_er(1);
Rmii2mac_crs <= Rmii_rx_crs(1);
Rmii2mac_rx_dv <= '1';
Rmii2mac_rxd <= Rmii_rx_data(7 downto 4);
end case;
end process;
end simulation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/ram16x4.vhd
|
4
|
12011
|
-------------------------------------------------------------------------------
-- ram16x4 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2007, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename : ram16x4.vhd
-- Version : v4.00.a
-- Description: This is a LUT RAM design to provide 4 bits wide and 16 bits
-- deep memory structue. The initial string for rom16x4 is
-- specially designed to ease the initialization of this memory.
-- The initialization value is taken from the "INIT_XX" string.
-- Each string is read in the standard Xilinx format, which is to
-- take the right-most character as the least significant bit.
-- INIT_00 is for address 0 to address 3, INIT_01 is for address
-- 4 to address 7, ..., INIT_03 is for address 12 to address 15.
-- Uses 16 LUTs (16 RAM16x1)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity ram16x4 is
generic(
INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for addr(3 downto 0)
INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for addr(7 downto 4)
INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for addr(11 downto 8)
INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for addr(15 downto 12)
);
port(
Addr : in std_logic_vector(3 downto 0);
D : in std_logic_vector(3 downto 0);
We : in std_logic;
Clk : in std_logic;
Q : out std_logic_vector(3 downto 0));
end entity ram16x4 ;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of ram16x4 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
attribute INIT : string ;
attribute INIT of ram16x1_0 : label is GetInitString4(0, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_1 : label is GetInitString4(1, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_2 : label is GetInitString4(2, INIT_00,INIT_01,
INIT_02, INIT_03);
attribute INIT of ram16x1_3 : label is GetInitString4(3, INIT_00,INIT_01,
INIT_02, INIT_03);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic ( init : bit_vector);
-- synopsys translate_on
-- synthesis translate_on
port (
a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
a3 : in std_logic;
d : in std_logic;
we : in std_logic;
wclk : in std_logic;
o : out std_logic);
end component;
begin
-----------------------------------------------------------------------------
-- RAM 0
-----------------------------------------------------------------------------
ram16x1_0 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(0, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(0), we => We, wclk => Clk, o => Q(0));
-----------------------------------------------------------------------------
-- RAM 1
-----------------------------------------------------------------------------
ram16x1_1 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(1, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(1), we => We, wclk => Clk, o => Q(1));
-----------------------------------------------------------------------------
-- RAM 2
-----------------------------------------------------------------------------
ram16x1_2 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(2, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(2), we => We, wclk => Clk, o => Q(2));
-----------------------------------------------------------------------------
-- RAM 3
-----------------------------------------------------------------------------
ram16x1_3 : ram16x1s
-- synthesis translate_off
-- synopsys translate_off
generic map (init => GetInitVector4(3, INIT_00,INIT_01,
INIT_02, INIT_03))
-- synopsys translate_on
-- synthesis translate_on
port map (a0 => Addr(0), a1 => Addr(1), a2 => Addr(2), a3 => Addr(3),
d => D(3), we => We, wclk => Clk, o => Q(3));
end imp;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/serport/tb/serport_xonrx_tb.vhd
|
1
|
3843
|
-- $Id: serport_xonrx_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_xonrx_tb - sim
-- Description: serial port: xon/xoff logic rx path (SIM only!)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-03 724 1.0 Initial version (copied from serport_xonrx)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib_tb.all;
entity serport_xonrx_tb is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end serport_xonrx_tb;
architecture sim of serport_xonrx_tb is
type regs_type is record
txok : slbit; -- tx channel ok state
escseen : slbit; -- escape seen
rxdata : slv8; -- user rxdata
rxval : slbit; -- user rxval
rxovr : slbit; -- user rxovr
end record regs_type;
constant regs_init : regs_type := (
'1', -- txok (startup default is ok !!)
'0', -- escseen
(others=>'0'), -- rxdata
'0','0' -- rxval,rxovr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if ENAXON = '0' then
n.txok := '1';
end if;
if ENAESC = '0' then
n.escseen := '0';
end if;
n.rxovr := '0'; -- ensure single clock pulse
if UART_RXVAL = '1' then
if ENAXON='1' and UART_RXDATA=c_serport_xon then
n.txok := '1';
elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then
n.txok := '0';
elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then
n.escseen := '1';
else
if r.escseen = '1' then
n.escseen := '0';
end if;
if r.rxval = '0' then
n.rxval := '1';
if r.escseen = '1' then
n.rxdata := not UART_RXDATA;
else
n.rxdata := UART_RXDATA;
end if;
else
n.rxovr := '1';
end if;
end if;
end if;
if r.rxval='1' and RXHOLD='0' then
n.rxval := '0';
end if;
N_REGS <= n;
RXDATA <= r.rxdata;
RXVAL <= r.rxval;
RXOVR <= r.rxovr;
TXOK <= r.txok;
end process proc_next;
end sim;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/nexys2/nexys2lib.vhd
|
1
|
8325
|
-- $Id: nexys2lib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2013 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: nexys2lib
-- Description: Nexys 2 components
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.4 add nexys2_cuff_aif, nexys2_fusp_cuff_aif
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 remove n2_cram_* modules, now in nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port in cram controller/dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock)
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy
-- 2010-05-23 294 1.0.2 add n2_cram_dummy;
-- 2010-05-23 293 1.0.1 use _ADV_N rather _ADV; add generic for memctl
-- 2010-05-21 292 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nexys2lib is
component nexys2_aif is -- NEXYS 2, abstract iface, base
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end component;
component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end component;
component nexys2_cuff_aif is -- NEXYS 2, abstract iface, base+cuff
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component nexys2_fusp_cuff_aif is -- NEXYS 2, abstract iface, +fusp+cuff
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package nexys2lib;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/w11a/nexys4d_bram/sys_conf.vhd
|
1
|
5020
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_br_n4d (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2016.2-2018.3; ghdl 0.33-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.0.4 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.0.3 add sys_conf_ibd_kw11p
-- 2017-03-04 858 1.0.2 enable deuna
-- 2017-01-29 847 1.0.1 add sys_conf_ibd_deuna
-- 2017-01-04 838 1.0 Initial version (derived from _br_n4 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 5;
constant sys_conf_memctl_nblock : positive := 32;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
--constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : natural := 8#003777#; -- 128 kByte (debug)
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/rbus/rbd_rbmon.vhd
|
1
|
21523
|
-- $Id: rbd_rbmon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rbd_rbmon - syn
-- Description: rbus dev: rbus monitor
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
--
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2014.4-2018.3; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-04-14 873 14.7 131013 xc6slx16-2 124 187 - 67 s 5.9
-- 2017-04-08 758 14.7 131013 xc6slx16-2 112 200 - 73 s 5.7
-- 2014-12-22 619 14.7 131013 xc6slx16-2 114 209 - 72 s 5.6
-- 2014-12-21 593 14.7 131013 xc6slx16-2 99 207 - 77 s 7.0
-- 2010-12-27 349 12.1 M53d xc3s1000-4 95 228 - 154 s 10.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 6.0.2 use rbaddr_ constants
-- 2019-03-02 1116 6.0.1 more robust ack,err trace when busy
-- 2017-04-16 879 6.0 revised interface, add suspend and repeat collapse
-- 2015-05-02 672 5.0.1 use natural for AWIDTH to work around a ghdl issue
-- 2014-12-22 619 5.0 reorganized, supports now 16 bit addresses
-- 2014-09-13 593 4.1 change default address -> ffe8
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit (but only 8 bit recorded)
-- 2011-11-19 427 1.0.3 now numeric_std clean
-- 2011-03-27 374 1.0.2 rename ncyc -> nbusy because it counts busy cycles
-- 2010-12-31 352 1.0.1 simplify irb_ack logic
-- 2010-12-27 349 1.0 Initial version
------------------------------------------------------------------------------
--
-- Addr Bits Name r/w/f Function
-- 000 cntl r/w/f Control register
-- 05 rcolw r/w/- repeat collapse writes
-- 04 rcolr r/w/- repeat collapse reads
-- 03 wstop r/w/- stop on wrap
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start and latch all options
-- 110 sus suspend (noop if not started)
-- 111 res resume (noop if not started)
-- 001 stat r/w/- Status register
-- 15:13 bsize r/-/- buffer size (AWIDTH-9)
-- 02 wrap r/-/- line address wrapped (cleared on start)
-- 01 susp r/-/- suspended
-- 00 run r/-/- running (can be suspended)
-- 010 hilim r/w/- upper address limit, inclusive (def: 0xfffb)
-- 011 lolim r/w/- lower address limit, inclusive (def: 0x0000)
-- 100 addr r/w/- Address register
-- *:02 laddr r/w/- line address
-- 01:00 waddr r/w/- word address
-- 101 data r/w/- Data register
--
-- data format:
-- word 3 15 : burst (2nd re/we in a aval sequence)
-- 14 : tout (busy in last re-we cycle)
-- 13 : nak (no ack in last non-busy cycle)
-- 12 : ack (ack seen)
-- 11 : busy (busy seen)
-- 10 : err (err seen)
-- 09 : we (write cycle)
-- 08 : init (init cycle)
-- 07:00 : delay to prev (msb's)
-- word 2 15:10 : delay to prev (lsb's)
-- 09:00 : number of busy cycles
-- word 1 : data
-- word 0 : addr
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.rbdlib.all;
-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
-- to control the instantiation. ghdl checks even for not instantiated
-- entities the validity of generics, that's why natural needed here ....
entity rbd_rbmon is -- rbus dev: rbus monitor
generic (
RB_ADDR : slv16 := rbaddr_rbmon;
AWIDTH : natural := 9);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_SRES_SUM : in rb_sres_type -- rbus: response (sum for monitor)
);
end entity rbd_rbmon;
architecture syn of rbd_rbmon is
constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
constant rbaddr_stat : slv3 := "001"; -- stat address offset
constant rbaddr_hilim : slv3 := "010"; -- hilim address offset
constant rbaddr_lolim : slv3 := "011"; -- lolim address offset
constant rbaddr_addr : slv3 := "100"; -- addr address offset
constant rbaddr_data : slv3 := "101"; -- data address offset
constant cntl_rbf_rcolw : integer := 5;
constant cntl_rbf_rcolr : integer := 4;
constant cntl_rbf_wstop : integer := 3;
subtype cntl_rbf_func is integer range 2 downto 0;
subtype stat_rbf_bsize is integer range 15 downto 13;
constant stat_rbf_wrap : integer := 2;
constant stat_rbf_susp : integer := 1;
constant stat_rbf_run : integer := 0;
subtype addr_rbf_laddr is integer range 2+AWIDTH-1 downto 2;
subtype addr_rbf_waddr is integer range 1 downto 0;
constant dat3_rbf_burst : integer := 15;
constant dat3_rbf_tout : integer := 14;
constant dat3_rbf_nak : integer := 13;
constant dat3_rbf_ack : integer := 12;
constant dat3_rbf_busy : integer := 11;
constant dat3_rbf_err : integer := 10;
constant dat3_rbf_we : integer := 9;
constant dat3_rbf_init : integer := 8;
subtype dat3_rbf_ndlymsb is integer range 7 downto 0;
subtype dat2_rbf_ndlylsb is integer range 15 downto 10;
subtype dat2_rbf_nbusy is integer range 9 downto 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_sus : slv3 := "110"; -- func: suspend
constant func_res : slv3 := "111"; -- func: resume
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
rcolw : slbit; -- rcolw flag (repeat collect writes)
rcolr : slbit; -- rcolr flag (repeat collect reads)
wstop : slbit; -- wstop flag (stop on wrap)
susp : slbit; -- suspended flag
go : slbit; -- go flag
hilim : slv16; -- upper address limit
lolim : slv16; -- lower address limit
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv2; -- word address
addrsame: slbit; -- curr rb addr equal last rb addr
addrwind: slbit; -- curr rb addr in [lolim,hilim] window
aval_1 : slbit; -- last cycle aval
arm1r : slbit; -- 1st level arm for read
arm2r : slbit; -- 2nd level arm for read
arm1w : slbit; -- 1st level arm for write
arm2w : slbit; -- 2nd level arm for write
rcol : slbit; -- repeat collaps
rbtake_1 : slbit; -- rb capture active in last cycle
rbaddr : slv16; -- rbus trace: addr
rbinit : slbit; -- rbus trace: init
rbwe : slbit; -- rbus trace: we
rback : slbit; -- rbus trace: ack seen
rbbusy : slbit; -- rbus trace: busy seen
rberr : slbit; -- rbus trace: err seen
rbnak : slbit; -- rbus trace: nak detected
rbtout : slbit; -- rbus trace: tout detected
rbburst : slbit; -- rbus trace: burst detected
rbdata : slv16; -- rbus trace: data
rbnbusy : slv10; -- rbus number of busy cycles
rbndly : slv14; -- rbus delay to prev. access
end record regs_type;
constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
'0', -- rbsel
'0','0','0', -- rcolw,rcolr,wstop
'0','1', -- susp,go
x"fffb", -- hilim (def: fffb)
x"0000", -- lolim (def: 0000)
'0', -- wrap
laddrzero, -- laddr
"00", -- waddr
'0','0','0', -- addrsame,addrwind,aval_1
'0','0','0','0','0', -- arm1r,arm2r,arm1w,arm2w,rcol
'0', -- rbtake_1
x"ffff", -- rbaddr (startup: ffff)
'0','0','0','0','0', -- rbinit,rbwe,rback,rbbusy,rberr
'0','0','0', -- rbnak,rbtout,rbburst
(others=>'0'), -- rbdata
(others=>'0'), -- rbnbusy
(others=>'0') -- rbndly
);
constant rbnbusylast : slv10 := (others=>'1');
constant rbndlylast : slv14 := (others=>'1');
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_EN : slbit := '0';
signal BRAM_WE : slbit := '0';
signal BRAM0_DI : slv32 := (others=>'0');
signal BRAM1_DI : slv32 := (others=>'0');
signal BRAM0_DO : slv32 := (others=>'0');
signal BRAM1_DO : slv32 := (others=>'0');
signal BRAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported AWIDTH"
severity failure;
BRAM1 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => BRAM1_DI,
DO => BRAM1_DO
);
BRAM0 : ram_1swsr_wfirst_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => 32)
port map (
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => BRAM0_DI,
DO => BRAM0_DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, RB_MREQ, RB_SRES_SUM, BRAM0_DO, BRAM1_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable ibramen : slbit := '0'; -- BRAM enable
variable ibramwe : slbit := '0'; -- BRAN we
variable rbtake : slbit := '0';
variable laddr_inc : slbit := '0';
variable idat0 : slv16 := (others=>'0');
variable idat1 : slv16 := (others=>'0');
variable idat2 : slv16 := (others=>'0');
variable idat3 : slv16 := (others=>'0');
variable iaddrinc : slv(AWIDTH-1 downto 0) := (others=>'0');
variable iaddroff : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
ibramen := '0';
ibramwe := '0';
laddr_inc := '0';
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
n.rbsel := '1';
ibramen := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
case RB_MREQ.din(cntl_rbf_func) is
when func_sto => -- func: stop ------------
n.go := '0';
n.susp := '0';
when func_sta => -- func: start -----------
n.rcolw := RB_MREQ.din(cntl_rbf_rcolw);
n.rcolr := RB_MREQ.din(cntl_rbf_rcolr);
n.wstop := RB_MREQ.din(cntl_rbf_wstop);
n.go := '1';
n.susp := '0';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "00";
when func_sus => -- func: susp ------------
if r.go = '1' then -- noop unless running
n.go := '0';
n.susp := r.go;
end if;
when func_res => -- func: resu ------------
n.go := r.susp;
n.susp := '0';
when others => null; -- <> --------------------
end case;
end if;
when rbaddr_stat => null; -- stat ------------------
when rbaddr_hilim => -- hilim -----------------
if RB_MREQ.we = '1' then
n.hilim := RB_MREQ.din;
end if;
when rbaddr_lolim => -- lolim -----------------
if RB_MREQ.we = '1' then
n.lolim := RB_MREQ.din;
end if;
when rbaddr_addr => -- addr ------------------
if RB_MREQ.we = '1' then
if r.go = '0' then -- if not active OK
n.laddr := RB_MREQ.din(addr_rbf_laddr);
n.waddr := RB_MREQ.din(addr_rbf_waddr);
else
irb_err := '1'; -- otherwise error
end if;
end if;
when rbaddr_data => -- data ------------------
-- write to data is an error
if RB_MREQ.we='1' then
irb_err := '1';
end if;
-- read to data always allowed, addr only incremented when not active
if RB_MREQ.re = '1' and r.go = '0' then
n.waddr := slv(unsigned(r.waddr) + 1);
if r.waddr = "11" then
laddr_inc := '1';
end if;
end if;
when others => -- <> --------------------
irb_err := '1';
end case;
end if;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl => -- cntl ------------------
irb_dout(cntl_rbf_rcolw) := r.rcolw;
irb_dout(cntl_rbf_rcolr) := r.rcolr;
irb_dout(cntl_rbf_wstop) := r.wstop;
when rbaddr_stat => -- stat ------------------
irb_dout(stat_rbf_bsize) := slv(to_unsigned(AWIDTH-9,3));
irb_dout(stat_rbf_wrap) := r.wrap;
irb_dout(stat_rbf_susp) := r.susp; -- started and suspended
irb_dout(stat_rbf_run) := r.go or r.susp; -- started
when rbaddr_hilim => -- hilim -----------------
irb_dout := r.hilim;
when rbaddr_lolim => -- lolim -----------------
irb_dout := r.lolim;
when rbaddr_addr => -- addr ------------------
irb_dout(addr_rbf_laddr) := r.laddr;
irb_dout(addr_rbf_waddr) := r.waddr;
when rbaddr_data => -- data ------------------
case r.waddr is
when "11" => irb_dout := BRAM1_DO(31 downto 16);
when "10" => irb_dout := BRAM1_DO(15 downto 0);
when "01" => irb_dout := BRAM0_DO(31 downto 16);
when "00" => irb_dout := BRAM0_DO(15 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
-- rbus monitor
-- a rbus transaction are captured if the address is in alim window
-- and the access is not refering to rbd_rbmon itself
-- Note: rbus init cycles come with aval=0 but addr is valid and checked !
-- rbus address monitor
if (RB_MREQ.aval='1' and r.aval_1='0') or RB_MREQ.init='1' then
n.rbaddr := RB_MREQ.addr;
n.addrsame := '0';
if RB_MREQ.addr = r.rbaddr then
n.addrsame := '1';
end if;
n.addrwind := '0';
if unsigned(RB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
unsigned(RB_MREQ.addr)<=unsigned(r.hilim) then
n.addrwind := '1';
end if;
end if;
n.aval_1 := RB_MREQ.aval;
-- rbus data monitor
if (RB_MREQ.aval='1' and irbena='1') or RB_MREQ.init='1' then
if RB_MREQ.init='1' or RB_MREQ.we='1' then -- for write/init of din
n.rbdata := RB_MREQ.din;
else -- for read of dout
n.rbdata := RB_SRES_SUM.dout;
end if;
end if;
-- track state and decide on storage
rbtake := '0';
if RB_MREQ.aval='1' and irbena='1' then -- aval and (re or we)
if r.addrwind='1' and r.rbsel='0' then -- and in window and not self
rbtake := '1';
end if;
end if;
if RB_MREQ.init = '1' then -- also take init's
rbtake := '1';
end if;
if rbtake = '1' then -- if capture active
n.rbinit := RB_MREQ.init; -- keep track of some state
n.rbwe := RB_MREQ.we;
if r.rbtake_1 = '0' then -- if initial cycle of a transaction
n.rback := RB_SRES_SUM.ack;
n.rbbusy := RB_SRES_SUM.busy;
n.rberr := RB_SRES_SUM.err;
n.rbnbusy := (others=>'0');
else -- if non-initial cycles
n.rback := r.rback or RB_SRES_SUM.ack; -- keep track of ack
n.rberr := r.rberr or RB_SRES_SUM.err; -- keep track of err
if r.rbnbusy /= rbnbusylast then -- and count
n.rbnbusy := slv(unsigned(r.rbnbusy) + 1);
end if;
end if;
n.rbnak := not RB_SRES_SUM.ack;
n.rbtout := RB_SRES_SUM.busy;
if RB_SRES_SUM.busy = '0' then -- if last cycle of a transaction
n.addrsame := '1'; -- in case of burst
n.arm1r := r.rcolr and RB_MREQ.re;
n.arm1w := r.rcolw and RB_MREQ.we;
n.arm2r := r.arm1r and r.addrsame and RB_MREQ.re;
n.arm2w := r.arm1w and r.addrsame and RB_MREQ.we;
n.rcol := ((r.arm2r and RB_MREQ.re) or
(r.arm2w and RB_MREQ.we)) and r.addrsame;
end if;
else -- if capture not active
if r.go='1' and r.rbtake_1='1' then -- active and transaction just ended
ibramen := '1';
ibramwe := '1';
laddr_inc := '1';
n.rbburst := '1'; -- assume burst
end if;
if r.rbtake_1 = '1' then -- rbus transaction just ended
n.rbndly := (others=>'0'); -- clear delay counter
else -- just idle
if r.rbndly /= rbndlylast then -- count cycles
n.rbndly := slv(unsigned(r.rbndly) + 1);
end if;
end if;
end if;
if RB_MREQ.aval = '0' then -- if aval gone
n.rbburst := '0'; -- clear burst flag
end if;
iaddrinc := (others=>'0');
iaddroff := (others=>'0');
iaddrinc(0) := not (r.rcol and r.go);
iaddroff(0) := (r.rcol and r.go);
if laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + unsigned(iaddrinc));
if r.go='1' and r.laddr=laddrlast then
n.wrap := '1';
if r.wstop = '1' then
n.go := '0';
end if;
end if;
end if;
idat3 := (others=>'0');
idat3(dat3_rbf_burst) := r.rbburst;
idat3(dat3_rbf_tout) := r.rbtout;
idat3(dat3_rbf_nak) := r.rbnak;
idat3(dat3_rbf_ack) := r.rback;
idat3(dat3_rbf_busy) := r.rbbusy;
idat3(dat3_rbf_err) := r.rberr;
idat3(dat3_rbf_we) := r.rbwe;
idat3(dat3_rbf_init) := r.rbinit;
idat3(dat3_rbf_ndlymsb):= r.rbndly(13 downto 6);
idat2(dat2_rbf_ndlylsb):= r.rbndly( 5 downto 0);
idat2(dat2_rbf_nbusy) := r.rbnbusy;
idat1 := r.rbdata;
idat0 := r.rbaddr;
n.rbtake_1 := rbtake;
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM_ADDR <= slv(unsigned(R_REGS.laddr) - unsigned(iaddroff));
BRAM1_DI <= idat3 & idat2;
BRAM0_DI <= idat1 & idat0;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
end process proc_next;
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/memlib/tb/tb_fifo_2c_dram.vhd
|
1
|
9946
|
-- $Id: tb_fifo_2c_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_fifo_2c_dram - sim
-- Description: Test bench for fifo_2c_dram
--
-- Dependencies: simlib/simclkv
-- simlib/simclkvcnt
-- tbd_fifo_2c_dram [UUT]
--
-- To test: fifo_2c_dram
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.3, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-11-07 421 1.0.5 now numeric_std clean
-- 2010-06-03 299 1.0.4 use sv_ prefix for shared variables
-- 2010-04-17 277 1.0.3 use direct instantiation of tbd_
-- 2009-11-22 252 1.0.2 CLK*_CYCLE now 31 bits
-- 2007-12-28 107 1.0.1 add reset and check handling
-- 2007-12-28 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_fifo_2c_dram is
end tb_fifo_2c_dram;
architecture sim of tb_fifo_2c_dram is
signal CLKW : slbit := '0';
signal CLKR : slbit := '0';
signal RESETW : slbit := '0';
signal RESETR : slbit := '0';
signal DI : slv16 := (others=>'0');
signal ENA : slbit := '0';
signal BUSY : slbit := '0';
signal DO : slv16 := (others=>'0');
signal VAL : slbit := '0';
signal SIZEW : slv4 := (others=>'0');
signal SIZER : slv4 := (others=>'0');
signal N_HOLD : slbit := '0';
signal R_HOLD : slbit := '0';
signal CLKW_PERIOD : Delay_length := 20 ns;
signal CLKR_PERIOD : Delay_length := 20 ns;
signal CLK_HOLD : slbit := '1';
signal CLK_STOP : slbit := '0';
signal CLKW_CYCLE : integer := 0;
signal CLKR_CYCLE : integer := 0;
signal CLKR_C2OUT : Delay_length := 10 ns;
shared variable sv_nrstr : integer := 0;
shared variable sv_ndatar : integer := 0; -- data counter (fifo data output)
begin
CLKWGEN : simclkv
port map (
CLK => CLKW,
CLK_PERIOD => CLKW_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKWCNT : simclkcnt port map (CLK => CLKW, CLK_CYCLE => CLKW_CYCLE);
CLKRGEN : simclkv
port map (
CLK => CLKR,
CLK_PERIOD => CLKR_PERIOD,
CLK_HOLD => CLK_HOLD,
CLK_STOP => CLK_STOP
);
CLKRCNT : simclkcnt port map (CLK => CLKR, CLK_CYCLE => CLKR_CYCLE);
UUT : entity work.tbd_fifo_2c_dram
port map (
CLKW => CLKW,
CLKR => CLKR,
RESETW => RESETW,
RESETR => RESETR,
DI => DI,
ENA => ENA,
BUSY => BUSY,
DO => DO,
VAL => VAL,
HOLD => R_HOLD,
SIZEW => SIZEW,
SIZER => SIZER
);
proc_stim: process
file fstim : text open read_mode is "tb_fifo_2c_dram_stim";
variable iline : line;
variable oline : line;
variable dname : string(1 to 6) := (others=>' ');
variable ok : boolean;
variable dtime : Delay_length := 0 ns;
variable nwait : integer := 0; --
variable nword : integer := 0; --
variable nbusy : integer := 0; -- number of busy before accept
variable idi : slv16 := (others=>'0');
variable ndataw : integer := 0; -- data counter (fifo data input)
variable iclkw_period : Delay_length := 20 ns;
variable iclkw_setup : Delay_length := 5 ns;
variable iclkr_period : Delay_length := 20 ns;
variable iclkr_c2out : Delay_length := 10 ns;
begin
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".chold" => -- .chold time
write(oline, string'(".chold"));
writeline(output, oline);
read_ea(iline, dtime);
CLK_HOLD <= '1';
wait for dtime;
CLK_HOLD <= '0';
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
when ".cdef " => -- .cdef wper wset rper rout
write(oline, string'(".cdef "));
writeline(output, oline);
read_ea(iline, iclkw_period);
read_ea(iline, iclkw_setup);
read_ea(iline, iclkr_period);
read_ea(iline, iclkr_c2out);
CLKW_PERIOD <= iclkw_period;
CLKR_PERIOD <= iclkr_period;
CLKR_C2OUT <= iclkr_c2out;
if CLK_HOLD = '0' then
wait until rising_edge(CLKW);
wait for iclkw_period-iclkw_setup;
end if;
when ".ndata" => -- .ndata num
read_ea(iline, ndataw);
sv_ndatar := ndataw;
when ".hold " => -- .hold time
read_ea(iline, dtime);
if dtime > 0 ns then
N_HOLD <= '1', '0' after dtime;
else -- allow hold abort with 0ns
N_HOLD <= '0';
end if;
when ".wait " => -- .wait ncyc
read_ea(iline, nwait);
wait for nwait*iclkw_period;
when "resetw" => -- resetw ncyc
read_ea(iline, nwait);
RESETW <= '1';
wait for nwait*iclkw_period;
RESETW <= '0';
when "resetr" => -- resetr ncyc
read_ea(iline, nwait);
sv_nrstr := nwait;
when "send " => -- send nw nd
read_ea(iline, nwait);
read_ea(iline, nword);
for i in 1 to nword loop
wait for nwait*iclkw_period;
idi := slv(to_unsigned(ndataw, 16));
ndataw := ndataw + 1;
DI <= idi;
ENA <= '1';
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for iclkw_period;
end loop;
writetimestamp(oline, CLKW_CYCLE, ": stim ");
write(oline, idi, right, 18);
write(oline, SIZEW, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(idi)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZEW)), right, 2);
write(oline, string'(")"));
if nbusy > 0 then
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
end if;
writeline(output, oline);
wait for iclkw_period;
ENA <= '0';
end loop; -- i
when others => -- bad directive
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
if N_HOLD = '1' then
wait until N_HOLD='0';
end if;
wait for 20*(iclkw_period+iclkr_period);
CLK_STOP <= '1';
writetimestamp(oline, CLKW_CYCLE, ": DONE-w ");
writeline(output, oline);
writetimestamp(oline, CLKR_CYCLE, ": DONE-r ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable nhold : integer := 0; -- number of hold cycles before accept
variable isizer_last : slv4 := (others=>'0');
variable ido : slv16 := (others=>'0');
begin
loop
wait until rising_edge(CLKR);
wait for CLKR_C2OUT;
if VAL = '1' then
if R_HOLD = '1' then
nhold := nhold + 1;
else
ido := slv(to_unsigned(sv_ndatar, 16));
sv_ndatar := sv_ndatar + 1;
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, DO, right, 18);
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(DO)), right, 5);
write(oline, string'(","));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
if nhold > 0 then
write(oline, string'(" nhold="));
write(oline, nhold, right, 2);
end if;
if DO = ido then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
write(oline, ido, right, 18);
end if;
writeline(output, oline);
nhold := 0;
end if;
else
if SIZER /= isizer_last then
writetimestamp(oline, CLKR_CYCLE, ": moni ");
write(oline, string'(" "));
write(oline, SIZER, right, 7);
write(oline, string'(" ("));
write(oline, to_integer(unsigned(SIZER)), right, 2);
write(oline, string'(")"));
writeline(output, oline);
end if;
end if;
isizer_last := SIZER;
end loop;
end process proc_moni;
proc_clkr: process (CLKR)
begin
if rising_edge(CLKR) then
R_HOLD <= N_HOLD;
if sv_nrstr > 0 then
RESETR <= '1';
sv_nrstr := sv_nrstr - 1;
else
RESETR <= '0';
end if;
end if;
end process proc_clkr;
end sim;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/nexys4/tb/nexys4_dummy.vhd
|
1
|
2266
|
-- $Id: nexys4_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys4_dummy - syn
-- Description: nexys4 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys4
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.3 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from nexys3_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity nexys4_dummy is -- NEXYS 4 dummy (base; loopback)
-- implements nexys4_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end nexys4_dummy;
architecture syn of nexys4_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/s3board/s3boardlib.vhd
|
1
|
5869
|
-- $Id: s3boardlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: s3boardlib
-- Description: S3BOARD components
--
-- Dependencies: -
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-09 391 1.3.5 move s3_rs232_iob_int_ext to bpgenlib
-- 2011-07-08 390 1.3.4 move s3_(dispdrv|humanio*) to bpgenlib
-- 2011-07-03 387 1.3.3 move s3_rs232_iob_(int|ext) to bpgenlib
-- 2010-12-30 351 1.3.2 use rblib; rename human s3_humanio_rri -> _rbus
-- 2010-11-06 336 1.3.1 rename input pin CLK -> I_CLK50
-- 2010-06-03 300 1.3 add s3_humanio_rri (now needs rrilib)
-- 2010-05-21 292 1.2.2 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.2.1 rename memctl_s3sram -> s3_sram_memctl; _usp->_fusp
-- 2010-05-01 286 1.2 added s3board_usp_aif (base+pm1_rs232)
-- 2010-04-17 278 1.1.6 rename, prefix dispdrv,sram_summy with s3_;
-- add s3_rs232_iob_(int|ext|int_ext)
-- 2010-04-11 276 1.1.5 add DEBOUNCE for s3_humanio
-- 2010-04-10 275 1.1.4 add s3_humanio
-- 2008-02-17 117 1.1.3 memctl_s3sram: use req,we interface
-- 2008-01-20 113 1.1.2 rename memdrv -> memctl_s3sram
-- 2007-12-16 101 1.1.1 use _N for active low
-- 2007-12-09 100 1.1 add sram memory signals; sram_dummy; memdrv
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package s3boardlib is
component s3board_aif is -- S3BOARD, abstract iface, base
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end component;
component s3board_fusp_aif is -- S3BOARD, abstract iface, base+fusp
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end component;
component s3_sram_dummy is -- SRAM protection dummy
port (
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end component;
component s3_sram_memctl is -- SRAM controller
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv18; -- address
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end component;
end package s3boardlib;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/nexys3/tb/nexys3_fusp_cuff_dummy.vhd
|
1
|
3933
|
-- $Id: nexys3_fusp_cuff_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: nexys3_dummy - syn
-- Description: nexys3 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys3
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version (derived nexys3_fusp_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.nxcramlib.all;
entity nexys3_fusp_cuff_dummy is -- NEXYS 3 dummy (+fusp+cuff; loopback)
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end nexys3_fusp_cuff_dummy;
architecture syn of nexys3_fusp_cuff_dummy is
begin
O_TXD <= I_RXD; -- loop back
O_FUSP_TXD <= I_FUSP_RXD;
O_FUSP_RTS_N <= I_FUSP_CTS_N;
O_FX2_SLRD_N <= '1'; -- keep fx2 iface quiet
O_FX2_SLWR_N <= '1';
O_FX2_SLOE_N <= '1';
O_FX2_PKTEND_N <= '1';
CRAM : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/comlib/comlib.vhd
|
1
|
13266
|
-- $Id: comlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: comlib
-- Description: communication components
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-20 749 1.6.2 crc*_update*: leave return type unconstraint
-- 2016-03-13 744 1.6.1 crc16_update_tbl: work around XSim 2015.4 issue
-- 2014-09-27 595 1.6 add crc16 (using CRC-CCITT polynomial)
-- 2014-09-14 593 1.5 new iface for cdata2byte and byte2cdata
-- 2011-09-17 410 1.4 now numeric_std clean; use for crc8 'A6' polynomial
-- of Koopman et al.; crc8_update(_tbl) now function
-- 2011-07-30 400 1.3 added byte2word, word2byte
-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.2 added procedure crc8_update_tbl
-- 2007-06-29 61 1.1.1 rename for crc8 SALT->INIT
-- 2007-06-17 58 1.1 add crc8
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package comlib is
component byte2word is -- 2 byte -> 1 word stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data (byte)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv16; -- output data (word)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
component word2byte is -- 1 word -> 2 byte stream converter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv16; -- input data (word)
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv8; -- output data (byte)
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
ODD : out slbit -- odd byte pending
);
end component;
constant c_cdata_escape : slv8 := "11001010"; -- char escape
constant c_cdata_fill : slv8 := "11010101"; -- char fill
constant c_cdata_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11
constant c_cdata_xoff : slv8 := "00010011"; -- char xoff: ^S = hex 13
constant c_cdata_ec_xon : slv3 := "100"; -- escape code: xon
constant c_cdata_ec_xoff : slv3 := "101"; -- escape code: xoff
constant c_cdata_ec_fill : slv3 := "110"; -- escape code: fill
constant c_cdata_ec_esc : slv3 := "111"; -- escape code: escape
constant c_cdata_ed_pref : slv2 := "01"; -- edata: prefix
subtype c_cdata_edf_pref is integer range 7 downto 6; -- edata pref field
subtype c_cdata_edf_eci is integer range 5 downto 3; -- edata inv field
subtype c_cdata_edf_ec is integer range 2 downto 0; -- edata code field
component cdata2byte is -- 9bit comma,data -> byte stream
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ESCXON : in slbit; -- enable xon/xoff escaping
ESCFILL : in slbit; -- enable fill escaping
DI : in slv9; -- input data; bit 8 = comma flag
ENA : in slbit; -- input data enable
BUSY : out slbit; -- input data busy
DO : out slv8; -- output data
VAL : out slbit; -- output data valid
HOLD : in slbit -- output data hold
);
end component;
component byte2cdata is -- byte stream -> 9bit comma,data
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv8; -- input data
ENA : in slbit; -- input data enable
ERR : in slbit; -- input data error
BUSY : out slbit; -- input data busy
DO : out slv9; -- output data; bit 8 = comma flag
VAL : out slbit; -- output data valid
HOLD : in slbit -- output data hold
);
end component;
component crc8 is -- crc-8 generator, checker
generic (
INIT: slv8 := "00000000"); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv8 -- crc code
);
end component;
component crc16 is -- crc-16 generator, checker
generic (
INIT: slv16 := (others=>'0')); -- initial state of crc register
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENA : in slbit; -- update enable
DI : in slv8; -- input data
CRC : out slv16 -- crc code
);
end component;
-- Note: leave return type unconstraint ! A direction constraint return
-- type works fine in ghdl and ISim, but XSim will abort with an
-- run time error (there is indeed a mismatch, some simulators
-- tolerate this, some not, so never constrain a return type...).
function crc8_update (crc : in slv8; data : in slv8) return slv;
function crc8_update_tbl (crc : in slv8; data : in slv8) return slv;
function crc16_update (crc : in slv16; data : in slv8) return slv;
function crc16_update_tbl (crc : in slv16; data : in slv8) return slv;
end package comlib;
-- ----------------------------------------------------------------------------
package body comlib is
-- crc8_update and crc8_update_tbl implement the 'A6' polynomial of
-- Koopman and Chakravarty
-- x^8 + x^6 + x^3 + x^2 + 1 (0xa6)
-- see
-- http://dx.doi.org/10.1109%2FDSN.2004.1311885
-- http://www.ece.cmu.edu/~koopman/roses/dsn04/koopman04_crc_poly_embedded.pdf
--
function crc8_update (crc: in slv8; data: in slv8) return slv is
variable t : slv8 := (others=>'0');
variable n : slv8 := (others=>'0');
begin
t := data xor crc;
n(0) := t(5) xor t(4) xor t(2) xor t(0);
n(1) := t(6) xor t(5) xor t(3) xor t(1);
n(2) := t(7) xor t(6) xor t(5) xor t(0);
n(3) := t(7) xor t(6) xor t(5) xor t(4) xor t(2) xor t(1) xor t(0);
n(4) := t(7) xor t(6) xor t(5) xor t(3) xor t(2) xor t(1);
n(5) := t(7) xor t(6) xor t(4) xor t(3) xor t(2);
n(6) := t(7) xor t(3) xor t(2) xor t(0);
n(7) := t(4) xor t(3) xor t(1);
return n;
end function crc8_update;
function crc8_update_tbl (crc: in slv8; data: in slv8) return slv is
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 77, 154, 215, 121, 52, 227, 174, -- 00-07
242, 191, 104, 37, 139, 198, 17, 92, -- 00-0f
169, 228, 51, 126, 208, 157, 74, 7, -- 10-17
91, 22, 193, 140, 34, 111, 184, 245, -- 10-1f
31, 82, 133, 200, 102, 43, 252, 177, -- 20-27
237, 160, 119, 58, 148, 217, 14, 67, -- 20-2f
182, 251, 44, 97, 207, 130, 85, 24, -- 30-37
68, 9, 222, 147, 61, 112, 167, 234, -- 30-3f
62, 115, 164, 233, 71, 10, 221, 144, -- 40-47
204, 129, 86, 27, 181, 248, 47, 98, -- 40-4f
151, 218, 13, 64, 238, 163, 116, 57, -- 50-57
101, 40, 255, 178, 28, 81, 134, 203, -- 50-5f
33, 108, 187, 246, 88, 21, 194, 143, -- 60-67
211, 158, 73, 4, 170, 231, 48, 125, -- 60-6f
136, 197, 18, 95, 241, 188, 107, 38, -- 70-70
122, 55, 224, 173, 3, 78, 153, 212, -- 70-7f
124, 49, 230, 171, 5, 72, 159, 210, -- 80-87
142, 195, 20, 89, 247, 186, 109, 32, -- 80-8f
213, 152, 79, 2, 172, 225, 54, 123, -- 90-97
39, 106, 189, 240, 94, 19, 196, 137, -- 90-9f
99, 46, 249, 180, 26, 87, 128, 205, -- a0-a7
145, 220, 11, 70, 232, 165, 114, 63, -- a0-af
202, 135, 80, 29, 179, 254, 41, 100, -- b0-b7
56, 117, 162, 239, 65, 12, 219, 150, -- b0-bf
66, 15, 216, 149, 59, 118, 161, 236, -- c0-c7
176, 253, 42, 103, 201, 132, 83, 30, -- c0-cf
235, 166, 113, 60, 146, 223, 8, 69, -- d0-d7
25, 84, 131, 206, 96, 45, 250, 183, -- d0-df
93, 16, 199, 138, 36, 105, 190, 243, -- e0-e7
175, 226, 53, 120, 214, 155, 76, 1, -- e0-ef
244, 185, 110, 35, 141, 192, 23, 90, -- f0-f7
6, 75, 156, 209, 127, 50, 229, 168 -- f0-ff
);
begin
return slv(to_unsigned(crc8_tbl(to_integer(unsigned(data xor crc))), 8));
end function crc8_update_tbl;
-- crc16_update and crc16_update_tbl implement the CCITT polynomial
-- x^16 + x^12 + x^5 + 1 (0x1021)
--
function crc16_update (crc: in slv16; data: in slv8) return slv is
variable n : slv16 := (others=>'0');
variable t : slv8 := (others=>'0');
begin
t := data xor crc(15 downto 8);
n(0) := t(4) xor t(0);
n(1) := t(5) xor t(1);
n(2) := t(6) xor t(2);
n(3) := t(7) xor t(3);
n(4) := t(4);
n(5) := t(5) xor t(4) xor t(0);
n(6) := t(6) xor t(5) xor t(1);
n(7) := t(7) xor t(6) xor t(2);
n(8) := t(7) xor t(3) xor crc(0);
n(9) := t(4) xor crc(1);
n(10) := t(5) xor crc(2);
n(11) := t(6) xor crc(3);
n(12) := t(7) xor t(4) xor t(0) xor crc(4);
n(13) := t(5) xor t(1) xor crc(5);
n(14) := t(6) xor t(2) xor crc(6);
n(15) := t(7) xor t(3) xor crc(7);
return n;
end function crc16_update;
function crc16_update_tbl (crc: in slv16; data: in slv8) return slv is
type crc16_tbl_type is array (0 to 255) of integer;
variable crc16_tbl : crc16_tbl_type :=
( 0, 4129, 8258, 12387, 16516, 20645, 24774, 28903,
33032, 37161, 41290, 45419, 49548, 53677, 57806, 61935,
4657, 528, 12915, 8786, 21173, 17044, 29431, 25302,
37689, 33560, 45947, 41818, 54205, 50076, 62463, 58334,
9314, 13379, 1056, 5121, 25830, 29895, 17572, 21637,
42346, 46411, 34088, 38153, 58862, 62927, 50604, 54669,
13907, 9842, 5649, 1584, 30423, 26358, 22165, 18100,
46939, 42874, 38681, 34616, 63455, 59390, 55197, 51132,
18628, 22757, 26758, 30887, 2112, 6241, 10242, 14371,
51660, 55789, 59790, 63919, 35144, 39273, 43274, 47403,
23285, 19156, 31415, 27286, 6769, 2640, 14899, 10770,
56317, 52188, 64447, 60318, 39801, 35672, 47931, 43802,
27814, 31879, 19684, 23749, 11298, 15363, 3168, 7233,
60846, 64911, 52716, 56781, 44330, 48395, 36200, 40265,
32407, 28342, 24277, 20212, 15891, 11826, 7761, 3696,
65439, 61374, 57309, 53244, 48923, 44858, 40793, 36728,
37256, 33193, 45514, 41451, 53516, 49453, 61774, 57711,
4224, 161, 12482, 8419, 20484, 16421, 28742, 24679,
33721, 37784, 41979, 46042, 49981, 54044, 58239, 62302,
689, 4752, 8947, 13010, 16949, 21012, 25207, 29270,
46570, 42443, 38312, 34185, 62830, 58703, 54572, 50445,
13538, 9411, 5280, 1153, 29798, 25671, 21540, 17413,
42971, 47098, 34713, 38840, 59231, 63358, 50973, 55100,
9939, 14066, 1681, 5808, 26199, 30326, 17941, 22068,
55628, 51565, 63758, 59695, 39368, 35305, 47498, 43435,
22596, 18533, 30726, 26663, 6336, 2273, 14466, 10403,
52093, 56156, 60223, 64286, 35833, 39896, 43963, 48026,
19061, 23124, 27191, 31254, 2801, 6864, 10931, 14994,
64814, 60687, 56684, 52557, 48554, 44427, 40424, 36297,
31782, 27655, 23652, 19525, 15522, 11395, 7392, 3265,
61215, 65342, 53085, 57212, 44955, 49082, 36825, 40952,
28183, 32310, 20053, 24180, 11923, 16050, 3793, 7920
);
variable ch : slv16 := (others=>'0');
variable cu : slv16 := (others=>'0');
variable t : slv8 := (others=>'0');
variable td : integer := 0;
begin
-- (crc<<8) ^ crc16_tbl[((crc>>8) ^ data) & 0x00ff]
ch := crc(7 downto 0) & "00000000";
t := data xor crc(15 downto 8);
td := crc16_tbl(to_integer(unsigned(t)));
return ch xor slv(to_unsigned(td, 16));
end function crc16_update_tbl;
end package body comlib;
|
gpl-3.0
|
abcsds/Micros
|
RS232Read_16/regserpar.vhd
|
4
|
736
|
library IEEE;
use IEEE.std_logic_1164.all;
entity RegSerPar is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
LDx : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end RegSerPar;
architecture simple of RegSerPar is
signal Qp, Qn: std_logic_vector(7 downto 0);
begin
COMB: process(Rx,LDx,Qp)
begin
if(LDx='0')then
Qn<= Qp;
else
Qn(7)<= Rx;
for i in 6 downto 0 loop
Qn(i)<= Qp(i+1);
end loop;
end if;
Q<= Qp;
end process COMB;
SEC: process(RST,CLK,Qn)
begin
if(RST='1')then
Qp<= (others=>'0');
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process SEC;
end simple;
|
gpl-3.0
|
wfjm/w11
|
rtl/w11a/pdp11_ubmap.vhd
|
1
|
4637
|
-- $Id: pdp11_ubmap.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ubmap - syn
-- Description: pdp11: 11/70 unibus mapper
--
-- Dependencies: memlib/ram_1swar_gen
-- ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 use ib_sel
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.1 use iblib
-- 2008-01-27 115 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_ubmap is -- 11/70 unibus mapper
port (
CLK : in slbit; -- clock
MREQ : in slbit; -- request mapping
ADDR_UB : in slv18_1; -- UNIBUS address (in)
ADDR_PM : out slv22_1; -- physical memory address (out)
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_ubmap;
architecture syn of pdp11_ubmap is
constant ibaddr_ubmap : slv16 := slv(to_unsigned(8#170200#,16));
signal IBSEL_UBMAP : slbit := '0';
signal MAP_2_WE : slbit := '0';
signal MAP_1_WE : slbit := '0';
signal MAP_0_WE : slbit := '0';
signal MAP_ADDR : slv5 := (others => '0'); -- map regs address
signal MAP_DOUT : slv22_1 := (others => '0'); -- map regs output
begin
MAP_2 : ram_1swar_gen -- bit 21:16 of map regs
generic map (
AWIDTH => 5,
DWIDTH => 6)
port map (
CLK => CLK,
WE => MAP_2_WE,
ADDR => MAP_ADDR,
DI => IB_MREQ.din(5 downto 0),
DO => MAP_DOUT(21 downto 16));
MAP_1 : ram_1swar_gen -- bit 15:08 of map regs
generic map (
AWIDTH => 5,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MAP_1_WE,
ADDR => MAP_ADDR,
DI => IB_MREQ.din(15 downto 8),
DO => MAP_DOUT(15 downto 8));
MAP_0 : ram_1swar_gen -- bit 07:01 of map regs
generic map (
AWIDTH => 5,
DWIDTH => 7)
port map (
CLK => CLK,
WE => MAP_0_WE,
ADDR => MAP_ADDR,
DI => IB_MREQ.din(7 downto 1),
DO => MAP_DOUT(7 downto 1));
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_ubmap,
SAWIDTH => 6) -- 2^6 = 64 = 2*32 words
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_UBMAP
);
proc_comb: process (MREQ, ADDR_UB, IBSEL_UBMAP, IB_MREQ, MAP_DOUT)
variable ibusy : slbit := '0';
variable idout : slv16 := (others=>'0');
variable iwe2 : slbit := '0';
variable iwe1 : slbit := '0';
variable iwe0 : slbit := '0';
variable iaddr : slv5 := (others=>'0');
begin
ibusy := '0';
idout := (others=>'0');
iwe2 := '0';
iwe1 := '0';
iwe0 := '0';
iaddr := (others=>'0');
if IBSEL_UBMAP = '1' then
if IB_MREQ.addr(1) = '1' then
idout(5 downto 0) := MAP_DOUT(21 downto 16);
else
idout(15 downto 1) := MAP_DOUT(15 downto 1);
end if;
if MREQ = '1' then -- if map request, stall ib cycle
ibusy := '1';
end if;
end if;
if IBSEL_UBMAP='1' and IB_MREQ.we='1' then
if IB_MREQ.addr(1)='1' then
if IB_MREQ.be0 = '1' then
iwe2 := '1';
end if;
else
if IB_MREQ.be1 = '1' then
iwe1 := '1';
end if;
if IB_MREQ.be0 = '1' then
iwe0 := '1';
end if;
end if;
end if;
if MREQ = '1' then
iaddr := ADDR_UB(17 downto 13);
else
iaddr := IB_MREQ.addr(6 downto 2);
end if;
MAP_ADDR <= iaddr;
MAP_2_WE <= iwe2;
MAP_1_WE <= iwe1;
MAP_0_WE <= iwe0;
ADDR_PM <= slv(unsigned(MAP_DOUT) +
unsigned("000000000"&ADDR_UB(12 downto 1)));
IB_SRES.ack <= IBSEL_UBMAP and (IB_MREQ.re or IB_MREQ.we);
IB_SRES.busy <= ibusy;
IB_SRES.dout <= idout;
end process proc_comb;
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_rlink/nexys4d/sys_conf.vhd
|
1
|
2423
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n4d (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- single clock design, clkser = clksys
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide;
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply;
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide;
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype;
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure further units -------------------------------------------------
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/memlib/memlib.vhd
|
1
|
11652
|
-- $Id: memlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: memlib
-- Description: Basic memory components: single/dual port synchronous and
-- asynchronus rams; Fifo's.
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-03 1109 1.1.1 add fifo_simple_dram
-- 2016-03-25 751 1.1 add fifo_2c_dram2
-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0.2 change generic default for BRAM models
-- 2007-12-27 106 1.0.1 add fifo_2c_dram
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package memlib is
component ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end component;
component ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable (port A)
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
component ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
generic (
AWIDTH : positive := 10; -- address port width
DWIDTH : positive := 16); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end component;
component ram_1swsr_rfirst_gen is -- RAM, 1 sync r/w ports, read first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end component;
component ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
component ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
component ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w port
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
component ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
component fifo_simple_dram is -- fifo, CE/WE interface, dram based
generic (
AWIDTH : positive := 6; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE : in slbit; -- clock enable
WE : in slbit; -- write enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
EMPTY : out slbit; -- fifo empty status
FULL : out slbit; -- fifo full status
SIZE : out slv(AWIDTH-1 downto 0) -- number of used slots
);
end component;
component fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
WE : in slbit; -- write enable
RE : in slbit; -- read enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
EMPTY : out slbit; -- empty flag
FULL : out slbit -- full flag
);
end component;
component fifo_1c_dram is -- fifo, 1 clock, dram based
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZE : out slv(AWIDTH downto 0) -- number of used slots
);
end component;
component fifo_1c_bubble is -- fifo, 1 clock, bubble regs
generic (
NSTAGE : positive := 4; -- number of stages
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
component fifo_2c_dram is -- fifo, 2 clock, dram based
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end component;
component fifo_2c_dram2 is -- fifo, 2 clock, dram based (v2)
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end component;
end package memlib;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd
|
1
|
9458
|
-- $Id: rlink_sp1c_fx2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c_fx2 - syn
-- Description: rlink_core8 + serport_1clock + fx2 combo
--
-- Dependencies: rlinklib/rlink_core8
-- serport/serport_1clock
-- rlinklib/rlink_rlbmux
-- fx2lib/fx2_2fifoctl_ic
-- rbus/rbd_rbmon
-- rbus/rb_sres_or_2
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2015-05-02 672 14.7 131013 xc6slx16-2 618 875 90 340 s 7.2 - -
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.3.1 use rbaddr_ constants
-- 2015-05-02 672 1.3 add rbd_rbmon (optional via generics)
-- 2015-04-11 666 1.2 drop ENAESC, rearrange XON handling
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
BTOWIDTH : positive := 5; -- rbus timeout counter width
RTAWIDTH : positive := 12; -- retransmit buffer address width
SYSID : slv32 := (others=>'0'); -- rlink system id
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv4; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end entity rlink_sp1c_fx2;
architecture syn of rlink_sp1c_fx2 is
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
signal RB_SRES_M : rb_sres_type := rb_sres_init;
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
begin
CORE : rlink_core8 -- rlink master ----------------------
generic map (
BTOWIDTH => BTOWIDTH,
RTAWIDTH => RTAWIDTH,
SYSID => SYSID,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RLBMON=> ENAPIN_RLBMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
ESCXON => ENAXON,
ESCFILL => '0', -- not used in FX2 enabled boards
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_M,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock -- serport interface -----------------
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => '0', -- escaping now in rlink_core8
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RLBMUX : rlink_rlbmux -- rlink control mux -----------------
port map (
SEL => ENAFX2,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA,
P1_TXBUSY => FX2_TXBUSY
);
RLB_MONI.rxval <= RLB_VAL;
RLB_MONI.rxhold <= RLB_HOLD;
RLB_MONI.txena <= RLB_ENA;
RLB_MONI.txbusy <= RLB_BUSY;
FX2CNTL : fx2_2fifoctl_ic -- FX2 interface ---------------------
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => PETOWIDTH,
CCWIDTH => CCWIDTH,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
begin
I0 : rbd_rbmon
generic map (
RB_ADDR => RBMON_RBADDR,
AWIDTH => RBMON_AWIDTH)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_RBMON,
RB_SRES_SUM => RB_SRES_M
);
end generate RBMON;
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES,
RB_SRES_2 => RB_SRES_RBMON,
RB_SRES_OR => RB_SRES_M
);
RB_MREQ <= RB_MREQ_M; -- setup output signals
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/nexys4/tb/sys_conf_sim.vhd
|
1
|
1727
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys4_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2012-09-21 534 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/memlib/fifo_1c_dram_raw.vhd
|
1
|
4152
|
-- $Id: fifo_1c_dram_raw.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_1c_dram_raw - syn
-- Description: FIFO, single clock domain, distributed RAM based, 'raw'
-- interface exposing dram signals.
--
-- Dependencies: ram_1swar_1ar_gen
--
-- Test bench: tb/tb_fifo_1c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-03 47 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
entity fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
WE : in slbit; -- write enable
RE : in slbit; -- read enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
EMPTY : out slbit; -- empty flag
FULL : out slbit -- full flag
);
end fifo_1c_dram_raw;
architecture syn of fifo_1c_dram_raw is
type regs_type is record
waddr : slv(AWIDTH-1 downto 0); -- write address
raddr : slv(AWIDTH-1 downto 0); -- read address
empty : slbit; -- empty flag
full : slbit; -- full flag
end record regs_type;
constant memsize : positive := 2**AWIDTH;
constant regs_init : regs_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr
slv(to_unsigned(0,AWIDTH)), -- raddr
'1','0' -- empty,full
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal RAM_WE : slbit := '0';
begin
RAM : ram_1swar_1ar_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
WE => RAM_WE,
ADDRA => R_REGS.waddr,
ADDRB => R_REGS.raddr,
DI => DI,
DOA => open,
DOB => DO
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, RESET, WE, RE)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
variable we_val : slbit := '0';
variable re_val : slbit := '0';
variable iram_we : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
re_val := RE and not r.empty;
we_val := WE and ((not r.full) or RE);
isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
iram_we := '0';
if RESET = '1' then
n := regs_init;
else
if we_val = '1' then
n.waddr := slv(unsigned(r.waddr) + 1);
iram_we := '1';
if re_val = '0' then
n.empty := '0';
if unsigned(isize) = memsize-1 then
n.full := '1';
end if;
end if;
end if;
if re_val = '1' then
n.raddr := slv(unsigned(r.raddr) + 1);
if we_val = '0' then
n.full := '0';
if unsigned(isize) = 1 then
n.empty := '1';
end if;
end if;
end if;
end if;
N_REGS <= n;
RAM_WE <= iram_we;
SIZE <= isize;
EMPTY <= r.empty;
FULL <= r.full;
end process proc_next;
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd
|
1
|
4267
|
-- $Id: s6_cmt_sfs_unisim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s6_cmt_sfs - syn
-- Description: Spartan-6 CMT for simple frequency synthesis
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-05 537 1.0 Initial version (derived from s7_cmt_sfs)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or DCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/dcm locked
);
end s6_cmt_sfs;
architecture syn of s6_cmt_sfs is
begin
assert GEN_TYPE = "PLL" or GEN_TYPE = "DCM"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate NOGEN;
USEPLL: if GEN_TYPE = "PLL" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKOUT0 : slbit;
signal CLKOUT1_UNUSED : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
begin
PLL : pll_base
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT => VCO_MULTIPLY,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => OUT_DIVIDE,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => CLKIN_PERIOD,
REF_JITTER => CLKIN_JITTER)
port map (
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1_UNUSED,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT,
CLKIN => CLKIN,
LOCKED => LOCKED,
RST => '0'
);
BUFG_CLKOUT : bufg
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEPLL;
USEDCM: if GEN_TYPE = "DCM" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKOUT0 : slbit;
begin
DCM : dcm_sp
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => VCO_DIVIDE,
CLKFX_MULTIPLY => VCO_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE",
STARTUP_WAIT => STARTUP_WAIT)
port map (
CLKIN => CLKIN,
CLKFX => CLKOUT0,
LOCKED => LOCKED
);
BUFG_CLKOUT : bufg
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEDCM;
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd
|
1
|
3711
|
-- $Id: tb_tst_serloop_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop_s3 - sim
-- Description: Test bench for sys_tst_serloop_s3
--
-- Dependencies: simlib/simclk
-- vlib/xlib/dcm_sfs
-- sys_tst_serloop_s3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop_s3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk
-- 2011-11-17 426 1.0.1 use dcm_sfs now
-- 2011-11-06 420 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop_s3 is
end tb_tst_serloop_s3;
architecture sim of tb_tst_serloop_s3 is
signal CLK50 : slbit := '0';
signal CLKS : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 6,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLK50,
CLKFX => CLKS,
LOCKED => open
);
UUT : entity work.sys_tst_serloop_s3
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLKS,
CLKH => CLKS,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
|
1
|
19892
|
-- $Id: sys_w11a_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_s3 - syn
-- Description: w11a test design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- vlib/rlink/rlink_sp1c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/s3board/s3_sram_memctl
-- vlib/rlink/ioleds_sp1c
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rbus/rb_sres_or_2
--
-- Test bench: tb/tb_sys_w11a_s3
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2019-05-19 1150 14.7 131013 xc3s1000-4 3019 8764 574 5558 OK: +dz11 72%
-- 2019-04-27 1140 14.7 131013 xc3s1000-4 2890 8306 524 5252 OK: +*buf 68%
-- 2019-03-02 1116 14.7 131013 xc3s1000-4 2830 8045 462 5086 OK: +ibtst 66%
-- 2019-01-27 1108 14.7 131013 xc3s1000-4 2782 7873 446 4942 OK: -iist 64%
-- 2018-10-13 1055 14.7 131013 xc3s1000-4 2890 8217 446 5177 OK: +dmpcnt 67%
-- 2018-09-15 1045 14.7 131013 xc3s1000-4 2670 7721 382 4851 OK: +KP11P 63%
-- 2017-03-04 858 14.7 131013 xc3s1000-4 2576 7471 382 4716 OK: +DEUNA 61%
-- 2017-01-29 846 14.7 131013 xc3s1000-4 2538 7355 382 4635 OK: +int24 60%
-- 2015-06-04 686 14.7 131013 xc3s1000-4 2158 6453 350 3975 OK: +TM11 51%
-- 2015-05-14 680 14.7 131013 xc3s1000-4 2087 6316 350 3928 OK: +RHRP 51%
-- 2015-02-21 649 14.7 131013 xc3s1000-4 1643 5124 318 3176 OK: +RL11
-- 2014-12-22 619 14.7 131013 xc3s1000-4 1569 4768 302 2994 OK: +rbmon
-- 2014-12-20 614 14.7 131013 xc3s1000-4 1455 4523 302 2807 OK: -RL11,rlv4
-- 2014-06-08 561 14.7 131013 xc3s1000-4 1374 4580 286 2776 OK: +RL11
-- 2014-06-01 558 14.7 131013 xc3s1000-4 1301 4306 270 2614 OK:
-- 2011-12-21 442 13.1 O40d xc3s1000-4 1301 4307 270 2613 OK: LP+PC+DL+II
-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II
-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II
-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II
-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II
-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II
-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 1250 4097 224 2494 OK: LP+PC+DL+II
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 1209 3986 224 2425 OK: LP+PC+DL+II
-- 2009-05-17 216 10.1.03 K39 xc3s1000-4 1039 3542 224 2116 m+p; TIME OK
-- 2009-05-09 213 10.1.03 K39 xc3s1000-4 1037 3500 224 2100 m+p; TIME OK
-- 2009-04-26 209 8.2.03 I34 xc3s1000-4 1099 3557 224 2264 m+p; TIME OK
-- 2008-12-13 176 8.2.03 I34 xc3s1000-4 1116 3672 224 2280 m+p; TIME OK
-- 2008-12-06 174 10.1.02 K37 xc3s1000-4 1038 3503 224 2100 m+p; TIME OK
-- 2008-12-06 174 8.2.03 I34 xc3s1000-4 1116 3682 224 2281 m+p; TIME OK
-- 2008-08-22 161 8.2.03 I34 xc3s1000-4 1118 3677 224 2288 m+p; TIME OK
-- 2008-08-22 161 10.1.02 K37 xc3s1000-4 1035 3488 224 2086 m+p; TIME OK
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3344 224 2119 m+p; 21ns;BR-32
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3357 224 2128 m+p; 21ns;BR-16
-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3509 224 2220 m+p; TIME OK
-- 2008-05-01 140 9.2.04 J40 xc3s200-4 1009 3195 224 1918 m+p; T-OK;BR-16
-- 2008-03-19 127 8.2.03 I34 xc3s1000-4 1077 3471 224 2207 m+p; TIME OK
-- 2008-03-02 122 8.2.03 I34 xc3s1000-4 1068 3448 224 2179 m+p; TIME OK
-- 2008-03-02 121 8.2.03 I34 xc3s1000-4 1064 3418 224 2148 m+p; TIME FAIL
-- 2008-02-24 119 8.2.03 I34 xc3s1000-4 1071 3372 224 2141 m+p; TIME OK
-- 2008-02-23 118 8.2.03 I34 xc3s1000-4 1035 3301 182 1996 m+p; TIME OK
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-16 1112 2.2.1 set BTOWIDTH 7 (was 6, must > vmbox atowidth (6))
-- 2018-10-13 1055 2.2 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form
-- 2015-04-11 666 1.7.1 rearrange XON handling
-- 2015-02-21 649 1.7 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
-- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address
-- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon
-- 2014-08-28 588 1.6 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit
-- 2011-12-21 442 1.4.4 use rlink_sp1c; hio led usage now a for n2/n3
-- 2011-11-19 427 1.4.3 now numeric_std clean
-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob
-- 2011-07-08 390 1.4.1 use now sn_humanio
-- 2010-12-30 351 1.4 ported to rbv3
-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...)
-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
-- 2010-06-13 305 1.6.1 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
-- 2010-06-11 303 1.6 use IB_MREQ.racc instead of RRI_REQ
-- 2010-06-03 300 1.5.6 use default FAWIDTH for rri_core_serport
-- 2010-05-28 295 1.5.5 rename sys_pdp11core -> sys_w11a_s3
-- 2010-05-21 292 1.5.4 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.5.3 rename memctl_s3sram->s3_sram_memctl
-- 2010-05-05 288 1.5.2 add sys_conf_hio_debounce
-- 2010-05-02 287 1.5.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT from interfaces; drop RTSFLUSH generic
-- add pm1 rs232 (usp) support
-- 2010-05-01 285 1.5 port to rri V2 interface, use rri_core_serport
-- 2010-04-17 278 1.4.5 rename sram_dummy -> s3_sram_dummy
-- 2010-04-10 275 1.4.4 use s3_humanio; invert DP(1,3)
-- 2009-07-12 233 1.4.3 adapt to ibdr_(mini|maxi)sys interface changes
-- 2009-06-01 221 1.4.2 support ibdr_maxisys as well as _minisys
-- 2009-05-10 214 1.4.1 use pdp11_tmu_sb instead of pdp11_tmu
-- 2008-08-22 161 1.4.0 use iblib, ibdlib; renames
-- 2008-05-03 143 1.3.6 rename _cpursta->_cpurust
-- 2008-05-01 142 1.3.5 reassign LED(cpugo,halt,rust) and DISP(dispreg)
-- 2008-04-19 137 1.3.4 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
-- 2008-04-18 136 1.3.3 add RESET for ibdr_minisys
-- 2008-04-13 135 1.3.2 add _mem70 also for _bram configs
-- 2008-02-23 118 1.3.1 add _mem70
-- 2008-02-17 117 1.3 use ext. memory interface of _core;
-- use _cache + memctl or _bram (configurable)
-- 2008-01-20 113 1.2.1 finalize AP_LAM handling (0=cpu,1=dl11;4=rk05)
-- 2008-01-20 112 1.2 rename clkgen->clkdivce; use ibdr_minisys, BRESET
-- add _ib_mux2
-- 2008-01-06 111 1.1 use now iob_reg_*; remove rricp_pdp11core hack
-- instanciate all parts directly
-- 2007-12-23 105 1.0.4 add rritb_cpmon_sb
-- 2007-12-16 101 1.0.3 use _N for active low; set IOB attribute to RI/RO
-- 2007-12-09 100 1.0.2 add sram memory signals, dummy handle them
-- 2007-10-19 90 1.0.1 init RI_RXD,RO_TXD=1 to avoid startup glitch
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
--
-- w11a test design for s3board
-- w11a + rlink + serport
--
-- Usage of S3BOARD Switches, Buttons, LEDs:
--
-- SWI(7:6): no function (only connected to sn_humanio_rbus)
-- (5:4): select DSP
-- 00 abclkdiv & abclkdiv_f
-- 01 PC
-- 10 DISPREG
-- 11 DR emulation
-- (3): select LED display
-- 0 overall status
-- 1 DR emulation
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1): 1 enable XON
-- (0): 0 -> main board RS232 port
-- 1 -> Pmod B/top RS232 port
--
-- LEDs if SWI(3) = 1
-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70
--
-- LEDs if SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.s3boardlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_s3 is -- top level
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_w11a_s3;
architecture syn of sys_w11a_s3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"01"; -- s3board
constant sysid_vers : slv8 := x"00";
begin
CLK <= I_CLK50; -- use 50MHz as system clock
CLKDIV : clkdivce -- usec/msec clock divider -----------
generic map (
CDUWIDTH => 6,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ----------------
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
RLINK : rlink_sp1c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 13,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG);
SRAMCTL: s3_sram_memctl -- memory controller -----------------
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR(17 downto 0),
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => DSP_DP
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 2)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_OR => RB_SRES
);
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_sram/arty/tb/tb_tst_sram_arty.vhd
|
1
|
810
|
-- $Id: tb_tst_sram_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_sram_arty
-- Description: Configuration for tb_tst_sram_arty for tb_arty_dram
--
-- Dependencies: sys_tst_sram_arty
--
-- To test: sys_tst_sram_arty
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_sram_arty of tb_arty_dram is
for sim
for all : arty_dram_aif
use entity work.sys_tst_sram_arty;
end for;
end for;
end tb_tst_sram_arty;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/rlink/tb/rlink_tba.vhd
|
1
|
21834
|
-- $Id: rlink_tba.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_tba - syn
-- Description: rlink test bench adapter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic [synthesizable, but only used in tb's]
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-09-27 595 4.0 now full rlink v4 iface
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit; add state r_txal;
-- 2011-11-22 432 3.0.2 now numeric_std clean
-- 2011-11-19 427 3.0.1 fix crc8_update usage;
-- 2010-12-24 347 3.0 rename rritba->rlink_tba, CP_*->RL_*; rbus v3 port;
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-05-05 289 1.0.3 drop dead snooper code and unneeded unsigned casts
-- 2008-03-02 121 1.0.2 remove snoopers
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
entity rlink_tba is -- rlink test bench adapter
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CNTL : in rlink_tba_cntl_type; -- control port
DI : in slv16; -- input data
STAT : out rlink_tba_stat_type; -- status port
DO : out slv16; -- output data
RL_DI : out slv9; -- rlink: data in
RL_ENA : out slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv9; -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : out slbit -- rlink: data hold
);
end entity rlink_tba;
architecture syn of rlink_tba is
constant d_f_cflag : integer := 8; -- d9: comma flag
subtype d_f_data is integer range 7 downto 0; -- d9: data field
subtype f_byte1 is integer range 15 downto 8;
subtype f_byte0 is integer range 7 downto 0;
type txstate_type is (
s_txidle, -- s_txidle: wait for ENA
s_txsop, -- s_txsop: send sop
s_txeop, -- s_txeop: send eop
s_txcmd, -- s_txcmd: send cmd
s_txal, -- s_txal: send addr lsb
s_txah, -- s_txah: send addr msb
s_txcl, -- s_txcl: send blk count lsb
s_txch, -- s_txcl: send blk count msb
s_txdl, -- s_txdl: send data lsb
s_txdh, -- s_txdh: send data msb
s_txcrcl1, -- s_txcrcl1: send cmd crc lsb in wblk
s_txcrch1, -- s_txcrch1: send cmd crc msb in wblk
s_txwbld, -- s_txwbld: wblk data load
s_txwbdl, -- s_txwbdl: wblk send data lsb
s_txwbdh, -- s_txwbdh: wblk send data msb
s_txcrcl2, -- s_txcrcl2: send final crc lsb
s_txcrch2 -- s_txcrch2: send final crc msb
);
type txregs_type is record
state : txstate_type; -- state
ccmd : slv3; -- current command
snum : slv5; -- command sequence number
crc : slv16; -- crc (cmd and data)
braddr : slv16; -- block read address
bdata : slv16; -- block data
bloop : slbit; -- block loop flag
tcnt : slv16; -- tcnt (down count for wblk)
sopdone : slbit; -- sop send
eoppend : slbit; -- eop pending
end record txregs_type;
constant txregs_init : txregs_type := (
s_txidle, -- state
"000", -- ccmd
"00000", -- snum
(others=>'0'), -- crc
(others=>'0'), -- braddr
(others=>'0'), -- bdata
'0', -- bloop
(others=>'0'), -- tcnt
'0','0' -- sopdone, eoppend
);
type rxstate_type is (
s_rxidle, -- s_rxidle: wait for ENA
s_rxcmd, -- s_rxcmd: wait cmd
s_rxcl, -- s_rxcl: wait cnt lsb
s_rxch, -- s_rxcl: wait cnt msb
s_rxbabo, -- s_rxbabo: wait babo
s_rxdcl, -- s_rxdcl: wait dcnt lsb
s_rxdch, -- s_rxdch: wait dcnt msb
s_rxdl, -- s_rxdl: wait data lsb
s_rxdh, -- s_rxdh: wait data msb
s_rxstat, -- s_rxstat: wait status
s_rxcrcl, -- s_rxcrcl: wait crc lsb
s_rxcrch, -- s_rxcrch: wait crc msb
s_rxapl, -- s_rxapl: wait attn pat lsb
s_rxaph, -- s_rxaph: wait attn pat msb
s_rxacl, -- s_rxapl: wait attn crc lsb
s_rxach -- s_rxaph: wait attn crc msb
);
type rxregs_type is record
state : rxstate_type; -- state
ccmd : slv3; -- current command
crc : slv16; -- crc
bwaddr : slv16; -- block write address
data : slv16; -- received data
dcnt : slv16; -- done count
tcnt : slv16; -- tcnt (down count for rblk)
ack : slbit; -- ack flag
err : slbit; -- crc error flag
stat : slv8; -- stat
apend : slbit; -- attn pending
ano : slbit; -- attn notify seen
apat : slv16; -- attn pat
end record rxregs_type;
constant rxregs_init : rxregs_type := (
s_rxidle, -- state
"000", -- ccmd
(others=>'0'), -- crc
(others=>'0'), -- bwaddr
(others=>'0'), -- data
(others=>'0'), -- dcnt
(others=>'0'), -- tcnt
'0','0', -- ack, err
(others=>'0'), -- stat
'0','0', -- apend, ano
(others=>'0') -- attn pat
);
signal R_TXREGS : txregs_type := txregs_init; -- TX state registers
signal N_TXREGS : txregs_type := txregs_init; -- TX next value state regs
signal R_RXREGS : rxregs_type := rxregs_init; -- RX state registers
signal N_RXREGS : rxregs_type := rxregs_init; -- RX next value state regs
signal TXBUSY : slbit := '0';
signal RXBUSY : slbit := '0';
signal STAT_L : rlink_tba_stat_type := rlink_tba_stat_init; -- local, readable
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_TXREGS <= txregs_init;
R_RXREGS <= rxregs_init;
else
R_TXREGS <= N_TXREGS;
R_RXREGS <= N_RXREGS;
end if;
end if;
end process proc_regs;
-- tx FSM ==================================================================
proc_txnext: process (R_TXREGS, CNTL, DI, RL_BUSY)
variable r : txregs_type := txregs_init;
variable n : txregs_type := txregs_init;
variable itxbusy : slbit := '0';
variable icpdi : slv9 := (others=>'0');
variable iena : slbit := '0';
variable ibre : slbit := '0';
variable do_crc : slbit := '0';
begin
r := R_TXREGS;
n := R_TXREGS;
itxbusy := '1';
icpdi := (others=>'0');
iena := '0';
ibre := '0';
do_crc := '0';
if CNTL.eop='1' and r.state/= s_txidle then -- if eop requested and busy
n.eoppend := '1'; -- queue it
end if;
case r.state is
when s_txidle => -- s_txidle: wait for ENA ------------
itxbusy := '0';
if CNTL.ena = '1' then -- cmd requested
n.ccmd := CNTL.cmd;
if CNTL.eop = '1' then -- if eop requested with ENA
n.eoppend := '1'; -- queue it, eop after this cmd
end if;
if r.sopdone = '0' then -- if not in active packet
n.snum := (others=>'0'); -- set snum=0
n.state := s_txsop; -- send sop
else
n.state := s_txcmd;
end if;
else -- no cmd requested
if CNTL.eop='1' and r.sopdone='1' then -- if eop req and in packet
n.state := s_txeop; -- send eop
end if;
end if;
when s_txsop => -- s_txsop: send sop -----------------
n.sopdone := '1';
icpdi := c_rlink_dat_sop;
iena := '1';
if RL_BUSY = '0' then
n.crc := (others=>'0');
n.state := s_txcmd;
end if;
when s_txeop => -- s_txeop: send eop -----------------
n.sopdone := '0';
n.eoppend := '0';
icpdi := c_rlink_dat_eop;
iena := '1';
if RL_BUSY = '0' then
n.crc := (others=>'0');
n.state := s_txidle;
end if;
when s_txcmd => -- s_txcmd: send cmd -----------------
n.tcnt := CNTL.cnt;
n.braddr := (others=>'0');
icpdi(c_rlink_cmd_rbf_seq) := r.snum;
icpdi(c_rlink_cmd_rbf_code) := r.ccmd;
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.snum := slv(unsigned(r.snum) + 1);-- otherwise just increment snum
case r.ccmd is
when c_rlink_cmd_labo => n.state := s_txcrcl2;
when c_rlink_cmd_attn => n.state := s_txcrcl2;
when others => n.state := s_txal;
end case;
end if;
when s_txal => -- s_txal: send addr lsb -------------
icpdi := '0' & CNTL.addr(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txah;
end if;
when s_txah => -- s_txah: send addr msb -------------
icpdi := '0' & CNTL.addr(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
case r.ccmd is
when c_rlink_cmd_rreg => n.state := s_txcrcl2;
when c_rlink_cmd_rblk => n.state := s_txcl;
when c_rlink_cmd_wblk => n.state := s_txcl;
when others => n.state := s_txdl;
end case;
end if;
when s_txcl => -- s_txcl: send blk count lsb -------
icpdi := '0' & CNTL.cnt(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txch;
end if;
when s_txch => -- s_txch: send blk count msb -------
icpdi := '0' & CNTL.cnt(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
if r.ccmd = c_rlink_cmd_wblk then
n.state := s_txcrcl1;
else
n.state := s_txcrcl2;
end if;
end if;
when s_txdl => -- s_txdl: send data lsb -------------
icpdi := '0' & DI(d_f_data);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txdh;
end if;
when s_txdh => -- s_txdh: send data msb -------------
icpdi := '0' & DI(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txcrcl2;
end if;
when s_txcrcl1 => -- s_txcrcl1: send cmd crc lsb in wblk
icpdi := '0' & r.crc(f_byte0);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txcrch1;
end if;
when s_txcrch1 => -- s_txcrch1: send cmd crc msb in wblk
icpdi := '0' & r.crc(f_byte1);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txwbld;
end if;
when s_txwbld => -- s_txwbld: wblk data load ----------
-- this state runs when s_wreg is
-- executed in rlink, thus doesn't cost
-- an extra cycle in 2nd+ iteration.
ibre := '1';
n.bdata := DI;
n.tcnt := slv(unsigned(r.tcnt) - 1);
n.braddr := slv(unsigned(r.braddr) + 1);
if unsigned(r.tcnt) = 1 then
n.bloop := '0';
else
n.bloop := '1';
end if;
n.state := s_txwbdl;
when s_txwbdl => -- s_txwbdl: wblk send data lsb ------
icpdi := '0' & r.bdata(f_byte0);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
n.state := s_txwbdh;
end if;
when s_txwbdh => -- s_txwbdh: wblk send data msb ------
icpdi := '0' & r.bdata(f_byte1);
iena := '1';
if RL_BUSY = '0' then
do_crc := '1';
if r.bloop = '1' then
n.state := s_txwbld;
else
n.state := s_txcrcl2;
end if;
end if;
when s_txcrcl2 => -- s_txcrcl2: send final crc lsb -----
icpdi := '0' & r.crc(f_byte0);
iena := '1';
if RL_BUSY = '0' then
n.state := s_txcrch2;
end if;
when s_txcrch2 => -- s_txcrch2: send final crc msb -----
icpdi := '0' & r.crc(f_byte1);
iena := '1';
if RL_BUSY = '0' then
if r.eoppend = '1' or unsigned(r.snum)=31 then
n.state := s_txeop;
else
n.state := s_txidle;
end if;
end if;
when others => null; -- <> --------------------------------
end case;
if do_crc = '1' then
n.crc := crc16_update(r.crc, icpdi(d_f_data));
end if;
N_TXREGS <= n;
TXBUSY <= itxbusy;
STAT_L.braddr <= r.braddr;
STAT_L.bre <= ibre;
RL_DI <= icpdi;
RL_ENA <= iena;
end process proc_txnext;
-- rx FSM ==================================================================
proc_rxnext: process (R_RXREGS, CNTL, RL_DO, RL_VAL)
variable r : rxregs_type := rxregs_init;
variable n : rxregs_type := rxregs_init;
variable irxbusy : slbit := '0';
variable ibwe : slbit := '0';
variable do_crc : slbit := '0';
variable ido : slv16 := (others=>'0');
begin
r := R_RXREGS;
n := R_RXREGS;
n.ack := '0';
n.ano := '0';
irxbusy := '1';
ibwe := '0';
do_crc := '0';
ido := r.data;
case r.state is
when s_rxidle => -- s_rxidle: wait --------------------
n.crc := (others=>'0');
n.err := '0';
if RL_VAL = '1' then
if RL_DO = c_rlink_dat_attn then -- attn seen ?
n.state := s_rxapl;
elsif RL_DO = c_rlink_dat_sop then
n.state := s_rxcmd;
end if;
else
irxbusy := '0'; -- signal rx not busy
end if;
when s_rxcmd => -- s_rxcmd: wait cmd ----------------
if RL_VAL = '1' then
if RL_DO = c_rlink_dat_eop then
n.state := s_rxidle;
else
n.bwaddr := (others=>'0');
do_crc := '1';
n.ccmd := RL_DO(n.ccmd'range);
case RL_DO(n.ccmd'range) is
when c_rlink_cmd_rreg => n.state := s_rxdl;
when c_rlink_cmd_rblk => n.state := s_rxcl;
when c_rlink_cmd_wreg => n.state := s_rxstat;
when c_rlink_cmd_wblk => n.state := s_rxdcl;
when c_rlink_cmd_labo => n.state := s_rxbabo;
when c_rlink_cmd_attn => n.state := s_rxdl;
when c_rlink_cmd_init => n.state := s_rxstat;
when others => null;
end case;
end if;
else
irxbusy := '0'; -- signal rx not busy
end if;
when s_rxcl => -- s_rxcl: wait cnt lsb --------------
if RL_VAL = '1' then
do_crc := '1';
n.tcnt(f_byte0) := RL_DO(d_f_data);
n.state := s_rxch;
end if;
when s_rxch => -- s_rxch: wait cnt msb --------------
if RL_VAL = '1' then
do_crc := '1';
n.tcnt(f_byte1) := RL_DO(d_f_data);
n.state := s_rxdl;
end if;
when s_rxbabo => -- s_rxbabo: wait babo ---------------
if RL_VAL = '1' then
do_crc := '1';
n.data(15 downto 0) := (others=>'0');
n.data(f_byte0) := RL_DO(d_f_data);
n.state := s_rxstat;
end if;
when s_rxdl => -- s_rxdl: wait data lsb -------------
if RL_VAL = '1' then
do_crc := '1';
n.data(f_byte0) := RL_DO(d_f_data);
n.state := s_rxdh;
end if;
when s_rxdh => -- s_rxdh: wait data msb -------------
if RL_VAL = '1' then
do_crc := '1';
n.data(f_byte1) := RL_DO(d_f_data);
n.tcnt := slv(unsigned(r.tcnt) - 1);
n.bwaddr := slv(unsigned(r.bwaddr) + 1);
if r.ccmd = c_rlink_cmd_rblk then
ido(f_byte1) := RL_DO(d_f_data);
ibwe := '1';
end if;
if r.ccmd /= c_rlink_cmd_rblk then
n.state := s_rxstat;
elsif unsigned(r.tcnt) = 1 then
n.state := s_rxdcl;
else
n.state := s_rxdl;
end if;
end if;
when s_rxdcl => -- s_rxdcl: wait dcnt lsb ------------
if RL_VAL = '1' then
do_crc := '1';
n.dcnt(f_byte0) := RL_DO(d_f_data);
n.state := s_rxdch;
end if;
when s_rxdch => -- s_rxdch: wait dcnt msb ------------
if RL_VAL = '1' then
do_crc := '1';
n.dcnt(f_byte1) := RL_DO(d_f_data);
n.state := s_rxstat;
end if;
when s_rxstat => -- s_rxstat: wait status -------------
if RL_VAL = '1' then
do_crc := '1';
n.stat := RL_DO(d_f_data);
n.apend := RL_DO(c_rlink_stat_rbf_attn); -- update attn status
n.state := s_rxcrcl;
end if;
when s_rxcrcl => -- s_rxcrcl: wait crc lsb ------------
if RL_VAL = '1' then
if r.crc(f_byte0) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.state := s_rxcrch;
end if;
when s_rxcrch => -- s_rxcrch: wait crc msb ------------
if RL_VAL = '1' then
if r.crc(f_byte1) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.ack := '1';
n.state := s_rxcmd;
end if;
when s_rxapl => -- s_rxapl: wait attn pat lsb --------
if RL_VAL = '1' then
do_crc := '1';
n.apat(f_byte0) := RL_DO(d_f_data);
n.state := s_rxaph;
end if;
when s_rxaph => -- s_rxaph: wait attn pat msb --------
if RL_VAL = '1' then
do_crc := '1';
n.apat(f_byte1) := RL_DO(d_f_data);
n.state := s_rxacl;
end if;
when s_rxacl => -- s_rxacl: wait attn crc lsb --------
if RL_VAL = '1' then
if r.crc(f_byte0) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.state := s_rxach;
end if;
when s_rxach => -- s_rxach: wait attn crc msb --------
if RL_VAL = '1' then
if r.crc(f_byte1) /= RL_DO(d_f_data) then
n.err := '1';
end if;
n.ano := '1';
n.state := s_rxidle;
end if;
when others => null; -- <> --------------------------------
end case;
if do_crc = '1' then
n.crc := crc16_update(r.crc, RL_DO(d_f_data));
end if;
N_RXREGS <= n;
RXBUSY <= irxbusy;
DO <= ido;
STAT_L.stat <= r.stat;
STAT_L.ack <= r.ack;
STAT_L.err <= r.err;
STAT_L.bwaddr <= r.bwaddr;
STAT_L.bwe <= ibwe;
STAT_L.dcnt <= r.dcnt;
STAT_L.apend <= r.apend;
STAT_L.ano <= r.ano;
STAT_L.apat <= r.apat;
RL_HOLD <= '0';
end process proc_rxnext;
STAT_L.busy <= RXBUSY or TXBUSY;
STAT <= STAT_L;
end syn;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_CNE
|
Extras/VHDL/CNE_01300_bad.vhd
|
1
|
3292
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01300_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of constant name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01300_good is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end CNE_01300_good;
architecture Behavioral of CNE_01300_good is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
constant Length : unsigned(3 downto 0) := "1001"; -- Counter period
begin
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count>=Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable='1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/s3board/tb/tb_s3board.vhd
|
1
|
5971
|
-- $Id: tb_s3board.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_s3board - sim
-- Description: Test bench for s3board (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- tb_s3board_core
-- s3board_aif [UUT]
-- serport/tb/serport_master_tb
--
-- To test: generic, any s3board_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 3.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 3.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.2 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-21 432 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 2.0.3 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 2.0.2 use serport_uart_rxtx
-- 2010-05-01 286 2.0.1 use rritb_core as component again (rriv1 is gone..)
-- 2010-04-25 283 2.0 factor out basic device handling to tb_s3board_core
-- and_conf/_stim file processing to rri/tb/rritb_core
-- 2010-04-24 281 1.3.2 use serport_uart_[tr]x directly again
-- 2007-12-16 101 1.3.1 use _N for active low, add sram memory model
-- 2007-12-09 100 1.3 add sram memory signals
-- 2007-11-23 97 1.2 use serport_uart_[tr]x_tb to allow that UUT is a
-- [sft]sim model compiled with keep hierarchy
-- 2007-10-26 92 1.1.1 use DONE timestamp at end of execution
-- 2007-10-19 90 1.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- use CLKDIV="00 --> sim with max. serport speed
-- 2007-09-23 85 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.s3boardlib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_s3board is
end tb_s3board;
architecture sim of tb_s3board is
signal CLK : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'1');
signal O_MEM_BE_N : slv4 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADDR : slv18 := (others=>'Z');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLK,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
S3CORE : entity work.tb_s3board_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : s3board_aif
port map (
I_CLK50 => CLK,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/cmoda7/tb/cmoda7_sram_dummy.vhd
|
1
|
2201
|
-- $Id: cmoda7_sram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: cmoda7_sram_dummy - syn
-- Description: cmoda7 target (base; serport loopback, sram protect)
--
-- Dependencies: -
-- To test: tb_cmoda7_sram
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity cmoda7_sram_dummy is -- CmodA7 dummy (base+sram)
-- implements cmoda7_sram_aif
port (
I_CLK12 : in slbit; -- 12 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N : out slv3; -- c7 rgb-led 0 (act.low)
O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv19; -- sram: address lines
IO_MEM_DATA : inout slv8 -- sram: data lines
);
end cmoda7_sram_dummy;
architecture syn of cmoda7_sram_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_BTN; -- mirror BTN on LED
O_RGBLED0_N(0) <= not I_BTN(0); -- mirror BTN on RGBLED 0 -> red
O_RGBLED0_N(1) <= not I_BTN(1); -- 1 -> green
O_RGBLED0_N(2) <= not (I_BTN(0) and I_BTN(1)); -- 0+1 -> white
O_MEM_CE_N <= '1';
O_MEM_WE_N <= '1';
O_MEM_OE_N <= '1';
O_MEM_ADDR <= (others=>'0');
IO_MEM_DATA <= (others=>'Z');
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3.vhd
|
1
|
952
|
-- $Id: tb_tst_rlink_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_n3
-- Description: Configuration for tb_tst_rlink_n3 for tb_nexys3_fusp
--
-- Dependencies: sys_tst_rlink_n3
--
-- To test: sys_tst_rlink_n3
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2011-11-xx xxx - 0.29 13.1 O40d xc6slx16-2 u:???
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_n3 of tb_nexys3_fusp is
for sim
for all : nexys3_fusp_aif
use entity work.sys_tst_rlink_n3;
end for;
end for;
end tb_tst_rlink_n3;
|
gpl-3.0
|
nanomolina/vhdl_examples
|
RAM/dmem.vhd
|
2
|
1084
|
-- -a --ieee=synopsis -fexplicit -Wc,-m32 -Wa,--32
-- -e -Wa,--32 -Wl,-m32
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dmem is
port (a: in std_logic_vector(31 downto 0);
wd: in std_logic_vector(31 downto 0);
clk, we: in bit;
rd: out std_logic_vector(31 downto 0));
end entity;
architecture arq_dmem of dmem is
type mem is array (0 to 63) of std_logic_vector(31 downto 0);
begin
process(clk)
variable my_mem: mem;
variable address: std_logic_vector(5 downto 0);
variable pos_a: integer;
begin
for pos in 0 to 63 loop --Inicializo mi memoria
my_mem(pos) := std_logic_vector(to_unsigned(pos, 32));
end loop;
if clk'EVENT and clk='1' then
address := a(7 downto 2);
pos_a := to_integer(unsigned(address));
if we='1' then
my_mem(pos_a) := wd;
rd <= wd;
else
rd <= my_mem(pos_a);
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/issi/is61lv25616al.vhd
|
1
|
5949
|
-- $Id: is61lv25616al.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: is61lv25616al - sim
-- Description: ISSI 61LV25612AL SRAM model
-- Currently a truely minimalistic functional model, without
-- any timing checks. It assumes, that addr/data is stable at
-- the trailing edge of we.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted
-- 2007-12-14 101 1.0 Initial version (written on warsaw airport)
------------------------------------------------------------------------------
-- Truth table accoring to data sheet:
--
-- Mode WE_N CE_N OE_N LB_N UB_N D(7:0) D(15:8)
-- Not selected X H X X X high-Z high-Z
-- Output disabled H L H X X high-Z high-Z
-- X L X H H high-Z high-Z
-- Read H L L L H D_out high-Z
-- H L L H L high-Z D_out
-- H L L L L D_out D_out
-- Write L L X L H D_in high-Z
-- L L X H L high-Z D_in
-- L L X L L D_in D_in
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity is61lv25616al is -- ISSI 61LV25612AL SRAM model
port (
CE_N : in slbit; -- chip enable (act.low)
OE_N : in slbit; -- output enable (act.low)
WE_N : in slbit; -- write enable (act.low)
UB_N : in slbit; -- upper byte enable (act.low)
LB_N : in slbit; -- lower byte enable (act.low)
ADDR : in slv18; -- address lines
DATA : inout slv16 -- data lines
);
end is61lv25616al;
architecture sim of is61lv25616al is
signal CE : slbit := '0';
signal OE : slbit := '0';
signal WE : slbit := '0';
signal BE_L : slbit := '0';
signal BE_U : slbit := '0';
component is61lv25616al_bank is -- ISSI 61LV25612AL bank
port (
CE : in slbit; -- chip enable (act.high)
OE : in slbit; -- output enable (act.high)
WE : in slbit; -- write enable (act.high)
BE : in slbit; -- byte enable (act.high)
ADDR : in slv18; -- address lines
DATA : inout slv8 -- data lines
);
end component;
begin
CE <= not CE_N;
OE <= not OE_N;
WE <= not WE_N;
BE_L <= not LB_N;
BE_U <= not UB_N;
BANK_L : is61lv25616al_bank port map (
CE => CE,
OE => OE,
WE => WE,
BE => BE_L,
ADDR => ADDR,
DATA => DATA(7 downto 0));
BANK_U : is61lv25616al_bank port map (
CE => CE,
OE => OE,
WE => WE,
BE => BE_U,
ADDR => ADDR,
DATA => DATA(15 downto 8));
end sim;
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity is61lv25616al_bank is -- ISSI 61LV25612AL bank
port (
CE : in slbit; -- chip enable (act.high)
OE : in slbit; -- output enable (act.high)
WE : in slbit; -- write enable (act.high)
BE : in slbit; -- byte enable (act.high)
ADDR : in slv18; -- address lines
DATA : inout slv8 -- data lines
);
end is61lv25616al_bank;
architecture sim of is61lv25616al_bank is
constant T_rc : Delay_length := 10 ns; -- read cycle time (min)
constant T_aa : Delay_length := 10 ns; -- address access time (max)
constant T_oha : Delay_length := 2 ns; -- output hold time (min)
constant T_ace : Delay_length := 10 ns; -- ce access time (max)
constant T_doe : Delay_length := 4 ns; -- oe access time (max)
constant T_hzoe : Delay_length := 4 ns; -- oe to high-Z output (max)
constant T_lzoe : Delay_length := 0 ns; -- oe to low-Z output (min)
constant T_hzce : Delay_length := 4 ns; -- ce to high-Z output (min=0,max=4)
constant T_lzce : Delay_length := 3 ns; -- ce to low-Z output (min)
constant T_ba : Delay_length := 4 ns; -- lb,ub access time (max)
constant T_hzb : Delay_length := 3 ns; -- lb,ub to high-Z out (min=0,max=3)
constant T_lzb : Delay_length := 0 ns; -- lb,ub low-Z output (min)
constant memsize : positive := 2**(ADDR'length);
constant datzero : slv(DATA'range) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DATA'range);
signal WE_EFF : slbit := '0';
begin
WE_EFF <= CE and WE and BE;
proc_sram: process (CE, OE, WE, BE, WE_EFF, ADDR, DATA)
variable ram : ram_type := (others=>datzero);
begin
if falling_edge(WE_EFF) then -- end of write cycle
-- note: to_x01 used below to prevent
-- that 'z' a written into mem.
ram(to_integer(unsigned(ADDR))) := to_x01(DATA);
end if;
if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver
DATA <= ram(to_integer(unsigned(ADDR)));
else
DATA <= (others=>'Z');
end if;
end process proc_sram;
end sim;
|
gpl-3.0
|
nanomolina/vhdl_examples
|
mux2/mux2.vhd
|
4
|
433
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY mux2 IS
GENERIC (N: INTEGER:=32);
PORT (d0, d1: IN std_logic_vector(N-1 DOWNTO 0);
s: IN std_logic;
y: OUT std_logic_vector(N-1 DOWNTO 0));
END mux2;
ARCHITECTURE mux_est OF mux2 IS
BEGIN
PROCESS(s)
BEGIN
IF (s='0') THEN
y <= d0;
ELSIF (s='1') THEN
y <= d1;
END IF;
END PROCESS;
END mux_est;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd
|
1
|
7461
|
-- $Id: tb_nexys4_cram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4_cram - sim
-- Description: Test bench for nexys4 (base+cram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4_core
-- serport/tb/serport_master_tb
-- nexys4_cram_aif [UUT]
-- simlib/simbididly
-- bplib/micron/mt45w8mw16b
--
-- To test: generic, any nexys4_cram_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.3.2 use sfs_gsim_core
-- 2016-09-02 805 1.3.1 tbcore_rlink without CLK_STOP now
-- 2016-07-20 791 1.3 use simbididly
-- 2016-02-20 734 1.2.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4_cram is
end tb_nexys4_cram;
architecture sim of tb_nexys4_cram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal TB_MEM_CE_N : slbit := '1';
signal TB_MEM_BE_N : slv2 := (others=>'1');
signal TB_MEM_WE_N : slbit := '1';
signal TB_MEM_OE_N : slbit := '1';
signal TB_MEM_ADV_N : slbit := '1';
signal TB_MEM_CLK : slbit := '0';
signal TB_MEM_CRE : slbit := '0';
signal TB_MEM_WAIT : slbit := '0';
signal TB_MEM_ADDR : slv23 := (others=>'Z');
signal TB_MEM_DATA : slv16 := (others=>'0');
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant pcb_delay : Delay_length := 1 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4_cram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => TB_MEM_CE_N,
O_MEM_BE_N => TB_MEM_BE_N,
O_MEM_WE_N => TB_MEM_WE_N,
O_MEM_OE_N => TB_MEM_OE_N,
O_MEM_ADV_N => TB_MEM_ADV_N,
O_MEM_CLK => TB_MEM_CLK,
O_MEM_CRE => TB_MEM_CRE,
I_MEM_WAIT => TB_MEM_WAIT,
O_MEM_ADDR => TB_MEM_ADDR,
IO_MEM_DATA => TB_MEM_DATA
);
MM_MEM_CE_N <= TB_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= TB_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= TB_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= TB_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= TB_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= TB_MEM_CLK after pcb_delay;
MM_MEM_CRE <= TB_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= TB_MEM_ADDR after pcb_delay;
TB_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => TB_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.mt45w8mw16b
port map (
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd
|
1
|
18702
|
-- $Id: sys_w11a_n4.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n4 - syn
-- Description: w11a test design for nexys4
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_4line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/nxcramlib/nx_cram_memctl_as
-- bplib/fx2rlink/ioleds_sp1c
-- w11a/pdp11_hio70
-- bplib/bpgen/sn_humanio_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_sys_w11a_n4
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2022.1; ghdl 0.29-2.0.0 (ise 14.5-14.7 retired)
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic MHz
-- 2022-07-05 1247 2022.1 xc7a100t-1 3455 6137 279 17.5 2100 80
-- 2019-05-19 1150 2017.2 xc7a100t-1 3418 7272 285 17.5 2234 80 +dz11
-- 2019-05-01 1143 2017.2 xc7a100t-1 3295 6597 260 17.5 2107 80 +m9312
-- 2019-04-27 1140 2017.2 xc7a100t-1 3288 6574 260 17.0 2132 80 +dlbuf
-- 2019-04-24 1137 2017.2 xc7a100t-1 3251 6465 228 17.0 2043 80 +pcbuf
-- 2019-03-17 1123 2017.2 xc7a100t-1 3231 6403 212 17.0 2053 80 +lpbuf
-- 2019-03-02 1116 2017.2 xc7a100t-1 3200 6317 198 17.0 2032 80 +ibtst
-- 2019-02-02 1108 2018.3 xc7a100t-1 3165 6497 182 17.0 2054 80
-- 2019-02-02 1108 2017.2 xc7a100t-1 3146 6227 182 17.0 1982 80
-- 2018-10-13 1056 2017.2 xc7a100t-1 3146 6228 182 17.0 1979 80 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a100t-1 2926 5904 150 17.0 1884 80 +KW11P
-- 2017-04-22 885 2016.4 xc7a100t-1 2862 5859 150 12.0 1900 80 +dmcmon
-- 2017-04-16 881 2016.4 xc7a100t-1 2645 5621 138 12.0 1804 80 +DEUNA
-- 2017-01-29 846 2016.4 xc7a100t-1 2574 5496 138 12.0 1750 80 +int24
-- 2016-05-26 768 2016.1 xc7a100t-1 2777 5672 150 10.0 1763 90 dms=0
-- 2016-05-22 767 2016.1 xc7a100t-1 2790 5774 150 11.0 1812 75 fsm
-- 2016-03-29 756 2015.4 xc7a100t-1 2651 4955 150 11.0 1608 75 2clock
-- 2016-03-27 753 2015.4 xc7a100t-1 2545 4850 150 11.0 1576 80 meminf
-- 2016-03-27 752 2015.4 xc7a100t-1 2544 4875 178 13.0 1569 80 +TW=8
-- 2016-03-13 742 2015.4 xc7a100t-1 2536 4868 178 10.5 1542 80 +XADC
-- 2015-06-04 686 2014.4 xc7a100t-1 2111 4541 162 7.5 1469 80 +TM11
-- 2015-05-14 680 2014.4 xc7a100t-1 2030 4459 162 7.5 1427 80
-- 2015-02-22 650 2014.4 xc7a100t-1 1606 3652 146 3.5 1158 80
-- 2015-02-22 650 i 14.7 xc7a100t-1 1670 3564 124 1508 80
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 2.5 use s7_cmt_1ce1ce
-- 2018-10-13 1055 2.4 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 2.3 use serport_2clock2
-- 2016-03-19 748 2.2.1 define rlink SYSID
-- 2016-03-13 742 2.2 add sysmon_rbus
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70
-- 2015-04-11 666 1.4.2 rearrange XON handling
-- 2015-02-21 649 1.4.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux)
-- 2015-02-07 643 1.4 new DSP+LED layout, use pdp11_dr; drop bram and
-- minisys options;
-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display
-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio
-- 2014-12-24 620 1.2.1 relocate ibus window and hio rbus address
-- 2014-08-28 588 1.2 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-22 543 1.0 Initial version (derived from sys_w11a_n3)
------------------------------------------------------------------------------
--
-- w11a test design for nexys4
-- w11a + rlink + serport
--
-- Usage of Nexys 4 Switches, Buttons, LEDs
--
-- SWI(15:5): no function (only connected to sn_humanio_rbus)
-- (5): select DSP(7:4) display
-- 0 abclkdiv & abclkdiv_f
-- 1 PC
-- (4): select DSP(3:0) display
-- 0 DISPREG
-- 1 DR emulation
-- (3): select LED display
-- 0 overall status
-- 1 DR emulation
-- (2): unused-reserved (USB port select)
-- (1): 1 enable XON
-- (0): unused-reserved (serial port select)
--
-- LEDs if SWI(3) = 1
-- (15:0) DR emulation; shows R0 during wait like 11/45+70
--
-- LEDs if SWI(3) = 0
-- (7) MEM_ACT_W
-- (6) MEM_ACT_R
-- (5) cmdbusy (all rlink access, mostly rdma)
-- (4:0) if cpugo=1 show cpu mode activity
-- (4) kernel mode, pri>0
-- (3) kernel mode, pri=0
-- (2) kernel mode, wait
-- (1) supervisor mode
-- (0) user mode
-- if cpugo=0 shows cpurust
-- (4) '1'
-- (3:0) cpurust code
--
-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS, depending on SWI(5)
-- DSP(3:0) shows DISPREG or DR emulation, depending on SWI(4)
-- DP(3:0) shows IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.nxcramlib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_n4 is -- top level
-- implements nexys4_cram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end sys_w11a_n4;
architecture syn of sys_w11a_n4 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MEM_ADDR_EXT : slv22 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"05"; -- nexys4
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK100,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_4line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
CRAMCTL: nx_cram_memctl_as -- memory controller -----------------
generic map (
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR_EXT,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => DSP_DP(3 downto 0)
);
DSP_DP(7 downto 4) <= "0010";
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : pdp11_hio70 -- hio from sys70 --------------------
generic map (
LWIDTH => LED'length,
DCWIDTH => 3)
port map (
SEL_LED => SWI(3),
SEL_DSP => SWI(5 downto 4),
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
ABCLKDIV => ABCLKDIV,
DISPREG => DISPREG,
LED => LED,
DSP_DAT => DSP_DAT
);
HIO : sn_humanio_rbus -- hio manager -----------------------
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
-- setup unused outputs in nexys4
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/ibus/ibdr_dl11_buf.vhd
|
1
|
15868
|
-- $Id: ibdr_dl11_buf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_dl11_buf - syn
-- Description: ibus dev(rem): DL11-A/B
--
-- Dependencies: fifo_simple_dram
-- ib_rlim_slv
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2017.2; ghdl 0.18-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-05-31 1156 1.0.1 size->fuse rename; re-organize rlim handling
-- 2019-04-26 1139 1.0 Initial version (derived from ibdr_{dl11,pc11_buf})
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dl11_buf is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16));
AWIDTH : natural := 5); -- fifo address width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end ibdr_dl11_buf;
architecture syn of ibdr_dl11_buf is
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
subtype rcsr_ibf_rrlim is integer range 14 downto 12;
subtype rcsr_ibf_type is integer range 10 downto 8;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_rir : integer := 5;
constant rcsr_ibf_rlb : integer := 4;
constant rcsr_ibf_fclr : integer := 1;
subtype rbuf_ibf_rfuse is integer range AWIDTH-1+8 downto 8;
subtype rbuf_ibf_xfuse is integer range AWIDTH-1 downto 0;
subtype rbuf_ibf_data is integer range 7 downto 0;
subtype xcsr_ibf_xrlim is integer range 14 downto 12;
constant xcsr_ibf_xrdy : integer := 7;
constant xcsr_ibf_xie : integer := 6;
constant xcsr_ibf_xir : integer := 5;
constant xcsr_ibf_rlb : integer := 4;
constant xcsr_ibf_fclr : integer := 1;
constant xbuf_ibf_xval : integer := 15;
subtype xbuf_ibf_fuse is integer range AWIDTH-1+8 downto 8;
subtype xbuf_ibf_data is integer range 7 downto 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rrlim : slv3; -- rcsr: receiver rate limit
rdone : slbit; -- rcsr: receiver done
rie : slbit; -- rcsr: receiver interrupt enable
rintreq : slbit; -- rx interrupt request
xrlim : slv3; -- xcsr: transmitter rate limit
xrdy : slbit; -- xcsr: transmitter ready
xie : slbit; -- xcsr: transmitter interrupt enable
xintreq : slbit; -- tx interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
"000", -- rrlim
'0','0','0', -- rdone,rie,rintreq
"000", -- xrlim
'1', -- xrdy !! is set !!
'0', -- xie
'0' -- xintreq
);
constant c_fuse1 : slv(AWIDTH-1 downto 0) := slv(to_unsigned(1,AWIDTH));
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal RBUF_CE : slbit := '0';
signal RBUF_WE : slbit := '0';
signal RBUF_DO : slv8 := (others=>'0');
signal RBUF_RESET : slbit := '0';
signal RBUF_EMPTY : slbit := '0';
signal RBUF_FULL : slbit := '0';
signal RBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal XBUF_CE : slbit := '0';
signal XBUF_WE : slbit := '0';
signal XBUF_DO : slv8 := (others=>'0');
signal XBUF_RESET : slbit := '0';
signal XBUF_EMPTY : slbit := '0';
signal XBUF_FULL : slbit := '0';
signal XBUF_FUSE : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RRLIM_START : slbit := '0';
signal RRLIM_BUSY : slbit := '0';
signal XRLIM_START : slbit := '0';
signal XRLIM_BUSY : slbit := '0';
begin
assert AWIDTH>=4 and AWIDTH<=7
report "assert(AWIDTH>=4 and AWIDTH<=7): unsupported AWIDTH"
severity failure;
RBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RBUF_RESET,
CE => RBUF_CE,
WE => RBUF_WE,
DI => IB_MREQ.din(rbuf_ibf_data),
DO => RBUF_DO,
EMPTY => RBUF_EMPTY,
FULL => RBUF_FULL,
SIZE => RBUF_FUSE
);
XBUF : fifo_simple_dram
generic map (
AWIDTH => AWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => XBUF_RESET,
CE => XBUF_CE,
WE => XBUF_WE,
DI => IB_MREQ.din(xbuf_ibf_data),
DO => XBUF_DO,
EMPTY => XBUF_EMPTY,
FULL => XBUF_FULL,
SIZE => XBUF_FUSE
);
RRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.rrlim,
START => RRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => RRLIM_BUSY
);
XRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.xrlim,
START => XRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => XRLIM_BUSY
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rrlim <= N_REGS.rrlim; -- keep RRLIM field
R_REGS.xrlim <= N_REGS.xrlim; -- keep XRLIM field
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX, RESET,
RBUF_DO, RBUF_EMPTY, RBUF_FULL, RBUF_FUSE, RRLIM_BUSY,
XBUF_DO, XBUF_EMPTY, XBUF_FULL, XBUF_FUSE, XRLIM_BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable iback : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable irbufce : slbit := '0';
variable irbufwe : slbit := '0';
variable irbufrst : slbit := '0';
variable irrlimsta : slbit := '0';
variable ixbufce : slbit := '0';
variable ixbufwe : slbit := '0';
variable ixbufrst : slbit := '0';
variable ixrlimsta : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
iback := r.ibsel and ibreq;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
irbufce := '0';
irbufwe := '0';
irbufrst := RESET;
irrlimsta := '0';
ixbufce := '0';
ixbufwe := '0';
ixbufrst := RESET;
ixrlimsta := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then -- ibus selected ---------------------
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- receive control status ----
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then -- rcsr write
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rdone='1' and r.rie='0' then -- ie 0->1 while done=1
n.rintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupt
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rrlim) := r.rrlim;
idout(rcsr_ibf_type) := slv(to_unsigned(AWIDTH,3));
idout(rcsr_ibf_rir) := r.rintreq;
idout(rcsr_ibf_rlb) := RRLIM_BUSY;
if ibw1 = '1' then
n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
end if;
if ibw0 = '1' then
if IB_MREQ.din(rcsr_ibf_fclr) = '1' then -- 1 written to FCLR
irbufrst := '1'; -- then reset fifo
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- receive data buffer -------
if IB_MREQ.racc = '0' then -- cpu ---------------------
idout(rbuf_ibf_data) := RBUF_DO;
if ibrd = '1' then -- rbuf read
n.rdone := '0'; -- clear done
n.rintreq := '0'; -- cancel interrupt
if r.rdone='1' then -- data available ?
irbufce := '1'; -- read next from fifo
irbufwe := '0';
if RBUF_FUSE = c_fuse1 then -- last value (fuse=1) ?
ilam := '1'; -- rri lam
end if;
end if;
end if;
else -- rri ---------------------
idout(rbuf_ibf_rfuse) := RBUF_FUSE;
idout(rbuf_ibf_xfuse) := XBUF_FUSE;
if ibw0 = '1' then
if RBUF_FULL = '0' then -- fifo not full
irbufce := '1'; -- write to fifo
irbufwe := '1';
else -- write to full fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
when ibaddr_xcsr => -- XCSR -- transmit control status ---
idout(xcsr_ibf_xrdy) := r.xrdy;
idout(xcsr_ibf_xie) := r.xie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xie := IB_MREQ.din(xcsr_ibf_xie);
if IB_MREQ.din(xcsr_ibf_xie) = '1' then-- set IE to 1
if r.xrdy='1' and r.xie='0' then -- ie 0->1 while ready=1
n.xintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.xintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
idout(xcsr_ibf_xrlim) := r.xrlim;
idout(xcsr_ibf_xir) := r.xintreq;
idout(xcsr_ibf_rlb) := XRLIM_BUSY;
if ibw1 = '1' then
n.xrlim := IB_MREQ.din(xcsr_ibf_xrlim); -- set XRLIM field
end if;
if ibw0 = '1' then
if IB_MREQ.din(xcsr_ibf_fclr) = '1' then -- 1 written to FCLR
ixbufrst := '1'; -- then reset fifo
end if;
end if;
end if;
when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.xrdy = '1' then -- ignore buf write when rdy=0
n.xrdy := '0'; -- clear ready
n.xintreq := '0'; -- cancel interrupt
if XBUF_FULL = '0' then -- fifo not full
ixbufce := '1'; -- write to fifo
ixbufwe := '1';
if XBUF_EMPTY = '1' then -- first write to empty fifo
ilam := '1'; -- request attention
end if;
end if;
end if;
end if;
else -- rri ---------------------
idout(xbuf_ibf_xval) := not XBUF_EMPTY;
idout(xbuf_ibf_fuse) := XBUF_FUSE;
idout(xbuf_ibf_data) := XBUF_DO;
if ibrd = '1' then
if XBUF_EMPTY = '0' then -- fifo not empty
ixbufce := '1'; -- read from fifo
ixbufwe := '0';
else -- read from empty fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
when others => null;
end case;
else -- ibus not selected -----------------
-- handle rx done, timer and interrupt
if RBUF_EMPTY='0' and RRLIM_BUSY='0' then -- not empty and not busy ?
if r.rdone = '0' then -- done not set ?
n.rdone := '1'; -- set done
irrlimsta := '1'; -- start timer
if r.rie = '1' then -- irupts enabled ?
n.rintreq := '1'; -- request rx interrupt
end if;
end if;
end if;
-- handle tx ready, timer and interrupt
if XBUF_FULL='0' and XRLIM_BUSY='0' then -- not full and not busy ?
if r.xrdy = '0' then -- ready not set ?
n.xrdy := '1'; -- set ready
ixrlimsta := '1'; -- start timer
if r.xie = '1' then -- irupts enabled ?
n.xintreq := '1'; -- request tx interrupt
end if;
end if;
end if;
end if; -- else r.ibsel='1'
-- other state changes
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
if EI_ACK_TX = '1' then
n.xintreq := '0';
end if;
N_REGS <= n;
RBUF_RESET <= irbufrst;
RBUF_CE <= irbufce;
RBUF_WE <= irbufwe;
RRLIM_START <= irrlimsta;
XBUF_RESET <= ixbufrst;
XBUF_CE <= ixbufce;
XBUF_WE <= ixbufwe;
XRLIM_START <= ixrlimsta;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.xintreq;
end process proc_next;
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/ibus/ibdr_rl11.vhd
|
1
|
27571
|
-- $Id: ibdr_rl11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2014-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_rl11 - syn
-- Description: ibus dev(rem): RL11
--
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-02-28 653 14.7 131013 xc6slx16-2 80 197 12 80 s 7.9
-- 2014-06-15 562 14.7 131013 xc6slx16-2 81 199 13 78 s 8.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 1.0.2 don't init N_REGS (vivado fix for fsm inference)
-- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore
-- 2015-02-28 653 1.0 Initial verison
-- 2014-06-09 561 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_rl11 is -- ibus dev(rem): RL11
-- fixed address: 174400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_rl11;
architecture syn of ibdr_rl11 is
constant ibaddr_rl11 : slv16 := slv(to_unsigned(8#174400#,16));
constant ibaddr_rlcs : slv2 := "00"; -- rlcs address offset
constant ibaddr_rlba : slv2 := "01"; -- rlba address offset
constant ibaddr_rlda : slv2 := "10"; -- rlda address offset
constant ibaddr_rlmp : slv2 := "11"; -- rlmp address offset
-- usage of 16x16 memory bank
-- 0 0000 unused (but mirrors rlcs)
-- 1 0001 rlba
-- 2 0010 unused (but mirrors rlda)
-- 3 0011 rlmp (1st value)
-- 4 0100 rlmp (3rd value after gs; the crc)
-- 5 0101 unused
-- 6 0110 unused
-- 7 0111 unused (target for bad mprem states)
-- 11: 8 10-- sta(ds) (drive status)
-- 15:12 11-- pos(ds) (drive disk address)
constant imem_cs : slv4 := "0000"; -- unused
constant imem_ba : slv4 := "0001";
constant imem_da : slv4 := "0010"; -- unused
constant imem_mp : slv4 := "0011";
constant imem_crc : slv4 := "0100";
constant imem_bad : slv4 := "0111"; -- target for bad mprem states
constant imem_sta : slv4 := "1000";
constant imem_pos : slv4 := "1100";
subtype imf_typ is integer range 3 downto 2;
subtype imf_ds is integer range 1 downto 0;
constant rlcs_ibf_err : integer := 15;
constant rlcs_ibf_de : integer := 14;
subtype rlcs_ibf_e is integer range 13 downto 10;
subtype rlcs_ibf_ds is integer range 9 downto 8;
constant rlcs_ibf_crdy : integer := 7;
constant rlcs_ibf_ie : integer := 6;
subtype rlcs_ibf_bae is integer range 5 downto 4;
subtype rlcs_ibf_func is integer range 3 downto 1;
constant rlcs_ibf_drdy : integer := 0;
constant func_noop : slv3 := "000"; -- func: noop
constant func_wchk : slv3 := "001"; -- func: write check
constant func_gs : slv3 := "010"; -- func: get status
constant func_seek : slv3 := "011"; -- func: seek
constant func_rhdr : slv3 := "100"; -- func: read header
constant func_write : slv3 := "101"; -- func: write data
constant func_read : slv3 := "110"; -- func: read data
constant func_rnhc : slv3 := "111"; -- func: read data without header check
constant e_ok : slv4 := "0000"; -- e code: ok
constant e_incomp : slv4 := "0001"; -- e code: operation incomplete
-- defs for rem access of rlcs; func codes
constant rfunc_wcs : slv3 := "001"; -- rem func: write cs (err,de,e,drdy)
constant rfunc_wmp : slv3 := "010"; -- rem func: write mprem or mploc
-- rlcs usage or rem func=wmp
subtype rlcs_ibf_mprem is integer range 15 downto 11;
subtype rlcs_ibf_mploc is integer range 10 downto 8;
constant rlcs_ibf_ena_mprem : integer := 5;
constant rlcs_ibf_ena_mploc : integer := 4;
subtype rlda_ibf_seek_df is integer range 15 downto 7;
constant rlda_ibf_seek_hs : integer := 4;
constant rlda_ibf_seek_dir : integer := 2;
constant rlda_msk_seek : slv16 := "0000000000001011";
constant rlda_val_seek : slv16 := "0000000000000001";
constant rlda_ibf_gs_rst : integer := 3;
constant rlda_msk_gs : slv16 := "0000000011110111";
constant rlda_val_gs : slv16 := "0000000000000011";
constant sta_ibf_wde : integer := 15; -- Write data error - always 0
constant sta_ibf_che : integer := 14; -- Current head error - always 0
constant sta_ibf_wl : integer := 13; -- Write lock - used
constant sta_ibf_sto : integer := 12; -- Seek time out - used
constant sta_ibf_spe : integer := 11; -- Spin error - used
constant sta_ibf_wge : integer := 10; -- Write gate error - used
constant sta_ibf_vce : integer := 9; -- Volume check - used
constant sta_ibf_dse : integer := 8; -- Drive select error - used
constant sta_ibf_dt : integer := 7; -- Drive type - used
constant sta_ibf_hs : integer := 6; -- Head select - used
constant sta_ibf_co : integer := 5; -- Cover open - used
constant sta_ibf_ho : integer := 4; -- Heads out - used
constant sta_ibf_bh : integer := 3; -- Brush home - always 1
subtype sta_ibf_st is integer range 2 downto 0; -- Drive state
constant st_load : slv3 := "000"; -- st: Load(ing) cartidge - used
constant st_spin : slv3 := "001"; -- st: Spin(ing) up - !unused!
constant st_brush : slv3 := "010"; -- st: Brush(ing) cycle - !unused!
constant st_hload : slv3 := "011"; -- st: Load(ing) heads - !unused!
constant st_seek : slv3 := "100"; -- st: Seek(ing) - may be used
constant st_lock : slv3 := "101"; -- st: Lock(ed) on - used
constant st_unl : slv3 := "110"; -- st: Unload(ing) heads - !unused!
constant st_down : slv3 := "111"; -- st: Spin(ing) down - !unused!
-- only two mayor drive states are used
-- on: st=lock; ho=1; co=0; ( file connected in backend)
-- off: st=load; ho=0; co=1; (no file connected in backend)
subtype pos_ibf_ca is integer range 15 downto 7;
constant pos_ibf_hs : integer := 6;
subtype pos_ibf_sa is integer range 5 downto 0;
constant mploc_mp : slv3 := "000"; -- return imem(mp)
constant mploc_sta : slv3 := "001"; -- return sta(ds)
constant mploc_pos : slv3 := "010"; -- return pos(ds)
constant mploc_zero : slv3 := "011"; -- return 0
constant mploc_crc : slv3 := "100"; -- return imem(crc)
constant mprem_f_map : integer := 4; -- mprem map enable
subtype mprem_f_addr is integer range 3 downto 0;
constant mprem_f_seq : integer := 3; -- mprem seq enable
subtype mprem_f_state is integer range 2 downto 0;
constant mprem_mapseq : slv2 := "11"; -- enable map + seq
constant mprem_s_mp : slv3 := "000"; -- access imem(mp)
constant mprem_s_sta : slv3 := "001"; -- access sta(ds)
constant mprem_s_pos : slv3 := "010"; -- access pos(ds)
constant mprem_init : slv5 := "10000"; -- enable map,fix, show mp
constant ca_max_rl01 : slv9 := "011111111"; -- max cylinder for RL01 (255)
constant ca_max_rl02 : slv9 := "111111111"; -- max cylinder for RL02 (511)
type state_type is (
s_idle, -- idle: handle ibus
s_csread, -- csread: handle cs read
s_gs_rpos, -- gs_rpos: read pos(ds)
s_gs_sta, -- gs_sta: handle status
s_seek_rsta, -- seek_rsta: read sta(ds)
s_seek_rpos, -- seek_rpos: read pos(ds)
s_seek_clip, -- seek_clip: clip new ca
s_seek_wpos, -- seek_wpos: write pos(ds)
s_init -- init: handle init
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
state : state_type; -- state
iaddr : slv4; -- init addr counter
cserr : slbit; -- rlcs: composite error
csde : slbit; -- rlcs: drive error
cse : slv4; -- rlcs: error
csds : slv2; -- rlcs: drive select
cscrdy : slbit; -- rlcs: controller ready
csie : slbit; -- rlcs: interrupt enable
csbae : slv2; -- rlcs: bus address extenstion
csfunc : slv3; -- rlcs: function code
csdrdy : slbit; -- rlcs: drive ready
da : slv16; -- rlda shadow reg
gshs : slbit; -- gs: pos(ds)(hs) (head select)
seekdt : slbit; -- seek: drive type: 0=RL01, 1=RL02
seekcan: slv10; -- seek: cylinder address, new
seekcac: slv9; -- seek: cylinder address, clipped
ireq : slbit; -- interrupt request flag
mploc : slv3; -- mp loc state
mprem : slv5; -- mp rem state
crdone : slbit; -- control reset done since last fdone
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
s_init, -- state
imem_ba, -- iaddr
'0','0', -- cserr,csde
(others=>'0'), -- cse
(others=>'0'), -- csds
'1','0', -- cscrdy, csie
(others=>'0'), -- csbae
(others=>'0'), -- csfunc
'0', -- csdrdy
(others=>'0'), -- da
'0', -- gshs
'0', -- seekdt
(others=>'0'), -- seekcan
(others=>'0'), -- seekcac
'0', -- ireq
mploc_mp, -- mploc
mprem_init, -- mprem
'1' -- crdone
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';
signal MEM_ADDR : slv4 := (others=>'0');
signal MEM_DIN : slv16 := (others=>'0');
signal MEM_DOUT : slv16 := (others=>'0');
begin
MEM_1 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_1_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte1),
DO => MEM_DOUT(ibf_byte1));
MEM_0 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_0_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte0),
DO => MEM_DOUT(ibf_byte0));
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET='1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, MEM_DOUT, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
variable iei_req : slbit := '0';
variable imem_we0 : slbit := '0';
variable imem_we1 : slbit := '0';
variable imem_addr : slv4 := (others=>'0');
variable imem_din : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
iei_req := '0';
imem_we0 := '0';
imem_we1 := '0';
imem_addr := "00" & IB_MREQ.addr(2 downto 1);
imem_din := IB_MREQ.din;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 3)=ibaddr_rl11(12 downto 3) then
n.ibsel := '1';
end if;
-- internal state machine
case r.state is
when s_idle => -- idle: handle ibus -----------------
if r.ibsel='1' then -- selected
idout := MEM_DOUT;
imem_we0 := ibw0;
imem_we1 := ibw1;
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rlcs => -- RLCS - control register -------
imem_we0 := '0'; -- MEM not used for rlcs
imem_we1 := '0';
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
-- determine DRDY
n.csdrdy := '1';
if MEM_DOUT(sta_ibf_st) /= st_lock or -- drive not on and locked
MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check
-- ??? also CRDY=0 here ???
n.csdrdy := '0';
end if;
-- determine DE and ERR
n.cserr := '0';
if MEM_DOUT(sta_ibf_st) = st_load or -- drive off
MEM_DOUT(sta_ibf_vce) = '1' then -- or volume check
n.csde := '1';
n.cserr := '1';
end if;
if r.csde = '1' or r.cse /= e_ok then
n.cserr := '1';
end if;
if ibrd = '1' then -- cs read
ibhold := '1';
n.state := s_csread;
elsif IB_MREQ.we = '1' then -- cs write
if ibrem = '0' then -- loc write access
if IB_MREQ.be1 = '1' then
if r.cscrdy = '1' then -- freeze csds when busy
n.csds := IB_MREQ.din(rlcs_ibf_ds);
end if;
end if;
if IB_MREQ.be0 = '1' then
n.csie := IB_MREQ.din(rlcs_ibf_ie);
n.csbae := IB_MREQ.din(rlcs_ibf_bae);
if r.cscrdy = '1' then -- controller ready
n.csfunc := IB_MREQ.din(rlcs_ibf_func); -- latch func
if IB_MREQ.din(rlcs_ibf_crdy) = '1' then -- no crdy clr
if IB_MREQ.din(rlcs_ibf_ie) = '1' and r.csie = '0' then
n.ireq := '1';
end if;
else -- crdy clr --> handle func
n.cserr := '0'; -- clear errors
n.csde := '0';
n.cse := "0000";
case IB_MREQ.din(rlcs_ibf_func) is
when func_noop => -- noop -------
n.ireq := r.csie; -- interrupt
when func_gs => -- get status -
if (r.da and rlda_msk_gs) /= rlda_val_gs then
n.cserr := '1';
n.cse := e_incomp;
n.ireq := IB_MREQ.din(rlcs_ibf_ie);
else
ibhold := '1';
n.state := s_gs_rpos;
end if;
when func_seek => -- seek -------
if (r.da and rlda_msk_seek) /= rlda_val_seek then
n.cserr := '1';
n.cse := e_incomp;
n.ireq := IB_MREQ.din(rlcs_ibf_ie);
else
ibhold := '1';
n.state := s_seek_rsta;
end if;
when others => -- all other funcs
n.cscrdy := '0'; -- signal cntl busy
ilam := '1'; -- issue lam
end case;
end if; -- else IB_MREQ.din(rlcs_ibf_crdy) = '1'
end if; -- r.cscrdy = '1'
end if; -- IB_MREQ.be0 = '1'
else -- rem write access
case IB_MREQ.din(rlcs_ibf_func) is
when rfunc_wcs =>
n.csde := IB_MREQ.din(rlcs_ibf_de);
n.cse := IB_MREQ.din(rlcs_ibf_e);
n.cscrdy := IB_MREQ.din(rlcs_ibf_crdy);
n.csbae := IB_MREQ.din(rlcs_ibf_bae);
if r.cscrdy = '0' and IB_MREQ.din(rlcs_ibf_crdy) = '1' then
n.ireq := r.csie;
end if;
when rfunc_wmp =>
if IB_MREQ.din(rlcs_ibf_ena_mprem) = '1' then
n.mprem := IB_MREQ.din(rlcs_ibf_mprem);
end if;
if IB_MREQ.din(rlcs_ibf_ena_mploc) = '1' then
n.mploc := IB_MREQ.din(rlcs_ibf_mploc);
end if;
when others => null;
end case;
end if;
end if;
when ibaddr_rlba => -- RLBA - bus address register ---
imem_din(0) := '0'; -- lsb forced 0
null;
when ibaddr_rlda => -- RLDA - disk address register --
if ibw1 = '1' then
n.da(15 downto 8) := IB_MREQ.din(15 downto 8);
end if;
if ibw0 = '1' then
n.da( 7 downto 0) := IB_MREQ.din( 7 downto 0);
end if;
when ibaddr_rlmp => -- RLMP - multipurpose register --
if ibrem = '0' then -- loc access
if ibrd = '1' then -- loc mp read
case r.mploc is
when mploc_mp => -- return imem(mp)
null;
when mploc_sta => -- return sta(ds)
imem_addr := imem_sta(imf_typ) & r.csds;
when mploc_pos => -- return pos(ds)
imem_addr := imem_pos(imf_typ) & r.csds;
n.mploc := mploc_zero;
when mploc_zero => -- return 0
idout := (others => '0');
n.mploc := mploc_crc;
when mploc_crc => -- return imem(crc)
imem_addr := imem_crc;
when others => null;
end case;
elsif IB_MREQ.we = '1' then -- loc mp write
n.mploc := mploc_mp; -- use main mp reg in future
end if;
else -- rem access
if r.mprem(mprem_f_map) = '0' then -- map off - fixed addr
imem_addr := r.mprem(mprem_f_addr);
else -- sequence
case r.mprem(mprem_f_state) is
when mprem_s_mp => -- mp {used as wc}
imem_addr := imem_mp;
if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!!
n.mprem := mprem_mapseq & mprem_s_sta;
end if;
when mprem_s_sta => -- sta(ds)
imem_addr := imem_sta(imf_typ) & r.csds;
if r.mprem(mprem_f_seq) = '1' then -- ??? check re&we !!!
n.mprem := mprem_mapseq & mprem_s_pos;
end if;
when mprem_s_pos => -- pos(ds)
imem_addr := imem_pos(imf_typ) & r.csds;
when others => -- bad state
imem_addr := imem_bad;
end case;
end if;
end if;
when others => null;
end case;
end if;
when s_csread => -- csread: handle cs read -----------
idout(rlcs_ibf_err) := r.cserr;
idout(rlcs_ibf_de) := r.csde;
idout(rlcs_ibf_e) := r.cse;
idout(rlcs_ibf_ds) := r.csds;
idout(rlcs_ibf_crdy) := r.cscrdy;
idout(rlcs_ibf_ie) := r.csie;
idout(rlcs_ibf_bae) := r.csbae;
idout(rlcs_ibf_func) := r.csfunc;
idout(rlcs_ibf_drdy) := r.csdrdy;
n.state := s_idle;
when s_gs_rpos => -- gs_rpos: read pos(ds) -----------
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
n.gshs := MEM_DOUT(pos_ibf_hs); -- get hs bit
ibhold := r.ibsel;
n.state := s_gs_sta;
when s_gs_sta => -- gs_sta: handle status -----------
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
imem_we0 := '1'; -- always update
imem_we1 := '1';
imem_din := MEM_DOUT;
imem_din(sta_ibf_hs) := r.gshs;
if r.da(rlda_ibf_gs_rst) = '1' then -- if RST set
imem_din(sta_ibf_wde) := '0'; -- clear error bits
imem_din(sta_ibf_che) := '0';
imem_din(sta_ibf_sto) := '0';
imem_din(sta_ibf_spe) := '0';
imem_din(sta_ibf_wge) := '0';
imem_din(sta_ibf_vce) := '0';
imem_din(sta_ibf_dse) := '0';
end if;
n.mploc := mploc_sta; -- use sta(ds) as mp
n.ireq := r.csie; -- interrupt
n.state := s_idle;
when s_seek_rsta => -- seek_rsta: read sta(ds) -----------
imem_addr := imem_sta(imf_typ) & r.csds; -- get sta(ds)
n.seekdt := MEM_DOUT(sta_ibf_dt);
imem_din := MEM_DOUT;
if MEM_DOUT(sta_ibf_st) /= st_lock then -- drive off
imem_we0 := '1'; -- update sta
imem_we1 := '1';
imem_din(sta_ibf_sto) := '1'; -- set STO (seek time out)
n.cse := e_incomp;
n.ireq := r.csie; -- interrupt
n.state := s_idle;
else -- drive on
ibhold := r.ibsel;
n.state := s_seek_rpos;
end if;
when s_seek_rpos => -- seek_rpos: read pos(ds) -----------
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
if r.da(rlda_ibf_seek_dir) = '1' then
n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) +
unsigned('0' & r.da(rlda_ibf_seek_df)) );
else
n.seekcan := slv(unsigned('0' & MEM_DOUT(pos_ibf_ca)) -
unsigned('0' & r.da(rlda_ibf_seek_df)) );
end if;
ibhold := r.ibsel;
n.state := s_seek_clip;
when s_seek_clip => -- seek_clip: clip new ca ------------
n.seekcac := r.seekcan(8 downto 0);
-- new ca overflowed ? for RL02 (9) and for RL01 (9:8) must be "00"
if r.seekcan(9) = '1' or
(r.seekdt = '0' and r.seekcan(8) = '1') then
if r.da(rlda_ibf_seek_dir) = '1' then -- outward seek
if r.seekdt = '1' then -- is RL02
n.seekcac := ca_max_rl02; -- clip to RL02 max ca
else -- is RL01
n.seekcac := ca_max_rl01; -- clip to RL01 max ca
end if;
else -- inward seek
n.seekcac := "000000000"; -- clip to 0
end if;
end if;
ibhold := r.ibsel;
n.state := s_seek_wpos;
when s_seek_wpos => -- seek_wpos: write pos(ds) ----------
imem_addr := imem_pos(imf_typ) & r.csds; -- get pos(ds)
imem_we0 := '1';
imem_we1 := '1';
imem_din := MEM_DOUT;
imem_din(pos_ibf_ca) := r.seekcac;
imem_din(pos_ibf_hs) := r.da(rlda_ibf_seek_hs);
n.ireq := r.csie; -- interrupt
n.state := s_idle;
when s_init => -- init: handle init -----------------
ibhold := r.ibsel; -- hold ibus when controller busy
imem_addr := r.iaddr;
imem_din := (others=>'0');
imem_we0 := '1';
imem_we1 := '1';
if r.iaddr(imf_typ) = imem_sta(imf_typ) then -- if sta(x)
imem_din := MEM_DOUT; -- keep state
imem_din(sta_ibf_wde) := '0'; -- and clear err
imem_din(sta_ibf_che) := '0';
imem_din(sta_ibf_sto) := '0';
imem_din(sta_ibf_spe) := '0';
imem_din(sta_ibf_wge) := '0';
imem_din(sta_ibf_vce) := '0';
imem_din(sta_ibf_dse) := '0';
end if;
n.iaddr := slv(unsigned(r.iaddr) + 1);
if unsigned(r.iaddr) = unsigned(imem_sta)+3 then -- stop after sta(3)
n.state := s_idle;
end if;
when others => null;
end case;
iei_req := r.ireq; -- ??? simplify, use r.ireq directly
if EI_ACK = '1' or r.csie = '0' then -- interrupt executed or ie disabled
n.ireq := '0'; -- cancel request
end if;
N_REGS <= n;
MEM_0_WE <= imem_we0;
MEM_1_WE <= imem_we1;
MEM_ADDR <= imem_addr;
MEM_DIN <= imem_din;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= iei_req;
end process proc_next;
end syn;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_CNE
|
Extras/VHDL/CNE_01300_good.vhd
|
1
|
3298
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01300_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of constant name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01300_good is
port (
i_Clock : in std_logic; -- Main clock signal
i_Reset_n : in std_logic; -- Main reset signal
i_Enable : in std_logic; -- Enables the counter
o_Count : out std_logic_vector(3 downto 0) -- Counter (unsigned value)
);
end CNE_01300_good;
architecture Behavioral of CNE_01300_good is
signal Count : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
constant c_Length : unsigned(3 downto 0) := "1001"; -- Counter period
begin
-- Will count undefinitely from 0 to i_Length while i_Enable is asserted
P_Count:process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
Count <= (others => '0');
elsif (rising_edge(i_Clock)) then
if (Count>=c_Length) then -- Counter restarts from 0
Count <= (others => '0');
elsif (i_Enable='1') then -- Increment counter value
Count <= Count + 1;
end if;
end if;
end process;
o_Count <= std_logic_vector(Count);
end Behavioral;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_rlink/nexys2/sys_conf.vhd
|
1
|
1506
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_CNE
|
Extras/VHDL/pkg_HBK.vhd
|
2
|
3376
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : pkg_HBK.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Package defining common elements used in examples of the handbook
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package pkg_HBK is
constant pkg_Width : integer range 1 to 256 := 4;
type pkg_Mux_record is
record
Data0 : std_logic_vector(pkg_Width-1 downto 0);
Data1 : std_logic_vector(pkg_Width-1 downto 0);
Sel : std_logic;
end record;
component Mux
port (
i_A : in std_logic; -- First Mux input
i_B : in std_logic; -- Second Mux input
i_S : in std_logic; -- Mux selector
o_O : out std_logic -- Mux output
);
end component;
component Mux_With_Record
port (
i_Record : in pkg_Mux_Record; -- Record containing datas and select
o_Data : out std_logic_vector(pkg_Width-1 downto 0) -- Mux data output
);
end component;
component DFlipFlop
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic; -- D Flip-Flop output signal
o_Q_n : out std_logic -- D Flip-Flop output signal, inverted
);
end component;
end package;
|
gpl-3.0
|
abcsds/Micros
|
RS232Write_16/RS232Write.vhd
|
2
|
1437
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity RS232Write is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
DATAWR : in std_logic_vector(7 downto 0);
NBaud : in std_logic_vector(3 downto 0);
EOT : out std_logic;
Tx : out std_logic
);
end RS232Write;
architecture moore of RS232Write is
signal CTRL : std_logic_vector(3 downto 0);
signal FBaud : std_logic;
component BaudRate
port(
RST : in std_logic;
CLK : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end component;
component RightShift
port(
RST : in std_logic;
CLK : in std_logic;
CTRL : in std_logic_vector(3 downto 0);
DATAWR : in std_logic_vector(7 downto 0);
Tx : out std_logic
);
end component;
component FsmWrite
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOT : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end component;
begin
U00 : BaudRate port map(RST,CLK,NBaud,FBaud);
U01 : RightShift port map(RST,CLK,CTRL,DATAWR,Tx);
U02 : FsmWrite port map(RST,CLK,STR,FBaud,EOT,CTRL);
end moore;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_serloop/nexys4d/tb/sys_conf2_sim.vhd
|
1
|
2657
|
-- $Id: sys_conf2_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n4d (for test bench)
--
-- Dependencies: -
-- Tool versions: 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to
-- 240 cycles (2 usec). This affects mainly the autobauder. A break will be
-- detected after 128 msec periods, this in simulation after 256 usec or
-- 30720 cycles. This is compatible with bitrates of 115200 baud or higher
-- (115200 <-> 8.68 usec <-> 1040 cycles)
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz
constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clksys_msecdiv : integer := 2; -- shortened !!
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
constant sys_conf_clkser_msecdiv : integer := 2; -- shortened !!
-- configure hio interfaces -----------------------------------------------
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure serport ------------------------------------------------------
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
gpl-3.0
|
abcsds/Micros
|
RS232Read_16/baudraterd.vhd
|
4
|
2064
|
-- This module is used for dividing master clock
-- frecuency to required base Bauds frecuency.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end BaudRateRD;
architecture simple of BaudRateRD is
signal NB, Qp, Qn : std_logic_vector(18 downto 0);
begin
COMB: process(NBaud,ENC,Qp)
begin
case NBaud is
when "0000"=>
NB<= "1111010000100100000"; -- 110 Bauds
when "0001"=>
NB<= "0101000101100001010"; -- 300 Bauds
when "0010"=>
NB<= "0010100010110000101"; -- 600 Bauds
when "0011"=>
NB<= "0001010001011000010"; -- 1200 Bauds
when "0100"=>
NB<= "0000101000101100001"; -- 2400 Bauds
when "0101"=>
NB<= "0000010100010110000"; -- 4800 Bauds
when "0110"=>
NB<= "0000001010001011000"; -- 9600 Bauds
when "0111"=>
NB<= "0000000110110010000"; -- 14400 Bauds
when "1000"=>
NB<= "0000000101000101100"; -- 19200 Bauds
when "1001"=>
NB<= "0000000010100010110"; -- 38400 Bauds
when "1010"=>
NB<= "0000000001101100100"; -- 57600 Bauds
when "1011"=>
NB<= "0000000000110110010"; -- 115200 Bauds
when "1100"=>
NB<= "0000000000110000110"; -- 128000 Bauds
when "1101"=>
NB<= "0000000000011000011"; -- 256000 Bauds
when others=>
NB<= "0000000000000000000"; -- 0 Bauds
end case;
if(ENC='0')then
Qn<= NB;
FBaud<= '0';
else
if(Qp= "0000000000000000000")then
Qn<= NB;
FBaud<= '1';
else
Qn<= Qp-1;
FBaud<= '0';
end if;
end if;
end process COMB;
FF: process(RST,CLK,Qn)
begin
if(RST='1')then
Qp <= (others=>'0');
elsif(CLK'event and CLK='1') then
Qp <= Qn;
end if;
end process FF;
end simple;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/w11a/nexys4/tb/tb_w11a_n4.vhd
|
1
|
1090
|
-- $Id: tb_w11a_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2015 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_n4
-- Description: Configuration for tb_w11a_n4 for tb_nexys4_cram
--
-- Dependencies: sys_w11a_n4
--
-- To test: sys_w11a_n4
--
-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat
-- (#2) ../../tb/tb_pdp11_core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2011-11-25 295 - -.-- - - -:--
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.1 use tb_nexys4_cram now
-- 2013-09-22 432 1.0 Initial version (cloned from _n3)
------------------------------------------------------------------------------
configuration tb_w11a_n4 of tb_nexys4_cram is
for sim
for all : nexys4_cram_aif
use entity work.sys_w11a_n4;
end for;
end for;
end tb_w11a_n4;
|
gpl-3.0
|
wfjm/w11
|
rtl/w11a/pdp11_sim.vhd
|
1
|
1048
|
-- $Id: pdp11_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2007 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: pdp11_sim
-- Description: Definitions for simulations
--
-- Dependencies: -
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
package pdp11_sim is
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 5 ns;
end package pdp11_sim;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd
|
1
|
9773
|
-- $Id: sys_tst_sram_c7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_c7 - syn
-- Description: test of cmoda7 sram and its controller
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- tst_sram
-- bplib/cmoda7/c7_cram_memctl
-- bplib/bpgen/sn_humanio_eum_rbus
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_tst_sram_c7
--
-- Target Devices: generic
-- Tool versions: viv 2017.1-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1 1045 1355 18 5.0 469
-- 2019-02-02 1108 2018.3 xc7a35t-1 1045 1537 24 5.0 490
-- 2019-02-02 1108 2017.2 xc7a35t-1 1042 1541 24 5.0 494
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-16 1086 1.1 use s7_cmt_1ce1ce
-- 2017-06-11 914 1.0 Initial version
-- 2017-06-11 912 0.5 First draft (derived from sys_tst_sram_n4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.cmoda7lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_sram_c7 is -- top level
-- implements cmoda7_sram_aif
port (
I_CLK12 : in slbit; -- 12 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N : out slv3; -- c7 rgb-led 0
O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv19; -- sram: address lines
IO_MEM_DATA : inout slv8 -- sram: data lines
);
end sys_tst_sram_c7;
architecture syn of sys_tst_sram_c7 is
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal MEM_RESET : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv17 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"09"; -- cmoda7
constant sysid_vers : slv8 := x"00";
begin
GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
generic map (
CLKIN_PERIOD => 83.3,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000)
port map (
CLKIN => I_CLK12,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
LOCKED => open
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 6, -- 64 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => x"ffe8")
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 17)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
MEM_RESET => MEM_RESET,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
SRAMCTL : c7_sram_memctl
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
HIO : sn_humanio_emu_rbus
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3)
port map (
CLK => CLK,
RESET => '0',
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
SMRB : sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
RB_LAM(0) <= RB_LAM_TST;
O_LED(1) <= SER_MONI.txact;
O_LED(0) <= SER_MONI.rxact;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
DSP_DP(7 downto 4) <= "0010";
DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) &
'0' & SER_MONI.abclkdiv_f;
-- setup unused outputs in cmoda7
O_RGBLED0_N <= (others=>'1');
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_sram/nexys3/tb/tb_tst_sram_n3.vhd
|
1
|
990
|
-- $Id: tb_tst_sram_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_sram_n3
-- Description: Configuration for tb_tst_sram_n3 for tb_nexys3_fusp
--
-- Dependencies: sys_tst_sram_n3
--
-- To test: sys_tst_sram_n3
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2011-11-27 433 - 0.29 13.1 O40d xc6slx16 ???
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-03 435 1.1 use tb_nexys3_fusp
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_sram_n3 of tb_nexys3_fusp is
for sim
for all : nexys3_fusp_aif
use entity work.sys_tst_sram_n3;
end for;
end for;
end tb_tst_sram_n3;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/xlib/iob_reg_i.vhd
|
1
|
1412
|
-- $Id: iob_reg_i.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, input only
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end iob_reg_i;
architecture syn of iob_reg_i is
begin
IOB : iob_reg_i_gen
generic map (
DWIDTH => 1,
INIT => INIT)
port map (
CLK => CLK,
CE => CE,
DI(0) => DI,
PAD(0) => PAD
);
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd
|
2
|
2392
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n4 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-12 741 1.1 add sysmon_rbus
-- 2013-09-28 535 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- single clock design, clkser = clksys
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide;
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply;
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide;
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype;
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure further units -------------------------------------------------
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
gpl-3.0
|
wfjm/w11
|
rtl/ibus/iblib.vhd
|
1
|
8739
|
-- $Id: iblib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: iblib
-- Description: Definitions for ibus interface and bus entities
--
-- Dependencies: -
-- Tool versions: ise 8.1-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-23 1136 2.2.4 add CLK port to ib_intmap,ib_intmap24
-- 2019-04-14 1131 2.2.3 ib_rlim_gen: add CPUSUSP port; RLIM_CEV now slv8
-- 2019-03-17 1123 2.2.2 add ib_rlim_gen,ib_rlim_slv
-- 2019-02-10 1111 2.2.1 add ibd_ibtst
-- 2017-01-28 846 2.2 add ib_intmap24
-- 2016-05-28 770 2.1.1 use type natural for vec,pri fields of intmap_type
-- 2015-04-24 668 2.1 add ibd_ibmon
-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon
-- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw
-- 2010-06-11 303 1.1 added racc,cacc signals to ib_mreq_type
-- 2009-06-01 221 1.0.1 added dip signal to ib_mreq_type
-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
package iblib is
type ib_mreq_type is record -- ibus - master request
aval : slbit; -- address valid
re : slbit; -- read enable
we : slbit; -- write enable
rmw : slbit; -- read-modify-write
be0 : slbit; -- byte enable low
be1 : slbit; -- byte enable high
cacc : slbit; -- console access
racc : slbit; -- remote access
addr : slv13_1; -- address bit(12:1)
din : slv16; -- data (input to slave)
end record ib_mreq_type;
constant ib_mreq_init : ib_mreq_type :=
('0','0','0','0', -- aval, re, we, rmw
'0','0','0','0', -- be0, be1, cacc, racc
(others=>'0'), -- addr
(others=>'0')); -- din
type ib_sres_type is record -- ibus - slave response
ack : slbit; -- acknowledge
busy : slbit; -- busy
dout : slv16; -- data (output from slave)
end record ib_sres_type;
constant ib_sres_init : ib_sres_type :=
('0','0', -- ack, busy
(others=>'0')); -- dout
type ib_sres_vector is array (natural range <>) of ib_sres_type;
subtype ibf_byte1 is integer range 15 downto 8;
subtype ibf_byte0 is integer range 7 downto 0;
component ib_sel is -- ibus address select logic
generic (
IB_ADDR : slv16; -- ibus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
IB_MREQ : in ib_mreq_type; -- ibus request
SEL : out slbit -- select state bit
);
end component;
component ib_sres_or_2 is -- ibus result or, 2 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
component ib_sres_or_3 is -- ibus result or, 3 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
component ib_sres_or_4 is -- ibus result or, 4 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
component ib_sres_or_gen is -- ibus result or, generic
generic (
WIDTH : natural := 4); -- number of input ports
port (
IB_SRES_IN : in ib_sres_vector(1 to WIDTH); -- ib_sres input array
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end component;
type intmap_type is record -- interrupt map entry type
vec : natural; -- vector address
pri : natural; -- priority
end record intmap_type;
constant intmap_init : intmap_type := (0,0);
type intmap_array_type is array (15 downto 0) of intmap_type;
constant intmap_array_init : intmap_array_type := (others=>intmap_init);
component ib_intmap is -- external interrupt mapper (15 line)
generic (
INTMAP : intmap_array_type := intmap_array_init);
port (
CLK : in slbit; -- clock
EI_REQ : in slv16_1; -- interrupt request lines
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor)
EI_PRI : out slv3; -- interrupt priority
EI_VECT : out slv9_2 -- interrupt vector
);
end component;
type intmap24_array_type is array (23 downto 0) of intmap_type;
constant intmap24_array_init : intmap24_array_type := (others=>intmap_init);
component ib_intmap24 is -- external interrupt mapper (23 line)
generic (
INTMAP : intmap24_array_type := intmap24_array_init);
port (
CLK : in slbit; -- clock
EI_REQ : in slv24_1; -- interrupt request lines
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_ACK : out slv24_1; -- interrupt acknowledge (to requestor)
EI_PRI : out slv3; -- interrupt priority
EI_VECT : out slv9_2 -- interrupt vector
);
end component;
component ibd_ibmon is -- ibus dev: ibus monitor
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16));
AWIDTH : natural := 9);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus: request
IB_SRES : out ib_sres_type; -- ibus: response
IB_SRES_SUM : in ib_sres_type -- ibus: response (sum for monitor)
);
end component;
component ibd_ibtst is -- ibus dev(rem): ibus tester
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#170000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component ib_rlim_gen is -- ibus rate limter - master
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
CPUSUSP : in slbit; -- cpu suspended
RLIM_CEV : out slv8 -- clock enable vector
);
end component;
component ib_rlim_slv is -- ibus rate limter - slave
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
RLIM_CEV : in slv8; -- clock enable vector
SEL : in slv3; -- rlim select
START : in slbit; -- start timer
STOP : in slbit; -- stop timer
DONE : out slbit; -- 1 cycle pulse when expired
BUSY : out slbit -- timer running
);
end component;
--
-- components for use in test benches (not synthesizable)
--
component ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end component;
end package iblib;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/arty/artylib.vhd
|
1
|
3466
|
-- $Id: artylib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: artylib
-- Description: Digilent Arty components
--
-- Dependencies: -
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-29 1063 1.2 add arty_dram_aif
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-01-31 726 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package artylib is
component arty_aif is -- ARTY, abstract iface, base
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4 -- arty pwrmon (pos)
);
end component;
component arty_dram_aif is -- ARTY, abstract iface, base+dram
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end component;
end package artylib;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/serport/serport_2clock2.vhd
|
1
|
11344
|
-- $Id: serport_2clock2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_2clock2 - syn
-- Description: serial port: serial port module, 2 clock domain (v2)
--
-- Dependencies: cdclib/cdc_pulse
-- cdclib/cdc_signal_s1
-- cdclib/cdc_vector_s0
-- serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_2c_dram2
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-08 759 1.1 all cdc's via cdc_(pulse|signal|vector)
-- 2016-03-28 755 1.0.1 check assertions only at raising clock
-- 2016-03-25 752 1.0 Initial version (derived from serport_2clock, is
-- exactly same logic, re-written to allow proper
-- usage of vivado constraints)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.cdclib.all;
use work.memlib.all;
entity serport_2clock2 is -- serial port module, 2 clock dom. (v2)
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLKU : in slbit; -- U|clock (backend:user)
RESET : in slbit; -- U|reset
CLKS : in slbit; -- S|clock (frontend:serial)
CES_MSEC : in slbit; -- S|1 msec clock enable
ENAXON : in slbit; -- U|enable xon/xoff handling
ENAESC : in slbit; -- U|enable xon/xoff escaping
RXDATA : out slv8; -- U|receiver data out
RXVAL : out slbit; -- U|receiver data valid
RXHOLD : in slbit; -- U|receiver data hold
TXDATA : in slv8; -- U|transmit data in
TXENA : in slbit; -- U|transmit data enable
TXBUSY : out slbit; -- U|transmit busy
MONI : out serport_moni_type; -- U|serport monitor port
RXSD : in slbit; -- S|receive serial data (uart view)
TXSD : out slbit; -- S|transmit serial data (uart view)
RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
);
end serport_2clock2;
architecture syn of serport_2clock2 is
subtype cd_range is integer range CDWIDTH-1 downto 0; -- clk div value regs
signal RXACT_U : slbit := '0'; -- rxact in CLKU
signal TXACT_U : slbit := '0'; -- txact in CLKU
signal ABACT_U : slbit := '0'; -- abact in CLKU
signal RXOK_U : slbit := '0'; -- rxok in CLKU
signal TXOK_U : slbit := '0'; -- txok in CLKU
signal ABCLKDIV_U : slv(cd_range) := (others=>'0'); -- abclkdiv
signal ABCLKDIV_F_U: slv3 := (others=>'0'); -- abclkdiv_f
signal ENAXON_S : slbit := '0'; -- enaxon in CLKS
signal ENAESC_S : slbit := '0'; -- enaesc in CLKS
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal RESET_CLKS : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZEW : slv(RXFAWIDTH-1 downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(cd_range) := (others=>'0');
signal ABCLKDIV_F : slv3 := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
signal RXERR_U : slbit := '0';
signal RXOVR_U : slbit := '0';
signal ABDONE_U : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
-- sync CLKU->CLKS
CDC_RESET : cdc_pulse -- provide CLKS side RESET
generic map (
POUT_SINGLE => false,
BUSY_WACK => false)
port map (
CLKM => CLKU,
RESET => '0',
CLKS => CLKS,
PIN => RESET,
BUSY => open,
POUT => RESET_CLKS
);
CDC_ENAXON: cdc_signal_s1
port map (CLKO => CLKS, DI => ENAXON, DO => ENAXON_S);
CDC_ENAESC: cdc_signal_s1
port map (CLKO => CLKS, DI => ENAESC, DO => ENAESC_S);
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLKS,
CE_MSEC => CES_MSEC,
RESET => RESET_CLKS,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV,
ABCLKDIV_F => ABCLKDIV_F
);
RESET_INT <= RESET_CLKS or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => ENAXON_S,
ENAESC => ENAESC_S,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLKS,
RESET => RESET_INT,
ENAXON => ENAXON_S,
ENAESC => ENAESC_S,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_2c_dram2 -- input fifo, 2 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKS,
CLKR => CLKU,
RESETW => ABACT, -- clear fifo on abact
RESETR => RESET,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZEW => RXFIFO_SIZEW,
SIZER => open
);
TXFIFO : fifo_2c_dram2 -- output fifo, 2 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLKW => CLKU,
CLKR => CLKS,
RESETW => RESET,
RESETR => ABACT, -- clear fifo on abact
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZEW => open,
SIZER => open
);
-- receive back pressure
-- on if fifo more than 3/4 full (less than 1/4 free)
-- off if fifo less than 1/2 full (more than 1/2 free)
proc_rxok: process (CLKS)
constant rxsize_rxok_off : slv2 := "01";
constant rxsize_rxok_on : slv2 := "10";
variable rxsize_msb : slv2 := "00";
begin
if rising_edge(CLKS) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZEW(RXFAWIDTH-1 downto RXFAWIDTH-2);
if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
-- sync CLKS->CLKU
CDC_RXACT : cdc_signal_s1
port map (CLKO => CLKU, DI => RXACT, DO => RXACT_U);
CDC_TXACT : cdc_signal_s1
port map (CLKO => CLKU, DI => UART_TXBUSY, DO => TXACT_U);
CDC_ABACT : cdc_signal_s1
port map (CLKO => CLKU, DI => ABACT, DO => ABACT_U);
CDC_RXOK : cdc_signal_s1
port map (CLKO => CLKU, DI => RXOK, DO => RXOK_U);
CDC_TXOK : cdc_signal_s1
port map (CLKO => CLKU, DI => TXOK, DO => TXOK_U);
CDC_CDIV : cdc_vector_s0
generic map (
DWIDTH => CDWIDTH)
port map (
CLKO => CLKU,
DI => ABCLKDIV,
DO => ABCLKDIV_U
);
CDC_CDIVF : cdc_vector_s0
generic map (
DWIDTH => 3)
port map (
CLKO => CLKU,
DI => ABCLKDIV_F,
DO => ABCLKDIV_F_U
);
CDC_RXERR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXERR,
BUSY => open,
POUT => RXERR_U
);
CDC_RXOVR : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => RXOVR,
BUSY => open,
POUT => RXOVR_U
);
CDC_ABDONE : cdc_pulse
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => CLKS,
RESET => '0',
CLKS => CLKU,
PIN => ABDONE,
BUSY => open,
POUT => ABDONE_U
);
MONI.rxerr <= RXERR_U;
MONI.rxovr <= RXOVR_U;
MONI.rxact <= RXACT_U;
MONI.txact <= TXACT_U;
MONI.abact <= ABACT_U;
MONI.abdone <= ABDONE_U;
MONI.rxok <= RXOK_U;
MONI.txok <= TXOK_U;
proc_abclkdiv: process (ABCLKDIV_U, ABCLKDIV_F_U)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(ABCLKDIV_U'range) <= ABCLKDIV_U;
MONI.abclkdiv_f <= ABCLKDIV_F_U;
end process proc_abclkdiv;
-- synthesis translate_off
proc_check: process (CLKS)
begin
if rising_edge(CLKS) then
assert RXOVR = '0'
report "serport_2clock2-W: RXOVR = " & slbit'image(RXOVR) &
"; data loss in receive fifo"
severity warning;
assert RXERR = '0'
report "serport_2clock2-W: RXERR = " & slbit'image(RXERR) &
"; spurious receive error"
severity warning;
end if;
end process proc_check;
-- synthesis translate_on
end syn;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_CNE
|
Extras/VHDL/CNE_01000_bad.vhd
|
1
|
3675
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01000_bad.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of variable name: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01000_bad is
generic (
g_Width : positive := 4 -- Data Width
);
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_Data : in std_logic_vector(g_Width-1 downto 0); -- Data from which to count ones
o_Nb_One : out std_logic_vector(g_Width-1 downto 0) -- Number of ones in i_Data signal
);
end CNE_01000_bad;
architecture Behavioral of CNE_01000_bad is
-- Function to get the number of ones in a signal
function Get_Ones(data : in std_logic_vector(g_Width-1 downto 0)) return integer is
-- Number of ones in the input signal
variable nb_ones : integer range 0 to g_Width;
begin
nb_ones := 0;
-- Loop on each signal's bit
for i in 0 to g_Width-1 loop
if (data(i)='1') then
nb_ones := nb_ones + 1;
end if;
end loop;
return nb_ones;
end function;
-- Module output
signal Nb_One : std_logic_vector(g_Width-1 downto 0);
begin
-- Counts the number of ones in a signal and register this count.
p_Count_Ones:process(i_Reset_n,i_Clock)
begin
if (i_Reset_n='0') then
Nb_One <= (others => '0');
elsif (rising_edge(i_Clock)) then
Nb_One <= std_logic_vector(to_unsigned(Get_Ones(i_Data),Nb_One'length));
end if;
end process;
o_Nb_One <= Nb_One;
end Behavioral;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/rlink/tb/tb_rlink_tba.vhd
|
1
|
26622
|
-- $Id: tb_rlink_tba.vhd 1203 2019-08-19 21:41:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_rlink_tba - sim
-- Description: Test bench for rbus devices via rlink_tba
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- genlib/tb/clkdivce_tb
-- rlink_tba
-- rlink_core
-- rbtba_aif [UUT]
-- rlink_mon
-- rb_mon
--
-- To test: generic, any rbtba_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2016.2-2019.1; ghdl 0.18-0.36
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-08-17 1203 4.0.2 fix for ghdl V0.36 -Whide warnings
-- 2016-09-10 806 4.0.1 use clkdivce_tb
-- 2014-12-20 616 4.0.1 add dcnt check (with -n=) and .ndef
-- 2014-09-21 595 4.0 now full rlink v4 iface, 4 bit STAT
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
-- 2011-12-23 444 3.2 use new simclk/simclkcnt
-- 2011-11-22 432 3.1.1 now numeric_std clean
-- 2010-12-29 351 3.1 use rbtba_aif now, support _ssim level again
-- 2010-12-28 350 3.0.3 list cmd address, list send data for wreg/init
-- 2010-12-27 349 3.0.2 suppress D CHECK message for all masked rreg/rblk
-- 2010-12-25 348 3.0.1 drop RL_FLUSH support, add RL_MONI for rlink_core
-- 2010-12-24 347 3.0 rm tb_rritba->tb_rlink_tba, CP_*->RL_*;rbus v3 port
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-05 301 2.1.3 rename _rpmon -> _rbmon, .rpmon -> .rbmon
-- 2010-06-03 299 2.1.2 use sv_ prefix for shared variables
-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.1 add CP_FLUSH for rri_core
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-24 129 1.1.4 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.1.3 default .sdef now checks for errors, ignore
-- status bits and the attn flag.
-- 2008-01-20 112 1.1.2 rename clkgen->clkdivce
-- 2007-12-23 105 1.1.1 add .dbas[io] (allows to set base for data values)
-- 2007-11-24 98 1.1 add RP_IINT support
-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.genlib.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.simlib.all;
entity tb_rlink_tba is
end tb_rlink_tba;
architecture sim of tb_rlink_tba is
signal CLK : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RESET : slbit := '0';
signal TBA_CNTL : rlink_tba_cntl_type := rlink_tba_cntl_init;
signal TBA_DI : slv16 := (others=>'0');
signal TBA_STAT : rlink_tba_stat_type := rlink_tba_stat_init;
signal TBA_DO : slv16 := (others=>'0');
signal RL_DI : slv9 := (others=>'0');
signal RL_ENA : slbit := '0';
signal RL_BUSY : slbit := '0';
signal RL_DO : slv9 := (others=>'0');
signal RL_VAL : slbit := '0';
signal RL_HOLD : slbit := '0';
signal RL_MONI : rl_moni_type := rl_moni_init;
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal RB_MREQ_aval : slbit := '0';
signal RB_MREQ_re : slbit := '0';
signal RB_MREQ_we : slbit := '0';
signal RB_MREQ_initt: slbit := '0';
signal RB_MREQ_addr : slv16 := (others=>'0');
signal RB_MREQ_din : slv16 := (others=>'0');
signal RB_SRES_ack : slbit := '0';
signal RB_SRES_busy : slbit := '0';
signal RB_SRES_err : slbit := '0';
signal RB_SRES_dout : slv16 := (others=>'0');
signal RLMON_EN : slbit := '0';
signal RBMON_EN : slbit := '0';
signal N_CMD_CODE : string(1 to 4) := (others=>' ');
signal N_CMD_ADDR : slv16 := (others=>'0');
signal N_CMD_DATA : slv16 := (others=>'0');
signal N_CHK_DATA : boolean := false;
signal N_REF_DATA : slv16 := (others=>'0');
signal N_MSK_DATA : slv16 := (others=>'0');
signal N_CHK_DONE : boolean := false;
signal N_REF_DONE : slv16 := (others=>'0');
signal N_CHK_STAT : boolean := false;
signal N_REF_STAT : slv8 := (others=>'0');
signal N_MSK_STAT : slv8 := (others=>'0');
signal R_CMD_CODE : string(1 to 4) := (others=>' ');
signal R_CMD_ADDR : slv16 := (others=>'0');
signal R_CMD_DATA : slv16 := (others=>'0');
signal R_CHK_DATA : boolean := false;
signal R_REF_DATA : slv16 := (others=>'0');
signal R_MSK_DATA : slv16 := (others=>'0');
signal R_CHK_DONE : boolean := false;
signal R_REF_DONE : slv16 := (others=>'0');
signal R_CHK_STAT : boolean := false;
signal R_REF_STAT : slv8 := (others=>'0');
signal R_MSK_STAT : slv8 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
shared variable sv_dbasi : integer := 2;
shared variable sv_dbaso : integer := 2;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
CLKDIV : entity work.clkdivce_tb
generic map (
CDUWIDTH => 6,
USECDIV => 4,
MSECDIV => 5)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
TBA : rlink_tba
port map (
CLK => CLK,
RESET => RESET,
CNTL => TBA_CNTL,
DI => TBA_DI,
STAT => TBA_STAT,
DO => TBA_DO,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
RLINK : rlink_core
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => (others=>'0'))
port map (
CLK => CLK,
CE_INT => CE_MSEC,
RESET => RESET,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RB_MREQ_aval <= RB_MREQ.aval;
RB_MREQ_re <= RB_MREQ.re;
RB_MREQ_we <= RB_MREQ.we;
RB_MREQ_initt<= RB_MREQ.init;
RB_MREQ_addr <= RB_MREQ.addr;
RB_MREQ_din <= RB_MREQ.din;
RB_SRES.ack <= RB_SRES_ack;
RB_SRES.busy <= RB_SRES_busy;
RB_SRES.err <= RB_SRES_err;
RB_SRES.dout <= RB_SRES_dout;
UUT : rbtba_aif
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ_aval => RB_MREQ_aval,
RB_MREQ_re => RB_MREQ_re,
RB_MREQ_we => RB_MREQ_we,
RB_MREQ_initt=> RB_MREQ_initt,
RB_MREQ_addr => RB_MREQ_addr,
RB_MREQ_din => RB_MREQ_din,
RB_SRES_ack => RB_SRES_ack,
RB_SRES_busy => RB_SRES_busy,
RB_SRES_err => RB_SRES_err,
RB_SRES_dout => RB_SRES_dout,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RLMON : rlink_mon
generic map (
DWIDTH => RL_DI'length)
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RLMON_EN,
RL_DI => RL_DI,
RL_ENA => RL_ENA,
RL_BUSY => RL_BUSY,
RL_DO => RL_DO,
RL_VAL => RL_VAL,
RL_HOLD => RL_HOLD
);
RBMON : rb_mon
port map (
CLK => CLK,
CLK_CYCLE => CLK_CYCLE,
ENA => RBMON_EN,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
proc_stim: process
file fstim : text open read_mode is "tb_rlink_tba_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable ien : slbit := '0';
variable iaddr : slv16 := (others=>'0');
variable idata : slv16 := (others=>'0');
variable bcnt : integer := 0;
variable ccnt : integer := 0;
variable cmax : integer := 32;
variable nwait : integer := 0;
variable amnemo : string(1 to 6) := (others=>' ');
variable newline : boolean := true;
variable chk_data : boolean := false;
variable ref_data : slv16 := (others=>'0');
variable msk_data : slv16 := (others=>'0');
variable chk_stat : boolean := false;
variable ref_stat : slv8 := (others=>'0');
variable msk_stat : slv8 := (others=>'0');
variable chk_sdef : boolean := true;
variable ref_sdef : slv8 := (others=>'0');
variable msk_sdef : slv8 := "11111000"; -- ignore status bits and attn
variable chk_ndef : boolean := true;
type amrec_type is record
name : string(1 to 6);
addr : slv16;
end record;
constant amrec_init : amrec_type := ((others=>' '),
(others=>'0'));
constant amtbl_size : integer := 256;
type amtbl_type is array (1 to amtbl_size) of amrec_type;
variable amtbl_defs : integer := 0;
variable amtbl : amtbl_type := (others=>amrec_init);
procedure get_addr(L: inout line;
addr: out slv16) is
variable ichar : character := ' ';
variable name : string(1 to 6) := (others=>' ');
variable lok : boolean := false;
variable liaddr : slv16 := (others=>'0');
variable iaddr_or : slv16 := (others=>'0');
begin
readwhite(L);
readoptchar(L, '.', lok);
if lok then
readword_ea(L, name);
for i in 1 to amtbl_defs loop
if amtbl(i).name = name then
liaddr := amtbl(i).addr;
readoptchar(L, '|', lok);
if lok then
readgen_ea(L, iaddr_or);
for j in iaddr_or'range loop
if iaddr_or(j) = '1' then
liaddr(j) := '1';
end if;
end loop;
end if;
addr := liaddr;
return;
end if;
end loop;
report "address mnemonic not defined: " & name
severity failure;
end if;
readgen_ea(L, addr);
end procedure get_addr;
procedure cmd_waitdone is
variable lnwait : integer := 0;
begin
lnwait := 0;
while TBA_STAT.busy='1' loop
lnwait := lnwait + 1;
assert lnwait<2000 report "assert(lnwait<2000)" severity failure;
wait for clock_period;
end loop;
end procedure cmd_waitdone;
procedure setup_check_n (
pbcnt : in integer)
is
variable chk_done : boolean := false;
variable ref_done : slv16 := (others=>'0');
begin
readtagval_ea(iline, "n", chk_done, ref_done, 10);
if chk_done then
N_CHK_DONE <= chk_done;
N_REF_DONE <= ref_done;
else
N_CHK_DONE <= chk_ndef;
N_REF_DONE <= slv(to_unsigned(pbcnt,16));
end if;
end procedure setup_check_n;
procedure setup_check_d is
variable lchk_data : boolean := false;
variable lref_data : slv16 := (others=>'0');
variable lmsk_data : slv16 := (others=>'0');
begin
readtagval2_ea(iline, "d", lchk_data, lref_data, lmsk_data, sv_dbasi);
N_CHK_DATA <= lchk_data;
N_REF_DATA <= lref_data;
N_MSK_DATA <= lmsk_data;
end procedure setup_check_d;
procedure setup_check_s is
variable lchk_stat : boolean := false;
variable lref_stat : slv8 := (others=>'0');
variable lmsk_stat : slv8 := (others=>'0');
begin
readtagval2_ea(iline, "s", lchk_stat, lref_stat, lmsk_stat);
if lchk_stat then
N_CHK_STAT <= lchk_stat;
N_REF_STAT <= lref_stat;
N_MSK_STAT <= lmsk_stat;
else
N_CHK_STAT <= chk_sdef;
N_REF_STAT <= ref_sdef;
N_MSK_STAT <= msk_sdef;
end if;
end procedure setup_check_s;
procedure cmd_start (
pcmd : in slv3;
paddr : in slv16 := (others=>'0');
pdata : in slv16 := (others=>'0');
pbcnt : in integer := 1) is
begin
TBA_CNTL <= rlink_tba_cntl_init;
TBA_CNTL.cmd <= pcmd;
TBA_CNTl.addr <= paddr;
TBA_CNTL.cnt <= slv(to_unsigned(pbcnt,16));
TBA_DI <= pdata;
ccnt := ccnt + 1;
if ccnt >= cmax then
ccnt := 0;
TBA_CNTL.eop <= '1';
end if;
TBA_CNTL.ena <= '1';
wait for clock_period;
TBA_CNTL.ena <= '0';
TBA_CNTL.eop <= '0';
end procedure cmd_start;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
if TBA_STAT.ack = '1' and -- if ack cycle
iline'length>0 then -- and non empty line
if iline(1) = 'C' then -- and leading 'C'
wait for clock_period; -- wait cycle to ensure that comment
-- comes after moni response
end if;
end if;
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
N_CMD_CODE <= " ";
N_CHK_DATA <= false;
N_CHK_DONE <= false;
N_CHK_STAT <= false;
case dname is
when ".mode " => -- .mode
readword_ea(iline, dname);
assert dname="rri "
report "assert .mode == rri" severity failure;
when ".rlmon" => -- .rlmon
read_ea(iline, ien);
RLMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
RBMON_EN <= ien;
wait for 2*clock_period; -- wait for monitor to start
when ".sdef " => -- .sdef , set default for status chk
readtagval2_ea(iline, "s", chk_sdef, ref_sdef, msk_sdef);
when ".ndef " => -- .ndef , enable/disable done chk
read_ea(iline, idata(0));
chk_ndef := idata(0) = '1';
when ".amclr" => -- .amclr , clear addr mnemo table
amtbl_defs := 0;
amtbl := (others=>amrec_init);
when ".amdef" => -- .amdef , define addr mnemo table
assert amtbl_defs<amtbl_size
report "assert(amtbl_defs<amtbl_size): too many .amdef's"
severity failure;
readword_ea(iline, amnemo);
readgen_ea(iline, iaddr);
amtbl_defs := amtbl_defs + 1;
amtbl(amtbl_defs).name := amnemo;
amtbl(amtbl_defs).addr := iaddr;
when ".dbasi" => -- .dbasi
read_ea(iline, idelta);
assert idelta=2 or idelta=8 or idelta=16
report "assert(dbasi = 2,8, or 16)"
severity failure;
sv_dbasi := idelta;
when ".dbaso" => -- .dbaso
read_ea(iline, idelta);
assert idelta=2 or idelta=8 or idelta=16
report "assert(dbaso = 2,8, or 16)"
severity failure;
sv_dbaso := idelta;
when ".cmax " => -- .cmax
readint_ea(iline, cmax, 1, 32);
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".wtlam" => -- .wtlam
read_ea(iline, idelta);
nwait := 0;
loop
if TBA_STAT.ano='1' or nwait>=idelta then
writetimestamp(oline, CLK_CYCLE, ": .wtlam" & " nwait=");
write(oline, nwait, left);
if TBA_STAT.ano = '0' then
write(oline, string'(" FAIL TIMEOUT"));
end if;
writeline(output, oline);
exit;
end if;
nwait := nwait + 1;
wait for clock_period;
end loop;
when ".eop " => -- .eop
TBA_CNTL <= rlink_tba_cntl_init;
TBA_CNTL.eop <= '1';
wait for clock_period;
TBA_CNTL.eop <= '0';
wait for clock_period; -- wait (or rlink_tba will hang...)
ccnt := 0;
when "rreg " => -- rreg
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
N_CMD_DATA <= (others=>'Z');
setup_check_d;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_rreg, paddr=>iaddr);
cmd_waitdone;
when "rblk " => -- rblk
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
N_CMD_DATA <= (others=>'Z');
read_ea(iline, bcnt);
assert bcnt>0 report "assert(bcnt>0)" severity failure;
setup_check_n(bcnt);
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_rblk, paddr=>iaddr, pbcnt=>bcnt);
testempty_ea(iline);
newline := true;
for i in 1 to bcnt loop
while TBA_STAT.bwe='0' loop
wait for clock_period;
end loop;
if newline then
rblk_line: loop
readline (fstim, iline);
readcomment(iline, ok);
exit rblk_line when not ok;
end loop;
end if;
readtagval2_ea(iline, "d", chk_data, ref_data, msk_data,sv_dbasi);
N_CHK_DATA <= chk_data;
N_REF_DATA <= ref_data;
N_MSK_DATA <= msk_data;
testempty(iline, newline);
wait for clock_period;
end loop;
N_CHK_DATA <= false;
cmd_waitdone;
when "wreg " => -- wreg
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
readgen_ea(iline, idata, sv_dbasi);
N_CMD_DATA <= idata;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_wreg, paddr=>iaddr, pdata=>idata);
cmd_waitdone;
when "wblk " => -- wblk
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
N_CMD_DATA <= (others=>'Z');
read_ea(iline, bcnt);
assert bcnt>0 report "assert(bcnt>0)" severity failure;
setup_check_n(bcnt);
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_wblk, paddr=>iaddr, pbcnt=>bcnt);
testempty_ea(iline);
newline := true;
for i in 1 to bcnt loop
while TBA_STAT.bre='0' loop
wait for clock_period;
end loop;
if newline then
wblk_line: loop
readline (fstim, iline);
readcomment(iline, ok);
exit wblk_line when not ok;
end loop;
end if;
readgen_ea(iline, idata, sv_dbasi);
TBA_DI <= idata;
testempty(iline, newline);
wait for clock_period;
end loop;
cmd_waitdone;
when "labo " => -- labo
N_CMD_CODE <= dname(N_CMD_CODE'range);
N_CMD_ADDR <= (others=>'0');
N_CMD_DATA <= (others=>'Z');
setup_check_d;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_labo);
cmd_waitdone;
when "attn " => -- attn
N_CMD_CODE <= dname(N_CMD_CODE'range);
N_CMD_ADDR <= (others=>'0');
N_CMD_DATA <= (others=>'Z');
setup_check_d;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_attn);
cmd_waitdone;
when "init " => -- init
N_CMD_CODE <= dname(N_CMD_CODE'range);
get_addr(iline, iaddr);
N_CMD_ADDR <= iaddr;
readgen_ea(iline, idata, sv_dbasi);
N_CMD_DATA <= idata;
setup_check_s;
cmd_start(pcmd=>c_rlink_cmd_init, paddr=>iaddr, pdata=>idata);
cmd_waitdone;
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
wait for 4*clock_period;
CLK_STOP <= '1';
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
variable chk_ok : boolean := true;
begin
loop
wait until rising_edge(CLK);
R_CMD_CODE <= N_CMD_CODE;
R_CMD_ADDR <= N_CMD_ADDR;
R_CMD_DATA <= N_CMD_DATA;
R_CHK_DATA <= N_CHK_DATA;
R_REF_DATA <= N_REF_DATA;
R_MSK_DATA <= N_MSK_DATA;
R_CHK_DONE <= N_CHK_DONE;
R_REF_DONE <= N_REF_DONE;
R_CHK_STAT <= N_CHK_STAT;
R_REF_STAT <= N_REF_STAT;
R_MSK_STAT <= N_MSK_STAT;
if TBA_STAT.bwe = '1' then
writetimestamp(oline, CLK_CYCLE, ": rblk ");
writehex(oline, R_CMD_ADDR, right, 4);
write(oline, string'(" bwe=1 "));
writegen(oline, TBA_DO, right, base=>sv_dbaso);
if N_CHK_DATA then
if N_MSK_DATA /= "1111111111111111" then -- not all masked off
write(oline, string'(" .D.-CHECK"));
else
write(oline, string'(" ...-CHECK"));
end if;
if unsigned((TBA_DO xor N_REF_DATA) and (not N_MSK_DATA)) /= 0 then
write(oline, string'(" FAIL d="));
writegen(oline, N_REF_DATA, base=>sv_dbaso);
if unsigned(N_MSK_DATA) /= 0 then
write(oline, string'(","));
writegen(oline, N_MSK_DATA, base=>sv_dbaso);
end if;
else
write(oline, string'(" OK"));
end if;
end if;
writeline(output, oline);
end if;
if TBA_STAT.ack = '1' then
writetimestamp(oline, CLK_CYCLE, ": ");
write(oline, R_CMD_CODE);
writehex(oline, R_CMD_ADDR, right, 5);
write(oline, string'(" "));
write(oline, TBA_STAT.err, right, 1);
write(oline, TBA_STAT.stat, right, 9);
write(oline, string'(" "));
if R_CMD_CODE="wreg" or R_CMD_CODE="init" then
writegen(oline, R_CMD_DATA, right, base=>sv_dbaso);
else
writegen(oline, TBA_DO, right, base=>sv_dbaso);
end if;
if R_CHK_DATA or R_CHK_DONE or R_CHK_STAT then
chk_ok := true;
write(oline, string'(" "));
if R_CHK_DONE then
write(oline, string'("N"));
else
write(oline, string'("."));
end if;
if R_CHK_DATA and R_MSK_DATA/="1111111111111111" then
write(oline, string'("D"));
else
write(oline, string'("."));
end if;
if R_CHK_STAT and R_MSK_STAT/="11111111" then
write(oline, string'("S"));
else
write(oline, string'("."));
end if;
write(oline, string'("-CHECK"));
if R_CHK_DONE then
if TBA_STAT.dcnt /= R_REF_DONE then
chk_ok := false;
write(oline, string'(" FAIL n="));
write(oline, to_integer(unsigned(R_REF_DONE)));
end if;
end if;
if R_CHK_DATA then
if unsigned((TBA_DO xor R_REF_DATA) and (not R_MSK_DATA)) /= 0 then
chk_ok := false;
write(oline, string'(" FAIL d="));
writegen(oline, R_REF_DATA, base=>sv_dbaso);
if unsigned(R_MSK_DATA) /= 0 then
write(oline, string'(","));
writegen(oline, R_MSK_DATA, base=>sv_dbaso);
end if;
end if;
end if;
if R_CHK_STAT then
if unsigned((TBA_STAT.stat xor R_REF_STAT) and
(not R_MSK_STAT)) /= 0 then
chk_ok := false;
write(oline, string'(" FAIL s="));
write(oline, R_REF_STAT);
if unsigned(R_MSK_STAT) /= 0 then
write(oline, string'(","));
write(oline, R_MSK_STAT);
end if;
end if;
end if;
if chk_ok then
write(oline, string'(" OK"));
end if;
end if;
writeline(output, oline);
end if;
if TBA_STAT.ano = '1' then
writetimestamp(oline, CLK_CYCLE, ": ---- attn notify ---- ");
write(oline, TBA_STAT.apat, right, 16);
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd
|
1
|
4245
|
-- $Id: sys_tst_snhumanio_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_snhumanio_s3 - syn
-- Description: snhumanio tester design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/sn_humanio
-- tst_snhumanio
-- s3board/s3_sram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-18 410 13.1 O40d xc3s1000-4 149 211 - 143 t 11.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-25 419 1.0.2 get entity name right...
-- 2011-10-15 416 1.0.1 remove O_CLKSYS top level port
-- 2011-09-18 410 1.0 Initial version
------------------------------------------------------------------------------
-- Usage of S3BOARD Switches, Buttons, LEDs:
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_snhumanio_s3 is -- top level
-- implements s3board_aif
port (
I_CLK50 : in slbit; -- 50 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end sys_tst_snhumanio_s3;
architecture syn of sys_tst_snhumanio_s3 is
signal CLK : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_MSEC : slbit := '0';
begin
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => 50,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 4,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
HIOTEST : entity work.tst_snhumanio
generic map (
BWIDTH => 4)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
O_TXD <= I_RXD;
SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/w11a/pdp11_tmu_sb.vhd
|
1
|
1902
|
-- $Id: pdp11_tmu_sb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_tmu - sim
-- Description: pdp11: trace and monitor unit; simbus wrapper
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.1-14.7; viv 2016.2-2018.2; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-05 1053 1.0.2 use DM_STAT_CA instead of DM_STAT_SY
-- 2015-11-01 712 1.0.1 use sbcntl_sbf_tmu
-- 2009-05-10 214 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11.all;
entity pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := sbcntl_sbf_tmu); -- SB_CNTL for tmu
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache
);
end pdp11_tmu_sb;
architecture sim of pdp11_tmu_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : pdp11_tmu
port map (
CLK => CLK,
ENA => ENA,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_CA => DM_STAT_CA
);
end sim;
|
gpl-3.0
|
wfjm/w11
|
rtl/vlib/serport/serport_xontx.vhd
|
1
|
4600
|
-- $Id: serport_xontx.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: serport_xontx - syn
-- Description: serial port: xon/xoff logic tx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 425 1.0 Initial version
-- 2011-10-22 417 0.5 First draft
------------------------------------------------------------------------------
-- Note: for test bench usage a copy of all serport_* entities, with _tb
-- appended to the name, has been created in the /tb sub folder.
-- Ensure to update the copy when this file is changed !!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_xontx is -- serial port: xon/xoff logic tx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_TXDATA : out slv8; -- uart data in
UART_TXENA : out slbit; -- uart data enable
UART_TXBUSY : in slbit; -- uart data busy
TXDATA : in slv8; -- user data in
TXENA : in slbit; -- user data enable
TXBUSY : out slbit; -- user data busy
RXOK : in slbit; -- rx channel ok
TXOK : in slbit -- tx channel ok
);
end serport_xontx;
architecture syn of serport_xontx is
type regs_type is record
ibuf : slv8; -- input buffer
ival : slbit; -- ibuf has valid data
obuf : slv8; -- output buffer
oval : slbit; -- obuf has valid data
rxok : slbit; -- rx channel ok state
enaxon_1 : slbit; -- last enaxon
escpend : slbit; -- escape pending
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'),'0', -- ibuf,ival
(others=>'0'),'0', -- obuf,oval
'1', -- rxok (startup default is ok !!)
'0', -- enaxon_1
'0' -- escpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_TXBUSY,
TXDATA, TXENA, RXOK, TXOK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if TXENA='1' and r.ival='0' then
n.ibuf := TXDATA;
n.ival := '1';
end if;
if r.oval = '0' then
if ENAXON='1' and r.rxok/=RXOK then
n.rxok := RXOK;
n.oval := '1';
if r.rxok = '0' then
n.obuf := c_serport_xon;
else
n.obuf := c_serport_xoff;
end if;
elsif TXOK = '1' then
if r.escpend = '1' then
n.obuf := not r.ibuf;
n.oval := '1';
n.escpend := '0';
n.ival := '0';
elsif r.ival = '1' then
if ENAESC='1' and (r.ibuf=c_serport_xon or
r.ibuf=c_serport_xoff or
r.ibuf=c_serport_xesc)
then
n.obuf := c_serport_xesc;
n.oval := '1';
n.escpend := '1';
else
n.obuf := r.ibuf;
n.oval := '1';
n.ival := '0';
end if;
end if;
end if;
end if;
if r.oval='1' and UART_TXBUSY='0' then
n.oval := '0';
end if;
-- FIXME: document this hack
n.enaxon_1 := ENAXON;
if ENAXON='1' and r.enaxon_1='0' then
n.rxok := not RXOK;
end if;
N_REGS <= n;
TXBUSY <= r.ival;
UART_TXDATA <= r.obuf;
UART_TXENA <= r.oval;
end process proc_next;
end syn;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_CNE
|
Extras/VHDL/CNE_01700_good.vhd
|
1
|
2993
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01700_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of rising edge detection signal: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_01700_good is
port (
i_Reset_n : in std_logic; -- Reset signal
i_Clock : in std_logic; -- Clock signal
i_D : in std_logic; -- Signal on which detect edges
o_D_re : out std_logic -- Rising edge of i_D
);
end CNE_01700_good;
architecture Behavioral of CNE_01700_good is
signal D_r1 : std_logic; -- i_D registered 1 time
signal D_r2 : std_logic; -- i_D registered 2 times
begin
-- Rising edge detection process
P_detection: process(i_Reset_n, i_Clock)
begin
if (i_Reset_n='0') then
D_r1 <= '0';
D_r2 <= '0';
elsif (rising_edge(i_Clock)) then
D_r1 <= i_D;
D_r2 <= D_r1;
end if;
end process;
o_D_re <= D_r1 and not D_r2;
end Behavioral;
--CODE
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_CNE
|
help/CNE_header_example.vhd
|
1
|
2684
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : John Doe (Developper Company JohnDoeCompany on behalf of ContractorBigcompany )
-- Copyright : Copyright (c) CNES.
-- Licensing : This VHDL entity can be licensed to be be used in the frame of CNES contracts.
-- Ask CNES for an end-user license agreement (EULA).
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : yyyy-mm-dd : Author name's John Doe (JohnDoeCompany): Creation
-- V2 : yyyy-mm-dd : Author name's John Toe (JohnToeCompany):
-- Modification description
-- Modifications impacts
-- Modifications reasons
-------------------------------------------------------------------------------------------------
-- File name : header.vhd
-- File Creation date : yyyy-mm-dd
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : PC (OS version) - Editor (Version) - Synthetizer (Version) - P&R (Version)
-- Automatic VHDL coding : YES/NO
-- Tool used + Version
-- Source file information
-------------------------------------------------------------------------------------------------
-- Description : Relevant information related to this entity
--
-- Limitations : Hypothesis/constraints made on the external interfaces or configuration
-- that will impact this entity
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity header is
port (
);
end header;
architecture Behavioral of header is
begin
-- Behavioral code of header
end Behavioral;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_CNE
|
Extras/VHDL/CNE_00200_good.vhd
|
1
|
2868
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-09 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_00200_good.vhd
-- File Creation date : 2015-04-09
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Unsuitability of frequency in clock name: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--CODE
entity CNE_00200_good is
port (
i_Clock_div2 : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_00200_good;
--CODE
architecture Behavioral of CNE_00200_good is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop:process(i_Clock_div2, i_Reset_n)
begin
if (i_Reset_n='0') then
Q <= '0';
elsif (rising_edge(i_Clock_div2)) then
Q <= i_D;
end if;
end process;
o_Q <= Q;
end Behavioral;
|
gpl-3.0
|
nanomolina/vhdl_examples
|
datapath/ALU.vhd
|
2
|
1364
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ALU IS
PORT (a: IN std_logic_vector(31 DOWNTO 0);
b: IN std_logic_vector(31 DOWNTO 0);
alucontrol: IN std_logic_vector(2 DOWNTO 0);
zero: OUT std_logic;
result: OUT std_logic_vector(31 DOWNTO 0));
END ALU;
ARCHITECTURE ALU_arq OF ALU IS
BEGIN
PROCESS(a, b, alucontrol)
VARIABLE temp: std_logic_vector(31 DOWNTO 0);
BEGIN
CASE alucontrol IS
WHEN "000" => temp:= a AND b;
WHEN "001" => temp:= a OR b;
WHEN "010" => temp:= std_logic_vector(unsigned(a) + unsigned(b));
WHEN "011" => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
WHEN "100" => temp:= a AND (NOT b);
WHEN "101" => temp:= a OR (NOT b);
WHEN "110" => temp:= std_logic_vector(unsigned(a) - unsigned(b));
WHEN "111" =>
IF a<b THEN
temp := x"00000001";
ELSE
temp := x"00000000";
END IF;
WHEN OTHERS => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
END CASE;
result <= temp;
IF temp=x"00000000" THEN
zero <= '1';
ELSIF temp=x"00000001" THEN
zero <= '0';
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd
|
1
|
3559
|
-- $Id: tb_tst_serloop1_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n3 - sim
-- Description: Test bench for sys_tst_serloop1_n3
--
-- Dependencies: simlib/simclk
-- sys_tst_serloop1_n3 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n3
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2 remove CLK_STOP logic (simstop via report)
-- 2011-12-23 444 1.1 use new simclk
-- 2011-12-11 438 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
entity tb_tst_serloop1_n3 is
end tb_tst_serloop1_n3;
architecture sim of tb_tst_serloop1_n3 is
signal CLK100 : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant delay_time : Delay_length := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK100
);
UUT : entity work.sys_tst_serloop1_n3
port map (
I_CLK100 => CLK100,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_PPCM_CE_N => open,
O_PPCM_RST_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK100,
CLKH => CLK100,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN(3 downto 0)
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
|
gpl-3.0
|
wfjm/w11
|
rtl/w11a/pdp11_mem70.vhd
|
1
|
5930
|
-- $Id: pdp11_mem70.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mem70 - syn
-- Description: pdp11: 11/70 memory system registers
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.1 now numeric_std clean
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib
-- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS
-- 2008-01-27 115 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_mem70 is -- 11/70 memory system registers
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
HM_ENA : in slbit; -- hit/miss enable
HM_VAL : in slbit; -- hit/miss value
CACHE_FMISS : out slbit; -- cache force miss
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_mem70;
architecture syn of pdp11_mem70 is
constant ibaddr_loaddr : slv16 := slv(to_unsigned(8#177740#,16));
constant ibaddr_hiaddr : slv16 := slv(to_unsigned(8#177742#,16));
constant ibaddr_syserr : slv16 := slv(to_unsigned(8#177744#,16));
constant ibaddr_cntl : slv16 := slv(to_unsigned(8#177746#,16));
constant ibaddr_maint : slv16 := slv(to_unsigned(8#177750#,16));
constant ibaddr_hm : slv16 := slv(to_unsigned(8#177752#,16));
constant ibaddr_losize : slv16 := slv(to_unsigned(8#177760#,16));
constant ibaddr_hisize : slv16 := slv(to_unsigned(8#177762#,16));
subtype cntl_ibf_frep is integer range 5 downto 4;
subtype cntl_ibf_fmiss is integer range 3 downto 2;
constant cntl_ibf_disutrap : integer := 1;
constant cntl_ibf_distrap : integer := 0;
type regs_type is record -- state registers
ibsel_cr : slbit; -- ibus select cntl
ibsel_hm : slbit; -- ibus select hitmiss
ibsel_ls : slbit; -- ibus select losize
ibsel_nn : slbit; -- ibus select others
hm_data : slv6; -- hit/miss: data
cr_frep : slv2; -- cntl: force replacement bits
cr_fmiss : slv2; -- cntl: force miss bits
cr_disutrap: slbit; -- cntl: disable unibus trap
cr_distrap: slbit; -- cntl: disable traps
end record regs_type;
constant regs_init : regs_type := (
'0','0','0','0', -- ibsel_*
(others=>'0'), -- hm_data
"00","00", -- cr_frep,_fmiss
'0','0' -- dis(u)trap
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if CRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, HM_ENA, HM_VAL, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
n.ibsel_cr := '0';
n.ibsel_hm := '0';
n.ibsel_ls := '0';
n.ibsel_nn := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr = ibaddr_cntl(12 downto 1) then
n.ibsel_cr := '1';
end if;
if IB_MREQ.addr = ibaddr_hm(12 downto 1) then
n.ibsel_hm := '1';
end if;
if IB_MREQ.addr = ibaddr_losize(12 downto 1) then
n.ibsel_ls := '1';
end if;
if IB_MREQ.addr=ibaddr_loaddr(12 downto 1) or
IB_MREQ.addr=ibaddr_hiaddr(12 downto 1) or
IB_MREQ.addr=ibaddr_syserr(12 downto 1) or
IB_MREQ.addr=ibaddr_maint(12 downto 1) or
IB_MREQ.addr=ibaddr_hisize(12 downto 1) then
n.ibsel_nn := '1';
end if;
end if;
-- ibus transactions
if r.ibsel_cr = '1' then
idout(cntl_ibf_frep) := r.cr_frep;
idout(cntl_ibf_fmiss) := r.cr_fmiss;
idout(cntl_ibf_disutrap) := r.cr_disutrap;
idout(cntl_ibf_distrap) := r.cr_distrap;
end if;
if r.ibsel_hm = '1' then
idout(r.hm_data'range) := r.hm_data;
end if;
if r.ibsel_ls = '1' then
idout := slv(to_unsigned(sys_conf_mem_losize,16));
end if;
if r.ibsel_cr='1' and ibw0='1' then
n.cr_frep := IB_MREQ.din(cntl_ibf_frep);
n.cr_fmiss := IB_MREQ.din(cntl_ibf_fmiss);
n.cr_disutrap := IB_MREQ.din(cntl_ibf_disutrap);
n.cr_distrap := IB_MREQ.din(cntl_ibf_distrap);
end if;
if HM_ENA = '1' then
n.hm_data := r.hm_data(r.hm_data'left-1 downto 0) & HM_VAL;
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= (r.ibsel_cr or r.ibsel_hm or
r.ibsel_ls or r.ibsel_nn) and ibreq;
IB_SRES.busy <= '0';
end process proc_next;
CACHE_FMISS <= (R_REGS.cr_fmiss(1) or R_REGS.cr_fmiss(0));
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/w11a/nexys4d_bram/tb/tb_w11a_br_n4d.vhd
|
1
|
1057
|
-- $Id: tb_w11a_br_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_br_n4d
-- Description: Configuration for tb_w11a_br_n4d for tb_nexys4d
--
-- Dependencies: sys_w11a_br_n4d
--
-- To test: sys_w11a_br_n4d
--
-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat
-- (#2) ../../tb/tb_pdp11_core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2011-11-25 295 - -.-- - - -:--
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version (cloned from _br_n4)
------------------------------------------------------------------------------
configuration tb_w11a_br_n4d of tb_nexys4d is
for sim
for all : nexys4d_aif
use entity work.sys_w11a_br_n4d;
end for;
end for;
end tb_w11a_br_n4d;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/w11a/artys7/sys_w11a_as7.vhd
|
1
|
16582
|
-- $Id: sys_w11a_as7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_br_as7 - syn
-- Description: w11a design for as7 (with dram via mig)
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/artys7/sramif_mig_artys7
-- vlib/rlink/ioleds_sp1c
-- pdp11_hio70_artys7
-- bplib/bpgen/bp_swibtnled
-- bplib/bpgen/rgbdrv_3x2mux
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_sys_w11a_as7
--
-- Target Devices: generic
-- Tool versions: viv 2018.3-2022.1; ghdl 0.35-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7s50 6843 9162 878 17.5 3184
-- 2019-05-19 1150 2018.3 xc7s50 6843 10554 926 17.5 3425 +dz11
-- 2019-01-12 1105 2018.3 xc7s50 6585 9837 806 17.0 3250
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.0.1 use bufg_unisim
-- 2019-01-12 1105 1.0 Initial version (derived from sys_w11a_arty/br_as7)
------------------------------------------------------------------------------
--
-- w11a design for artys7 (using DDR3 memory via MIG)
-- w11a + rlink + serport
--
-- Usage of Arty S7 switches, Buttons, LEDs
--
-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
-- 00xy LED shows IO
-- y=1 enables CPU activities on RGB_G,RGB_R
-- x=1 enables MEM activities on RGB_B
-- 0100 LED+RGB give DR emulation 'light show'
-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
-- LED shows bit 7:4, RGB bit 1:0 of the byte selected by x
--
-- LED and RGB assignment for SWI=00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
-- (1) kernel mode, non-wait
-- (0) user or supervisor mode
-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
-- (1:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with SWI(1))
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- LED and RGB assignment for SWI=0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR( 9:08)
-- RGB_G DR( 5:04)
-- RGB_R DR( 1:00)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib.all;
use work.miglib_artys7.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_as7 is -- top level
-- implements artys7_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- artys7 switches
I_BTN : in slv4; -- artys7 buttons
O_LED : out slv4; -- artys7 leds
O_RGBLED0 : out slv3; -- artys7 rgb-led 0
O_RGBLED1 : out slv3; -- artys7 rgb-led 1
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sys_w11a_as7;
architecture syn of sys_w11a_as7 is
signal CLK100_BUF : slbit := '0';
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal IOLEDS : slv4 := (others=>'0');
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RGB_R : slv2 := (others=>'0');
signal RGB_G : slv2 := (others=>'0');
signal RGB_B : slv2 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"0a"; -- artys7
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 16, -- vco 1600 MHz
CLK2_OUTDIV => 10, -- mig sys 160.0 MHz
CLK3_OUTDIV => 8, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
CDC_CLK_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_CLK
);
GBL_RESET <= not LOCKED_CLK;
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 9, -- 512 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= MIG_MONI.rdrhit; -- ext_rdrhit
PERFEXT(1) <= MIG_MONI.wrrhit; -- ext_wrrhit
PERFEXT(2) <= MIG_MONI.wrflush; -- ext_wrflush
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEMCTL: sramif_mig_artys7 -- SRAM to MIG iface -----------------
port map (
CLK => CLK,
RESET => GBL_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
CLKMIG => CLKMIG,
CLKREF => CLKREF,
TEMP => XADC_TEMP,
MONI => MIG_MONI,
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => IOLEDS
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : entity work.pdp11_hio70_artys7 -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
HIORGB : rgbdrv_3x2mux
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
DATR => RGB_R,
DATG => RGB_G,
DATB => RGB_B,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1
);
SMRB : sysmonx_rbus_base -- always instantiated, needed for mig
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;
|
gpl-3.0
|
nanomolina/vhdl_examples
|
register/test_regfile.vhd
|
3
|
1882
|
library ieee;
use ieee.std_logic_1164.all;
entity test_regfile is
end entity;
architecture behaviour of test_regfile is
component regfile
port (ra1, ra2, wa3: in std_logic_vector(4 downto 0);
wd3: in std_logic_vector(31 downto 0);
we3, clk: in std_logic;
rd1, rd2: out std_logic_vector(31 downto 0));
end component;
signal ra1, ra2, wa3: std_logic_vector(4 downto 0);
signal wd3, rd1, rd2: std_logic_vector(31 downto 0);
signal we3, clk: std_logic;
begin
prueba: regfile port map (ra1, ra2, wa3, wd3, we3, clk, rd1, rd2);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
process
begin
we3 <= '1';
wait for 15 ns;
we3 <= '0';
wait for 10 ns;
end process;
process
begin
wd3 <= x"ab120abb";
wait for 5 ns;
wd3 <= x"fff01bba";
wait for 5 ns;
wd3 <= x"abc99fff";
wait for 5 ns;
wd3 <= x"88888999";
wait for 10 ns;
wd3 <= x"66ff1010";
wait for 5 ns;
wd3 <= x"44ff8acc";
wait for 5 ns;
wd3 <= x"67bfaf11";
wait for 5 ns;
end process;
process
begin
wa3 <= "00001";
ra1 <= "00001";
ra2 <= "11111";
wait for 5 ns;
wa3 <= "00010";
ra1 <= "00110";
ra2 <= "00010";
wait for 5 ns;
wa3 <= "11111";
ra1 <= "00010";
ra2 <= "11111";
wait for 5 ns;
wa3 <= "10100";
ra1 <= "10100";
ra2 <= "00011";
wait for 5 ns;
wa3 <= "00011";
ra1 <= "00011";
ra2 <= "10100";
wait for 5 ns;
wa3 <= "00110";
ra1 <= "10100";
ra2 <= "00000";
wait for 5 ns;
end process;
end architecture;
|
gpl-3.0
|
wfjm/w11
|
rtl/w11a/pdp11_bram.vhd
|
1
|
3784
|
-- $Id: pdp11_bram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_bram - syn
-- Description: pdp11: BRAM based ext. memory dummy
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
-- 2008-02-17 117 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.pdp11.all;
entity pdp11_bram is -- cache
generic (
AWIDTH : positive := 14); -- address width
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type -- em response
);
end pdp11_bram;
architecture syn of pdp11_bram is
type regs_type is record
req_r : slbit; -- read request
req_w : slbit; -- write request
be : slv2; -- byte enables
addr : slv(AWIDTH-1 downto 1); -- address
end record regs_type;
constant addrzero : slv(AWIDTH-1 downto 1) := (others=>'0');
constant regs_init : regs_type := (
'0','0', -- req_r,w
(others=>'0'), -- be
addrzero -- addr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal MEM_ENB : slbit := '0';
signal MEM_WEA : slv2 := "00";
signal MEM_DOA : slv16 := (others=>'0');
begin
MEM_BYT0 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(0),
WEB => R_REGS.be(0),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(7 downto 0),
DIB => MEM_DOA(7 downto 0),
DOA => MEM_DOA(7 downto 0),
DOB => open
);
MEM_BYT1 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => AWIDTH-1,
DWIDTH => 8)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => EM_MREQ.req,
ENB => MEM_ENB,
WEA => MEM_WEA(1),
WEB => R_REGS.be(1),
ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
ADDRB => R_REGS.addr,
DIA => EM_MREQ.din(15 downto 8),
DIB => MEM_DOA(15 downto 8),
DOA => MEM_DOA(15 downto 8),
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
N_REGS.req_r <= EM_MREQ.req and not EM_MREQ.we;
N_REGS.req_w <= EM_MREQ.req and EM_MREQ.we;
N_REGS.be <= EM_MREQ.be;
N_REGS.addr <= EM_MREQ.addr(N_REGS.addr'range);
MEM_WEA(0) <= EM_MREQ.we and EM_MREQ.be(0);
MEM_WEA(1) <= EM_MREQ.we and EM_MREQ.be(1);
MEM_ENB <= EM_MREQ.cancel and R_REGS.req_w;
EM_SRES.ack_r <= R_REGS.req_r;
EM_SRES.ack_w <= R_REGS.req_w;
EM_SRES.dout <= MEM_DOA;
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/artys7/tb/artys7_dummy.vhd
|
1
|
1703
|
-- $Id: artys7_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: artys7_dummy - syn
-- Description: artys7 minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_artys7
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-05 1038 1.0 Initial version (cloned from artya7)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity artys7_dummy is -- ARTY S7 dummy (base; loopback)
-- implements artys7_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- artys7 switches
I_BTN : in slv4; -- artys7 buttons
O_LED : out slv4; -- artys7 leds
O_RGBLED0 : out slv3; -- artys7 rgb-led 0
O_RGBLED1 : out slv3 -- artys7 rgb-led 1
);
end artys7_dummy;
architecture syn of artys7_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0
O_RGBLED1 <= (others=>'0');
end syn;
|
gpl-3.0
|
nanomolina/vhdl_examples
|
ROM/test_imem.vhd
|
2
|
727
|
library ieee;
use ieee.std_logic_1164.all;
entity test_imem is
end entity;
architecture arq_test_imem of test_imem is
component imem
port (a: in std_logic_vector(5 downto 0);
y: out std_logic_vector(31 downto 0));
end component;
signal a1: std_logic_vector(5 downto 0):="000000";
signal y1: std_logic_vector(31 downto 0);
begin
prueba0: imem port map (a=>a1, y=>y1);
process
begin
a1 <= "100000";
wait for 5 ns;
a1 <= "000100";
wait for 5 ns;
a1 <= "111000";
wait for 5 ns;
a1 <= "111111";
wait for 5 ns;
a1 <= "110000";
wait for 5 ns;
a1 <= "101010";
end process;
end architecture;
|
gpl-3.0
|
VHDLTool/VHDL_Handbook_CNE
|
Extras/VHDL/CNE_01200_good.vhd
|
1
|
2843
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-14 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : CNE_01200_good.vhd
-- File Creation date : 2015-04-14
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Identification of process label: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CNE_01200_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end CNE_01200_good;
architecture Behavioral of CNE_01200_good is
signal Q : std_logic; -- D Flip-Flop output
begin
--CODE
-- D FlipFlop process
P_FlipFlop:process(i_Clock, i_Reset_n)
begin
if (i_Reset_n='0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
end if;
end process;
--CODE
o_Q <= Q;
end Behavioral;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd
|
1
|
8521
|
-- $Id: sys_tst_rlink_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_s3 - syn
-- Description: rlink tester design for s3board
--
-- Dependencies: vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- bplib/s3board/s3_sram_dummy
--
-- Test bench: tb/tb_tst_rlink_s3
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2016-03-12 743 14.7 131013 xc3s1000e-4 931 2078 128 1383
-- 2014-12-20 614 14.7 131013 xc3s1000e-4 916 1973 128 1316 t 15.9
-- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-19 748 1.2.2 define rlink SYSID
-- 2015-04-11 666 1.2.1 rearrange XON handling
-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2)
------------------------------------------------------------------------------
-- Usage of S3board switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): 1 enable XON
-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(1): timer 1 busy
-- LED(0): timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.s3boardlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_s3 is -- top level
-- implements s3board_fusp_aif
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_rlink_s3;
architecture syn of sys_tst_rlink_s3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"01"; -- s3board
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
CLK <= I_CLK50;
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
SRAM : s3_sram_dummy -- connect SRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd
|
1
|
1757
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;
|
gpl-3.0
|
nanomolina/vhdl_examples
|
ALU/ALU.vhd
|
2
|
1352
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY ALU IS
PORT (a: IN std_logic_vector(31 DOWNTO 0);
b: IN std_logic_vector(31 DOWNTO 0);
alucontrol: IN bit_vector(2 DOWNTO 0);
zero: OUT bit;
result: OUT std_logic_vector(31 DOWNTO 0));
END ALU;
ARCHITECTURE ALU_arq OF ALU IS
BEGIN
PROCESS(a, b, alucontrol)
VARIABLE temp: std_logic_vector(31 DOWNTO 0);
BEGIN
CASE alucontrol IS
WHEN "000" => temp:= a AND b;
WHEN "001" => temp:= a OR b;
WHEN "010" => temp:= std_logic_vector(unsigned(a) + unsigned(b));
WHEN "011" => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
WHEN "100" => temp:= a AND (NOT b);
WHEN "101" => temp:= a OR (NOT b);
WHEN "110" => temp:= std_logic_vector(unsigned(a) - unsigned(b));
WHEN "111" =>
IF a<b THEN
temp := x"00000001";
ELSE
temp := x"00000000";
END IF;
WHEN OTHERS => temp := "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
END CASE;
result <= temp;
IF temp=x"00000000" THEN
zero <= '1';
ELSIF temp=x"00000001" THEN
zero <= '0';
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-3.0
|
nanomolina/vhdl_examples
|
maindec/maindec.vhd
|
6
|
1077
|
library ieee;
use ieee.std_logic_1164.all;
entity maindec is
port (Op: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluOp: out std_logic_vector(1 downto 0));
end entity;
architecture arq_maindec of maindec is
signal parcial_result: std_logic_vector(8 downto 0);
begin
parcial_result <= ("110000010") when (Op = "000000") else
("101001000") when (Op = "100011") else
("001010000") when (Op = "101011") else
("000100001") when (Op = "000100") else
("101000000") when (Op = "001000") else
("000000100") when (Op = "000010") else
("---------");
RegWrite <= parcial_result(8);
RegDst <= parcial_result(7);
AluSrc <= parcial_result(6);
Branch <= parcial_result(5);
MemWrite <= parcial_result(4);
MemToReg <= parcial_result(3);
Jump <= parcial_result(2);
AluOp <= parcial_result(1 downto 0);
end architecture;
|
gpl-3.0
|
nanomolina/vhdl_examples
|
controller/maindec.vhd
|
6
|
1077
|
library ieee;
use ieee.std_logic_1164.all;
entity maindec is
port (Op: in std_logic_vector(5 downto 0);
MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite,
Jump: out std_logic;
AluOp: out std_logic_vector(1 downto 0));
end entity;
architecture arq_maindec of maindec is
signal parcial_result: std_logic_vector(8 downto 0);
begin
parcial_result <= ("110000010") when (Op = "000000") else
("101001000") when (Op = "100011") else
("001010000") when (Op = "101011") else
("000100001") when (Op = "000100") else
("101000000") when (Op = "001000") else
("000000100") when (Op = "000010") else
("---------");
RegWrite <= parcial_result(8);
RegDst <= parcial_result(7);
AluSrc <= parcial_result(6);
Branch <= parcial_result(5);
MemWrite <= parcial_result(4);
MemToReg <= parcial_result(3);
Jump <= parcial_result(2);
AluOp <= parcial_result(1 downto 0);
end architecture;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/sysmon/sysmonx_rbus_arty.vhd
|
1
|
8459
|
-- $Id: sysmonx_rbus_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sysmonx_rbus_arty - syn
-- Description: 7series XADC interface to rbus (arty pwrmon version)
--
-- Dependencies: sysmon_rbus_core
--
-- Test bench: -
--
-- Target Devices: 7series
-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers: see sysmon_rbus_core and XADC user guide
--
-- XADC usage:
-- - build-in sensors: temp, Vccint, Vccaux, Vccbram
-- - arty power monitoring:
-- VAUX( 1) VPWR(0) <- 1/5.99 of JPR5V0 (main 5 V line)
-- VAUX( 2) VPWR(1) <- 1/16 of VU (external power jack)
-- VAUX( 9) VPWR(2) <- 250mV/A from shunt on JPR5V0 (main 5 V line)
-- VAUX(10) VPWR(3) <- 500mV/A from shunt on VCC0V95 (FPGA core)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.rblib.all;
use work.sysmonrbuslib.all;
-- ----------------------------------------------------------------------------
entity sysmonx_rbus_arty is -- XADC interface to rbus (for arty)
generic (
INIT_OT_LIMIT : real := 125.0; -- INIT_53
INIT_OT_RESET : real := 70.0; -- INIT_57
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types)
INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types)
INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := x"fb00");
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12; -- xadc: die temp
VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon)
VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon)
);
end sysmonx_rbus_arty;
architecture syn of sysmonx_rbus_arty is
constant vpwrmap_0 : integer := 1; -- map vpwr(0) -> xadc vaux
constant vpwrmap_1 : integer := 2; -- map vpwr(1) -> xadc vaux
constant vpwrmap_2 : integer := 9; -- map vpwr(2) -> xadc vaux
constant vpwrmap_3 : integer := 10; -- map vpwr(3) -> xadc vaux
constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio
constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16)));
constant init_49 : bv16 := (vpwrmap_0 => '1', -- seq #1: (enable pwrmon)
vpwrmap_1 => '1',
vpwrmap_2 => '1',
vpwrmap_3 => '1',
others => '0');
signal VAUXN : slv16 := (others=>'0');
signal VAUXP : slv16 := (others=>'0');
signal SM_DEN : slbit := '0';
signal SM_DWE : slbit := '0';
signal SM_DADDR : slv7 := (others=>'0');
signal SM_DI : slv16 := (others=>'0');
signal SM_DO : slv16 := (others=>'0');
signal SM_DRDY : slbit := '0';
signal SM_EOS : slbit := '0';
signal SM_EOC : slbit := '0';
signal SM_RESET : slbit := '0';
signal SM_CHAN : slv5 := (others=>'0');
signal SM_ALM : slv8 := (others=>'0');
signal SM_OT : slbit := '0';
signal SM_JTAGLOCKED : slbit := '0';
signal SM_JTAGMODIFIED : slbit := '0';
signal SM_JTAGBUSY : slbit := '0';
begin
SM : XADC
generic map (
INIT_40 => xadc_init_40_default, -- conf #0
INIT_41 => xadc_init_41_default, -- conf #1
INIT_42 => init_42,
INIT_43 => x"0000", -- test #0 - don't use, stay 0
INIT_44 => x"0000", -- test #1 - "
INIT_45 => x"0000", -- test #2 - "
INIT_46 => x"0000", -- test #3 - "
INIT_47 => x"0000", -- test #4 - "
INIT_48 => xadc_init_48_default, -- seq #0: sel 0
INIT_49 => init_49, -- seq #1: sel 1 (enable pwrmon)
INIT_4A => xadc_init_4a_default, -- seq #2: avr 0
INIT_4B => x"0000", -- seq #3: avr 1: "
INIT_4C => x"0000", -- seq #4: mode 0: unipolar
INIT_4D => x"0000", -- seq #5: mode 1: "
INIT_4E => x"0000", -- seq #6: time 0: fast
INIT_4F => x"0000", -- seq #7: time 1: "
INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0)
INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1)
INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2)
INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT
INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0)
INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1)
INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2)
INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT
INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3)
INIT_59 => x"0000", -- alm #09: ccpint up (4)
INIT_5A => x"0000", -- alm #10: ccpaux up (5)
INIT_5B => x"0000", -- alm #11: ccdram up (6)
INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3)
INIT_5D => x"0000", -- alm #13: ccpint low (4)
INIT_5E => x"0000", -- alm #14: ccpaux low (5)
INIT_5F => x"0000", -- alm #15: ccdram low (6)
-- IS_CONVSTCLK_INVERTED => '0',
-- IS_DCLK_INVERTED => '0',
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "sysmon_stim")
port map (
DCLK => CLK,
DEN => SM_DEN,
DWE => SM_DWE,
DADDR => SM_DADDR,
DI => SM_DI,
DO => SM_DO,
DRDY => SM_DRDY,
EOC => SM_EOC, -- connected for tb usage
EOS => SM_EOS,
BUSY => open,
RESET => SM_RESET,
CHANNEL => SM_CHAN, -- connected for tb usage
MUXADDR => open,
ALM => SM_ALM,
OT => SM_OT,
CONVST => '0',
CONVSTCLK => '0',
JTAGBUSY => SM_JTAGBUSY,
JTAGLOCKED => SM_JTAGLOCKED,
JTAGMODIFIED => SM_JTAGMODIFIED,
VAUXN => VAUXN,
VAUXP => VAUXP,
VN => '0',
VP => '0'
);
VAUXN <= (vpwrmap_0 => VPWRN(0),
vpwrmap_1 => VPWRN(1),
vpwrmap_2 => VPWRN(2),
vpwrmap_3 => VPWRN(3),
others=>'0');
VAUXP <= (vpwrmap_0 => VPWRP(0),
vpwrmap_1 => VPWRP(1),
vpwrmap_2 => VPWRP(2),
vpwrmap_3 => VPWRP(3),
others=>'0');
SMRB : sysmon_rbus_core
generic map (
DAWIDTH => 7,
ALWIDTH => 8,
TEWIDTH => 12,
IBASE => x"78",
RB_ADDR => RB_ADDR)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
SM_DEN => SM_DEN,
SM_DWE => SM_DWE,
SM_DADDR => SM_DADDR,
SM_DI => SM_DI,
SM_DO => SM_DO,
SM_DRDY => SM_DRDY,
SM_EOS => SM_EOS,
SM_RESET => SM_RESET,
SM_ALM => SM_ALM,
SM_OT => SM_OT,
SM_JTAGBUSY => SM_JTAGBUSY,
SM_JTAGLOCKED => SM_JTAGLOCKED,
SM_JTAGMODIFIED => SM_JTAGMODIFIED,
TEMP => TEMP
);
ALM <= SM_ALM;
OT <= SM_OT;
end syn;
|
gpl-3.0
|
wfjm/w11
|
rtl/bplib/nexys4d/tb/tb_nexys4d.vhd
|
1
|
4917
|
-- $Id: tb_nexys4d.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4d - sim
-- Description: Test bench for nexys4d (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4d_core
-- serport/tb/serport_master_tb
-- nexys4d_aif [UUT]
--
-- To test: generic, any nexys4d_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
-- 2017-01-04 838 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4dlib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4d is
end tb_nexys4d;
architecture sim of tb_nexys4d is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4d_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4d_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
|
gpl-3.0
|
TierraDelFuego/Open-Source-FPGA-Bitcoin-Miner
|
projects/VHDL_StratixIV_OrphanedGland/sha256/tb/sha256_tb.vhd
|
4
|
3681
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sha256_tb is
end entity sha256_tb;
architecture sha256_tb_behav of sha256_tb is
alias slv is std_logic_vector;
component sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_pc;
component sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_qp;
-- SHA256_SEL = 0 => sha256_pc, uses precalculated H + K + W technique
-- SHA256_SEL = 1 => sha256_qp, uses quasi-pipelining technique
constant SHA256_SEL : natural := 0;
constant tclk_125 : time := 8 ns;
signal clk : std_logic := '0';
signal reset : std_logic;
signal msg_in : slv(511 downto 0) := (others => '0');
signal digest : slv(255 downto 0);
begin
reset <= '1','0' after 12.5 * tclk_125;
sha256_pc_gen: if SHA256_SEL = 0 generate
sha256: sha256_pc
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => msg_in,
digest => digest
);
end generate sha256_pc_gen;
sha256_qp_gen: if SHA256_SEL = 1 generate
sha256: sha256_qp
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => msg_in,
digest => digest
);
end generate sha256_qp_gen;
msg_gen: process is
begin
wait until reset = '0';
-- input message 'abc' after padding
msg_in <= X"00000018" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" &
X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"61626380";
wait for tclk_125;
-- input message 'hello' after padding
msg_in <= X"00000028" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" &
X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"6F800000" & X"68656C6C";
wait for tclk_125;
-- input message 'bitcoin' after padding
msg_in <= X"00000038" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" &
X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"00000000" & X"6F696E80" & X"62697463";
end process msg_gen;
clk_gen: process is
begin
clk <= not clk;
wait for tclk_125/2;
end process clk_gen;
end architecture sha256_tb_behav;
|
gpl-3.0
|
andbet050197/IS773UTP
|
modulo4/Memoria.vhd
|
1
|
864
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Memoria is
port( clk, lectura_escritura, habilitador: in STD_LOGIC;
direccion: in STD_LOGIC_VECTOR(3 downto 0);
dato_entrada: in STD_LOGIC_VECTOR(2 downto 0);
dato_salida: out STD_LOGIC_VECTOR(2 downto 0));
end Memoria;
architecture Behavioral of Memoria is
constant bits_direccion : integer := 4;
constant bits_dato : integer := 3;
type Block_ram is array(2**bits_direccion-1 downto 0) of STD_LOGIC_VECTOR(bits_dato-1 downto 0);
signal RAM: Block_ram;
begin
process(clk)
begin
if clk'event and clk = '1' then
if habilitador = '1' then
if lectura_escritura = '1' then
RAM(conv_integer(direccion)) <= dato_entrada;
else
dato_salida <= RAM(conv_integer(direccion));
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
andbet050197/IS773UTP
|
Latch/LatchSR_AB_HAA.vhd
|
1
|
673
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LatchSR_AB_HAA is
Port ( Sn : in STD_LOGIC;
Rn : in STD_LOGIC;
EN : in STD_LOGIC;
Q : out STD_LOGIC;
Qn : out STD_LOGIC);
end LatchSR_AB_HAA;
architecture Behavioral of LatchSR_AB_HAA is
COMPONENT LatchSR_AA
PORT(
S : IN std_logic;
R : IN std_logic;
Q : OUT std_logic;
Qn : OUT std_logic
);
END COMPONENT;
signal S_aux : std_logic := '0';
signal R_aux : std_logic := '0';
begin
S_aux <= Sn nor (not EN);
R_aux <= Rn nor (not EN);
Inst_LatchSR_AA: LatchSR_AA PORT MAP(
S => S_aux,
R => R_aux,
Q => Q,
Qn => Qn
);
end Behavioral;
|
gpl-3.0
|
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