repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
hiyuh/nvc
|
test/perf/bigram.vhd
|
5
|
3098
|
package util is
function log2(x : in integer) return integer;
end package;
package body util is
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity memory is
generic (
WIDTH : integer;
DEPTH : integer );
port (
clk : in std_logic;
addr : in unsigned(log2(DEPTH) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic );
end entity;
architecture rtl of memory is
type ram_t is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
signal addr_r : unsigned(log2(DEPTH) - 1 downto 0);
signal ram : ram_t;
begin
reg: process (clk) is
begin
if rising_edge(clk) then
addr_r <= addr;
if we = '1' then
ram(to_integer(addr)) <= din;
end if;
end if;
end process;
dout <= ram(to_integer(addr_r));
end architecture;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity bigram is
end entity;
architecture test of bigram is
constant ITERS : integer := 100;
constant WIDTH : integer := 1024;
constant DEPTH : integer := 1024;
signal clk : std_logic := '0';
signal addr : unsigned(log2(DEPTH) - 1 downto 0);
signal din : std_logic_vector(WIDTH - 1 downto 0);
signal dout : std_logic_vector(WIDTH - 1 downto 0);
signal we : std_logic := '1';
signal running : boolean := true;
begin
clk <= not clk after 5 ns when running else '0';
uut: entity work.memory
generic map (
WIDTH => WIDTH,
DEPTH => DEPTH )
port map (
clk => clk,
addr => addr,
din => din,
dout => dout,
we => we );
stim: process is
begin
for j in 1 to ITERS loop
wait for 20 ns;
we <= '1';
for i in 0 to DEPTH - 1 loop
addr <= to_unsigned(i, addr'length);
din <= std_logic_vector(to_unsigned((i + j) mod DEPTH, WIDTH));
wait for 10 ns;
end loop;
we <= '0';
for i in 0 to DEPTH - 1 loop
addr <= to_unsigned(i, addr'length);
wait for 10 ns;
assert dout = std_logic_vector(to_unsigned((i + j) mod DEPTH, WIDTH));
end loop;
end loop;
running <= false;
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/for1.vhd
|
5
|
516
|
entity for1 is
end entity;
architecture test of for1 is
begin
process is
variable x : integer;
begin
for i in 1 to 5 loop
report integer'image(i);
end loop;
for i in 100 downto 95 loop
report integer'image(i);
end loop;
x := -1;
for i in 1 to x loop
null;
end loop;
x := 4;
for i in 5 to x loop
null;
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/for2.vhd
|
5
|
372
|
entity for2 is
end entity;
architecture test of for2 is
type myint is range -1 to 4;
type myenum is (A, B, C, D);
begin
process is
begin
for x in myint loop
report myint'image(x);
end loop;
for y in myenum loop
report myenum'image(y);
end loop;
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/sem/issue53.vhd
|
5
|
175
|
entity c is
port (i : in bit);
begin
assert (i = '0') report "not '0'" severity note; -- OK
assert (i = '1') report "not '1'" severity note; -- OK
end entity c;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/record5.vhd
|
5
|
762
|
entity record5 is
end entity;
architecture test of record5 is
type rec is record
b : bit_vector(1 to 8);
i : integer;
end record;
type rec_array is array (natural range <>) of rec;
function reduce_or(x : bit_vector) return bit is
variable r : bit := '0';
begin
for i in x'range loop
r := r or x(i);
end loop;
return r;
end function;
function foo(a : rec_array) return bit is
begin
return reduce_or(a(0).b);
end function;
begin
process is
variable ra : rec_array(0 to 1) := (
( b => X"05", i => 6 ),
( b => X"1a", i => 1 ) );
begin
assert foo(ra) = '1';
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/issue38.vhd
|
4
|
720
|
package p is
function f (i : bit) return integer;
end package p;
package body p is
function f (i : bit) return integer is
begin
assert f'instance_name = ":work:p:f";
assert f'path_name = ":work:p:f";
return 0;
end function f;
end package body p;
-------------------------------------------------------------------------------
entity issue38 is
begin
end entity issue38;
use work.p.all;
architecture a of issue38 is
function g (i : bit) return integer is
begin
assert g'instance_name = ":issue38(a):g";
assert g'path_name = ":issue38:g";
return 0;
end function g;
begin
assert (f('1') = 0);
assert (g('1') = 0);
end architecture a;
|
gpl-3.0
|
hiyuh/nvc
|
test/elab/libbind3.vhd
|
5
|
481
|
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;
entity binding1 is
end entity;
architecture test of binding1 is
component sub1 is
end component;
begin
sub_i: component sub1;
end architecture;
|
gpl-3.0
|
dobairoland/ZyEHW
|
hw/hdl/parallel_pe_fitness.vhd
|
1
|
5099
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.zyehw_pkg.all;
entity parallel_pe_fitness is
port (
clk: in std_logic;
pe_start: in std_logic;
mux_chromosome_arr: in mux_chromosome_arr_t;
redundant_kernel_pixels: in cgp_input_redundant_t;
correct: in cgp_t;
fitness_arr: out fitness_arr_t;
fitness_wr: out std_logic
);
end parallel_pe_fitness;
architecture struct_parallel_pe_fitness of parallel_pe_fitness is
component pe_array is
generic (
COL: integer;
ROW: integer;
SLICE_X_BASE: integer;
SLICE_Y_BASE: integer;
SLICE_X_STEP: integer;
SLICE_X_COLUMNS: integer
);
port (
clk: in std_logic;
input: in cgp_input_t;
mux_chromosome: in mux_chromosome_t;
filtered: out cgp_t
);
end component;
component fitness_controler is
port (
clk: in std_logic;
pe_start: in std_logic;
fitness_wr: out std_logic;
fitness_en: out std_logic;
fitness_rst: out std_logic
);
end component;
component fitness_unit is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
filtered_pixel: in cgp_t;
correct_data: in cgp_t;
fitness: out fitness_t
);
end component;
component output_pipeline is
generic (
DEPTH: integer
);
port (
clk: in std_logic;
en: in std_logic;
input: in cgp_t;
output: out cgp_t
);
end component;
type filtered_arr_t is array(0 to population-1) of cgp_t;
constant bottom_index: integer:= 0;
constant pe_array_in_row: integer:= 4;
constant always_enabled: std_logic:= '1';
constant output_pipeline_depth: integer:= columns + -- PE columns
columns + -- PE mux columns
1; -- output stage
signal delayed_reference: cgp_t;
signal filtered_arr: filtered_arr_t;
signal fitness_en: std_logic;
signal fitness_rst: std_logic;
begin
parallel_pe_array: for i in 0 to population-1 generate
bottom_row: if i < pe_array_in_row generate
pe_array_i: pe_array
generic map (
COL => columns,
ROW => rows,
SLICE_X_BASE => 1 + 32*i,
SLICE_Y_BASE => ((bottom_index+1) * slice_per_row) - 1,
SLICE_X_STEP => 10,
SLICE_X_COLUMNS => 2
)
port map (
clk => clk,
input => redundant_kernel_pixels(i),
mux_chromosome => mux_chromosome_arr(i),
filtered => filtered_arr(i)
);
end generate;
right_column: if i >= pe_array_in_row generate
pe_array_i: pe_array
generic map (
COL => columns,
ROW => rows,
SLICE_X_BASE => 97,
SLICE_Y_BASE =>
((i-pe_array_in_row+2)*(bottom_index+1)*slice_per_row) - 1,
SLICE_X_STEP => 10,
SLICE_X_COLUMNS => 2
)
port map (
clk => clk,
input => redundant_kernel_pixels(i),
mux_chromosome => mux_chromosome_arr(i),
filtered => filtered_arr(i)
);
end generate;
fitness_unit_i: fitness_unit
port map (
clk => clk,
rst => fitness_rst,
en => fitness_en,
filtered_pixel => filtered_arr(i),
correct_data => delayed_reference,
fitness => fitness_arr(i)
);
end generate;
output_pipeline_i: output_pipeline
generic map (
DEPTH => output_pipeline_depth
)
port map (
clk => clk,
en => always_enabled,
input => correct,
output => delayed_reference
);
fitness_controler_i: fitness_controler
port map (
clk => clk,
pe_start => pe_start,
fitness_wr => fitness_wr,
fitness_en => fitness_en,
fitness_rst => fitness_rst
);
end struct_parallel_pe_fitness;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/signal6.vhd
|
5
|
316
|
entity signal6 is
end entity;
architecture test of signal6 is
signal x : integer := 0;
begin
process is
begin
x <= 1, 2 after 3 ns, 4 after 5 ns, 8 after 9 ns;
wait;
end process;
process (x) is
begin
report integer'image(x);
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/operator2.vhd
|
5
|
859
|
entity operator2 is
end entity;
architecture test of operator2 is
type t is (A, B);
type tv is array (integer range <>) of t;
function "and"(x, y : t) return t is
begin
if x = y then
return A;
else
return B;
end if;
end function;
function "and"(x, y : tv) return tv is
variable tmp : tv(x'range);
begin
for i in x'range loop
tmp(i) := x(i) and y(i);
end loop;
return tmp;
end function;
begin
process is
variable x, y : t;
variable xv, yv : tv(1 to 2);
begin
x := A;
y := A;
assert (x and y) = A;
y := B;
assert (x and y) = B;
xv := (A, B);
yv := (B, B);
assert (xv and yv) = (B, A);
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/record6.vhd
|
3
|
1261
|
entity record6 is
end entity;
architecture test of record6 is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
type rec_array is array (natural range <>) of rec;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
end function;
function make_rec_array(x : rec; l, r : natural) return rec_array is
variable ra : rec_array(l to r) := (others => x);
begin
return ra;
end function;
function get_bit(v : in rec) return bit is
begin
return v.x(v.y);
end function;
begin
process is
variable r : rec;
begin
r.x := "101";
r.y := 1;
assert get_bit(r) = '1';
r.y := 2;
assert get_bit(r) = '0';
assert get_bit(make_rec("011", 2)) = '1';
r.x := make_rec("010", 1).x;
assert r.x = "010";
r.y := make_rec("010", 1).y;
assert r.y = 1;
r := make_rec("010", 1);
assert make_rec_array(r, 1, 2) = ( ("010", 1), ("010", 1) );
assert make_rec_array(("111", 5), 1, 2) = ( ("111", 5), ("111", 5) );
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/sem/integer.vhd
|
4
|
1456
|
entity b is
end entity;
architecture a of b is
type my_int1 is range 0 to 10;
type my_int2 is range -20 to 30;
signal x : my_int1 := 2;
begin
process is
variable z : my_int1;
begin
z := x;
end process;
process is
variable y : my_int2;
begin
-- Should generate error as my_int1 and my_int2 incompatible
y := x;
end process;
process is
subtype my_int2_sub is my_int2 range 0 to 10;
variable yy : my_int2_sub;
begin
yy := 6; -- OK
-- Should fail even though the range is the same
yy := x;
end process;
process is
-- Base type is undefined
subtype bad is nothing range 1 to 2;
begin
end process;
process is
subtype my_int2_same is my_int2;
subtype another_one is my_int2_same range 0 to 10;
variable yyy : another_one;
variable foo : my_int2 range 0 to 10;
begin
yyy := foo; -- OK
yyy := foo * 2; -- OK
yyy := 5 * (2 + 4) / 2; -- OK
yyy := (yyy + 5) * x + 2; -- Cannot convert my_int1 to my_int2
end process;
process is
variable b : my_int2 := my_int2'left;
begin
b := my_int2'low;
b := my_int2'high;
b := my_int2'right;
b := my_int2'cake; -- Error
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/sem/attr.vhd
|
3
|
4179
|
entity e is
end entity;
architecture a1 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of x : signal is 6; -- OK
attribute bar of y : signal is "hello"; -- OK
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
signal i : int_vec(1 to 3);
attribute foo of i : signal is 6; -- OK
begin
process is
variable v : integer;
begin
v := x'foo; -- OK
report y'bar; -- OK
end process;
process is
begin
report z'foo; -- Error
end process;
process is
variable v : int_vec_ptr;
begin
assert v'length = 5;
assert v.all'length = 62;
end process;
process is
begin
report e'path_name; -- OK
report e'instance_name; -- OK
report a1'path_name; -- OK
report a1'instance_name; -- OK
end process;
process is
begin
assert i'event; -- OK
assert i(1)'event; -- OK
assert i(x)'event; -- OK
assert i'foo = 1; -- OK
assert i(1)'foo = 2; -- Error
end process;
end architecture;
architecture a2 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of z : signal is string'("boo"); -- Error
attribute bar of x : signal is 73; -- Error
attribute foo of q : signal is 71; -- Error
attribute foo of yah : label is 12; -- Ignored
begin
end architecture;
architecture a3 of e is
type int10_vec is array (integer range 1 to 10) of integer;
begin
process is
variable x : integer;
begin
assert int10_vec'low = 1; -- OK
assert int10_vec'high = 10; -- OK
assert int10_vec'left = 1; -- OK
assert int10_vec'right = 10; -- OK
assert int10_vec'low(1) = 1; -- OK
assert int10_vec'left(x) = 2; -- Error
end process;
end architecture;
package p is
function func(x : in integer) return integer;
end package;
package body p is
function func(x : in integer) return integer is
begin
report func'instance_name;
return x + 1;
end function;
end package body;
entity issue39 is
generic (
g : bit := '0'
);
begin
assert (g = '0' or g = '1')
report issue39'instance_name & "oops!"
severity failure;
end entity issue39;
architecture a4 of e is
begin
process is
begin
assert integer'image(0)(0) = '0'; -- OK
end process;
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
attribute b : integer;
attribute b of i : variable is 4;
begin
assert i'a(1) = '0'; -- OK
assert i'b(1) = 1; -- Error
end process;
process is
variable i : integer;
attribute a : boolean;
attribute a of i : signal is true; -- Error
begin
end process;
process is
variable x : integer;
begin
assert x'last_event = 0 ns; -- Error
end process;
process is
type bv_ptr is access bit_vector;
variable a : bv_ptr;
type r is record
x : integer;
end record;
variable b : r;
begin
a(a'range) := "110101"; -- OK
a(bit_vector'range) := "110101"; -- Error
a(b'range) := "101010"; -- Error
a(e'range) := "110101"; -- Error
end process;
process is
function func(x : integer) return bit_vector;
variable a : bit_vector(1 to 10);
begin
a(func(4)'range) := (others => '1'); -- OK
end process;
process is
type bvptr is access bit_vector;
variable b : bvptr;
begin
for i in b.all'range loop -- OK
end loop;
for i in b'range loop -- OK
end loop;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/proc9.vhd
|
4
|
416
|
entity proc9 is
end entity;
architecture test of proc9 is
procedure foo (x : in integer; y : out bit_vector) is
constant c : bit_vector(1 to x) := (others => '1');
begin
wait;
y := c;
end procedure;
begin
process is
variable b : bit_vector(1 to 5);
begin
foo(5, b);
assert b = (1 to 5 => '1');
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/attr12.vhd
|
4
|
511
|
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name;
report iname;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity attr12 is
end entity;
use work.pack.all;
architecture test of attr12 is
begin
process is
begin
proc;
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/lower/attr1.vhd
|
4
|
503
|
entity attr1 is
end entity;
architecture test of attr1 is
type my_int is range 10 downto 0;
begin
process is
variable x : integer := 0;
variable y : my_int;
variable z : integer := 1;
begin
assert integer'succ(x) = 1;
assert integer'pred(x) = -1;
assert integer'leftof(z) = 0;
assert integer'rightof(z) = 2;
assert my_int'leftof(y) = 2;
assert my_int'rightof(y) = 0;
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/sem/static.vhd
|
2
|
1923
|
entity static is
generic ( G : integer := 1 );
end entity;
architecture test of static is
begin
process is
subtype byte is bit_vector(7 downto 0);
variable bv : byte;
variable i : integer;
attribute hello : integer;
attribute hello of bv : variable is 6;
begin
case i is
when bv'length => -- OK
null;
when bv'left => -- OK
null;
when byte'right => -- OK
null;
when bv'hello => -- OK
null;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(3 downto 0);
constant c : bit_vector := "1010";
constant d : bit_vector(G downto 0) := (others => '0');
begin
case v is
when c => -- Error
null;
when others =>
null;
end case;
case v is
when d => -- Error
null;
when others =>
null;
end case;
end process;
end architecture;
-------------------------------------------------------------------------------
entity sub is
generic ( N : integer );
port ( x : bit_vector );
end entity;
architecture test of sub is
signal y : bit_vector(N - 1 downto 0) := (others => '0') ;
begin
sub_i: entity work.sub
generic map ( N => N )
port map (
x => x(x'left downto x'right) ); -- Error
gen1: for i in y'range generate -- OK
end generate;
b1: block is
type r is record
x, y : integer;
end record;
signal x : r := (1, 2);
begin
gen2: if (N, 2) = r'(1, 2) generate -- OK
end generate;
end block;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/lower/loop2.vhd
|
5
|
252
|
entity loop2 is
end entity;
architecture test of loop2 is
procedure p3(t : in time) is
begin
loop
if t >= 1 ps then
return;
end if;
end loop;
end procedure;
begin
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/simp/cfold.vhd
|
3
|
2672
|
entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5);
constant a3 : int_array(1 to 9) := (8 => 24, others => 0);
constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5);
constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1);
begin
process is
variable b : boolean;
begin
x <= c / 2;
y <= t'high;
y <= t'left;
b := t'right = 8;
b := (t'right - t'left) = 2;
b := t'high /= 2;
b := true and true;
b := true and false;
b := true or false;
b := true xor true;
b := not true;
b := not false;
b := true xnor false;
b := false nand false;
b := false nor true;
b := 7 > 5 and 6 < 2;
x <= a1(2);
x <= a2(1);
x <= a2(3);
x <= a3(8);
x <= a1'length;
x <= a4(2);
x <= a5(4);
x <= 2 ** 4;
end process;
process is
begin
if true then
x <= 1;
end if;
if false then
x <= 5;
end if;
if false then
null;
else
x <= 5;
end if;
while false loop
null;
end loop;
if true then
x <= 1;
x <= 5;
null;
end if;
end process;
process is
variable r : real;
variable b : boolean;
begin
r := 1.0 + 0.0;
r := 1.5 * 4.0;
r := 2.0 / 2.0;
b := 4.6 > 1.2;
end process;
process
variable k : time;
begin
end process;
process
type int2_vec is array (66 to 67) of integer;
begin
assert a1'length = 5;
assert a1'low(1) = 1;
assert a1'high(1) = 5;
assert a1'left = 1;
assert a1'right = 5;
assert int2_vec'length = 2;
assert int2_vec'low = 66;
end process;
process is
begin
case 1 is
when 1 => null;
when others => report "bang";
end case;
end process;
process is
variable r : real;
begin
r := 1.5 * 2;
r := 3 * 0.2;
r := 5.0 / 2;
end process;
process is
constant one : bit := '1';
variable b : boolean;
begin
b := one = '1';
b := '0' /= one;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/elab/issue153.vhd
|
5
|
290
|
entity issue153 is
end entity;
architecture test of issue153 is
signal s, t : bit_vector(7 downto 0);
begin
g1: for i in s'range generate
s(i) <= s(i - 1);
end generate;
g2: for i in s'range generate
t(i - 1) <= s(i);
end generate;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/parse/loc.vhd
|
4
|
86
|
architecture a of e is
begin
f(1, 2, 3 + 5);
assert x'attr;
end architecture;
|
gpl-3.0
|
dobairoland/ZyEHW
|
hw/hdl/test/img_pkg.vhd
|
1
|
656361
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.zyehw_pkg.all;
package img_pkg is
type test_img_t is array (0 to img_pixels-1) of cgp_t;
constant test_correct_image: test_img_t:= (
"00010111",
"00011001",
"00011010",
"00101101",
"10110100",
"10111110",
"10111101",
"10011001",
"01010000",
"01111000",
"10010010",
"10011111",
"10100001",
"10100011",
"10011110",
"01000000",
"00100010",
"00010011",
"00010110",
"00011010",
"00100000",
"00101111",
"00100110",
"00101011",
"00101010",
"00100110",
"01100001",
"00100110",
"00011111",
"00110011",
"00111000",
"00110001",
"01000011",
"01000001",
"01001111",
"00110000",
"00010000",
"00101010",
"00110001",
"00010110",
"00110100",
"00100011",
"01011010",
"00100111",
"00101101",
"00110100",
"00111010",
"01000110",
"01001100",
"01010001",
"01010110",
"01010111",
"01011001",
"01011101",
"01011100",
"01011100",
"01011100",
"01011110",
"01100001",
"01011101",
"01011111",
"01100110",
"01100110",
"01011111",
"01100010",
"01100111",
"01101010",
"01101001",
"01110000",
"01101111",
"01110000",
"01101110",
"01110010",
"01110001",
"01110111",
"01110101",
"01110111",
"01110111",
"01111001",
"01110111",
"10000010",
"10000000",
"10000101",
"10001101",
"10001110",
"10010011",
"10011010",
"10100110",
"10101111",
"10110100",
"10111000",
"10111110",
"11000011",
"11000110",
"11001110",
"10011000",
"01000001",
"01000101",
"01000000",
"01001110",
"01010011",
"01011111",
"01101000",
"01011110",
"01011011",
"01011010",
"01101010",
"01101010",
"01010110",
"00111110",
"00111100",
"00110010",
"00110000",
"00111110",
"01000000",
"00111000",
"00111101",
"01010110",
"01101011",
"01101000",
"01001111",
"00101010",
"00011011",
"00010010",
"00011000",
"00101011",
"01000001",
"01000101",
"00011011",
"00011100",
"00011110",
"00111110",
"10111000",
"11000010",
"11000000",
"10100000",
"01001101",
"01110110",
"10010110",
"10011101",
"10011111",
"10100100",
"10011001",
"01100001",
"00100010",
"00010110",
"00010111",
"00011101",
"00100110",
"00011111",
"00100001",
"00110010",
"00011101",
"00110100",
"00011111",
"01010011",
"00010001",
"00110101",
"00111100",
"00110111",
"01110101",
"00000100",
"01001001",
"00110000",
"00100000",
"00110101",
"00110001",
"00100010",
"01001100",
"01100000",
"00100101",
"00000101",
"00010010",
"00101000",
"00110111",
"01000110",
"01001011",
"01001101",
"01010101",
"01010011",
"01010110",
"01011110",
"01011010",
"01011100",
"01100000",
"01011110",
"01100001",
"01011100",
"01100100",
"01100101",
"01100011",
"01100010",
"01101100",
"01101000",
"01100111",
"01101011",
"01101110",
"01110010",
"01110000",
"01101111",
"01110011",
"01110010",
"01110110",
"01110110",
"01110011",
"01110010",
"01111000",
"01111100",
"01111100",
"01111110",
"10001000",
"10001101",
"10001101",
"10011100",
"10011110",
"10101010",
"10110000",
"10110110",
"10111110",
"11000010",
"11000111",
"11001001",
"11010010",
"01100110",
"00110011",
"01000110",
"01001100",
"01001111",
"01011101",
"01011100",
"01011101",
"01011100",
"01010011",
"01010001",
"01010010",
"01011100",
"01011100",
"01001001",
"00111101",
"01001001",
"00111111",
"00111000",
"00111010",
"00111000",
"00110000",
"01000111",
"01100100",
"01101001",
"01011010",
"01000110",
"00101010",
"00011010",
"00011000",
"00100010",
"00100111",
"00111001",
"00011101",
"00011011",
"00100100",
"00111110",
"10101010",
"11000110",
"11000011",
"10000001",
"01010001",
"01111000",
"10010110",
"10011101",
"10100010",
"10100110",
"10011011",
"01001000",
"00011101",
"00011001",
"00011110",
"00010110",
"00011000",
"00100001",
"00011110",
"00101001",
"00100010",
"00100111",
"00010011",
"01100000",
"00010010",
"00101001",
"01000000",
"01100111",
"00111100",
"00010111",
"01010101",
"00011110",
"00010101",
"01010111",
"00011000",
"00110100",
"01010011",
"00100001",
"00001111",
"00010100",
"00010110",
"00010101",
"00101111",
"00111111",
"01001010",
"01001111",
"01010010",
"01010001",
"01011000",
"01011010",
"01011011",
"01011001",
"01011110",
"01100001",
"01011110",
"01100000",
"01100011",
"01100010",
"01101000",
"01100101",
"01100110",
"01101001",
"01101010",
"01101010",
"01110000",
"01101100",
"01110010",
"01110011",
"01110001",
"01110011",
"01110011",
"01110001",
"01110100",
"01110010",
"01110111",
"01110111",
"01111010",
"10000001",
"10000111",
"10001110",
"10010100",
"10011101",
"10100011",
"10101010",
"10101111",
"10111011",
"10111111",
"11000100",
"11001000",
"11001001",
"11010101",
"00111001",
"00111011",
"01001001",
"01001111",
"01010101",
"01011110",
"01100010",
"01011011",
"01010101",
"01010100",
"01010000",
"01001001",
"01001001",
"01010110",
"01001110",
"00111101",
"00111011",
"01001000",
"01000101",
"00101111",
"00101010",
"00101011",
"00110011",
"01001011",
"01100001",
"01100110",
"01010010",
"00111110",
"00101000",
"00100000",
"00011111",
"00011010",
"00100001",
"00100001",
"00100011",
"00110100",
"01001010",
"10010101",
"10110010",
"10100100",
"01100101",
"01001011",
"01110110",
"10010110",
"10011111",
"10100010",
"10100101",
"10011011",
"01101010",
"00100011",
"00100100",
"00010110",
"00011011",
"00010101",
"00100100",
"00100010",
"00011111",
"00111011",
"00010001",
"00010110",
"01000100",
"00001110",
"00100011",
"01000010",
"01101011",
"00000101",
"00110100",
"01011100",
"00000111",
"00110100",
"01000000",
"00110000",
"01100101",
"01000000",
"00101101",
"00001110",
"00011001",
"00001111",
"00010001",
"00011001",
"00101101",
"00111010",
"01001101",
"01001100",
"01010010",
"01010111",
"01011001",
"01011010",
"01011100",
"01011110",
"01011100",
"01011010",
"01100011",
"01100110",
"01100100",
"01100010",
"01101001",
"01101001",
"01101001",
"01101010",
"01101011",
"01110000",
"01110000",
"01101110",
"01110010",
"01101111",
"01110100",
"01101110",
"01101110",
"01101101",
"01110010",
"01110101",
"01110110",
"01111011",
"01111111",
"10000110",
"10001110",
"10010100",
"10011101",
"10100011",
"10101110",
"10110101",
"10111001",
"11000001",
"11001001",
"11001000",
"11001101",
"11000011",
"00100100",
"01000000",
"01001010",
"01010001",
"01011001",
"01011000",
"01011011",
"01011111",
"01010100",
"01010100",
"01001010",
"01000111",
"01000000",
"01000111",
"01001011",
"00111100",
"00110000",
"00111000",
"01001011",
"00111110",
"00110000",
"00110001",
"00101100",
"00110001",
"01010100",
"01011111",
"01011101",
"01010000",
"00110011",
"00100010",
"00011111",
"00011011",
"00011000",
"00011000",
"00101100",
"01000001",
"01011011",
"10011001",
"10101000",
"10010110",
"01011000",
"01001011",
"01110110",
"10010101",
"10011110",
"10100001",
"10100111",
"10011000",
"01111010",
"00100111",
"00010010",
"00010011",
"00011101",
"00011000",
"00100101",
"00011110",
"00011010",
"00110110",
"00010110",
"00100000",
"00111101",
"00010101",
"00101111",
"01100001",
"01000001",
"00010011",
"01000001",
"00100111",
"00010110",
"01010000",
"00100100",
"01010000",
"01011000",
"01100010",
"00100101",
"00010011",
"00011001",
"00010110",
"00010010",
"00001110",
"00010011",
"00011010",
"00101110",
"00110110",
"01000010",
"01010010",
"01010110",
"01011001",
"01011101",
"01011110",
"01011100",
"01011110",
"01100011",
"01100001",
"01100110",
"01100111",
"01100100",
"01101011",
"01101001",
"01101010",
"01101111",
"01110000",
"01110011",
"01101110",
"01101111",
"01101110",
"01101101",
"01101010",
"01101110",
"01101011",
"01101111",
"01110100",
"01111001",
"01111111",
"10000100",
"10001001",
"10001110",
"10011101",
"10100100",
"10101010",
"10110010",
"10111000",
"11000000",
"11000100",
"11001011",
"11001011",
"11010001",
"10010010",
"00110000",
"01000011",
"01001011",
"01010001",
"01010101",
"01001111",
"01010001",
"01011000",
"01010110",
"01001110",
"01010110",
"01011010",
"00111001",
"00110101",
"00110110",
"00111001",
"00110001",
"00101000",
"01000000",
"01010010",
"01000111",
"00101110",
"00100101",
"00100011",
"01000101",
"01010101",
"01011111",
"01010101",
"01000101",
"00101010",
"00100010",
"00100010",
"00011001",
"00011110",
"01001001",
"01001100",
"01100111",
"10011110",
"10101100",
"10010101",
"01001000",
"01001011",
"01111010",
"10010111",
"10011110",
"10100001",
"10100101",
"10011001",
"01100110",
"01000110",
"00011101",
"00010011",
"00011101",
"00011101",
"00011111",
"00011000",
"00010111",
"00101110",
"00010110",
"00100000",
"01000000",
"00100001",
"00101111",
"01010010",
"00100000",
"00010010",
"00111111",
"00001100",
"01000110",
"00110000",
"00100100",
"01000001",
"10000101",
"00101010",
"00101010",
"00001100",
"00011001",
"00010011",
"00010001",
"00010011",
"00011101",
"00100100",
"00010011",
"00010101",
"00011110",
"00110111",
"01000111",
"01010010",
"01011000",
"01011000",
"01100001",
"01011110",
"01100110",
"01100110",
"01100101",
"01101000",
"01101000",
"01100111",
"01101110",
"01101100",
"01101111",
"01110100",
"01110010",
"01110001",
"01101100",
"01101110",
"01101000",
"01101011",
"01101011",
"01101101",
"01110001",
"01110110",
"01111010",
"01111111",
"10000101",
"10001010",
"10010101",
"10011011",
"10100001",
"10101101",
"10110101",
"10111101",
"11000011",
"11000110",
"11001001",
"11001100",
"11010011",
"01100011",
"00111100",
"01001001",
"01001101",
"01010000",
"01001100",
"01001101",
"01000101",
"01001010",
"01001010",
"00111111",
"10000111",
"10110111",
"01111100",
"00110001",
"00110010",
"00100110",
"00110000",
"00101110",
"00101101",
"01001000",
"01011001",
"01000011",
"00110011",
"00100101",
"00101100",
"01001001",
"01011011",
"01010100",
"01001011",
"00110000",
"00100100",
"00101011",
"00100010",
"00110001",
"01010100",
"01011111",
"01111000",
"10100101",
"10101001",
"10010100",
"01000101",
"01001101",
"01111101",
"10010111",
"10011100",
"10011111",
"10101000",
"10011001",
"01010110",
"01100000",
"00100101",
"00010101",
"00011010",
"00011100",
"00011001",
"00011001",
"00100001",
"00011001",
"00010011",
"00011110",
"00111010",
"00100011",
"00110011",
"00110101",
"00010011",
"00010111",
"01000011",
"00100000",
"00110011",
"00100101",
"00110100",
"01001101",
"01011011",
"00100011",
"00110111",
"00010011",
"00010100",
"00010100",
"00001111",
"00001011",
"00010110",
"00110000",
"01000001",
"01000100",
"00110001",
"00001011",
"00011001",
"01000000",
"01010000",
"01011001",
"01011101",
"01100000",
"01100101",
"01100110",
"01101000",
"01101000",
"01101011",
"01101000",
"01101010",
"01101101",
"01101101",
"01101110",
"01101101",
"01101100",
"01101100",
"01101011",
"01101011",
"01100111",
"01101000",
"01101110",
"01110100",
"01110100",
"01111100",
"10000010",
"10001001",
"10010000",
"10001111",
"10011011",
"10101000",
"10101111",
"10111001",
"10111111",
"11000100",
"11001000",
"11001010",
"11001101",
"11010111",
"00110101",
"01000101",
"01001101",
"01001110",
"01001100",
"01001001",
"01000110",
"00111010",
"00111001",
"00111010",
"00111001",
"10011100",
"11010000",
"11000000",
"01111000",
"00111000",
"00011101",
"00011010",
"00101100",
"00100111",
"00101011",
"01000101",
"01010000",
"01000010",
"00101101",
"00101111",
"00111010",
"01010100",
"01010101",
"01001000",
"01000001",
"00101010",
"00101001",
"00100110",
"00111101",
"01000010",
"01010010",
"01111111",
"10100111",
"10110001",
"10010110",
"00111101",
"01001011",
"01111110",
"10010111",
"10011110",
"10011110",
"10100110",
"10011110",
"01011001",
"01011011",
"00110001",
"00010110",
"00010101",
"00010100",
"00010110",
"00010011",
"00100001",
"00011101",
"00010111",
"00010010",
"00100110",
"00100100",
"00100010",
"00100100",
"00010111",
"00011100",
"00100010",
"00100001",
"00100101",
"00101011",
"00100110",
"00110000",
"01010100",
"01111101",
"00011100",
"00010110",
"00010101",
"00010110",
"00010011",
"00001011",
"00010011",
"00011110",
"00101101",
"01000001",
"01010111",
"01010101",
"00011111",
"00001001",
"00110101",
"01011000",
"01011011",
"01011111",
"01100110",
"01100101",
"01101001",
"01101000",
"01101001",
"01100111",
"01101001",
"01101111",
"01101001",
"01110000",
"01101010",
"01101011",
"01100110",
"01100111",
"01101010",
"01101101",
"01101010",
"01110010",
"01110100",
"01111000",
"01111100",
"10000110",
"10001100",
"10001010",
"10011010",
"10100011",
"10101101",
"10110100",
"10111101",
"11000011",
"11000110",
"11001001",
"11001000",
"11001110",
"10110101",
"00101110",
"01001010",
"01010011",
"01010010",
"01000111",
"01000110",
"00111011",
"00110001",
"00101000",
"00011001",
"00100100",
"10011001",
"11000010",
"10111010",
"10110101",
"10011111",
"01000100",
"00010100",
"00011000",
"00101001",
"00100010",
"00110000",
"01001001",
"01001010",
"00111000",
"00101111",
"00110010",
"01000001",
"01011000",
"01001110",
"01000001",
"00110101",
"00100000",
"00101011",
"01000001",
"00111011",
"01000000",
"01110000",
"10101000",
"10110000",
"10001100",
"00110011",
"01001100",
"01111111",
"10010111",
"10011111",
"10011011",
"10101000",
"10011000",
"01100011",
"01011011",
"00110101",
"00001110",
"00011100",
"00100110",
"00011001",
"00010110",
"00011010",
"00011011",
"00011011",
"00101000",
"00011110",
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"10000011",
"10000001",
"01111110",
"10000101",
"10001101",
"10010000",
"10001111",
"10001100",
"10001100",
"01111110",
"01101100",
"01010010",
"00111000",
"00111001",
"01000000",
"01000001",
"01000111",
"01001011",
"01000101",
"01001000",
"01000100",
"01000100",
"01001110",
"01010010",
"01010110",
"01011000",
"01011100",
"01011100",
"01011111",
"01100001",
"01011111",
"01100011",
"01100001",
"01100011",
"01100011",
"01100001",
"01100010",
"01100011",
"01100011",
"01100100",
"01100111",
"01100010",
"01100011",
"01100011",
"01011111",
"01100110",
"01100010",
"01100101",
"01100011",
"01100011",
"01100101",
"01100000",
"01100001",
"01100101",
"01011111",
"01100010",
"01100111",
"01101001",
"01100011",
"01100011",
"01100100",
"01100011",
"01100011",
"01011101",
"01100001",
"01100010",
"01011100",
"01011110",
"01100001",
"01100001",
"01011110",
"01100001",
"01100000",
"01011010",
"01010001",
"01010101",
"01001110",
"01000101",
"01010110",
"01101111",
"01111010",
"10000011",
"10001011",
"10001000",
"10000110",
"10001010",
"10001001",
"10001010",
"10000011",
"10000111",
"10000010",
"01111111",
"01111110",
"10000000",
"01111100",
"01111110",
"01111110",
"01111010",
"10000011",
"11000011",
"11010010",
"11010101",
"11010010",
"10001110",
"01000011",
"01001101",
"01010110",
"01010101",
"01011010",
"01011010",
"01011111",
"01011100",
"01011111",
"01011110",
"01011111",
"01011111",
"01100011",
"01100100",
"01101001",
"00111111",
"00010000",
"00010001",
"00011001",
"00010010",
"10000011",
"10000010",
"10000011",
"10000000",
"10000001",
"10000001",
"01111111",
"10000000",
"10001001",
"10010000",
"10010011",
"10010001",
"10001110",
"10000011",
"01101010",
"01010000",
"00111010",
"00111011",
"00111111",
"01000101",
"01001001",
"01001011",
"01001001",
"01000101",
"01000101",
"01000110",
"01001111",
"01010011",
"01010100",
"01011010",
"01011100",
"01011101",
"01011100",
"01011111",
"01100000",
"01100100",
"01100010",
"01100000",
"01100000",
"01100011",
"01100001",
"01100010",
"01100011",
"01100100",
"01100000",
"01100011",
"01100100",
"01100001",
"01100001",
"01100011",
"01100010",
"01100001",
"01100011",
"01100011",
"01100000",
"01100001",
"01100011",
"01100010",
"01011110",
"01100011",
"01100110",
"01100101",
"01100010",
"01100100",
"01100010",
"01100001",
"01100011",
"01100010",
"01100000",
"01011111",
"01100000",
"01100001",
"01011101",
"01100000",
"01100000",
"01100000",
"01011100",
"01011010",
"01010010",
"01010011",
"01001011",
"01001010",
"01100001",
"01110011",
"01111101",
"10000111",
"10000111",
"10000110",
"10000100",
"10001000",
"10001010",
"10000100",
"10000011",
"10000000",
"10000010",
"10000000",
"10000000",
"01111110",
"01111101",
"01111111",
"01111111",
"01111000",
"10101110",
"11001100",
"11010100",
"11010111",
"10110110",
"01010001",
"01001110",
"01010000",
"01010111",
"01011001",
"01011001",
"01011100",
"01011000",
"01011011",
"01011010",
"01011010",
"01011101",
"01011100",
"01011111",
"01011110",
"01100000",
"01101010",
"01000111",
"00011100",
"00010010",
"00011010",
"10000011",
"01111110",
"10000100",
"10000010",
"10000001",
"10000000",
"01111110",
"01111111",
"01111111",
"10001100",
"10010001",
"10010101",
"10010011",
"10000110",
"01101100",
"01010010",
"00111000",
"00110111",
"01000010",
"01000010",
"01000101",
"01000110",
"01001001",
"01000101",
"01000110",
"01001010",
"01001110",
"01010010",
"01010111",
"01011011",
"01011100",
"01011111",
"01011110",
"01100000",
"01100001",
"01100001",
"01100010",
"01100001",
"01100010",
"01100011",
"01100001",
"01100110",
"01100100",
"01100011",
"01100101",
"01100010",
"01100101",
"01100011",
"01100011",
"01100010",
"01100010",
"01100001",
"01100001",
"01100011",
"01100001",
"01011110",
"01100011",
"01100101",
"01011111",
"01100010",
"01100010",
"01100011",
"01100000",
"01100000",
"01100010",
"01100011",
"01100001",
"01011111",
"01011111",
"01100000",
"01011110",
"01011110",
"01100000",
"01100000",
"01011111",
"01011110",
"01011101",
"01010111",
"01010010",
"01001101",
"01000111",
"01010100",
"01101001",
"01111000",
"10000001",
"10001000",
"10000000",
"01111110",
"10000011",
"10000010",
"10000001",
"10000010",
"10000010",
"01111111",
"10000001",
"01111110",
"10000001",
"01111111",
"10000000",
"01111111",
"01111101",
"10001111",
"11000110",
"11010001",
"11010100",
"11001101",
"01110101",
"01000110",
"01010000",
"01010110",
"01011011",
"01011011",
"01011011",
"01011010",
"01011000",
"01011011",
"01011100",
"01011100",
"01011101",
"01011100",
"01011101",
"01011110",
"01011101",
"01100011",
"01100101",
"01001011",
"00010101",
"00010001",
"10000110",
"10000100",
"10000110",
"01111110",
"10000010",
"01111110",
"10000001",
"01111111",
"10000000",
"10001000",
"10010000",
"10010110",
"10010101",
"10001001",
"01110001",
"01010010",
"00111010",
"00111100",
"01000001",
"01001100",
"01000111",
"01001000",
"01000110",
"01001001",
"01001001",
"01001000",
"01001101",
"01010101",
"01011000",
"01011100",
"01011100",
"01011100",
"01100010",
"01100010",
"01100100",
"01100010",
"01100010",
"01100100",
"01100001",
"01100100",
"01100100",
"01100111",
"01100011",
"01100101",
"01100100",
"01100010",
"01100011",
"01100011",
"01100110",
"01100100",
"01100110",
"01100100",
"01101000",
"01100101",
"01100100",
"01100010",
"01100100",
"01100101",
"01100010",
"01100011",
"01100101",
"01100101",
"01100011",
"01100100",
"01100111",
"01100001",
"01100000",
"01100010",
"01100000",
"01100010",
"01011110",
"01100010",
"01100000",
"01100000",
"01100000",
"01011111",
"01011001",
"01011010",
"01010011",
"01001011",
"01001100",
"01100010",
"01110011",
"01111110",
"10000111",
"10000110",
"01111101",
"01111101",
"01111100",
"01111111",
"10000010",
"01111110",
"01111110",
"01111110",
"01111111",
"10000000",
"10000001",
"10000010",
"10000100",
"10000001",
"10000000",
"10111010",
"11001110",
"11010011",
"11010101",
"10100100",
"01000110",
"01001100",
"01010111",
"01011000",
"01011011",
"01011100",
"01011110",
"01011011",
"01011011",
"01011101",
"01011110",
"01011110",
"01011101",
"01011010",
"01011100",
"01011111",
"01011111",
"01011110",
"01010110",
"01100000",
"01101010",
"01000100",
"10001000",
"10000110",
"10001000",
"10000101",
"10001000",
"10000001",
"10000001",
"10000001",
"10000010",
"10001010",
"10001111",
"10010111",
"10010100",
"10001011",
"01111000",
"01010100",
"00111101",
"01000000",
"01001000",
"01001001",
"01001100",
"01001110",
"01001011",
"01001101",
"01001110",
"01001001",
"01010001",
"01010101",
"01010101",
"01011100",
"01011111",
"01100000",
"01100011",
"01011111",
"01101010",
"01100010",
"01011111",
"01100101",
"01100001",
"01101001",
"01100010",
"01100110",
"01100100",
"01100100",
"01100111",
"01100100",
"01101000",
"01100100",
"01101000",
"01101001",
"01101000",
"01100111",
"01101010",
"01100101",
"01100100",
"01100011",
"01100110",
"01100110",
"01100100",
"01100010",
"01100111",
"01101001",
"01100100",
"01100011",
"01101100",
"01100001",
"01100100",
"01100100",
"01100011",
"01100100",
"01100010",
"01100010",
"01100010",
"01100000",
"01011111",
"01100011",
"01011011",
"01011001",
"01010101",
"01001010",
"01001111",
"01100110",
"01110101",
"10000001",
"10001001",
"10001000",
"01111001",
"01111111",
"01111111",
"10000000",
"10000100",
"01111111",
"01111110",
"01111111",
"01111111",
"01111111",
"10000011",
"10000011",
"10000111",
"10000001",
"10001000",
"11000011",
"11001111",
"11010100",
"11010001",
"10001011",
"01000101",
"01001110",
"01011001",
"01011011",
"01011100",
"01011011",
"01100001",
"01011011",
"01011010",
"01011001",
"01011101",
"01011111",
"01011111",
"01011000",
"01100000",
"01100001",
"01011110",
"01011110",
"01010101",
"01010101",
"10001011",
"10000111"
);
constant test_corrupt_image: test_img_t:= (
"00010111",
"00011001",
"00011010",
"00101101",
"10110100",
"10111110",
"10111101",
"10011001",
"01010000",
"01111000",
"10010010",
"10011111",
"10100001",
"10100011",
"10011110",
"01000000",
"00100010",
"00010011",
"00010110",
"00011010",
"00100000",
"00101111",
"00100110",
"00000000",
"00101010",
"00100110",
"01100001",
"00100110",
"00011111",
"00110011",
"00111000",
"00110001",
"01000011",
"01000001",
"01001111",
"00110000",
"00010000",
"00101010",
"00110001",
"00010110",
"11111111",
"00100011",
"01011010",
"00100111",
"00101101",
"00110100",
"00111010",
"01000110",
"01001100",
"01010001",
"00000000",
"01010111",
"01011001",
"01011101",
"01011100",
"01011100",
"01011100",
"01011110",
"01100001",
"01011101",
"01011111",
"01100110",
"01100110",
"01011111",
"01100010",
"01100111",
"01101010",
"01101001",
"01110000",
"01101111",
"01110000",
"01101110",
"01110010",
"01110001",
"11111111",
"01110101",
"01110111",
"01110111",
"01111001",
"01110111",
"10000010",
"10000000",
"10000101",
"10001101",
"10001110",
"10010011",
"10011010",
"10100110",
"10101111",
"10110100",
"10111000",
"10111110",
"11000011",
"11000110",
"11001110",
"10011000",
"01000001",
"01000101",
"11111111",
"01001110",
"01010011",
"01011111",
"01101000",
"01011110",
"01011011",
"01011010",
"01101010",
"01101010",
"01010110",
"00111110",
"00111100",
"00110010",
"00110000",
"00111110",
"01000000",
"00111000",
"00111101",
"11111111",
"01101011",
"11111111",
"01001111",
"00101010",
"00011011",
"00010010",
"00011000",
"00101011",
"01000001",
"01000101",
"00011011",
"00011100",
"00011110",
"00111110",
"10111000",
"11000010",
"11000000",
"10100000",
"01001101",
"01110110",
"10010110",
"10011101",
"10011111",
"10100100",
"10011001",
"01100001",
"00100010",
"00010110",
"00010111",
"00011101",
"00100110",
"00011111",
"00100001",
"00000000",
"00011101",
"00110100",
"00011111",
"01010011",
"00010001",
"00110101",
"00111100",
"00110111",
"01110101",
"00000100",
"01001001",
"00110000",
"00100000",
"00110101",
"00110001",
"00100010",
"01001100",
"01100000",
"00100101",
"00000101",
"00010010",
"00101000",
"00110111",
"01000110",
"01001011",
"00000000",
"01010101",
"01010011",
"01010110",
"00000000",
"01011010",
"01011100",
"01100000",
"01011110",
"01100001",
"01011100",
"01100100",
"01100101",
"01100011",
"01100010",
"01101100",
"01101000",
"11111111",
"01101011",
"01101110",
"01110010",
"01110000",
"01101111",
"01110011",
"01110010",
"00000000",
"01110110",
"01110011",
"01110010",
"01111000",
"11111111",
"01111100",
"01111110",
"10001000",
"10001101",
"10001101",
"10011100",
"10011110",
"10101010",
"10110000",
"10110110",
"10111110",
"11000010",
"11000111",
"11001001",
"11010010",
"01100110",
"00110011",
"01000110",
"01001100",
"01001111",
"01011101",
"01011100",
"00000000",
"01011100",
"01010011",
"01010001",
"01010010",
"01011100",
"01011100",
"01001001",
"00111101",
"01001001",
"00111111",
"00111000",
"00111010",
"00111000",
"00110000",
"01000111",
"01100100",
"01101001",
"01011010",
"01000110",
"00101010",
"00011010",
"00011000",
"00100010",
"00100111",
"00111001",
"00011101",
"00011011",
"00100100",
"00111110",
"10101010",
"11000110",
"11000011",
"10000001",
"01010001",
"01111000",
"10010110",
"10011101",
"10100010",
"10100110",
"10011011",
"01001000",
"00011101",
"00011001",
"00011110",
"00010110",
"00011000",
"00100001",
"00011110",
"00101001",
"00100010",
"00100111",
"00010011",
"01100000",
"00010010",
"00101001",
"01000000",
"01100111",
"00111100",
"00010111",
"01010101",
"00011110",
"00010101",
"01010111",
"00011000",
"00110100",
"01010011",
"00100001",
"11111111",
"00010100",
"00010110",
"00010101",
"00101111",
"00111111",
"01001010",
"01001111",
"01010010",
"01010001",
"01011000",
"01011010",
"01011011",
"01011001",
"00000000",
"01100001",
"01011110",
"01100000",
"01100011",
"01100010",
"01101000",
"01100101",
"01100110",
"01101001",
"01101010",
"01101010",
"01110000",
"01101100",
"01110010",
"01110011",
"01110001",
"01110011",
"00000000",
"01110001",
"11111111",
"01110010",
"01110111",
"01110111",
"01111010",
"10000001",
"10000111",
"10001110",
"10010100",
"10011101",
"10100011",
"10101010",
"10101111",
"10111011",
"10111111",
"11000100",
"11001000",
"11001001",
"11010101",
"00111001",
"00000000",
"01001001",
"01001111",
"01010101",
"01011110",
"01100010",
"01011011",
"01010101",
"01010100",
"01010000",
"01001001",
"01001001",
"01010110",
"01001110",
"00111101",
"00111011",
"01001000",
"01000101",
"00101111",
"00101010",
"00101011",
"00110011",
"01001011",
"01100001",
"01100110",
"01010010",
"00111110",
"00101000",
"00100000",
"00011111",
"00011010",
"00100001",
"00100001",
"00100011",
"00110100",
"01001010",
"10010101",
"10110010",
"10100100",
"01100101",
"01001011",
"01110110",
"10010110",
"10011111",
"10100010",
"10100101",
"10011011",
"01101010",
"00100011",
"00100100",
"00010110",
"00011011",
"00010101",
"00100100",
"00100010",
"00011111",
"00111011",
"00010001",
"00010110",
"01000100",
"00001110",
"00100011",
"01000010",
"01101011",
"00000101",
"00110100",
"01011100",
"00000111",
"00110100",
"01000000",
"00110000",
"01100101",
"01000000",
"00101101",
"00001110",
"00011001",
"00001111",
"00000000",
"00011001",
"00101101",
"00111010",
"01001101",
"01001100",
"01010010",
"01010111",
"01011001",
"01011010",
"01011100",
"01011110",
"01011100",
"01011010",
"01100011",
"01100110",
"01100100",
"01100010",
"01101001",
"01101001",
"01101001",
"01101010",
"01101011",
"01110000",
"01110000",
"01101110",
"01110010",
"01101111",
"01110100",
"01101110",
"01101110",
"01101101",
"01110010",
"01110101",
"01110110",
"01111011",
"01111111",
"10000110",
"10001110",
"10010100",
"10011101",
"10100011",
"10101110",
"10110101",
"10111001",
"11000001",
"11001001",
"11001000",
"11001101",
"11000011",
"00100100",
"01000000",
"01001010",
"01010001",
"01011001",
"01011000",
"01011011",
"01011111",
"00000000",
"01010100",
"01001010",
"01000111",
"01000000",
"01000111",
"00000000",
"00111100",
"00110000",
"00111000",
"01001011",
"00111110",
"00110000",
"00110001",
"00101100",
"00110001",
"01010100",
"01011111",
"01011101",
"01010000",
"00110011",
"00100010",
"00011111",
"00011011",
"00011000",
"00011000",
"00101100",
"01000001",
"01011011",
"10011001",
"10101000",
"10010110",
"01011000",
"01001011",
"01110110",
"10010101",
"10011110",
"10100001",
"10100111",
"10011000",
"01111010",
"00100111",
"00010010",
"00010011",
"00011101",
"00011000",
"11111111",
"00011110",
"00011010",
"00110110",
"00010110",
"00100000",
"00111101",
"00010101",
"00101111",
"01100001",
"01000001",
"00010011",
"01000001",
"00100111",
"00000000",
"01010000",
"11111111",
"01010000",
"01011000",
"11111111",
"00100101",
"00010011",
"00011001",
"00010110",
"00010010",
"00001110",
"00010011",
"00011010",
"00101110",
"00110110",
"01000010",
"01010010",
"01010110",
"01011001",
"01011101",
"01011110",
"01011100",
"01011110",
"01100011",
"01100001",
"01100110",
"01100111",
"01100100",
"01101011",
"01101001",
"01101010",
"01101111",
"01110000",
"01110011",
"01101110",
"01101111",
"01101110",
"01101101",
"01101010",
"01101110",
"01101011",
"01101111",
"01110100",
"01111001",
"01111111",
"10000100",
"10001001",
"10001110",
"10011101",
"10100100",
"10101010",
"10110010",
"10111000",
"11000000",
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"01011101",
"01011110",
"01100010",
"01101001",
"00110111",
"00001100",
"00010000",
"00010100",
"00010100",
"00010110",
"00010110",
"11111111",
"10000000",
"10000000",
"10000100",
"10000011",
"10000101",
"10000010",
"10000100",
"10001100",
"10001111",
"10010000",
"10001000",
"10000110",
"10000111",
"10000010",
"01101110",
"01001101",
"00110111",
"00110100",
"00111100",
"01000110",
"01000110",
"01000111",
"00000000",
"01000100",
"01000011",
"01001001",
"01001100",
"01001110",
"01011001",
"01010111",
"01011010",
"01011101",
"01011111",
"01011011",
"01100000",
"01100001",
"01011101",
"01100000",
"01011110",
"01100001",
"01100000",
"01011111",
"01011110",
"01100010",
"01100000",
"01011101",
"01100000",
"01100011",
"01100110",
"01100001",
"01011011",
"01011011",
"01011010",
"01011011",
"01011101",
"01011101",
"01011100",
"01011101",
"01011110",
"01011101",
"01011110",
"01100000",
"01100100",
"01100010",
"01100011",
"01100100",
"11111111",
"01011100",
"01011110",
"01011101",
"01011110",
"01011101",
"01011111",
"01011100",
"01011101",
"01011110",
"01011100",
"01011010",
"01011101",
"01001101",
"01001100",
"01001000",
"01010101",
"01100010",
"01110100",
"10000010",
"10000111",
"10001001",
"10001011",
"10000101",
"10000110",
"10000110",
"10000111",
"10000011",
"10000010",
"10000001",
"10000000",
"11111111",
"01111111",
"01111101",
"01111110",
"01111100",
"01110111",
"01111011",
"10111111",
"11010001",
"11010111",
"11010111",
"10100101",
"01000100",
"01010000",
"01010111",
"01011110",
"01011011",
"01011101",
"01011011",
"01011001",
"01011101",
"01011111",
"01100100",
"01101100",
"00111011",
"00100000",
"00010001",
"00010001",
"00010010",
"00010100",
"00011010",
"10000010",
"01111111",
"10000010",
"10000100",
"10000100",
"10000001",
"00000000",
"10000110",
"11111111",
"10001100",
"10001101",
"10001011",
"10001000",
"01111110",
"01101101",
"01011010",
"00111100",
"00111011",
"01000000",
"01000100",
"01001100",
"01000101",
"01000111",
"01000011",
"01001000",
"01000101",
"01001110",
"01010000",
"01010101",
"01010111",
"01011010",
"01011010",
"01011110",
"01100000",
"01100000",
"01100001",
"01100011",
"01100000",
"01100001",
"01100001",
"01100001",
"01100011",
"01100001",
"01100010",
"01100000",
"01100010",
"01011111",
"01100001",
"01100010",
"01100000",
"01011111",
"01100001",
"01100000",
"01100000",
"01100000",
"11111111",
"01100011",
"01100010",
"01011101",
"01100000",
"01100100",
"01100110",
"01100111",
"01100001",
"01100001",
"01100001",
"01100100",
"01011111",
"01100001",
"01011100",
"01011101",
"01011101",
"01011110",
"01011110",
"01011100",
"01011111",
"01011011",
"01011011",
"01011100",
"01010001",
"01001101",
"01001001",
"01001110",
"01100111",
"01111001",
"10000001",
"10001001",
"10001011",
"10000111",
"11111111",
"10001011",
"10000111",
"10001000",
"10000001",
"10000011",
"11111111",
"10000000",
"01111101",
"01111101",
"01111111",
"01111011",
"01111101",
"01110010",
"10100001",
"11001100",
"11010100",
"11010111",
"11000101",
"01011100",
"01001100",
"01010000",
"01010111",
"01010110",
"01011011",
"01011011",
"01011011",
"01011001",
"01100011",
"01100011",
"01100100",
"01100110",
"01101101",
"00111011",
"00010110",
"00011010",
"00011100",
"00010101",
"00011000",
"10000001",
"10000001",
"10000001",
"10000011",
"10000011",
"10000001",
"01111110",
"10000101",
"10001101",
"10010000",
"10001111",
"10001100",
"10001100",
"01111110",
"01101100",
"01010010",
"00111000",
"00111001",
"01000000",
"01000001",
"01000111",
"01001011",
"01000101",
"01001000",
"01000100",
"01000100",
"01001110",
"01010010",
"01010110",
"01011000",
"01011100",
"01011100",
"01011111",
"01100001",
"01011111",
"11111111",
"01100001",
"01100011",
"01100011",
"01100001",
"01100010",
"01100011",
"01100011",
"01100100",
"01100111",
"01100010",
"01100011",
"01100011",
"01011111",
"01100110",
"01100010",
"01100101",
"01100011",
"01100011",
"00000000",
"01100000",
"01100001",
"01100101",
"01011111",
"01100010",
"01100111",
"01101001",
"11111111",
"00000000",
"01100100",
"01100011",
"01100011",
"01011101",
"01100001",
"01100010",
"01011100",
"01011110",
"01100001",
"01100001",
"01011110",
"01100001",
"01100000",
"01011010",
"01010001",
"01010101",
"01001110",
"01000101",
"01010110",
"01101111",
"01111010",
"10000011",
"10001011",
"10001000",
"10000110",
"10001010",
"10001001",
"10001010",
"10000011",
"10000111",
"10000010",
"01111111",
"01111110",
"10000000",
"01111100",
"01111110",
"01111110",
"01111010",
"10000011",
"11000011",
"11010010",
"11010101",
"11010010",
"10001110",
"01000011",
"01001101",
"01010110",
"01010101",
"01011010",
"01011010",
"01011111",
"01011100",
"01011111",
"01011110",
"01011111",
"01011111",
"01100011",
"01100100",
"01101001",
"00111111",
"00010000",
"00010001",
"00011001",
"00010010",
"10000011",
"10000010",
"10000011",
"10000000",
"10000001",
"10000001",
"01111111",
"10000000",
"10001001",
"10010000",
"10010011",
"10010001",
"10001110",
"10000011",
"01101010",
"01010000",
"00111010",
"00111011",
"00111111",
"01000101",
"01001001",
"01001011",
"01001001",
"01000101",
"01000101",
"01000110",
"01001111",
"01010011",
"01010100",
"01011010",
"01011100",
"01011101",
"01011100",
"01011111",
"01100000",
"01100100",
"01100010",
"11111111",
"01100000",
"01100011",
"01100001",
"01100010",
"01100011",
"01100100",
"01100000",
"01100011",
"11111111",
"01100001",
"01100001",
"01100011",
"01100010",
"01100001",
"01100011",
"01100011",
"01100000",
"01100001",
"01100011",
"01100010",
"01011110",
"01100011",
"01100110",
"01100101",
"01100010",
"01100100",
"01100010",
"01100001",
"01100011",
"01100010",
"01100000",
"01011111",
"11111111",
"01100001",
"01011101",
"01100000",
"01100000",
"01100000",
"01011100",
"01011010",
"01010010",
"01010011",
"01001011",
"01001010",
"01100001",
"01110011",
"01111101",
"00000000",
"10000111",
"10000110",
"10000100",
"10001000",
"10001010",
"10000100",
"10000011",
"10000000",
"10000010",
"10000000",
"10000000",
"01111110",
"01111101",
"01111111",
"00000000",
"01111000",
"10101110",
"11001100",
"11010100",
"11010111",
"10110110",
"01010001",
"00000000",
"01010000",
"01010111",
"01011001",
"01011001",
"01011100",
"01011000",
"01011011",
"01011010",
"01011010",
"01011101",
"01011100",
"01011111",
"01011110",
"01100000",
"01101010",
"01000111",
"00011100",
"00010010",
"00011010",
"10000011",
"01111110",
"10000100",
"10000010",
"10000001",
"10000000",
"01111110",
"01111111",
"01111111",
"10001100",
"10010001",
"10010101",
"10010011",
"10000110",
"11111111",
"01010010",
"00111000",
"00110111",
"01000010",
"01000010",
"01000101",
"01000110",
"01001001",
"01000101",
"01000110",
"01001010",
"01001110",
"01010010",
"01010111",
"11111111",
"11111111",
"01011111",
"01011110",
"01100000",
"01100001",
"01100001",
"01100010",
"00000000",
"01100010",
"01100011",
"01100001",
"01100110",
"01100100",
"01100011",
"01100101",
"01100010",
"01100101",
"01100011",
"01100011",
"01100010",
"01100010",
"01100001",
"01100001",
"01100011",
"01100001",
"01011110",
"01100011",
"01100101",
"01011111",
"01100010",
"01100010",
"01100011",
"01100000",
"01100000",
"01100010",
"01100011",
"01100001",
"01011111",
"01011111",
"00000000",
"01011110",
"01011110",
"01100000",
"01100000",
"01011111",
"01011110",
"01011101",
"01010111",
"01010010",
"01001101",
"00000000",
"01010100",
"01101001",
"01111000",
"10000001",
"10001000",
"10000000",
"01111110",
"10000011",
"10000010",
"10000001",
"10000010",
"10000010",
"01111111",
"10000001",
"01111110",
"10000001",
"01111111",
"10000000",
"01111111",
"01111101",
"10001111",
"11000110",
"11010001",
"11010100",
"11001101",
"01110101",
"01000110",
"01010000",
"01010110",
"01011011",
"01011011",
"01011011",
"01011010",
"01011000",
"01011011",
"01011100",
"01011100",
"01011101",
"01011100",
"01011101",
"01011110",
"01011101",
"01100011",
"01100101",
"01001011",
"00010101",
"00010001",
"10000110",
"10000100",
"10000110",
"01111110",
"10000010",
"01111110",
"10000001",
"11111111",
"10000000",
"10001000",
"10010000",
"10010110",
"10010101",
"10001001",
"01110001",
"01010010",
"00111010",
"00111100",
"01000001",
"01001100",
"01000111",
"11111111",
"01000110",
"01001001",
"01001001",
"01001000",
"01001101",
"01010101",
"01011000",
"01011100",
"01011100",
"01011100",
"01100010",
"01100010",
"01100100",
"01100010",
"01100010",
"01100100",
"01100001",
"01100100",
"01100100",
"01100111",
"01100011",
"01100101",
"01100100",
"01100010",
"01100011",
"01100011",
"01100110",
"01100100",
"01100110",
"01100100",
"01101000",
"01100101",
"01100100",
"01100010",
"11111111",
"01100101",
"11111111",
"01100011",
"01100101",
"01100101",
"01100011",
"01100100",
"01100111",
"01100001",
"01100000",
"01100010",
"01100000",
"01100010",
"00000000",
"01100010",
"01100000",
"01100000",
"01100000",
"01011111",
"01011001",
"01011010",
"01010011",
"01001011",
"01001100",
"01100010",
"01110011",
"01111110",
"11111111",
"10000110",
"01111101",
"01111101",
"01111100",
"01111111",
"10000010",
"01111110",
"01111110",
"01111110",
"01111111",
"10000000",
"10000001",
"10000010",
"10000100",
"10000001",
"10000000",
"10111010",
"11001110",
"11010011",
"11010101",
"10100100",
"01000110",
"01001100",
"01010111",
"01011000",
"01011011",
"00000000",
"01011110",
"00000000",
"01011011",
"01011101",
"01011110",
"01011110",
"01011101",
"01011010",
"01011100",
"01011111",
"11111111",
"01011110",
"01010110",
"01100000",
"01101010",
"01000100",
"00000000",
"10000110",
"10001000",
"10000101",
"10001000",
"10000001",
"10000001",
"10000001",
"10000010",
"10001010",
"10001111",
"10010111",
"10010100",
"10001011",
"01111000",
"01010100",
"00111101",
"01000000",
"01001000",
"01001001",
"00000000",
"01001110",
"01001011",
"01001101",
"11111111",
"01001001",
"01010001",
"01010101",
"01010101",
"01011100",
"01011111",
"01100000",
"01100011",
"01011111",
"01101010",
"11111111",
"01011111",
"01100101",
"01100001",
"01101001",
"01100010",
"01100110",
"01100100",
"01100100",
"01100111",
"01100100",
"01101000",
"00000000",
"01101000",
"01101001",
"01101000",
"01100111",
"01101010",
"01100101",
"01100100",
"01100011",
"01100110",
"01100110",
"01100100",
"01100010",
"01100111",
"01101001",
"01100100",
"01100011",
"01101100",
"01100001",
"01100100",
"01100100",
"01100011",
"01100100",
"01100010",
"01100010",
"01100010",
"01100000",
"01011111",
"01100011",
"01011011",
"01011001",
"01010101",
"01001010",
"01001111",
"01100110",
"01110101",
"10000001",
"10001001",
"00000000",
"01111001",
"01111111",
"01111111",
"10000000",
"10000100",
"01111111",
"11111111",
"01111111",
"11111111",
"01111111",
"10000011",
"10000011",
"10000111",
"10000001",
"10001000",
"11000011",
"11001111",
"11010100",
"11010001",
"10001011",
"01000101",
"01001110",
"01011001",
"01011011",
"01011100",
"01011011",
"01100001",
"01011011",
"01011010",
"01011001",
"01011101",
"01011111",
"01011111",
"01011000",
"01100000",
"01100001",
"01011110",
"01011110",
"01010101",
"01010101",
"10001011",
"10000111"
);
end;
package body img_pkg is
end package body;
|
gpl-3.0
|
hiyuh/nvc
|
test/sem/generics.vhd
|
4
|
2489
|
entity bot is
generic ( N : integer );
port ( o : out integer );
end entity;
architecture a of bot is
begin
process is
begin
o <= N;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity top is
end entity;
architecture test of top is
signal x : integer;
begin
bot0: entity work.bot -- OK
generic map ( N => 5 )
port map ( o => x );
bot1: entity work.bot -- OK
generic map ( 5 )
port map ( o => x );
bot3: entity work.bot -- Missing N
port map ( o => x );
bot4: entity work.bot -- Too many generics
generic map ( 1, 2 )
port map ( o => x );
end architecture;
-------------------------------------------------------------------------------
entity bad is
generic (
X : integer;
Y : integer := X + 1 ); -- X not visible
port (
p : in integer := X );
end entity;
-------------------------------------------------------------------------------
entity class is
generic (
constant X : integer; -- OK
signal Y : integer ); -- Error
end entity;
-------------------------------------------------------------------------------
package p is
component c is
generic ( X : integer ); -- OK
port ( p : in integer range 1 to X; -- OK
q : in integer range 1 to Y ); -- Error
end component;
end package;
-------------------------------------------------------------------------------
entity static is
generic ( X : integer );
end entity;
architecture a of static is
constant k : integer := X + 1;
signal s : bit_vector(1 to 3);
alias sx : bit is s(X);
alias sx1 : bit is s(X + 1);
alias sx2 : bit_vector is s(k to 3);
function f(x : bit_vector) return integer;
component c is
generic (
x : bit_vector(2 downto 0) );
end component;
component d is
generic (
t : time );
end component;
begin
i1: entity work.bot
generic map (
N => f("100") )
port map (
o => open );
i2: component c
generic map ( x => "00" & '1' ); -- OK
i3: component c
generic map ( x => "00" & sx ); -- Error
i4: component d
generic map ( t => 100 ns ); -- OK
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/bounds15.vhd
|
4
|
542
|
entity bounds15 is
end entity;
architecture test of bounds15 is
function fact(n : natural) return positive is
begin
if n = 0 then
return 1;
else
return n * fact(n - 1);
end if;
end function;
begin
process is
variable x : integer;
begin
x := 5;
report integer'image(fact(x));
x := 0;
report integer'image(fact(x));
x := -1;
report integer'image(fact(x)); -- Error
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/lower/issue122.vhd
|
5
|
338
|
entity issue122 is
end entity;
architecture test of issue122 is
impure function func(x : integer) return integer is
impure function nested return integer is
begin
return x;
end function;
variable v : integer := nested;
begin
return v;
end function;
begin
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/elab1.vhd
|
5
|
656
|
entity elab1_bot is
port (
i : in integer;
o : out integer );
end entity;
architecture test of elab1_bot is
begin
process (i) is
begin
o <= i + 1;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab1 is
end entity;
architecture test of elab1 is
signal x, y : integer;
begin
uut: entity work.elab1_bot
port map ( x, y );
process is
begin
x <= 0;
wait for 1 ns;
assert y = 1;
x <= 2;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/issue18.vhd
|
5
|
900
|
entity sub is
port (
x, y : in bit_vector(3 downto 0);
z : out bit_vector(3 downto 0) );
end entity;
architecture test of sub is
begin
z <= x and y;
end architecture;
-------------------------------------------------------------------------------
entity issue18 is
end entity;
architecture test of issue18 is
signal s : bit_vector(7 downto 0);
constant c : bit_vector(7 downto 0) := X"AA";
begin
sub_i: entity work.sub
port map (
x => c(3 downto 0),
y => s(3 downto 0),
z => s(7 downto 4) );
process is
begin
s(3 downto 0) <= X"A";
wait for 1 ns;
assert s = X"AA";
s(3 downto 0) <= X"0";
wait for 1 ns;
assert s = X"00";
s(3 downto 0) <= X"F";
wait for 1 ns;
assert s = X"AF";
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/issue217.vhd
|
5
|
863
|
entity SUB is
port (
USER_I : in bit_vector(1 downto 0);
RESULT : out boolean
);
end SUB;
architecture MODEL of SUB is
procedure match(user:in bit_vector; ok: out boolean) is begin
ok := (user(USER_I'range) = USER_I);
end procedure;
begin
process(USER_I)
variable ok : boolean;
constant user : bit_vector(1 downto 0) := "01";
begin
match(user, ok);
RESULT <= ok;
end process;
end MODEL;
entity issue217 is
end issue217;
architecture MODEL of issue217 is
signal USER : bit_vector(1 downto 0);
signal OK : boolean;
begin
U: entity WORK.SUB port map (
USER_I => USER,
RESULT => OK
);
user <= "01";
process is
begin
assert not ok;
wait on ok;
assert ok;
wait;
end process;
end MODEL;
|
gpl-3.0
|
hiyuh/nvc
|
lib/std/env.vhd
|
4
|
1318
|
--
-- Environment package for VHDL-2008
--
-- This is also compiled into the NVC library for use with earlier standards
--
package env is
procedure stop(status : integer);
procedure stop;
procedure finish(status : integer);
procedure finish;
function resolution_limit return delay_length;
end package;
package body env is
procedure stop_impl(finish, have_status : boolean; status : integer) is
procedure nvc_env_stop(finish, have_status : boolean; status : integer);
attribute foreign of nvc_env_stop : procedure is "_nvc_env_stop";
begin
nvc_env_stop(finish, have_status, status);
end procedure;
procedure stop(status : integer) is
begin
stop_impl(finish => false, have_status => true, status => status);
end procedure;
procedure stop is
begin
stop_impl(finish => false, have_status => false, status => 0);
end procedure;
procedure finish(status : integer) is
begin
stop_impl(finish => true, have_status => true, status => status);
end procedure;
procedure finish is
begin
stop_impl(finish => true, have_status => false, status => 0);
end procedure;
function resolution_limit return delay_length is
begin
return fs;
end function;
end package body;
|
gpl-3.0
|
hiyuh/nvc
|
test/misc/kcuart.vhd
|
5
|
724
|
entity kcuart is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of kcuart is
signal clk : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0);
signal tx_full : std_logic;
signal tx_wr : std_logic := '0';
signal uart_tx : std_logic;
signal en_16_x_baud : std_logic;
begin
clk <= not clk after 5 ns;
tx_i: entity work.uart_tx6
port map (
data_in => tx_data,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => tx_wr,
buffer_full => tx_full,
buffer_reset => '0',
clk => clk );
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/issue56.vhd
|
5
|
372
|
entity issue56 is
generic (
x : integer := 5;
y : bit_vector := "110" );
port (
pi : in integer := 2;
po : out bit );
end entity;
architecture test of issue56 is
begin
process is
begin
assert x = 5;
assert y = "110";
assert pi = 2;
wait;
end process;
po <= '1';
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/parse/context.vhd
|
4
|
378
|
context widget_context is
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use widget_lib.widget_defs.all;
use widget_lib.widget_comps.all;
end context;
context dongle_context is
library widget_lib;
context widget_lib.widget_context;
end context;
library foo;
use foo.moo;
context bad is -- Error
end context;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/issue9.vhd
|
5
|
609
|
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
x=>x1,
y=>'0', --y=>y1 works !
z=>z1 );
process is
begin
y1 <='1';
x1 <= '0';
wait for 1 ns;
assert z1 = '0';
x1<='1';
wait for 1 ns;
assert z1 = '0';
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/group/issue73.vhd
|
5
|
540
|
entity issue73 is
end entity;
architecture test of issue73 is
type ma_t is array (1 downto 0) of bit_vector(3 downto 0);
signal x : ma_t; -- 0..7
signal y : ma_t; -- 8..15
begin
x(0)(1 downto 0) <= "00";
x(0)(3 downto 2) <= "11";
x(1)(0 downto 0) <= "0";
x(1)(3 downto 1) <= "101";
process (y) is
begin
for i in x'range loop
y(i)(1 downto 0) <= "00";
y(i)(3 downto 2) <= "11";
end loop;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/issue83.vhd
|
5
|
450
|
entity read_output is
port (
output1, output2 : out integer);
end entity;
architecture a of read_output is
begin
output1 <= 5;
output2 <= output1 after 1 ns;
end architecture;
-------------------------------------------------------------------------------
entity issue83 is
end entity;
architecture test of issue83 is
signal x, y : integer;
begin
sub: entity work.read_output
port map ( x, y );
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/lower/proc1.vhd
|
4
|
364
|
entity proc1 is
end entity;
architecture test of proc1 is
procedure add1(x : in integer; y : out integer) is
begin
y := x + 1;
end procedure;
begin
process is
variable a, b : integer;
begin
add1(a, b);
assert b = 3;
add1(5, b);
assert b = 6;
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/bounds11.vhd
|
4
|
177
|
entity bounds11 is
end entity;
architecture test of bounds11 is
type my_int is range 0 to 100;
signal i : my_int;
begin
i <= i + 1 after 10 ns;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/lower/staticwait.vhd
|
4
|
181
|
entity staticwait is
end entity;
architecture test of staticwait is
signal x : integer;
begin
process (x) is
begin
x <= 0;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/issue229.vhd
|
5
|
361
|
use std.textio.all;
entity issue229 is
end entity issue229;
architecture test of issue229 is
begin
process
begin
for ii in 1 to 2049 loop
write(OUTPUT, integer'image(1));
end loop;
wait;
end process;
-- Alternatively, delete the for loop and the wait statement -- it fails the same way
end architecture test;
|
gpl-3.0
|
hiyuh/nvc
|
test/parse/procedure.vhd
|
4
|
490
|
package p is
procedure foo(x : in integer; y : out integer);
end package;
package body p is
procedure foo(x : in integer; y : out integer) is
variable i : integer;
begin
y := x + 1;
end procedure;
procedure bar(file x : text);
procedure baz is
type foo;
alias x is y;
constant k : integer := 2;
begin
end procedure;
procedure tralala is
use work.foo;
begin
end procedure;
end package body;
|
gpl-3.0
|
hiyuh/nvc
|
test/regress/proc3.vhd
|
3
|
1531
|
package pack is
function func(x : in integer) return integer;
end package;
package body pack is
procedure p5(x : in integer; y : out integer) is
variable k : integer := x + 1;
begin
y := k;
end procedure;
function func(x : in integer) return integer is
variable y : integer;
begin
p5(x, y);
return y;
end function;
end package body;
-------------------------------------------------------------------------------
entity proc3 is
end entity;
use work.pack.all;
architecture test of proc3 is
procedure p1 is
begin
wait for 10 ns;
wait for 5 ns;
end procedure;
procedure p2 is
begin
p1;
p1;
end procedure;
procedure p3(t : in time) is
begin
loop
wait for t;
if now >= 100 ns then
return;
end if;
end loop;
end procedure;
procedure p4(x : in integer; y : out integer) is
variable k : integer;
begin
k := x;
for i in 1 to 5 loop
k := k + 1;
wait for 1 ns;
end loop;
y := k;
end procedure;
begin
process is
variable x : integer;
begin
p1;
assert now = 15 ns;
p2;
assert now = 45 ns;
p3(5 ns);
assert now = 100 ns;
p4(5, x);
assert x = 10;
assert now = 105 ns;
x := func(9);
assert x = 10;
wait;
end process;
end architecture;
|
gpl-3.0
|
hiyuh/nvc
|
test/parse/empty.vhd
|
12226531
|
0
|
gpl-3.0
|
|
freecores/usb_fpga_2_16
|
examples/usb-fpga-1.11/1.11c/lightshow/fpga/lightshow.vhd
|
36
|
2235
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lightshow is
port(
led : out std_logic_vector(11 downto 0);
CLK : in std_logic -- 32 MHz
);
end lightshow;
--signal declaration
architecture RTL of lightshow is
type tPattern is array(11 downto 0) of integer range 0 to 15;
signal pattern1 : tPattern := (0, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1);
signal pattern2 : tPattern := (6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5);
signal pattern3 : tPattern := (0, 1, 4, 9, 4, 1, 0, 0, 0, 0, 0, 0);
type tXlatTable1 is array(0 to 12) of integer range 0 to 1023;
constant xt1 : tXlatTable1 := (0, 0, 1, 4, 13, 31, 64, 118, 202, 324, 493, 722, 1023);
type tXlatTable2 is array(0 to 9) of integer range 0 to 255;
--constant xt2 : tXlatTable2 := (0, 1, 11, 38, 90, 175, 303, 481, 718, 1023);
constant xt2 : tXlatTable2 := (0, 0, 3, 9, 22, 44, 76, 120, 179, 255);
signal cp1 : std_logic_vector(22 downto 0);
signal cp2 : std_logic_vector(22 downto 0);
signal cp3 : std_logic_vector(22 downto 0);
signal d : std_logic_vector(16 downto 0);
begin
dpCLK: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( cp1 = conv_std_logic_vector(3000000,23) )
then
pattern1(10 downto 0) <= pattern1(11 downto 1);
pattern1(11) <= pattern1(0);
cp1 <= (others => '0');
else
cp1 <= cp1 + 1;
end if;
if ( cp2 = conv_std_logic_vector(2200000,23) )
then
pattern2(10 downto 0) <= pattern2(11 downto 1);
pattern2(11) <= pattern2(0);
cp2 <= (others => '0');
else
cp2 <= cp2 + 1;
end if;
if ( cp3 = conv_std_logic_vector(1500000,23) )
then
pattern3(11 downto 1) <= pattern3(10 downto 0);
pattern3(0) <= pattern3(11);
cp3 <= (others => '0');
else
cp3 <= cp3 + 1;
end if;
if ( d = conv_std_logic_vector(1278*64-1,17) )
then
d <= (others => '0');
else
d <= d + 1;
end if;
for i in 0 to 11 loop
if ( d(16 downto 6) < conv_std_logic_vector( xt1(pattern1(i) + pattern2(i)) + xt2(pattern3(i)) ,11) )
then
led(i) <= '1';
else
led(i) <= '0';
end if;
end loop;
end if;
end process dpCLK;
end RTL;
|
gpl-3.0
|
rpereira-dev/ENSIIE
|
UE/S3/microarchi/bus_ia/serpentinclignonant.vhd
|
1
|
740
|
-------------------------------------------------------------------------------
-- Ce bloc est un registre contenant la configuration a transmettre au
-- serpentin programmable, pour qu'il affiche un serpentin clignotant
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity serpentinclignotant is
port(
Config : OUT STD_LOGIC_VECTOR(229 downto 0)
);
end serpentinclignotant;
architecture montage of serpentinclignotant is
begin
-- boucle sur 2 frames
Config(229 downto 224) <= "000010";
-- 2 frames, 1 allumé, 1 éteinte
Config( 6 downto 0) <= "1111111";
Config( 13 downto 7) <= "0000001";
end montage;
|
gpl-3.0
|
rpereira-dev/ENSIIE
|
UE/S3/microarchi/bus_ia/terminateurSplit.vhd
|
2
|
5791
|
-- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: terminateurSplit.vhd 322 2015-05-29 06:43:59Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/terminateurSplit.vhd $
-- $Author : Ivan Auge (Email: [email protected])
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-------------------------------------------------------------------------------
-- Ce module récupère un message (????,addrsrc,addrdest,data) sur busin et le
-- découpe en 6 octets B5, B4, B3,B2,B1,B0 puis les envoie 1 par 1 sur RS232out.
-- B0 est le premier octet envoyé, B5 est le dernier octet envoyé.
-- busin[43:40] = control = B5 (0000CCCC)
-- busin[39:32] = adddest = B4
-- busin[31:24] = addrsrc = B3
-- busin[23: 0] = data = B2<<16 | B1<<8 | B0
--
-- Du coté busin, il suit le protocole "poignee de main" (signaux: busin,
-- busin_valid, busin_eated).
-- Du coté RS232out, il suit le protocole du module RS232out (signaux:
-- Data, Ndata, Busy).
-------------------------------------------------------------------------------
ENTITY terminateurSplit IS
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 DOWNTO 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface vers rs232in
Data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
Ndata : OUT STD_LOGIC;
Busy : IN STD_LOGIC);
END terminateurSplit;
ARCHITECTURE Montage OF terminateurSplit IS
-- compteur donnant le nombre d'octets de R deja envoye sur Data
TYPE T_CMD_i IS (NOOP, COUNT, INIT);
SIGNAL CMD_i : T_CMD_i ;
SIGNAL R_i : INTEGER RANGE 0 TO 6;
SIGNAL VT_endLoop: STD_LOGIC;
-- accumule les octets venant de Data.
TYPE T_CMD IS (NOOP, LOAD, SHIFT);
SIGNAL CMD : T_CMD ;
SIGNAL R : STD_LOGIC_VECTOR (47 DOWNTO 0);
-- FSM
TYPE STATE_TYPE IS (
ST_READ_BUSIN, ST_WAIT_NOBUSY, ST_WRITE, ST_LOOP);
SIGNAL state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
PROCESS (clk)
BEGIN IF clk'EVENT AND clk = '1' THEN
-- R_i
if ( CMD_i = INIT ) then
R_i <= 6 ;
elsif ( CMD_i = COUNT ) then
R_i <= R_i - 1;
else
R_i <= R_i;
end if;
-- R
if ( CMD = LOAD ) then
R(43 DOWNTO 0) <= busin ;
R(47 DOWNTO 44) <= "0000" ;
elsif ( CMD = SHIFT ) then
R(39 DOWNTO 32) <= R(47 DOWNTO 40);
R(31 DOWNTO 24) <= R(39 DOWNTO 32);
R(23 DOWNTO 16) <= R(31 DOWNTO 24);
R(15 DOWNTO 8) <= R(23 DOWNTO 16);
R( 7 DOWNTO 0) <= R(15 DOWNTO 8);
else
R <= R ;
end if;
END IF; END PROCESS;
VT_endLoop <= '1' when R_i=0 else '0' ;
data <= R(7 DOWNTO 0);
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: busin_valid Busy
-- Outputs: busin_eated Ndata CMD_i CMD
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
IF reset = '1' THEN
state <= ST_READ_BUSIN;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN ST_READ_BUSIN =>
IF busin_valid = '1' THEN state <= ST_WAIT_NOBUSY; END IF;
WHEN ST_WAIT_NOBUSY =>
IF Busy /= '1' THEN state <= ST_WRITE; END IF;
WHEN ST_WRITE =>
state <= ST_LOOP;
WHEN ST_LOOP =>
IF VT_endLoop = '1' THEN
state <= ST_READ_BUSIN;
ELSE
state <= ST_WAIT_NOBUSY;
END IF;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busin_eated <=
'1' WHEN ST_READ_BUSIN,
'0' WHEN OTHERS;
WITH state SELECT Ndata <=
'1' WHEN ST_WRITE,
'0' WHEN OTHERS;
WITH state SELECT CMD_i <=
INIT WHEN ST_READ_BUSIN,
COUNT WHEN ST_WRITE,
NOOP WHEN OTHERS;
WITH state SELECT CMD <=
LOAD WHEN ST_READ_BUSIN,
SHIFT WHEN ST_WRITE,
NOOP WHEN OTHERS;
END Montage;
|
gpl-3.0
|
DaveyPocket/btrace448
|
core/debounce.vhd
|
1
|
1273
|
-- Btrace 448
-- Debounce Device
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity debouncer is
generic(DD, k: integer);
port(input, clk, reset: in std_logic;
output: out std_logic);
end debouncer;
architecture circuit of debouncer is
component debounceCounter
generic(k: integer);
port(en, rst, clk: in std_logic;
Q: out std_logic_vector(k-1 downto 0));
end component;
component dff
port(D, clk, set, rst: in std_logic;
Q: out std_logic);
end component;
signal previous_input: std_logic;
signal count: std_logic;
signal Q: std_logic_vector(k-1 downto 0);
signal mux_out: std_logic;
signal inReset: std_logic;
signal force1: std_logic;
signal onCompare: std_logic;
signal bufOut: std_logic;
begin
flip: dff port map (input, clk, '0', '0', previous_input);
flop: dff port map (mux_out, clk, '0', '0', bufOut);
sandal: dff port map (count, clk, force1, inReset, count);
counter: debounceCounter generic map (k) port map (count, inReset, clk, Q);
force1 <= (input xor previous_input) and not(count);
inReset <= reset or onCompare;
onCompare <= '1' when (to_integer(unsigned(Q)) = (DD - 1)) else '0';
mux_out <= input when count = '0' else bufOut;
output <= bufOut;
end circuit;
|
gpl-3.0
|
freecores/usb_fpga_2_16
|
examples/usb-fpga-2.16/2.16b/mmio/fpga/ucecho.vhd
|
4
|
3683
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--#use IEEE.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ucecho is
port(
fxclk_in : in std_logic;
MM_A : in std_logic_vector(15 downto 0);
MM_D : inout std_logic_vector(7 downto 0);
MM_WRN : in std_logic;
MM_RDN : in std_logic;
MM_PSENN : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal rd : std_logic := '1';
signal rd0,rd1 : std_logic := '1';
signal wr : std_logic := '1';
signal wr0,wr1 : std_logic := '1';
signal datain : std_logic_vector(7 downto 0);
signal dataout : std_logic_vector(7 downto 0);
signal fxclk : std_logic; -- 96 MHz
signal fxclk_fb : std_logic;
begin
-- PLL is used as clock filter
fxclk_pll : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 10,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
CLKOUT0 => fxclk,
CLKFBOUT => fxclk_fb, -- 1-bit output: Feedback clock
CLKIN1 => fxclk_in, -- 1-bit input: Input clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
CLKFBIN => fxclk_fb -- 1-bit input: Feedback clock
);
rd <= MM_RDN and MM_PSENN;
wr <= MM_WRN;
MM_D <= dataout when ((rd1 or rd0 or rd) = '0') else ( others => 'Z' ); -- enable output
dpUCECHO: process(fxclk)
begin
if fxclk' event and fxclk = '1' then
if (wr1 = '1') and (wr0 = '0') -- EZ-USB write strobe
then
if MM_A = conv_std_logic_vector(16#5001#,16) -- read data from EZ-USB if addr=0x5001
then
datain <= MM_D;
end if;
elsif (rd1 = '1') and (rd0 = '0') -- EZ-USB read strobe
then
if MM_A = conv_std_logic_vector(16#5002#,16) -- write data to EZ-USB if addr=0x5002
then
if ( datain >= conv_std_logic_vector(97,8) ) and ( datain <= conv_std_logic_vector(122,8) ) -- do the upercase conversion
then
dataout <= datain - conv_std_logic_vector(32,8);
else
dataout <= datain ;
end if;
end if;
end if;
rd0 <= rd;
rd1 <= rd0;
wr0 <= wr;
wr1 <= wr0;
end if;
end process dpUCECHO;
end RTL;
|
gpl-3.0
|
DaveyPocket/btrace448
|
core/compare.vhd
|
1
|
909
|
-- Btrace 448
-- (un)signed Comparison
-- Bradley Boccuzzi
-- 2016
--! Remove from project
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.btrace_pack.all;
entity compare is
generic(N: integer := 8;
op: comp_op);
port(a, b: in std_logic_vector(N-1 downto 0);
c: out std_logic);
end compare;
architecture arch_unsigned of compare is
signal comparison: boolean;
begin
with op select
comparison <= unsigned(a) > unsigned(b) when gt,
unsigned(a) >= unsigned(b) when gte,
unsigned(a) = unsigned(b) when others;
c <= '1' when comparison = true else '0';
end arch_unsigned;
architecture arch_signed of compare is
signal comparison: boolean;
begin
with op select
comparison <= signed(a) > signed(b) when gt,
signed(a) >= signed(b) when gte,
signed(a) = signed(b) when others;
c <= '1' when comparison = true else '0';
end arch_signed;
|
gpl-3.0
|
DaveyPocket/btrace448
|
core/vga/list_ch13_01_font_rom.vhd
|
1
|
51592
|
-- Obtained from: http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl_book/fpga_vhdl_src.zip
-- Listing 13.1
-- ROM with synchonous read (inferring Block RAM)
-- character ROM
-- - 8-by-16 (8-by-2^4) font
-- - 128 (2^7) characters
-- - ROM size: 512-by-8 (2^11-by-8) bits
-- 16K bits: 1 BRAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity font_rom is
port(
clk: in std_logic;
addr: in std_logic_vector(10 downto 0);
data: out std_logic_vector(7 downto 0)
);
end font_rom;
architecture arch of font_rom is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
signal addr_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
type rom_type is array (0 to 2**ADDR_WIDTH-1)
of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition
constant ROM: rom_type:=( -- 2^11-by-8
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x510
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
-- addr register to infer block RAM
process (clk)
begin
if (clk'event and clk = '1') then
addr_reg <= addr;
end if;
end process;
data <= ROM(to_integer(unsigned(addr_reg)));
end arch;
|
gpl-3.0
|
rpereira-dev/ENSIIE
|
UE/S3/microarchi/bus_ia/serpentinhoraire.vhd
|
1
|
891
|
-------------------------------------------------------------------------------
-- Ce bloc est un registre contenant la configuration a transmettre au
-- serpentin programmable, pour qu'il affiche un serpentin tournant dans
-- le sens horaire.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity serpentinhoraire is
port(
Config : OUT STD_LOGIC_VECTOR(229 downto 0)
);
end serpentinhoraire;
architecture montage of serpentinhoraire is
begin
-- boucle sur 6 frames
Config(229 downto 224) <= "000110";
-- les frames
Config( 6 downto 0) <= "0001111";
Config( 13 downto 7) <= "1000111";
Config( 20 downto 14) <= "1100011";
Config( 27 downto 21) <= "1110001";
Config( 34 downto 28) <= "0111001";
Config( 41 downto 35) <= "0011101";
end montage;
|
gpl-3.0
|
freecores/usb_fpga_2_16
|
examples/usb-fpga-1.11/1.11b/memtest/fpga/memtest.vhd
|
16
|
23751
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
PA3 : in std_logic;
-- errors ...
PC : out std_logic_vector(7 downto 0);
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component dcm0
port (
-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic;
CLK_VALID : out std_logic
);
end component;
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(17 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(17 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(17 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(17 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
inst_dcm0 : dcm0 port map(
-- Clock in ports
CLK_IN1 => FXCLK,
-- Clock out ports
CLK_OUT1 => MEM_CLK,
CLK_OUT2 => CLK,
-- Status and control signals
RESET => RESET_IN,
LOCKED => DCM0_LOCKED,
CLK_VALID => DCM0_CLK_VALID
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
PC(0) <= WR_UNDERRUN(0) or WR_UNDERRUN(1) or WR_UNDERRUN(2);
PC(1) <= WR_ERROR(0) or WR_ERROR(1) or WR_ERROR(2);
PC(2) <= RD_OVERFLOW(0) or RD_OVERFLOW(1) or RD_OVERFLOW(2);
PC(3) <= RD_ERROR(0) or RD_ERROR(1) or RD_ERROR(2);
PC(4) <= C3_CALIB_DONE;
PC(5) <= C3_RST0;
PC(6) <= RESET0;
PC(7) <= RESET;
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,18);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(25 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PA3 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,18);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(25 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
|
gpl-3.0
|
freecores/usb_fpga_2_16
|
examples/usb-fpga-1.11/1.11a/ucecho/fpga/ucecho.vhd
|
42
|
580
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ucecho is
port(
pc : in unsigned(7 downto 0);
pb : out unsigned(7 downto 0);
CLK : in std_logic
);
end ucecho;
architecture RTL of ucecho is
--signal declaration
signal pb_buf : unsigned(7 downto 0);
begin
dpUCECHO: process(CLK)
begin
if CLK' event and CLK = '1' then
if ( pc >= 97 ) and ( pc <= 122)
then
pb_buf <= pc - 32;
else
pb_buf <= pc;
end if;
pb <= pb_buf;
end if;
end process dpUCECHO;
end RTL;
|
gpl-3.0
|
DaveyPocket/btrace448
|
core/vga/outputInterface.vhd
|
1
|
1183
|
-- Btrace 448
-- Output Interface
--
-- Bradley Boccuzzi
-- 2016
library ieee;
use ieee.std_logic_1164.all;
entity outputInterface is
port(clk, rst: in std_logic;
get_pixel: out std_logic; -- Status signal
pixel_x, pixel_y: out std_logic_vector(9 downto 0); -- Address read signal
din: in std_logic_vector(11 downto 0); -- RGB in 1
overlay: in std_logic_vector(11 downto 0);-- RGB in 2
en_overlay: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(11 downto 0));
end outputInterface;
architecture arch of outputInterface is
signal video_on, p_tick: std_logic;
signal s_rgb: std_logic_vector(11 downto 0);
begin
-- VGA sync generator
vga_sync_dev: entity work.vga_sync port map(clk, rst, hsync, vsync, video_on, p_tick, pixel_x, pixel_y);
-- Pixel buffer
process(clk, rst)
begin
if rst = '1' then
s_rgb <= (others => '0');
elsif rising_edge(clk) then
s_rgb <= din;
end if;
end process;
-- Concurrent signal assignment
get_pixel <= p_tick;
--rgb <= s_rgb when overlay else x"000";
rgb <= s_rgb when ((video_on = '1') and (en_overlay = '0')) else
overlay when ((video_on and en_overlay) = '1') else x"000";
end arch;
|
gpl-3.0
|
peladex/RHD2132_FPGA
|
quartus/test_spi_de0/hex27seg.vhd
|
1
|
3043
|
---------------------------------------------------------
-- hex27seg
-- creacion 20/08/16
-- modificado de bcd27seg
-- seg_out(6 downto 0)= abcdefg
---------------------------------------------------------
-----------------------------------------------------------
----- PACKAGE pk_bcd27seg
-----------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
PACKAGE pk_hex27seg IS
COMPONENT hex27seg IS
PORT(
hex_in : IN STD_LOGIC_VECTOR(3 downto 0);
seg_out : OUT STD_LOGIC_VECTOR(6 downto 0)
);
END COMPONENT;
END PACKAGE;
-----------------------------------------------------------
----- ENTITY bcd27seg
-----------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY hex27seg IS
PORT(
hex_in : IN STD_LOGIC_VECTOR(3 downto 0);
seg_out : OUT STD_LOGIC_VECTOR(6 downto 0)
);
END hex27seg;
ARCHITECTURE synth of hex27seg IS
--constants
-- "abcdefg"
CONSTANT cero : std_logic_vector(6 DOWNTO 0):= "0000001";
CONSTANT uno : std_logic_vector(6 DOWNTO 0):= "1001111";
CONSTANT dos : std_logic_vector(6 DOWNTO 0):= "0010010";
CONSTANT tres : std_logic_vector(6 DOWNTO 0):= "0000110";
CONSTANT cuatro : std_logic_vector(6 DOWNTO 0):= "1001100";
CONSTANT cinco : std_logic_vector(6 DOWNTO 0):= "0100100";
CONSTANT seis : std_logic_vector(6 DOWNTO 0):= "0100000";
CONSTANT siete : std_logic_vector(6 DOWNTO 0):= "0001101";
CONSTANT ocho : std_logic_vector(6 DOWNTO 0):= "0000000";
CONSTANT nueve : std_logic_vector(6 DOWNTO 0):= "0000100";
CONSTANT A : std_logic_vector(6 DOWNTO 0):= "0001000";
CONSTANT b : std_logic_vector(6 DOWNTO 0):= "1100000";
CONSTANT C : std_logic_vector(6 DOWNTO 0):= "0110001";
CONSTANT d : std_logic_vector(6 DOWNTO 0):= "1000010";
CONSTANT E : std_logic_vector(6 DOWNTO 0):= "0110000";
CONSTANT F : std_logic_vector(6 DOWNTO 0):= "0111000";
BEGIN
--***********
seg_decoder:
--***********
PROCESS (hex_in)
BEGIN
CASE hex_in IS
WHEN X"0" =>
seg_out <= cero;
WHEN X"1" =>
seg_out <= uno;
WHEN X"2" =>
seg_out <= dos;
WHEN X"3" =>
seg_out <= tres;
WHEN X"4" =>
seg_out <= cuatro;
WHEN X"5" =>
seg_out <= cinco;
WHEN X"6" =>
seg_out <= seis;
WHEN X"7" =>
seg_out <= siete;
WHEN X"8" =>
seg_out <= ocho;
WHEN X"9" =>
seg_out <= nueve;
WHEN X"A" =>
seg_out <= A;
WHEN X"B" =>
seg_out <= b;
WHEN X"C" =>
seg_out <= C;
WHEN X"D" =>
seg_out <= d;
WHEN X"E" =>
seg_out <= E;
WHEN X"F" =>
seg_out <= F;
END CASE;
END PROCESS;
END synth;
|
gpl-3.0
|
freecores/usb_fpga_2_16
|
examples/usb-fpga-1.15/1.15a/memtest/fpga/memtest.vhd
|
5
|
24307
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity memtest is
port(
FXCLK : in std_logic;
RESET_IN : in std_logic;
IFCLK : in std_logic;
PC0 : in std_logic;
-- FX2 FIFO
FD : out std_logic_vector(15 downto 0);
SLOE : out std_logic;
SLRD : out std_logic;
SLWR : out std_logic;
FIFOADR0 : out std_logic;
FIFOADR1 : out std_logic;
PKTEND : out std_logic;
FLAGB : in std_logic;
-- DDR-SDRAM
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
-- mcb3_dram_odt : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end memtest;
architecture RTL of memtest is
component mem0
generic (
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 2500;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_RST_ACT_LOW : integer := 0;
C3_CALIB_SOFT_IP : string := "FALSE";
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
-- mcb3_dram_odt : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end component;
--attribute optimize : string;
--attribute optimize of counters:entity is "off";
signal fxclk_buf : std_logic;
signal CLK : std_logic;
signal RESET0 : std_logic; -- released after dcm0 is ready
signal RESET : std_logic; -- released after MCB is ready
signal DCM0_LOCKED : std_logic;
--signal DCM0_CLK_VALID : std_logic;
----------------------------
-- test pattern generator --
----------------------------
signal GEN_CNT : std_logic_vector(29 downto 0);
signal GEN_PATTERN : std_logic_vector(29 downto 0);
signal FIFO_WORD : std_logic;
-----------------------
-- memory controller --
-----------------------
signal MEM_CLK : std_logic;
signal C3_CALIB_DONE : std_logic;
signal C3_RST0 : std_logic;
---------------
-- DRAM FIFO --
---------------
signal WR_CLK : std_logic;
signal WR_CMD_EN : std_logic_vector(2 downto 0);
type WR_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal WR_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal WR_ADDR : std_logic_vector(18 downto 0); -- in 256 bytes burst blocks
signal WR_EN : std_logic_vector(2 downto 0);
signal WR_EN_TMP : std_logic_vector(2 downto 0);
signal WR_DATA : std_logic_vector(31 downto 0);
signal WR_EMPTY : std_logic_vector(2 downto 0);
signal WR_UNDERRUN : std_logic_vector(2 downto 0);
signal WR_ERROR : std_logic_vector(2 downto 0);
type WR_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal WR_COUNT : WR_COUNT_ARRAY;
signal WR_PORT : std_logic_vector(1 downto 0);
signal RD_CLK : std_logic;
signal RD_CMD_EN : std_logic_vector(2 downto 0);
type RD_CMD_ADDR_ARRAY is array(2 downto 0) of std_logic_vector(29 downto 0);
signal RD_CMD_ADDR : WR_CMD_ADDR_ARRAY;
signal RD_ADDR : std_logic_vector(18 downto 0); -- in 256 bytes burst blocks
signal RD_EN : std_logic_vector(2 downto 0);
type RD_DATA_ARRAY is array(2 downto 0) of std_logic_vector(31 downto 0);
signal RD_DATA : RD_DATA_ARRAY;
signal RD_EMPTY : std_logic_vector(2 downto 0);
signal RD_OVERFLOW : std_logic_vector(2 downto 0);
signal RD_ERROR : std_logic_vector(2 downto 0);
signal RD_PORT : std_logic_vector(1 downto 0);
type RD_COUNT_ARRAY is array(2 downto 0) of std_logic_vector(6 downto 0);
signal RD_COUNT : RD_COUNT_ARRAY;
signal FD_TMP : std_logic_vector(15 downto 0);
signal RD_ADDR2 : std_logic_vector(18 downto 0); -- 256 bytes burst block currently beeing read
signal RD_ADDR2_BAK1 : std_logic_vector(18 downto 0); -- backup for synchronization
signal RD_ADDR2_BAK2 : std_logic_vector(18 downto 0); -- backup for synchronization
signal WR_ADDR2 : std_logic_vector(18 downto 0); -- 256 bytes burst block currently beeing written
signal WR_ADDR2_BAK1 : std_logic_vector(18 downto 0); -- backup for synchronization
signal WR_ADDR2_BAK2 : std_logic_vector(18 downto 0); -- backup for synchronization
signal RD_STOP : std_logic;
begin
clkin_buf : IBUFG
port map (
O => FXCLK_BUF,
I => FXCLK
);
dcm0 : DCM_CLKGEN
generic map (
CLKFX_DIVIDE => 3,
-- CLKFX_MULTIPLY => 33,
CLKFX_MULTIPLY => 21,
CLKFXDV_DIVIDE => 8,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 20.83333,
CLKFX_MD_MAX => 0.000
)
port map (
CLKIN => FXCLK_BUF,
CLKFX => MEM_CLK,
CLKFX180 => open,
CLKFXDV => CLK,
LOCKED => DCM0_LOCKED,
PROGDONE => open,
STATUS => open,
FREEZEDCM => '0',
PROGCLK => '0',
PROGDATA => '0',
PROGEN => '0',
RST => '0'
);
inst_mem0 : mem0 port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
-- mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n=> mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
c3_sys_clk => MEM_CLK,
c3_sys_rst_n => RESET0,
c3_clk0 => open,
c3_rst0 => C3_RST0,
c3_calib_done => C3_CALIB_DONE,
c3_p0_cmd_clk => WR_CLK,
c3_p0_cmd_en => WR_CMD_EN(0),
c3_p0_cmd_instr => "000",
c3_p0_cmd_bl => ( others => '1' ),
c3_p0_cmd_byte_addr => WR_CMD_ADDR(0),
c3_p0_cmd_empty => open,
c3_p0_cmd_full => open,
c3_p0_wr_clk => WR_CLK,
c3_p0_wr_en => WR_EN(0),
c3_p0_wr_mask => ( others => '0' ),
c3_p0_wr_data => WR_DATA,
c3_p0_wr_full => open,
c3_p0_wr_empty => WR_EMPTY(0),
c3_p0_wr_count => open,
c3_p0_wr_underrun => WR_UNDERRUN(0),
c3_p0_wr_error => WR_ERROR(0),
c3_p0_rd_clk => WR_CLK,
c3_p0_rd_en => '0',
c3_p0_rd_data => open,
c3_p0_rd_full => open,
c3_p0_rd_empty => open,
c3_p0_rd_count => open,
c3_p0_rd_overflow => open,
c3_p0_rd_error => open,
c3_p2_cmd_clk => WR_CLK,
c3_p2_cmd_en => WR_CMD_EN(1),
c3_p2_cmd_instr => "000",
c3_p2_cmd_bl => ( others => '1' ),
c3_p2_cmd_byte_addr => WR_CMD_ADDR(1),
c3_p2_cmd_empty => open,
c3_p2_cmd_full => open,
c3_p2_wr_clk => WR_CLK,
c3_p2_wr_en => WR_EN(1),
c3_p2_wr_mask => ( others => '0' ),
c3_p2_wr_data => WR_DATA,
c3_p2_wr_full => open,
c3_p2_wr_empty => WR_EMPTY(1),
c3_p2_wr_count => open,
c3_p2_wr_underrun => WR_UNDERRUN(1),
c3_p2_wr_error => WR_ERROR(1),
c3_p4_cmd_clk => WR_CLK,
c3_p4_cmd_en => WR_CMD_EN(2),
c3_p4_cmd_instr => "000",
c3_p4_cmd_bl => ( others => '1' ),
c3_p4_cmd_byte_addr => WR_CMD_ADDR(2),
c3_p4_cmd_empty => open,
c3_p4_cmd_full => open,
c3_p4_wr_clk => WR_CLK,
c3_p4_wr_en => WR_EN(2),
c3_p4_wr_mask => ( others => '0' ),
c3_p4_wr_data => WR_DATA,
c3_p4_wr_full => open,
c3_p4_wr_empty => WR_EMPTY(2),
c3_p4_wr_count => open,
c3_p4_wr_underrun => WR_UNDERRUN(2),
c3_p4_wr_error => WR_ERROR(2),
c3_p1_cmd_clk => RD_CLK,
c3_p1_cmd_en => RD_CMD_EN(0),
c3_p1_cmd_instr => "001",
c3_p1_cmd_bl => ( others => '1' ),
c3_p1_cmd_byte_addr => RD_CMD_ADDR(0),
c3_p1_cmd_empty => open,
c3_p1_cmd_full => open,
c3_p1_wr_clk => RD_CLK,
c3_p1_wr_en => '0',
c3_p1_wr_mask => ( others => '0' ),
c3_p1_wr_data => ( others => '0' ),
c3_p1_wr_full => open,
c3_p1_wr_empty => open,
c3_p1_wr_count => open,
c3_p1_wr_underrun => open,
c3_p1_wr_error => open,
c3_p1_rd_clk => RD_CLK,
c3_p1_rd_en => RD_EN(0),
c3_p1_rd_data => RD_DATA(0),
c3_p1_rd_full => open,
c3_p1_rd_empty => RD_EMPTY(0),
c3_p1_rd_count => open,
c3_p1_rd_overflow => RD_OVERFLOW(0),
c3_p1_rd_error => RD_ERROR(0),
c3_p3_cmd_clk => RD_CLK,
c3_p3_cmd_en => RD_CMD_EN(1),
c3_p3_cmd_instr => "001",
c3_p3_cmd_bl => ( others => '1' ),
c3_p3_cmd_byte_addr => RD_CMD_ADDR(1),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_rd_clk => RD_CLK,
c3_p3_rd_en => RD_EN(1),
c3_p3_rd_data => RD_DATA(1),
c3_p3_rd_full => open,
c3_p3_rd_empty => RD_EMPTY(1),
c3_p3_rd_count => open,
c3_p3_rd_overflow => RD_OVERFLOW(1),
c3_p3_rd_error => RD_ERROR(1),
c3_p5_cmd_clk => RD_CLK,
c3_p5_cmd_en => RD_CMD_EN(2),
c3_p5_cmd_instr => "001",
c3_p5_cmd_bl => ( others => '1' ),
c3_p5_cmd_byte_addr => RD_CMD_ADDR(2),
c3_p5_cmd_empty => open,
c3_p5_cmd_full => open,
c3_p5_rd_clk => RD_CLK,
c3_p5_rd_en => RD_EN(2),
c3_p5_rd_data => RD_DATA(2),
c3_p5_rd_full => open,
c3_p5_rd_empty => RD_EMPTY(2),
c3_p5_rd_count => open,
c3_p5_rd_overflow => RD_OVERFLOW(2),
c3_p5_rd_error => RD_ERROR(2)
);
SLOE <= '1';
SLRD <= '1';
FIFOADR0 <= '0';
FIFOADR1 <= '0';
PKTEND <= '1';
WR_CLK <= CLK;
RD_CLK <= IFCLK;
-- DCM0_CLK_VALID <= ( DCM0_LOCKED and ( not status_internal(2) ) );
-- RESET0 <= RESET_IN or (not DCM0_LOCKED) or (not DCM0_CLK_VALID);
RESET0 <= RESET_IN or (not DCM0_LOCKED);
RESET <= RESET0 or (not C3_CALIB_DONE) or C3_RST0;
dpCLK: process (CLK, RESET)
begin
-- reset
if RESET = '1'
then
GEN_CNT <= ( others => '0' );
GEN_PATTERN <= "100101010101010101010101010101";
WR_CMD_EN <= ( others => '0' );
WR_CMD_ADDR(0) <= ( others => '0' );
WR_CMD_ADDR(1) <= ( others => '0' );
WR_CMD_ADDR(2) <= ( others => '0' );
WR_ADDR <= conv_std_logic_vector(3,19);
WR_EN <= ( others => '0' );
WR_COUNT(0) <= ( others => '0' );
WR_COUNT(1) <= ( others => '0' );
WR_COUNT(2) <= ( others => '0' );
WR_PORT <= ( others => '0' );
WR_ADDR2 <= ( others => '0' );
RD_ADDR2_BAK1 <= ( others => '0' );
RD_ADDR2_BAK2 <= ( others => '0' );
-- CLK
elsif CLK'event and CLK = '1'
then
WR_CMD_EN <= ( others => '0' );
WR_EN <= ( others => '0' );
WR_CMD_ADDR(conv_integer(WR_PORT))(26 downto 8) <= WR_ADDR;
if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(64,7) )
then
-- FF flag = 1
if ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
then
WR_CMD_EN(conv_integer(WR_PORT)) <= '1';
WR_COUNT(conv_integer(WR_PORT)) <= ( others => '0' );
if WR_PORT = "10"
then
WR_PORT <= "00";
else
WR_PORT <= WR_PORT + 1;
end if;
WR_ADDR <= WR_ADDR + 1;
WR_ADDR2 <= WR_ADDR2 + 1;
end if;
elsif ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(0,7)) and (WR_EMPTY(conv_integer(WR_PORT)) = '0' ) -- write port fifo not empty
then
-- FF flag = 1
else
WR_EN(conv_integer(WR_PORT)) <= '1';
WR_DATA(31) <= '1';
WR_DATA(15) <= '0';
if PC0 = '1'
then
WR_DATA(30 downto 16) <= GEN_PATTERN(29 downto 15);
WR_DATA(14 downto 0) <= GEN_PATTERN(14 downto 0);
else
WR_DATA(30 downto 16) <= GEN_CNT(29 downto 15);
WR_DATA(14 downto 0) <= GEN_CNT(14 downto 0);
end if;
GEN_CNT <= GEN_CNT + 1;
GEN_PATTERN(29) <= GEN_PATTERN(0);
GEN_PATTERN(28 downto 0) <= GEN_PATTERN(29 downto 1);
-- if ( WR_COUNT(conv_integer(WR_PORT)) = conv_std_logic_vector(63,7) ) and ( RD_ADDR2_BAK1 = RD_ADDR2_BAK2 ) and ( RD_ADDR2_BAK2 /= WR_ADDR )
-- Add code from above here. This saves one clock cylcle and is required for uninterrupred input.
-- then
-- else
WR_COUNT(conv_integer(WR_PORT)) <= WR_COUNT(conv_integer(WR_PORT)) + 1;
-- end if;
end if;
RD_ADDR2_BAK1 <= RD_ADDR2;
RD_ADDR2_BAK2 <= RD_ADDR2_BAK1;
end if;
end process dpCLK;
dpIFCLK: process (IFCLK, RESET)
begin
-- reset
if RESET = '1'
then
FIFO_WORD <= '0';
SLWR <= '1';
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(0) <= ( others => '0' );
RD_CMD_ADDR(1) <= ( others => '0' );
RD_CMD_ADDR(2) <= ( others => '0' );
RD_ADDR <= conv_std_logic_vector(3,19);
RD_EN <= ( others => '0' );
RD_COUNT(0) <= conv_std_logic_vector(64,7);
RD_COUNT(1) <= conv_std_logic_vector(64,7);
RD_COUNT(2) <= conv_std_logic_vector(64,7);
RD_PORT <= ( others => '0' );
RD_ADDR2 <= ( others => '0' );
WR_ADDR2_BAK1 <= ( others => '0' );
WR_ADDR2_BAK2 <= ( others => '0' );
RD_STOP <= '1';
-- IFCLK
elsif IFCLK'event and IFCLK = '1'
then
RD_CMD_EN <= ( others => '0' );
RD_CMD_ADDR(conv_integer(RD_PORT))(26 downto 8) <= RD_ADDR;
RD_EN(conv_integer(RD_PORT)) <= '0';
if FLAGB = '1'
then
if ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) or ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) )
then
SLWR <= '1';
if ( RD_COUNT(conv_integer(RD_PORT)) = conv_std_logic_vector(64,7) ) and ( RD_EMPTY(conv_integer(RD_PORT)) = '1' ) and ( WR_ADDR2_BAK2 = WR_ADDR2_BAK1 ) and ( WR_ADDR2_BAK2 /= RD_ADDR ) and ( RD_STOP = '0' )
then
RD_CMD_EN(conv_integer(RD_PORT)) <= '1';
RD_COUNT(conv_integer(RD_PORT)) <= ( others => '0' );
if RD_PORT = "10"
then
RD_PORT <= "00";
else
RD_PORT <= RD_PORT + 1;
end if;
RD_ADDR <= RD_ADDR + 1;
RD_ADDR2 <= RD_ADDR2 + 1;
end if;
else
SLWR <= '0';
if FIFO_WORD = '0'
then
FD(15 downto 0) <= RD_DATA(conv_integer(RD_PORT))(15 downto 0);
FD_TMP <= RD_DATA(conv_integer(RD_PORT))(31 downto 16);
RD_EN(conv_integer(RD_PORT)) <= '1';
else
FD(15 downto 0) <= FD_TMP;
RD_COUNT(conv_integer(RD_PORT)) <= RD_COUNT(conv_integer(RD_PORT)) + 1;
end if;
FIFO_WORD <= not FIFO_WORD;
end if;
end if;
WR_ADDR2_BAK1 <= WR_ADDR2;
WR_ADDR2_BAK2 <= WR_ADDR2_BAK1;
if ( WR_ADDR2_BAK1 = WR_ADDR2_BAK2 ) and ( WR_ADDR2_BAK2(3) = '1')
then
RD_STOP <= '0';
end if;
end if;
end process dpIFCLK;
end RTL;
|
gpl-3.0
|
peladex/RHD2132_FPGA
|
quartus/test_spi_comm/test_spi_side.vhd
|
2
|
8462
|
-----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 09/11/2016 -- dd/mm/yyyy
-- Module Name: test_spi_side
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- ...
--
-----------------------------------------------------------------------------------------------------------------------
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY test_spi_side IS
PORT(
m_clk : in std_logic; -- master clock
m_reset : in std_logic; -- master reset
---- master_control interface ----
di_1_i : in std_logic_vector(15 downto 0);
do_1_o : out std_logic_vector(15 downto 0);
wren_1_i : in std_logic;
drdy_1_o : out std_logic;
rdreq_1_i : in std_logic;
di_2_i : in std_logic_vector(15 downto 0);
do_2_o : out std_logic_vector(15 downto 0);
wren_2_i : in std_logic;
drdy_2_o : out std_logic;
rdreq_2_i : in std_logic;
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic;
---- serial interface 1 ----
spi1_ssel_o : out std_logic; -- spi bus slave select line
spi1_sck_o : out std_logic; -- spi bus sck
spi1_mosi_o : out std_logic; -- spi bus mosi output
spi1_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- serial interface 2 ----
spi2_ssel_o : out std_logic; -- spi bus slave select line
spi2_sck_o : out std_logic; -- spi bus sck
spi2_mosi_o : out std_logic; -- spi bus mosi output
spi2_miso_i : in std_logic := 'X' -- spi bus spi_miso_i input
);
END test_spi_side;
ARCHITECTURE synth OF test_spi_side IS
---- COMPONENTS
COMPONENT interconnect IS
PORT (
---- master_control interface ----
di_1_i : in std_logic_vector(15 downto 0);
do_1_o : out std_logic_vector(15 downto 0);
wren_1_i : in std_logic; --triggers spi cycle
drdy_1_o : out std_logic;
rdreq_1_i : in std_logic;
di_2_i : in std_logic_vector(15 downto 0);
do_2_o : out std_logic_vector(15 downto 0);
wren_2_i : in std_logic; --triggers spi cycle
drdy_2_o : out std_logic;
rdreq_2_i : in std_logic;
---- spi 1 interface ----
s1_do_o : out std_logic_vector(15 downto 0);
s1_di_i : in std_logic_vector(15 downto 0);
s1_wren_o : out std_logic;
s1_drdy_i : in std_logic;
---- spi 2 interface ----
s2_do_o : out std_logic_vector(15 downto 0);
s2_di_i : in std_logic_vector(15 downto 0);
s2_wren_o : out std_logic;
s2_drdy_i : in std_logic;
---- fifo 1 interface ----
f1_do_o : out std_logic_vector(15 downto 0);
f1_wren_o : out std_logic;
---- fifo 2 interface ----
f2_do_o : out std_logic_vector(15 downto 0);
f2_wren_o : out std_logic
);
END COMPONENT;
COMPONENT spi_master IS
Generic (
N : positive := 16; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 2); -- for a 100MHz sclk_i, yields a 25MHz SCK
Port (
sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
rst_i : in std_logic := 'X'; -- reset core
---- serial interface ----
spi_ssel_o : out std_logic; -- spi bus slave select line
spi_sck_o : out std_logic; -- spi bus sck
spi_mosi_o : out std_logic; -- spi bus mosi output
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- parallel interface ----
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
--- debug ports: can be removed or left unconnected for the application circuit ---
sck_ena_o : out std_logic; -- debug: internal sck enable signal
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
core_n_ce_o : out std_logic;
sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register
);
END COMPONENT;
---- SIGNALS
SIGNAL sg_pll_out_clk : std_logic;
SIGNAL sg_do_1, sg_di_1 : std_logic_vector(15 downto 0);
SIGNAL sg_wren_1, sg_drdy_1 : std_logic;
SIGNAL sg_do_2, sg_di_2 : std_logic_vector(15 downto 0);
SIGNAL sg_wren_2, sg_drdy_2 : std_logic;
BEGIN
---- INSTANCES
U0: interconnect PORT MAP (
---- master_control interface ----
di_1_i => di_1_i,
do_1_o => do_1_o,
wren_1_i => wren_1_i,
drdy_1_o => drdy_1_o,
rdreq_1_i => rdreq_1_i,
di_2_i => di_2_i,
do_2_o => do_2_o,
wren_2_i => wren_2_i,
drdy_2_o => drdy_2_o,
rdreq_2_i => rdreq_2_i,
---- spi 1 interface ----
s1_do_o => sg_do_1,
s1_di_i => sg_di_1,
s1_wren_o => sg_wren_1,
s1_drdy_i => sg_drdy_1,
---- spi 2 interface ----
s2_do_o => sg_do_2,
s2_di_i => sg_di_2,
s2_wren_o => sg_wren_2,
s2_drdy_i => sg_drdy_2,
---- fifo 1 interface ----
f1_do_o => f1_do_o,
f1_wren_o => f1_wren_o,
---- fifo 2 interface ----
f2_do_o => f2_do_o,
f2_wren_o => f2_wren_o
);
SPI_1: spi_master PORT MAP (
sclk_i => sg_pll_out_clk,
pclk_i => sg_pll_out_clk,
rst_i => m_reset,
---- serial interface ----
spi_ssel_o => spi1_ssel_o,
spi_sck_o => spi1_sck_o,
spi_mosi_o => spi1_mosi_o,
spi_miso_i => spi1_miso_i,
---- parallel interface ----
di_i => sg_do_1,
wren_i => sg_wren_1,
do_valid_o => sg_drdy_1,
do_o => sg_di_1
);
SPI_2: spi_master PORT MAP (
sclk_i => sg_pll_out_clk,
pclk_i => sg_pll_out_clk,
rst_i => m_reset,
---- serial interface ----
spi_ssel_o => spi2_ssel_o,
spi_sck_o => spi2_sck_o,
spi_mosi_o => spi2_mosi_o,
spi_miso_i => spi2_miso_i,
---- parallel interface ----
di_i => sg_do_2,
wren_i => sg_wren_2,
do_valid_o => sg_drdy_2,
do_o => sg_di_2
);
sg_pll_out_clk <= m_clk;
END synth;
|
gpl-3.0
|
scottlbaker/PDP11-SOC
|
src/cmpr.vhd
|
1
|
1149
|
--========================================================================
-- cmpr.vhd :: 4-bit comparator
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity CMPR is
port (
A_LE_B : out std_logic; -- A <= B
A : in std_logic_vector(3 downto 0); -- operand A
B : in std_logic_vector(3 downto 0) -- operand B
);
end CMPR;
architecture BEHAVIORAL of CMPR is
signal P : std_logic_vector(3 downto 0);
signal G : std_logic_vector(3 downto 0);
signal CX : std_logic_vector(3 downto 1);
begin
--=====================================
-- Propagate and Generate
--=====================================
G <= (not A(3 downto 0)) and B(3 downto 0);
P <= (not A(3 downto 0)) or B(3 downto 0);
A_LE_B <= G(3) or (P(3) and CX(3));
CX(3) <= G(2) or (P(2) and CX(2));
CX(2) <= G(1) or (P(1) and CX(1));
CX(1) <= G(0) or P(0);
end BEHAVIORAL;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc_addr_gen.vhd
|
4
|
23323
|
-------------------------------------------------------------------------------
-- axi_emc_addr_gen - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc_addr_gen.vhd
-- Version: v2.0
-- Description: This file includes the logic for address generataion on
-- IP interface based upon the AXI transactions.
-------------------------------------------------------------------------------
-- Structure:
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: SK
--
-- History:
-- SK 10/02/10
-- ~~~~~~
-- -- Created the new version v1.01.a
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
use ieee.std_logic_misc.and_reduce;
-------------------------------------------------------------------------------
entity axi_emc_addr_gen is
generic(
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer range 32 to 64 := 32
);
port(
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Cre_reg_en : in std_logic;
-- combo I/P signals
stop_addr_incr : in std_logic;
Store_addr_info_cmb : in std_logic;
Addr_int_cmb : in std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0);
Ip2Bus_Addr_ack : in std_logic;
Fifo_full_1 : in std_logic;
derived_len_reg : in std_logic_vector(3 downto 0);
Rst_Rd_CE : in std_logic;
-- registered signals
Derived_burst_reg : in std_logic_vector(1 downto 0);
Derived_size_reg : in std_logic_vector(1 downto 0);
-- registered O/P signals
Bus2IP_Addr : out std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1)downto 0)
);
end entity axi_emc_addr_gen;
-----------------------
------------------------------------
architecture imp of axi_emc_addr_gen is
------------------------------------
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
constant ACTIVE_LOW_RESET : integer := 0;
signal bus2ip_addr_i : std_logic_vector
((C_S_AXI_MEM_ADDR_WIDTH-1) downto ((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1)) := (OTHERS => '0');
signal int_addr_enable_11_2 : std_logic;
signal addr_sel_0 : std_logic;
signal addr_sel_1 : std_logic;
signal addr_sel_2 : std_logic;
signal addr_sel_3 : std_logic;
signal Bus2IP_Addr_lower_bits_reg_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits_cmb_i : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
signal Bus2IP_Addr_lower_bits : std_logic_vector(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
-----
begin
-----
---====================---
--*** axi_emc_addr_gen logic ***--
---====================---
--bus2ip_addr_i (0) <= '0';
--bus2ip_addr_i (1) <= '0';
Bus2IP_Addr <= bus2ip_addr_i((C_S_AXI_MEM_ADDR_WIDTH-1) downto (clog2(C_S_AXI_MEM_DATA_WIDTH/8))) & Bus2IP_Addr_lower_bits;
Bus2IP_Addr_lower_bits <= Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0)
when Cre_reg_en = '0'
else
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
----------- all addresses are word/dword aligned addresses, only the BE decide
-- which byte lane to be accessed
Bus2IP_Addr_lower_bits_cmb_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
---------------------------------------------------------------------------------
-- ADDR_BITS_LAST_3_OR_3_BITS_REG_P: Address registering for lower 3 or 2 bits
---------------------
ADDR_BITS_LAST_3_OR_3_BITS_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
Bus2IP_Addr_lower_bits_reg_i(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0) <= Addr_int_cmb(((clog2(C_S_AXI_MEM_DATA_WIDTH/8))-1) downto 0);
end if;
end if;
end process ADDR_BITS_LAST_3_OR_3_BITS_REG_P;
----------------------------------
-- ADDR_BITS_31_12_REG_P: Address registering for upper order address bits
---------------------
ADDR_BITS_31_12_REG_P:process(Bus2IP_Clk)
---------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(31 downto 12) <= (others => '0');
elsif(Store_addr_info_cmb = '1')then
bus2ip_addr_i(31 downto 12) <= Addr_int_cmb(31 downto 12);
end if;
end if;
end process ADDR_BITS_31_12_REG_P;
----------------------------------
int_addr_enable_11_2 <= ( Store_addr_info_cmb
or
(Ip2Bus_Addr_ack and
(not Fifo_full_1) and (not stop_addr_incr)
)
);
----------- Below are the select line for MUX operation
addr_sel_0 <= (derived_len_reg(0) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_1 <= (derived_len_reg(1) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_2 <= (derived_len_reg(2) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
addr_sel_3 <= (derived_len_reg(3) and Derived_burst_reg(1))
or
Derived_burst_reg(0);
-----------
--------------------------------------
--BUS2IP_ADDR_GEN_DATA_WDTH_32:Address geenration for logic for 32 bit data bus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_32: if C_S_AXI_MEM_DATA_WIDTH = 32 generate
----------------------------
-- address(2) calculation
signal calc_addr_2: std_logic_vector(1 downto 0);
signal addr_2_int : std_logic;
signal addr_2_cmb : std_logic;
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(11:6) calculation
signal calc_addr_11_6: std_logic_vector(6 downto 0);
signal addr_11_6_int : std_logic_vector(5 downto 0);
signal addr_11_6_cmb : std_logic_vector(5 downto 0);
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic_vector(1 downto 0);
signal addr_6_cmb : std_logic_vector(1 downto 0);
signal address_carry : std_logic;
signal internal_count : std_logic_vector(2 downto 0) :=(others => '0');
-----
begin
-----
-------------------
-- INT_COUNTER_P32: to store the the internal address lower bits
-------------------
INT_COUNTER_P32: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb='1') then
internal_count <= '0' & Addr_int_cmb(1 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end process INT_COUNTER_P32;
-------------------
address_Carry <= Derived_size_reg(1) or
(Derived_size_reg(0) and internal_count(1))or
(internal_count(0) and internal_count(1));
calc_addr_2 <= ('0' & bus2ip_addr_i(2)) + ('0' & address_Carry);
addr_2_int <= calc_addr_2(0) when (addr_sel_0='1') else bus2ip_addr_i(2);
addr_2_cmb <= Addr_int_cmb(2) when (Store_addr_info_cmb='1') else addr_2_int;
-- ADDR_BITS_2_REG_P: store the 2nd address bit
------------------
ADDR_BITS_2_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(2) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(2) <= addr_2_cmb;
end if;
end if;
end process ADDR_BITS_2_REG_P;
------------------
calc_addr_3 <= ('0' & bus2ip_addr_i(3)) + ('0' & calc_addr_2(1));
addr_3_int <= calc_addr_3(0) when (addr_sel_1='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the third address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_2='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store the 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & bus2ip_addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_3='1') else bus2ip_addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P:store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_11_6 <= ('0'& bus2ip_addr_i(11 downto 6)) +
("000000" & calc_addr_5(1));
addr_11_6_int <= calc_addr_11_6(5 downto 0) when (Derived_burst_reg(0)='1')
else
bus2ip_addr_i(11 downto 6);
addr_11_6_cmb <= Addr_int_cmb(11 downto 6) when(Store_addr_info_cmb='1')
else
addr_11_6_int(5 downto 0);
-- ADDR_BITS_11_6_REG_P: store the 11 to 6 address bits
--------------------
ADDR_BITS_11_6_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if((Bus2IP_Resetn = '0')) then
bus2ip_addr_i(11 downto 6) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 6) <= addr_11_6_cmb(5 downto 0);
end if;
end if;
end process ADDR_BITS_11_6_REG_P;
---------------------------------
------------------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_32;
------------------------------------------
-- BUS2IP_ADDR_GEN_DATA_WDTH_64: below address logic is used for 64 bit dbus
-- ============================
BUS2IP_ADDR_GEN_DATA_WDTH_64: if C_S_AXI_MEM_DATA_WIDTH = 64 generate
-- address(3) calculation
signal calc_addr_3: std_logic_vector(1 downto 0);
signal addr_3_int : std_logic;
signal addr_3_cmb : std_logic;
-- address(4) calculation
signal calc_addr_4: std_logic_vector(1 downto 0);
signal addr_4_int : std_logic;
signal addr_4_cmb : std_logic;
-- address(5) calculation
signal calc_addr_5: std_logic_vector(1 downto 0);
signal addr_5_int : std_logic;
signal addr_5_cmb : std_logic;
-- address(6) calculation
signal calc_addr_6: std_logic_vector(1 downto 0);
signal addr_6_int : std_logic;
signal addr_6_cmb : std_logic;
-- address(7) calculation
signal calc_addr_7: std_logic_vector(1 downto 0);
signal addr_7_int : std_logic;
signal addr_7_cmb : std_logic;
-- address(11:7) calculation
signal calc_addr_11_7: std_logic_vector(5 downto 0);
signal addr_11_7_int : std_logic_vector(4 downto 0);
signal addr_11_7_cmb : std_logic_vector(4 downto 0);
signal address_carry : std_logic;
signal internal_count: std_logic_vector(3 downto 0):=(others => '0');
-----
begin
-----
--------------------
-- INT_COUNTER_P64: to store the internal address bits
--------------------
INT_COUNTER_P64: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Store_addr_info_cmb = '1') then
internal_count <= '0' & Addr_int_cmb(2 downto 0);
elsif(
(Ip2Bus_Addr_ack='1') and
(Fifo_full_1='0')
)then
if(Derived_size_reg(1) = '1') then
internal_count <= internal_count + "100";
else
internal_count <= internal_count + Derived_size_reg + '1';
end if;
end if;
end if;
end process INT_COUNTER_P64;
----------------------------
address_Carry<=(Derived_size_reg(1) and Derived_size_reg(0)) or -- for double word
(Derived_size_reg(1) and internal_count(2) ) or -- for word
(Derived_size_reg(0) and
internal_count(2) and
internal_count(1)
)or -- for half word
(internal_count(2) and
internal_count(1) and
internal_count(0)
); -- for byte
calc_addr_3 <= ('0' & Bus2IP_Addr_i(3)) + ('0' & address_Carry);
addr_3_int <= calc_addr_3(0) when (addr_sel_0='1') else bus2ip_addr_i(3);
addr_3_cmb <= Addr_int_cmb(3) when (Store_addr_info_cmb='1') else addr_3_int;
-- ADDR_BITS_3_REG_P: store the 3rd address bit
------------------
ADDR_BITS_3_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0'))) then
bus2ip_addr_i(3) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(3) <= addr_3_cmb;
end if;
end if;
end process ADDR_BITS_3_REG_P;
------------------
calc_addr_4 <= ('0' & bus2ip_addr_i(4)) + ('0' & calc_addr_3(1));
addr_4_int <= calc_addr_4(0) when (addr_sel_1='1') else bus2ip_addr_i(4);
addr_4_cmb <= Addr_int_cmb(4) when (Store_addr_info_cmb='1') else addr_4_int;
-- ADDR_BITS_4_REG_P: store teh 4th address bit
------------------
ADDR_BITS_4_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(4) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(4) <= addr_4_cmb;
end if;
end if;
end process ADDR_BITS_4_REG_P;
------------------
calc_addr_5 <= ('0' & Bus2IP_Addr_i(5)) + ('0' & calc_addr_4(1));
addr_5_int <= calc_addr_5(0) when (addr_sel_2='1') else Bus2IP_Addr_i(5);
addr_5_cmb <= Addr_int_cmb(5) when (Store_addr_info_cmb='1') else addr_5_int;
-- ADDR_BITS_5_REG_P: store the 5th address bit
------------------
ADDR_BITS_5_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(5) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(5) <= addr_5_cmb;
end if;
end if;
end process ADDR_BITS_5_REG_P;
------------------
calc_addr_6 <= ('0' & Bus2IP_Addr_i(6)) + ('0' & calc_addr_5(1));
addr_6_int <= calc_addr_6(0) when (addr_sel_3='1') else Bus2IP_Addr_i(6);
addr_6_cmb <= Addr_int_cmb(6) when (Store_addr_info_cmb='1') else addr_6_int;
-- ADDR_BITS_6_REG_P: store the 6th address bit
------------------
ADDR_BITS_6_REG_P:process(Bus2IP_Clk)
------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(6) <= '0';
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(6) <= addr_6_cmb;
end if;
end if;
end process ADDR_BITS_6_REG_P;
------------------
calc_addr_11_7 <= ('0' & Bus2IP_Addr_i(11 downto 7))
+ ("00000" & calc_addr_6(1));
addr_11_7_int <= calc_addr_11_7(4 downto 0) when (Derived_burst_reg(0)='1')
else
Bus2IP_Addr_i(11 downto 7);
addr_11_7_cmb <= Addr_int_cmb(11 downto 7) when(Store_addr_info_cmb='1')
else
addr_11_7_int(4 downto 0);
-- ADDR_BITS_11_7_REG_P: store the 11 to 7 address bits
--------------------
ADDR_BITS_11_7_REG_P:process(Bus2IP_Clk)
--------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(((Bus2IP_Resetn = '0')) ) then
bus2ip_addr_i(11 downto 7) <= (others => '0');
elsif(int_addr_enable_11_2 = '1')then
bus2ip_addr_i(11 downto 7) <= addr_11_7_cmb(4 downto 0);
end if;
end if;
end process ADDR_BITS_11_7_REG_P;
---------------------------------
end generate BUS2IP_ADDR_GEN_DATA_WDTH_64;
-------------------------------------------------------------------------------
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/mdm_primitives.vhd
|
4
|
7680
|
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_primitives.vhd
--
-- Description: one bit AND function using carry-chain
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2014-05-23 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_and is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_and;
architecture IMP of carry_and is
signal carry_out_i : std_logic;
begin -- architecture IMP
MUXCY_I : MUXCY_L
port map (
DI => '0',
CI => Carry_IN,
S => A,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library IEEE;
use IEEE.std_logic_1164.all;
entity carry_or_vec is
generic (
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end entity carry_or_vec;
library unisim;
use unisim.vcomponents.all;
architecture IMP of carry_or_vec is
constant C_BITS_PER_LUT : natural := 6;
signal sel : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT) - 1);
signal carry : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT));
signal sig1 : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
begin -- architecture IMP
assign_sigs : process (In_Vec) is
begin -- process assign_sigs
sig1 <= (others => '0');
sig1(0 to Size-1) <= In_Vec;
end process assign_sigs;
carry(carry'right) <= Carry_In;
The_Compare : for I in sel'right downto sel'left generate
begin
Compare_All_Bits: process(sig1)
variable sel_I : std_logic;
begin
sel_I := '0';
Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
sel_I := sel_I or ( sig1(C_BITS_PER_LUT * I + J) );
end loop Compare_Bits;
sel(I) <= not sel_I;
end process Compare_All_Bits;
MUXCY_L_I1 : MUXCY_L
port map (
DI => '1', -- [in std_logic S = 0]
CI => Carry(I+1), -- [in std_logic S = 1]
S => sel(I), -- [in std_logic (Select)]
LO => Carry(I)); -- [out std_logic]
end generate The_Compare;
Carry_Out <= Carry(0);
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_or is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_or;
architecture IMP of carry_or is
signal carry_out_i : std_logic;
signal A_N : std_logic;
begin -- architecture IMP
A_N <= not A;
MUXCY_I : MUXCY_L
port map (
DI => '1',
CI => Carry_IN,
S => A_N,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity select_bit is
generic (
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end entity select_bit;
architecture IMP of select_bit is
signal di : std_logic;
signal sel : std_logic;
begin -- architecture IMP
-- Just pass the carry value if none is requesting or is enabled
sel <= not( (Request(1) and Mask(1)) or (Request(0) and Mask(0)));
di <= ((Request(0) and Mask(0) and sel_value(0))) or
( not(Request(0) and Mask(0)) and Request(1) and Mask(1) and sel_value(1));
MUXCY_I : MUXCY_L
port map (
DI => di,
CI => Carry_In,
S => sel,
LO => Carry_Out);
end architecture IMP;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mdm_v3_2/fbb28dda/hdl/vhdl/mdm_primitives.vhd
|
4
|
7680
|
-------------------------------------------------------------------------------
-- mdm_primitives.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: mdm_primitives.vhd
--
-- Description: one bit AND function using carry-chain
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- mdm_primitives.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
--
-- History:
-- stefana 2014-05-23 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_and is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_and;
architecture IMP of carry_and is
signal carry_out_i : std_logic;
begin -- architecture IMP
MUXCY_I : MUXCY_L
port map (
DI => '0',
CI => Carry_IN,
S => A,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library IEEE;
use IEEE.std_logic_1164.all;
entity carry_or_vec is
generic (
Size : natural);
port (
Carry_In : in std_logic;
In_Vec : in std_logic_vector(0 to Size-1);
Carry_Out : out std_logic);
end entity carry_or_vec;
library unisim;
use unisim.vcomponents.all;
architecture IMP of carry_or_vec is
constant C_BITS_PER_LUT : natural := 6;
signal sel : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT) - 1);
signal carry : std_logic_vector(0 to ((Size+(C_BITS_PER_LUT - 1))/C_BITS_PER_LUT));
signal sig1 : std_logic_vector(0 to sel'length*C_BITS_PER_LUT - 1);
begin -- architecture IMP
assign_sigs : process (In_Vec) is
begin -- process assign_sigs
sig1 <= (others => '0');
sig1(0 to Size-1) <= In_Vec;
end process assign_sigs;
carry(carry'right) <= Carry_In;
The_Compare : for I in sel'right downto sel'left generate
begin
Compare_All_Bits: process(sig1)
variable sel_I : std_logic;
begin
sel_I := '0';
Compare_Bits: for J in C_BITS_PER_LUT - 1 downto 0 loop
sel_I := sel_I or ( sig1(C_BITS_PER_LUT * I + J) );
end loop Compare_Bits;
sel(I) <= not sel_I;
end process Compare_All_Bits;
MUXCY_L_I1 : MUXCY_L
port map (
DI => '1', -- [in std_logic S = 0]
CI => Carry(I+1), -- [in std_logic S = 1]
S => sel(I), -- [in std_logic (Select)]
LO => Carry(I)); -- [out std_logic]
end generate The_Compare;
Carry_Out <= Carry(0);
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity carry_or is
port (
Carry_IN : in std_logic;
A : in std_logic;
Carry_OUT : out std_logic);
end entity carry_or;
architecture IMP of carry_or is
signal carry_out_i : std_logic;
signal A_N : std_logic;
begin -- architecture IMP
A_N <= not A;
MUXCY_I : MUXCY_L
port map (
DI => '1',
CI => Carry_IN,
S => A_N,
LO => carry_out_i);
Carry_OUT <= carry_out_i;
end architecture IMP;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity select_bit is
generic (
sel_value : std_logic_vector(1 downto 0));
port (
Mask : in std_logic_vector(1 downto 0);
Request : in std_logic_vector(1 downto 0);
Carry_In : in std_logic;
Carry_Out : out std_logic);
end entity select_bit;
architecture IMP of select_bit is
signal di : std_logic;
signal sel : std_logic;
begin -- architecture IMP
-- Just pass the carry value if none is requesting or is enabled
sel <= not( (Request(1) and Mask(1)) or (Request(0) and Mask(0)));
di <= ((Request(0) and Mask(0) and sel_value(0))) or
( not(Request(0) and Mask(0)) and Request(1) and Mask(1) and sel_value(1));
MUXCY_I : MUXCY_L
port map (
DI => di,
CI => Carry_In,
S => sel,
LO => Carry_Out);
end architecture IMP;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/addr_counter_mux.vhd
|
4
|
35347
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: addr_counter_mux.vhd-- Description:
-- This file contains the addr_counter and mux for the EMC
-- design.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 02/12/08 Updated
-- ^^^^^^^^
-- Removed the unused part of code (not supporting C_IPIF_DWIDTH = 64): -
-- 1. Deleted the generate block lebelled "CYCLE_END_CNT_64_GEN".
-- 2. In the process "ADDR_SUFFIX_PROCESS" deleted the part of code as
-- C_ADDR_OFFSET = 3 is valid only when C_IPIF_DWIDTH = 64 is supported.
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
--
-- KSB 05/08/08 version v4_00_a
-- 1. Modified for Page mdoe read
-- 2. Modified for 64 Bit memory address align
-- ~~~~~~~~
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- vcomponents package of the unisim library is used for the FDR and FDCE
-- component declaration
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library emc_common_v3_0;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_ADDR_CNTR_WIDTH -- Width of address counter
-- C_IPIF_AWIDTH -- Width of IPIF address bus
-- C_IPIF_DWIDTH -- Width of IPIF data bus
-- C_ADDR_OFFSET -- Unused lower address bits based on data
-- width
-- C_GLOBAL_DATAWIDTH_MATCH-- Indicates whether any memory bank is
-- supporting data width matching
--
-- Definition of Ports:
-- Bus2IP_Addr -- Processor address bus
-- Bus2IP_BE -- Processor bus byte enables
-- Address_strobe -- Address strobe signal
-- Data_strobe -- Data and BEs strobe signal
-- Mem_width_bytes -- Width in bytes of currently addressed
-- memory bank
-- Datawidth_match -- Data width matching for currently addressed
-- memory bank
-- Addr_cnt_ce -- Address counter count enable
-- Addr_cnt_rst -- Address counter reset
-- Addr_cnt -- Address count
-- Cycle_cnt_ld -- Cycle end counter count load
-- Cycle_cnt_en -- Cycle end counter count enable
-- Cycle_end -- Current cycle end flag
-- Mem_addr -- Address out to memory
-- Mem_Ben -- Memory byte enables
-- Clk -- System Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity addr_counter_mux is
generic(
C_ADDR_CNTR_WIDTH : integer range 1 to 5;
C_IPIF_AWIDTH : integer;
C_IPIF_DWIDTH : integer;
C_ADDR_OFFSET : integer range 0 to 4;
PARITY_TYPE_MEMORY : integer range 0 to 1 := 1;
C_GLOBAL_DATAWIDTH_MATCH : integer range 0 to 1
);
port(
Clk : in std_logic;
Rst : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Address_strobe : in std_logic; -- 07-12-2012
--Data_strobe : in std_logic;09-12-2012
Bus2Mem_CS : in std_logic;
Mem_width_bytes : in std_logic_vector(0 to 3);
Datawidth_match : in std_logic;
Addr_cnt_ce : in std_logic;
Addr_cnt_rst : in std_logic;
Addr_cnt : out std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
Addr_align : out std_logic;
Cycle_cnt_ld : in std_logic;
Cycle_cnt_en : in std_logic;
Cycle_End : out std_logic;
CS_par_addr : in std_logic;
Mem_addr : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
par_error_addr : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
Mem_Ben : out std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_RdReq : in std_logic;
address_strobe_c : in std_logic;
be_strobe_c : in std_logic;
data_strobe_c : in std_logic;
Cre_reg_en : in std_logic; -- 1/16/2013
psram_page_mode : in std_logic;
axi_trans_size_reg : in std_logic_vector(1 downto 0)
);
end entity addr_counter_mux;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of addr_counter_mux is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- reset values
constant ZERO_CYCLE_CNT : std_logic_vector(0 to (log2(C_IPIF_DWIDTH/8)-1))
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal addr_cnt_i : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_suffix : std_logic_vector(0 to C_ADDR_OFFSET-1)
:= (others => '0');
signal addr_cnt_val : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal cycle_cnt : std_logic_vector(0 to (log2(C_IPIF_DWIDTH/8)-1));
signal cycle_end_cnt : std_logic_vector(0 to (log2(C_IPIF_DWIDTH/8)-1));
signal int_addr : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal Mem_Ben_i : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal mem_addr_cmb : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal addr_cnt_cmb : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_align_32_64 : std_logic;
signal reduced_low_be : std_logic;
signal reduced_high_be : std_logic;
signal reduced_16_0_be : std_logic;
signal reduced_16_1_be : std_logic;
signal reduced_16_2_be : std_logic;
signal reduced_16_3_be : std_logic;
signal par_error_addr_reg: std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal Cycle_End_reg : std_logic;
signal Cycle_cnt_en_int : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Store the address coming from bus as address ack and data ack are issued
-- early to make burst appear as continuous on memory side.
---------------------------------------------------------------------------
Mem_Ben <= Mem_Ben_i;
ADDRESS_STORE_GEN: for i in 0 to C_IPIF_AWIDTH - 1 generate
begin
ADDRESS_REG: FDRE
port map (
Q => int_addr(i), --[out]
C => Clk, --[in]
CE => address_strobe_c,--Data_strobe, --[in]
D => Bus2IP_Addr(i), --[in]
R => Rst --[in]
);
end generate ADDRESS_STORE_GEN;
---------------------------------------------------------------------------
-- Store the Byte Enables coming from bus as address ack and data ack are
-- issued early to make burst appear as continuous one on memory side.
---------------------------------------------------------------------------
BEN_STORE_GEN: for i in 0 to C_IPIF_DWIDTH/8-1 generate
begin
BEN_REG: FDRE
port map (
Q => Mem_Ben_i(i), --[out]
C => Clk, --[in]
CE => be_strobe_c,--Data_strobe, --[in]
D => Bus2IP_BE(i), --[in]
R => Rst --[in]
);
end generate BEN_STORE_GEN;
---------------------------------------------------------------------------
-- Address and address count generation logic.
---------------------------------------------------------------------------
Mem_addr <= mem_addr_cmb ;
Addr_cnt <= addr_cnt_cmb;
PARITY_ERROR_GEN: if PARITY_TYPE_MEMORY = 1 generate
par_error_addr <= Bus2IP_Addr when CS_par_addr='1'
else
par_error_addr_reg;
PARITY_ERROR_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1') then
if(Rst = '1')then
par_error_addr_reg <= (others=>'0');
elsif CS_par_addr = '1' then
par_error_addr_reg <= Bus2IP_Addr;
end if;
end if;
end process PARITY_ERROR_PROCESS;
end generate PARITY_ERROR_GEN;
---------------------------------------------------------------------------
---------------------------- NO DATAWIDTH MATCHING ------------------------
-- If datawidth matching has not been turned on for any memory banks,
-- simplify the logic.
---------------------------------------------------------------------------
NO_DATAWIDTH_MATCH_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
begin
addr_cnt_cmb <= (others => '0');
mem_addr_cmb <= int_addr;
Cycle_End <= '1';
end generate NO_DATAWIDTH_MATCH_GEN;
---------------------------------------------------------------------------
---------------------------- DATAWIDTH MATCHING ---------------------------
-- If datawidth matching has been turned on at least 1 memory bank,
-- implement the data width matching logic. Note that an individual bank
-- with datawidth matching turned off will still use this logic.
---------------------------------------------------------------------------
DATAWIDTH_MATCH_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 1 generate
begin
-----------------------------------------------------------------------
-- Assign output signals
-----------------------------------------------------------------------
addr_cnt_cmb <= (others => '0') when Datawidth_match = '0' else
addr_cnt_i;
ADDR_CNT_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1') then
if(Rst = '1')then
addr_cnt_i <= (others=>'0');
elsif Addr_cnt_rst = '1' then
if(Cre_reg_en = '0') then
addr_cnt_i <= addr_cnt_val;
else
addr_cnt_i <= (others => '0');
end if;
elsif Addr_cnt_ce = '1' then
addr_cnt_i <= addr_cnt_i + 1;
end if;
end if;
end process ADDR_CNT_PROCESS;
-----------------------------------------------------------------------
-- Create cycle termination logic for C_IPIF_DWIDTH = 64.
-----------------------------------------------------------------------
CYCLE_END_CNT_64_GEN : if C_IPIF_DWIDTH = 64 generate
begin
mem_addr_cmb <= int_addr when Datawidth_match = '0' or Cre_reg_en = '1' else
int_addr(0 to C_IPIF_AWIDTH-C_ADDR_OFFSET-1)
& addr_suffix;
Addr_align <= '0';
reduced_high_be <= or_reduce (Bus2IP_BE(0 to 3));
reduced_low_be <= or_reduce (Bus2IP_BE(4 to 7));
reduced_16_0_be <= or_reduce (Bus2IP_BE(6 to 7));
reduced_16_1_be <= or_reduce (Bus2IP_BE(4 to 5));
reduced_16_2_be <= or_reduce (Bus2IP_BE(2 to 3));
reduced_16_3_be <= or_reduce (Bus2IP_BE(0 to 1));
---------------------------------------------------------------------
-- Create the address suffix.
---------------------------------------------------------------------
ADDR_SUFFIX_PROCESS_64: process(Mem_width_bytes,
Bus2IP_Addr,
addr_cnt_i)
begin
addr_suffix <= (others => '0');
addr_cnt_val<= (others => '0');
case Mem_width_bytes is
when "0001" =>
addr_suffix <= addr_cnt_i;
addr_cnt_val <= Bus2IP_Addr(C_IPIF_AWIDTH-C_ADDR_OFFSET
to C_IPIF_AWIDTH - 1);
when "0010" =>
addr_suffix <= addr_cnt_i(1 to C_ADDR_CNTR_WIDTH-1)
& '0';
addr_cnt_val <= '0' & Bus2IP_Addr(C_IPIF_AWIDTH-
C_ADDR_OFFSET to C_IPIF_AWIDTH - 2);
when "0100" =>
addr_suffix <= addr_cnt_i(2 to C_ADDR_CNTR_WIDTH-1)
& "00";
addr_cnt_val<= "00" & Bus2IP_Addr(C_IPIF_AWIDTH-
C_ADDR_OFFSET
to C_IPIF_AWIDTH - 3);
when "1000" =>
addr_suffix <= (others => '0');
addr_cnt_val<= (others => '0');
-- coverage off
when others=>
addr_suffix <= (others => '0');
addr_cnt_val<= (others => '0');
-- coverage on
end case;
end process ADDR_SUFFIX_PROCESS_64;
---------------------------------------------------------------------
-- Create the cycle_end_cnt
---------------------------------------------------------------------
CYCLE_END_CNT_PROCESS_64 : process(Mem_width_bytes,
reduced_low_be,
reduced_high_be,
reduced_16_0_be,
reduced_16_1_be,
reduced_16_2_be,
reduced_16_3_be,
Bus2IP_BE,
Bus2IP_RdReq,
Cycle_cnt_en,
axi_trans_size_reg)
variable Mem_width_bytes_rd_req : std_logic_vector(4 downto 0);
begin
Mem_width_bytes_rd_req := Mem_width_bytes & Bus2IP_RdReq ;
case Mem_width_bytes_rd_req is
when "00010" => -- 8 bit memory write access
Cycle_cnt_en_int <= Cycle_cnt_en;
if (Bus2IP_BE(0) = '1' and Bus2IP_BE(7)='1')then
cycle_end_cnt <= "111";
elsif (
(Bus2IP_BE(0) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(7)='1'))
then
cycle_end_cnt <= "110";
elsif (
(Bus2IP_BE(2) = '1' and Bus2IP_BE(7)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(0) = '1' and Bus2IP_BE(5)='1')) then
cycle_end_cnt <= "101";
elsif (
(Bus2IP_BE(3) = '1' and Bus2IP_BE(7)='1') or
(Bus2IP_BE(2) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(5)='1') or
(Bus2IP_BE(0) = '1' and Bus2IP_BE(4)='1'))
then
cycle_end_cnt <= "100";
elsif (
(Bus2IP_BE(4) = '1' and Bus2IP_BE(7)='1') or
(Bus2IP_BE(3) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(2) = '1' and Bus2IP_BE(5)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(4)='1') or
(Bus2IP_BE(0) = '1' and Bus2IP_BE(3)='1'))
then
cycle_end_cnt <= "011";
elsif (
(Bus2IP_BE(5) = '1' and Bus2IP_BE(7)='1') or
(Bus2IP_BE(4) = '1' and Bus2IP_BE(6)='1') or
(Bus2IP_BE(3) = '1' and Bus2IP_BE(5)='1') or
(Bus2IP_BE(2) = '1' and Bus2IP_BE(4)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(3)='1') or
(Bus2IP_BE(0) = '1' and Bus2IP_BE(2)='1'))
then
cycle_end_cnt <= "010";
elsif (Bus2IP_BE = "00000011" or Bus2IP_BE = "00001100" or
Bus2IP_BE = "00110000" or Bus2IP_BE = "11000000" or
Bus2IP_BE = "01100000" or Bus2IP_BE = "00011000" or
Bus2IP_BE = "00000110") then
cycle_end_cnt <= "001";
else
cycle_end_cnt <= "000";
end if;
when "00100" => -- 16 bit memory write access
Cycle_cnt_en_int <= Cycle_cnt_en;
if (
(reduced_16_0_be = '1' and reduced_16_3_be = '1')) then
cycle_end_cnt <= "011";
elsif (
(reduced_16_0_be = '1' and reduced_16_2_be = '1') or
(reduced_16_1_be = '1' and reduced_16_3_be = '1'))
then
cycle_end_cnt <= "010";
elsif (
(reduced_16_0_be = '1' and reduced_16_1_be = '1') or
(reduced_16_1_be = '1' and reduced_16_2_be = '1') or
(reduced_16_2_be = '1' and reduced_16_3_be = '1'))
then
cycle_end_cnt <= "001";
else
cycle_end_cnt <= "000";
end if;
when "01000" => -- 32 bit memory write access
Cycle_cnt_en_int <= Cycle_cnt_en;
if (
(reduced_low_be = '1' and reduced_high_be = '1')) then
cycle_end_cnt <= "001";
else
cycle_end_cnt <= "000";
end if;
when "00011" => -- 8 bit memory read access
Cycle_cnt_en_int <= Cycle_cnt_en and or_reduce(axi_trans_size_reg);
if (axi_trans_size_reg = "01") then -- size Half word
cycle_end_cnt <= "001";
elsif(axi_trans_size_reg = "10")then -- size word
cycle_end_cnt <= "011";
elsif(axi_trans_size_reg = "11")then -- size double word
cycle_end_cnt <= "111";
else -- size byte - Default
cycle_end_cnt <= "000";
end if;
when "00101" => -- 16 bit memory read access - can be 16 bit, 32 bit or 64 bit
Cycle_cnt_en_int <= Cycle_cnt_en and axi_trans_size_reg(1);
if (axi_trans_size_reg = "00" or
axi_trans_size_reg = "01") then -- Byte or HW word
cycle_end_cnt <= "000";
elsif (axi_trans_size_reg = "10") then -- Word
cycle_end_cnt <= "001";
else --if (axi_trans_size_reg = "11") then -- DWord
cycle_end_cnt <= "011";
end if;
when "01001" => -- 32 bit memory read access - can be 16 bit, 32 bit or 64 bit
Cycle_cnt_en_int <= Cycle_cnt_en and axi_trans_size_reg(1);
if (axi_trans_size_reg = "00") then -- Byte word
cycle_end_cnt <= "000";
elsif (axi_trans_size_reg = "01") then -- HW word
cycle_end_cnt <= "000";
elsif (axi_trans_size_reg = "10") then -- Word
cycle_end_cnt <= "000";
else -- if (axi_trans_size_reg = "11") then -- DWord
cycle_end_cnt <= "001";
end if;
-- coverage off
when others =>
Cycle_cnt_en_int <= '0'; -- 1/21/2013
cycle_end_cnt <= "000" ;
-- coverage on
end case;
end process CYCLE_END_CNT_PROCESS_64;
end generate CYCLE_END_CNT_64_GEN;
-----------------------------------------------------------------------
-- Create cycle termination logic for C_IPIF_DWIDTH = 32.
-----------------------------------------------------------------------
CYCLE_END_CNT_32_GEN : if C_IPIF_DWIDTH = 32 generate
begin
reduced_16_1_be <= or_reduce (Bus2IP_BE(2 to 3));
reduced_16_0_be <= or_reduce (Bus2IP_BE(0 to 1));
-------------------------------------------------------------------
-- Create the address suffix.
-------------------------------------------------------------------
ADDR_SUFFIX_PROCESS_32: process(Mem_width_bytes,
Bus2IP_Addr,
addr_cnt_i)
begin
--addr_suffix <= (others => '0');
--addr_cnt_val <= (others => '0');
case Mem_width_bytes is
when "0001" =>
addr_suffix <= addr_cnt_i;
addr_cnt_val <= Bus2IP_Addr(C_IPIF_AWIDTH-C_ADDR_OFFSET
to C_IPIF_AWIDTH - 1);
when "0010" =>
addr_suffix <= addr_cnt_i(1 to C_ADDR_CNTR_WIDTH-1) & '0';
addr_cnt_val <= '0' & Bus2IP_Addr(C_IPIF_AWIDTH-
C_ADDR_OFFSET to C_IPIF_AWIDTH - 2);
-- coverage off
when others=>
addr_suffix <= (others => '0');
addr_cnt_val <= (others => '0');
-- coverage on
end case;
end process ADDR_SUFFIX_PROCESS_32;
---------------------------------------------------------------------
-- Create the cycle_end_cnt
---------------------------------------------------------------------
MEM_ADDR_PROCESS: process(int_addr, Datawidth_match, addr_suffix, Cre_reg_en)
begin
if (Datawidth_match = '0') or (Cre_reg_en = '1')then
mem_addr_cmb <= int_addr;
else
mem_addr_cmb <= int_addr(0 to C_IPIF_AWIDTH-
C_ADDR_OFFSET-1) & addr_suffix ;
end if;
end process MEM_ADDR_PROCESS;
---------------------------------------------------------------------
-- Create the cycle_end_cnt
---------------------------------------------------------------------
CYCLE_END_CNT_PROCESS_32 : process(Mem_width_bytes,
reduced_16_1_be,
reduced_16_0_be,
Bus2IP_BE,
Cycle_cnt_en,
Bus2IP_RdReq,
axi_trans_size_reg)
variable Mem_width_bytes_rd_req : std_logic_vector(4 downto 0);
begin
Mem_width_bytes_rd_req := Mem_width_bytes & Bus2IP_RdReq ;
case Mem_width_bytes_rd_req is
when "00010" => -- 8 bit memory width write
Cycle_cnt_en_int <= Cycle_cnt_en; -- 1/18/2013
if
(Bus2IP_BE(0) = '1' and Bus2IP_BE(3)='1')then
cycle_end_cnt <= "11";
elsif (
(Bus2IP_BE(0) = '1' and Bus2IP_BE(2)='1') or
(Bus2IP_BE(1) = '1' and Bus2IP_BE(3)='1')) then
cycle_end_cnt <= "10";
elsif (Bus2IP_BE = "0011" or Bus2IP_BE = "1100" or
Bus2IP_BE = "0110") then
cycle_end_cnt <= "01";
else
cycle_end_cnt <= "00";
end if;
when "00100" => -- 16 bit memory width write
Cycle_cnt_en_int <= Cycle_cnt_en; -- 1/18/2013
if (
(reduced_16_0_be = '1' and reduced_16_1_be= '1'))
then
cycle_end_cnt <= "01";
else
cycle_end_cnt <= "00";
end if;
when "00011" => -- 8 bit memory read access
Cycle_cnt_en_int <= Cycle_cnt_en and or_reduce(axi_trans_size_reg);
if (axi_trans_size_reg = "01") then -- size Half word
cycle_end_cnt <= "01";
elsif(axi_trans_size_reg = "10")then -- size word
cycle_end_cnt <= "11";
else -- size byte - Default
cycle_end_cnt <= "00";
end if;
when "00101" => -- 16 bit memory read access - can be 8 bit, 16 bit, 32 bit
Cycle_cnt_en_int <= Cycle_cnt_en and axi_trans_size_reg(1);
--if (axi_trans_size_reg = "00" or
-- axi_trans_size_reg = "01") then -- Byte or HW word
-- cycle_end_cnt <= "00";
--elsif (axi_trans_size_reg = "10") then -- Word
-- cycle_end_cnt <= "01";
--end if;
if(axi_trans_size_reg = "10") then -- Word
cycle_end_cnt <= "01";
else
cycle_end_cnt <= "00";
end if;
when "01001" => -- 32 bit memory read access - can be 8 bit, 16 bit, 32 bit
Cycle_cnt_en_int <= Cycle_cnt_en and axi_trans_size_reg(1);
if (axi_trans_size_reg = "00") then -- Byte word
cycle_end_cnt <= "00";
elsif (axi_trans_size_reg = "01") then -- HW word
cycle_end_cnt <= "00";
elsif (axi_trans_size_reg = "10") then -- Word
cycle_end_cnt <= "00";
else -- if (axi_trans_size_reg = "11") then -- DWord
cycle_end_cnt <= "01";
end if;
-- coverage off
when others =>
Cycle_cnt_en_int <= '0'; -- 1/21/2013
cycle_end_cnt <= "00" ;
-- coverage on
end case;
end process CYCLE_END_CNT_PROCESS_32;
end generate CYCLE_END_CNT_32_GEN;
-----------------------------------------------------------------------
-- Instantiate the cycle_end_counter.
-----------------------------------------------------------------------
CYCLE_END_CNTR_I:entity emc_common_v3_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_ADDR_CNTR_WIDTH,
C_RESET_VALUE => ZERO_CYCLE_CNT,
C_LD_WIDTH => C_ADDR_CNTR_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => cycle_cnt,
LD => cycle_end_cnt,
AD => "1",
LOAD => Cycle_cnt_ld, -- Cycle_cnt_ld,
OP => Cycle_cnt_en_int
);
Cycle_End <= '1' when (conv_integer(cycle_cnt) = 0)
-- else
-- '1' when psram_page_mode = '1'
else
'0';
end generate DATAWIDTH_MATCH_GEN;
end imp;
-------------------------------------------------------------------------------
-- End of File addr_counter_mux.vhd.
-------------------------------------------------------------------------------
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/lfsr16.vhd
|
4
|
11229
|
-------------------------------------------------------------------------------
-- lfsr16 - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : lfsr16.vhd
-- Version : v2.0
-- Description : This is a 15 bit random number generator.
-- In simulation we need to reset first, then give the enable signal.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- This is a 15 bit random number generator.
-- In simulation we need to reset first, then give the enable signal.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Clken -- Clock enable
-- Enbl -- LFSR enable
-- Shftout -- Shift data output
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity lfsr16 is
port
(
Clk : in std_logic;
Rst : in std_logic;
Clken : in std_logic; -- tx Clk based. Assumed to be 2.5 or 25 MHz
Enbl : in std_logic;
Shftout : out std_logic
);
end lfsr16;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture imp of lfsr16 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Bit1 : std_logic;
signal Bit15 : std_logic;
signal Bit14 : std_logic;
signal XNORGateOutput : std_logic;
signal zero : std_logic;
signal one : std_logic;
signal combo_enbl : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the 16 bit lfsr
component SRL16E
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (
Q : out std_logic;
A0 : in std_logic; -- Set the address to 12.
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
Clk : in std_logic;
CE : in std_logic);
end component;
begin
zero <= '0';
one <= '1';
SHREG0 : SRL16E
-- synthesis translate_off
generic map (INIT => X"5a5a")
-- synthesis translate_on
port map(
Q => Bit14,
A0 => zero,
A1 => zero,
A2 => one,
A3 => one,
D => Bit1,
CE => combo_enbl,
Clk => Clk);
combo_enbl <= Enbl and Clken;
-------------------------------------------------------------------------------
-- determine bit 15 value
-------------------------------------------------------------------------------
REG0_PROCESS:process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Bit15 <= '0';
elsif combo_enbl = '1' then
Bit15 <= Bit14;
end if;
end if;
end process REG0_PROCESS;
-------------------------------------------------------------------------------
-- determine bit 1 value
-------------------------------------------------------------------------------
REG1_PROCESS:process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Bit1 <= '0';
elsif combo_enbl = '1' then
Bit1 <= XNORGateOutput;
end if;
end if;
end process REG1_PROCESS;
XNORGateOutput <= Bit14 XNOR Bit15;
Shftout <= Bit1;
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lib_pkg_v1_0/22b9c58c/hdl/src/vhdl/lib_pkg.vhd
|
28
|
16351
|
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/srl_fifo.vhd
|
4
|
10681
|
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/transmit.vhd
|
4
|
36318
|
-------------------------------------------------------------------------------
-- transmit - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : transmit.vhd
-- Version : v2.0
-- Description : This is the transmit path portion of the design
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.numeric_std."-";
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- NibbleLength -- Transmit frame nibble length
-- NibbleLength_orig -- Transmit nibble length before pkt adjustment
-- En_pad -- Enable padding
-- TxClkEn -- Transmit clock enable
-- Phy_tx_clk -- PHY TX Clock
-- Phy_crs -- Ethernet carrier sense
-- Phy_col -- Ethernet collision indicator
-- Phy_tx_en -- Ethernet transmit enable
-- Phy_tx_data -- Ethernet transmit data
-- Tx_addr_en -- TX buffer address enable
-- Tx_start -- TX start
-- Tx_done -- TX complete
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- TX idle
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Transmit_start -- Transmit start
-- Mac_program_start -- MAC Program start
-- Mac_addr_ram_we -- MAC Address RAM write enable
-- Mac_addr_ram_addr_wr -- MAC Address RAM write address
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity transmit is
generic
(
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_FAMILY : string := "virtex6"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
NibbleLength : in std_logic_vector(0 to 11);
NibbleLength_orig : in std_logic_vector(0 to 11);
En_pad : in std_logic;
TxClkEn : in std_logic;
Phy_tx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_col : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_addr_en : out std_logic;
Tx_start : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Tx_DPM_ce : out std_logic;
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Mac_addr_ram_we : out std_logic;
Mac_addr_ram_addr_wr : out std_logic_vector(0 to 3)
);
end transmit;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No Generics were used for this Entity.
--
-- Definition of Ports:
--
-------------------------------------------------------------------------------
architecture imp of transmit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant logic_one :std_logic := '1';
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal tx_d_rst : std_logic;
signal full_half_n : std_logic;
signal bus_combo : std_logic_vector (0 to 5);
signal txChannelReset : std_logic;
signal emac_tx_wr_i : std_logic;
signal txfifo_full : std_logic;
signal txfifo_empty : std_logic;
signal tx_en_i : std_logic;
signal tx_en_i_tx_clk : std_logic;
signal fifo_tx_en : std_logic;
signal axi_fifo_tx_en : std_logic;
signal txNibbleCntLd : std_logic;
signal txNibbleCntEn : std_logic;
signal txNibbleCntRst : std_logic;
signal txComboNibbleCntRst : std_logic;
--signal phy_tx_en_i : std_logic;
signal phy_tx_en_i_p : std_logic;
signal axi_phy_tx_en_i_p : std_logic;
signal deferring : std_logic;
signal txBusFifoWrCntRst : std_logic;
signal txBusFifoWrCntEn : std_logic;
signal txComboBusFifoWrCntRst : std_logic;
signal txComboBusFifoWrCntEn : std_logic;
signal txComboColRetryCntRst_n : std_logic;
signal txComboBusFifoRst : std_logic;
signal txColRetryCntRst_n : std_logic;
signal enblPreamble : std_logic;
signal enblSFD : std_logic;
signal enblData : std_logic;
signal enblJam : std_logic;
signal enblCRC : std_logic;
signal txCntEnbl : std_logic;
signal txColRetryCntEnbl : std_logic;
signal jamTxComboNibCntEnbl : std_logic;
signal txRetryRst : std_logic;
signal txLateColnRst : std_logic;
signal initBackoff : std_logic;
signal backingOff_i : std_logic;
signal txCrcShftOutEn : std_logic;
signal txCrcEn : std_logic;
signal crcComboRst : std_logic;
signal emac_tx_wr_data_i : std_logic_vector (0 to 3);
signal crcCnt : std_logic_vector(0 to 3);
signal collisionRetryCnt : std_logic_vector(0 to 4);
signal jamTxNibbleCnt : std_logic_vector(0 to 3);
signal colWindowNibbleCnt : std_logic_vector(0 to 7);
signal prb : std_logic_vector(0 to 3);
signal sfd : std_logic_vector(0 to 3);
signal jam : std_logic_vector(0 to 3);
signal crc : std_logic_vector(0 to 3);
signal currentTxBusFifoWrCnt : std_logic_vector(0 to 11);
signal currentTxNibbleCnt : std_logic_vector (0 to 11);
signal phy_tx_en_n : std_logic;
signal txComboColRetryCntRst : std_logic;
signal phy_tx_en_i_n : std_logic;
signal jam_rst : std_logic;
signal txExcessDefrlRst : std_logic;
signal enblclear : std_logic;
signal tx_en_mod : std_logic;
signal emac_tx_wr_mod : std_logic;
signal pre_sfd_done : std_logic;
signal mux_in_data : std_logic_vector (0 to 6*4-1);
signal mux_in_sel : std_logic_vector (0 to 5);
signal transmit_data : std_logic_vector (0 to 3);
signal txNibbleCnt_pad : unsigned (0 to 11);
signal tx_idle_i : std_logic;
signal emac_tx_wr_data_d1 : std_logic_vector (0 to 3);
signal emac_tx_wr_d1 : std_logic;
signal txcrcen_d1 : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component FDRE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDCE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- tx crc generator
----------------------------------------------------------------------------
INST_CRCGENTX: entity axi_ethernetlite_v3_0.crcgentx
port map
(
Clk => Clk,
Rst => crcComboRst,
Clken => emac_tx_wr_d1,
Data => emac_tx_wr_data_d1,
DataEn => txcrcen_d1,
OutEn => txCrcShftOutEn,
CrcNibs => crc
);
crcComboRst <= Rst or not (tx_en_i); -- having tx_en form same clock domain as Clk
-- crcComboRst <= Rst or not (fifo_tx_en);
----------------------------------------------------------------------------
-- tx interface contains the ethernet tx fifo
----------------------------------------------------------------------------
INST_TX_INTRFCE: entity axi_ethernetlite_v3_0.tx_intrfce
generic map
(
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => txComboBusFifoRst,
Phy_tx_clk => Phy_tx_clk,
Emac_tx_wr_data => emac_tx_wr_data_i,
Tx_er => '0',
PhyTxEn => tx_en_mod,
Tx_en => fifo_tx_en,
Fifo_empty => txfifo_empty,
Fifo_full => txfifo_full,
Emac_tx_wr => emac_tx_wr_mod,
Phy_tx_data => bus_combo
);
txComboBusFifoRst <= Rst or txRetryRst or
(jam_rst and not(full_half_n) and
Phy_col and pre_sfd_done);
jam <= "0110"; -- arbitrary
prb <= "0101"; -- transmitted as 1010
sfd <= "1101"; -- transmitted as 1011
----------------------------------------------------------------------------
-- PHY output selection
----------------------------------------------------------------------------
mux_in_sel <= enblPreamble & enblSFD & enblData & enblJam & enblCRC &
logic_one;
mux_in_data <= prb & sfd & transmit_data & jam & crc & "0000";
transmit_data <= "0000" when (txNibbleCnt_pad = 0) else
Tx_DPM_rd_data;
Tx_idle <= tx_idle_i;
----------------------------------------------------------------------------
-- Multiplexing PHY transmit data
----------------------------------------------------------------------------
ONR_HOT_MUX:entity axi_ethernetlite_v3_0.mux_onehot_f
generic map
(
C_DW => 4,
C_NB => 6,
C_FAMILY => C_FAMILY
)
port map
(
D => mux_in_data,
S => mux_in_sel,
Y => emac_tx_wr_data_i
);
----------------------------------------------------------------------------
-- PHY transmit data
----------------------------------------------------------------------------
Phy_tx_data <= "0110" when (Phy_col = '1' or
not(jamTxNibbleCnt(0) = '1' and
jamTxNibbleCnt(1) = '0' and
jamTxNibbleCnt(2) = '0' and
jamTxNibbleCnt(3) = '1')) and
full_half_n = '0' and
not (jamTxNibbleCnt = "0000") and
pre_sfd_done = '1' else
"0000" when jamTxNibbleCnt = "0000" and
full_half_n = '0' else
"0000" when axi_phy_tx_en_i_p = '0' else
bus_combo(0 to 3);
----------------------------------------------------------------------------
-- PHY transmit enable
----------------------------------------------------------------------------
Phy_tx_en <= '1' when (Phy_col = '1' or
not(jamTxNibbleCnt(0) = '1' and
jamTxNibbleCnt(1) = '0' and
jamTxNibbleCnt(2) = '0' and
jamTxNibbleCnt(3) = '1')) and
full_half_n = '0' and
not (jamTxNibbleCnt = "0000") and
pre_sfd_done = '1' else
'0' when jamTxNibbleCnt = "0000" and
full_half_n = '0' else
'0' when axi_phy_tx_en_i_p = '0' else
bus_combo(5);
----------------------------------------------------------------------------
-- transmit packet fifo read nibble counter
----------------------------------------------------------------------------
INST_TXNIBBLECOUNT: entity axi_ethernetlite_v3_0.ld_arith_reg
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 12,
C_RESET_VALUE => "000000000000",
C_LD_WIDTH => 12,
C_LD_OFFSET => 0,
C_AD_WIDTH => 12,
C_AD_OFFSET => 0
)
port map
(
CK => Clk,
Rst => txComboNibbleCntRst,
Q => currentTxNibbleCnt,
LD => NibbleLength,
AD => "000000000001",
LOAD => txNibbleCntLd,
OP => txNibbleCntEn
);
txComboNibbleCntRst <= Rst or txNibbleCntRst or txRetryRst;
----------------------------------------------------------------------------
-- PROCESS : PKT_TX_PAD_COUNTER
----------------------------------------------------------------------------
-- This counter is used to check if the receive packet length is greater
-- minimum packet length (64 byte - 128 nibble)
----------------------------------------------------------------------------
PKT_TX_PAD_COUNTER : process(Clk)
begin
if (Clk'event and Clk='1') then
if (Rst=RESET_ACTIVE) then
txNibbleCnt_pad <= (others=>'0');
elsif (enblSFD='1') then -- load the counter for minimum
txNibbleCnt_pad <= unsigned(NibbleLength_orig); -- packet length
elsif (enblData='1' and En_pad='1') then -- Enable Down Counter
if (txNibbleCnt_pad=0 ) then
txNibbleCnt_pad <= (others=>'0');
else
txNibbleCnt_pad <= txNibbleCnt_pad-1;
end if;
end if;
end if;
end process PKT_TX_PAD_COUNTER;
----------------------------------------------------------------------------
-- transmit state machine
----------------------------------------------------------------------------
INST_TX_STATE_MACHINE: entity axi_ethernetlite_v3_0.tx_statemachine
generic map
(
C_DUPLEX => C_DUPLEX
)
port map
(
Clk => Clk,
Rst => txChannelReset,
TxClkEn => TxClkEn,
Jam_rst => jam_rst,
TxRst => txChannelReset,
Deferring => deferring,
ColRetryCnt => collisionRetryCnt,
ColWindowNibCnt => colWindowNibbleCnt,
JamTxNibCnt => jamTxNibbleCnt,
TxNibbleCnt => currentTxNibbleCnt,
BusFifoWrNibbleCnt => currentTxBusFifoWrCnt,
CrcCnt => crcCnt,
BusFifoFull => txfifo_full,
BusFifoEmpty => txfifo_empty,
PhyCollision => Phy_col,
InitBackoff => initBackoff,
TxRetryRst => txRetryRst,
TxExcessDefrlRst => txExcessDefrlRst,
TxLateColnRst => txLateColnRst,
TxColRetryCntRst_n => txColRetryCntRst_n,
TxColRetryCntEnbl => txColRetryCntEnbl,
TxNibbleCntRst => txNibbleCntRst,
TxEnNibbleCnt => txNibbleCntEn,
TxNibbleCntLd => txNibbleCntLd,
BusFifoWrCntRst => txBusFifoWrCntRst,
BusFifoWrCntEn => txBusFifoWrCntEn,
EnblPre => enblPreamble,
EnblSFD => enblSFD,
EnblData => enblData,
EnblJam => enblJam,
EnblCRC => enblCRC,
BusFifoWr => emac_tx_wr_i,
Phytx_en => tx_en_i,
TxCrcEn => txCrcEn,
TxCrcShftOutEn => txCrcShftOutEn,
Tx_addr_en => Tx_addr_en,
Tx_start => Tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => tx_idle_i,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Enblclear => enblclear,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => Mac_addr_ram_we,
Mac_addr_ram_addr_wr => Mac_addr_ram_addr_wr,
Pre_sfd_done => pre_sfd_done
);
----------------------------------------------------------------------------
-- deferral control
----------------------------------------------------------------------------
full_half_n <= '1'when C_DUPLEX = 1 else
'0';
INST_DEFERRAL_CONTROL: entity axi_ethernetlite_v3_0.deferral
port map
(
Clk => Clk,
Rst => Rst,
TxEn => tx_en_i,
TxRst => txChannelReset,
Tx_clk_en => TxClkEn,
BackingOff => backingOff_i,
Crs => Phy_crs,
Full_half_n => full_half_n,
Ifgp1 => "10000",
Ifgp2 => "01000",
Deferring => deferring
);
----------------------------------------------------------------------------
-- transmit bus fifo write nibble counter
----------------------------------------------------------------------------
INST_TXBUSFIFOWRITENIBBLECOUNT: entity axi_ethernetlite_v3_0.ld_arith_reg
generic map
(
C_ADD_SUB_NOT => true,
C_REG_WIDTH => 12,
C_RESET_VALUE => "000000000000",
C_LD_WIDTH => 12,
C_LD_OFFSET => 0,
C_AD_WIDTH => 12,
C_AD_OFFSET => 0
)
port map
(
CK => Clk,
Rst => txComboBusFifoWrCntRst,
Q => currentTxBusFifoWrCnt,
LD => "000000000000",
AD => "000000000001",
LOAD => '0',
OP => txComboBusFifoWrCntEn
);
txComboBusFifoWrCntRst <= Rst or txBusFifoWrCntRst
or txRetryRst;
txComboBusFifoWrCntEn <= txBusFifoWrCntEn and emac_tx_wr_i;
----------------------------------------------------------------------------
-- crc down counter
----------------------------------------------------------------------------
phy_tx_en_n <= not(tx_en_i); -- modified to have this in lite clock domain
INST_CRCCOUNTER: entity axi_ethernetlite_v3_0.ld_arith_reg
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 4,
C_RESET_VALUE => "1000",
C_LD_WIDTH => 4,
C_LD_OFFSET => 0,
C_AD_WIDTH => 4,
C_AD_OFFSET => 0
)
port map
(
CK => Clk,
Rst => Rst,
Q => crcCnt,
LD => "1000",
AD => "0001",
LOAD => phy_tx_en_n,
OP => enblCRC
);
----------------------------------------------------------------------------
-- Full Duplex mode operation
----------------------------------------------------------------------------
TX3_NOT_GENERATE: if(C_DUPLEX = 1) generate --Set outputs to zero
begin
collisionRetryCnt <= (others=> '0');
colWindowNibbleCnt <= (others=> '0');
jamTxNibbleCnt <= (others=> '0');
backingOff_i <= '0';
end generate TX3_NOT_GENERATE;
----------------------------------------------------------------------------
-- Half Duplex mode operation
----------------------------------------------------------------------------
tx3_generate: if(C_DUPLEX = 0) generate --Include collision cnts when 1
----------------------------------------------------------------------------
-- transmit collision retry down counter
----------------------------------------------------------------------------
INST_COLRETRYCNT: entity axi_ethernetlite_v3_0.msh_cnt
generic map
(
C_ADD_SUB_NOT => true,
C_REG_WIDTH => 5,
C_RESET_VALUE => "00000"
)
port map
(
Clk => Clk,
Rst => txComboColRetryCntRst,
Q => collisionRetryCnt,
Z => open,
LD => "00000",
AD => "00001",
LOAD => '0',
OP => txColRetryCntEnbl
);
txComboColRetryCntRst_n <= not(Rst) and txColRetryCntRst_n;
txComboColRetryCntRst <= not txComboColRetryCntRst_n;
----------------------------------------------------------------------------
-- transmit collision window nibble down counter
----------------------------------------------------------------------------
INST_COLWINDOWNIBCNT: entity axi_ethernetlite_v3_0.msh_cnt
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 8,
C_RESET_VALUE => "10001111"
)
port map
(
Clk => Clk,
Rst => phy_tx_en_i_n,
Q => colWindowNibbleCnt,
Z => open,
LD => "10001111",
AD => "00000001",
LOAD => '0',
OP => txCntEnbl
);
phy_tx_en_i_n <= not(axi_phy_tx_en_i_p);
----------------------------------------------------------------------------
-- jam transmit nibble down counter
----------------------------------------------------------------------------
INST_JAMTXNIBCNT: entity axi_ethernetlite_v3_0.msh_cnt
generic map
(
C_ADD_SUB_NOT => false,
C_REG_WIDTH => 4,
C_RESET_VALUE => "1001"
)
port map
(
Clk => Clk,
Rst => phy_tx_en_i_n,
Q => jamTxNibbleCnt,
Z => open,
LD => "1001",
AD => "0001",
LOAD => '0',
OP => jamTxComboNibCntEnbl
);
----------------------------------------------------------------------------
-- tx collision back off counter
----------------------------------------------------------------------------
INST_BOCNT: entity axi_ethernetlite_v3_0.bocntr
port map
(
Clk => Clk,
Clken => TxClkEn,
Rst => Rst,
InitBackoff => initBackoff,
RetryCnt => collisionRetryCnt,
BackingOff => backingOff_i
);
end generate tx3_generate;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_EN: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => tx_en_i,
prmry_ack => open,
scndry_out => tx_en_i_tx_clk,
scndry_aclk => Phy_tx_clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
--- ----------------------------------------------------------------------------
--- -- CDC module for syncing phy_tx_en_i in Clk domain
--- ----------------------------------------------------------------------------
--- CDC_PHY_TX_EN: entity lib_cdc_v1_0.cdc_sync
--- generic map (
--- C_CDC_TYPE => 1,
--- C_RESET_STATE => 0,
--- C_SINGLE_BIT => 1,
--- C_FLOP_INPUT => 0,
--- C_VECTOR_WIDTH => 1,
--- C_MTBF_STAGES => 4
--- )
--- port map(
--- prmry_aclk => '1',
--- prmry_resetn => '1',
--- prmry_in => phy_tx_en_i_p,
--- prmry_ack => open,
--- scndry_out => phy_tx_en_i,
--- scndry_aclk => Clk,
--- scndry_resetn => '1',
--- prmry_vect_in => (OTHERS => '0'),
--- scndry_vect_out => open
--- );
--- ----------------------------------------------------------------------------
-- CDC module for syncing rst in tx_clk domain
----------------------------------------------------------------------------
CDC_PHY_TX_RST: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Rst,
prmry_ack => open,
scndry_out => tx_d_rst,
scndry_aclk => Phy_tx_clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_en_PROCESS
----------------------------------------------------------------------------
-- This process assigns the outputs the phy enable
----------------------------------------------------------------------------
INT_TX_EN_PROCESS: process (Phy_tx_clk)
begin --
if (Phy_tx_clk'event and Phy_tx_clk = '1') then
if (tx_d_rst = RESET_ACTIVE) then
phy_tx_en_i_p <= '0';
fifo_tx_en <= '0';
else
fifo_tx_en <= tx_en_i_tx_clk; -- having cdc sync for tx_en_i for MTBF
phy_tx_en_i_p <= fifo_tx_en and tx_en_i_tx_clk;
-- fifo_tx_en <= tx_en_i;
-- phy_tx_en_i <= fifo_tx_en and tx_en_i;
end if;
end if;
end process INT_TX_EN_PROCESS;
AXI_INT_TX_EN_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
axi_fifo_tx_en <= '0';
axi_phy_tx_en_i_p <= '0';
else
axi_fifo_tx_en <= tx_en_i;
axi_phy_tx_en_i_p <= axi_fifo_tx_en and tx_en_i;
end if;
end if;
end process AXI_INT_TX_EN_PROCESS;
emac_tx_wr_mod <= emac_tx_wr_i or enblclear;
tx_en_mod <= '0' when enblclear = '1' else
tx_en_i;
txChannelReset <= Rst;
txCntEnbl <= TxClkEn and axi_phy_tx_en_i_p and
not(not(full_half_n) and Phy_col);
----------------------------------------------------------------------------
-- jam transmit nibble down counter enable
----------------------------------------------------------------------------
jamTxComboNibCntEnbl <= (Phy_col or not(jamTxNibbleCnt(0) and
not(jamTxNibbleCnt(1)) and
not(jamTxNibbleCnt(2)) and
jamTxNibbleCnt(3))) and
pre_sfd_done and TxClkEn and not(full_half_n);
----------------------------------------------------------------------------
-- INT_CRC_DATA_REG_PROCESS
----------------------------------------------------------------------------
-- This process registers the emac data going to CRCgen Module to break long
-- timing path.
----------------------------------------------------------------------------
INT_CRC_DATA_REG_PROCESS: process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
emac_tx_wr_data_d1 <= (others=>'0');
emac_tx_wr_d1 <= '0';
txcrcen_d1 <= '0';
else
emac_tx_wr_data_d1 <= emac_tx_wr_data_i;
emac_tx_wr_d1 <= emac_tx_wr_i;
txcrcen_d1 <= txCrcEn;
end if;
end if;
end process INT_CRC_DATA_REG_PROCESS;
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_clk_wiz.vhd
|
2
|
8017
|
-- file: design_1_clk_wiz_1_0_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______130.958_____98.575
-- CLK_OUT2____50.000______0.000______50.0______151.636_____98.575
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity design_1_clk_wiz_1_0_clk_wiz is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
clk_out2 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end design_1_clk_wiz_1_0_clk_wiz;
architecture xilinx of design_1_clk_wiz_1_0_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_in1_design_1_clk_wiz_1_0 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_design_1_clk_wiz_1_0 : std_logic;
signal clkfbout_buf_design_1_clk_wiz_1_0 : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_out1_design_1_clk_wiz_1_0 : std_logic;
signal clkout0b_unused : std_logic;
signal clk_out2_design_1_clk_wiz_1_0 : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
signal reset_high : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => clk_in1_design_1_clk_wiz_1_0,
I => clk_in1);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 10.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 20,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_design_1_clk_wiz_1_0,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_out1_design_1_clk_wiz_1_0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clk_out2_design_1_clk_wiz_1_0,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_design_1_clk_wiz_1_0,
CLKIN1 => clk_in1_design_1_clk_wiz_1_0,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => reset_high);
reset_high <= not resetn;
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_design_1_clk_wiz_1_0,
I => clkfbout_design_1_clk_wiz_1_0);
clkout1_buf : BUFG
port map
(O => clk_out1,
I => clk_out1_design_1_clk_wiz_1_0);
clkout2_buf : BUFG
port map
(O => clk_out2,
I => clk_out2_design_1_clk_wiz_1_0);
end xilinx;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_mii_to_rmii_0_0/synth/design_1_mii_to_rmii_0_0.vhd
|
2
|
7550
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mii_to_rmii:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mii_to_rmii_v2_0;
USE mii_to_rmii_v2_0.mii_to_rmii;
ENTITY design_1_mii_to_rmii_0_0 IS
PORT (
rst_n : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
mac2rmii_tx_en : IN STD_LOGIC;
mac2rmii_txd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mac2rmii_tx_er : IN STD_LOGIC;
rmii2mac_tx_clk : OUT STD_LOGIC;
rmii2mac_rx_clk : OUT STD_LOGIC;
rmii2mac_col : OUT STD_LOGIC;
rmii2mac_crs : OUT STD_LOGIC;
rmii2mac_rx_dv : OUT STD_LOGIC;
rmii2mac_rx_er : OUT STD_LOGIC;
rmii2mac_rxd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy2rmii_crs_dv : IN STD_LOGIC;
phy2rmii_rx_er : IN STD_LOGIC;
phy2rmii_rxd : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_txd : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_tx_en : OUT STD_LOGIC
);
END design_1_mii_to_rmii_0_0;
ARCHITECTURE design_1_mii_to_rmii_0_0_arch OF design_1_mii_to_rmii_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mii_to_rmii_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT mii_to_rmii IS
GENERIC (
C_INSTANCE : STRING;
C_FIXED_SPEED : STD_LOGIC;
C_SPEED_100 : STD_LOGIC
);
PORT (
rst_n : IN STD_LOGIC;
ref_clk : IN STD_LOGIC;
mac2rmii_tx_en : IN STD_LOGIC;
mac2rmii_txd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
mac2rmii_tx_er : IN STD_LOGIC;
rmii2mac_tx_clk : OUT STD_LOGIC;
rmii2mac_rx_clk : OUT STD_LOGIC;
rmii2mac_col : OUT STD_LOGIC;
rmii2mac_crs : OUT STD_LOGIC;
rmii2mac_rx_dv : OUT STD_LOGIC;
rmii2mac_rx_er : OUT STD_LOGIC;
rmii2mac_rxd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy2rmii_crs_dv : IN STD_LOGIC;
phy2rmii_rx_er : IN STD_LOGIC;
phy2rmii_rxd : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_txd : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rmii2phy_tx_en : OUT STD_LOGIC
);
END COMPONENT mii_to_rmii;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_mii_to_rmii_0_0_arch: ARCHITECTURE IS "mii_to_rmii,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mii_to_rmii_0_0_arch : ARCHITECTURE IS "design_1_mii_to_rmii_0_0,mii_to_rmii,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_mii_to_rmii_0_0_arch: ARCHITECTURE IS "design_1_mii_to_rmii_0_0,mii_to_rmii,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mii_to_rmii,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_INSTANCE=design_1_mii_to_rmii_0_0,C_FIXED_SPEED=1,C_SPEED_100=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
ATTRIBUTE X_INTERFACE_INFO OF ref_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF mac2rmii_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF mac2rmii_txd: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF mac2rmii_tx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_ER";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rx_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF rmii2mac_rxd: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy2rmii_crs_dv: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M CRS_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy2rmii_rx_er: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy2rmii_rxd: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M RXD";
ATTRIBUTE X_INTERFACE_INFO OF rmii2phy_txd: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M TXD";
ATTRIBUTE X_INTERFACE_INFO OF rmii2phy_tx_en: SIGNAL IS "xilinx.com:interface:rmii:1.0 RMII_PHY_M TX_EN";
BEGIN
U0 : mii_to_rmii
GENERIC MAP (
C_INSTANCE => "design_1_mii_to_rmii_0_0",
C_FIXED_SPEED => '1',
C_SPEED_100 => '1'
)
PORT MAP (
rst_n => rst_n,
ref_clk => ref_clk,
mac2rmii_tx_en => mac2rmii_tx_en,
mac2rmii_txd => mac2rmii_txd,
mac2rmii_tx_er => mac2rmii_tx_er,
rmii2mac_tx_clk => rmii2mac_tx_clk,
rmii2mac_rx_clk => rmii2mac_rx_clk,
rmii2mac_col => rmii2mac_col,
rmii2mac_crs => rmii2mac_crs,
rmii2mac_rx_dv => rmii2mac_rx_dv,
rmii2mac_rx_er => rmii2mac_rx_er,
rmii2mac_rxd => rmii2mac_rxd,
phy2rmii_crs_dv => phy2rmii_crs_dv,
phy2rmii_rx_er => phy2rmii_rx_er,
phy2rmii_rxd => phy2rmii_rxd,
rmii2phy_txd => rmii2phy_txd,
rmii2phy_tx_en => rmii2phy_tx_en
);
END design_1_mii_to_rmii_0_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/876b8fe4/hdl/src/vhdl/address_decoder.vhd
|
16
|
22444
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/macaddrram.vhd
|
4
|
10845
|
-------------------------------------------------------------------------------
-- MacAddrRAM - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : macaddram.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- There is a rom used in the MII to store the MAC address
--
-- Note that the two nibbles in each word of the MAC address
-- are transposed in order to transmit to the network in the
-- proper order.However, the generic value (MACAddr)of this
-- ROM keeps the normal order.
--
-- Representation of each word in this ROM (list with address order)
--
-- Addr (3 downto 0) : netOrder(MACAddr(47 downto 32)) e.g.: 0xafec
-- Addr (7 downto 4) : netOrder(MACAddr(31 downto 16)) e.g.: 0xedfa
-- Addr (11 downto 8) : netOrder(MACAddr(15 downto 0)) e.g.: 0xacef
-- Addr (15 downto 12) : netOrder(Filler) e.g.: 0x0000
--
-- Uses 4 LUTs (4 rom16x1), 0 register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
--
-- MACAddr -- MAC Address
-- Filler -- Filler
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Addr -- Address
-- Dout -- Data output
-- Din -- Data input
-- We -- Write Enable
-- Clk -- Clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity MacAddrRAM is
generic
(MACAddr : bit_vector(47 downto 0) := x"ffffffffffaa";
-- use the normal order
Filler : bit_vector(15 downto 0) := x"0000");
port(
Addr : in std_logic_vector (3 downto 0);
Dout : out std_logic_vector (3 downto 0);
Din : in std_logic_vector (3 downto 0);
We : in std_logic;
Clk : in std_logic
);
end MacAddrRAM;
architecture imp of MacAddrRAM is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
--component ram16x4
-- generic(
-- INIT_00 : bit_vector(15 downto 0) :=x"0000";-- for Addr(3 downto 0)
-- INIT_01 : bit_vector(15 downto 0) :=x"0000";-- for Addr(7 downto 4)
-- INIT_02 : bit_vector(15 downto 0) :=x"0000";-- for Addr(11 downto 8)
-- INIT_03 : bit_vector(15 downto 0) :=x"0000" -- for Addr(15 downto 12)
-- );
-- port(
-- Addr : in std_logic_vector(3 downto 0);
-- D : in std_logic_vector(3 downto 0);
-- We : in std_logic;
-- Clk : in std_logic;
-- Q : out std_logic_vector(3 downto 0));
--end component;
begin
ram16x4i: entity axi_ethernetlite_v3_0.ram16x4
generic map
(INIT_00 => netOrder(MACAddr(47 downto 32)),
INIT_01 => netOrder(MACAddr(31 downto 16)),
INIT_02 => netOrder(MACAddr(15 downto 0)),
INIT_03 => netOrder(Filler)
)
port map
(Addr => Addr,
D => Din,
Q => Dout,
We => We,
Clk => Clk
);
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/axi_emc.vhd
|
4
|
163491
|
-------------------------------------------------------------------------------
-- $Id: axi_emc.vhd
-------------------------------------------------------------------------------
-- axi_emc.vhd - Entity and architecture
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_emc.vhd
-- Version: v2.0
-- Description: This is the top-level design file for the AXI External
-- Memory Controller.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_emc.vhd
-- -- axi_emc_native_interface.vhd
-- -- axi_emc_addr_gen.vhd
-- -- axi_emc_address_decode.vhd
-- -- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 10/02/10 -- created v1.01.a version
-- ^^^^^^
-- 1. Replaced the AXI Lite IPIF interface with AXI4 lite native interface
-- 2. Replaced the AXI Slave Burst interface with AXI4 full native interface
-- 3. Reduced the core utilization to resolve CR 573074
-- ~~~~~~
-- SK 12/02/10
-- ^^^^^^
-- 1. Added NO_REG_EN_GEN section to drive all the output signals in the register
-- interface to '0' when not selected.
-- ~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-- SK 04/14/13
-- ^^^^^^
-- -- Fixed CR 723506 - Fixed issues with the signal driven X when parity is enabled.
-- -- Fixed CR 721840 - Fixed issues in linear sync flash memory mode, parameter ordering is updated
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library emc_common_v3_0;
use emc_common_v3_0.all;
library axi_emc_v3_0;
use axi_emc_v3_0.all;
use axi_emc_v3_0.emc_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_BANKS_MEM -- Number of memory banks
-- C_MEM0_TYPE -- Type of Memory
-- 0-> Sync SRAM
-- 1-> Async SRAM
-- 2-> Nor Flash
-- 3-> Page Mode Nor Flash
-- 4-> Cellar RAM/PSRAM
-- C_PARITY_TYPE_MEM_0 -- Type of Parity
-- 0-> No Parity
-- 1-> Odd Parity
-- 2-> Even Parity
-- C_INCLUDE_NEGEDGE_IOREGS -- Include negative edge IO registers
-- C_NUM_MASTERS -- Number of axi masters
-- C_MEM(0:3)_BASEADDR -- Memory bank (0:3) base address
-- C_MEM(0:3)_HIGHADDR -- Memory bank (0:3) high address
-- C_MEM(0:3)_WIDTH -- Memory bank (0:3) data width
-- C_MAX_MEM_WIDTH -- Maximum data width of all memory banks
--
-- C_INCLUDE_DATAWIDTH_MATCHING_(0:3) -- Support data width matching for
-- memory bank (0:3)
-- C_SYNCH_MEM_(0:3) -- Memory bank (0:3) type
-- C_SYNCH_PIPEDELAY_(0:3) -- Memory bank (0:3) synchronous pipedelay
-- C_TCEDV_PS_MEM_(0:3) -- Chip Enable to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_TAVDV_PS_MEM_(0:3) -- Address Valid to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_THZCE_PS_MEM_(0:3) -- Chip Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_THZOE_PS_MEM_(0:3) -- Output Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_TWC_PS_MEM_(0:3) -- Write Cycle Time
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TWP_PS_MEM_(0:3) -- Write Enable Minimum Pulse Width
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TLZWE_PS_MEM_(0:3) -- Write Enable High to Data Bus Low
-- Impedance (Applied as Write Recovery
-- before Read)
-- C_WR_REC_TIME_MEM_0 -- Write recovery time between the write
-- -- and next consecutive read transaction
-- C_S_AXI_MEM_DWIDTH -- axi Data Bus Width
-- C_S_AXI_MEM_AWIDTH -- axi Address Width
-- C_AXI_CLK_PERIOD_PS -- axi clock period to calculate wait
-- state pulse widths.
--
--
-- Definition of Ports:
-- Memory Signals
-- mem_a -- Memory address inputs
-- mem_dq_i -- Memory Input Data Bus
-- mem_dq_o -- Memory Output Data Bus
-- mem_dq_t -- Memory Data Output Enable
-- mem_dq_parity_i -- Memory Parity Input Data Bus
-- mem_dq_parity_o -- Memory Parity Output Data Bus
-- mem_dq_parity_t -- Memory Parity Output Enable
-- mem_cen -- Memory Chip Select
-- mem_oen -- Memory Output Enable
-- mem_wen -- Memory Write Enable
-- mem_qwen -- Memory Qualified Write Enable
-- mem_ben -- Memory Byte Enables
-- mem_rpn -- Memory Reset/Power Down
-- mem_ce -- Memory chip enable
-- mem_adv_ldn -- Memory counter advance/load (=0)
-- mem_lbon -- Memory linear/interleaved burst order (=0)
-- mem_cken -- Memory clock enable (=0)
-- mem_rnw -- Memory read not write
-------------------------------------------------------------------------------
entity axi_emc is
-- Generics to be set by user
generic (
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_emc_inst";
C_AXI_CLK_PERIOD_PS : integer := 10000;
C_LFLASH_PERIOD_PS : integer := 20000;
C_LINEAR_FLASH_SYNC_BURST : integer range 0 to 1 := 0;
---- AXI REG Parameters
C_S_AXI_REG_ADDR_WIDTH : integer range 5 to 5 := 5;
C_S_AXI_REG_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_EN_REG : integer range 0 to 1 := 0;
----C_S_AXI_REG_BASEADDR : std_logic_vector := x"FFFFFFFF";
----C_S_AXI_REG_HIGHADDR : std_logic_vector := x"00000000";
---- AXI MEM Parameters
C_S_AXI_MEM_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MEM_DATA_WIDTH : integer := 32;--8,16,32,64
C_S_AXI_MEM_ID_WIDTH : integer range 1 to 16 := 4;
C_S_AXI_MEM0_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM0_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM1_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM1_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM2_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM2_HIGHADDR : std_logic_vector := x"00000000";
C_S_AXI_MEM3_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_S_AXI_MEM3_HIGHADDR : std_logic_vector := x"00000000";
-- EMC generics
C_INCLUDE_NEGEDGE_IOREGS : integer range 0 to 1 := 0;
C_NUM_BANKS_MEM : integer range 1 to 4 := 1;
C_MEM0_TYPE : integer range 0 to 5 := 0;
C_MEM1_TYPE : integer range 0 to 5 := 0;
C_MEM2_TYPE : integer range 0 to 5 := 0;
C_MEM3_TYPE : integer range 0 to 5 := 0;
C_MEM0_WIDTH : integer := 32;--8,16,32,64 allowed
C_MEM1_WIDTH : integer := 32;--8,16,32,64
C_MEM2_WIDTH : integer := 32;--8,16,32,64
C_MEM3_WIDTH : integer := 32;--8,16,32,64
C_MAX_MEM_WIDTH : integer := 32;--8,16,32,64
-- parity type of memory 0-no parity, 1-odd parity, 2-even parity
C_PARITY_TYPE_MEM_0 : integer range 0 to 2 := 0;
C_PARITY_TYPE_MEM_1 : integer range 0 to 2 := 0;
C_PARITY_TYPE_MEM_2 : integer range 0 to 2 := 0;
C_PARITY_TYPE_MEM_3 : integer range 0 to 2 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_0 : integer range 0 to 1 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_1 : integer range 0 to 1 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_2 : integer range 0 to 1 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_3 : integer range 0 to 1 := 0;
-- Memory read and write access times for all memory banks
C_SYNCH_PIPEDELAY_0 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_0 : integer := 15000;
C_TAVDV_PS_MEM_0 : integer := 15000;
C_TPACC_PS_FLASH_0 : integer := 25000;
C_THZCE_PS_MEM_0 : integer := 7000;
C_THZOE_PS_MEM_0 : integer := 7000;
C_TWC_PS_MEM_0 : integer := 15000;
C_TWP_PS_MEM_0 : integer := 12000;
C_TWPH_PS_MEM_0 : integer := 12000;
C_TLZWE_PS_MEM_0 : integer := 0;
C_WR_REC_TIME_MEM_0 : integer := 270000000;
C_SYNCH_PIPEDELAY_1 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_1 : integer := 15000;
C_TAVDV_PS_MEM_1 : integer := 15000;
C_TPACC_PS_FLASH_1 : integer := 25000;
C_THZCE_PS_MEM_1 : integer := 7000;
C_THZOE_PS_MEM_1 : integer := 7000;
C_TWC_PS_MEM_1 : integer := 15000;
C_TWP_PS_MEM_1 : integer := 12000;
C_TWPH_PS_MEM_1 : integer := 12000;
C_TLZWE_PS_MEM_1 : integer := 0;
C_WR_REC_TIME_MEM_1 : integer := 270000000;
C_SYNCH_PIPEDELAY_2 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_2 : integer := 15000;
C_TAVDV_PS_MEM_2 : integer := 15000;
C_TPACC_PS_FLASH_2 : integer := 25000;
C_THZCE_PS_MEM_2 : integer := 7000;
C_THZOE_PS_MEM_2 : integer := 7000;
C_TWC_PS_MEM_2 : integer := 15000;
C_TWP_PS_MEM_2 : integer := 12000;
C_TWPH_PS_MEM_2 : integer := 12000;
C_TLZWE_PS_MEM_2 : integer := 0;
C_WR_REC_TIME_MEM_2 : integer := 270000000;
C_SYNCH_PIPEDELAY_3 : integer range 1 to 2 := 2;
C_TCEDV_PS_MEM_3 : integer := 15000;
C_TAVDV_PS_MEM_3 : integer := 15000;
C_TPACC_PS_FLASH_3 : integer := 25000;
C_THZCE_PS_MEM_3 : integer := 7000;
C_THZOE_PS_MEM_3 : integer := 7000;
C_TWC_PS_MEM_3 : integer := 15000;
C_TWP_PS_MEM_3 : integer := 12000;
C_TWPH_PS_MEM_3 : integer := 12000;
C_TLZWE_PS_MEM_3 : integer := 0 ;
C_WR_REC_TIME_MEM_3 : integer := 270000000
);
port (
-- -- AXI Slave signals ------------------------------------------------------
-- AXI Global System Signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
rdclk : in std_logic;
-- axi lite interface
-- -- axi write address Channel Signals
s_axi_reg_awaddr : in std_logic_vector
(4 downto 0);
s_axi_reg_awvalid : in std_logic;
s_axi_reg_awready : out std_logic;
-- -- axi write channel Signals
s_axi_reg_wdata : in std_logic_vector
(31 downto 0);
s_axi_reg_wstrb : in std_logic_vector
(3 downto 0);
s_axi_reg_wvalid : in std_logic;
s_axi_reg_wready : out std_logic;
-- -- axi write response Channel Signals
s_axi_reg_bresp : out std_logic_vector(1 downto 0);
s_axi_reg_bvalid : out std_logic;
s_axi_reg_bready : in std_logic;
-- -- axi read address Channel Signals
s_axi_reg_araddr : in std_logic_vector
(4 downto 0);
s_axi_reg_arvalid : in std_logic;
s_axi_reg_arready : out std_logic;
-- -- axi read data Channel Signals
s_axi_reg_rdata : out std_logic_vector
(31 downto 0);
s_axi_reg_rresp : out std_logic_vector(1 downto 0);
s_axi_reg_rvalid : out std_logic;
s_axi_reg_rready : in std_logic;
-- -- axi full interface
-- -- axi write address Channel Signals
s_axi_mem_awid : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
s_axi_mem_awaddr : in std_logic_vector(31 downto 0);
s_axi_mem_awlen : in std_logic_vector(7 downto 0);
s_axi_mem_awsize : in std_logic_vector(2 downto 0);
s_axi_mem_awburst : in std_logic_vector(1 downto 0);
s_axi_mem_awlock : in std_logic;
s_axi_mem_awcache : in std_logic_vector(3 downto 0);
s_axi_mem_awprot : in std_logic_vector(2 downto 0);
s_axi_mem_awvalid : in std_logic;
s_axi_mem_awready : out std_logic;
-- -- axi write channel Signals
s_axi_mem_wdata : in std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
s_axi_mem_wstrb : in std_logic_vector
(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0);
s_axi_mem_wlast : in std_logic;
s_axi_mem_wvalid : in std_logic;
s_axi_mem_wready : out std_logic;
-- -- axi write response Channel Signals
s_axi_mem_bid : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
s_axi_mem_bresp : out std_logic_vector(1 downto 0);
s_axi_mem_bvalid : out std_logic;
s_axi_mem_bready : in std_logic;
-- -- axi read address Channel Signals
s_axi_mem_arid : in std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1) downto 0);
s_axi_mem_araddr : in std_logic_vector(31 downto 0);
s_axi_mem_arlen : in std_logic_vector(7 downto 0);
s_axi_mem_arsize : in std_logic_vector(2 downto 0);
s_axi_mem_arburst : in std_logic_vector(1 downto 0);
s_axi_mem_arlock : in std_logic;
s_axi_mem_arcache : in std_logic_vector(3 downto 0);
s_axi_mem_arprot : in std_logic_vector(2 downto 0);
s_axi_mem_arvalid : in std_logic;
s_axi_mem_arready : out std_logic;
-- -- axi read data Channel Signals
s_axi_mem_rid : out std_logic_vector((C_S_AXI_MEM_ID_WIDTH-1)
downto 0);
s_axi_mem_rdata : out std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1)
downto 0);
s_axi_mem_rresp : out std_logic_vector(1 downto 0);
s_axi_mem_rlast : out std_logic;
s_axi_mem_rvalid : out std_logic;
s_axi_mem_rready : in std_logic;
-- memory signals
mem_dq_i : in std_logic_vector((C_MAX_MEM_WIDTH-1) downto 0);
mem_dq_o : out std_logic_vector((C_MAX_MEM_WIDTH-1) downto 0);
mem_dq_t : out std_logic_vector((C_MAX_MEM_WIDTH-1) downto 0);
mem_dq_parity_i : in std_logic_vector(((C_MAX_MEM_WIDTH/8)-1) downto 0);
mem_dq_parity_o : out std_logic_vector(((C_MAX_MEM_WIDTH/8)-1) downto 0);
mem_dq_parity_t : out std_logic_vector(((C_MAX_MEM_WIDTH/8)-1) downto 0);
mem_a : out std_logic_vector(31 downto 0);
-- chip selects
mem_ce : out std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
mem_cen : out std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-- read enable
mem_oen : out std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-- write enable
mem_wen : out std_logic;-- write enable
-- byte enables
mem_ben : out std_logic_vector((C_MAX_MEM_WIDTH/8-1) downto 0);
mem_qwen : out std_logic_vector((C_MAX_MEM_WIDTH/8-1) downto 0);
-- reset or power down
mem_rpn : out std_logic;
-- address valid active low
mem_adv_ldn : out std_logic;
-- interleaved burst order
mem_lbon : out std_logic;
-- clock enable
mem_cken : out std_logic;
-- synch mem read not write signal
mem_rnw : out std_logic;
--
mem_cre : out std_logic;
mem_wait : in std_logic_vector(C_NUM_BANKS_MEM -1 downto 0)
);
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
attribute MAX_FANOUT of rdclk : signal is "10000";
-- Added attribute to FIX CR CR204317. The following attribute prevent
-- the tools from optimizing the tristate control down to a single
-- registered signal and to pack input, output, and tri-state registers
-- into the IOB.
attribute EQUIVALENT_REGISTER_REMOVAL : string;
attribute EQUIVALENT_REGISTER_REMOVAL of Mem_DQ_T: signal is "no";
attribute EQUIVALENT_REGISTER_REMOVAL of MEM_DQ_PARITY_T: signal is "no";
-- SIGIS attribute for specifying clocks,interrrupts,resets for EDK
attribute SIGIS : string;
attribute SIGIS of s_axi_aclk : signal is "Clk" ;
attribute SIGIS of s_axi_aresetn : signal is "Rst" ;
attribute SIGIS of rdclk : signal is "Clk" ;
-- Minimum size attribute for EDK
attribute MIN_SIZE : string;
attribute MIN_SIZE of C_S_AXI_MEM0_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_S_AXI_MEM1_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_S_AXI_MEM2_BASEADDR : constant is "0x08";
attribute MIN_SIZE of C_S_AXI_MEM3_BASEADDR : constant is "0x08";
-- Assignment attribute for EDK
attribute ASSIGNMENT : string;
attribute ASSIGNMENT of C_S_AXI_MEM0_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM0_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM1_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM1_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM2_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM2_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM3_BASEADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM3_HIGHADDR : constant is "REQUIRE";
attribute ASSIGNMENT of C_S_AXI_MEM_ADDR_WIDTH : constant is "CONSTANT";
-- ADDR_TYPE attribute for EDK
attribute ADDR_TYPE : string;
attribute ADDR_TYPE of C_S_AXI_MEM0_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM0_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM1_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM1_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM2_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM2_HIGHADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM3_BASEADDR : constant is "MEMORY";
attribute ADDR_TYPE of C_S_AXI_MEM3_HIGHADDR : constant is "MEMORY";
------------------------------------------------------------------------------
-- end of PSFUtil MPD attributes
------------------------------------------------------------------------------
end axi_emc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_emc is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
--constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_emc,{"
-- & "c_family=" & C_FAMILY
-- & ",c_instance=" & C_INSTANCE
-- & ",c_axi_clk_period_ps=" & integer'image(C_AXI_CLK_PERIOD_PS)
-- & ",c_lflash_period_ps=" & integer'image(C_LFLASH_PERIOD_PS)
-- & ",c_linear_flash_sync_burst=" & integer'image(C_LINEAR_FLASH_SYNC_BURST)
-- & ",c_s_axireg_addr_width=" & integer'image(C_S_AXI_REG_ADDR_WIDTH)
-- & ",c_s_axi_reg_data_width=" & integer'image(C_S_AXI_REG_DATA_WIDTH)
-- & ",c_s_axi_en_reg=" & integer'image(C_S_AXI_EN_REG)
-- & ",c_s_axi_mem_addr_width=" & integer'image(C_S_AXI_MEM_ADDR_WIDTH)
-- & ",c_s_axi_mem_data_width=" & integer'image(C_S_AXI_MEM_DATA_WIDTH)
-- & ",c_s_axi_mem_id_width=" & integer'image(C_S_AXI_MEM_ID_WIDTH)
-- & ",c_include_negedge_ioregs=" & integer'image(C_INCLUDE_NEGEDGE_IOREGS)
-- & ",c_num_banks_mem=" & integer'image(C_NUM_BANKS_MEM)
-- & ",c_mem0_type=" & integer'image(C_MEM0_TYPE)
-- & ",c_mem1_type=" & integer'image(C_MEM1_TYPE)
-- & ",c_mem2_type=" & integer'image(C_MEM2_TYPE)
-- & ",c_mem3_type=" & integer'image(C_MEM3_TYPE)
-- & ",c_mem0_width=" & integer'image(C_MEM0_WIDTH)
-- & ",c_mem1_width=" & integer'image(C_MEM1_WIDTH)
-- & ",c_mem2_width=" & integer'image(C_MEM2_WIDTH)
-- & ",c_mem3_width=" & integer'image(C_MEM3_WIDTH)
-- & ",c_max_mem_width=" & integer'image(C_MAX_MEM_WIDTH)
-- & ",c_parity_type_mem_0=" & integer'image(C_PARITY_TYPE_MEM_0)
-- & ",c_parity_type_mem_1=" & integer'image(C_PARITY_TYPE_MEM_1)
-- & ",c_parity_type_mem_2=" & integer'image(C_PARITY_TYPE_MEM_2)
-- & ",c_parity_type_mem_3=" & integer'image(C_PARITY_TYPE_MEM_3)
-- & ",c_include_datawidth_matching_0=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_0)
-- & ",c_include_datawidth_matching_1=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_1)
-- & ",c_include_datawidth_matching_2=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_2)
-- & ",c_include_datawidth_matching_3=" & integer'image(C_INCLUDE_DATAWIDTH_MATCHING_3)
-- & ",c_synch_pipedelay_0=" & integer'image(C_SYNCH_PIPEDELAY_0)
-- & ",c_synch_pipedelay_1=" & integer'image(C_SYNCH_PIPEDELAY_1)
-- & ",c_synch_pipedelay_2=" & integer'image(C_SYNCH_PIPEDELAY_2)
-- & ",c_synch_pipedelay_3=" & integer'image(C_SYNCH_PIPEDELAY_3)
-- & ",c_tcedv_ps_mem_0=" & integer'image(C_TCEDV_PS_MEM_0)
-- & ",c_tcedv_ps_mem_1=" & integer'image(C_TCEDV_PS_MEM_1)
-- & ",c_tcedv_ps_mem_2=" & integer'image(C_TCEDV_PS_MEM_2)
-- & ",c_tcedv_ps_mem_=3" & integer'image(C_TCEDV_PS_MEM_3)
-- & ",c_tavdv_ps_mem_0=" & integer'image(C_TAVDV_PS_MEM_0)
-- & ",c_tavdv_ps_mem_1=" & integer'image(C_TAVDV_PS_MEM_1)
-- & ",c_tavdv_ps_mem_2=" & integer'image(C_TAVDV_PS_MEM_2)
-- & ",c_tavdv_ps_mem_3=" & integer'image(C_TAVDV_PS_MEM_3)
-- & ",c_tpacc_ps_flash_0=" & integer'image(C_TPACC_PS_FLASH_0)
-- & ",c_tpacc_ps_flash_1=" & integer'image(C_TPACC_PS_FLASH_1)
-- & ",c_tpacc_ps_flash_2=" & integer'image(C_TPACC_PS_FLASH_2)
-- & ",c_tpacc_ps_flash_3=" & integer'image(C_TPACC_PS_FLASH_3)
-- & ",c_thzce_ps_mem_0=" & integer'image(C_THZCE_PS_MEM_0)
-- & ",c_thzce_ps_mem_1=" & integer'image(C_THZCE_PS_MEM_1)
-- & ",c_thzce_ps_mem_2=" & integer'image(C_THZCE_PS_MEM_2)
-- & ",c_thzce_ps_mem_3=" & integer'image(C_THZCE_PS_MEM_3)
-- & ",c_thzoe_ps_mem_0=" & integer'image(C_THZOE_PS_MEM_0)
-- & ",c_thzoe_ps_mem_1=" & integer'image(C_THZOE_PS_MEM_1)
-- & ",c_thzoe_ps_mem_2=" & integer'image(C_THZOE_PS_MEM_2)
-- & ",c_thzoe_ps_mem_3=" & integer'image(C_THZOE_PS_MEM_3)
-- & ",c_twc_ps_mem_0=" & integer'image(C_TWC_PS_MEM_0)
-- & ",c_twc_ps_mem_1=" & integer'image(C_TWC_PS_MEM_1)
-- & ",c_twc_ps_mem_2=" & integer'image(C_TWC_PS_MEM_2)
-- & ",c_twc_ps_mem_3=" & integer'image(C_TWC_PS_MEM_3)
-- & ",c_twp_ps_mem_0=" & integer'image(C_TWP_PS_MEM_0)
-- & ",c_twp_ps_mem_1=" & integer'image(C_TWP_PS_MEM_1)
-- & ",c_twp_ps_mem_2=" & integer'image(C_TWP_PS_MEM_2)
-- & ",c_twp_ps_mem_3=" & integer'image(C_TWP_PS_MEM_3)
-- & ",c_twph_ps_mem_0=" & integer'image(C_TWPH_PS_MEM_0)
-- & ",c_twph_ps_mem_1=" & integer'image(C_TWPH_PS_MEM_1)
-- & ",c_twph_ps_mem_2=" & integer'image(C_TWPH_PS_MEM_2)
-- & ",c_twph_ps_mem_3=" & integer'image(C_TWPH_PS_MEM_3)
-- & ",c_tlzwe_ps_mem_0=" & integer'image(C_TLZWE_PS_MEM_0)
-- & ",c_tlzwe_ps_mem_1=" & integer'image(C_TLZWE_PS_MEM_1)
-- & ",c_tlzwe_ps_mem_2=" & integer'image(C_TLZWE_PS_MEM_2)
-- & ",c_tlzwe_ps_mem_3=" & integer'image(C_TLZWE_PS_MEM_3)
-- & ",c_wr_rec_time_mem_0=" & integer'image(C_WR_REC_TIME_MEM_0)
-- & ",c_wr_rec_time_mem_1=" & integer'image(C_WR_REC_TIME_MEM_1)
-- & ",c_wr_rec_time_mem_2=" & integer'image(C_WR_REC_TIME_MEM_2)
-- & ",c_wr_rec_time_mem_3=" & integer'image(C_WR_REC_TIME_MEM_3)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of implementation : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- addresses for axi_slave_burst are 64-bits wide - create constants to
-- zero the most significant address bits
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_S_AXI_MEM_ADDR_WIDTH-1)
:= (others => '0');
-- four banks with SRAM, ASYNC SRAM, PSRAM, Cellular RAM, Flash memory
type MEM_TYPE_ARRAY_TYPE is array (0 to 3) of integer range 0 to 5;
type MEM_PARITY_ARRAY_TYPE is array (0 to 3) of integer range 0 to 2;
-----------------------------------------------------------------------------
-- Function: get_AXI_ARD_ADDR_RANGE_ARRAY
-- Purpose: Fill AXI_ARD_ADDR_RANGE_ARRAY based on input parameters
-----------------------------------------------------------------------------
function get_AXI_ARD_ADDR_RANGE_ARRAY return SLV64_ARRAY_TYPE is
variable axi_ard_addr_range_array_v : SLV64_ARRAY_TYPE
(0 to C_NUM_BANKS_MEM*2-1);
begin
if (C_NUM_BANKS_MEM = 1) then
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
elsif (C_NUM_BANKS_MEM = 2) then
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
axi_ard_addr_range_array_v(2) := ZERO_ADDR_PAD&C_S_AXI_MEM1_BASEADDR;
axi_ard_addr_range_array_v(3) := ZERO_ADDR_PAD&C_S_AXI_MEM1_HIGHADDR;
elsif (C_NUM_BANKS_MEM = 3) then
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
axi_ard_addr_range_array_v(2) := ZERO_ADDR_PAD&C_S_AXI_MEM1_BASEADDR;
axi_ard_addr_range_array_v(3) := ZERO_ADDR_PAD&C_S_AXI_MEM1_HIGHADDR;
axi_ard_addr_range_array_v(4) := ZERO_ADDR_PAD&C_S_AXI_MEM2_BASEADDR;
axi_ard_addr_range_array_v(5) := ZERO_ADDR_PAD&C_S_AXI_MEM2_HIGHADDR;
else
axi_ard_addr_range_array_v(0) := ZERO_ADDR_PAD&C_S_AXI_MEM0_BASEADDR;
axi_ard_addr_range_array_v(1) := ZERO_ADDR_PAD&C_S_AXI_MEM0_HIGHADDR;
axi_ard_addr_range_array_v(2) := ZERO_ADDR_PAD&C_S_AXI_MEM1_BASEADDR;
axi_ard_addr_range_array_v(3) := ZERO_ADDR_PAD&C_S_AXI_MEM1_HIGHADDR;
axi_ard_addr_range_array_v(4) := ZERO_ADDR_PAD&C_S_AXI_MEM2_BASEADDR;
axi_ard_addr_range_array_v(5) := ZERO_ADDR_PAD&C_S_AXI_MEM2_HIGHADDR;
axi_ard_addr_range_array_v(6) := ZERO_ADDR_PAD&C_S_AXI_MEM3_BASEADDR;
axi_ard_addr_range_array_v(7) := ZERO_ADDR_PAD&C_S_AXI_MEM3_HIGHADDR;
end if;
return axi_ard_addr_range_array_v;
end function get_AXI_ARD_ADDR_RANGE_ARRAY;
constant AXI_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= get_AXI_ARD_ADDR_RANGE_ARRAY;
-----------------------------------------------------------------------------
-- Function: get_axi_ard_num_ce_array
-- Purpose: Fill AXI_NUM_CE_ARRAY based on input parameters
-----------------------------------------------------------------------------
function get_axi_ard_num_ce_array return INTEGER_ARRAY_TYPE is
variable axi_ard_num_ce_array_v : INTEGER_ARRAY_TYPE(0 to C_NUM_BANKS_MEM-1);
begin
if (C_NUM_BANKS_MEM = 1) then
axi_ard_num_ce_array_v(0) := 1; -- memories have only 1 CE
elsif (C_NUM_BANKS_MEM = 2) then
axi_ard_num_ce_array_v(0) := 1;
axi_ard_num_ce_array_v(1) := 1;
elsif (C_NUM_BANKS_MEM = 3) then
axi_ard_num_ce_array_v(0) := 1;
axi_ard_num_ce_array_v(1) := 1;
axi_ard_num_ce_array_v(2) := 1;
else
axi_ard_num_ce_array_v(0) := 1;
axi_ard_num_ce_array_v(1) := 1;
axi_ard_num_ce_array_v(2) := 1;
axi_ard_num_ce_array_v(3) := 1;
end if;
return axi_ard_num_ce_array_v;
end function get_axi_ard_num_ce_array;
-------------------------------------------------------------------------------
-- constant declaration
-----------------------
constant AXI_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= get_axi_ard_num_ce_array;
-- axi full read/write interconnect related parameters
constant C_S_AXI_MEM_SUPPORTS_WRITE : integer := 1;
constant C_S_AXI_MEM_SUPPORTS_READ : integer := 1;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
--IPIC request qualifier signals
signal ip2bus_rdack : std_logic;
signal ip2bus_wrack : std_logic;
signal ip2bus_addrack : std_logic;
signal ip2bus_errack : std_logic;
-- IPIC address, data signals
signal ip2bus_data : std_logic_vector(0 to (C_S_AXI_MEM_DATA_WIDTH-1));
signal bus2ip_addr : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
signal bus2ip_addr_temp : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
-- lower two bits address to generate the byte level address
signal bus2ip_addr_reg : std_logic_vector(0 to 2);
-- Bus2IP_* Signals
signal bus2ip_data : std_logic_vector(0 to (C_S_AXI_MEM_DATA_WIDTH-1));
-- below little endian signals are for data & BE swapping
signal temp_bus2ip_data : std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal temp_ip2bus_data : std_logic_vector((C_S_AXI_MEM_DATA_WIDTH-1) downto 0);
signal temp_bus2ip_be : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0);
--
signal bus2ip_rnw : std_logic;
signal bus2ip_rdreq_i : std_logic;
signal bus2ip_wrreq_i : std_logic;
--
signal bus2ip_cs_i : std_logic;
----
signal bus2ip_cs : std_logic_vector
(0 to ((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
-- big endian bus2ip_cs is used for EMC to maintain its big-endian structure
----
signal temp_bus2ip_cs : std_logic_vector
(((AXI_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
----
signal bus2ip_rdce : std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector
(0 to calc_num_ce(AXI_ARD_NUM_CE_ARRAY)-1);
--
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_MEM_DATA_WIDTH/8)-1);
signal bus2ip_burst : std_logic;
-- External memory signals
signal mem_dq_o_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
signal mem_dq_i_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
signal mem_dq_t_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH-1));
signal mem_dq_parity_o_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_dq_parity_t_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_dq_parity_i_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
--
signal parity_error_adrss : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
signal parity_error_MEM : std_logic_vector(1 downto 0);
signal err_parity_bits : std_logic_vector(2 downto 0);
--
signal mem_cen_i : std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
signal mem_oen_i : std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
signal mem_wen_i : std_logic;
signal mem_qwen_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_ben_i : std_logic_vector(0 to (C_MAX_MEM_WIDTH/8-1));
signal mem_adv_ldn_i : std_logic;
signal mem_cken_i : std_logic;
signal mem_ce_i : std_logic_vector(0 to (C_NUM_BANKS_MEM-1));
signal mem_a_i : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
signal bus2ip_burstlength : std_logic_vector(0 to 7);
signal Type_of_xfer : std_logic;
signal psram_page_mode : std_logic;
signal bus2ip_reset : std_logic;
signal temp_single_0 : std_logic;
signal temp_single_1 : std_logic;
signal temp_single_2 : std_logic;
signal or_reduced_rdce_d1 : std_logic;
signal or_reduced_wrce : std_logic;
signal bus2ip_wrreq_reg : std_logic;
signal original_wrce : std_logic;
signal Bus2IP_RdReq_emc : std_logic;
signal Bus2IP_WrReq_emc : std_logic;
signal synch_mem, last_addr1 : std_logic;
signal axi_trans_size_reg_int : std_logic_vector(1 downto 0); -- 1/3/2013
signal axi_lite_ip2bus_wrack_d1: std_logic;
signal axi_arsize : std_logic_vector(2 downto 0) := (OTHERS => '0');
--*
--**
-------------------------------------------------------------------------------
-- not_all_psram: checks if any of the memory is of PSRAM type. PSRAM is assigned
---------------- with value 4, so check if MEM_TYPE = 4 and return 0 or 1.
function not_all_psram(input_array : MEM_TYPE_ARRAY_TYPE;
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 4 := 0;
begin
for i in 0 to num_real_elements -1 loop
if input_array(i) = 4 then
sum := sum + 1;
end if;
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function not_all_psram;
-------------------------------------------------------------------------------
-- not_all_parity : check if any of the memory is assigned with PARITY bit
------------------ if any of the memory is assigned with parity, return 1.
function not_all_parity(input_array : MEM_PARITY_ARRAY_TYPE;
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 4 := 0;
begin
for i in 0 to num_real_elements -1 loop
if input_array(i) /= 0 then
sum := sum + 1;
end if;
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function not_all_parity;
-------------------------------------------------------------------------------
-- sync_get_val: Check if the memory is SYNC memory type, if yes return 1.
---------------
function sync_get_val(x: integer; y: integer) return integer is
begin
if x = 0 then
return 1;
else
return 0;
end if;
end function sync_get_val;
-------------------------------------------------------------------------------
-- page_get_val: If Page Mode Flash or PSRAM, then return 1.
---------------
function page_get_val(x: integer) return integer is
begin
if x = 3 or x = 4 then
return 1;
else
return 0;
end if;
end function page_get_val;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- psram_or_lflash_sync: If PSRAM or Linear Flash sync burst, then return 1.
---------------
function psram_or_lflash_sync(x: integer; y: integer) return integer is
begin
if ((x = 1) or (y = 1)) then
return 1;
else
return 0;
end if;
end function psram_or_lflash_sync;
-------------------------------------------------------------------------------
constant MEM_TYPE_ARRAY : MEM_TYPE_ARRAY_TYPE :=
(
C_MEM0_TYPE,
C_MEM1_TYPE,
C_MEM2_TYPE,
C_MEM3_TYPE
);
constant MEM_PARITY_ARRAY : MEM_PARITY_ARRAY_TYPE :=
(
C_PARITY_TYPE_MEM_0,
C_PARITY_TYPE_MEM_1,
C_PARITY_TYPE_MEM_2,
C_PARITY_TYPE_MEM_3
);
constant GLOBAL_PSRAM_MEM : integer range 0 to 1
:= not_all_psram(MEM_TYPE_ARRAY,
C_NUM_BANKS_MEM);
constant GLOBAL_PSRAM_FLASH_MEM : integer range 0 to 1
:= psram_or_lflash_sync(C_LINEAR_FLASH_SYNC_BURST,
GLOBAL_PSRAM_MEM);
constant GLOBAL_PARITY_MEM : integer range 0 to 1
:= not_all_parity(MEM_PARITY_ARRAY,
C_NUM_BANKS_MEM);
-- if SYNC memories are configured, then below parameter will be = 1
constant C_SYNCH_MEM_0 : integer :=sync_get_val(C_MEM0_TYPE, C_LINEAR_FLASH_SYNC_BURST);
constant C_SYNCH_MEM_1 : integer :=sync_get_val(C_MEM1_TYPE, C_LINEAR_FLASH_SYNC_BURST);
constant C_SYNCH_MEM_2 : integer :=sync_get_val(C_MEM2_TYPE, C_LINEAR_FLASH_SYNC_BURST);
constant C_SYNCH_MEM_3 : integer :=sync_get_val(C_MEM3_TYPE, C_LINEAR_FLASH_SYNC_BURST);
-- if Page Mode or PSRAM memories are configured,then below parameter will be= 1
constant C_PAGEMODE_FLASH_0 : integer :=page_get_val(C_MEM0_TYPE);
constant C_PAGEMODE_FLASH_1 : integer :=page_get_val(C_MEM1_TYPE);
constant C_PAGEMODE_FLASH_2 : integer :=page_get_val(C_MEM2_TYPE);
constant C_PAGEMODE_FLASH_3 : integer :=page_get_val(C_MEM3_TYPE);
--signal Mem_CRE_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
signal bus2ip_ce_lite_cmb : std_logic_vector(7 downto 0);
signal sync_mode : std_logic_vector(C_NUM_BANKS_MEM-1 downto 0):= (others => '0');
signal Cre_reg_en : std_logic_vector(C_NUM_BANKS_MEM-1 downto 0):= (others => '0');-- := '0';
signal Cre_reg_en_reduced : std_logic:= '0';
signal CTRL_REG : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal Linear_flash_brst_rd_flag : std_logic := '0';
signal Linear_flash_rd_data_ack: std_logic := '0';
signal mem_a_io : std_logic_vector(31 downto 0);
signal mem_wait_io : std_logic_vector(C_NUM_BANKS_MEM -1 downto 0);
signal Mem_WAIT_reg : std_logic := '0';
signal Mem_WAIT_reg_d1,
Mem_WAIT_reg_d2,
Mem_WAIT_reg_one_hot : std_logic := '0';
signal CTRL_REG_DATA: std_logic_vector(15 downto 0);
signal CTRL_REG_ADDR: std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0) := (others => '0');
signal sync_burst_data_ack : std_logic;
signal sync_data_select : std_logic;
constant FREQ_FACT_INT : integer range 0 to 15
:= (C_LFLASH_PERIOD_PS/C_AXI_CLK_PERIOD_PS);
constant FLASH_FREQ_FACTOR : std_logic_vector(3 downto 0)
:= conv_std_logic_vector(FREQ_FACT_INT - 1, 4);
signal test_rd : std_logic;
signal ADDR_PROGRAM : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal ADDR_PROGRAM_D : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal ADDR_SYNCH_BURST_RD : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal ADDR_SYNCH_BURST_RD_D : std_logic_vector((C_S_AXI_MEM_ADDR_WIDTH-1) downto 0);
signal Addr_select : std_logic := '0';
signal S_AXI_MEM_BVALID1 : std_logic;
signal S_AXI_MEM_WREADY1 : std_logic;
signal S_AXI_MEM_ARREADY1 : std_logic;
signal temp_strb : std_logic_vector(((C_S_AXI_MEM_DATA_WIDTH/8)-1) downto 0) := (others => '1');
signal temp_prog_cmd_data : std_logic_vector(15 downto 0) := X"0040";
signal Mem_WAIT_temp0 : std_logic := '0';
signal Mem_WAIT_temp1 : std_logic := '0';
signal Mem_WAIT_temp2 : std_logic := '0';
signal Mem_WAIT_temp3 : std_logic := '0';
signal Mem_WAIT_cmb_delay: std_logic := '0';
signal Parity_err_i : std_logic;
signal s_axi_reg_bvalid_i : std_logic;
signal s_axi_reg_awready_i : std_logic;
signal pr_idle, axi_sm_ns_IDLE : std_logic; -- 11-12-2012
signal mem_cre_int : std_logic;
signal mem_a_int : std_logic_vector(0 to (C_S_AXI_MEM_ADDR_WIDTH-1));
attribute IOB : string;
attribute IOB of Mem_WAIT_io : signal is "true";
attribute IOB of Mem_cre_int : signal is "true";
attribute IOB of Mem_a_int : signal is "true";
-----
begin -- architecture IMP
-----
s_axi_mem_bvalid <= S_AXI_MEM_BVALID1;
s_axi_mem_wready <= S_AXI_MEM_WREADY1;
s_axi_mem_arready <= S_AXI_MEM_ARREADY1;
-- EMC memory read/write access times assignments
-- CMD_ADDR_LOGIC_LFLASH : if (C_LINEAR_FLASH_SYNC_BURST = 1) generate
-- Mem_A <= mem_a_i when Cre_reg_en = '0' else CTRL_REG_ADDR ;
-- end generate CMD_ADDR_LOGIC_LFLASH;
-- ADDR_LOGIC_NO_LFLASH : if (C_LINEAR_FLASH_SYNC_BURST = 0) generate
mem_a_io <= ADDR_PROGRAM when Addr_select = '1' else
ADDR_SYNCH_BURST_RD when Linear_flash_brst_rd_flag = '1' else mem_a_i ;
-- end generate ADDR_LOGIC_NO_LFLASH;
mem_wen <= mem_wen_i ;
mem_adv_ldn <= mem_adv_ldn_i;
mem_cken <= mem_cken_i ;
err_parity_bits <= parity_error_MEM & Parity_err_i;
--axi_arsize <= S_AXI_MEM_ARSIZE when (S_AXI_MEM_ARVALID = '1' and S_AXI_MEM_ARREADY1 = '1') else axi_arsize;
mem_a <= mem_a_int;
mem_cre <= mem_cre_int;
INPUT_MEM_A_REG_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
mem_a_int <= mem_a_io;
end if;
end process INPUT_MEM_A_REG_PROCESS;
INPUT_MEM_WAIT_REG_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_io(C_NUM_BANKS_MEM -1 downto 0) <= Mem_WAIT(C_NUM_BANKS_MEM -1 downto 0);
end if;
end process INPUT_MEM_WAIT_REG_PROCESS;
process (s_axi_aclk) begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if S_AXI_MEM_ARVALID = '1' and S_AXI_MEM_ARREADY1 = '1' then
axi_arsize <= S_AXI_MEM_ARSIZE;
else
axi_arsize <= axi_arsize;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- AXI EMC is little endian and EMC COMMON is still big endian, to make
-- this interface work normally, we need to swap the Write and read data
-- bytes comming from and going to external memory interface
---------------------------------------------------------------------------
ENDIAN_CEN_BANKS_1 : if (C_NUM_BANKS_MEM = 1) generate
mem_cen(0) <= mem_cen_i(0);
mem_ce(0) <= mem_ce_i(0);
end generate ENDIAN_CEN_BANKS_1;
ENDIAN_CEN_BANKS_2 : if (C_NUM_BANKS_MEM = 2) generate
mem_cen(0) <= mem_cen_i(0);
mem_cen(1) <= mem_cen_i(1);
mem_ce(0) <= mem_ce_i(0);
mem_ce(1) <= mem_ce_i(1);
end generate ENDIAN_CEN_BANKS_2;
ENDIAN_CEN_BANKS_3 : if (C_NUM_BANKS_MEM = 3) generate
mem_cen(0) <= mem_cen_i(0);
mem_cen(1) <= mem_cen_i(1);
mem_cen(2) <= mem_cen_i(2);
mem_ce(0) <= mem_ce_i(0);
mem_ce(1) <= mem_ce_i(1);
mem_ce(2) <= mem_ce_i(2);
end generate ENDIAN_CEN_BANKS_3;
ENDIAN_CEN_BANKS_4 : if (C_NUM_BANKS_MEM = 4) generate
mem_cen(0) <= mem_cen_i(0);
mem_cen(1) <= mem_cen_i(1);
mem_cen(2) <= mem_cen_i(2);
mem_cen(3) <= mem_cen_i(3);
mem_ce(0) <= mem_ce_i(0);
mem_ce(1) <= mem_ce_i(1);
mem_ce(2) <= mem_ce_i(2);
mem_ce(3) <= mem_ce_i(3);
end generate ENDIAN_CEN_BANKS_4;
-- assign OutPut Enable signals (Read Enable Signals)
ENDIAN_OEN_BANKS_1 : if (C_NUM_BANKS_MEM = 1) generate
mem_oen(0) <= mem_oen_i(0);
end generate ENDIAN_OEN_BANKS_1;
ENDIAN_OEN_BANKS_2 : if (C_NUM_BANKS_MEM = 2) generate
mem_oen(0) <= mem_oen_i(0);
mem_oen(1) <= mem_oen_i(1);
end generate ENDIAN_OEN_BANKS_2;
ENDIAN_OEN_BANKS_3 : if (C_NUM_BANKS_MEM = 3) generate
mem_oen(0) <= mem_oen_i(0);
mem_oen(1) <= mem_oen_i(1);
mem_oen(2) <= mem_oen_i(2);
end generate ENDIAN_OEN_BANKS_3;
ENDIAN_OEN_BANKS_4 : if (C_NUM_BANKS_MEM = 4) generate
mem_oen(0) <= mem_oen_i(0);
mem_oen(1) <= mem_oen_i(1);
mem_oen(2) <= mem_oen_i(2);
mem_oen(3) <= mem_oen_i(3);
end generate ENDIAN_OEN_BANKS_4;
-- data byte swapping for 8 bit memory
ENDIAN_MEM_CONVERSION_8 : if (C_MAX_MEM_WIDTH = 8) generate
-- output from memory core
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
-- input to memory core
mem_dq_i_i (0 to 7) <= Mem_DQ_I (7 downto 0);
mem_qwen <= mem_qwen_i;
mem_ben <= mem_ben_i;
-- o/p from memory
mem_dq_parity_o <= mem_dq_parity_o_i;
mem_dq_parity_t <= mem_dq_parity_t_i;
-- i/p to memory
mem_dq_parity_i_i <= MEM_DQ_PARITY_I;
end generate ENDIAN_MEM_CONVERSION_8;
-- data byte swapping for 16 bit memory
-- ENDIAN_MEM_CONVERSION_16: byte -by -byte swapping for 16 bit memory
---------------------------
ENDIAN_MEM_CONVERSION_16 : if (C_MAX_MEM_WIDTH = 16) generate
-- o/p to memory
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_o(15 downto 8) <= mem_dq_o_i (8 to 15);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
mem_dq_t(15 downto 8) <= mem_dq_t_i (8 to 15);
-- i/p from memory
mem_dq_i_i (0 to 7) <= Mem_DQ_I (7 downto 0);
mem_dq_i_i (8 to 15) <= Mem_DQ_I (15 downto 8);
-- qualified write enabls
mem_qwen(0) <= mem_qwen_i(0);
mem_qwen(1) <= mem_qwen_i(1);
-- byte enabls
mem_ben(0) <= mem_ben_i(0);
mem_ben(1) <= mem_ben_i(1);
-- parity bits to memory
mem_dq_parity_o(0) <= mem_dq_parity_o_i(0);
mem_dq_parity_o(1) <= mem_dq_parity_o_i(1);
mem_dq_parity_t(0) <= mem_dq_parity_t_i(0);
mem_dq_parity_t(1) <= mem_dq_parity_t_i(1);
-- parity bits from memory
mem_dq_parity_i_i(0) <= MEM_DQ_PARITY_I(0);
mem_dq_parity_i_i(1) <= MEM_DQ_PARITY_I(1);
end generate ENDIAN_MEM_CONVERSION_16;
-- data byte swapping for 32 bit memory
-- ENDIAN_MEM_CONVERSION_32: byte -by -byte swapping for 32 bit memory
ENDIAN_MEM_CONVERSION_32 : if (C_MAX_MEM_WIDTH = 32) generate
-- o/p to memory
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_o(15 downto 8) <= mem_dq_o_i (8 to 15);
mem_dq_o(23 downto 16) <= mem_dq_o_i (16 to 23);
mem_dq_o(31 downto 24) <= mem_dq_o_i (24 to 31);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
mem_dq_t(15 downto 8) <= mem_dq_t_i (8 to 15);
mem_dq_t(23 downto 16) <= mem_dq_t_i (16 to 23);
mem_dq_t(31 downto 24) <= mem_dq_t_i (24 to 31);
-- i/p from memory
mem_dq_i_i (0 to 7) <= Mem_DQ_I (7 downto 0);
mem_dq_i_i (8 to 15) <= Mem_DQ_I (15 downto 8);
mem_dq_i_i (16 to 23) <= Mem_DQ_I (23 downto 16);
mem_dq_i_i (24 to 31) <= Mem_DQ_I (31 downto 24);
-- qualified write enabls
mem_qwen(0) <= mem_qwen_i(0);
mem_qwen(1) <= mem_qwen_i(1);
mem_qwen(2) <= mem_qwen_i(2);
mem_qwen(3) <= mem_qwen_i(3);
-- byte enabls
mem_ben(0) <= mem_ben_i(0);
mem_ben(1) <= mem_ben_i(1);
mem_ben(2) <= mem_ben_i(2);
mem_ben(3) <= mem_ben_i(3);
-- parity bits to memory
mem_dq_parity_o(0) <= mem_dq_parity_o_i(0);
mem_dq_parity_o(1) <= mem_dq_parity_o_i(1);
mem_dq_parity_o(2) <= mem_dq_parity_o_i(2);
mem_dq_parity_o(3) <= mem_dq_parity_o_i(3);
mem_dq_parity_t(0) <= mem_dq_parity_t_i(0);
mem_dq_parity_t(1) <= mem_dq_parity_t_i(1);
mem_dq_parity_t(2) <= mem_dq_parity_t_i(2);
mem_dq_parity_t(3) <= mem_dq_parity_t_i(3);
-- parity bits from memory
mem_dq_parity_i_i(0) <= mem_dq_parity_i(0);
mem_dq_parity_i_i(1) <= mem_dq_parity_i(1);
mem_dq_parity_i_i(2) <= mem_dq_parity_i(2);
mem_dq_parity_i_i(3) <= mem_dq_parity_i(3);
end generate ENDIAN_MEM_CONVERSION_32;
-- data byte swapping for 64 bit memory
-- ENDIAN_MEM_CONVERSION_64: byte -by -byte swapping for 64 bit memory
ENDIAN_MEM_CONVERSION_64 : if (C_MAX_MEM_WIDTH = 64) generate
-- o/p to memory
mem_dq_o(7 downto 0) <= mem_dq_o_i (0 to 7);
mem_dq_o(15 downto 8) <= mem_dq_o_i (8 to 15);
mem_dq_o(23 downto 16) <= mem_dq_o_i (16 to 23);
mem_dq_o(31 downto 24) <= mem_dq_o_i (24 to 31);
mem_dq_o(39 downto 32) <= mem_dq_o_i (32 to 39);
mem_dq_o(47 downto 40) <= mem_dq_o_i (40 to 47);
mem_dq_o(55 downto 48) <= mem_dq_o_i (48 to 55);
mem_dq_o(63 downto 56) <= mem_dq_o_i (56 to 63);
mem_dq_t(7 downto 0) <= mem_dq_t_i (0 to 7);
mem_dq_t(15 downto 8) <= mem_dq_t_i (8 to 15);
mem_dq_t(23 downto 16) <= mem_dq_t_i (16 to 23);
mem_dq_t(31 downto 24) <= mem_dq_t_i (24 to 31);
mem_dq_t(39 downto 32) <= mem_dq_t_i (32 to 39);
mem_dq_t(47 downto 40) <= mem_dq_t_i (40 to 47);
mem_dq_t(55 downto 48) <= mem_dq_t_i (48 to 55);
mem_dq_t(63 downto 56) <= mem_dq_t_i (56 to 63);
-- o/p from memory
mem_dq_i_i (0 to 7) <= mem_dq_i (7 downto 0);
mem_dq_i_i (8 to 15) <= mem_dq_i (15 downto 8);
mem_dq_i_i (16 to 23) <= mem_dq_i (23 downto 16);
mem_dq_i_i (24 to 31) <= mem_dq_i (31 downto 24);
mem_dq_i_i (32 to 39) <= mem_dq_i (39 downto 32);
mem_dq_i_i (40 to 47) <= mem_dq_i (47 downto 40);
mem_dq_i_i (48 to 55) <= mem_dq_i (55 downto 48);
mem_dq_i_i (56 to 63) <= mem_dq_i (63 downto 56);
-- qualified write enabls
mem_qwen(0) <= mem_qwen_i(0);
mem_qwen(1) <= mem_qwen_i(1);
mem_qwen(2) <= mem_qwen_i(2);
mem_qwen(3) <= mem_qwen_i(3);
mem_qwen(4) <= mem_qwen_i(4);
mem_qwen(5) <= mem_qwen_i(5);
mem_qwen(6) <= mem_qwen_i(6);
mem_qwen(7) <= mem_qwen_i(7);
-- byte enabls
mem_ben(0) <= mem_ben_i(0);
mem_ben(1) <= mem_ben_i(1);
mem_ben(2) <= mem_ben_i(2);
mem_ben(3) <= mem_ben_i(3);
mem_ben(4) <= mem_ben_i(4);
mem_ben(5) <= mem_ben_i(5);
mem_ben(6) <= mem_ben_i(6);
mem_ben(7) <= mem_ben_i(7);
-- parity bits to memory
mem_dq_parity_o(0) <= mem_dq_parity_o_i(0);
mem_dq_parity_o(1) <= mem_dq_parity_o_i(1);
mem_dq_parity_o(2) <= mem_dq_parity_o_i(2);
mem_dq_parity_o(3) <= mem_dq_parity_o_i(3);
mem_dq_parity_o(4) <= mem_dq_parity_o_i(4);
mem_dq_parity_o(5) <= mem_dq_parity_o_i(5);
mem_dq_parity_o(6) <= mem_dq_parity_o_i(6);
mem_dq_parity_o(7) <= mem_dq_parity_o_i(7);
mem_dq_parity_t(0) <= mem_dq_parity_t_i(0);
mem_dq_parity_t(1) <= mem_dq_parity_t_i(1);
mem_dq_parity_t(2) <= mem_dq_parity_t_i(2);
mem_dq_parity_t(3) <= mem_dq_parity_t_i(3);
mem_dq_parity_t(4) <= mem_dq_parity_t_i(4);
mem_dq_parity_t(5) <= mem_dq_parity_t_i(5);
mem_dq_parity_t(6) <= mem_dq_parity_t_i(6);
mem_dq_parity_t(7) <= mem_dq_parity_t_i(7);
-- parity bits from memory
mem_dq_parity_i_i(0) <= mem_dq_parity_i(0);
mem_dq_parity_i_i(1) <= mem_dq_parity_i(1);
mem_dq_parity_i_i(2) <= mem_dq_parity_i(2);
mem_dq_parity_i_i(3) <= mem_dq_parity_i(3);
mem_dq_parity_i_i(4) <= mem_dq_parity_i(4);
mem_dq_parity_i_i(5) <= mem_dq_parity_i(5);
mem_dq_parity_i_i(6) <= mem_dq_parity_i(6);
mem_dq_parity_i_i(7) <= mem_dq_parity_i(7);
end generate ENDIAN_MEM_CONVERSION_64;
-------------------------------------------------------------------------------
-- NO_REG_EN_GEN: the below instantion is to make the output signals for
-- register interface driving '0'.
--------------
NO_REG_EN_GEN : if (C_S_AXI_EN_REG = 0) generate
-------------
begin
-------------------------------------
s_axi_reg_awready <= '0';
s_axi_reg_wready <= '0';
s_axi_reg_bresp <= (others => '0');
s_axi_reg_bvalid <= '0';
s_axi_reg_arready <= '0';
s_axi_reg_rdata <= (others => '0');
s_axi_reg_rresp <= (others => '0');
s_axi_reg_rvalid <= '0';
-- PSRAM_CONFIG_REG_DIS: if (GLOBAL_PSRAM_FLASH_MEM = 0) generate
psram_page_mode <= '0';-- Default value is psram in async mode
-- end generate PSRAM_CONFIG_REG_DIS;
-------------------------------------
end generate NO_REG_EN_GEN;
-------------------------------------------------------------------------------
-- EMC REGISTER MODULE Instantiations
-------------------------------------------------------------------------------
-- REG_EN_GEN: Include the AXI Lite IPIF and register module
--------------
REG_EN_GEN : if (C_S_AXI_EN_REG = 1) generate
-------------
-- IPIC Used Sgnals
constant RST_ACTIVE : std_logic := '0';
type MEM_PARITY_REG_ARRAY_TYPE is array(3 downto 0) of
std_logic_vector((C_S_AXI_REG_DATA_WIDTH -1) downto 0);
type MEM_PSRAM_REG_ARRAY_TYPE is array(3 downto 0) of
std_logic_vector((C_S_AXI_REG_DATA_WIDTH -1) downto 0);
signal PEAR_REG : MEM_PARITY_REG_ARRAY_TYPE;-- 4 parity regs of each 32 bit
signal PCR_REG : MEM_PSRAM_REG_ARRAY_TYPE ; -- 4 psram regs of each 32 bit
signal axi_lite_ip2bus_data_i : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal axi_lite_ip2bus_data1 : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal axi_lite_ip2bus_data2 : std_logic_vector((C_S_AXI_REG_DATA_WIDTH-1)
downto 0);
signal bus2ip_addr_lite_reg : std_logic_vector(4 downto 2);--((3+GLOBAL_PSRAM_FLASH_MEM)
-- downto 2);
signal arready_i : std_logic;
signal awready_i : std_logic;
signal rvalid : std_logic;
signal axi_lite_ip2bus_wrack_i : std_logic;
signal axi_lite_ip2bus_rdack_i : std_logic;
signal axi_lite_ip2bus_rdack1 : std_logic;
signal axi_lite_ip2bus_rdack2 : std_logic;
signal axi_lite_ip2bus_wrack1 : std_logic;
signal axi_lite_ip2bus_wrack2 : std_logic;
signal read_reg_req : std_logic;
signal write_reg_req : std_logic;
signal bus2ip_rdce_lite_cmb : std_logic_vector(7 downto 0);-- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM)) downto 0);
signal bus2ip_wrce_lite_cmb : std_logic_vector(7 downto 0);-- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM)) downto 0);
signal s_axi_reg_rresp_reg: std_logic_vector(1 downto 0);
signal s_axi_reg_bresp_reg: std_logic_vector(1 downto 0);
signal s_axi_reg_bvalid_i : std_logic;
------------------------
-----
begin
-------------------------------------------------------------------------------
-- *
-------------------------------------------------------------------------------
PSRAM_FLASH_PARITY_CE_LOCAL_REG_GEN : if (GLOBAL_PSRAM_FLASH_MEM = 1)generate
-------------------------------
--signal bus2ip_ce_lite_cmb : std_logic_vector(7 downto 0);
-----
begin-- *
-----
--* to generate the WRCE and RDCE for register access.
PSRAM_PARITY_NUM_BANKS_4_GEN: if (C_NUM_BANKS_MEM=4) generate
begin
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
when "000" => bus2ip_ce_lite_cmb <= "00000001";
when "001" => bus2ip_ce_lite_cmb <= "00000010";
when "010" => bus2ip_ce_lite_cmb <= "00000100";
when "011" => bus2ip_ce_lite_cmb <= "00001000";
when "100" => bus2ip_ce_lite_cmb <= "00010000";
when "101" => bus2ip_ce_lite_cmb <= "00100000";
when "110" => bus2ip_ce_lite_cmb <= "01000000";
when "111" => bus2ip_ce_lite_cmb <= "10000000";
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_4_GEN;
------------------------------------------
PSRAM_PARITY_NUM_BANKS_3_GEN: if (C_NUM_BANKS_MEM=3) generate
begin
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
-- when "000" => bus2ip_ce_lite_cmb <= "00000001";
-- when "001" => bus2ip_ce_lite_cmb <= "00000010";
-- when "010" => bus2ip_ce_lite_cmb <= "00000100";
-- when "011" => bus2ip_ce_lite_cmb <= "00001000"; -- this will complete the transaction without any updates
-- -- psram configuration registers
-- when "100" => bus2ip_ce_lite_cmb <= "00010000";
-- when "101" => bus2ip_ce_lite_cmb <= "00100000";
-- when "110" => bus2ip_ce_lite_cmb <= "01000000";
-- -- coverage off
-- when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- -- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- bank 2 present if SRAM is chosen
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- REGISTER HOLE - provide only ack
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- bank 2 present if PSRAM/Flash is chosen
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- REGISTER HOLE - provide only ack
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
-- end if;
-- end if;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_3_GEN;
------------------------------------------
PSRAM_PARITY_NUM_BANKS_2_GEN: if (C_NUM_BANKS_MEM=2) generate
begin
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
--when "000" => bus2ip_ce_lite_cmb <= "00000001";
--when "001" => bus2ip_ce_lite_cmb <= "00000010";
--when "010" => bus2ip_ce_lite_cmb <= "00000100"; -- this will complete the transaction without any updates
--when "011" => bus2ip_ce_lite_cmb <= "00001000"; -- this will complete the transaction without any updates
---- psram configuration registers
--when "100" => bus2ip_ce_lite_cmb <= "00010000";
--when "101" => bus2ip_ce_lite_cmb <= "00100000";
--when "110" => bus2ip_ce_lite_cmb <= "01000000"; -- this will complete the transaction without any updates
--when "111" => bus2ip_ce_lite_cmb <= "10000000"; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= (others=> '0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- REGISTER HOLE - provide only ack
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- REGISTER HOLE - provide only ack
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- REGISTER HOLE - provide only ack
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- REGISTER HOLE - provide only ack
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_2_GEN;
PSRAM_PARITY_NUM_BANKS_1_GEN: if (C_NUM_BANKS_MEM=1) generate
begin
BUS2IP_CE_GEN_P: process--(s_axi_aclk) is
(
bus2ip_addr_lite_reg(4 downto 2)
)is
--------
variable bus2ip_addr_reg_4_2 : std_logic_vector(2 downto 0);
--------
begin
--
bus2ip_addr_reg_4_2 := bus2ip_addr_lite_reg;
--
case bus2ip_addr_reg_4_2 is
--when "000" => bus2ip_ce_lite_cmb <= "00000001";
--when "001" => bus2ip_ce_lite_cmb <= "00000010";-- this will complete the transaction without any updates
--when "010" => bus2ip_ce_lite_cmb <= "00000100";-- this will complete the transaction without any updates
--when "011" => bus2ip_ce_lite_cmb <= "00001000"; -- this will complete the transaction without any updates
-- psram configuration registers
--when "100" => bus2ip_ce_lite_cmb <= "00010000";
--when "101" => bus2ip_ce_lite_cmb <= "00100000"; -- this will complete the transaction without any updates
--when "110" => bus2ip_ce_lite_cmb <= "01000000"; -- this will complete the transaction without any updates
--when "111" => bus2ip_ce_lite_cmb <= "10000000"; -- this will complete the transaction without any updates
-- coverage off
--when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- REGISTER HOLE - provide only ack
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- REGISTER HOLE - provide only ack
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- REGISTER HOLE - provide only ack
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- REGISTER HOLE - provide only ack
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- REGISTER HOLE - provide only ack
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- REGISTER HOLE - provide only ack
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_FLASH_MEM))) downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
----------------------------------------
end generate PSRAM_PARITY_NUM_BANKS_1_GEN;
end generate PSRAM_FLASH_PARITY_CE_LOCAL_REG_GEN;
-------------------------------------------------------------------------------
NO_LFLASH_PSRAM_CE_LOCAL_REG_GEN: if (GLOBAL_PSRAM_FLASH_MEM = 0)generate
-----
begin-- *
-----
--* to generate the WRCE and RDCE for register access.
NUM_BANKS_4_GEN: if (C_NUM_BANKS_MEM=4) generate
--signal bus2ip_ce_lite_cmb : std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);--9/14/2013
-----
begin
-----
BUS2IP_CE_GEN_P: process
(
bus2ip_addr_lite_reg(4 downto 2) -- (3 downto 2)
) is
--------
--variable bus2ip_addr_reg_3_2 : std_logic_vector(1 downto 0);
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is -- (3 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= "0001";
--when "01" => bus2ip_ce_lite_cmb <= "0010";
--when "10" => bus2ip_ce_lite_cmb <= "0100";
--when "11" => bus2ip_ce_lite_cmb <= "1000";
---- coverage off
--when others => bus2ip_ce_lite_cmb <= "0001";--(others => '0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen, else hole
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- bank 2 present if SRAM is chosen, else hole
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- bank 3 present if SRAM is chosen, else hole
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen, else hole
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- bank 2 present if PSRAM/Flash is chosen, else hole
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- bank 3 present if PSRAM/Flash is chosen, else hole
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate --C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_4_GEN;
------------------------------------------
NUM_BANKS_3_GEN: if (C_NUM_BANKS_MEM=3) generate
--signal bus2ip_ce_lite_cmb : std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-----
begin
-----
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)-- (3 downto 2)
) is
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= "001";
--when "01" => bus2ip_ce_lite_cmb <= "010";
--when "10" => bus2ip_ce_lite_cmb <= "100";
--when "11" => bus2ip_ce_lite_cmb <= "001"; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= "001";--(others=>'0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen, else hole
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- bank 2 present if SRAM is chosen, else hole
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- hole, provide ack in any case
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen, else hole
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- bank 2 present if PSRAM/Flash is chosen, else hole
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- hole, provide ack in any case
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_3_GEN;
------------------------------------------
NUM_BANKS_2_GEN: if (C_NUM_BANKS_MEM=2) generate
--signal bus2ip_ce_lite_cmb : std_logic_vector((C_NUM_BANKS_MEM-1) downto 0);
-----
begin
-----
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2)-- (3 downto 2)
) is
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is -- (3 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= "01";
--when "01" => bus2ip_ce_lite_cmb <= "10";
--when "10" => bus2ip_ce_lite_cmb <= "01"; -- this will complete the transaction without any updates
--when "11" => bus2ip_ce_lite_cmb <= "01"; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= "01";-- (others=>'0');
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- bank 1 present if SRAM is chosen, else hole
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- hole, provide ack in any case
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- hole, provide ack in any case
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- bank 1 present if PSRAM/Flash is chosen, else hole
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- hole, provide ack in any case
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- hole, provide ack in any case
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_2_GEN;
------------------------------------------
NUM_BANKS_1_GEN: if (C_NUM_BANKS_MEM=1) generate
--signal bus2ip_ce_lite_cmb : std_logic;
-----
begin
-----
BUS2IP_CE_GEN_P: process(
bus2ip_addr_lite_reg(4 downto 2) -- (3 downto 2)
) is
--------
begin
--
case bus2ip_addr_lite_reg(4 downto 2) is -- (3 downto 2) is
--when "00" => bus2ip_ce_lite_cmb <= '1';
--when "01" => bus2ip_ce_lite_cmb <= '1'; -- this will complete the transaction without any updates
--when "10" => bus2ip_ce_lite_cmb <= '1'; -- this will complete the transaction without any updates
--when "11" => bus2ip_ce_lite_cmb <= '1'; -- this will complete the transaction without any updates
---- coverage off
--when others => bus2ip_ce_lite_cmb <= '1';-- '0';
---- coverage on
when "000" => bus2ip_ce_lite_cmb <= "00000001";-- bank 0 present if SRAM is chosen, else hole
when "001" => bus2ip_ce_lite_cmb <= "00000010";-- hole, provide ack in any case
when "010" => bus2ip_ce_lite_cmb <= "00000100";-- hole, provide ack in any case
when "011" => bus2ip_ce_lite_cmb <= "00001000";-- hole, provide ack in any case
when "100" => bus2ip_ce_lite_cmb <= "00010000";-- bank 0 present if PSRAM/Flash is chosen, else hole
when "101" => bus2ip_ce_lite_cmb <= "00100000";-- hole, provide ack in any case
when "110" => bus2ip_ce_lite_cmb <= "01000000";-- hole, provide ack in any case
when "111" => bus2ip_ce_lite_cmb <= "10000000";-- hole, provide ack in any case
-- coverage off
when others => bus2ip_ce_lite_cmb <= (others=> '0');
-- coverage on
end case;
end process BUS2IP_CE_GEN_P;
--------------------------------------
RDCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_rdce_lite_cmb(i) <= read_reg_req and
bus2ip_ce_lite_cmb(i);
end generate RDCE_GEN;
--------------------------------------
WRCE_GEN: for i in 7 downto 0 generate -- C_NUM_BANKS_MEM-1 downto 0 generate
-----
begin
-----
bus2ip_wrce_lite_cmb(i) <= s_axi_reg_wvalid and
write_reg_req and
bus2ip_ce_lite_cmb(i);
end generate WRCE_GEN;
--------------------------------------
end generate NUM_BANKS_1_GEN;
--------------------------------------
end generate NO_LFLASH_PSRAM_CE_LOCAL_REG_GEN;
--*
s_axi_reg_awready <= axi_lite_ip2bus_wrack_i; -- awready_i;
s_axi_reg_wready <= axi_lite_ip2bus_wrack_i; -- write_reg_req;
s_axi_reg_bresp <= s_axi_reg_bresp_reg;
s_axi_reg_arready <= arready_i;
s_axi_reg_rvalid <= rvalid;
s_axi_reg_rresp <= s_axi_reg_rresp_reg;
-- AWREADY is enabled only if valid write request and no read request
awready_i <= (not write_reg_req) and
not ( s_axi_reg_arvalid or read_reg_req or rvalid ) and
s_axi_aresetn;
-- ARREADY is enabled only if valid read request and no current write request
arready_i <= not(rvalid or read_reg_req) and
not (write_reg_req)
and s_axi_aresetn;
-- WRITE_AWREADY_P: process (s_axi_aclk) is
-- begin
-- if (s_axi_aclk'event and s_axi_aclk = '1') then
-- if (s_axi_aresetn=RST_ACTIVE) then
-- s_axi_reg_awready_i <= '0';
-- --elsif (s_axi_reg_awvalid = '0') and (axi_lite_ip2bus_wrack_i = '1') then
-- -- s_axi_reg_awready_i <= '1';
-- elsif (s_axi_reg_awvalid = '1') and (s_axi_reg_awready_i = '1') then
-- s_axi_reg_awready_i <= '0';
-- else
-- s_axi_reg_awready_i <= axi_lite_ip2bus_wrack_i;
-- end if;
-- end if;
-- end process WRITE_AWREADY_P;
-- ---------------------------------------------------------------------------------
-- s_axi_reg_awready <= s_axi_reg_awready_i;
-------------------------------------------------------------------------------
-- Process READ_REQUEST_P to generate read request
-------------------------------------------------------------------------------
READ_REQUEST_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
read_reg_req <= '0';
elsif (s_axi_reg_arvalid = '1' and arready_i = '1') then
read_reg_req <= '1';
elsif (axi_lite_ip2bus_rdack_i = '1') then
read_reg_req <= '0';
end if;
end if;
end process READ_REQUEST_P;
-------------------------------------------------------------------------------
-- Process WRITE_REQUEST_P to generate Write request on the IPIC
-------------------------------------------------------------------------------
WRITE_REQUEST_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
write_reg_req <= '0';
elsif (s_axi_reg_awvalid = '1' and awready_i = '1') then
write_reg_req <= '1';
elsif (axi_lite_ip2bus_wrack_i = '1') then
write_reg_req <= '0';
end if;
end if;
end process WRITE_REQUEST_P;
-------------------------------------------------------------------------------
-- Process ADDR_GEN_P to generate bus2ip_addr for read/write
-------------------------------------------------------------------------------
PSRAM_PARITY_ADDR_REG_GEN : if (GLOBAL_PSRAM_FLASH_MEM = 1) generate
------------------------
-----
begin-- *
-----
ADDR_GEN_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
bus2ip_addr_lite_reg(4 downto 2) <= (others=>'0');
elsif (s_axi_reg_arvalid = '1' and arready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_araddr(4 downto 2);
elsif (s_axi_reg_awvalid = '1' and awready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_awaddr(4 downto 2);
end if;
end if;
end process ADDR_GEN_P;
end generate PSRAM_PARITY_ADDR_REG_GEN;
---------------------------------------
NO_PSRAM_PARITY_ADDR_REG_GEN : if (GLOBAL_PSRAM_FLASH_MEM = 0) generate
------------------------
-----
begin-- *
-----
ADDR_GEN_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
bus2ip_addr_lite_reg(4 downto 2) <= (others=>'0');
elsif (s_axi_reg_arvalid = '1' and arready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_araddr(4 downto 2);
elsif (s_axi_reg_awvalid = '1' and awready_i = '1') then
bus2ip_addr_lite_reg(4 downto 2) <= s_axi_reg_awaddr(4 downto 2);
end if;
end if;
end process ADDR_GEN_P;
end generate NO_PSRAM_PARITY_ADDR_REG_GEN;
---------------------------------------
-- -----------------------------------------------------------------------
-- Process AXI_READ_OUTPUT_P to generate Write request on the IPIC
-- -----------------------------------------------------------------------
AXI_READ_OUTPUT_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
s_axi_reg_rdata <= (others =>'0');
elsif (axi_lite_ip2bus_rdack_i = '1') then
s_axi_reg_rdata <= axi_lite_ip2bus_data_i;
elsif(rvalid='0')then
s_axi_reg_rdata <= (others =>'0');
end if;
end if;
end process AXI_READ_OUTPUT_P;
-- -----------------------------------------------------------------------
-- Process READ_RVALID_P to generate Read valid
-- -----------------------------------------------------------------------
READ_RVALID_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
s_axi_reg_rresp_reg <= "00";
if (s_axi_aresetn=RST_ACTIVE) then
rvalid <= '0';
elsif (axi_lite_ip2bus_rdack_i = '1') then
rvalid <= '1';
elsif (s_axi_reg_rready='1') then
rvalid <= '0';
end if;
end if;
end process READ_RVALID_P;
-- -----------------------------------------------------------------------
-- Process WRITE_BVALID_P to generate Write valid
-- -----------------------------------------------------------------------
WRITE_BVALID_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
s_axi_reg_bresp_reg <= "00";
if (s_axi_aresetn=RST_ACTIVE) then
s_axi_reg_bvalid_i <= '0';
--elsif (axi_lite_ip2bus_wrack_i = '1') then
-- s_axi_reg_bvalid <= '1';
--elsif (s_axi_reg_bready='1') then
-- s_axi_reg_bvalid <= '0';
--elsif(s_axi_reg_bready='1')then
--else
--s_axi_reg_bvalid <= axi_lite_ip2bus_wrack_i;
elsif ((axi_lite_ip2bus_wrack_i and (not axi_lite_ip2bus_wrack_d1)) = '1') then
s_axi_reg_bvalid_i <= '1';
elsif (s_axi_reg_bready = '0') and (s_axi_reg_bvalid_i = '1') then
s_axi_reg_bvalid_i <= '1';
elsif (s_axi_reg_bready = '1') and (s_axi_reg_bvalid_i = '1') then
s_axi_reg_bvalid_i <= '0';
end if;
end if;
end process WRITE_BVALID_P;
LOCK_BVALID_P: process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if (s_axi_aresetn=RST_ACTIVE) then
axi_lite_ip2bus_wrack_d1 <= '0';
else -- if (axi_lite_ip2bus_wrack_i = '1') then
axi_lite_ip2bus_wrack_d1 <= axi_lite_ip2bus_wrack_i;
end if;
end if;
end process LOCK_BVALID_P;
---------------------------------------------------------------------------------
s_axi_reg_bvalid <= s_axi_reg_bvalid_i;
-----------------------------------------------------------------------------
axi_lite_ip2bus_data_i <= axi_lite_ip2bus_data1 or
axi_lite_ip2bus_data2;
axi_lite_ip2bus_rdack_i <= axi_lite_ip2bus_rdack1 or
axi_lite_ip2bus_rdack2;
axi_lite_ip2bus_wrack_i <= axi_lite_ip2bus_wrack1 or
axi_lite_ip2bus_wrack2;
-----------------------------------------------------------------------------
-- PEAR_X_RD, Byte Parity Register Read Process
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
NO_PARITY_ENABLED_REG_GEN : if (MEM_PARITY_ARRAY(0) = 0 and -- if all mentioned meories are not having
MEM_PARITY_ARRAY(1) = 0 and -- parity included, then there wont be any
MEM_PARITY_ARRAY(2) = 0 and -- local registers
MEM_PARITY_ARRAY(3) = 0) generate
-----
begin
------
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= '0';
axi_lite_ip2bus_wrack1 <= '0';
end generate NO_PARITY_ENABLED_REG_GEN;
---------------------------------------
-- PEAR_X_RD : If any of the memories are having parity enabled then local register may be
-- needed. 1-odd parity, 2-even parity
--------------
PARITY_ENABLED_REG_GEN : if ( MEM_PARITY_ARRAY(0) /= 0 or -- if any of the memories are of
MEM_PARITY_ARRAY(1) /= 0 or -- having parity enables, then there
MEM_PARITY_ARRAY(2) /= 0 or -- is need of local registers
MEM_PARITY_ARRAY(3) /= 0
) generate
-----
begin
-----
-- PARITY_REG_DUMMY_WR_ACK_P : Parity registers are read only registers. write to these registers is not allowed or should come
-- out safely. Below logic generates ACK and write transactions are come out safely.
PARITY_REG_DUMMY_WR_ACK_P :process(s_axi_aclk)is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
axi_lite_ip2bus_wrack1 <= '0';
else--if(or_reduce(bus2ip_wrce_lite_cmb) = '1') then
axi_lite_ip2bus_wrack1 <= or_reduce(bus2ip_wrce_lite_cmb); -- '1';
end if;
end if;
end process PARITY_REG_DUMMY_WR_ACK_P;
----------------------------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_4_GEN: if C_NUM_BANKS_MEM = 4 generate
------------------
begin
-----
FOUR_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0),
PEAR_REG(1),
PEAR_REG(2),
PEAR_REG(3)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0); -- 9/14/2013
--(((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0);--(3 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;
-- defaults
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
case internal_bus2ip_rdack(7 downto 0) is -- (3 downto 0) is
--when "0001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
--when "0010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
--when "0100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
--when "1000" => axi_lite_ip2bus_data1 <= PEAR_REG(3);
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
when "00000010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
when "00000100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
when "00001000" => axi_lite_ip2bus_data1 <= PEAR_REG(3);
-- hole returns data 0
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
-- coverage off
when others => axi_lite_ip2bus_data1 <= (others=> '0');
-- coverage on
end case;
end process FOUR_BANKS_PARITY_REG_RD_P;
----------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
--err_parity_bits := ip2bus_errack & parity_error_MEM;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
when "011" => PEAR_REG(1) <= parity_error_adrss;
when "101" => PEAR_REG(2) <= parity_error_adrss;
when "111" => PEAR_REG(3) <= parity_error_adrss;
-- coverage off
when others => NULL;
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
PEAR_REG(1) <= PEAR_REG(1);
PEAR_REG(2) <= PEAR_REG(2);
PEAR_REG(3) <= PEAR_REG(3);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_4_GEN;
------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_3_GEN: if C_NUM_BANKS_MEM = 3 generate
------------------
begin
-----
THREE_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0),
PEAR_REG(1),
PEAR_REG(2)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0);--9/14/2013
--(((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0);--(3 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;
-- defaults
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
-- axi_lite_ip2bus_data1 <= (others => '0');
case internal_bus2ip_rdack(7 downto 0) is -- (2 downto 0) is
--when "001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
--when "010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
--when "100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
---- coverage off
--when others => null;
---- coverage on
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
when "00000010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
when "00000100" => axi_lite_ip2bus_data1 <= PEAR_REG(2);
-- hole returns data 0
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage off
when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
end case;
end process THREE_BANKS_PARITY_REG_RD_P;
----------------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i ) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
when "011" => PEAR_REG(1) <= parity_error_adrss;
when "101" => PEAR_REG(2) <= parity_error_adrss;
-- coverage off
when others => null; -- axi_lite_ip2bus_data1 <= (others => '0');
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
PEAR_REG(1) <= PEAR_REG(1);
PEAR_REG(2) <= PEAR_REG(2);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_3_GEN;
------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_2_GEN: if C_NUM_BANKS_MEM = 2 generate
------------------
begin
-----
TWO_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0),
PEAR_REG(1)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0); -- 9/14/2013
--(((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0);--(3 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;
-- defaults
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
case internal_bus2ip_rdack(7 downto 0) is -- (1 downto 0) is
--when "01" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
--when "10" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
---- coverage off
--when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
when "00000010" => axi_lite_ip2bus_data1 <= PEAR_REG(1);
-- hole returns data 0
when "00000100" => axi_lite_ip2bus_data1 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage off
when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
end case;
end process TWO_BANKS_PARITY_REG_RD_P;
----------------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
when "011" => PEAR_REG(1) <= parity_error_adrss;
-- coverage off
when others => NULL;
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
PEAR_REG(1) <= PEAR_REG(1);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_2_GEN;
------------------------------------------------------
------------------------------------------------------
PERR_NUM_MEM_1_GEN: if C_NUM_BANKS_MEM = 1 generate
------------------
begin
-----
ONE_BANKS_PARITY_REG_RD_P : process (bus2ip_rdce_lite_cmb,
PEAR_REG(0)
) is
variable internal_bus2ip_rdack : std_logic_vector(7 downto 0);
-----
begin
-----
internal_bus2ip_rdack := bus2ip_rdce_lite_cmb;-- or_reduce(bus2ip_rdce_lite_cmb);
-- defaults
axi_lite_ip2bus_data1 <= (others => '0');
axi_lite_ip2bus_rdack1 <= or_reduce(bus2ip_rdce_lite_cmb);
case internal_bus2ip_rdack is
--when '1' => axi_lite_ip2bus_data1 <= PEAR_REG(0);
---- coverage off
--when others => axi_lite_ip2bus_data1 <= (others=> '0'); -- null;
---- coverage on
when "00000001" => axi_lite_ip2bus_data1 <= PEAR_REG(0);
-- hole returns data 0
when "00000010" => axi_lite_ip2bus_data1 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data1 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data1 <= (others => '0');
when "00100000" => axi_lite_ip2bus_data1 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data1 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage off
when others => axi_lite_ip2bus_data1 <= (others => '0');
---- coverage on
end case;
end process ONE_BANKS_PARITY_REG_RD_P;
----------------------------------------
PARITY_ERR_REG_STORE_P: process (s_axi_aclk) is
-----------------------
--variable err_parity_bits : std_logic_vector(2 downto 0);
-----
begin
-----
--err_parity_bits := parity_error_MEM & Parity_err_i;
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PEAR_REG (i) <= (others => '0');
end loop;
else
if (ip2bus_errack = '1') then
case err_parity_bits is -- (parity_error_MEM & Parity_err_i) is
when "001" => PEAR_REG(0) <= parity_error_adrss;
-- coverage off
when others => NULL;
-- coverage on
end case;
else
PEAR_REG(0) <= PEAR_REG(0);
end if;
end if;
end if;
end process PARITY_ERR_REG_STORE_P;
end generate PERR_NUM_MEM_1_GEN;
------------------------------------------------------
end generate PARITY_ENABLED_REG_GEN;
------------------------------------
-----------------------------------------------------------------------------
-- PCR_X_RD, Byte Parity Register Read Process
-----------------------------------------------------------------------------
LINEAR_FLASH_CONFIG_REG_GEN: if (C_LINEAR_FLASH_SYNC_BURST = 1) generate
--------------------
begin
-----
PCR_FOUR_GEN: if C_NUM_BANKS_MEM = 4 generate
LFLASH_CONFIG_REG_RD_PROCESS_4 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= PCR_REG(3);
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_4;
end generate PCR_FOUR_GEN;
PCR_THREE_GEN: if C_NUM_BANKS_MEM = 3 generate
LFLASH_CONFIG_REG_RD_PROCESS_3 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_3;
end generate PCR_THREE_GEN;
PCR_TWO_GEN: if C_NUM_BANKS_MEM = 2 generate
LFLASH_CONFIG_REG_RD_PROCESS_2 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_2;
end generate PCR_TWO_GEN;
PCR_ONE_GEN: if C_NUM_BANKS_MEM = 1 generate
LFLASH_CONFIG_REG_RD_PROCESS_1 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process LFLASH_CONFIG_REG_RD_PROCESS_1;
end generate PCR_ONE_GEN;
-----------------------------------------
axi_lite_ip2bus_wrack2 <= or_reduce(bus2ip_wrce_lite_cmb);-- ((C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
-----------------------------------------
LFLASH_CONFIG_REG_WR_PROCESS : process (s_axi_aclk) is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PCR_REG (i) <= X"0000_0024";
end loop;
else
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if((bus2ip_wrce_lite_cmb(4+i)='1') and
(MEM_TYPE_ARRAY(i) = 2 or MEM_TYPE_ARRAY(i) = 5 )
)then
PCR_REG(i)(31 downto 30) <= s_axi_reg_wdata(31 downto 30);
PCR_REG(i)(6 downto 0) <= s_axi_reg_wdata(6 downto 0);
else
PCR_REG(i) <= PCR_REG(i);
end if;
end loop;
end if;
end if;
end process LFLASH_CONFIG_REG_WR_PROCESS;
----------------------------------------
MEM_WAIT_TEMP_1_GEN: if C_NUM_BANKS_MEM = 1 generate
------------------
begin
-------------------------------------------------------------------------------
-- Registers the input memory wait signal.
-------------------------------------------------------------------------------
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1')then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= sync_mode(0) and
(not Cre_reg_en(0))and
temp_bus2ip_cs(0); -- 4/2/2013
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
-----------------------------------------
end generate MEM_WAIT_TEMP_1_GEN;
MEM_WAIT_TEMP_2_GEN: if C_NUM_BANKS_MEM = 2 generate
------------------
begin
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1' or Mem_WAIT_io(1) = '1')then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk) is
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= (sync_mode(0) and (not Cre_reg_en(0)))
when (temp_bus2ip_cs(0) = '1')
else
(sync_mode(1) and (not Cre_reg_en(1)))
when (temp_bus2ip_cs(1) = '1')
else
'0';
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
----------------------------------------
end generate MEM_WAIT_TEMP_2_GEN;
MEM_WAIT_TEMP_3_GEN: if C_NUM_BANKS_MEM = 3 generate
------------------
begin
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1' or Mem_WAIT_io(1) = '1' or Mem_WAIT_io(2) = '1')then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
-----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
-----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= (sync_mode(0) and (not Cre_reg_en(0)))
when (temp_bus2ip_cs(0) = '1')
else
(sync_mode(1) and (not Cre_reg_en(1)))
when (temp_bus2ip_cs(1) = '1')
else
(sync_mode(2) and (not Cre_reg_en(2)))
when (temp_bus2ip_cs(2) = '1')
else
'0';
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
-----------------------------------------
end generate MEM_WAIT_TEMP_3_GEN;
MEM_WAIT_TEMP_4_GEN: if C_NUM_BANKS_MEM = 4 generate
------------------
begin
INPUT_MEM_WAIT_REGS_PROCESS: process(RdClk)is
begin
if RdClk'event and RdClk = '1' then
if(Mem_WAIT_reg_one_hot = '1') then
Mem_WAIT_reg_d1 <= '0';
elsif(Mem_WAIT_io(0) = '1' or
Mem_WAIT_io(1) = '1' or
Mem_WAIT_io(2) = '1' or
Mem_WAIT_io(3) = '1'
)then
Mem_WAIT_reg_d1 <= '1';
end if;
end if;
end process INPUT_MEM_WAIT_REGS_PROCESS;
----------------------------------------
DUAL_REG_MEM_WAIT_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
Mem_WAIT_reg_d2 <= Mem_WAIT_reg_d1;
end if;
end process DUAL_REG_MEM_WAIT_PROCESS;
----------------------------------------
Mem_WAIT_reg_one_hot <= Mem_WAIT_reg_d1 and (not Mem_WAIT_reg_d2);
Mem_WAIT_reg <= Mem_WAIT_reg_d1;
Linear_flash_brst_rd_flag <= (sync_mode(0) and (not Cre_reg_en(0)))
when (temp_bus2ip_cs(0) = '1')
else
(sync_mode(1) and (not Cre_reg_en(1)))
when (temp_bus2ip_cs(1) = '1')
else
(sync_mode(2) and (not Cre_reg_en(2)))
when (temp_bus2ip_cs(2) = '1')
else
(sync_mode(3) and (not Cre_reg_en(3)))
when (temp_bus2ip_cs(3) = '1')
else
'0';
Cre_reg_en_reduced <= or_reduce(Cre_reg_en);
----------------------------------------
end generate MEM_WAIT_TEMP_4_GEN;
Linear_flash_rd_data_ack <= Mem_WAIT_reg;
WR_PROGRAM_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
ADDR_select <= '0';
--ADDR_PROGRAM <= (others => '0');
elsif(S_AXI_MEM_WREADY1 = '1' and S_AXI_MEM_WVALID = '1') then
if(signed(S_AXI_MEM_WDATA(15 downto 0)) = signed(temp_prog_cmd_data)) then
ADDR_select <= '1';
-- ADDR_PROGRAM <= S_AXI_MEM_AWADDR;
end if;
elsif(S_AXI_MEM_BREADY = '1' and S_AXI_MEM_BVALID1 = '1') then
ADDR_select <= '0';
--ADDR_PROGRAM <= (others => '0');
end if;
end if;
end process WR_PROGRAM_PROCESS;
WR_PROGRAM_PROCESS_N : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
ADDR_PROGRAM_D <= (others => '0');
else
ADDR_PROGRAM_D <= ADDR_PROGRAM;
end if;
end if;
end process WR_PROGRAM_PROCESS_N;
ADDR_PROGRAM <= (others => '0') when (s_axi_aresetn = '0')
else S_AXI_MEM_AWADDR when ((S_AXI_MEM_WREADY1 = '1' and S_AXI_MEM_WVALID = '1') and (signed(S_AXI_MEM_WDATA(15 downto 0)) = signed(temp_prog_cmd_data)))
else (others => '0') when (S_AXI_MEM_BREADY = '1' and S_AXI_MEM_BVALID1 = '1')
else ADDR_PROGRAM_D;
-------------------------------
BURST_RD_ADDR_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
ADDR_SYNCH_BURST_RD_D <= (others => '0');
elsif(S_AXI_MEM_ARREADY1 = '1' and S_AXI_MEM_ARVALID = '1') then
ADDR_SYNCH_BURST_RD_D <= ADDR_SYNCH_BURST_RD;
end if;
--if (s_axi_aresetn = '0') then
-- ADDR_SYNCH_BURST_RD <= (others => '0');
--elsif(S_AXI_MEM_ARREADY1 = '1' and S_AXI_MEM_ARVALID = '1') then
-- ADDR_SYNCH_BURST_RD <= S_AXI_MEM_ARADDR;
--end if;
end if;
end process BURST_RD_ADDR_PROCESS;
ADDR_SYNCH_BURST_RD <= (others => '0') when (s_axi_aresetn = '0')
else S_AXI_MEM_ARADDR when (S_AXI_MEM_ARREADY1 = '1' and S_AXI_MEM_ARVALID = '1')
else ADDR_SYNCH_BURST_RD_D;
--CTRL_REG_ADDR(16 downto 1) <= CTRL_REG_DATA;
-- Linear_flash_rd_data_ack <= sync_data_select;
--Linear_flash_brst_rd_flag <= sync_mode and (not Cre_reg_en);
FLASH_SYNCH_CRE_WR_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
Cre_reg_en <= (others => '0');
sync_mode <= (others => '0');
else
Cre_reg_en <= (others => '0');
sync_mode <= (others => '0');
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if(bus2ip_ce_lite_cmb(4+i) = '1' ) then
sync_mode(i) <= ( PCR_REG(i)(30));
Cre_reg_en(i) <= PCR_REG(i)(31);
end if;
end loop;
end if;
end if;
end process FLASH_SYNCH_CRE_WR_PROCESS;
end generate LINEAR_FLASH_CONFIG_REG_GEN;
--------------------------------------------------------------------------------
NO_LFLASH_PSRAM_CONFIG_REG_GEN: if (GLOBAL_PSRAM_FLASH_MEM = 0) generate
--------------------
begin
-----
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= '0';
axi_lite_ip2bus_wrack2 <= '0'; -- 6/6/2013
psram_page_mode <= '1';-- DONT change this value
CRE_WR_PROCESS_G : process (s_axi_aclk) is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
Mem_CRE_int <= '0';
end if;
end process CRE_WR_PROCESS_G;
end generate NO_LFLASH_PSRAM_CONFIG_REG_GEN;
-------------------------------------
-- NO_PSRAM_CONFIG_REG_GEN : If any of the memories are defined with PSRAM, then there will
-- local register in the core.
----------------
PSRAM_CONFIG_REG_GEN: if (GLOBAL_PSRAM_MEM = 1) generate
--------------------
begin
-----
--SRAM_CONFIG_REG_RD_PROCESS : process (bus2ip_rdce_lite_cmb,
-- PCR_REG) is
--egin
--- defaults
--xi_lite_ip2bus_data2 <= (others => '0');
--xi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb); -- 9/14/2013 -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0));
--or i in C_NUM_BANKS_MEM-1 downto 0 loop
-- if( (bus2ip_rdce_lite_cmb(4+i)='1') and
-- (MEM_TYPE_ARRAY(i)=4 )
-- )then
-- axi_lite_ip2bus_data2 <= PCR_REG(i);
-- else -- 9/14/2013
-- axi_lite_ip2bus_data2 <= (others => '0');
-- end if;
--nd loop;
--nd process PSRAM_CONFIG_REG_RD_PROCESS;
PSRAM_ONE_GEN: if C_NUM_BANKS_MEM = 1 generate
PSRAM_CONFIG_REG_RD_PROCESS_1 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= (others => '0');
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_1;
end generate PSRAM_ONE_GEN;
PSRAM_TWO_GEN: if C_NUM_BANKS_MEM = 2 generate
PSRAM_CONFIG_REG_RD_PROCESS_2 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= (others => '0');
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_2;
end generate PSRAM_TWO_GEN;
PSRAM_THREE_GEN: if C_NUM_BANKS_MEM = 3 generate
PSRAM_CONFIG_REG_RD_PROCESS_3 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= (others => '0');
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_3;
end generate PSRAM_THREE_GEN;
PSRAM_FOUR_GEN: if C_NUM_BANKS_MEM = 4 generate
PSRAM_CONFIG_REG_RD_PROCESS_4 : process (bus2ip_rdce_lite_cmb,
PCR_REG
--MEM_TYPE_ARRAY
) is
variable j : integer := 0;
begin
-- defaults
axi_lite_ip2bus_data2 <= (others => '0');
axi_lite_ip2bus_rdack2 <= or_reduce(bus2ip_rdce_lite_cmb);-- ( ( (C_NUM_BANKS_MEM-1)+(4*C_LINEAR_FLASH_SYNC_BURST)) downto 0));
case bus2ip_rdce_lite_cmb is
when "00000001" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000010" => axi_lite_ip2bus_data2 <= (others => '0');
when "00000100" => axi_lite_ip2bus_data2 <= (others => '0');
when "00001000" => axi_lite_ip2bus_data2 <= (others => '0');
when "00010000" => axi_lite_ip2bus_data2 <= PCR_REG(0);
when "00100000" => axi_lite_ip2bus_data2 <= PCR_REG(1);
when "01000000" => axi_lite_ip2bus_data2 <= PCR_REG(2);
when "10000000" => axi_lite_ip2bus_data2 <= PCR_REG(3);
when others => axi_lite_ip2bus_data2 <= (others => '0');
end case;
end process PSRAM_CONFIG_REG_RD_PROCESS_4;
end generate PSRAM_FOUR_GEN;
axi_lite_ip2bus_wrack2 <= or_reduce(bus2ip_wrce_lite_cmb); -- 9/14/2013 -- (((C_NUM_BANKS_MEM-1)+(4*GLOBAL_PSRAM_MEM)) downto 0));
PSRAM_CONFIG_REG_WR_PROCESS : process (s_axi_aclk) is
begin
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
for i in C_NUM_BANKS_MEM-1 downto 0 loop
PCR_REG (i) <= X"0000_0024";
end loop;
else
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if((bus2ip_wrce_lite_cmb(4+i)='1') and
(MEM_TYPE_ARRAY(i) = 4 )
)then
--PCR_REG(i) <= s_axi_reg_wdata;
PCR_REG(i)(31 downto 30) <= s_axi_reg_wdata(31 downto 30);
PCR_REG(i)(6 downto 0) <= s_axi_reg_wdata(6 downto 0);
else
PCR_REG(i) <= PCR_REG(i);
end if;
end loop;
end if;
end if;
end process PSRAM_CONFIG_REG_WR_PROCESS;
----------------------------------------
CRE_WR_PROCESS : process (s_axi_aclk) is
begin
-----
if (s_axi_aclk'EVENT and s_axi_aclk = '1') then
if (s_axi_aresetn = '0') then
Mem_CRE_int <= '0';
psram_page_mode <= '1';
else
-- defaults
Mem_CRE_int <= '0';
psram_page_mode <= '0';
for i in C_NUM_BANKS_MEM-1 downto 0 loop
if (temp_bus2ip_cs(i) = '1' ) then
Mem_CRE_int <= PCR_REG(i)(6);-- (25);
psram_page_mode <= PCR_REG(i)(0); -- (31);
end if;
end loop;
end if;
end if;
end process CRE_WR_PROCESS;
---------------------------
end generate PSRAM_CONFIG_REG_GEN;
-------------------------
end generate REG_EN_GEN;
-------------------------------------------------------------------------------
AXI_EMC_NATIVE_INTERFACE_I: entity axi_emc_v3_0.axi_emc_native_interface
-- Generics to be set by user
generic map(
C_FAMILY => C_FAMILY ,
C_S_AXI_MEM_ADDR_WIDTH => C_S_AXI_MEM_ADDR_WIDTH ,
C_S_AXI_MEM_DATA_WIDTH => C_S_AXI_MEM_DATA_WIDTH ,
C_S_AXI_MEM_ID_WIDTH => C_S_AXI_MEM_ID_WIDTH ,
C_S_AXI_MEM0_BASEADDR => C_S_AXI_MEM0_BASEADDR ,
C_S_AXI_MEM0_HIGHADDR => C_S_AXI_MEM0_HIGHADDR ,
C_S_AXI_MEM1_BASEADDR => C_S_AXI_MEM1_BASEADDR ,
C_S_AXI_MEM1_HIGHADDR => C_S_AXI_MEM1_HIGHADDR ,
C_S_AXI_MEM2_BASEADDR => C_S_AXI_MEM2_BASEADDR ,
C_S_AXI_MEM2_HIGHADDR => C_S_AXI_MEM2_HIGHADDR ,
C_S_AXI_MEM3_BASEADDR => C_S_AXI_MEM3_BASEADDR ,
C_S_AXI_MEM3_HIGHADDR => C_S_AXI_MEM3_HIGHADDR ,
AXI_ARD_ADDR_RANGE_ARRAY => AXI_ARD_ADDR_RANGE_ARRAY,
AXI_ARD_NUM_CE_ARRAY => AXI_ARD_NUM_CE_ARRAY ,
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM
)
port map(
s_axi_aclk => s_axi_aclk ,
s_axi_aresetn => s_axi_aresetn ,
-- -- AXI Write Address Channel Signals
S_AXI_MEM_AWID => s_axi_mem_awid ,
S_AXI_MEM_AWADDR => s_axi_mem_awaddr ,
S_AXI_MEM_AWLEN => s_axi_mem_awlen ,
S_AXI_MEM_AWSIZE => s_axi_mem_awsize ,
S_AXI_MEM_AWBURST => s_axi_mem_awburst ,
S_AXI_MEM_AWLOCK => s_axi_mem_awlock ,
S_AXI_MEM_AWCACHE => s_axi_mem_awcache ,
S_AXI_MEM_AWPROT => s_axi_mem_awprot ,
S_AXI_MEM_AWVALID => s_axi_mem_awvalid ,
S_AXI_MEM_AWREADY => s_axi_mem_awready ,
-- -- AXI Write Channel Signals
S_AXI_MEM_WDATA => s_axi_mem_wdata ,
S_AXI_MEM_WSTRB => s_axi_mem_wstrb ,
S_AXI_MEM_WLAST => s_axi_mem_wlast ,
S_AXI_MEM_WVALID => s_axi_mem_wvalid ,
S_AXI_MEM_WREADY => s_axi_mem_wready1 ,
-- -- AXI Write Response Channel Signals
S_AXI_MEM_BID => s_axi_mem_bid ,
S_AXI_MEM_BRESP => s_axi_mem_bresp ,
S_AXI_MEM_BVALID => s_axi_mem_bvalid1 ,
S_AXI_MEM_BREADY => s_axi_mem_bready ,
-- -- AXI Read Address Channel Signals
S_AXI_MEM_ARID => s_axi_mem_arid ,
S_AXI_MEM_ARADDR => s_axi_mem_araddr ,
S_AXI_MEM_ARLEN => s_axi_mem_arlen ,
S_AXI_MEM_ARSIZE => s_axi_mem_arsize ,
S_AXI_MEM_ARBURST => s_axi_mem_arburst ,
S_AXI_MEM_ARLOCK => s_axi_mem_arlock ,
S_AXI_MEM_ARCACHE => s_axi_mem_arcache ,
S_AXI_MEM_ARPROT => s_axi_mem_arprot ,
S_AXI_MEM_ARVALID => s_axi_mem_arvalid ,
S_AXI_MEM_ARREADY => s_axi_mem_arready1 ,
-- -- AXI Read Data Channel Signals
S_AXI_MEM_RID => s_axi_mem_rid ,
S_AXI_MEM_RDATA => s_axi_mem_rdata ,
S_AXI_MEM_RRESP => s_axi_mem_rresp ,
S_AXI_MEM_RLAST => s_axi_mem_rlast ,
S_AXI_MEM_RVALID => s_axi_mem_rvalid ,
S_AXI_MEM_RREADY => s_axi_mem_rready ,
-- IP Interconnect (IPIC) port signals ------------------------------------
-- Controls to the IP/IPIF modules
-- IP Interconnect (IPIC) port signals
IP2Bus_Data => temp_ip2bus_data ,
IP2Bus_WrAck => IP2Bus_WrAck ,
IP2Bus_RdAck => IP2Bus_RdAck ,
IP2Bus_AddrAck => IP2Bus_AddrAck ,
IP2Bus_Error => ip2bus_errack ,
Bus2IP_Addr => bus2ip_addr_temp ,
Bus2IP_Data => temp_bus2ip_data ,
Bus2IP_RNW => Bus2IP_RNW ,
Bus2IP_BE => temp_bus2ip_be ,
Bus2IP_Burst => Bus2IP_Burst ,
Bus2IP_BurstLength => bus2ip_burstlength ,
Bus2IP_RdReq => Bus2IP_RdReq_emc ,
Bus2IP_WrReq => Bus2IP_WrReq_emc ,
Bus2IP_CS => temp_bus2ip_cs ,
Bus2IP_RdCE => bus2ip_rdce ,
Bus2IP_WrCE => bus2ip_wrce ,
Type_of_xfer => Type_of_xfer ,
Cre_reg_en => Cre_reg_en_reduced , -- newly added
synch_mem => synch_mem ,
last_addr1 => last_addr1 ,
pr_idle => pr_idle ,
axi_trans_size_reg => axi_trans_size_reg_int
);
---------------------------------------------------------------------------
-- Miscellaneous assignments to match EMC controller to IPIC
---------------------------------------------------------------------------
or_reduced_wrce <= or_reduce(bus2ip_wrce);
------------------------------------------
RD_CE_PIPE_PROCESS : process(s_axi_aclk)is
begin
if(s_axi_aclk'EVENT and s_axi_aclk = '1') then
or_reduced_rdce_d1 <= or_reduce(bus2ip_rdce);
bus2ip_wrreq_reg <= or_reduced_wrce;
end if;
end process RD_CE_PIPE_PROCESS;
------------------------------------------
original_wrce <= or_reduced_wrce;
bus2ip_wrreq_i <= Bus2IP_WrReq_emc;--or_reduce(bus2ip_wrce);
--bus2ip_rdreq_i <= or_reduce(bus2ip_rdce); -- Bus2IP_RdReq_emc;--or_reduce(bus2ip_rdce);
bus2ip_rdreq_i <= Bus2IP_RdReq_emc when synch_mem = '1' else or_reduce(bus2ip_rdce);--or_reduce(bus2ip_rdce);
bus2ip_cs_i <= or_reduce(temp_bus2ip_cs);
---------------------------------------------------------------------------
-- AXI EMC is little endian and EMC COMMON is still big endian, to make
-- this interface work normally, we need to swap the Write and read data
-- comming from and going to slave burst interface
---------------------------------------------------------------------------
ENDIAN_BANKS_0 : if (C_NUM_BANKS_MEM = 1) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
end generate ENDIAN_BANKS_0;
ENDIAN_BANKS_1 : if (C_NUM_BANKS_MEM = 2) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
bus2ip_cs(1)<= temp_bus2ip_cs(1);
end generate ENDIAN_BANKS_1;
ENDIAN_BANKS_2 : if (C_NUM_BANKS_MEM = 3) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
bus2ip_cs(1)<= temp_bus2ip_cs(1);
bus2ip_cs(2)<= temp_bus2ip_cs(2);
end generate ENDIAN_BANKS_2;
ENDIAN_BANKS_3 : if (C_NUM_BANKS_MEM = 4) generate
bus2ip_cs(0)<= temp_bus2ip_cs(0);
bus2ip_cs(1)<= temp_bus2ip_cs(1);
bus2ip_cs(2)<= temp_bus2ip_cs(2);
bus2ip_cs(3)<= temp_bus2ip_cs(3);
end generate ENDIAN_BANKS_3;
ENDIAN_CONVERSION_32 : if (C_S_AXI_MEM_DATA_WIDTH = 32) generate
bus2ip_data(0 to 7) <= temp_bus2ip_data(7 downto 0);
bus2ip_data(8 to 15) <= temp_bus2ip_data(15 downto 8);
bus2ip_data(16 to 23) <= temp_bus2ip_data(23 downto 16);
bus2ip_data(24 to 31) <= temp_bus2ip_data(31 downto 24);
temp_ip2bus_data(7 downto 0) <= ip2bus_data(0 to 7) ;
temp_ip2bus_data(15 downto 8) <= ip2bus_data(8 to 15) ;
temp_ip2bus_data(23 downto 16) <= ip2bus_data(16 to 23);
temp_ip2bus_data(31 downto 24) <= ip2bus_data(24 to 31);
bus2ip_be(0) <= temp_bus2ip_be(0);
bus2ip_be(1) <= temp_bus2ip_be(1);
bus2ip_be(2) <= temp_bus2ip_be(2);
bus2ip_be(3) <= temp_bus2ip_be(3);
-- the below logic is to generate the lower 2 bits of address for 32
-- bit data width
temp_single_0 <= or_reduce(temp_bus2ip_be(1 downto 0));
temp_single_1 <= or_reduce(temp_bus2ip_be(3 downto 0));
bus2ip_addr_reg(2) <= ((not temp_bus2ip_be(0)) and
(temp_bus2ip_be(1)
OR
((NOT temp_bus2ip_be(2)) and
temp_bus2ip_be(3) and
(NOT temp_single_0)
)
)
) and Type_of_xfer;
bus2ip_addr_reg(1) <= (((not temp_bus2ip_be(0)) and (not
temp_bus2ip_be(1))) and (temp_bus2ip_be(2) OR
temp_bus2ip_be(3)))and Type_of_xfer;
bus2ip_addr <= (bus2ip_addr_temp (0 to 29) & bus2ip_addr_reg (1 to 2))
when (Cre_reg_en_reduced = '0')
else
bus2ip_addr_temp ;
bus2ip_addr_reg(0) <= '0';
end generate ENDIAN_CONVERSION_32;
ENDIAN_CONVERSION_64 : if (C_S_AXI_MEM_DATA_WIDTH = 64) generate
bus2ip_data(0 to 7) <= temp_bus2ip_data(7 downto 0);
bus2ip_data(8 to 15) <= temp_bus2ip_data(15 downto 8);
bus2ip_data(16 to 23) <= temp_bus2ip_data(23 downto 16);
bus2ip_data(24 to 31) <= temp_bus2ip_data(31 downto 24);
bus2ip_data(32 to 39) <= temp_bus2ip_data(39 downto 32);
bus2ip_data(40 to 47) <= temp_bus2ip_data(47 downto 40);
bus2ip_data(48 to 55) <= temp_bus2ip_data(55 downto 48);
bus2ip_data(56 to 63) <= temp_bus2ip_data(63 downto 56);
temp_ip2bus_data(7 downto 0) <= ip2bus_data(0 to 7) ;
temp_ip2bus_data(15 downto 8) <= ip2bus_data(8 to 15) ;
temp_ip2bus_data(23 downto 16) <= ip2bus_data(16 to 23);
temp_ip2bus_data(31 downto 24) <= ip2bus_data(24 to 31);
temp_ip2bus_data(39 downto 32) <= ip2bus_data(32 to 39);
temp_ip2bus_data(47 downto 40) <= ip2bus_data(40 to 47);
temp_ip2bus_data(55 downto 48) <= ip2bus_data(48 to 55);
temp_ip2bus_data(63 downto 56) <= ip2bus_data(56 to 63);
bus2ip_be(0) <= temp_bus2ip_be(0);
bus2ip_be(1) <= temp_bus2ip_be(1);
bus2ip_be(2) <= temp_bus2ip_be(2);
bus2ip_be(3) <= temp_bus2ip_be(3);
bus2ip_be(4) <= temp_bus2ip_be(4);
bus2ip_be(5) <= temp_bus2ip_be(5);
bus2ip_be(6) <= temp_bus2ip_be(6);
bus2ip_be(7) <= temp_bus2ip_be(7);
-- the below logic is to generate the lower 3 bits of address for 64 bit
-- data width
temp_single_0 <= or_reduce(temp_bus2ip_be(1 downto 0));
temp_single_1 <= or_reduce(temp_bus2ip_be(3 downto 0));
temp_single_2 <= or_reduce(temp_bus2ip_be(5 downto 0));
bus2ip_addr_reg(2) <=((not temp_bus2ip_be(0)) and (temp_bus2ip_be(1)
OR ((NOT temp_bus2ip_be(2)) and
temp_bus2ip_be(3) and
(NOT temp_single_0))
OR ((NOT temp_bus2ip_be(4)) and
temp_bus2ip_be(5) and
(NOT temp_single_1))
OR ((NOT temp_bus2ip_be(6)) and
temp_bus2ip_be(7) and
(NOT temp_single_2)))) and Type_of_xfer;
bus2ip_addr_reg(1) <=((((not temp_bus2ip_be(0)) and
(not temp_bus2ip_be(1))) and (temp_bus2ip_be(2)
OR temp_bus2ip_be(3))) OR
(((not temp_bus2ip_be(4)) and
(not temp_bus2ip_be(5))) and (temp_bus2ip_be(6)
OR temp_bus2ip_be(7)) and (NOT temp_single_0)))
and Type_of_xfer;
bus2ip_addr_reg(0) <= (not (temp_bus2ip_be(0) or temp_bus2ip_be(1) or
temp_bus2ip_be(2) or temp_bus2ip_be(3)))
and Type_of_xfer;
bus2ip_addr <= bus2ip_addr_temp (0 to 28) &
bus2ip_addr_reg (0 to 2)
when bus2ip_cs_i = '1' else
(others => '0');
end generate ENDIAN_CONVERSION_64;
-----------------------------------------------------------------------------
--RESET_TOGGLE: convert active low to active hig reset to rest of the core.
-----------------------------------------------------------------------------
RESET_TOGGLE: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(s_axi_aresetn);
end if;
end process RESET_TOGGLE;
EMC_CTRL_I: entity emc_common_v3_0.emc
generic map(
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_IPIF_DWIDTH => C_S_AXI_MEM_DATA_WIDTH,
C_IPIF_AWIDTH => C_S_AXI_MEM_ADDR_WIDTH,
C_MEM0_BASEADDR => C_S_AXI_MEM0_BASEADDR,
C_MEM0_HIGHADDR => C_S_AXI_MEM0_HIGHADDR,
C_MEM1_BASEADDR => C_S_AXI_MEM1_BASEADDR,
C_MEM1_HIGHADDR => C_S_AXI_MEM1_HIGHADDR,
C_MEM2_BASEADDR => C_S_AXI_MEM2_BASEADDR,
C_MEM2_HIGHADDR => C_S_AXI_MEM2_HIGHADDR,
C_MEM3_BASEADDR => C_S_AXI_MEM3_BASEADDR,
C_MEM3_HIGHADDR => C_S_AXI_MEM3_HIGHADDR,
C_PAGEMODE_FLASH_0 => C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1 => C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2 => C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3 => C_PAGEMODE_FLASH_3,
C_INCLUDE_NEGEDGE_IOREGS => C_INCLUDE_NEGEDGE_IOREGS,
C_MEM0_WIDTH => C_MEM0_WIDTH,
C_MEM1_WIDTH => C_MEM1_WIDTH,
C_MEM2_WIDTH => C_MEM2_WIDTH,
C_MEM3_WIDTH => C_MEM3_WIDTH,
C_MAX_MEM_WIDTH => C_MAX_MEM_WIDTH,
C_MEM0_TYPE => C_MEM0_TYPE,
C_MEM1_TYPE => C_MEM1_TYPE,
C_MEM2_TYPE => C_MEM2_TYPE,
C_MEM3_TYPE => C_MEM3_TYPE,
C_PARITY_TYPE_0 => C_PARITY_TYPE_MEM_0,
C_PARITY_TYPE_1 => C_PARITY_TYPE_MEM_1,
C_PARITY_TYPE_2 => C_PARITY_TYPE_MEM_2,
C_PARITY_TYPE_3 => C_PARITY_TYPE_MEM_3,
C_INCLUDE_DATAWIDTH_MATCHING_0 => C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3 => C_INCLUDE_DATAWIDTH_MATCHING_3,
-- Memory read and write access times for all memory banks
C_BUS_CLOCK_PERIOD_PS => C_AXI_CLK_PERIOD_PS,
C_SYNCH_MEM_0 => C_SYNCH_MEM_0,
C_SYNCH_PIPEDELAY_0 => C_SYNCH_PIPEDELAY_0,
C_TCEDV_PS_MEM_0 => C_TCEDV_PS_MEM_0,
C_TAVDV_PS_MEM_0 => C_TAVDV_PS_MEM_0,
C_TPACC_PS_FLASH_0 => C_TPACC_PS_FLASH_0,
C_THZCE_PS_MEM_0 => C_THZCE_PS_MEM_0,
C_THZOE_PS_MEM_0 => C_THZOE_PS_MEM_0,
C_TWC_PS_MEM_0 => C_TWC_PS_MEM_0,
C_TWP_PS_MEM_0 => C_TWP_PS_MEM_0,
C_TWPH_PS_MEM_0 => C_TWPH_PS_MEM_0,
C_TLZWE_PS_MEM_0 => C_TLZWE_PS_MEM_0,
C_WR_REC_TIME_MEM_0 => C_WR_REC_TIME_MEM_0,
C_SYNCH_MEM_1 => C_SYNCH_MEM_1,
C_SYNCH_PIPEDELAY_1 => C_SYNCH_PIPEDELAY_1,
C_TCEDV_PS_MEM_1 => C_TCEDV_PS_MEM_1,
C_TAVDV_PS_MEM_1 => C_TAVDV_PS_MEM_1,
C_TPACC_PS_FLASH_1 => C_TPACC_PS_FLASH_1,
C_THZCE_PS_MEM_1 => C_THZCE_PS_MEM_1,
C_THZOE_PS_MEM_1 => C_THZOE_PS_MEM_1,
C_TWC_PS_MEM_1 => C_TWC_PS_MEM_1,
C_TWP_PS_MEM_1 => C_TWP_PS_MEM_1,
C_TWPH_PS_MEM_1 => C_TWPH_PS_MEM_1,
C_TLZWE_PS_MEM_1 => C_TLZWE_PS_MEM_1,
C_WR_REC_TIME_MEM_1 => C_WR_REC_TIME_MEM_1,
C_SYNCH_MEM_2 => C_SYNCH_MEM_2,
C_SYNCH_PIPEDELAY_2 => C_SYNCH_PIPEDELAY_2,
C_TCEDV_PS_MEM_2 => C_TCEDV_PS_MEM_2,
C_TAVDV_PS_MEM_2 => C_TAVDV_PS_MEM_2,
C_TPACC_PS_FLASH_2 => C_TPACC_PS_FLASH_2,
C_THZCE_PS_MEM_2 => C_THZCE_PS_MEM_2,
C_THZOE_PS_MEM_2 => C_THZOE_PS_MEM_2,
C_TWC_PS_MEM_2 => C_TWC_PS_MEM_2,
C_TWP_PS_MEM_2 => C_TWP_PS_MEM_2,
C_TWPH_PS_MEM_2 => C_TWPH_PS_MEM_2,
C_TLZWE_PS_MEM_2 => C_TLZWE_PS_MEM_2,
C_WR_REC_TIME_MEM_2 => C_WR_REC_TIME_MEM_2,
C_SYNCH_MEM_3 => C_SYNCH_MEM_3,
C_SYNCH_PIPEDELAY_3 => C_SYNCH_PIPEDELAY_3,
C_TCEDV_PS_MEM_3 => C_TCEDV_PS_MEM_3,
C_TAVDV_PS_MEM_3 => C_TAVDV_PS_MEM_3,
C_TPACC_PS_FLASH_3 => C_TPACC_PS_FLASH_3,
C_THZCE_PS_MEM_3 => C_THZCE_PS_MEM_3,
C_THZOE_PS_MEM_3 => C_THZOE_PS_MEM_3,
C_TWC_PS_MEM_3 => C_TWC_PS_MEM_3,
C_TWP_PS_MEM_3 => C_TWP_PS_MEM_3,
C_TWPH_PS_MEM_3 => C_TWPH_PS_MEM_3,
C_TLZWE_PS_MEM_3 => C_TLZWE_PS_MEM_3,
C_WR_REC_TIME_MEM_3 => C_WR_REC_TIME_MEM_3
)
port map (
Bus2IP_Clk => s_axi_aclk ,
RdClk => RdClk ,
Bus2IP_Reset => Bus2IP_Reset ,
-- Bus and IPIC Interface signals
Bus2IP_Addr => bus2ip_addr ,
Bus2IP_BE => bus2ip_be ,
Bus2IP_Data => bus2ip_data ,
Bus2IP_RNW => bus2ip_rnw ,
Bus2IP_Burst => bus2ip_burst ,
Bus2IP_WrReq => bus2ip_wrreq_i ,
Bus2IP_RdReq => bus2ip_rdreq_i ,
Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag ,
Linear_flash_rd_data_ack => Linear_flash_rd_data_ack ,
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc ,
Bus2IP_WrReq_emc => Bus2IP_WrReq_emc ,
Bus2IP_Mem_CS => bus2ip_cs ,
Bus2IP_BurstLength => bus2ip_burstlength ,
IP2Bus_Data => ip2bus_data ,
IP2Bus_errAck => ip2bus_errack ,
IP2Bus_retry => open ,
IP2Bus_toutSup => open ,
IP2Bus_RdAck => ip2bus_rdack ,
IP2Bus_WrAck => ip2bus_wrack ,
IP2Bus_AddrAck => ip2bus_addrack ,
parity_error_adrss => parity_error_adrss , -- 32 bit
parity_error_mem => parity_error_MEM , -- 2 bit
Type_of_xfer => Type_of_xfer ,
psram_page_mode => psram_page_mode ,
original_wrce => original_wrce ,
-- Memory signals
Mem_A => mem_a_i ,
Mem_DQ_I => mem_dq_i_i ,
Mem_DQ_O => mem_dq_o_i ,
Mem_DQ_T => mem_dq_t_i ,
Mem_DQ_PRTY_I => mem_dq_parity_i_i ,
Mem_DQ_PRTY_O => mem_dq_parity_o_i ,
Mem_DQ_PRTY_T => mem_dq_parity_t_i ,
Mem_CEN => mem_cen_i ,
Mem_OEN => mem_oen_i ,
Mem_WEN => mem_wen_i ,
Mem_QWEN => mem_qwen_i ,
Mem_BEN => mem_ben_i ,
Mem_RPN => Mem_RPN ,
Mem_CE => mem_ce_i ,
Mem_ADV_LDN => mem_adv_ldn_i ,
Mem_LBON => Mem_LBON ,
Mem_CKEN => mem_cken_i ,
Mem_RNW => Mem_RNW ,
Cre_reg_en => Cre_reg_en_reduced ,
MEM_WAIT => Mem_WAIT_reg ,
synch_mem12 => synch_mem ,
last_addr1 => last_addr1 ,
pr_idle => pr_idle ,
axi_trans_size_reg => axi_trans_size_reg_int,
axi_arsize => axi_arsize,
axi_wvalid => S_AXI_MEM_WVALID,
axi_wlast => S_AXI_MEM_WLAST,
Parity_err => Parity_err_i
);
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/xemac.vhd
|
4
|
63822
|
-------------------------------------------------------------------------------
-- xemac.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : xemac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC with
-- IPIF elements included.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/21/2010
-- ^^^^^^
-- Updated local register decoding logic to fix the issue related with read.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_FAMILY -- Target device family (spartan3e, spartan3a,
-- spartan3an, spartan3af, virtex4 or virtex6)
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 only
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- C_TX_PING_PONG -- 1 = ping-pong memory used for transmit buffer
-- C_RX_PING_PONG -- 1 = ping-pong memory used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface, 0 = No MDIO Interface
-- NODE_MAC -- = Default MAC address of the core
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- System signals
-- Clk -- System clock
-- Rst -- System Reset
-- IP2INTC_Irpt -- System Interrupt
-- IPIC signals
-- IP2Bus_Data -- IP to Bus data
-- IP2Bus_Error -- IP to Bus error
-- Bus2IP_Addr -- Bus to IP address
-- Bus2IP_Data -- Bus to IP data
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- Bus2IP_Burst -- Bus to IP burst
-- Ethernet
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Loopback -- Internal Loopback enable
-- PHY_MDIO_I -- Ethernet PHY MDIO data input
-- PHY_MDIO_O -- Ethernet PHY MDIO data output
-- PHY_MDIO_T -- Ethernet PHY MDIO data 3-state control
-- PHY_MDC -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity xemac is
generic (
C_FAMILY : string := "virtex6";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_DUPLEX : integer := 1; -- 1 = full duplex, 0 = half duplex
C_RX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- receive buffer
C_TX_PING_PONG : integer := 0; -- 1 = ping-pong memory used for
-- transmit buffer
C_INCLUDE_MDIO : integer := 1; -- 1 = Include MDIO interface
-- 0 = No MDIO interface
NODE_MAC : bit_vector := x"00005e00FACE"
-- power up defaul MAC address
);
port (
Clk : in std_logic;
Rst : in std_logic;
IP2INTC_Irpt : out std_logic;
-- Controls to the IP/IPIF modules
IP2Bus_Data : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0 );
IP2Bus_Error : out std_logic;
Bus2IP_Addr : in std_logic_vector(12 downto 0);
Bus2IP_Data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
Bus2IP_BE : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Burst : in std_logic;
-- Ethernet Interface
PHY_tx_clk : in std_logic;
PHY_rx_clk : in std_logic;
PHY_crs : in std_logic;
PHY_dv : in std_logic;
PHY_rx_data : in std_logic_vector (3 downto 0);
PHY_col : in std_logic;
PHY_rx_er : in std_logic;
PHY_tx_en : out std_logic;
PHY_tx_data : out std_logic_vector (3 downto 0);
Loopback : out std_logic;
-- MDIO Interface
PHY_MDIO_I : in std_logic;
PHY_MDIO_O : out std_logic;
PHY_MDIO_T : out std_logic;
PHY_MDC : out std_logic
);
end xemac;
architecture imp of xemac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant MDIO_CNT : integer := ((200000/C_S_AXI_ACLK_PERIOD_PS)+1);
constant IP2BUS_DATA_ZERO : std_logic_vector(0 to 31) := X"00000000";
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal phy_rx_data_i : std_logic_vector (3 downto 0);
signal phy_tx_data_i : std_logic_vector (3 downto 0);
signal tx_DPM_ce : std_logic;
signal tx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal tx_DPM_adr : std_logic_vector (11 downto 0);
signal tx_DPM_wr_data : std_logic_vector (3 downto 0);
signal tx_DPM_rd_data : std_logic_vector (3 downto 0);
signal tx_ping_rd_data : std_logic_vector (3 downto 0);
signal tx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal tx_DPM_wr_rd_n : std_logic;
signal rx_DPM_ce : std_logic;
signal rx_DPM_ce_i : std_logic; -- added 03-03-05 MSH
signal rx_DPM_adr : std_logic_vector (11 downto 0);
signal rx_DPM_wr_data : std_logic_vector (3 downto 0);
signal rx_DPM_rd_data : std_logic_vector (3 downto 0);
signal rx_ping_rd_data : std_logic_vector (3 downto 0);
signal rx_pong_rd_data : std_logic_vector (3 downto 0) := (others => '0');
signal rx_DPM_wr_rd_n : std_logic;
signal IPIF_tx_Ping_CE : std_logic;
signal IPIF_tx_Pong_CE : std_logic := '0';
signal IPIF_rx_Ping_CE : std_logic;
signal IPIF_rx_Pong_CE : std_logic := '0';
signal tx_ping_data_out : std_logic_vector (31 downto 0);
signal tx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal rx_ping_data_out : std_logic_vector (31 downto 0);
signal rx_pong_data_out : std_logic_vector (31 downto 0) := (others => '0');
signal dpm_wr_ack : std_logic;
signal dpm_rd_ack : std_logic;
signal rx_done : std_logic;
signal rx_done_d1 : std_logic := '0';
signal tx_done : std_logic;
signal tx_done_d1 : std_logic := '0';
signal tx_done_d2 : std_logic := '0';
signal tx_ping_ce : std_logic;
signal tx_pong_ping_l : std_logic := '0';
signal tx_idle : std_logic;
signal rx_idle : std_logic;
signal rx_ping_ce : std_logic;
signal rx_pong_ping_l : std_logic := '0';
signal reg_access : std_logic;
signal reg_en : std_logic;
signal tx_ping_reg_en : std_logic;
signal tx_pong_reg_en : std_logic;
signal rx_ping_reg_en : std_logic;
signal rx_pong_reg_en : std_logic;
signal tx_ping_ctrl_reg_en : std_logic;
signal tx_ping_length_reg_en : std_logic;
signal tx_pong_ctrl_reg_en : std_logic;
signal tx_pong_length_reg_en : std_logic;
signal rx_ping_ctrl_reg_en : std_logic;
signal rx_pong_ctrl_reg_en : std_logic;
signal loopback_en : std_logic;
signal tx_intr_en : std_logic;
signal ping_mac_program : std_logic;
signal pong_mac_program : std_logic;
signal ping_tx_status : std_logic;
signal pong_tx_status : std_logic;
signal ping_pkt_lenth : std_logic_vector(15 downto 0);
signal pong_pkt_lenth : std_logic_vector(15 downto 0);
signal rx_intr_en : std_logic;
signal ping_rx_status : std_logic;
signal pong_rx_status : std_logic;
signal ping_tx_done : std_logic;
signal mdio_data_out : std_logic_vector(31 downto 0);
signal reg_data_out : std_logic_vector(31 downto 0);
signal mdio_reg_en : std_logic;
signal gie_reg : std_logic;
signal gie_reg_en : std_logic;
signal gie_enable : std_logic;
signal tx_packet_length : std_logic_vector(15 downto 0);
signal stat_reg_en : std_logic;
signal status_reg : std_logic_vector(5 downto 0);
signal ping_mac_prog_done : std_logic;
signal transmit_start : std_logic;
signal mac_program_start : std_logic;
signal rx_buffer_ready : std_logic;
signal dpm_addr_ack : std_logic;
signal control_reg : std_logic;
signal length_reg : std_logic;
signal word_access : std_logic;
signal reg_access_i : std_logic;
signal ip2intc_irpt_i : std_logic;
signal reg_access_d1 : std_logic;
signal ping_soft_status : std_logic;
signal pong_soft_status : std_logic;
signal rx_pong_ce_en : std_logic;
signal tx_pong_ce_en : std_logic;
-------------------------------------------------------------------------------
-- New ipif_ssp1 signal declaration --
-------------------------------------------------------------------------------
signal bus2ip_ce : std_logic;
signal tx_ping_ce_en : std_logic;
signal rx_ping_ce_en : std_logic;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component SRL16E
generic (
INIT : bit_vector := X"0000"
);
port (
Q : out std_logic; --[out]
A0 : in std_logic; --[in]
A1 : in std_logic; --[in]
A2 : in std_logic; --[in]
A3 : in std_logic; --[in]
CE : in std_logic; --[in]
CLK : in std_logic; --[in]
D : in std_logic --[in]
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component LUT4
generic(INIT : bit_vector);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
begin
IP2Bus_Error <= '0';
-- IP2INTC_Irpt generation if global interrupt is enable
ip2intc_irpt_i <= gie_enable and ((rx_done and rx_intr_en) or
(tx_done and tx_intr_en));
----------------------------------------------------------------------------
-- IP2INTC_IRPT register
----------------------------------------------------------------------------
IP2INTC_IRPT_REG_I: FDR
port map (
Q => IP2INTC_Irpt , --[out]
C => Clk , --[in]
D => ip2intc_irpt_i, --[in]
R => Rst --[in]
);
-- ----------------------------------------------------------------------------
-- -- IPIF interface
-- ----------------------------------------------------------------------------
-- PHY_tx_data conversion
PHY_tx_data(0) <= phy_tx_data_i(0);
PHY_tx_data(1) <= phy_tx_data_i(1);
PHY_tx_data(2) <= phy_tx_data_i(2);
PHY_tx_data(3) <= phy_tx_data_i(3);
-- PHY_rx_data conversion
phy_rx_data_i(0) <= PHY_rx_data(0);
phy_rx_data_i(1) <= PHY_rx_data(1);
phy_rx_data_i(2) <= PHY_rx_data(2);
phy_rx_data_i(3) <= PHY_rx_data(3);
----------------------------------------------------------------------------
-- EMAC
----------------------------------------------------------------------------
EMAC_I: entity axi_ethernetlite_v3_0.emac
generic map (
C_DUPLEX => C_DUPLEX,
NODE_MAC => NODE_MAC,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Rst => Rst,
Phy_tx_clk => PHY_tx_clk,
Phy_rx_clk => PHY_rx_clk,
Phy_crs => phy_crs,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data_i,
Phy_col => Phy_col,
Phy_rx_er => Phy_rx_er,
Phy_tx_en => Phy_tx_en,
Phy_tx_data => Phy_tx_data_i,
Tx_DPM_ce => tx_DPM_ce_i,
Tx_DPM_adr => tx_DPM_adr,
Tx_DPM_wr_data => tx_DPM_wr_data,
Tx_DPM_rd_data => tx_DPM_rd_data,
Tx_DPM_wr_rd_n => tx_DPM_wr_rd_n,
Tx_done => tx_done,
Tx_pong_ping_l => tx_pong_ping_l,
Tx_idle => tx_idle,
Rx_idle => rx_idle,
Rx_DPM_ce => rx_DPM_ce_i,
Rx_DPM_adr => rx_DPM_adr,
Rx_DPM_wr_data => rx_DPM_wr_data,
Rx_DPM_rd_data => rx_DPM_rd_data,
Rx_DPM_wr_rd_n => rx_DPM_wr_rd_n ,
Rx_done => rx_done,
Rx_pong_ping_l => rx_pong_ping_l,
Tx_packet_length => tx_packet_length,
Transmit_start => transmit_start,
Mac_program_start => mac_program_start,
Rx_buffer_ready => rx_buffer_ready
);
----------------------------------------------------------------------------
-- This core only supports word access
word_access <= '1' when bus2ip_be="1111" else '0';
-- DPRAM buffer chip enable generation
bus2ip_ce <= (Bus2IP_RdCE or (Bus2IP_WrCE and word_access));
tx_ping_ce_en <= not Bus2IP_Addr(12) and not Bus2IP_Addr(11);
rx_ping_ce_en <= Bus2IP_Addr(12) and not Bus2IP_Addr(11);
IPIF_tx_Ping_CE <= bus2ip_ce and tx_ping_ce_en;
IPIF_rx_Ping_CE <= bus2ip_ce and rx_ping_ce_en;
-- IP2Bus_Data generation
IP2BUS_DATA_GENERATE: for i in 31 downto 0 generate
IP2Bus_Data(i) <= ((
(tx_ping_data_out(i) and tx_ping_ce_en) or
(tx_pong_data_out(i) and tx_pong_ce_en) or
(rx_ping_data_out(i) and rx_ping_ce_en) or
(rx_pong_data_out(i) and rx_pong_ce_en)
) and not reg_access)
or
((
(reg_data_out(i) and not mdio_reg_en) or
(mdio_data_out(i) and mdio_reg_en)
) and reg_access) ;
end generate IP2BUS_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_TX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates tx_DPM_rd_data for transmit section from
-- tx_ping_buffer and tx_pong_buffer.
----------------------------------------------------------------------------
DPM_TX_RD_DATA_GENERATE: for i in 0 to 3 generate
tx_DPM_rd_data(i) <= (tx_ping_rd_data(i) and not tx_pong_ping_l
and (not tx_idle)) or
(tx_pong_rd_data(i) and tx_pong_ping_l
and (not tx_idle));
end generate DPM_TX_RD_DATA_GENERATE;
----------------------------------------------------------------------------
-- DPM_RX_RD_DATA_GENERATE
----------------------------------------------------------------------------
-- This logic generates rx_DPM_rd_data for receive section from
-- rx_ping_buffer and rx_pong_buffer.
----------------------------------------------------------------------------
DPM_RX_RD_DATA_GENERATE: for i in 0 to 3 generate
rx_DPM_rd_data(i) <= (rx_ping_rd_data(i) and not rx_pong_ping_l) or
(rx_pong_rd_data(i) and rx_pong_ping_l);
end generate DPM_RX_RD_DATA_GENERATE;
-- Chip enable generation
tx_ping_ce <= tx_DPM_ce and not tx_pong_ping_l;
tx_DPM_ce <= tx_DPM_ce_i;
rx_DPM_ce <= rx_DPM_ce_i;
rx_ping_ce <= rx_DPM_ce and not rx_pong_ping_l;
----------------------------------------------------------------------------
-- TX_PING Buffer
----------------------------------------------------------------------------
TX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_ping_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_ping_rd_data ,
Ce_b => IPIF_tx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_ping_data_out
);
----------------------------------------------------------------------------
-- RX_PING Buffer
----------------------------------------------------------------------------
RX_PING: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_ping_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_ping_rd_data ,
Ce_b => IPIF_rx_Ping_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_ping_data_out
);
----------------------------------------------------------------------------
-- TX Done register
----------------------------------------------------------------------------
TX_DONE_D1_I: FDR
port map (
Q => tx_done_d1 , --[out]
C => Clk , --[in]
D => tx_done , --[in]
R => Rst --[in]
);
TX_DONE_D2_I: FDR
port map (
Q => tx_done_d2 , --[out]
C => Clk , --[in]
D => tx_done_d1 , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Transmit Pong memory generate
----------------------------------------------------------------------------
TX_PONG_GEN: if C_TX_PING_PONG = 1 generate
signal tx_pong_ce : std_logic;
signal pp_tog_ce : std_logic;
attribute INIT : string;
-- attribute INIT of PP_TOG_LUT_I: label is "1111";
Begin
TX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => tx_pong_ce ,
Wr_rd_n_a => tx_DPM_wr_rd_n ,
Adr_a => tx_DPM_adr ,
Data_in_a => tx_DPM_wr_data ,
Data_out_a => tx_pong_rd_data ,
Ce_b => IPIF_tx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => tx_pong_data_out
);
-- TX Pong Buffer Chip enable
tx_pong_ce <= tx_DPM_ce and tx_pong_ping_l;
--IPIF_tx_Pong_CE <= bus2ip_ce and not Bus2IP_Addr(12) Bus2IP_Addr(11);
IPIF_tx_Pong_CE <= bus2ip_ce and tx_pong_ce_en;
tx_pong_ce_en <= not Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- TX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate tx_pong_ping_l for TX PING/PONG buffer access
-------------------------------------------------------------------------
TX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_pong_ping_l <= '0';
elsif (tx_done_d1 = '1' ) then
tx_pong_ping_l <= not tx_pong_ping_l;
elsif (pong_tx_status = '1' and ping_tx_status = '0' ) then
tx_pong_ping_l <= '1';
elsif (pong_tx_status = '0' and ping_tx_status = '1' ) then
tx_pong_ping_l <= '0';
else
tx_pong_ping_l <= tx_pong_ping_l;
end if;
end if;
end process;
end generate TX_PONG_GEN;
----------------------------------------------------------------------------
-- RX Done register
----------------------------------------------------------------------------
RX_DONE_D1_I: FDR
port map (
Q => rx_done_d1 , --[out]
C => Clk , --[in]
D => rx_done , --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Receive Pong memory generate
----------------------------------------------------------------------------
RX_PONG_GEN: if C_RX_PING_PONG = 1 generate
signal rx_pong_ce : std_logic;
Begin
RX_PONG_I: entity axi_ethernetlite_v3_0.emac_dpram
generic map (
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk ,
Rst => Rst ,
Ce_a => rx_pong_ce ,
Wr_rd_n_a => rx_DPM_wr_rd_n ,
Adr_a => rx_DPM_adr ,
Data_in_a => rx_DPM_wr_data ,
Data_out_a => rx_pong_rd_data ,
Ce_b => IPIF_rx_Pong_CE ,
Wr_rd_n_b => Bus2IP_WrCE ,
Adr_b => bus2ip_addr(10 downto 2) ,
Data_in_b => Bus2IP_Data ,
Data_out_b => rx_pong_data_out
);
-- RX Pong Buffer enable
rx_pong_ce <= rx_DPM_ce and rx_pong_ping_l;
--IPIF_rx_Pong_CE <= bus2ip_ce and Bus2IP_Addr(12) and Bus2IP_Addr(11);
IPIF_rx_Pong_CE <= bus2ip_ce and rx_pong_ce_en;
rx_pong_ce_en <= Bus2IP_Addr(12) and Bus2IP_Addr(11);
-------------------------------------------------------------------------
-- RX_PONG_PING_L_PROCESS
-------------------------------------------------------------------------
-- This process generate rx_pong_ping_l for RX PING/PONG buffer access
-------------------------------------------------------------------------
RX_PONG_PING_L_PROCESS:process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_pong_ping_l <= '0';
elsif (rx_done_d1 = '1') then
if rx_pong_ping_l = '0' then
rx_pong_ping_l <= '1';
else
rx_pong_ping_l <= '0';
end if;
else
rx_pong_ping_l <= rx_pong_ping_l;
end if;
end if;
end process;
end generate RX_PONG_GEN;
----------------------------------------------------------------------------
-- Regiter Address Decoding
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- Register Address Space
-----------------------------------------
-- **** MDIO Registers offset ****
-- Address Register => 0x07E4
-- Write Data Register => 0x07E8
-- Read Data Register => 0x07Ec
-- Control Register => 0x07F0
-----------------------------------------
-- **** Transmit Registers offset ****
-- Ping Length Register => 0x07F4
-- Ping Control Register => 0x07FC
-- Pong Length Register => 0x0FF4
-- Pong Control Register => 0x0FFC
-----------------------------------------
-- **** Receive Registers offset ****
-- Ping Control Register => 0x17FC
-- Pong Control Register => 0x1FFC
------------------------------------------
-- bus2ip_addr(12 downto 0)= axi_addr (12 downto 0)
----------------------------------------------------------------------------
reg_access_i <= '1' when bus2ip_addr(10 downto 5) = "111111"
else '0';
-- Register access enable
reg_en <= reg_access_i and (not Bus2IP_Burst);
-- TX/RX PING/PONG address decode
tx_ping_reg_en <= reg_en and (not bus2ip_addr(12)) and (not bus2ip_addr(11));
rx_ping_reg_en <= reg_en and ( bus2ip_addr(12)) and (not bus2ip_addr(11));
-- Status/Control/Length address decode
stat_reg_en <= not (bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2));
control_reg <= bus2ip_addr(4) and bus2ip_addr(3) and bus2ip_addr(2);
length_reg <= bus2ip_addr(4) and (not bus2ip_addr(3)) and bus2ip_addr(2);
gie_reg <= bus2ip_addr(4) and bus2ip_addr(3) and (not bus2ip_addr(2));
---- TX/RX Ping/Pong Control/Length reg enable
tx_ping_ctrl_reg_en <= tx_ping_reg_en and control_reg;
tx_ping_length_reg_en <= tx_ping_reg_en and length_reg;
rx_ping_ctrl_reg_en <= rx_ping_reg_en and control_reg;
gie_reg_en <= tx_ping_reg_en and gie_reg;
----------------------------------------------------------------------------
-- REG_ACCESS_PROCESS
----------------------------------------------------------------------------
-- Registering the reg_access to break long timing path
----------------------------------------------------------------------------
REG_ACCESS_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_access <= '0';
reg_access_d1 <= '0';
elsif Bus2IP_RdCE='1' then
-- TX/RX Ping/Pong Control/Length reg enable
reg_access <= reg_access_i;
reg_access_d1 <= reg_access;
end if;
end if;
end process REG_ACCESS_PROCESS;
----------------------------------------------------------------------------
-- TX_PONG_REG_GEN : Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
TX_PONG_REG_GEN: if C_TX_PING_PONG = 1 generate
tx_pong_reg_en <= reg_en and (not bus2ip_addr(12))
and (bus2ip_addr(11));
tx_pong_ctrl_reg_en <= '1' when (tx_pong_reg_en='1') and
(control_reg='1') else
'0';
tx_pong_length_reg_en <= '1' when (tx_pong_reg_en='1') and
(length_reg='1') else
'0';
-------------------------------------------------------------------------
-- TX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-------------------------------------------------------------------------
TX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_mac_program <= '0';
pong_tx_status <= '0';
pong_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- Load Pong Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_soft_status <= Bus2IP_Data(31);
pong_mac_program <= Bus2IP_Data(1);
pong_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '1') then
pong_tx_status <= '0';
pong_mac_program <= '0';
end if;
end if;
end process TX_PONG_CTRL_REG_PROCESS;
-------------------------------------------------------------------------
-- TX_PONG_LENGTH_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the length register is enabled.
-------------------------------------------------------------------------
TX_PONG_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_pong_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
pong_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PONG_LENGTH_REG_PROCESS;
end generate TX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- NO_TX_PING_SIG :No Pong registers
----------------------------------------------------------------------------
NO_TX_PING_SIG: if C_TX_PING_PONG = 0 generate
tx_pong_ping_l <= '0';
tx_pong_length_reg_en <= '0';
tx_pong_ctrl_reg_en <= '0';
pong_pkt_lenth <= (others=>'0');
pong_mac_program <= '0';
pong_tx_status <= '0';
IPIF_tx_Pong_CE <= '0';
tx_pong_data_out <= (others=>'0');
tx_pong_rd_data <= (others=>'0');
end generate NO_TX_PING_SIG;
----------------------------------------------------------------------------
-- RX_PONG_REG_GEN: Receive Pong Register generate
----------------------------------------------------------------------------
-- This Logic is included only if both the buffers are enabled.
----------------------------------------------------------------------------
RX_PONG_REG_GEN: if C_RX_PING_PONG = 1 generate
rx_pong_reg_en <= reg_en and (bus2ip_addr(12)) and (bus2ip_addr(11));
rx_pong_ctrl_reg_en <= '1' when (rx_pong_reg_en='1') and
(control_reg='1') else
'0';
-- Receive frame indicator
rx_buffer_ready <= not (ping_rx_status and pong_rx_status);
-------------------------------------------------------------------------
-- RX_PONG_CTRL_REG_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Pong control register is enabled.
-------------------------------------------------------------------------
RX_PONG_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
pong_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
pong_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
--elsif (rx_done_d1 = '1' and rx_pong_ping_l = '1') then
elsif (rx_done = '1' and rx_pong_ping_l = '1') then
pong_rx_status <= '1';
end if;
end if;
end process RX_PONG_CTRL_REG_PROCESS;
end generate RX_PONG_REG_GEN;
----------------------------------------------------------------------------
-- No Pong registers
----------------------------------------------------------------------------
NO_RX_PING_SIG: if C_RX_PING_PONG = 0 generate
rx_pong_ping_l <= '0';
rx_pong_reg_en <= '0';
rx_pong_ctrl_reg_en <= '0';
pong_rx_status <= '0';
IPIF_rx_Pong_CE <= '0';
rx_pong_rd_data <= (others=>'0');
rx_pong_data_out <= (others=>'0');
-- Receive frame indicator
rx_buffer_ready <= not ping_rx_status ;
end generate NO_RX_PING_SIG;
----------------------------------------------------------------------------
-- TX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_intr_en <= '0';
ping_mac_program <= '0';
ping_tx_status <= '0';
ping_soft_status <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
ping_soft_status <= Bus2IP_Data(31);
tx_intr_en <= Bus2IP_Data(3);
ping_mac_program <= Bus2IP_Data(1);
ping_tx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (tx_done_d1 = '1' and tx_pong_ping_l = '0') then
ping_tx_status <= '0';
ping_mac_program <= '0';
end if;
end if;
end process TX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LOOPBACK_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LOOPBACK_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
loopback_en <= '0';
elsif (Bus2IP_WrCE = '1' and tx_ping_ctrl_reg_en = '1'
and tx_idle='1' ) then
-- Load loopback Register with AXI
-- data if there is a write request
-- and the Loopback register is enabled
loopback_en <= Bus2IP_Data(4);
-- Clear the status bit when trnasmit complete
end if;
end if;
end process TX_LOOPBACK_REG_PROCESS;
----------------------------------------------------------------------------
-- CDC module for syncing tx_en_i in fifo_empty domain
----------------------------------------------------------------------------
-- CDC_LOOPBACK: entity proc_common_v4_0.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => loopback_en,
-- prmry_ack => open,
-- scndry_out => Loopback,
-- scndry_aclk => PHY_rx_clk,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
Loopback <= loopback_en; --added the cdc block to drive the output directly
----------------------------------------------------------------------------
-- TX_PING_LENGTH_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Length register is enabled.
----------------------------------------------------------------------------
TX_PING_LENGTH_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
ping_pkt_lenth <= (others=>'0');
elsif (Bus2IP_WrCE = '1' and tx_ping_length_reg_en = '1') then
-- Load Packet length Register with AXI
-- data if there is a write request
-- and the length register is enabled
ping_pkt_lenth <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process TX_PING_LENGTH_REG_PROCESS;
----------------------------------------------------------------------------
-- GIE_EN_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the GIE register is enabled.
----------------------------------------------------------------------------
GIE_EN_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
gie_enable <= '0';
elsif (Bus2IP_WrCE = '1' and gie_reg_en = '1') then
-- Load Global Interrupt Enable Register with AXI
-- data if there is a write request
-- and the length register is enabled
gie_enable <= Bus2IP_Data(31);
end if;
end if;
end process GIE_EN_REG_PROCESS;
----------------------------------------------------------------------------
-- RX_PING_CTRL_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Ping control register is enabled.
----------------------------------------------------------------------------
RX_PING_CTRL_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
rx_intr_en <= '0';
ping_rx_status <= '0';
elsif (Bus2IP_WrCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
rx_intr_en <= Bus2IP_Data(3);
ping_rx_status <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif (rx_done = '1' and rx_pong_ping_l = '0') then
ping_rx_status <= '1';
end if;
end if;
end process RX_PING_CTRL_REG_PROCESS;
----------------------------------------------------------------------------
-- REGISTER_READ_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
REGISTER_READ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
reg_data_out <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_ping_ctrl_reg_en = '1') then
-- TX PING Control Register Read through AXI
reg_data_out(0) <= ping_tx_status;
reg_data_out(1) <= ping_mac_program;
reg_data_out(2) <= '0';
reg_data_out(3) <= tx_intr_en;
reg_data_out(4) <= loopback_en;
reg_data_out(31) <= ping_soft_status;
reg_data_out(30 downto 5) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and tx_pong_ctrl_reg_en = '1') then
-- TX PONG Control Register Read through AXI
reg_data_out(0) <= pong_tx_status;
reg_data_out(1) <= pong_mac_program;
reg_data_out(30 downto 2) <= (others=>'0');
reg_data_out(31) <= pong_soft_status;
elsif (Bus2IP_RdCE = '1' and tx_ping_length_reg_en = '1') then
-- TX PING Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= ping_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and tx_pong_length_reg_en = '1') then
-- TX PONG Length Register Read through AXI
reg_data_out(31 downto 16) <= (others=>'0');
reg_data_out(15 downto 0) <= pong_pkt_lenth;
elsif (Bus2IP_RdCE = '1' and rx_ping_ctrl_reg_en = '1') then
-- RX PING Control Register Read through AXI
reg_data_out(0) <= ping_rx_status;
reg_data_out(1) <= '0';
reg_data_out(2) <= '0';
reg_data_out(3) <= rx_intr_en;
reg_data_out(31 downto 4) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and rx_pong_ctrl_reg_en = '1') then
-- RX PONG Control Register Read through AXI
reg_data_out(0) <= pong_rx_status;
reg_data_out(31 downto 1) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and gie_reg_en = '1') then
-- GIE Register Read through AXI
reg_data_out(31) <= gie_enable;
reg_data_out(30 downto 0) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and stat_reg_en = '1') then
-- Common Status Register Read through AXI
reg_data_out(0) <= status_reg(0);
reg_data_out(1) <= status_reg(1);
reg_data_out(2) <= status_reg(2);
reg_data_out(3) <= status_reg(3);
reg_data_out(4) <= status_reg(4);
reg_data_out(5) <= status_reg(5);
reg_data_out(31 downto 6) <= (others=>'0');
--else
-- reg_data_out <= (others=>'0');
end if;
end if;
end process REGISTER_READ_PROCESS;
----------------------------------------------------------------------------
-- COMMON_STATUS_REG_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
-- status_reg : std_logic_vector(0 to 5);
-- status reg address = 0x07E0
-- status_reg(5) : Ping TX complete
-- status_reg(4) : Pong TX complete
-- status_reg(3) : Ping RX complete
-- status_reg(2) : Pong RX complete
-- status_reg(1) : Ping MAC program complete
-- status_reg(0) : Pong MAC program complete
-- All Status bit will be cleared after reading this register
----------------------------------------------------------------------------
COMMON_STATUS_REG_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
status_reg <= (others=>'0');
elsif (tx_done = '1') then
if (tx_pong_ping_l = '0' and ping_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(5) <= '1';
elsif (tx_pong_ping_l = '0' and ping_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(1) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='0' ) then
status_reg <= (others=>'0');
status_reg(4) <= '1';
elsif (tx_pong_ping_l = '1' and pong_mac_program='1' ) then
status_reg <= (others=>'0');
status_reg(0) <= '1';
end if;
elsif (rx_done_d1 = '1') then
if (rx_pong_ping_l = '0') then
status_reg <= (others=>'0');
status_reg(3) <= '1';
else
status_reg <= (others=>'0');
status_reg(2) <= '1';
end if;
end if;
end if;
end process COMMON_STATUS_REG_PROCESS;
----------------------------------------------------------------------------
-- TX_LENGTH_MUX_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
TX_LENGTH_MUX_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
tx_packet_length <= (others=>'0');
elsif (tx_pong_ping_l = '1') then
-- Load Control Register with AXI
tx_packet_length <= pong_pkt_lenth;
-- Clear the status bit when trnasmit complete
else
tx_packet_length <= ping_pkt_lenth;
end if;
end if;
end process TX_LENGTH_MUX_PROCESS;
-- Tx Start indicator
transmit_start <= ((ping_tx_status and not ping_mac_program) or
(pong_tx_status and not pong_mac_program)) and
not tx_done_d2;
-- MAC program start indicator
mac_program_start <= (ping_tx_status and ping_mac_program) or
(pong_tx_status and pong_mac_program);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 1
----------------------------------------------------------------------------
MDIO_GEN: if C_INCLUDE_MDIO = 1 generate
signal mdio_addr_en : std_logic;
signal mdio_wr_data_en : std_logic;
signal mdio_rd_data_en : std_logic;
signal mdio_ctrl_en : std_logic;
signal mdio_op_i : std_logic;
signal mdio_en_i : std_logic;
signal mdio_req_i : std_logic;
signal mdio_done_i : std_logic;
signal mdio_wr_data_reg : std_logic_vector(15 downto 0);
signal mdio_rd_data_reg : std_logic_vector(15 downto 0);
signal mdio_phy_addr : std_logic_vector(4 downto 0);
signal mdio_reg_addr : std_logic_vector(4 downto 0);
signal mdio_clk_i : std_logic;
-- signal mdio_ctrl_en_reg : std_logic;
signal clk_cnt : integer range 0 to 63;
begin
-- MDIO reg enable
mdio_reg_en <= --not stat_reg_en_reg and
(mdio_addr_en or
mdio_wr_data_en or
mdio_rd_data_en or
mdio_ctrl_en ) and (not Bus2IP_Burst);
--mdio_ctrl_en or mdio_ctrl_en_reg ) and (not Bus2IP_Burst);
-- MDIO address reg enable
mdio_addr_en <= reg_en and (not bus2ip_addr(4))
and (not bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO write data reg enable
mdio_wr_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and (not bus2ip_addr(2));
-- MDIO read data reg enable
mdio_rd_data_en <= reg_en and (not bus2ip_addr(4))
and ( bus2ip_addr(3))
and ( bus2ip_addr(2));
-- MDIO controlreg enable
mdio_ctrl_en <= reg_en and ( bus2ip_addr(4))
and (not bus2ip_addr(3))
and (not bus2ip_addr(2));
-------------------------------------------------------------------------
-- MDIO_CTRL_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO control register is enabled.
-------------------------------------------------------------------------
MDIO_CTRL_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_en_i <= '0';
mdio_req_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_ctrl_en= '1') then
-- Load MDIO Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
mdio_en_i <= Bus2IP_Data(3);
mdio_req_i <= Bus2IP_Data(0);
-- Clear the status bit when trnasmit complete
elsif mdio_done_i = '1' then
mdio_req_i <= '0';
end if;
end if;
end process MDIO_CTRL_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_ADDR_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the MDIO Address register is enabled.
-------------------------------------------------------------------------
MDIO_ADDR_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_phy_addr <= (others =>'0');
mdio_reg_addr <= (others =>'0');
mdio_op_i <= '0';
elsif (Bus2IP_WrCE = '1' and mdio_addr_en= '1') then
-- Load MDIO ADDR Register with AXI
-- data if there is a write request
-- and the Address register is enabled
mdio_phy_addr <= Bus2IP_Data(9 downto 5);
mdio_reg_addr <= Bus2IP_Data(4 downto 0);
mdio_op_i <= Bus2IP_Data(10);
end if;
end if;
end process MDIO_ADDR_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_WRITE_REG_WR_PROCESS
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request
-- and the MDIO Write register is enabled.
-------------------------------------------------------------------------
MDIO_WRITE_REG_WR_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_wr_data_reg <= (others =>'0');
elsif (Bus2IP_WrCE = '1' and mdio_wr_data_en= '1') then
-- Load MDIO Write Data Register with AXI
-- data if there is a write request
-- and the Write Data register is enabled
mdio_wr_data_reg <= Bus2IP_Data(15 downto 0);
end if;
end if;
end process MDIO_WRITE_REG_WR_PROCESS;
-------------------------------------------------------------------------
-- MDIO_REG_RD_PROCESS
-------------------------------------------------------------------------
-- This process allows MDIO register read from the AXI when there is a
-- read request and the MDIO registers are enabled.
-------------------------------------------------------------------------
MDIO_REG_RD_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if (Rst = '1') then
mdio_data_out <= (others =>'0');
elsif (Bus2IP_RdCE = '1' and mdio_addr_en= '1') then
-- MDIO Address Register Read through AXI
mdio_data_out(4 downto 0) <= mdio_reg_addr;
mdio_data_out(9 downto 5) <= mdio_phy_addr;
mdio_data_out(10) <= mdio_op_i;
mdio_data_out(31 downto 11) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_wr_data_en= '1') then
-- MDIO Write Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_wr_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_rd_data_en= '1') then
-- MDIO Read Data Register Read through AXI
mdio_data_out(15 downto 0) <= mdio_rd_data_reg;
mdio_data_out(31 downto 16) <= (others=>'0');
elsif (Bus2IP_RdCE = '1' and mdio_ctrl_en= '1') then
-- MDIO Control Register Read through AXI
mdio_data_out(0) <= mdio_req_i;
mdio_data_out(1) <= '0';
mdio_data_out(2) <= '0';
mdio_data_out(3) <= mdio_en_i;
mdio_data_out(31 downto 4) <= (others=>'0');
--else
-- mdio_data_out <= (others =>'0');
end if;
end if;
end process MDIO_REG_RD_PROCESS;
-------------------------------------------------------------------------
-- PROCESS : MDIO_CLK_COUNTER
-------------------------------------------------------------------------
-- Generating MDIO clock. The minimum period for MDC clock is 400 ns.
-------------------------------------------------------------------------
MDIO_CLK_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= '0';
elsif (clk_cnt = 0) then
clk_cnt <= MDIO_CNT;
mdio_clk_i <= not mdio_clk_i;
else
clk_cnt <= clk_cnt - 1;
end if;
end if;
end process;
-------------------------------------------------------------------------
-- MDIO master interface module
-------------------------------------------------------------------------
MDIO_IF_I: entity axi_ethernetlite_v3_0.mdio_if
port map (
Clk => Clk ,
Rst => Rst ,
MDIO_CLK => mdio_clk_i ,
MDIO_en => mdio_en_i ,
MDIO_OP => mdio_op_i ,
MDIO_Req => mdio_req_i ,
MDIO_PHY_AD => mdio_phy_addr ,
MDIO_REG_AD => mdio_reg_addr ,
MDIO_WR_DATA => mdio_wr_data_reg ,
MDIO_RD_DATA => mdio_rd_data_reg ,
PHY_MDIO_I => PHY_MDIO_I ,
PHY_MDIO_O => PHY_MDIO_O ,
PHY_MDIO_T => PHY_MDIO_T ,
PHY_MDC => PHY_MDC ,
MDIO_done => mdio_done_i
);
end generate MDIO_GEN;
----------------------------------------------------------------------------
-- NO_MDIO_GEN :- Include MDIO interface if the parameter C_INCLUDE_MDIO = 0
----------------------------------------------------------------------------
NO_MDIO_GEN: if C_INCLUDE_MDIO = 0 generate
begin
mdio_data_out <= (others=>'0');
mdio_reg_en <= '0';
PHY_MDIO_O <= '0';
PHY_MDIO_T <= '1';
end generate NO_MDIO_GEN;
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_timer_v2_0/de85f913/hdl/src/vhdl/tc_types.vhd
|
10
|
6731
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/ipic_if.vhd
|
4
|
25987
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: ipic_if.vhd
-- Description: IPIC Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- ~~~~~~~~
-- ^^^^^^^^
-- KSB 08/08/08 version v4_00_a
-- 1. This file is same as in version v3_00_a.
-- 2. Upgraded to version v4.00.a
-- ~~~~~~~~
-- SK 10/07/10
-- ^^^^^^^^
-- 1. Added "clear_pend_rdreq <= '1' when ((burst_cnt_i = 0) and (Bus2IP_Burst = '0') and
--(Mem2Bus_RdAddrAck = '1')) or bus2Mem_CS_i = '0'
-- else
--'0' ;
-- 2. condition for "clear_pend_wrreq". This is similar to "clear_pend_rdreq" .
-- ~~~~~~~~
-- SK 25/10/10
-- ^^^^^^^^
-- 1. Registered IP2bus_RdAck and IP2Bus_Data signals.
-- ~~~~~~~~
-- SK 24/11/10
-- ^^^^^^^^
-- 1. Added "Bus2IP_RdReq_emc = '0'" signal to reset the RDREQ_PROCESS.
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
library emc_common_v3_0;
-------------------------------------------------------------------------------
-- vcomponents package of the unisim library is used for the FDR component
-- declaration
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BANKS_MEM -- Number of Memory Banks
-- C_IPIF_DWIDTH -- Processor Data Bus Width
--
-- Definition of Ports:
-- Bus2IP_RNW -- Processor read not write (1=Read, 0=Write)
-- Bus2IP_Mem_CS -- Memory Channel Chip Select
-- Mem2Bus_RdAddrAck -- Memory Read Cycle Address Acknowledge
-- Mem2Bus_WrAddrAck -- Memory Write Cycle Address Acknowledge
-- Mem2Bus_RdAck -- Memory Read Cycle Acknowledge
-- Mem2Bus_WrAck -- Memory Write Cycle Acknowledge
-- Mem2Bus_Data -- Memory Read Data
-- Bus2Mem_RdReq -- Read request was seen by mem_state_machine
-- Bus2Mem_WrReq -- Write request was seen by mem_state_machine
-- Bus2Mem_CS -- Memory is being accessed
-- IP2Bus_Data -- Read data from memory device or register
-- IP2Bus_errAck -- Error acknowledge
-- IP2Bus_retry -- Retry indicator
-- IP2Bus_toutSup -- Suppress watch dog timer
-- IP2Bus_RdAck -- Read acknowledge
-- IP2Bus_WrAck -- Write acknowledge
-- IP2Bus_AddrAck -- Address acknowledge
-- Burst_length -- Count of current burst length
-- Transaction_done -- Operation complete indication for current
-- -- transaction
-- Bus2IP_Clk -- System clock
-- Bus2IP_Reset -- System Reset
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity ipic_if is
generic (
C_NUM_BANKS_MEM : integer := 2;
C_IPIF_DWIDTH : integer := 64
);
port (
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_RNW : in std_logic;
Bus2IP_Mem_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem2Bus_RdAddrAck : in std_logic;
Mem2Bus_WrAddrAck : in std_logic;
Mem2Bus_RdAck : in std_logic;
Mem2Bus_WrAck : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Mem2Bus_Data : in std_logic_vector(0 to C_IPIF_DWIDTH - 1);
Bus2IP_Burst : in std_logic;
Bus2IP_RdReq_emc : in std_logic;
Bus2IP_WrReq_emc : in std_logic;
Bus2Mem_CS : out std_logic;
Bus2Mem_RdReq : out std_logic;
Bus2Mem_WrReq : out std_logic;
Parity_err : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH - 1);
IP2Bus_errAck : out std_logic;
IP2Bus_retry : out std_logic;
IP2Bus_toutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_AddrAck : out std_logic;
Type_of_xfer : in std_logic;
Burst_length : in std_logic_vector(0 to 7);
Transaction_done : in std_logic;
single_transaction : in std_logic ;
last_burst_cnt : out std_logic;
pr_state_wait_temp_cmb : in std_logic;
synch_mem : in std_logic; -- 10-12-2012
mem_width_bytes : in std_logic_vector(0 to 3);
stop_oen : out std_logic;
axi_trans_size_reg : in std_logic_vector(1 downto 0); -- 1/3/2013
Linear_flash_brst_rd_flag : in std_logic -- 1/28/2013
);
end entity ipic_if;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of ipic_if is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declaration
-------------------------------------------------------------------------------
constant BURST_CNT_WIDTH : integer := 8;
constant ZERO_CNT : std_logic_vector(0 to BURST_CNT_WIDTH -1)
:= (others=>'0');
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
signal bus2mem_cs_i : std_logic;
signal burst_cnt_en : std_logic;
signal burst_cnt_ld_cmb : std_logic;
signal pend_wrreq : std_logic;
signal set_pend_wrreq : std_logic;
signal clear_pend_wrreq : std_logic;
signal pend_rdreq : std_logic;
signal set_pend_rdreq : std_logic;
signal clear_pend_rdreq : std_logic;
signal burst_cnt_i : std_logic_vector(0 to BURST_CNT_WIDTH - 1);
signal int_wrreq : std_logic;
signal int_rdreq : std_logic;
---remove this signal once fix is made to ipif
signal burst_length_i :std_logic_vector(0 to BURST_CNT_WIDTH - 1);
signal bus2ip_mem_cs_reg :std_logic;--_vector(0 to C_NUM_BANKS_MEM-1);
signal IP2Bus_AddrAck_d1 :std_logic;
signal burst_rst :std_logic;
signal stop_init_rd :std_logic;
signal reload_address :std_logic;
signal reload_req :std_logic;
signal IP2Bus_WrAck_i :std_logic;
signal IP2Bus_AddrAck_i :std_logic;
signal IP2Bus_RdAck_i :std_logic;
signal reset_fifo :std_logic;
signal burst_cnt_i_rdack : std_logic_vector(0 to BURST_CNT_WIDTH - 1);
signal diff_addr_rd_ack : std_logic;
signal burst_cnt_en_rdack: std_logic;
signal first_rd_ack : std_logic;
signal rd_ack_d1 : std_logic;
signal Bus2Mem_RdReq_int : std_logic;
signal bus2Mem_CS_reduce_reg : std_logic;
signal pr_state_wait_temp_reg: std_logic;
signal rd_cnt : std_logic_vector(3 downto 0);
signal stop_oen_int : std_logic;
-- signal stop_oen : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
---------------------------------------------------------------------------
-- IPIC
---------------------------------------------------------------------------
burst_length_i <= Burst_length(0 to BURST_CNT_WIDTH - 1);
bus2Mem_CS_i <= or_reduce(Bus2IP_Mem_CS); -- (bus2IP_Mem_CS_reg); -- 1/3/2013
Bus2Mem_CS <= bus2Mem_CS_i;
IP2Bus_errAck <= (Parity_err or (not Type_of_xfer)) and
bus2Mem_CS_i;
IP2Bus_retry <= '0';
IP2Bus_toutSup <= bus2Mem_CS_i;
--IP2Bus_Data <= Mem2Bus_Data;
int_wrreq <= Bus2IP_WrReq and bus2Mem_CS_i;
int_rdreq <= Bus2IP_RdReq and bus2Mem_CS_i;
---------------------------------------------------------------------------
-- Register the Bus2IP_Mem_CS
---------------------------------------------------------------------------
CS_REG_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
bus2IP_Mem_CS_reg <= '0';--(others=>'0');
pr_state_wait_temp_reg <= '0';
else
bus2IP_Mem_CS_reg <= or_reduce(Bus2IP_Mem_CS);
pr_state_wait_temp_reg <= pr_state_wait_temp_cmb;
end if;
end if;
end process CS_REG_PROCESS;
ONE_HOT_CS_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
bus2Mem_CS_reduce_reg <= '0';
else
bus2Mem_CS_reduce_reg <= bus2Mem_CS_i;
end if;
end if;
end process ONE_HOT_CS_PROCESS;
---------------------------------------------------------------------------
-- Register the acks signals
---------------------------------------------------------------------------
ACK_REG_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
IP2Bus_Data <= (others => '0');
IP2Bus_RdAck <= '0';
else
IP2Bus_Data <= Mem2Bus_Data;
IP2Bus_RdAck <= Mem2Bus_RdAck and (Bus2Mem_RdReq_int or
single_transaction or
Linear_flash_brst_rd_flag);
end if;
end if;
end process ACK_REG_PROCESS;
IP2Bus_WrAck <= Mem2Bus_WrAck;
IP2Bus_AddrAck <= (Mem2Bus_RdAddrAck or Mem2Bus_WrAddrAck) and
(Bus2IP_WrReq or Bus2IP_RdReq);
---------------------------------------------------------------------------
-- Burst length counter instantiation
---------------------------------------------------------------------------
BURST_CNT: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => BURST_CNT_WIDTH,
C_RESET_VALUE => ZERO_CNT,
C_LD_WIDTH => BURST_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Bus2IP_Clk,
RST => reset_fifo,
Q => burst_cnt_i,
LD => burst_length_i,
AD => "1",
LOAD => burst_cnt_ld_cmb,
OP => burst_cnt_en
);
---------------------------------------------------------------------------
-- Burst length counter instantiation -- For Read Ack
---------------------------------------------------------------------------
BURST_CNT_RDACK: entity emc_common_v3_0.ld_arith_reg
generic map (C_ADD_SUB_NOT => false,
C_REG_WIDTH => BURST_CNT_WIDTH,
C_RESET_VALUE => ZERO_CNT,
C_LD_WIDTH => BURST_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Bus2IP_Clk,
RST => reset_fifo,
Q => burst_cnt_i_rdack,
LD => burst_length_i,
AD => "1",
LOAD => burst_cnt_ld_cmb,
OP => burst_cnt_en_rdack
);
burst_cnt_en_rdack <= (diff_addr_rd_ack and Mem2Bus_RdAck);
diff_addr_rd_ack <= or_reduce(burst_cnt_i xor burst_cnt_i_rdack);
---------------------------------------------------------------------------
-- Burst length counter control signals
---------------------------------------------------------------------------
burst_cnt_en <= (Mem2Bus_RdAddrAck or Mem2Bus_WrAddrAck) and
(Bus2IP_WrReq or Bus2IP_RdReq);
burst_cnt_ld_cmb <= not(bus2Mem_CS_reduce_reg) and bus2Mem_CS_i;
reset_fifo <= Bus2IP_Reset or (not bus2Mem_CS_i);
last_burst_cnt <= not (or_reduce(burst_cnt_i));
---------------------------------------------------------------------------
-- Generation of pend_wrreq
---------------------------------------------------------------------------
set_pend_wrreq <= (not pend_wrreq) and Transaction_done and int_wrreq;
clear_pend_wrreq <= '1' when ((burst_cnt_i = 0) and (Bus2IP_Burst = '0') and
(Mem2Bus_WrAddrAck = '1'))or bus2Mem_CS_i = '0' else
'0' ;
WRREQ_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
pend_wrreq <= '0';
elsif set_pend_wrreq ='1' then
pend_wrreq <= '1';
--elsif clear_pend_wrreq = '1' then
elsif(Bus2IP_Burst = '0' and (Mem2Bus_WrAddrAck = '1')) or
(bus2Mem_CS_i = '0') then
pend_wrreq <= '0';
end if;
end if;
end process WRREQ_PROCESS;
Bus2Mem_WrReq <= (pend_wrreq and Bus2IP_WrReq);
---------------------------------------------------------------------------
-- Generation of pend_rdreq
---------------------------------------------------------------------------
set_pend_rdreq <= (not pend_rdreq) and Transaction_done
and int_rdreq;
clear_pend_rdreq <= '1' when ((burst_cnt_i = 0) and (Bus2IP_Burst = '0') and
(Mem2Bus_RdAddrAck = '1')) or bus2Mem_CS_i = '0'
else
'0' ;
RDREQ_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Bus2IP_Reset = '1')then
pend_rdreq <= '0';
elsif set_pend_rdreq = '1'then
pend_rdreq <= '1';
elsif clear_pend_rdreq = '1' then -- 1/3/2013
-- elsif ((Bus2IP_Burst = '0') and -- 1/3/2013
-- (Mem2Bus_RdAddrAck = '1') and -- 1/3/2013
-- (Bus2IP_RdReq_emc = '0')) or -- 1/3/2013
-- (bus2Mem_CS_i = '0') then -- 1/3/2013
pend_rdreq <= '0';
end if;
end if;
end process RDREQ_PROCESS;
Bus2Mem_RdReq_int <= (pend_rdreq and (Bus2IP_RdReq or (diff_addr_rd_ack and Synch_mem)))
when (single_transaction = '0' or Synch_mem = '1')
else
Bus2IP_RdReq;
Bus2Mem_RdReq <= Bus2Mem_RdReq_int;
-- 10-12-2012
RD_CNT_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
if(Transaction_done = '1')then
rd_cnt <= (others => '0');
elsif diff_addr_rd_ack ='1' and Bus2IP_RdReq = '0' and stop_oen_int = '0' then
rd_cnt <= rd_cnt + 1;
end if;
end if;
end process RD_CNT_PROCESS;
-- stop_oen_int <= '1' when rd_cnt = "010" and mem_width_bytes = "0001" else -- 8 bit - reduced by 1 here
-- '1' when rd_cnt = "001" and mem_width_bytes = "0010" else -- 16 bit - reduced by 1 here
-- '1' when rd_cnt = "001" and mem_width_bytes = "0100" else -- 32 bit - reduced by 1 here
-- '0';
STOP_OEN_GEN_PROCESS: process(axi_trans_size_reg,
mem_width_bytes,
rd_cnt) is
variable mem_width_and_size : std_logic_vector(5 downto 0);
-----
begin
-----
mem_width_and_size := mem_width_bytes & axi_trans_size_reg;
case mem_width_and_size is
when "000100" => -- axi byte access for 8 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "000101" => -- axi HW access for 8 bit mem width
--if(rd_cnt = "0010")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(1);
when "000110" => -- axi WORD access for 8 bit mem width
--if(rd_cnt = "0100")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(2);
when "000111" => -- axi Double WORD access for 8 bit mem width
--if(rd_cnt = "1000")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(3);
--------------- for 16 bit mem width
when "001000" => -- axi byte access for 16 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "001001" => -- axi HW access for 16 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "001010" => -- axi WORD access for 16 bit mem width
--if(rd_cnt = "0010")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(1);
when "001011" => -- axi DOUBLE WORD access for 16 bit mem width
--if(rd_cnt = "0100")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(2);
--------------- for 32 bit mem width
when "010000" => -- axi byte access for 32 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "010001" => -- axi HW access for 32 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "010010" => -- axi WORD access for 32 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
when "010011" => -- axi DPOUBLE WORD access for 32 bit mem width
--if(rd_cnt = "0010")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(1);
--------------- for 64 bit mem width
when "100000" | -- axi byte access for 64 bit mem width
"100001" | -- axi HW access for 64 bit mem width
"100010" | -- axi WORD access for 64 bit mem width
"100011" =>-- axi DOUBLE WORD access for 64 bit mem width
--if(rd_cnt = "0001")then
-- stop_oen_int <= '1';
--else
-- stop_oen_int <= '0';
--end if;
stop_oen_int <= rd_cnt(0);
---------------
when others => stop_oen_int <= '0';
end case;
end process STOP_OEN_GEN_PROCESS;
stop_oen <= stop_oen_int;
end imp;
-------------------------------------------------------------------------------
-- End of File ipic_if.vhd
-------------------------------------------------------------------------------
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/mem_steer.vhd
|
4
|
121972
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: mem_steer.vhd
-- Description: This file contains the logic for steering the read data,
-- write data and memory controls to the appropriate memory
-- and data byte lane.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is same as in version v3_01_c - no change in the logic of this
-- module. Deleted the history from version v3_01_c.
-- ~~~~~~
-- NSK 02/12/08 Updated
-- ^^^^^^^^
-- Removed the unused part of code (not supporting C_MAX_MEM_WIDTH = 64): -
-- 1. Deleted the generate block lebelled "WRITE_DATABE_MUX_64_GEN".
-- 2. Deleted the generate block lebelled "READ_DATA_64_GEN".
-- Removed the unused part of code (not supporting C_IPIF_DWIDTH = 64): -
-- 1. Deleted the generate block lebelled "READ_DATA_CE_64_GEN".
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- KSB 05/08/08 version v4_00_a
-- 1. Modified for Page mdoe read
-- 2. Modified for 64 Bit memory address align
-- ~~~~~~~~
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- ~~~~~~
-- SK 25/10/10
-- ^^^^^^^^
-- 1. Added "parity_error_mem" in default condition in "MEM_CEN_STEER_PROCESS".
-- 2. In "PARITY_ACK_SYNC",
-- a.added "MEM2BUS_PARITY_ERR_P" by replacing priority logic
-- b.added "MEM2BUS_RD_ACK_P" by replacing priority logic
-- c.added "ADDR_ALIGN_READ_P" by replacing priority logic for addr_align_read
-- ~~~~~~
-- SK 24/11/10
-- ^^^^^^^^
-- 1. Added "ns_idle" signal to reset the address counter in mem_steer.vhd
-- ~~~~~~~~
-- SK 02/11/11 version v5_02_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
-------------------------------------------------------------------------------
-- vcomponents package of the unisim library is used for the FDS, FDR and FDCE
-- component declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BANKS_MEM -- Number of Memory Banks
-- C_MAX_MEM_WIDTH -- Maximum memory width of all memory banks
-- C_MIN_MEM_WIDTH -- Minimum memory width (set to 8 bits)
-- C_IPIF_DWIDTH -- Width of IPIF data bus
-- C_ADDR_CNTR_WIDTH -- Width of address counter
-- C_GLOBAL_DATAWIDTH_MATCH -- Indicates if datawidth matching is
-- implemented in any memory bank
-- C_GLOBAL_SYNC_MEM -- Indicates if any memory bank is
-- synchronous
--
-- Definition of Ports:
-- EMC signals
-- Bus2IP_Data -- Processor Data Bus
-- Bus2IP_BE -- Processor Byte Enable
-- Bus2IP_Mem_CS -- Memory Channel Chip Select
--
-- Memory state machine signals
-- Write_req_ack -- Memory Write Acknowledge
-- Read_req_ack -- Memory Read Address Acknowledge
-- Read_ack -- Memory Read Acknowledge
-- Read_data_en -- Read Data Enable for read registers
-- Data_strobe -- Data Strobe signal
-- MSM_Mem_CEN -- Memory Chip Enable
-- MSM_Mem_OEN -- Memory Output Enable
-- MSM_Mem_WEN -- Memory Write Enable
-- Mem2Bus_WrAddrAck -- Memory Write Address Acknowledge
-- Mem2Bus_WrAck -- Memory Write Data Acknowledge
-- Mem2Bus_RdAddrAck -- Memory Read Address Acknowledge
-- Mem2Bus_RdAck -- Memory Read Data Acknowledge
-- Mem2Bus_Data -- Memory Read Data
-- Select Param signals
-- Mem_width_bytes -- Memory Device Width in Bytes
-- Synch_mem -- Synchronous Memory Control
-- Two_pipe_delay -- Synchronous pipeline stages
-- Addr counter mux signals
-- Addr_cnt -- Address Count
-- IO Register signals
-- MemSteer_Mem_DQ_I -- Memory Device Data In
-- MemSteer_Mem_DQ_O -- Memory Device Data Out
-- MemSteer_Mem_DQ_T -- Memory Device FPGA Impedance Control
-- MemSteer_Mem_DQ_prty_I -- Memory Device Parity Input
-- MemSteer_Mem_DQ_prty_O -- Memory Device Parity Output
-- MemSteer_Mem_DQ_prty_T -- Memory Device Parity Impedance Control
-- MemSteer_Mem_CEN -- Memory Device Chip Enable (Active Low)
-- MemSteer_Mem_OEN -- Memory Device Output Enable
-- MemSteer_Mem_WEN -- Memory Device Write Enable
-- MemSteer_Mem_QWEN -- Memory Device Qualified Write Enabled
-- MemSteer_Mem_BEN -- Memory Device Byte Enable
-- MemSteer_Mem_CE -- Memory Device Chip Enable (Active High)
-- MemSteer_Mem_RNW -- Memory Device Read/Write
--
-- Clock and reset
-- Clk -- System Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity mem_steer is
generic (
C_NUM_BANKS_MEM : integer;
C_MAX_MEM_WIDTH : integer;
C_MIN_MEM_WIDTH : integer;
C_IPIF_DWIDTH : integer;
C_IPIF_AWIDTH : integer;
C_PARITY_TYPE_MEMORY : integer range 0 to 1;
C_ADDR_CNTR_WIDTH : integer range 1 to 5;
C_GLOBAL_DATAWIDTH_MATCH : integer range 0 to 1;
C_GLOBAL_SYNC_MEM : integer range 0 to 1
);
port (
-- Clock and reset
Clk : in std_logic;
Rst : in std_logic;
-- EMC signals
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_Mem_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Bus2IP_RdReq : in std_logic;
Bus2IP_Burst : in std_logic;
-- Memory state machine signals
Write_req_ack : in std_logic;
Read_req_ack : in std_logic;
Read_ack : in std_logic;
Read_data_en : in std_logic;
-- Data_strobe : in std_logic;09-12-2012
MSM_Mem_CEN : in std_logic;
MSM_Mem_OEN : in std_logic;
MSM_Mem_WEN : in std_logic;
Mem2Bus_WrAddrAck : out std_logic;
Mem2Bus_WrAck : out std_logic;
Mem2Bus_RdAddrAck : out std_logic;
Mem2Bus_RdAck : out std_logic;
Mem2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH -1);
-- Select param signals
Mem_width_bytes : in std_logic_vector(0 to 3);
Synch_mem : in std_logic;
Two_pipe_delay : in std_logic;
single_transaction : in std_logic;
-- Parity logic
parity_error_mem : out std_logic_vector(0 to 1);
Parity_enable : in std_logic;
Parity_type : in std_logic;
Parity_err : out std_logic;
-- Addr counter mux signal
Addr_cnt : in std_logic_vector(0 to
C_ADDR_CNTR_WIDTH-1);
Addr_align : in std_logic;
Addr_align_rd : in std_logic;
-- IO register signals
MemSteer_Mem_DQ_I : in std_logic_vector
(0 to C_MAX_MEM_WIDTH-1);
MemSteer_Mem_DQ_O : out std_logic_vector
(0 to C_MAX_MEM_WIDTH-1);
MemSteer_Mem_DQ_T : out std_logic_vector
(0 to C_MAX_MEM_WIDTH-1);
MemSteer_Mem_DQ_prty_I : in std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_DQ_prty_O : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_DQ_prty_T : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_CEN : out std_logic_vector
(0 to C_NUM_BANKS_MEM-1);
MemSteer_Mem_OEN : out std_logic_vector
(0 to C_NUM_BANKS_MEM-1);
MemSteer_Mem_WEN : out std_logic;
MemSteer_Mem_QWEN : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_BEN : out std_logic_vector
(0 to C_MAX_MEM_WIDTH/8-1);
MemSteer_Mem_CE : out std_logic_vector
(0 to C_NUM_BANKS_MEM-1);
MemSteer_Mem_RNW : out std_logic;
Bus2IP_RdReq_emc : in std_logic;
Bus2IP_WrReq_emc : in std_logic;
Write_req_data_ack : in std_logic;
Write_req_addr_ack : in std_logic;
address_strobe_c : in std_logic;
be_strobe_c : in std_logic;
data_strobe_c : in std_logic;
ns_idle : in std_logic;
Linear_flash_rd_data_ack : in std_logic;
Linear_flash_brst_rd_flag : in std_logic;
last_addr : in std_logic; -- stop_oen
stop_oen : in std_logic;
cycle_end: in std_logic;
axi_arsize: in std_logic_vector(2 downto 0);
axi_trans_size_reg : in std_logic_vector(1 downto 0)
);
end entity mem_steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of mem_steer is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal mem_cen_cmb : std_logic;
signal mem_oen_cmb : std_logic;
signal read_ack_d : std_logic_vector(0 to 5);
signal read_parity_d : std_logic_vector(0 to 5);
signal addr_align_d : std_logic_vector(0 to 5);
signal addr_align_read : std_logic;
signal write_data : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal write_data_cmb : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal write_data_parity : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal write_data_parity_cmb : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal read_data : std_logic_vector(0 to C_IPIF_DWIDTH-1);
signal read_parity : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal write_data_d1 : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal write_data_d2 : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal write_data_parity_d1 : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal write_data_parity_d2 : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_be_i : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_t_cmb : std_logic_vector(0 to 3);
signal mem_dq_parity_t_cmb : std_logic_vector(0 to 3);
signal addr_cnt_d1 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_d2 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_d3 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_d4 : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal addr_cnt_sel : std_logic_vector(0 to C_ADDR_CNTR_WIDTH-1);
signal mem_dqt_t_d : std_logic;
signal mem_dqt_t_async : std_logic;
signal mem_dqt_parity_t_d : std_logic;
signal mem_dqt_parity_t_async : std_logic;
signal Read_req_ack_reg : std_logic;
signal readreq_th_reset : std_logic;
signal read_data_ce : std_logic_vector(0 to 7);
signal read_data_en_d : std_logic_vector(0 to 4);
signal read_data_en_sel : std_logic;
signal read_data_cmb : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal read_data_parity : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal read_data_parity_cmb : std_logic_vector(0 to C_IPIF_DWIDTH/8-1) := (OTHERS => '0');
signal read_data_parity_int : std_logic_vector(0 to C_IPIF_DWIDTH/8-1) := (OTHERS => '0');
signal Bus2IP_Mem_CS_del : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal single_par_err : std_logic;
signal single_par_err_int : std_logic;
signal Mem2Bus_RdAck_int : std_logic;
signal Parity_err_int : std_logic;
signal cmb_ored,comp_int : std_logic;
signal arsize_int,arsize_int_e,mem_bytes_int: integer range 0 to 64;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function "and" ( l : std_logic_vector; r : std_logic )
return std_logic_vector is
variable rex : std_logic_vector(l'range);
begin
rex := (others => r);
return( l and rex );
end function "and";
function calc_parity ( data_in : std_logic_vector (0 to 7);
Parity_type : std_logic
)
return std_logic is
variable parity_out_temp: std_logic;
begin
if Parity_type = '0' then
parity_out_temp := '0';
for j in 0 to 7 loop
parity_out_temp := parity_out_temp XOR data_in(j);
end loop;
elsif Parity_type = '1' then
parity_out_temp := '1';
for j in 0 to 7 loop
parity_out_temp := NOT(parity_out_temp XOR data_in(j));
end loop;
else
parity_out_temp := '0';
end if;
return parity_out_temp;
end function calc_parity;
function check_parity ( data_in : std_logic_vector (0 to 7);
parity_bit : std_logic;
Parity_type : std_logic
)
return std_logic is
variable parity_result : std_logic;
variable parity_out_temp : std_logic;
begin
if Parity_type = '0' then
parity_out_temp := '0';
for j in 0 to 7 loop
parity_out_temp := parity_out_temp XOR data_in(j);
end loop;
elsif Parity_type = '1' then
parity_out_temp := '1';
for j in 0 to 7 loop
parity_out_temp := NOT(parity_out_temp XOR data_in(j));
end loop;
else
parity_out_temp := '0';
end if;
if parity_bit= parity_out_temp then
return '0';
else
return '1';
end if;
end function check_parity;
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
signal addr_cnt_numonyx : std_logic;
--attribute IOB : string;
--attribute IOB of mem_dqt_t_d : signal is "true";
begin -- architecture imp
read_ack_d (5) <= '0';
addr_align_d (5) <= '0';
MemSteer_Mem_BEN <= not mem_be_i;
MemSteer_Mem_RNW <= MSM_Mem_WEN;
MemSteer_Mem_QWEN <= not(mem_be_i and (not MSM_Mem_WEN));
MemSteer_Mem_WEN <= MSM_Mem_WEN;
Mem2Bus_RdAck <= Mem2Bus_RdAck_int;
ADDR_CNT_SYNCH_MODE : process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
addr_cnt_numonyx <= '0';
elsif(Linear_flash_brst_rd_flag = '1') then
if(Read_ack = '1') then
addr_cnt_numonyx <= not(addr_cnt_numonyx);
end if;
end if;
end if;
end process ADDR_CNT_SYNCH_MODE;
-------------------------------------------------------------------------------
-- Memory chip enable control generation.
-------------------------------------------------------------------------------
mem_cen_cmb <= MSM_Mem_CEN;
MEM_CEN_SINGLE_BANK_GEN: if C_NUM_BANKS_MEM = 1 generate
begin
MemSteer_Mem_CEN(0) <= mem_cen_cmb; -- 10-12-2012
--CEN_P: process (stop_oen, synch_mem,mem_cen_cmb) is -- 10-12-2012
--begin
-- if(synch_mem = '1') then
-- MemSteer_Mem_CEN(0) <= mem_cen_cmb or stop_oen;
-- else
-- MemSteer_Mem_CEN(0) <= mem_cen_cmb;
-- end if;
--end process CEN_P;
MemSteer_Mem_CE(0) <= not mem_cen_cmb;
parity_error_mem <= "00";
end generate MEM_CEN_SINGLE_BANK_GEN;
-------------------------------------------------------------------------------
-- Generate chip enable signals for multiple memory banks.
-------------------------------------------------------------------------------
MEM_CEN_MULTI_BANK_GEN: if C_NUM_BANKS_MEM > 1 generate
begin
-------------------------------------------------------------------------------
-- Chip enable steer process steers the chip enable to the corresponding memory
-- bank.
-------------------------------------------------------------------------------
MEM_CEN_STEER_PROCESS: process(mem_cen_cmb, Bus2IP_Mem_CS)
begin
MemSteer_Mem_CEN <= (others => '1');
MemSteer_Mem_CE <= (others => '0');
parity_error_mem <= (others => '0');
for i in 0 to C_NUM_BANKS_MEM -1 loop
if(Bus2IP_Mem_CS(i) = '1')then
MemSteer_Mem_CEN(i) <= mem_cen_cmb;
MemSteer_Mem_CE(i) <= not mem_cen_cmb;
parity_error_mem <= conv_std_logic_vector
(i,2);
end if;
end loop;
end process MEM_CEN_STEER_PROCESS;
end generate MEM_CEN_MULTI_BANK_GEN;
-------------------------------------------------------------------------------
-- Memory output enable control generation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_MEM_OEN : if C_GLOBAL_SYNC_MEM = 1 generate
signal mem_oen_d : std_logic_vector(0 to 2);
signal mem_oen_sync : std_logic;
begin
mem_oen_d(0) <= MSM_Mem_OEN;
-------------------------------------------------------------------------------
-- FDS primitive is used for output enable pipe generation.
-------------------------------------------------------------------------------
OEN_PIPE_GEN : for i in 0 to 1 generate
begin
OEN_PIPE: FDS
port map (
Q => mem_oen_d(i+1), --[out]
C => Clk, --[in]
D => mem_oen_d(i), --[in]
S => Rst --[in]
);
end generate OEN_PIPE_GEN;
mem_oen_sync <= mem_oen_d(2) and mem_oen_d(1) when (Two_pipe_delay = '1') -- 1/3/2013
--mem_oen_d(2) when (Two_pipe_delay = '1') -- 1/3/2013
else
mem_oen_d(1) and mem_oen_d(0);
mem_oen_cmb <= mem_oen_d(0) when (Synch_mem = '0')
else
mem_oen_sync;
end generate SYNC_MEM_OEN;
-------------------------------------------------------------------------------
-- Generate output enable signals when C_GLOBAL_STNC_MEM = 0.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_MEM_OEN : if C_GLOBAL_SYNC_MEM = 0 generate
begin
mem_oen_cmb <= MSM_Mem_OEN;
end generate ASYNC_MEM_OEN;
-------------------------------------------------------------------------------
-- Generate output enable signals for multiple memory banks.
-------------------------------------------------------------------------------
MEM_OEN_SINGLE_BANK_GEN: if C_NUM_BANKS_MEM = 1 generate
begin
--OEN_P: process (stop_oen, synch_mem,mem_oen_cmb) is -- 10-12-2012
--begin
-- if(synch_mem = '1') then
-- MemSteer_Mem_OEN(0) <= mem_oen_cmb or stop_oen;
-- else
-- MemSteer_Mem_OEN(0) <= mem_oen_cmb;
-- end if;
--end process OEN_P;
MemSteer_Mem_OEN(0) <= mem_oen_cmb; -- 10-12-2012
end generate MEM_OEN_SINGLE_BANK_GEN;
-------------------------------------------------------------------------------
-- Generate output enable signals for multiple memory banks.
-------------------------------------------------------------------------------
MEM_OEN_MULTI_BANK_GEN: if C_NUM_BANKS_MEM > 1 generate
begin
-------------------------------------------------------------------------------
-- Output enable steer process is used to steer the output enable to the
-- corresponding memory bank.
-------------------------------------------------------------------------------
MEM_OEN_STEER_PROCESS: process(mem_oen_cmb, Bus2IP_Mem_CS)
begin
MemSteer_Mem_OEN <= (others => '1');
for i in 0 to C_NUM_BANKS_MEM -1 loop
if(Bus2IP_Mem_CS(i) = '1')then
MemSteer_Mem_OEN(i) <= mem_oen_cmb;
end if;
end loop;
end process MEM_OEN_STEER_PROCESS;
end generate MEM_OEN_MULTI_BANK_GEN;
-------------------------------------------------------------------------------
-- Address and Data ack generation.
-------------------------------------------------------------------------------
--Mem2Bus_WrAddrAck <= Write_req_ack and (Bus2IP_WrReq_emc or single_transaction);
--Mem2Bus_WrAck <= Write_req_ack ;
Mem2Bus_WrAddrAck <= Write_req_addr_ack and
(Bus2IP_WrReq_emc or single_transaction or last_addr);
Mem2Bus_WrAck <= Write_req_data_ack;
Mem2Bus_RdAddrAck <= Read_req_ack;-- and Bus2IP_RdReq_emc;
read_ack_d(0) <= Read_ack;
addr_align_d(0) <= Addr_align_rd;
-------------------------------------------------------------------------------
-- Geneartion of Mem2Bus_RdAck signal when external memory bank has at least
-- one synchronous memory
-------------------------------------------------------------------------------
GSYNC_MEM_RDACK_GEN : if C_GLOBAL_SYNC_MEM = 1 generate
begin
---------------------------------------------------------------------------
-- Read ack pipe generation.
---------------------------------------------------------------------------
RDACK_PIPE_GEN_SYNC : for i in 0 to 3 generate
begin
readreq_th_reset <= ((not Bus2IP_RdReq) and ( not single_transaction))
or Rst;
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
RDACK_PIPE_SYNC: FDR
port map (
Q => read_ack_d(i+1), --[out]
C => Clk, --[in]
D => read_ack_d(i), --[in]
R => readreq_th_reset --[in]
);
end generate RDACK_PIPE_GEN_SYNC;
NO_PARITY_ACK_SYNC : if (C_PARITY_TYPE_MEMORY=0) generate
Parity_err <= '0';
end generate NO_PARITY_ACK_SYNC;
PARITY_ACK_SYNC : if (C_PARITY_TYPE_MEMORY/=0) generate
---------------------------------------------------------------------------
-- ERR ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_GEN_SYNC : for i in 0 to 3 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_SYNC: FDR
port map (
Q => read_parity_d(i+1), --[out]
C => Clk, --[in]
D => read_parity_d(i), --[in]
R => Rst --[in]
);
end generate ERRACK_PIPE_GEN_SYNC;
--Parity_err_int <= read_parity_d(2) when (Synch_mem = '0') else
-- read_parity_d(3) when (Synch_mem = '1' and
-- Two_pipe_delay = '0') else
-- read_parity_d(4) when (Two_pipe_delay = '1')
--
-- else '0'; --10/25/2010
COMP_INT_S:process (clk)
begin
if clk'event and clk = '1' then
if arsize_int >= mem_bytes_int then
comp_int <= '0';
else
comp_int <= '1';
end if;
end if;
end process COMP_INT_S;
MEM2BUS_PARITY_ERR_P: process(read_parity_d(1),
read_parity_d(2),--10/25/2010
read_parity_d(3),
read_parity_d(4),
Synch_mem,
comp_int,
Two_pipe_delay) is
variable parity_sync_mem_pipe_delay: std_logic_vector(2 downto 0);
begin
parity_sync_mem_pipe_delay := comp_int & Synch_mem & Two_pipe_delay;
case parity_sync_mem_pipe_delay is
when "000" => Parity_err_int <= read_parity_d(2); -- async mem
when "001" => Parity_err_int <= read_parity_d(2); -- async mem
when "010" => Parity_err_int <= read_parity_d(2); -- and read_ack_d(3);--(3); -- sync mem + pipe delay
when "011" => Parity_err_int <= read_parity_d(4); -- sync mem + pipe delay 2
when "100" => Parity_err_int <= read_parity_d(1); -- async mem
when "101" => Parity_err_int <= read_parity_d(1); -- async mem
when "110" => Parity_err_int <= read_parity_d(1); -- and read_ack_d(3);--(3); -- sync mem + pipe delay
when "111" => Parity_err_int <= read_parity_d(3); -- sync mem + pipe delay 2
-- coverage off
when others => Parity_err_int <= '0';
-- coverage on
end case;
end process MEM2BUS_PARITY_ERR_P;
arsize_int_e <= conv_integer(axi_arsize);
PARITY_CALC_32 : if (C_IPIF_DWIDTH = 32) generate
SIZE_SYN_32: process(CLK)
begin
if (clk'event and clk = '1') then
case axi_arsize is
when "000" =>
cmb_ored <= read_data_parity_cmb(0);
when "001" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 1));
when "010" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 3));
when OTHERS =>
cmb_ored <= read_data_parity_cmb(0);
end case;
end if;
end process SIZE_SYN_32;
end generate PARITY_CALC_32;
PARITY_CALC_64 : if (C_IPIF_DWIDTH = 64) generate
SIZE_SYN_64: process(CLK)
begin
if (clk'event and clk = '1') then
case axi_arsize is
when "000" =>
cmb_ored <= read_data_parity_cmb(0);
when "001" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 1));
when "010" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 3));
when "011" =>
cmb_ored <= or_reduce(read_data_parity_cmb(0 to 7));
when OTHERS =>
cmb_ored <= read_data_parity_cmb(0);
end case;
end if;
end process SIZE_SYN_64;
end generate PARITY_CALC_64;
--SIZE_CONV: process(arsize_int)
--begin
-- case arsize_int is
-- when 0 =>
-- arsize_bytes <= 1;
-- when 1 =>
-- arsize_bytes <= 2;
-- when 2 =>
-- arsize_bytes <= 4;
-- when 3 =>
-- arsize_bytes <= 8;
-- when 4 =>
-- arsize_bytes <= 16;
-- when 5 =>
-- arsize_bytes <= 32;
-- when 6 =>
-- arsize_bytes <= 64;
-- when OTHERS =>
-- arsize_bytes <= 1;
-- end case;
--end process SIZE_CONV;
INT_CONV_SIZE: process(arsize_int_e)
begin
case arsize_int_e is
when 0 =>
arsize_int <= 1;
when 1 =>
arsize_int <= 2;
when 2 =>
arsize_int <= 4;
when 3 =>
arsize_int <= 8;
when OTHERS =>
arsize_int <= 1;
end case;
end process INT_CONV_SIZE;
INT_CONV: process(Mem_width_bytes)
begin
case Mem_width_bytes is
when "0001" =>
mem_bytes_int <= 1;
when "0010" =>
mem_bytes_int <= 2;
when "0100" =>
mem_bytes_int <= 4;
when "1000" =>
mem_bytes_int <= 8;
when OTHERS =>
mem_bytes_int <= 1;
end case;
end process INT_CONV;
-------------------------
--process (read_data_parity_cmb)
--begin
-- for i in 0 to arsize_int loop
-- read_data_parity_int(i) <= read_data_parity_cmb(i);
-- end loop;
--end process;
process (Clk)
begin
if (clk'event and clk = '1') then
if (Rst = '1') then
single_par_err <= '0';
else
if (arsize_int >= mem_bytes_int) then
single_par_err <= or_reduce(read_data_parity_cmb) and single_transaction;
else
--single_par_err <= or_reduce(read_data_parity_cmb(0 to arsize_int)) and single_transaction;
single_par_err <= cmb_ored;
end if;
end if;
end if;
end process;
process (Clk)
begin
if (clk'event and clk = '1') then
if (Rst = '1') then
single_par_err_int <= '0';
else
single_par_err_int <= Mem2Bus_RdAck_int and single_par_err;
end if;
end if;
end process;
Parity_err <= Parity_err_int or single_par_err_int;
---------------------------
--read_parity_d(0) <= -- or_reduce(read_data_parity_cmb) and Read_ack;
-- (or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq) -- read_ack_d(3))
-- when Two_pipe_delay = '0'
-- else
-- (or_reduce(read_data_parity_cmb) and read_ack_d(4));
--read_parity_d(0) <=
-- (or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq) when Two_pipe_delay = '0' else (or_reduce(read_data_parity_cmb) and read_ack_d(4))
-- when arsize_int >= mem_bytes_int else
-- ((cmb_ored) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq)) when Two_pipe_delay = '0' else ((cmb_ored) and read_ack_d(4));
read_parity_d(0) <=
(or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq) when arsize_int >= mem_bytes_int else ((cmb_ored) and (or_reduce(read_data_ce)) and (Read_ack))
when Two_pipe_delay = '0' else
(or_reduce(read_data_parity_cmb) and read_ack_d(4)) when arsize_int >= mem_bytes_int else ((cmb_ored) and read_ack_d(4));
--process (read_data_ce,
-- read_data_parity_cmb,
-- Bus2IP_RdReq,
-- read_ack_d,
-- Two_pipe_delay,
-- read_data_parity_int
-- )
--begin
-- if (arsize_int >= mem_bytes_int) then
-- if (Two_pipe_delay = '0') then
-- read_parity_d(0) <= (or_reduce(read_data_parity_cmb)) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq); -- read_ack_d(3))
-- else
-- read_parity_d(0) <= (or_reduce(read_data_parity_cmb) and read_ack_d(4));
-- end if;
-- else
-- if (Two_pipe_delay = '0') then
-- read_parity_d(0) <= (cmb_ored) and (or_reduce(read_data_ce)) and (Bus2IP_RdReq); -- read_ack_d(3))
-- else
-- read_parity_d(0) <= (cmb_ored) and read_ack_d(4);
-- end if;
-- end if;
--end process;
end generate PARITY_ACK_SYNC;
--Mem2Bus_RdAck <= -- read_ack_d(2) when (Synch_mem = '0') else
-- read_ack_d(3) when (Synch_mem = '1' and
-- Two_pipe_delay = '0') else
-- read_ack_d(4) when (Two_pipe_delay = '1')
-- else '0'; -- 10/25/2010
MEM2BUS_RD_ACK_P: process(read_ack_d(2), -- 10/25/2010
read_ack_d(3),
read_ack_d(4),
Synch_mem,
addr_cnt_numonyx,
Read_ack,
Linear_flash_brst_rd_flag,
Two_pipe_delay) is
variable sync_mem_pipe_delay: std_logic_vector(1 downto 0);
begin
sync_mem_pipe_delay := Synch_mem & Two_pipe_delay;
case sync_mem_pipe_delay is
when "00" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(2);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
when "01" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(2);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
when "10" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(3);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
when "11" => if (Linear_flash_brst_rd_flag = '0') then
Mem2Bus_RdAck_int <= read_ack_d(4);
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
-- coverage off
when others => Mem2Bus_RdAck_int <= '0';
-- coverage on
end case;
end process MEM2BUS_RD_ACK_P;
ADDR_ALIGN_PIPE_GEN : for i in 0 to 3 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for Address align pipe generation.
---------------------------------------------------------------------------
ALIGN_PIPE: FDR
port map (
Q => addr_align_d(i+1), --[out]
C => Clk, --[in]
D => addr_align_d(i), --[in]
R => Rst --[in]
);
end generate ADDR_ALIGN_PIPE_GEN;
--addr_align_read <= addr_align_d(0)when Synch_mem = '0'
-- else
-- addr_align_d(1) when Synch_mem = '1' and Two_pipe_delay = '0'
-- else
-- addr_align_d(2);--10/25/2010
ADDR_ALIGN_READ_P: process(addr_align_d(0), -- 10/25/2010
addr_align_d(1),
addr_align_d(2),
Synch_mem,
Two_pipe_delay) is
variable addr_align_syn_pipe_dly: std_logic_vector(1 downto 0);
begin
addr_align_syn_pipe_dly := Synch_mem & Two_pipe_delay;
case addr_align_syn_pipe_dly is
when "00" => addr_align_read <= addr_align_d(0);
when "01" => addr_align_read <= addr_align_d(0);
when "10" => addr_align_read <= addr_align_d(1);
when "11" => addr_align_read <= addr_align_d(2);
-- coverage off
when others => addr_align_read <=addr_align_d(2);
-- coverage on
end case;
end process ADDR_ALIGN_READ_P;
------------------------------
end generate GSYNC_MEM_RDACK_GEN;
-------------------------------------------------------------------------------
-- Geneartion of Mem2Bus_RdAck signal when external memory bank has only
-- asynchronous memory
-------------------------------------------------------------------------------
ASYNC_MEM_RDACK_GEN : if (C_GLOBAL_SYNC_MEM = 0) generate
begin
---------------------------------------------------------------------------
-- Read ack pipe generation.
---------------------------------------------------------------------------
RDACK_PIPE_GEN_ASYNC : for i in 0 to 1 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
readreq_th_reset <= ((not Bus2IP_RdReq) and ( not single_transaction))
or Rst;
RDACK_PIPE_ASYNC: FDR
port map (
Q => read_ack_d(i+1), --[out]
C => Clk, --[in]
D => read_ack_d(i), --[in]
R => readreq_th_reset --[in]
);
end generate RDACK_PIPE_GEN_ASYNC;
NO_ASYN_PARITY_ACK_SYNC : if (C_PARITY_TYPE_MEMORY=0) generate
Parity_err <= '0';
end generate NO_ASYN_PARITY_ACK_SYNC;
PARITY_ACK : if (C_PARITY_TYPE_MEMORY/=0) generate
---------------------------------------------------------------------------
-- ERR ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_GEN_ASYNC : for i in 0 to 1 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for read data ack pipe generation.
---------------------------------------------------------------------------
ERRACK_PIPE_ASYNC: FDR
port map (
Q => read_parity_d(i+1), --[out]
C => Clk, --[in]
D => read_parity_d(i), --[in]
R => Rst --[in]
);
end generate ERRACK_PIPE_GEN_ASYNC;
Parity_err <= read_parity_d(2);
end generate PARITY_ACK;
-- Mem2Bus_RdAck <= read_ack_d(2) when (Linear_flash_brst_rd_flag = '0') else (addr_cnt_numonyx and Read_ack) ;
ASYNC_MEM_MEM2BUS_RDACK_P: process(read_ack_d(2),
Linear_flash_brst_rd_flag,
cycle_end,
Read_ack,
axi_trans_size_reg,
addr_cnt_numonyx )is
begin
if(Linear_flash_brst_rd_flag = '0')then
Mem2Bus_RdAck_int <= read_ack_d(2);
else
if(axi_trans_size_reg(1) = '0')then -- half word access
Mem2Bus_RdAck_int <= cycle_end and Read_ack;
else
Mem2Bus_RdAck_int <= addr_cnt_numonyx and Read_ack;
end if;
end if;
end process ASYNC_MEM_MEM2BUS_RDACK_P;
---------------------------------------------------------------------------
-- ADDR ALLIGN pipe generation.
---------------------------------------------------------------------------
AALIGN_PIPE_GEN : for i in 0 to 1 generate
begin
---------------------------------------------------------------------------
-- FDR primitive is used for Address align pipe generation.
---------------------------------------------------------------------------
AALIGN_PIPE: FDR
port map (
Q => addr_align_d(i+1), --[out]
C => Clk, --[in]
D => addr_align_d(i), --[in]
R => Rst --[in]
);
end generate AALIGN_PIPE_GEN;
addr_align_read <= addr_align_d(0);
end generate ASYNC_MEM_RDACK_GEN;
-------------------------------------------------------------------------------
-- Store the data coming from bus, as address ack and data ack is issued early,
-- and to make burst appear as continuous on memory side.
-------------------------------------------------------------------------------
DATA_STORE_GEN: for i in 0 to C_IPIF_DWIDTH - 1 generate
begin
-------------------------------------------------------------------------------
-- FDCE primitive is used for latching Bus2IP_Data when Data_strobe = 1.
-------------------------------------------------------------------------------
WRDATA_REG: FDRE
port map (
Q => write_data(i), --[out]
C => Clk, --[in]
CE => data_strobe_c,--Data_strobe, --[in]
D => Bus2IP_Data(i), --[in]
R => Rst --[in]
);
end generate DATA_STORE_GEN;
-------------------------------------------------------------------------------
-- When one of the memory bank has different data width than OPB/MCH data
-- width, data steering logic is required.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 1 ------------------------
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 1 generate
begin
-------------------------------------------------------------------------------
-- Write data path
-------------------------------------------------------------------------------
-- Write data mux is used to multiplex write_data out to memories. This will
-- vary on whether the max memory data width is 8, 16, 32 or 64. Separate
-- generate statements are used for each of them. If the memory is synchronous,
-- the BEs assert at the same time. However, the write data goes out one or
-- two clocks later (depending on Two_pipe_delay). Therefore, separate
-- processes are used for the write data and byte enables.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_64_GEN: if (C_MAX_MEM_WIDTH=64 and C_IPIF_DWIDTH=64) generate
begin
-------------------------------------------------------------------------------
-- Write data path for 64 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_64: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
write_data_parity_cmb <= (others => '0');
case Mem_width_bytes is
when "0001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "0010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 2*C_MIN_MEM_WIDTH-1) <=
write_data(i*2*C_MIN_MEM_WIDTH to
i*2*C_MIN_MEM_WIDTH + 2*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "0100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 4*C_MIN_MEM_WIDTH-1) <=
write_data(i*4*C_MIN_MEM_WIDTH to
i*4*C_MIN_MEM_WIDTH + 4*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "1000" =>
if Addr_cnt = conv_std_logic_vector(0, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MAX_MEM_WIDTH-1) <=
write_data(0 to C_MAX_MEM_WIDTH-1);
end if;
when others =>
write_data_cmb <= (others => '0');
end case;
end process WRITE_DATA_MUX_PROCESS_64;
-------------------------------------------------------------------------------
-- Write data path for 64 bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_64: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
case Mem_width_bytes is
when "0001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "0010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 2*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*2*C_MIN_MEM_WIDTH/8 to
i*2*C_MIN_MEM_WIDTH/8 + 2*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "0100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 4*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*4*C_MIN_MEM_WIDTH/8 to
i*4*C_MIN_MEM_WIDTH/8 + 4*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "1000" =>
if Addr_cnt = conv_std_logic_vector(0, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH-1) <=
Bus2IP_BE(0 to C_MIN_MEM_WIDTH-1);
end if;
when others =>
mem_be_i <= (others => '0');
end case;
end process WRITE_BE_MUX_PROCESS_64;
WRITE_PARITY_EN_64_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
--
-- WRITE_PARITY_MUX_PROCESS_64: process(Parity_type,
-- Addr_cnt,
-- write_data)
-- begin
--
-- write_data_parity_cmb <= (others => '0');
--
-- for i in 0 to 7 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb (i)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
--
--
-- end process WRITE_PARITY_MUX_PROCESS_64;
WRITE_DATA_PARITY_PROCESS_64: process(Mem_width_bytes,
Addr_cnt,
write_data_parity_cmb,
Parity_type,
write_data,
write_data_cmb
) is
begin
write_data_parity_cmb <= (others => '0');
--------------
case Mem_width_bytes is
when "0001" => -- 8 bit memory (need only one Parity Enable bit to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(0) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
write_data_parity_cmb(0) <= calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);
when "0010" => -- 16 bit memory (need only two Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
for i in 0 to 1 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
when "0100" => -- 32 bit memory (need four Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
for i in 0 to 3 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
when "1000" => -- 64 bit memory (need eight Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
--end loop;
for i in 0 to 7 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
-- coverage off
when others =>
write_data_parity_cmb <= (others => '0');
-- coverage on
end case;
--------------
end process WRITE_DATA_PARITY_PROCESS_64;
end generate WRITE_PARITY_EN_64_MAX;
end generate WRITE_DATABE_MUX_64_GEN;
-------------------------------------------------------------------------------
-- Write data path
-------------------------------------------------------------------------------
-- Write data mux is used to multiplex write_data out to memories. This will
-- vary on whether the max memory data width is 8, 16, 32 or 64. Separate
-- generate statements are used for each of them. If the memory is synchronous,
-- the BEs assert at the same time. However, the write data goes out one or
-- two clocks later (depending on Two_pipe_delay). Therefore, separate
-- processes are used for the write data and byte enables.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Write data byte enable generation for 32 bit.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_32_GEN: if (C_MAX_MEM_WIDTH=32) generate
begin
-------------------------------------------------------------------------------
-- Write data path for 32 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_32: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 2*C_MIN_MEM_WIDTH-1) <=
write_data(i*2*C_MIN_MEM_WIDTH to
i*2*C_MIN_MEM_WIDTH + 2*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 4*C_MIN_MEM_WIDTH-1) <=
write_data(i*4*C_MIN_MEM_WIDTH to
i*4*C_MIN_MEM_WIDTH + 4*C_MIN_MEM_WIDTH-1);
end if;
end loop;
when others =>
write_data_cmb <= (others => '0');
end case;
end process WRITE_DATA_MUX_PROCESS_32;
-------------------------------------------------------------------------------
-- Write data path for 32 Bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_32: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "010" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 2*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*2*C_MIN_MEM_WIDTH/8 to
i*2*C_MIN_MEM_WIDTH/8 + 2*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "100" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 4*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*4*C_MIN_MEM_WIDTH/8 to
i*4*C_MIN_MEM_WIDTH/8 + 4*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when others =>
mem_be_i <= (others => '0');
end case;
end process WRITE_BE_MUX_PROCESS_32;
-----------------------------------**--
WRITE_PARITY_EN_32_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
--
-- WRITE_PARITY_MUX_PROCESS_32: process(Parity_type, Addr_cnt, write_data)
-- begin
--
-- write_data_parity_cmb <= (others => '0');
-- ----------
-- for i in 0 to 3 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb (i)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
-- ----------
-- end process WRITE_PARITY_MUX_PROCESS_32;
-- WRITE_DATA_PARITY_PROCESS_32: process(Mem_width_bytes,
-- Addr_cnt,
-- write_data_parity_cmb,
-- Parity_type
-- ) is
-- begin
-- write_data_parity_cmb <= (others => '0');
-- --------------
-- case Mem_width_bytes(1 to 3) is
-- when "001" => -- 8 bit memory (need only one Parity Enable bit to active)
-- for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(0) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
--
-- when "010" => -- 16 bit memory (need only two Parity Enable bits to active)
-- for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
-- when "100" => -- 32 bit memory (need four Parity Enable bits to active)
-- for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
-- -- coverage off
-- when others =>
-- write_data_parity_cmb <= (others => '0');
-- -- coverage on
-- end case;
-- --------------
-- end process WRITE_DATA_PARITY_PROCESS_32;
WRITE_DATA_PARITY_PROCESS_32: process(Mem_width_bytes,
Addr_cnt,
write_data_cmb,
Parity_type,
write_data
) is
-----
begin
-----
write_data_parity_cmb <= (others => '0');
--------------
case Mem_width_bytes(1 to 3) is
------------
when "001" => -- 8 bit memory (need only one Parity Enable bit to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- for j in 0 to 1 loop
-- write_data_parity_cmb(0) <=
-- calc_parity(write_data((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
-- end loop;
--end if;
--end loop;
write_data_parity_cmb(0) <= calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);
------------
when "010" => -- 16 bit memory (need only two Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- for j in 0 to 1 loop
-- write_data_parity_cmb(j) <=
-- calc_parity(write_data((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
--
-- end loop;
-- end if;
--end loop;
for i in 0 to 1 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
------------
when "100" => -- 32 bit memory (need four Parity Enable bits to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH) -1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- --for j in 0 to 3 loop
-- write_data_parity_cmb(i) <=
-- calc_parity(write_data((i*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
--
-- --end loop;
-- end if;
--end loop;
for i in 0 to 3 loop
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
------------
-- coverage off
when others =>
write_data_parity_cmb <= (others => '0');
-- coverage on
------------
end case;
--------------
end process WRITE_DATA_PARITY_PROCESS_32;
--------------------------------------
end generate WRITE_PARITY_EN_32_MAX;
-----------------------------------**--
end generate WRITE_DATABE_MUX_32_GEN;
-------------------------------------------------------------------------------
-- Write data byte enable generation for 16 bit.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_16_GEN: if C_MAX_MEM_WIDTH=16 generate
begin
-------------------------------------------------------------------------------
-- Write data path for 16 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_16: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
--------------
case Mem_width_bytes(2 to 3) is
when "01" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
when "10" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to 2*C_MIN_MEM_WIDTH-1) <=
write_data(i*2*C_MIN_MEM_WIDTH to
i*2*C_MIN_MEM_WIDTH + 2*C_MIN_MEM_WIDTH-1);
end if;
end loop;
-- coverage off
when others =>
write_data_cmb <= (others => '0');
-- coverage on
end case;
--------------
end process WRITE_DATA_MUX_PROCESS_16;
-------------------------------------------------------------------------------
-- Write data path for 16 bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_16: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
case Mem_width_bytes(2 to 3) is
when "01" =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
when "10" =>
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to 2*C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*2*C_MIN_MEM_WIDTH/8 to
i*2*C_MIN_MEM_WIDTH/8 + 2*C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
-- coverage off
when others =>
mem_be_i <= (others => '0');
-- coverage on
end case;
end process WRITE_BE_MUX_PROCESS_16;
WRITE_PARITY_EN_16_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
-- WRITE_PARITY_MUX_PROCESS_16: process(Parity_type, Addr_cnt, write_data)
-- begin
--
-- write_data_parity_cmb <= (others => '0');
-- --------------------
-- for i in 0 to 1 loop
-- if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
-- write_data_parity_cmb (i)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end if;
-- end loop;
---- ------------------
-- end process WRITE_PARITY_MUX_PROCESS_16;
WRITE_DATA_PARITY_PROCESS_16: process(Mem_width_bytes,
Addr_cnt,
write_data_cmb,
Parity_type,
write_data
) is
begin
write_data_parity_cmb <= (others => '0');
--------------
case Mem_width_bytes(2 to 3) is
------------
when "01" => -- 8 bit memory (need only one Parity Enable bit to active)
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
--if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
--for j in 0 to 1 loop
write_data_parity_cmb(0) <=
--calc_parity(write_data_cmb((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);
--end loop;
--end if;
--end loop;
------------
when "10" => -- 16 bit memory (need only two Parity Enable bits to active)
for i in 0 to 1 loop
--if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
--for j in 0 to 1 loop
--write_data_parity_cmb(j) <=
--calc_parity(write_data_cmb((i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH) to
-- (i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1)),
-- Parity_type);
--end loop;
write_data_parity_cmb (i)<=
calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
--end if;
end loop;
------------
-- coverage off
when others =>
write_data_parity_cmb <= (others => '0');
-- coverage on
------------
end case;
--------------
end process WRITE_DATA_PARITY_PROCESS_16;
-- for j in 0 to 1 loop
-- write_data_parity_cmb(j)<=
-- calc_parity(write_data(i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH*2 + j*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
-- end loop;
end generate WRITE_PARITY_EN_16_MAX;
end generate WRITE_DATABE_MUX_16_GEN;
-------------------------------------------------------------------------------
-- Write data byte enable generation for 8 bit.
-------------------------------------------------------------------------------
WRITE_DATABE_MUX_8_GEN: if C_MAX_MEM_WIDTH=8 generate
begin
-------------------------------------------------------------------------------
-- Write data path for 8 bit maximum memory width. Write data mux process is
-- used to multiplex the write_data depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_DATA_MUX_PROCESS_8: process(Mem_width_bytes, Addr_cnt, write_data)
begin
write_data_cmb <= (others => '0');
--------------
case Mem_width_bytes(3) is
when '1' =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_cmb(0 to C_MIN_MEM_WIDTH-1) <=
write_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1);
end if;
end loop;
-- coverage off
when others =>
write_data_cmb <= (others => '0');
-- coverage on
end case;
---------------
end process WRITE_DATA_MUX_PROCESS_8;
-------------------------------------------------------------------------------
-- Write data path for 8 bit maximum memory width. Write byte enable mux
-- process is used to multiplex the byte enable depending on the addr_cnt.
-------------------------------------------------------------------------------
WRITE_BE_MUX_PROCESS_8: process(Mem_width_bytes, Addr_cnt, Bus2IP_BE)
begin
mem_be_i <= (others => '0');
--------------------------
case Mem_width_bytes(3) is
when '1' =>
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
mem_be_i(0 to C_MIN_MEM_WIDTH/8-1) <=
Bus2IP_BE(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8 + C_MIN_MEM_WIDTH/8-1);
end if;
end loop;
-- coverage off
when others =>
mem_be_i <= (others => '0');
-- coverage on
end case;
--------------------------
end process WRITE_BE_MUX_PROCESS_8;
WRITE_PARITY_EN_8_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
WRITE_PARITY_MUX_PROCESS_8: process(Parity_type,
Addr_cnt,
write_data_parity_cmb,
write_data_cmb
) is
begin
write_data_parity_cmb <= (others => '0');
--for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
--if Addr_cnt = conv_std_logic_vector(i, C_ADDR_CNTR_WIDTH) then
write_data_parity_cmb (0) <=
calc_parity(write_data_cmb(0 to C_MIN_MEM_WIDTH-1),Parity_type);--(i*C_MIN_MEM_WIDTH to
-- i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
-- Parity_type);
--end if;
--end loop;
end process WRITE_PARITY_MUX_PROCESS_8;
end generate WRITE_PARITY_EN_8_MAX;
end generate WRITE_DATABE_MUX_8_GEN;
end generate WRITE_DATABE_MUX_GEN;
-------------------------------------------------------------------------------
-- When all the memory banks has same data width as OPB/MCH data width,
-- data steering logic is not required.
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 0 ------------------------
-------------------------------------------------------------------------------
WRITE_DATABE_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
begin
write_data_cmb <= write_data(0 to C_MAX_MEM_WIDTH-1);
mem_be_i <= Bus2IP_BE(0 to C_MAX_MEM_WIDTH/8-1);
---------**--
WRITE_PARITY_EN : if (C_PARITY_TYPE_MEMORY/=0) generate
begin
WRITE_PARITY: process(Parity_type,
write_data_cmb
) is
begin
for i in 0 to C_MAX_MEM_WIDTH/8 -1 loop
write_data_parity_cmb (i)<= calc_parity(write_data_cmb(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
Parity_type);
end loop;
end process WRITE_PARITY;
end generate WRITE_PARITY_EN;
---------**--
end generate WRITE_DATABE_GEN;
-------------------------------------------------------------------------------
-- Write data generation for synchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_MEM_WRITE_DATA : if C_GLOBAL_SYNC_MEM = 1 generate
begin
-------------------------------------------------------------------------------
-- Write data pipeline process is used to pipeline write_data_cmb.
-------------------------------------------------------------------------------
WRITE_DATA_PIPE_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
write_data_d1 <= (others => '0');
write_data_d2 <= (others => '0');
Read_req_ack_reg <= '0';
else
write_data_d1 <= write_data_cmb;
write_data_d2 <= write_data_d1;
Read_req_ack_reg <= Read_req_ack;
end if;
end if;
end process WRITE_DATA_PIPE_PROCESS;
-- PARITY_GEN: if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
-- begin
---------------------------------------------------------------------------
-- Write Parity pipeline process is used to pipeline write_data_cmb
---------------------------------------------------------------------------
WRITE_PARITY_PIPE_PROCESS : process(Clk)
begin
if(Clk'EVENT and Clk = '1')then
if(Rst = '1')then
write_data_parity_d1 <= (others => '0');
write_data_parity_d2 <= (others => '0');
else
write_data_parity_d1 <= write_data_parity_cmb;
write_data_parity_d2 <= write_data_parity_d1;
end if;
end if;
end process WRITE_PARITY_PIPE_PROCESS;
-- end generate PARITY_GEN;
-------------------------------------------------------------------------------
-- Write data process is used to multiplex the write data on the memory
-- depending on the type of memory.
-------------------------------------------------------------------------------
WRITE_DATA_PROCESS: process(write_data_cmb, Synch_mem, Two_pipe_delay,
write_data_parity_cmb, write_data_parity_d2,
write_data_parity_d1, write_data_d1,
write_data_d2)
begin
if Synch_mem = '1' then
if Two_pipe_delay = '1' then
MemSteer_Mem_DQ_O <= write_data_d2;
MemSteer_Mem_DQ_prty_O <= write_data_parity_d2;
else
MemSteer_Mem_DQ_O <= write_data_d1;
MemSteer_Mem_DQ_prty_O <= write_data_parity_d1;
end if;
else
MemSteer_Mem_DQ_O <= write_data_cmb;
MemSteer_Mem_DQ_prty_O <= write_data_parity_cmb;
end if;
end process WRITE_DATA_PROCESS;
end generate SYNC_MEM_WRITE_DATA;
-------------------------------------------------------------------------------
-- Memory write data generation for asynchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_MEM_WRITE_DATA : if C_GLOBAL_SYNC_MEM = 0 generate
begin
MemSteer_Mem_DQ_O <= write_data_cmb;
MemSteer_Mem_DQ_prty_O <= write_data_parity_cmb;
end generate ASYNC_MEM_WRITE_DATA;
-------------------------------------------------------------------------------
-- Memory data bus high impedance buffer control.
-------------------------------------------------------------------------------
mem_dq_t_cmb(0) <= MSM_Mem_WEN;
mem_dqt_t_async <= MSM_Mem_WEN and mem_dqt_t_d;
ASYNC_PARITY_MEM_WRITE: if C_PARITY_TYPE_MEMORY /= 0 generate
begin
mem_dq_parity_t_cmb(0) <= MSM_Mem_WEN;
mem_dqt_parity_t_async <= MSM_Mem_WEN and mem_dqt_parity_t_d;
end generate ASYNC_PARITY_MEM_WRITE;
-------------------------------------------------------------------------------
-- Asynchronous memory DQT process is used to generate impedance control
-- signal.
-------------------------------------------------------------------------------
MEM_DQT_D_ASYNC_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
mem_dqt_t_d <= '1';
mem_dqt_parity_t_d <= '1';
else
mem_dqt_t_d <= MSM_Mem_WEN;
mem_dqt_parity_t_d <= MSM_Mem_WEN;
end if;
end if;
end process MEM_DQT_D_ASYNC_PROCESS;
-------------------------------------------------------------------------------
-- Impedance generation for synchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_MEM_DQT : if C_GLOBAL_SYNC_MEM = 1 generate
begin
REG_DQT_GEN : for i in 0 to 2 generate
begin
-------------------------------------------------------------------------------
-- FDS primitive is used for mem_dq_t_cmb pipe generation.
-------------------------------------------------------------------------------
DQT_REG: FDS
port map (
Q => mem_dq_t_cmb(i+1), --[out]
C => Clk, --[in]
D => mem_dq_t_cmb(i), --[in]
S => Rst --[in]
);
end generate REG_DQT_GEN;
-------------------------------------------------------------------------------
-- Memory dqt process is used to multiplex the impeadance control signal on to
-- the memory depending on the type of memory.
-------------------------------------------------------------------------------
MEM_DQT_PROCESS_SYNC: process(Synch_mem, Two_pipe_delay, mem_dq_t_cmb,
mem_dqt_t_async)
begin
MemSteer_Mem_DQ_T <= (others => '1');
for i in 0 to C_MAX_MEM_WIDTH-1 loop
if(Synch_mem = '1')then
if(Two_pipe_delay = '1')then
MemSteer_Mem_DQ_T(i) <= mem_dq_t_cmb(2);
else
MemSteer_Mem_DQ_T(i) <= mem_dq_t_cmb(1);
end if;
else
MemSteer_Mem_DQ_T(i) <= mem_dqt_t_async;
end if;
end loop;
end process MEM_DQT_PROCESS_SYNC;
SYNC_PARITY_MEM_WRITE_DQT: if C_PARITY_TYPE_MEMORY /= 0 generate
begin
REG_DQT_PARITY_GEN : for i in 0 to 2 generate
begin
-------------------------------------------------------------------------------
-- FDS primitive is used for mem_dq_t_cmb pipe generation.
-------------------------------------------------------------------------------
DQT_REG: FDS
port map (
Q => mem_dq_parity_t_cmb(i+1), --[out]
C => Clk, --[in]
D => mem_dq_parity_t_cmb(i), --[in]
S => Rst --[in]
);
end generate REG_DQT_PARITY_GEN;
-------------------------------------------------------------------------------
-- Memory dqt process is used to multiplex the impeadance control signal on to
-- the memory depending on the type of memory.
-------------------------------------------------------------------------------
MEM_DQT_PARITY_PROCESS_SYNC: process(Synch_mem,
Two_pipe_delay,
mem_dq_parity_t_cmb,
mem_dqt_parity_t_async
) is
begin
MemSteer_Mem_DQ_prty_T <= (others => '1');
for i in 0 to C_MAX_MEM_WIDTH/8-1 loop
if(Synch_mem = '1')then
if(Two_pipe_delay = '1')then
MemSteer_Mem_DQ_prty_T(i) <= mem_dq_parity_t_cmb(2);
else
MemSteer_Mem_DQ_prty_T(i) <= mem_dq_parity_t_cmb(1);
end if;
else
MemSteer_Mem_DQ_prty_T(i) <= mem_dqt_parity_t_async;
end if;
end loop;
end process MEM_DQT_PARITY_PROCESS_SYNC;
end generate SYNC_PARITY_MEM_WRITE_DQT;
end generate SYNC_MEM_DQT;
-------------------------------------------------------------------------------
-- Impedance generation for asynchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_MEM_DQT : if C_GLOBAL_SYNC_MEM = 0 generate
begin
-------------------------------------------------------------------------------
-- Memory dqt process is used to generate impeadance control signal on to
-- the memory.
-------------------------------------------------------------------------------
MEM_DQT_PROCESS_ASYNC: process(mem_dqt_t_async)
begin
for i in 0 to C_MAX_MEM_WIDTH-1 loop
MemSteer_Mem_DQ_T(i) <= mem_dqt_t_async;
end loop;
end process MEM_DQT_PROCESS_ASYNC;
-------------------------------------------------------------------------------
-- Memory PARITY dqt process is used to generate impeadance control signal on
-- to the memory.
-------------------------------------------------------------------------------
ASYNC_PARITY_MEM_WRITE_DQT: if C_PARITY_TYPE_MEMORY /= 0 generate
begin
MEM_PARITY_DQT_PROCESS_ASYNC: process(mem_dqt_parity_t_async)
begin
for i in 0 to C_MAX_MEM_WIDTH/8-1 loop
MemSteer_Mem_DQ_prty_T(i) <= mem_dqt_parity_t_async;
end loop;
end process MEM_PARITY_DQT_PROCESS_ASYNC;
end generate ASYNC_PARITY_MEM_WRITE_DQT;
end generate ASYNC_MEM_DQT;
-------------------------------------------------------------------------------
-- Read data path.
-- Read data and byte enable generation.
-------------------------------------------------------------------------------
RDDATA_GEN: for j in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH - 1 generate
begin
RDDATA_BYTE_GEN:for i in 0 to C_MIN_MEM_WIDTH - 1 generate
begin
-------------------------------------------------------------------------------
-- FDCE primitive is used for latching read_data when read_data_ce = 1.
-------------------------------------------------------------------------------
RDDATA_REG: FDRE
port map (
Q => Mem2Bus_Data(C_MIN_MEM_WIDTH*j+i), --[out]
C => Clk, --[in]
CE => read_data_ce(j), --[in]
D => read_data(C_MIN_MEM_WIDTH*j+i), --[in]
R => RST --[in]
);
end generate RDDATA_BYTE_GEN;
end generate RDDATA_GEN;
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 0 ------------------------
-------------------------------------------------------------------------------
RDDATA_PATH_GEN : if C_GLOBAL_DATAWIDTH_MATCH = 0 generate
begin
read_data <= MemSteer_Mem_DQ_I;
read_data_ce <= (others=>'1');
READ_PARITY_EN : if (C_PARITY_TYPE_MEMORY/=0) generate
begin
READ_PARITY: process(MemSteer_Mem_DQ_I,
Parity_type,
read_ack_d,
MemSteer_Mem_DQ_prty_I
) is
begin
-- default assignment
--read_parity <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to C_MAX_MEM_WIDTH/8 -1 loop
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY;
end generate READ_PARITY_EN;
end generate RDDATA_PATH_GEN;
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_DATAWIDTH_MATCH = 1 ------------------------
-------------------------------------------------------------------------------
RDDATA_PATH_MUX_GEN : if C_GLOBAL_DATAWIDTH_MATCH = 1 generate
begin
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 1 -------------------------------
-------------------------------------------------------------------------------
SYNC_ADDR_CNT_GEN: if C_GLOBAL_SYNC_MEM = 1 generate
begin
-------------------------------------------------------------------------------
-- Address count pipeline process is used to pipeline address count.
-------------------------------------------------------------------------------
ADDR_CNT_PIPE_PROCESS_SYN: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
addr_cnt_d1 <= (others => '0');
addr_cnt_d2 <= (others => '0');
addr_cnt_d3 <= (others => '0');
addr_cnt_d4 <= (others => '0');
else
if Bus2IP_RdReq = '1' or single_transaction = '1' then
addr_cnt_d1 <= Addr_cnt;
addr_cnt_d2 <= addr_cnt_d1;
addr_cnt_d3 <= addr_cnt_d2;
addr_cnt_d4 <= addr_cnt_d3;
else
addr_cnt_d1 <= (others => '0');
addr_cnt_d2 <= (others => '0');
addr_cnt_d3 <= (others => '0');
addr_cnt_d4 <= (others => '0');
end if;
end if;
end if;
end process ADDR_CNT_PIPE_PROCESS_SYN;
-------------------------------------------------------------------------------
-- Synchonous address counter process is used to multiplex the address counter
-- select signal depending on the type of memory.
-------------------------------------------------------------------------------
SYNC_ADDR_CNT_PROCESS: process(ns_idle,
Synch_mem,
Two_pipe_delay,
addr_cnt_d2,
addr_cnt_d3,
addr_cnt_d4)
begin
if (ns_idle='0') then
if Synch_mem = '1' then
if Two_pipe_delay = '1' then
addr_cnt_sel <= addr_cnt_d4;
else
addr_cnt_sel <= addr_cnt_d3;
end if;
else
addr_cnt_sel <= addr_cnt_d2;
end if;
else
addr_cnt_sel <= (others => '0');
end if;
end process SYNC_ADDR_CNT_PROCESS;
---------------------------- Read Data Enable Logic ---------------------------
read_data_en_d(0) <= Read_data_en;
RDDATA_EN_GEN_SYNC: for i in 0 to 3 generate
begin
-------------------------------------------------------------------------------
-- FDR primitive is used for read_data_en_d pipe generation.
-------------------------------------------------------------------------------
RDDATA_EN_REG_SYNC: FDR
port map (
Q => read_data_en_d(i+1), --[out]
C => Clk, --[in]
D => read_data_en_d(i), --[in]
R => Rst --[in]
);
end generate RDDATA_EN_GEN_SYNC;
-------------------------------------------------------------------------------
-- Read data enable select process is used to multiplex the read data enable
-- depending on the type of memory.
-------------------------------------------------------------------------------
READ_DATA_EN_SEL_PROCESS: process(read_data_en_d, Synch_mem,
Two_pipe_delay)
begin
if Synch_mem = '1' then
if Two_pipe_delay = '1' then
read_data_en_sel <= read_data_en_d(3);
else
read_data_en_sel <= read_data_en_d(2);
end if;
else
read_data_en_sel <= read_data_en_d(1);
end if;
end process READ_DATA_EN_SEL_PROCESS;
end generate SYNC_ADDR_CNT_GEN;
-------------------------------------------------------------------------------
-- Address count select generation for asynchronous memory.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------- C_GLOBAL_SYNC_MEM = 0 -------------------------------
-------------------------------------------------------------------------------
ASYNC_ADDR_CNT_GEN: if C_GLOBAL_SYNC_MEM = 0 generate
begin
-------------------------------------------------------------------------------
-- Address count pipeline process is used to pipeline address count.
-------------------------------------------------------------------------------
ADDR_CNT_PIPE_PROCESS_ASYNC: process(Clk)
begin
if Clk'event and Clk = '1' then
if ((Rst = '1') or (ns_idle='1')) then
addr_cnt_d1 <= (others => '0');
addr_cnt_d2 <= (others => '0');
else
addr_cnt_d1 <= Addr_cnt;
addr_cnt_d2 <= addr_cnt_d1;
end if;
end if;
end process ADDR_CNT_PIPE_PROCESS_ASYNC;
addr_cnt_sel <= addr_cnt_d2;
---------------------------- Read Data Enable Logic ---------------------------
read_data_en_d(0) <= Read_data_en;
read_data_en_sel <= read_data_en_d(1);
RDDATA_EN_GEN_ASYNC: for i in 0 to 3 generate
begin
-------------------------------------------------------------------------------
-- FDR primitive is used for read_data_en_d pipe generation.
-------------------------------------------------------------------------------
RDDATA_EN_REG_ASYNC: FDR
port map (
Q => read_data_en_d(i+1), --[out]
C => Clk, --[in]
D => read_data_en_d(i), --[in]
R => Rst --[in]
);
end generate RDDATA_EN_GEN_ASYNC;
end generate ASYNC_ADDR_CNT_GEN;
-------------------------------------------------------------------------------
-- Read Data CE generation For 64 Bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_64_GEN: if C_IPIF_DWIDTH = 64 generate
begin
--signal test :std_logic_vector(0 downto 7);
--test <= read_data_ce(conv_integer(addr_cnt_sel)*4+i);
-------------------------------------------------------------------------------
-- Read data CE process is used to generate read data chip enable for 64 Bit
-- DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_PROCESS_64: process(read_data_en_sel,
addr_cnt_sel,
single_transaction,
Bus2IP_RdReq,
Mem_width_bytes,
Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack,
addr_cnt_numonyx
) is
begin
read_data_ce <= (others => '0');
if Bus2IP_RdReq = '1' or single_transaction = '1' then
case Mem_width_bytes is
when "0001" =>
read_data_ce(conv_integer(addr_cnt_sel))
<= read_data_en_sel;
when "0010" =>
for i in 0 to 1 loop
--read_data_ce(conv_integer(addr_cnt_sel)*2+i)
-- <= read_data_en_sel;
if(Linear_flash_brst_rd_flag = '0') then
read_data_ce(conv_integer(addr_cnt_sel)*2+i)
<= read_data_en_sel;
else
read_data_ce(conv_integer(addr_cnt_numonyx)*2+i)
<= Linear_flash_rd_data_ack;--read_data_en_sel;
end if;
end loop;
when "0100" =>
for i in 0 to 3 loop
read_data_ce(conv_integer(addr_cnt_sel)*4+i)
<= read_data_en_sel;
end loop;
when "1000" =>
for i in 0 to 7 loop
read_data_ce(i) <= read_data_en_sel;
end loop;
-- coverage off
when others =>
read_data_ce <= (others => '0');
-- coverage on
end case;
end if;
end process READ_DATA_CE_PROCESS_64;
end generate READ_DATA_CE_64_GEN;
-------------------------------------------------------------------------------
-- Read data CE generation For 32 Bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_32_GEN: if C_IPIF_DWIDTH = 32 generate
begin
-------------------------------------------------------------------------------
-- Read data CE process is used to generate read data chip enable for 32 Bit
-- DWidth.
-------------------------------------------------------------------------------
READ_DATA_CE_PROCESS_32: process(Mem_width_bytes,
addr_cnt_sel,
addr_cnt_numonyx,
read_data_en_sel,
Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack
) is
begin
read_data_ce <= (others => '0');
case Mem_width_bytes is
when "0001" =>
read_data_ce(conv_integer(addr_cnt_sel))
<= read_data_en_sel ; -- and not(Linear_flash_brst_rd_flag)) or (Linear_flash_brst_rd_flag and Linear_flash_rd_data_ack);
when "0010" =>
for i in 0 to 1 loop
if(Linear_flash_brst_rd_flag = '0') then
read_data_ce(conv_integer(addr_cnt_sel)*2+i)
<= read_data_en_sel;
else
read_data_ce(conv_integer(addr_cnt_numonyx)*2+i)
<= Linear_flash_rd_data_ack;--read_data_en_sel;
end if;
end loop;
when "0100" =>
for i in 0 to 3 loop
read_data_ce(i) <= read_data_en_sel ;--and not(Linear_flash_brst_rd_flag)) or (Linear_flash_brst_rd_flag and Linear_flash_rd_data_ack);--read_data_en_sel;
end loop;
-- coverage off
when others =>
read_data_ce <= (others => '0');
-- coverage on
end case;
end process READ_DATA_CE_PROCESS_32;
end generate READ_DATA_CE_32_GEN;
-------------------------------------------------------------------------------
-- Read Data Path For 64 Bit Maximum Memory Width.
-------------------------------------------------------------------------------
READ_DATA_64_GEN: if (C_MAX_MEM_WIDTH=64 and C_IPIF_DWIDTH=64) generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 64 Bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_64_64: process(Mem_width_bytes, MemSteer_Mem_DQ_I )
begin
read_data <= (others => '0');
case Mem_width_bytes is
when "0001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
when "0010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
read_data(i*C_MIN_MEM_WIDTH*2 to
i*C_MIN_MEM_WIDTH*2+C_MIN_MEM_WIDTH*2-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*2-1);
end loop;
when "0100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
read_data(i*C_MIN_MEM_WIDTH*4 to
i*C_MIN_MEM_WIDTH*4+C_MIN_MEM_WIDTH*4-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*4-1);
end loop;
when "1000" =>
read_data <= MemSteer_Mem_DQ_I;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_64_64;
READ_PARITY_EN_64_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_PRTY_PROCESS_64: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes is
when "0001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when "0010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2) -1 loop
read_parity(i*C_MIN_MEM_WIDTH*2/8 to
i*C_MIN_MEM_WIDTH*2/8+C_MIN_MEM_WIDTH*2/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*2/8-1);
end loop;
when "0100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4) -1 loop
read_parity(i*C_MIN_MEM_WIDTH*4/8 to
i*C_MIN_MEM_WIDTH*4/8+C_MIN_MEM_WIDTH*4/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*4/8-1);
end loop;
when "1000" =>
read_parity <= MemSteer_Mem_DQ_prty_I;
when others =>
read_parity <= (others => '0');
end case;
end process READ_PRTY_PROCESS_64;
READ_PARITY_MUX_PROCESS_64: process(MemSteer_Mem_DQ_I,
Parity_type,
Bus2IP_BE,
read_ack_d,
MemSteer_Mem_DQ_prty_I)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 7 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I
(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH
+ C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_64;
end generate READ_PARITY_EN_64_MAX;
end generate READ_DATA_64_GEN;
-------------------------------------------------------------------------------
-- Read data path For 32 bit maximum memory width.
-------------------------------------------------------------------------------
READ_DATA_32_GEN: if (C_MAX_MEM_WIDTH=32) generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 32 bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_32: process(Mem_width_bytes, MemSteer_Mem_DQ_I)
begin
read_data <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
when "010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_data(i*C_MIN_MEM_WIDTH*2 to
i*C_MIN_MEM_WIDTH*2+C_MIN_MEM_WIDTH*2-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*2-1);
end loop;
when "100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4)-1 loop
read_data(i*C_MIN_MEM_WIDTH*4 to
i*C_MIN_MEM_WIDTH*4+C_MIN_MEM_WIDTH*4-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*4-1);
end loop;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_32;
READ_PARITY_EN_32_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_PRTY_PROCESS_32: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes(1 to 3) is
when "001" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when "010" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_parity(i*C_MIN_MEM_WIDTH*2/8 to
i*C_MIN_MEM_WIDTH*2/8+C_MIN_MEM_WIDTH*2/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*2/8-1);
end loop;
when "100" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*4)-1 loop
read_parity(i*C_MIN_MEM_WIDTH*4/8 to
i*C_MIN_MEM_WIDTH*4/8+C_MIN_MEM_WIDTH*4/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*4/8-1);
end loop;
-- coverage off
when others =>
read_parity <= (others => '0');
-- coverage on
end case;
end process READ_PRTY_PROCESS_32;
READ_PARITY_MUX_PROCESS_32: process(MemSteer_Mem_DQ_I,
Parity_type,
MemSteer_Mem_DQ_prty_I,
read_ack_d,
Bus2IP_BE)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 3 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I
(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH
+ C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_32;
end generate READ_PARITY_EN_32_MAX;
end generate READ_DATA_32_GEN;
-------------------------------------------------------------------------------
-- Read data path for 16 bit maximum memory width.
-------------------------------------------------------------------------------
READ_DATA_16_GEN: if C_MAX_MEM_WIDTH=16 generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 16 bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_16: process(Mem_width_bytes, MemSteer_Mem_DQ_I)
begin
read_data <= (others => '0');
case Mem_width_bytes(2 to 3) is
when "01" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
when "10" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_data(i*C_MIN_MEM_WIDTH*2 to
i*C_MIN_MEM_WIDTH*2+C_MIN_MEM_WIDTH*2-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH*2-1);
end loop;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_16;
READ_PARITY_EN_16_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_DATA_PROCESS_16: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes(2 to 3) is
when "01" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when "10" =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/(C_MIN_MEM_WIDTH*2)-1 loop
read_parity(i*C_MIN_MEM_WIDTH*2/8 to
i*C_MIN_MEM_WIDTH*2/8+C_MIN_MEM_WIDTH*2/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH*2/8-1);
end loop;
-- coverage off
when others =>
read_parity <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_16;
READ_PARITY_MUX_PROCESS_16: process(MemSteer_Mem_DQ_I,
Parity_type,
MemSteer_Mem_DQ_prty_I,
read_ack_d,
Bus2IP_BE)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 1 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_16;
end generate READ_PARITY_EN_16_MAX;
end generate READ_DATA_16_GEN;
-------------------------------------------------------------------------------
-- Read data path for 8 bit maximum memory width.
-------------------------------------------------------------------------------
READ_DATA_8_GEN: if C_MAX_MEM_WIDTH=8 generate
begin
-------------------------------------------------------------------------------
-- Read data process is used to generate read data for 8 bit DWidth.
-------------------------------------------------------------------------------
READ_DATA_PROCESS_8: process(Mem_width_bytes,
MemSteer_Mem_DQ_I)
begin
read_data <= (others => '0');
case Mem_width_bytes(3) is
when '1' =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_data(i*C_MIN_MEM_WIDTH to
i*C_MIN_MEM_WIDTH+C_MIN_MEM_WIDTH-1)
<= MemSteer_Mem_DQ_I(0 to C_MIN_MEM_WIDTH-1);
end loop;
-- coverage off
when others =>
read_data <= (others => '0');
-- coverage on
end case;
end process READ_DATA_PROCESS_8;
READ_PARITY_EN_8_MAX : if (C_PARITY_TYPE_MEMORY/=0) generate
READ_DATA_PROCESS_8: process(Mem_width_bytes, MemSteer_Mem_DQ_prty_I)
begin
read_parity <= (others => '0');
case Mem_width_bytes(3) is
when '1' =>
-- create the input data
for i in 0 to C_IPIF_DWIDTH/C_MIN_MEM_WIDTH -1 loop
read_parity(i*C_MIN_MEM_WIDTH/8 to
i*C_MIN_MEM_WIDTH/8+C_MIN_MEM_WIDTH/8-1)
<= MemSteer_Mem_DQ_prty_I(0 to C_MIN_MEM_WIDTH/8-1);
end loop;
when others =>
read_parity <= (others => '0');
end case;
end process READ_DATA_PROCESS_8;
READ_PARITY_MUX_PROCESS_8: process(MemSteer_Mem_DQ_I,
Parity_type,
Bus2IP_BE,
read_ack_d,
MemSteer_Mem_DQ_prty_I)
begin
read_data_parity_cmb <= (others => '0');
if (read_ack_d(2) = '1') then
for i in 0 to 0 loop
--if Bus2IP_BE(i) = '1' then
read_data_parity_cmb (i)<= check_parity(MemSteer_Mem_DQ_I(i*C_MIN_MEM_WIDTH to i*C_MIN_MEM_WIDTH + C_MIN_MEM_WIDTH-1),
MemSteer_Mem_DQ_prty_I(i),
Parity_type);
--end if;
end loop;
else
read_data_parity_cmb <= (OTHERS => '0');
end if;
end process READ_PARITY_MUX_PROCESS_8;
end generate READ_PARITY_EN_8_MAX;
end generate READ_DATA_8_GEN;
end generate RDDATA_PATH_MUX_GEN;
end imp;
-------------------------------------------------------------------------------
-- End of file mem_steer.vhd.
-------------------------------------------------------------------------------
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/cntr5bit.vhd
|
4
|
9577
|
-------------------------------------------------------------------------------
-- cntr5bit - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : cntr5bit.vhd
-- Version : v2.0
--
-- Description : This file contains the a 5 bit resetable, loadable
-- down counter by 1.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Cntout -- Counter output
-- En -- Counter enable
-- Ld -- Counter load enable
-- Load_in -- Counter load data
-- Zero -- Terminal count
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity cntr5bit is
port (
Clk : in std_logic; -- input clock
Rst : in std_logic; -- reset counter
Cntout : out std_logic_vector (0 to 4);
En : in std_logic; -- counter down enable by 1
Ld : in std_logic; -- load enable
Load_in : in std_logic_vector (0 to 4); -- load input value
Zero : out std_logic -- terminal count
);
end cntr5bit;
architecture implementation of cntr5bit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Constants used in this design are found in mac_pkg.vhd
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal count : std_logic_vector(0 to 4);
signal zero_i : std_logic;
begin
Cntout <= count;
-------------------------------------------------------------------------------
-- INT_count_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal control register signals to the out port
-------------------------------------------------------------------------------
INT_COUNT_PROCESS1: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
count <= (others => '1');
elsif (Ld = '1') then
count <= Load_in;
elsif (En = '1' and zero_i = '0') then
count <= count - 1;
else
null;
end if;
end if;
end process INT_COUNT_PROCESS1;
INT_COUNT_PROCESS2: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
zero_i <= '1';
else
if (count = "00001") then
zero_i <= '1';
else
zero_i <= '0';
end if;
end if;
end if;
end process INT_COUNT_PROCESS2;
Zero <= zero_i;
end implementation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lib_fifo_v1_0/a73caf46/hdl/src/vhdl/async_fifo_fg.vhd
|
11
|
123226
|
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v12_0;
use fifo_generator_v12_0.all;
--library lib_fifo_v1_0;
--use lib_fifo_v1_0.lib_fifo_pkg.all;
--use lib_fifo_v1_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full, -- : OUT std_logic;
almost_full => Almost_full, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rx_fifo.vhd
|
4
|
8495
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rx_fifo.vhd
--
-- Version: v1.01.a
-- Description: This module
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library mii_to_rmii_v2_0;
-- synopsys translate_off
-- synopsys translate_on
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity rx_fifo is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_fifo_wr_en : in std_logic;
Rx_fifo_rd_en : in std_logic;
Rx_fifo_input : in std_logic_vector(15 downto 0);
Rx_fifo_mt_n : out std_logic;
Rx_fifo_full : out std_logic;
Rx_fifo_output : out std_logic_vector(15 downto 0)
);
end rx_fifo;
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_RESET_ACTIVE --
--
-- Definition of Ports:
--
------------------------------------------------------------------------------
architecture simulation of rx_fifo is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as C_RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply lene this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No constants in this architecture.
------------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------------
signal srl_fifo_reset : std_logic;
signal rx_fifo_output_i : std_logic_vector(15 downto 0);
------------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------------
component srl_fifo
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end component;
begin
------------------------------------------------------------------------------
-- Component Instantiations
------------------------------------------------------------------------------
-- Lene the function the component is performing with comments
-- Component instantiation names are all uppercase and are of the form:
-- <ENTITY_>I_<#|FUNC>
-- If no components are required, delete this section from the file
------------------------------------------------------------------------------
I_SRL_FIFO : srl_fifo
generic map (
C_DATA_BITS => 16,
C_DEPTH => 16,
C_XON => false
)
port map (
Clk => Ref_Clk,
Reset => srl_fifo_reset,
FIFO_Write => Rx_fifo_wr_en,
Data_In => Rx_fifo_input,
FIFO_Read => Rx_fifo_rd_en,
Data_Out => rx_fifo_output_i,
FIFO_Full => Rx_fifo_full,
Data_Exists => Rx_fifo_mt_n,
Addr => open
);
------------------------------------------------------------------------------
-- RESET_PROCESS
------------------------------------------------------------------------------
RESET_PROCESS : process (Sync_rst_n)
begin
if (Sync_rst_n = C_RESET_ACTIVE) then
srl_fifo_reset <= '1';
else
srl_fifo_reset <= '0';
end if;
end process;
------------------------------------------------------------------------------
-- FIFO_REGISTER_PROCESS
------------------------------------------------------------------------------
-- Include comments about the function of the process
------------------------------------------------------------------------------
FIFO_REGISTER_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rx_fifo_output <= (others => '0');
elsif (Rx_fifo_rd_en = '1') then
Rx_fifo_output <= rx_fifo_output_i;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
-- NONE
end simulation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_axi_intc_0/synth/design_1_microblaze_0_axi_intc_0.vhd
|
2
|
11544
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_intc:4.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_intc_v4_1;
USE axi_intc_v4_1.axi_intc;
ENTITY design_1_microblaze_0_axi_intc_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_microblaze_0_axi_intc_0;
ARCHITECTURE design_1_microblaze_0_axi_intc_0_arch OF design_1_microblaze_0_axi_intc_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_intc IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_INTR_INPUTS : INTEGER;
C_NUM_SW_INTR : INTEGER;
C_KIND_OF_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_EDGE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_KIND_OF_LVL : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ASYNC_INTR : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_NUM_SYNC_FF : INTEGER;
C_IVAR_RESET_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_ENABLE_ASYNC : INTEGER;
C_HAS_IPR : INTEGER;
C_HAS_SIE : INTEGER;
C_HAS_CIE : INTEGER;
C_HAS_IVR : INTEGER;
C_HAS_ILR : INTEGER;
C_IRQ_IS_LEVEL : INTEGER;
C_IRQ_ACTIVE : STD_LOGIC;
C_DISABLE_SYNCHRONIZERS : INTEGER;
C_MB_CLK_NOT_CONNECTED : INTEGER;
C_HAS_FAST : INTEGER;
C_EN_CASCADE_MODE : INTEGER;
C_CASCADE_MASTER : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
intr : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
processor_clk : IN STD_LOGIC;
processor_rst : IN STD_LOGIC;
irq : OUT STD_LOGIC;
processor_ack : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
interrupt_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
interrupt_address_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
processor_ack_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT axi_intc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "axi_intc,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_axi_intc_0_arch : ARCHITECTURE IS "design_1_microblaze_0_axi_intc_0,axi_intc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_axi_intc_0_arch: ARCHITECTURE IS "design_1_microblaze_0_axi_intc_0,axi_intc,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_intc,x_ipVersion=4.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_intc_inst,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_NUM_INTR_INPUTS=2,C_NUM_SW_INTR=0,C_KIND_OF_INTR=0xfffffffe,C_KIND_OF_EDGE=0xffffffff,C_KIND_OF_LVL=0xffffffff,C_ASYNC_INTR=0xFFFFFFFC,C_NUM_SYNC_FF=2,C_IVAR_RESET_VALUE=0x00000010,C_ENABLE_ASYNC=0,C_HAS_IPR=1,C_HAS_SIE=1,C_HAS_CIE=1,C_HAS_IVR=1,C_HAS_ILR=0,C_IRQ_IS_LEVEL=1,C_IRQ_ACTIVE=0x1,C_DISABLE_SYNCHRONIZERS=1,C_MB_CLK_NOT_CONNECTED=1,C_HAS_FAST=1,C_EN_CASCADE_MODE=0,C_CASCADE_MASTER=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_resetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi RREADY";
ATTRIBUTE X_INTERFACE_INFO OF intr: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt_input INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 proc_clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF processor_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 proc_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF processor_ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ACK";
ATTRIBUTE X_INTERFACE_INFO OF interrupt_address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 interrupt ADDRESS";
BEGIN
U0 : axi_intc
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_intc_inst",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_INTR_INPUTS => 2,
C_NUM_SW_INTR => 0,
C_KIND_OF_INTR => X"fffffffe",
C_KIND_OF_EDGE => X"ffffffff",
C_KIND_OF_LVL => X"ffffffff",
C_ASYNC_INTR => X"FFFFFFFC",
C_NUM_SYNC_FF => 2,
C_IVAR_RESET_VALUE => X"00000010",
C_ENABLE_ASYNC => 0,
C_HAS_IPR => 1,
C_HAS_SIE => 1,
C_HAS_CIE => 1,
C_HAS_IVR => 1,
C_HAS_ILR => 0,
C_IRQ_IS_LEVEL => 1,
C_IRQ_ACTIVE => '1',
C_DISABLE_SYNCHRONIZERS => 1,
C_MB_CLK_NOT_CONNECTED => 1,
C_HAS_FAST => 1,
C_EN_CASCADE_MODE => 0,
C_CASCADE_MASTER => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
intr => intr,
processor_clk => processor_clk,
processor_rst => processor_rst,
irq => irq,
processor_ack => processor_ack,
interrupt_address => interrupt_address,
interrupt_address_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_microblaze_0_axi_intc_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_timer_v2_0/de85f913/hdl/src/vhdl/axi_timer.vhd
|
7
|
17227
|
-------------------------------------------------------------------------------
-- xps_timer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :axi_timer.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Timer/Counter for AXI
-- Standard :VHDL-93
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_timer.
--
-- axi_timer.vhd
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-- --tc_types.vhd
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
--
--
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-------------------------------------------------------------------------------
-- timer/counter signals
-------------------------------------------------------------------------------
-- capturetrig0 -- Capture Trigger 0
-- capturetrig1 -- Capture Trigger 1
-- generateout0 -- Generate Output 0
-- generateout1 -- Generate Output 1
-- pwm0 -- Pulse Width Modulation Ouput 0
-- interrupt -- Interrupt
-- freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0;
library axi_lite_ipif_v3_0;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0.ipif_pkg.SLV64_ARRAY_TYPE;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity axi_timer is
generic (
C_FAMILY : string := "virtex7";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
-- axi lite ipif block generics
C_S_AXI_DATA_WIDTH: integer := 32;
C_S_AXI_ADDR_WIDTH: integer := 5 --5
);
port
(
--Timer/Counter signals
capturetrig0 : in std_logic;
capturetrig1 : in std_logic;
generateout0 : out std_logic;
generateout1 : out std_logic;
pwm0 : out std_logic;
interrupt : out std_logic;
freeze : in std_logic;
--system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic := '1';
s_axi_awaddr : in std_logic_vector(4 downto 0);
--(c_s_axi_addr_width-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
-- (c_s_axi_data_width-1 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
-- ((c_s_axi_data_width/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(4 downto 0);
--(c_s_axi_addr_width-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
--(c_s_axi_data_width-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN: signal is "10000";
end entity axi_timer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of axi_timer is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
constant ZEROES : std_logic_vector(0 to 31) := X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- Timer registers Base Address
ZEROES & X"00000000",
ZEROES & X"0000001F"
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 8
);
constant C_S_AXI_MIN_SIZE :std_logic_vector(31 downto 0):= X"0000001F";
constant C_USE_WSTRB :integer := 0;
constant C_DPHASE_TIMEOUT :integer range 0 to 256 := 32;
--Signal declaration --------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_reset : std_logic;
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1)
:=(others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
-----------------------------------------------------------------------
signal bus2ip_data : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_be : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH/8-1 );
signal bus2ip_rdce : std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
TC_CORE_I: entity axi_timer_v2_0.tc_core
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH,
C_ONE_TIMER_ONLY => C_ONE_TIMER_ONLY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_AWIDTH => C_S_AXI_ADDR_WIDTH,
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
-- IPIF signals
Clk => bus2ip_clk, --[in]
Rst => bus2ip_reset, --[in]
Bus2ip_addr => bus2ip_addr, --[in]
Bus2ip_be => bus2ip_be, --[in]
Bus2ip_data => bus2ip_data, --[in]
TC_DBus => ip2bus_data, --[out]
bus2ip_rdce => bus2ip_rdce, --[in]
bus2ip_wrce => bus2ip_wrce, --[in]
ip2bus_rdack => ip2bus_rdack, --[out]
ip2bus_wrack => ip2bus_wrack, --[out]
TC_errAck => ip2bus_error, --[out]
-- Timer/Counter signals
CaptureTrig0 => capturetrig0, --[in]
CaptureTrig1 => capturetrig1, --[in]
GenerateOut0 => generateout0, --[out]
GenerateOut1 => generateout1, --[out]
PWM0 => pwm0, --[out]
Interrupt => interrupt, --[out]
Freeze => freeze --[in]
);
---------------------------------------------------------------------------
-- INSTANTIATE AXI Lite IPIF
---------------------------------------------------------------------------
AXI4_LITE_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals -------------------------------
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => open,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
bus2ip_reset <= not bus2ip_resetn;
end architecture imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/emc.vhd
|
4
|
73849
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: emc.vhd
-- Version: v2.1
-- Description: Common interface for External Memory Controller
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 03/01/08 First Version
-- ^^^^^^^^^^
-- This file is based on version v3_01_c updated to fixed CR #466745: -
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE. The same generic is mapped to
-- component io_registers from emc_common_v3_03_a.
-- ~~~~~~~~~
-- NSK 03/12/08 Updated
-- ^^^^^^^^
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE in comment "Definition of Generics"
-- section.
-- ~~~~~~~~
-- NSK 03/03/08 Updated
-- ^^^^^^^^
-- 1. Removed generic C_MEM_DQ_CAPTURE_NEGEDGE.
-- 2. Added the port RdClk used as clock to capture the data from memory.
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_03_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
--
-- KSB 05/08/08 version v4_00_a
-- 1. Modified for Page mdoe read
-- 2. Modified for 64 Bit memory address align
-- ~~~~~~~~
--
-- KSB 22/05/10 version v5_00_a
-- 1. Modified for AXI EMC, PSRAM, Byte parity Memory Support
-- 2. Modified for AXI Slave burst interface
-- ~~~~~~~~
-- SK 03/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Registered the IP2Bus_RdAck and IP2Bus_Data signals.
-- 2. Reduced utilization
-- ~~~~~~~~
-- SK 03/11/11 version v5_03_a
-- ^^^^^^^^
-- 1. Fixed CR#595758 and CR#606038
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- emc_common_v3_0 library is used for emc_common component declarations
-------------------------------------------------------------------------------
library emc_common_v3_0;
use emc_common_v3_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_BANKS_MEM -- Number of memory banks
-- C_IPIF_DWIDTH -- Width of processor data bus
-- C_IPIF_AWIDTH -- Width of processor address bus
-- C_MEM(0:3)_BASEADDR -- Memory bank (0:3) base address
-- C_MEM(0:3)_HIGHADDR -- Memory bank (0:3) high address
-- C_INCLUDE_NEGEDGE_IOREGS -- Include negative edge IO registers
-- C_PAGEMODE_FLASH_(0:3) -- Whether a PAGE MODE Flash device is used
-- C_MEM(0:3)_WIDTH -- Width of memory bank's data bus
-- C_MAX_MEM_WIDTH -- Maximum width of memory data bus
-- C_INCLUDE_DATAWIDTH_MATCHING_(0:3) -- Include datawidth matching logic for
-- -- memory bank
-- C_BUS_CLOCK_PERIOD_PS -- Bus clock period to calculate wait
-- state pulse widths.
-- C_SYNCH_MEM_(0:3) -- Memory bank is synchronous
-- C_TCEDV_PS_MEM_(0:3) -- Chip Enable to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_TAVDV_PS_MEM_(0:3) -- Address Valid to Data Valid Time
-- -- (Maximum of TCEDV and TAVDV applied
-- as read cycle start to first data valid)
-- C_TPACC_PS_FLASH_(0:3) -- Address Valid to Data Valid Time
-- -- for a PAGE Read for a PAGE MODE Flash
-- C_THZCE_PS_MEM_(0:3) -- Chip Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_THZOE_PS_MEM_(0:3) -- Output Enable High to Data Bus High
-- Impedance (Maximum of THZCE and THZOE
-- applied as Read Recovery before Write)
-- C_TWC_PS_MEM_(0:3) -- Write Cycle Time
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TWP_PS_MEM_(0:3) -- Write Enable Minimum Pulse Width
-- (Maximum of TWC and TWP applied as write
-- enable pulse width)
-- C_TLZWE_PS_MEM_(0:3) -- Write Enable High to Data Bus Low
-- Impedance (Applied as Write Recovery
-- before Read)
-- C_WR_REC_TIME_MEM_(0:3) -- Write recovery time between the write
-- -- and next consecutive read transaction
-- Definition of Ports:
--
-- Bus2IP_Clk -- System clock
-- RdClk -- Read Clock
-- Bus2IP_Reset -- System Reset
--
-- Bus and IPIC Interface signals
-- Bus2IP_Addr -- Processor bus address
-- Bus2IP_BE -- Processor bus byte enables
-- Bus2IP_Data -- Processor data
-- Bus2IP_RNW -- Processor read not write
-- Bus2IP_Burst -- Processor burst
-- Bus2IP_WrReq -- Processor write request
-- Bus2IP_RdReq -- Processor read request
-- Bus2IP_Mem_CS -- Memory address range is being accessed
--
-- EMC to bus signals
-- IP2Bus_Data -- Data to processor bus
-- IP2Bus_errAck -- Error acknowledge
-- IP2Bus_retry -- Retry indicator
-- IP2Bus_toutSup -- Suppress watch dog timer
-- IP2Bus_RdAck -- Read acknowledge
-- IP2Bus_WrAck -- Write acknowledge
-- IP2Bus_AddrAck -- Read/Write Address acknowledge
--
-- Memory signals
-- Mem_A -- Memory address inputs
-- Mem_DQ_I -- Memory input data bus
-- Mem_DQ_O -- Memory output data bus
-- Mem_DQ_T -- Memory data output enable
-- Mem_CEN -- Memory chip select
-- Mem_OEN -- Memory output enable
-- Mem_WEN -- Memory write enable
-- Mem_QWEN -- Memory qualified write enable
-- Mem_BEN -- Memory byte enables
-- Mem_RPN -- Memory reset/power down
-- Mem_CE -- Memory chip enable
-- Mem_ADV_LDN -- Memory counter advance/load (=0)
-- Mem_LBON -- Memory linear/interleaved burst order (=0)
-- Mem_CKEN -- Memory clock enable (=0)
-- Mem_RNW -- Memory read not write
-------------------------------------------------------------------------------
-- Port declarations
-------------------------------------------------------------------------------
entity EMC is
generic (
C_NUM_BANKS_MEM : integer range 1 to 4 := 1;
C_IPIF_DWIDTH : integer := 32;
C_IPIF_AWIDTH : integer := 32;
C_MEM0_BASEADDR : std_logic_vector := x"30000000";
C_MEM0_HIGHADDR : std_logic_vector := x"3000ffff";
C_MEM1_BASEADDR : std_logic_vector := x"40000000";
C_MEM1_HIGHADDR : std_logic_vector := x"4000ffff";
C_MEM2_BASEADDR : std_logic_vector := x"50000000";
C_MEM2_HIGHADDR : std_logic_vector := x"5000ffff";
C_MEM3_BASEADDR : std_logic_vector := x"60000000";
C_MEM3_HIGHADDR : std_logic_vector := x"6000ffff";
C_INCLUDE_NEGEDGE_IOREGS : integer := 0;
C_PAGEMODE_FLASH_0 : integer := 0;
C_PAGEMODE_FLASH_1 : integer := 0;
C_PAGEMODE_FLASH_2 : integer := 0;
C_PAGEMODE_FLASH_3 : integer := 0;
C_MEM0_WIDTH : integer range 8 to 64 := 32;
C_MEM1_WIDTH : integer range 8 to 64 := 32;
C_MEM2_WIDTH : integer range 8 to 64 := 32;
C_MEM3_WIDTH : integer range 8 to 64 := 32;
C_MAX_MEM_WIDTH : integer range 8 to 64 := 32;
C_MEM0_TYPE : integer range 0 to 5 := 0;
C_MEM1_TYPE : integer range 0 to 5 := 0;
C_MEM2_TYPE : integer range 0 to 5 := 0;
C_MEM3_TYPE : integer range 0 to 5 := 0;
C_PARITY_TYPE_0 : integer range 0 to 2 := 0;
C_PARITY_TYPE_1 : integer range 0 to 2 := 0;
C_PARITY_TYPE_2 : integer range 0 to 2 := 0;
C_PARITY_TYPE_3 : integer range 0 to 2 := 0;
C_INCLUDE_DATAWIDTH_MATCHING_0 : integer := 0;
C_INCLUDE_DATAWIDTH_MATCHING_1 : integer := 0;
C_INCLUDE_DATAWIDTH_MATCHING_2 : integer := 0;
C_INCLUDE_DATAWIDTH_MATCHING_3 : integer := 0;
C_BUS_CLOCK_PERIOD_PS : integer := 10000;
-- Memory Channel 0 Timing Parameters
C_SYNCH_MEM_0 : integer := 0;
--C_SUPPORT_SYNC_RD_0 : integer := 0;
C_SYNCH_PIPEDELAY_0 : integer := 2;
C_TCEDV_PS_MEM_0 : integer := 15000;
C_TAVDV_PS_MEM_0 : integer := 15000;
C_TPACC_PS_FLASH_0 : integer := 25;
C_THZCE_PS_MEM_0 : integer := 7000;
C_THZOE_PS_MEM_0 : integer := 7000;
C_TWC_PS_MEM_0 : integer := 15000;
C_TWP_PS_MEM_0 : integer := 12000;
C_TWPH_PS_MEM_0 : integer := 12000;
C_TLZWE_PS_MEM_0 : integer := 0;
C_WR_REC_TIME_MEM_0 : integer := 100000;
-- Memory Channel 1 Timing Parameters
C_SYNCH_MEM_1 : integer := 0;
--C_SUPPORT_SYNC_RD_1 : integer := 0;
C_SYNCH_PIPEDELAY_1 : integer := 2;
C_TCEDV_PS_MEM_1 : integer := 15000;
C_TAVDV_PS_MEM_1 : integer := 15000;
C_TPACC_PS_FLASH_1 : integer := 25000;
C_THZCE_PS_MEM_1 : integer := 7000;
C_THZOE_PS_MEM_1 : integer := 7000;
C_TWC_PS_MEM_1 : integer := 15000;
C_TWP_PS_MEM_1 : integer := 12000;
C_TWPH_PS_MEM_1 : integer := 12000;
C_TLZWE_PS_MEM_1 : integer := 0;
C_WR_REC_TIME_MEM_1 : integer := 100000;
-- Memory Channel 2 Timing Parameters
C_SYNCH_MEM_2 : integer := 0;
--C_SUPPORT_SYNC_RD_2 : integer := 0;
C_SYNCH_PIPEDELAY_2 : integer := 2;
C_TCEDV_PS_MEM_2 : integer := 15000;
C_TAVDV_PS_MEM_2 : integer := 15000;
C_TPACC_PS_FLASH_2 : integer := 25000;
C_THZCE_PS_MEM_2 : integer := 7000;
C_THZOE_PS_MEM_2 : integer := 7000;
C_TWC_PS_MEM_2 : integer := 15000;
C_TWP_PS_MEM_2 : integer := 12000;
C_TWPH_PS_MEM_2 : integer := 12000;
C_TLZWE_PS_MEM_2 : integer := 0;
C_WR_REC_TIME_MEM_2 : integer := 100000;
-- Memory Channel 3 Timing Parameters
C_SYNCH_MEM_3 : integer := 0;
--C_SUPPORT_SYNC_RD_3 : integer := 0;
C_SYNCH_PIPEDELAY_3 : integer := 2;
C_TCEDV_PS_MEM_3 : integer := 15000;
C_TAVDV_PS_MEM_3 : integer := 15000;
C_TPACC_PS_FLASH_3 : integer := 25000;
C_THZCE_PS_MEM_3 : integer := 7000;
C_THZOE_PS_MEM_3 : integer := 7000;
C_TWC_PS_MEM_3 : integer := 15000;
C_TWP_PS_MEM_3 : integer := 12000;
C_TWPH_PS_MEM_3 : integer := 12000;
C_TLZWE_PS_MEM_3 : integer := 0 ;
C_WR_REC_TIME_MEM_3 : integer := 100000
);
port (
Bus2IP_Clk : in std_logic;
RdClk : in std_logic;
Bus2IP_Reset : in std_logic;
-- Bus and IPIC Interface signals
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_RNW : in std_logic;
Bus2IP_Burst : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Mem_CS : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Bus2IP_BurstLength : in std_logic_vector (0 to 7);
Linear_flash_brst_rd_flag : in std_logic;
Linear_flash_rd_data_ack : in std_logic;
Bus2IP_RdReq_emc : in std_logic;
Bus2IP_WrReq_emc : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
IP2Bus_errAck : out std_logic;
IP2Bus_retry : out std_logic;
IP2Bus_toutSup : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_AddrAck : out std_logic;
parity_error_adrss : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
parity_error_mem : out std_logic_vector(0 to 1);
Type_of_xfer : in std_logic;
psram_page_mode : in std_logic;
original_wrce : in std_logic;
Mem_DQ_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_PRTY_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_A : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
Mem_RPN : out std_logic;
Mem_CEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_OEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_BEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_CE : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic;
Cre_reg_en : in std_logic;
Mem_WAIT : in std_logic;
Synch_mem12 : out std_logic;
last_addr1 : in std_logic;
pr_idle : out std_logic; -- 11-12-2012
axi_trans_size_reg : in std_logic_vector(1 downto 0); -- 1/3/2013
axi_wvalid : in std_logic;
axi_wlast : in std_logic;
axi_arsize : in std_logic_vector(2 downto 0);
Parity_err : out std_logic
);
end entity EMC;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of EMC is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Data Types
-------------------------------------------------------------------------------
type EMC_ARRAY_TYPE is array (0 to 3) of integer;
-- type EMC_ARRAY_TYPE is array (0 to C_NUM_BANKS_MEM-1) of integer;
type INTEGER_ARRAY is array (natural range <>) of integer;
type MEM_ADDR_ARRAY is array (0 to C_NUM_BANKS_MEM-1) of
std_logic_vector(0 to C_IPIF_AWIDTH-1);
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- not_all_zeros()
-------------------------------------------------------------------------------
function not_all_zeros(input_array : EMC_ARRAY_TYPE;
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 16 := 0;
begin
for i in 0 to num_real_elements -1 loop
sum := sum + input_array(i);
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function not_all_zeros;
--------------------------------------------------------------------------------
function check_flash_mem(input_array : EMC_ARRAY_TYPE; -- 9/7/2011
num_real_elements : integer)
return integer is
variable sum : integer range 0 to 10 := 0;
begin
for i in 0 to num_real_elements -1 loop
if(input_array(i) = 2)or
(input_array(i) = 3)or
(input_array(i) = 5)or
(input_array(i) = 4)then
sum := sum + 1;
end if;
end loop;
if sum = 0 then
return 0;
else
return 1;
end if;
end function check_flash_mem;
-- --------------------------------------------------------------------------------
-- -- flash_supports_sync_rd: below function is used to check if any of the memories in the assigned
-- -- memory location is of Linear Flash which supports Sync Burst Read mode
-- --------------------------------------------------------------------------------
-- function flash_supports_sync_rd (input_flash_array : EMC_ARRAY_TYPE;
-- num_of_mem_banks : integer)
-- return integer is
-- variable flash_sync_rd : integer range 0 to 1 := 0;
-- begin
-- for i in 0 to num_of_mem_banks -1 loop
-- flash_sync_rd := flash_sync_rd + input_flash_array(i);
-- end loop;
--
-- if flash_sync_rd = 0 then
-- return 0;
-- else
-- return 1;
-- end if;
-- end function flash_supports_sync_rd;
-- -------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- minimum memory data width supported is 8 bits
constant MIN_MEM_WIDTH : integer := 8;
-- address offset
constant ADDR_OFFSET : integer range 0 to 4
:= log2(C_IPIF_DWIDTH/8);
constant ADDR_CNTR_WIDTH : integer range 1 to 5
:= max2(1,log2(C_IPIF_DWIDTH/8));
-- create arrays of generics for use in functions
constant SYNCH_MEM_ARRAY : EMC_ARRAY_TYPE :=
(C_SYNCH_MEM_0,
C_SYNCH_MEM_1,
C_SYNCH_MEM_2,
C_SYNCH_MEM_3);
constant DATAWIDTH_MATCH_ARRAY : EMC_ARRAY_TYPE :=
(C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3);
constant C_PAGEMODE_FLASH : EMC_ARRAY_TYPE :=
(C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3);
-- constant C_FLASH_SUPPORTS_SYNC_RD : EMC_ARRAY_TYPE :=
-- (
-- C_SUPPORT_SYNC_RD_0,
-- C_SUPPORT_SYNC_RD_1,
-- C_SUPPORT_SYNC_RD_2,
-- C_SUPPORT_SYNC_RD_3
-- );
type MEM_PARITY_ARRAY_TYPE is array (0 to 3) of integer range 0 to 2;
constant MEM_PARITY_TYPE_ARRAY : EMC_ARRAY_TYPE :=
(
C_PARITY_TYPE_0,
C_PARITY_TYPE_1,
C_PARITY_TYPE_2,
C_PARITY_TYPE_3
);
-- constant C_WRITE_RECOVERY_TIME : EMC_ARRAY_TYPE :=
-- (
-- C_WR_REC_TIME_MEM_0,
-- C_WR_REC_TIME_MEM_1,
-- C_WR_REC_TIME_MEM_2,
-- C_WR_REC_TIME_MEM_3
-- );
constant C_FLASH_TYPE_MEM : EMC_ARRAY_TYPE :=
(C_MEM0_TYPE,
C_MEM1_TYPE,
C_MEM2_TYPE,
C_MEM3_TYPE);
-------------------------------------------------------------------------------
-- Create global constants that indicate if any data matching is needed or if
-- any memories are synchronous. These can be used to eliminate un-necessary
-- logic.
-------------------------------------------------------------------------------
-- check for any memory in configuration is SYNC type or not.
constant GLOBAL_SYNC_MEM : integer range 0 to 1
:= not_all_zeros(SYNCH_MEM_ARRAY,
C_NUM_BANKS_MEM);
-- check for any memory in configuration needs Data Width Matching or not.
constant GLOBAL_DATAWIDTH_MATCH : integer range 0 to 1
:= not_all_zeros(DATAWIDTH_MATCH_ARRAY,
C_NUM_BANKS_MEM);
-- check for any memory in configuration is Page Mode Flash type or not.
constant PAGEMODE_FLASH : integer range 0 to 1
:= not_all_zeros(C_PAGEMODE_FLASH,
C_NUM_BANKS_MEM);
--constant C_FLASH_SYNC_RD : integer range 0 to 1
-- := flash_supports_sync_rd(C_FLASH_SUPPORTS_SYNC_RD,
-- C_NUM_BANKS_MEM);
-- check for any memory in configuration is parity enabled or not.
-- 0 - no parity
-- 1 - odd parity
-- 2 - even parity
constant PARITY_TYPE_MEMORY : integer range 0 to 2
:= not_all_zeros(MEM_PARITY_TYPE_ARRAY,
C_NUM_BANKS_MEM);
constant FLASH_TYP_MEM : integer range 0 to 1
:= check_flash_mem(C_FLASH_TYPE_MEM,
C_NUM_BANKS_MEM);
-------------------------------------------------------------------------------
-- Memory Cycle Time Calculations
-------------------------------------------------------------------------------
-- Read Cycle (maximum of CE or Address Change to Valid Data)
-- Note: Minimum 1 extra clock is required to interface from the asynchronous
-- environment to a synchronous environment.
-------------------------------------------------------------------------------
-- C_TCEDV_PS_MEM_x:
-- Read cycle chip enable low to data valid duration of memory bank x
-- C_TAVDV_PS_MEM_x:
-- Read cycle address valid to data valid duration of memory bank x
-- CE ----\
-- \-------------
-- _ _ _ _ _ _
-- Addr __/
-- \_ _ _ _ _ _
--
-- TRD_CLKS_x
-- |<------>|
-- _ _ _ _ _
-- Data _ _ _ _ _ __/
-- \_ _ _ _ _
constant TRD_CLKS_0 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_0,
C_TAVDV_PS_MEM_0))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TRD_CLKS_1 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_1,
C_TAVDV_PS_MEM_1))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TRD_CLKS_2 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_2,
C_TAVDV_PS_MEM_2))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TRD_CLKS_3 : integer range 0 to 31
:= ((max2(1,max2(C_TCEDV_PS_MEM_3,
C_TAVDV_PS_MEM_3))-1)/C_BUS_CLOCK_PERIOD_PS);
-- std logic vector counter for rd_clks_x
constant TRDCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_0+1, 5);
constant TRDCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_1+1, 5);
constant TRDCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_2+1, 5);
constant TRDCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_CLKS_3+1, 5);
-----------------------------------------------------------------------------
-- TRD_TPACC_x: Page access time of memory bank x in page mode flash mode
constant TRD_TPACC_0 :integer range 0 to 31 --:= (0);
:= (C_TPACC_PS_FLASH_0/C_BUS_CLOCK_PERIOD_PS);
constant TRD_TPACC_1 :integer range 0 to 31 --:= (0);
:= (C_TPACC_PS_FLASH_1/C_BUS_CLOCK_PERIOD_PS);
constant TRD_TPACC_2 :integer range 0 to 31 --:= (0);
:= (C_TPACC_PS_FLASH_2/C_BUS_CLOCK_PERIOD_PS);
constant TRD_TPACC_3 :integer range 0 to 31 -- := (0);
:= (C_TPACC_PS_FLASH_3/C_BUS_CLOCK_PERIOD_PS);
-- TRD_TPACC_x: std logic vector counter for Page Access Time
constant TPACC_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_0+1, 5);
constant TPACC_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_1+1, 5);
constant TPACC_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_2+1, 5);
constant TPACC_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TRD_TPACC_3+1, 5);
-------------------------------------------------------------------------------
-- Read Cycle End to Data Bus High Impedance
-------------------------------------------------------------------------------
-- C_THZCE_PS_MEM_x:
-- Read cycle chip enable low to data valid duration of memory bank x
-- C_THZOE_PS_MEM_x:
-- Enable high to data bus high impedance duration of memory bank x
-- CE ----\ /--------
-- \-----------xx-------/
-- OE ----\ /--------
-- \-----------xx-------/
-- THZ_CLKS_x
-- |<------->|
-- _ _ _ _ _ _ _ _ _ _ _
-- Data _ _ _ _ _ __/ \_ _ _ _
-- \_ _ _ _ _ _ _ _ _ _ _/
constant THZ_CLKS_0 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_0,
C_THZOE_PS_MEM_0))-1)/C_BUS_CLOCK_PERIOD_PS);
constant THZ_CLKS_1 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_1,
C_THZOE_PS_MEM_1))-1)/C_BUS_CLOCK_PERIOD_PS);
constant THZ_CLKS_2 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_2,
C_THZOE_PS_MEM_2))-1)/C_BUS_CLOCK_PERIOD_PS);
constant THZ_CLKS_3 : integer range 0 to 31
:= ((max2(1,max2(C_THZCE_PS_MEM_3,
C_THZOE_PS_MEM_3))-1)/C_BUS_CLOCK_PERIOD_PS);
-- HZ counter in std logic vector
constant THZCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_0+1, 5);
constant THZCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_1+1, 5);
constant THZCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_2+1, 5);
constant THZCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(THZ_CLKS_3+1, 5);
-------------------------------------------------------------------------------
-- Write Cycle to Data Store
-------------------------------------------------------------------------------
-- C_TWC_PS_MEM_x:
-- Write cycle time of memory bank x
-- C_TWP_PS_MEM_x:
-- Write enable minimum pulse width duration of memory bank x
constant TWR_CLKS_0 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_0,
C_TWP_PS_MEM_0))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TWR_CLKS_1 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_1,
C_TWP_PS_MEM_1))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TWR_CLKS_2 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_2,
C_TWP_PS_MEM_2))-1)/C_BUS_CLOCK_PERIOD_PS);
constant TWR_CLKS_3 : integer range 0 to 31
:= ((max2(1,max2(C_TWC_PS_MEM_3,
C_TWP_PS_MEM_3))-1)/C_BUS_CLOCK_PERIOD_PS);
-- TWRCNT_x: std logic vector counter for Write cycle Time
constant TWRCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_0, 5);
constant TWRCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_1, 5);
constant TWRCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_2, 5);
constant TWRCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWR_CLKS_3, 5);
-------------------------------------------------------------------------------
-- Write Cycle High Period
-------------------------------------------------------------------------------
constant TWPH_CLKS_0 : integer range 0 to 31
:= (C_TWPH_PS_MEM_0/C_BUS_CLOCK_PERIOD_PS);
constant TWPH_CLKS_1 : integer range 0 to 31
:= (C_TWPH_PS_MEM_1/C_BUS_CLOCK_PERIOD_PS);
constant TWPH_CLKS_2 : integer range 0 to 31
:= (C_TWPH_PS_MEM_2/C_BUS_CLOCK_PERIOD_PS);
constant TWPH_CLKS_3 : integer range 0 to 31
:= (C_TWPH_PS_MEM_3/C_BUS_CLOCK_PERIOD_PS);
-- TWPHCNT_x: std logic vector counter for Write Cycle High Time
constant TWPHCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_0+1, 5);
constant TWPHCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_1+1, 5);
constant TWPHCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_2+1, 5);
constant TWPHCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TWPH_CLKS_3+1, 5);
------------------------------------------------------------------------------
-- Write Cycle End Data Hold Time
-------------------------------------------------------------------------------
-- C_TLZWE_PS_MEM_x:
-- Write cycle write enable high to data bus low impedance
-- duration of memory bank x
-- WE ----\ /--------
-- \------------/
-- TLZ_CLKS_x
-- |<----->|
-- _ _ _ _ _ _ _ _ _ _ _
-- Data __/ \_ _ _ _
-- \_ _ _ _ _ _ _ _ _ _ _/
constant TLZ_CLKS_0 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_0)-1)/C_BUS_CLOCK_PERIOD_PS);
constant TLZ_CLKS_1 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_1)-1)/C_BUS_CLOCK_PERIOD_PS);
constant TLZ_CLKS_2 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_2)-1)/C_BUS_CLOCK_PERIOD_PS);
constant TLZ_CLKS_3 : integer range 0 to 31
:= ((max2(1,C_TLZWE_PS_MEM_3)-1)/C_BUS_CLOCK_PERIOD_PS);
-- TLZCNT_x: std logic vector counter for Write Cycle End Data Hold Time
constant TLZCNT_0 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_0+1, 5);
constant TLZCNT_1 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_1+1, 5);
constant TLZCNT_2 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_2+1, 5);
constant TLZCNT_3 : std_logic_vector(0 to 4)
:= conv_std_logic_vector(TLZ_CLKS_3+1, 5);
--------------------------------------------------------------
-- Write recovery time for Flash. some idle time is needed for Flash memories
-- after write and begin of next consecutive read cycle.
-- TWR_REC_TIME_x: Write recovery time of memory bank x in flash mode
constant TWR_REC_TIME_0 :integer range 0 to 65535 -- 7/4/2011
:= (C_WR_REC_TIME_MEM_0/C_BUS_CLOCK_PERIOD_PS);
constant TWR_REC_TIME_1 :integer range 0 to 65535
:= (C_WR_REC_TIME_MEM_1/C_BUS_CLOCK_PERIOD_PS);
constant TWR_REC_TIME_2 :integer range 0 to 65535
:= (C_WR_REC_TIME_MEM_2/C_BUS_CLOCK_PERIOD_PS);
constant TWR_REC_TIME_3 :integer range 0 to 65535
:= (C_WR_REC_TIME_MEM_3/C_BUS_CLOCK_PERIOD_PS);
constant TP_WR_REC_CNT_0 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_0+1, 16);
constant TP_WR_REC_CNT_1 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_1+1, 16);
constant TP_WR_REC_CNT_2 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_2+1, 16);
constant TP_WR_REC_CNT_3 : std_logic_vector(0 to 15)
:= conv_std_logic_vector(TWR_REC_TIME_3+1, 16);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- Write Cycle Time
signal twr_data : std_logic_vector(0 to 4);
signal twr_load : std_logic;
signal twr_cnt_en : std_logic;
signal twr_end : std_logic;
-- Write Cycle High Time
signal twph_data : std_logic_vector(0 to 4);
signal twph_load : std_logic;
signal twph_cnt_en : std_logic;
signal twph_end : std_logic;
-- Write Cycle End To Data Bus Low-Z
signal tlz_data : std_logic_vector(0 to 4);
signal tlz_load : std_logic;
signal Tlz_cnt_en : std_logic;
signal tlz_end : std_logic;
-- Read Cycle End To Data Bus High-Z
signal thz_data : std_logic_vector(0 to 4);
signal thz_load : std_logic;
signal Thz_cnt_en : std_logic;
signal thz_end : std_logic;
-- Read Cycle Address Change to Valid Data
signal trd_data : std_logic_vector(0 to 4);
signal trd_load : std_logic;
signal trd_cnt_en : std_logic;
signal trd_end : std_logic;
-- Read Cycle Address Change to Valid Data
signal tpacc_data : std_logic_vector(0 to 4);
signal tpacc_load : std_logic;
signal tpacc_cnt_en : std_logic;
signal tpacc_end : std_logic;
-- Write recovery time for flash
-- signal twr_rec_data : std_logic_vector(0 to 4);--7/4/2011
-- signal twr_rec_load : std_logic;
-- signal twr_rec_cnt_en : std_logic;
-- signal twr_rec_end : std_logic;
signal twr_rec_data_int : std_logic_vector(0 to 15);--7/4/2011
signal twr_rec_load_int : std_logic;
signal twr_rec_cnt_en_int : std_logic;
signal twr_rec_end_int : std_logic;
-- Memory Access IPIC Signals
signal bus2ip_cs_reg : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal bus2ip_cs_reg_d1 : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal cs_Strobe : std_logic;
signal new_page_access : std_logic;
signal Parity_enable : std_logic;
signal Parity_type : std_logic;
signal Parity_err_i : std_logic;
signal bus2Mem_CS : std_logic;
signal bus2Mem_RdReq : std_logic;
signal bus2Mem_WrReq : std_logic;
signal mem2Bus_RdAck : std_logic;
signal mem2Bus_WrAck : std_logic;
signal mem2Bus_RdAddrAck : std_logic;
signal mem2Bus_WrAddrAck : std_logic;
signal mem2Bus_Data : std_logic_vector(0 to C_IPIF_DWIDTH - 1);
signal write_req_ack : std_logic;
signal read_req_ack : std_logic;
signal read_data_en : std_logic;
signal read_ack : std_logic;
-- Memory Control Internal Signals
signal mem_CEN_cmb : std_logic;
signal mem_OEN_cmb : std_logic;
signal mem_WEN_cmb : std_logic;
signal bus2ip_ben_int : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal bus2ip_ben_fixed : std_logic_vector(0 to C_IPIF_DWIDTH/8-1);
signal mem_a_int : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal par_error_addr : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal mem_dq_i_int : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_o_int : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_t_int : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_parity_i_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_parity_o_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_parity_t_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_cen_int : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_oen_int : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_wen_int : std_logic;
signal mem_qwen_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_ben_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_rpn_int : std_logic;
signal mem_ce_int : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_adv_ldn_int : std_logic;
signal mem_lbon_int : std_logic;
signal mem_cken_int : std_logic;
signal mem_rnw_int : std_logic;
signal mem_be_int : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
-- Data Width Matching Address Management
signal addr_cnt_ce : std_logic;
signal addr_cnt_rst : std_logic;
signal addr_cnt : std_logic_vector(0 to ADDR_CNTR_WIDTH-1);
signal addr_align : std_logic;
signal addr_align_rd : std_logic;
signal addr_align_write : std_logic;
signal CS_par_addr : std_logic;
signal cycle_cnt_en : std_logic;
signal cycle_cnt_ld : std_logic;
signal cycle_End : std_logic;
signal address_strobe : std_logic;
signal data_strobe : std_logic;
-- Access Parameters
signal mem_width_bytes : std_logic_vector(0 to 3);
signal datawidth_match : std_logic;
signal synch_mem1 : std_logic;
signal two_pipe_delay : std_logic;
signal ip2Bus_RdAck_i : std_logic;
signal IP2Bus_errAck_i : std_logic;
signal Mem_Addr_rst : std_logic;
signal transaction_done_i : std_logic;
signal Bus2IP_Mem_CS_i : std_logic;
signal single_transaction : std_logic;
signal temp_parity_error_adrss: std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal last_burst_cnt : std_logic;
signal Write_req_data_ack : std_logic;
signal Write_req_addr_ack : std_logic;
signal address_strobe_c : std_logic;
signal be_strobe_c : std_logic;
signal data_strobe_c : std_logic;
signal pr_state_wait_temp_cmb : std_logic;
signal ns_idle : std_logic;
signal flash_mem_access_int : std_logic;
signal flash_mem_access_int_1 : std_logic;
signal int_Flash_mem_access_dis : std_logic;
signal Adv_L_N : std_logic;
signal stop_oen : std_logic;
signal bus2ip_ben_all_1 : std_logic;-- 12-12-2012
--signal Linear_flash_brst_rd_flag : std_logic;
--signal Linear_flash_rd_data_ack : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
mem_rpn_int <= not Bus2IP_Reset;
mem_adv_ldn_int <= '0';
mem_lbon_int <= '0';
mem_cken_int <= '0';
IP2Bus_RdAck <= ip2Bus_RdAck_i;
IP2Bus_errAck <= IP2Bus_errAck_i;
Parity_err <= Parity_err_i;
Bus2IP_Mem_CS_i <= or_reduce(Bus2IP_Mem_CS);
---------------------------------------------------------------------------
-- Store the Chip Select Coming from IPIF in case C_NUM_BANKS_MEM > 1
---------------------------------------------------------------------------
CS_STORE_GEN: if (C_NUM_BANKS_MEM > 1) generate
begin
CS_STORE_PROCESS:process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if Bus2IP_Reset = '1' then
bus2ip_cs_reg_d1 <= (others=>'0');
else
bus2ip_cs_reg_d1 <= bus2ip_cs_reg;
end if;
end if;
end process CS_STORE_PROCESS;
bus2ip_cs_reg <= Bus2IP_Mem_CS when (cs_Strobe = '1')
else
bus2ip_cs_reg_d1;
end generate CS_STORE_GEN;
---------------------------------------------------------------------------
-- Pass on the Chip Select Coming from IPIF in case C_NUM_BANKS_MEM = 1
---------------------------------------------------------------------------
CS_PASS_GEN: if (C_NUM_BANKS_MEM = 1) generate
-----
function int_to_std (flash_type: integer) return std_logic is
begin
if (flash_type = 1) then
return '1';
else
return '0';
end if;
end function;
------------------------------------------------------------------------------
begin
-----
bus2ip_cs_reg <= Bus2IP_Mem_CS;
flash_mem_access_int_1 <= int_to_std(FLASH_TYP_MEM);
end generate CS_PASS_GEN;
------------------------------------------------------------------------------
-- Generate single transaction signals for multiple memory banks.
------------------------------------------------------------------------------
SINGLE_BURST_GEN_PROCESS: process(Bus2IP_Mem_CS,
bus2ip_burst,
Bus2IP_BurstLength)is
-----
begin
-----
single_transaction <= '0';
for i in 0 to C_NUM_BANKS_MEM -1 loop
if(Bus2IP_Mem_CS(i) = '1' and
--bus2ip_burst= '0' and
or_reduce(Bus2IP_BurstLength) = '0') then -- = "00000000") then
single_transaction <= '1';
end if;
end loop;
end process SINGLE_BURST_GEN_PROCESS;
----------------------------------------------------------------
MULTIPLE_MEM_FLASH_ACCESS_GEN: if (C_NUM_BANKS_MEM > 1) generate
-----
begin
-----
REG_FLASH_ACCESS: process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(flash_mem_access_int = '1') then
flash_mem_access_int_1 <= '1';
elsif(Bus2IP_Reset = '1' or int_Flash_mem_access_dis = '1')then
flash_mem_access_int_1 <= '0';
end if;
end if;
end process REG_FLASH_ACCESS;
FLASH_ACCESS_PROCESS: process (Bus2IP_Mem_CS) is
-----
begin
-----
flash_mem_access_int <= '0';
for i in 0 to C_NUM_BANKS_MEM -1 loop
if((Bus2IP_Mem_CS(i) = '1') and
((C_FLASH_TYPE_MEM(i) = 2)or -- check if the memory is flash,page mode flash
(C_FLASH_TYPE_MEM(i) = 3)or
(C_FLASH_TYPE_MEM(i) = 4)or
(C_FLASH_TYPE_MEM(i) = 5)
)) then
flash_mem_access_int <= '1';
--else
-- flash_mem_access_int <= '0';
end if;
end loop;
end process FLASH_ACCESS_PROCESS;
---------------------------------
end generate MULTIPLE_MEM_FLASH_ACCESS_GEN;
-------------------------------------------
-------------------------------------------------------------------------------
-- IPIC Interface
-------------------------------------------------------------------------------
IPIC_IF_I : entity emc_common_v3_0.ipic_if
generic map (
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_IPIF_DWIDTH => C_IPIF_DWIDTH
)
port map (
Bus2IP_Clk => Bus2IP_Clk ,
Bus2IP_Reset => Bus2IP_Reset ,
Bus2IP_RNW => Bus2IP_RNW ,-- in std_logic;
Bus2IP_Mem_CS => Bus2IP_Mem_CS ,-- in std_logic_vector
Mem2Bus_RdAddrAck => mem2Bus_RdAddrAck ,-- in std_logic;
Mem2Bus_WrAddrAck => mem2Bus_WrAddrAck ,-- in std_logic;
Mem2Bus_RdAck => mem2Bus_RdAck ,-- in std_logic;
Mem2Bus_WrAck => mem2Bus_WrAck ,-- in std_logic;
Mem2Bus_Data => mem2Bus_Data ,-- in std_logic;
Bus2IP_WrReq => Bus2IP_WrReq ,-- in std_logic;
Bus2IP_RdReq => Bus2IP_RdReq ,-- in std_logic_vector
Bus2IP_Burst => bus2ip_burst ,-- in std_logic;
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc ,-- in std_logic;
Bus2IP_WrReq_emc => Bus2IP_WrReq_emc ,-- in std_logic;
Bus2Mem_CS => bus2Mem_CS ,-- out std_logic;
Bus2Mem_RdReq => bus2Mem_RdReq ,-- out std_logic;
Bus2Mem_WrReq => bus2Mem_WrReq ,-- out std_logic;
Parity_err => Parity_err_i ,-- in std_logic;
IP2Bus_Data => IP2Bus_Data ,-- out std_logic_vector
IP2Bus_errAck => IP2Bus_errAck_i ,-- out std_logic;
IP2Bus_retry => IP2Bus_retry ,-- out std_logic;
IP2Bus_toutSup => IP2Bus_toutSup ,-- out std_logic;
IP2Bus_RdAck => ip2Bus_RdAck_i ,-- out std_logic;
IP2Bus_WrAck => IP2Bus_WrAck ,-- out std_logic;
IP2Bus_AddrAck => IP2Bus_AddrAck ,-- out std_logic;
Type_of_xfer => Type_of_xfer ,-- in std_logic;
Burst_length => Bus2IP_BurstLength ,-- in std_logic_vector(
Transaction_done => transaction_done_i ,-- in std_logic;
single_transaction=> single_transaction ,-- in std_logic;
last_burst_cnt => last_burst_cnt ,-- out std_logic;
pr_state_wait_temp_cmb => pr_state_wait_temp_cmb ,
Synch_mem => synch_mem1 ,
Mem_width_bytes => mem_width_bytes , -- 10-12-2012
stop_oen => stop_oen , -- 10-12-2012
axi_trans_size_reg => axi_trans_size_reg ,-- 1/3/2013
Linear_flash_brst_rd_flag=> Linear_flash_brst_rd_flag -- 1/28/2013
);
-------------------------------------------------------------------------------
-- Memory State Machine
-------------------------------------------------------------------------------
MEM_STATE_MACHINE_I : entity emc_common_v3_0.mem_state_machine
port map (
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_RdReq => bus2Mem_RdReq,
Bus2IP_WrReq => Bus2Mem_WrReq,
original_wrce => original_wrce,
--flash_mem_access => flash_mem_access_int,
Synch_mem => synch_mem1,
Two_pipe_delay => two_pipe_delay,
Cycle_End => cycle_End,
Bus2IP_Mem_CS => Bus2IP_Mem_CS_i,
Bus2IP_Burst => bus2ip_burst,
Read_data_en => read_data_en,
Read_ack => read_ack,
Address_strobe => address_strobe,
-- Data_strobe => data_strobe,09-12-2012
CS_Strobe => cs_Strobe,
axi_wvalid => axi_wvalid,
axi_wlast => axi_wlast,
Addr_cnt_ce => addr_cnt_ce,
Addr_cnt_rst => addr_cnt_rst,
Cycle_cnt_ld => cycle_cnt_ld,
Cycle_cnt_en => cycle_cnt_en,
single_trans => single_transaction,
Trd_cnt_en => trd_cnt_en,
Twr_cnt_en => twr_cnt_en,
Twph_cnt_en => twph_cnt_en,
Tpacc_cnt_en => tpacc_cnt_en,
Trd_load => trd_load,
Twr_load => twr_load,
Twph_load => twph_load,
Tpacc_load => tpacc_load,
Thz_load => thz_load,
Tlz_load => tlz_load,
Trd_end => trd_end,
Twr_end => twr_end,
Twph_end => twph_end,
Thz_end => thz_end,
Tlz_end => tlz_end,
Tpacc_end => Tpacc_end,
New_page_access => new_page_access,
Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack => Linear_flash_rd_data_ack,
MSM_Mem_CEN => mem_CEN_cmb,
MSM_Mem_OEN => mem_OEN_cmb,
MSM_Mem_WEN => mem_WEN_cmb,
CS_Strobe_par_addr => CS_par_addr,
Addr_align => addr_align_write,
Addr_align_rd => addr_align_rd,
Write_req_ack => write_req_ack,
Read_req_ack => read_req_ack,
Transaction_done => transaction_done_i,
Mem_Addr_rst => Mem_Addr_rst,
last_burst_cnt => last_burst_cnt,
Write_req_data_ack => Write_req_data_ack,
Write_req_addr_ack => Write_req_addr_ack,
address_strobe_c => address_strobe_c,
be_strobe_c => be_strobe_c,
data_strobe_c => data_strobe_c,
ns_idle => ns_idle ,
pr_state_wait_temp_cmb => pr_state_wait_temp_cmb,
Twr_rec_load => twr_rec_load_int ,
Twr_rec_cnt_en => twr_rec_cnt_en_int,
Twr_rec_end => twr_rec_end_int,
Flash_mem_access_disable => int_Flash_mem_access_dis, --
Flash_mem_access => flash_mem_access_int_1, --Flash_mem_access_int
Mem_WAIT => Mem_WAIT,
Adv_L_N => Adv_L_N,
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc, -- 17-10-2012
last_addr1 => last_addr1,
stop_oen => stop_oen,
pr_idle => pr_idle, -- 11-12-2012
bus2ip_ben_all_1 => bus2ip_ben_all_1
--Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag,
--Linear_flash_rd_data_ack => Linear_flash_rd_data_ack
);
bus2ip_ben_fixed <= (others=>'0') when Type_of_xfer = '0'
else
Bus2IP_BE;
bus2ip_ben_all_1 <= and_reduce(Bus2IP_BE);-- 13-12-2012
parity_error_adrss <= temp_parity_error_adrss when (ip2Bus_RdAck_i = '1' and IP2Bus_errAck_i = '1') else (others => '0');
-------------------------------------------------------------------------------
-- Datawidth Matching Address Counter
-------------------------------------------------------------------------------
ADDR_COUNTER_MUX_I : entity emc_common_v3_0.addr_counter_mux
generic map (
C_ADDR_CNTR_WIDTH => ADDR_CNTR_WIDTH,
C_IPIF_DWIDTH => C_IPIF_DWIDTH,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_ADDR_OFFSET => ADDR_OFFSET,
PARITY_TYPE_MEMORY => PARITY_TYPE_MEMORY,
C_GLOBAL_DATAWIDTH_MATCH => GLOBAL_DATAWIDTH_MATCH
)
port map (
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_BE => bus2ip_ben_fixed,
Address_strobe => address_strobe,
--Data_strobe => data_strobe,09-12-2012
Mem_width_bytes => mem_width_bytes,
Datawidth_match => datawidth_match,
Bus2Mem_CS => bus2Mem_CS,
Addr_cnt_ce => addr_cnt_ce,
Addr_cnt_rst => addr_cnt_rst,
Addr_cnt => addr_cnt,
Addr_align => addr_align_write,
CS_par_addr => CS_par_addr,
par_error_addr => temp_parity_error_adrss,
Cycle_cnt_ld => cycle_cnt_ld,
Cycle_cnt_en => cycle_cnt_en,
Cycle_End => cycle_End,
Mem_addr => Mem_A_int,
Mem_Ben => bus2ip_ben_int,
address_strobe_c => address_strobe_c,
be_strobe_c => be_strobe_c ,
data_strobe_c => data_strobe_c,
Cre_reg_en => Cre_reg_en,
Bus2IP_RdReq => bus2Mem_RdReq, -- 17-10-2012
psram_page_mode => psram_page_mode,
axi_trans_size_reg => axi_trans_size_reg -- 1/17/2013
);
-------------------------------------------------------------------------------
-- Asynchronous Memory Cycle Timers
-------------------------------------------------------------------------------
COUNTERS_I: entity emc_common_v3_0.counters
port map (
Synch_mem => synch_mem1,
Twr_data => twr_data,
Twr_load => twr_load,
Twr_cnt_en => twr_cnt_en,
twph_data => twph_data,
twph_load => twph_load,
twph_cnt_en => twph_cnt_en,
Tlz_data => tlz_data,
Tlz_load => tlz_load,
Trd_data => trd_data,
Trd_load => trd_load,
Trd_cnt_en => trd_cnt_en,
Tpacc_data => tpacc_data,
Tpacc_load => tpacc_load,
Tpacc_cnt_en => tpacc_cnt_en,
Thz_data => thz_data,
Thz_load => thz_load,
Twr_end => twr_end,
Twph_end => twph_end,
Tlz_end => tlz_end,
Trd_end => trd_end,
Thz_end => thz_end,
Tpacc_end => Tpacc_end,
--------------------------
Twr_rec_data => twr_rec_data_int ,
Twr_rec_load => twr_rec_load_int ,
Twr_rec_cnt_en => twr_rec_cnt_en_int,
Twr_rec_end => twr_rec_end_int ,
--------------------------
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset
);
-------------------------------------------------------------------------------
-- Memory Paramter Selector
-------------------------------------------------------------------------------
SELECT_PARAM_I: entity emc_common_v3_0.select_param
generic map (
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_GLOBAL_SYNC_MEM => GLOBAL_SYNC_MEM,
C_SYNCH_MEM_0 => C_SYNCH_MEM_0,
C_SYNCH_MEM_1 => C_SYNCH_MEM_1,
C_SYNCH_MEM_2 => C_SYNCH_MEM_2,
C_SYNCH_MEM_3 => C_SYNCH_MEM_3,
C_MEM0_WIDTH => C_MEM0_WIDTH,
C_MEM1_WIDTH => C_MEM1_WIDTH,
C_MEM2_WIDTH => C_MEM2_WIDTH,
C_MEM3_WIDTH => C_MEM3_WIDTH,
C_PAGEMODE_FLASH => PAGEMODE_FLASH,
C_PAGEMODE_FLASH_0 => C_PAGEMODE_FLASH_0,
C_PAGEMODE_FLASH_1 => C_PAGEMODE_FLASH_1,
C_PAGEMODE_FLASH_2 => C_PAGEMODE_FLASH_2,
C_PAGEMODE_FLASH_3 => C_PAGEMODE_FLASH_3,
PARITY_TYPE_MEMORY => PARITY_TYPE_MEMORY,
C_PARITY_TYPE_0 => C_PARITY_TYPE_0,
C_PARITY_TYPE_1 => C_PARITY_TYPE_1,
C_PARITY_TYPE_2 => C_PARITY_TYPE_2,
C_PARITY_TYPE_3 => C_PARITY_TYPE_3,
C_SYNCH_PIPEDELAY_0 => C_SYNCH_PIPEDELAY_0,
C_SYNCH_PIPEDELAY_1 => C_SYNCH_PIPEDELAY_1,
C_SYNCH_PIPEDELAY_2 => C_SYNCH_PIPEDELAY_2,
C_SYNCH_PIPEDELAY_3 => C_SYNCH_PIPEDELAY_3,
C_GLOBAL_DATAWIDTH_MATCH => GLOBAL_DATAWIDTH_MATCH,
C_INCLUDE_DATAWIDTH_MATCHING_0 => C_INCLUDE_DATAWIDTH_MATCHING_0,
C_INCLUDE_DATAWIDTH_MATCHING_1 => C_INCLUDE_DATAWIDTH_MATCHING_1,
C_INCLUDE_DATAWIDTH_MATCHING_2 => C_INCLUDE_DATAWIDTH_MATCHING_2,
C_INCLUDE_DATAWIDTH_MATCHING_3 => C_INCLUDE_DATAWIDTH_MATCHING_3,
TRDCNT_0 => TRDCNT_0,
TRDCNT_1 => TRDCNT_1,
TRDCNT_2 => TRDCNT_2,
TRDCNT_3 => TRDCNT_3,
THZCNT_0 => THZCNT_0,
THZCNT_1 => THZCNT_1,
THZCNT_2 => THZCNT_2,
THZCNT_3 => THZCNT_3,
TWRCNT_0 => TWRCNT_0,
TWRCNT_1 => TWRCNT_1,
TWRCNT_2 => TWRCNT_2,
TWRCNT_3 => TWRCNT_3,
TWPHCNT_0 => TWPHCNT_0,
TWPHCNT_1 => TWPHCNT_1,
TWPHCNT_2 => TWPHCNT_2,
TWPHCNT_3 => TWPHCNT_3,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_IPIF_DWIDTH => C_IPIF_DWIDTH,
TPACC_0 => TPACC_0,
TPACC_1 => TPACC_1,
TPACC_2 => TPACC_2,
TPACC_3 => TPACC_3,
TLZCNT_0 => TLZCNT_0,
TLZCNT_1 => TLZCNT_1,
TLZCNT_2 => TLZCNT_2,
TLZCNT_3 => TLZCNT_3,
TP_WR_REC_CNT_0 => TP_WR_REC_CNT_0,--7/4/2011
TP_WR_REC_CNT_1 => TP_WR_REC_CNT_1,
TP_WR_REC_CNT_2 => TP_WR_REC_CNT_2,
TP_WR_REC_CNT_3 => TP_WR_REC_CNT_3
)
port map (
Bus2IP_Mem_CS => bus2ip_cs_reg,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => Bus2IP_Reset,
Bus2IP_RNW => Bus2IP_RNW,
psram_page_mode => psram_page_mode,
New_page_access => new_page_access,
Parity_enable => Parity_enable,
Parity_type => Parity_type,
Twr_data => twr_data,
Twph_data => twph_data,
Tlz_data => tlz_data,
Trd_data => trd_data,
Thz_data => thz_data,
Tpacc_data => tpacc_data,
Twr_rec_data => twr_rec_data_int,-- 9/6/2011
Synch_mem => synch_mem1,
Mem_width_bytes => mem_width_bytes,
Two_pipe_delay => two_pipe_delay,
Datawidth_match => datawidth_match
);
-------------------------------------------------------------------------------
-- Memory Data/Control Steering Logic
-------------------------------------------------------------------------------
MEM_STEER_I : entity emc_common_v3_0.mem_steer
generic map(
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM,
C_MAX_MEM_WIDTH => C_MAX_MEM_WIDTH,
C_MIN_MEM_WIDTH => MIN_MEM_WIDTH,
C_IPIF_DWIDTH => C_IPIF_DWIDTH,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_ADDR_CNTR_WIDTH => ADDR_CNTR_WIDTH,
C_PARITY_TYPE_MEMORY => PARITY_TYPE_MEMORY,
C_GLOBAL_SYNC_MEM => GLOBAL_SYNC_MEM,
C_GLOBAL_DATAWIDTH_MATCH => GLOBAL_DATAWIDTH_MATCH
)
port map(
--
--Clk => Bus2IP_Clk,
--Rst => Bus2IP_Reset
Clk => Bus2IP_Clk,
Rst => Bus2IP_Reset,
Bus2IP_Data => Bus2IP_Data, -- in std_logic_vector
Bus2IP_BE => bus2ip_ben_int, -- in std_logic_vector
Bus2IP_Mem_CS => bus2ip_cs_reg, -- in std_logic_vector
Bus2IP_RdReq => bus2Mem_RdReq, -- in std_logic;
Bus2IP_Burst => bus2ip_burst, -- in std_logic;
Write_req_ack => write_req_ack, -- in std_logic;
Read_req_ack => read_req_ack, -- in std_logic;
Read_ack => read_ack, -- in std_logic;
Read_data_en => read_data_en, -- in std_logic;
--Data_strobe => data_strobe, -- in std_logic;09-12-2012
MSM_Mem_CEN => mem_CEN_cmb, -- in std_logic;
MSM_Mem_OEN => mem_OEN_cmb, -- in std_logic;
MSM_Mem_WEN => mem_WEN_cmb, -- in std_logic;
Mem2Bus_WrAddrAck => mem2Bus_WrAddrAck,-- out std_logic;
Mem2Bus_WrAck => mem2Bus_WrAck, -- out std_logic;
Mem2Bus_RdAddrAck => mem2Bus_RdAddrAck,-- out std_logic;
Mem2Bus_RdAck => mem2Bus_RdAck, -- out std_logic;
Mem2Bus_Data => mem2Bus_Data, -- out std_logic_vector
Mem_width_bytes => mem_width_bytes, -- in std_logic_vector
Synch_mem => synch_mem1, -- in std_logic;
Two_pipe_delay => two_pipe_delay, -- in std_logic;
single_transaction => single_transaction,-- in std_logic;
Parity_enable => Parity_enable, -- out std_logic_vector
Parity_type => Parity_type, -- in std_logic;
parity_error_mem => parity_error_mem, -- in std_logic;
Parity_err => Parity_err_i, -- out std_logic;
Addr_cnt => addr_cnt, -- in std_logic_vector
Addr_align => addr_align_write, -- in std_logic
Addr_align_rd => addr_align_rd, -- in std_logic
MemSteer_Mem_DQ_I => mem_dq_i_int, -- in std_logic_vector
MemSteer_Mem_DQ_O => mem_dq_o_int, -- out std_logic_vector
MemSteer_Mem_DQ_T => mem_dq_t_int, -- out std_logic_vector
MemSteer_Mem_DQ_prty_I => mem_dq_parity_i_int,-- in std_logic_vector
MemSteer_Mem_DQ_prty_O => mem_dq_parity_o_int,-- out std_logic_vector
MemSteer_Mem_DQ_prty_T => mem_dq_parity_t_int,-- out std_logic_vector
MemSteer_Mem_CEN => mem_cen_int, -- out std_logic_vector
MemSteer_Mem_OEN => mem_oen_int, -- out std_logic_vector
MemSteer_Mem_WEN => mem_wen_int, -- out std_logic
MemSteer_Mem_QWEN => mem_qwen_int, -- out std_logic_vector
MemSteer_Mem_BEN => mem_ben_int, -- out std_logic_vector
MemSteer_Mem_CE => mem_ce_int, -- out std_logic_vector
MemSteer_Mem_RNW => mem_rnw_int, -- out std_logic
Bus2IP_RdReq_emc => Bus2IP_RdReq_emc, -- in std_logic;
Bus2IP_WrReq_emc => Bus2IP_WrReq_emc, -- in std_logic;
Write_req_data_ack => Write_req_data_ack,
Write_req_addr_ack => Write_req_addr_ack,
address_strobe_c => address_strobe_c, --- in
be_strobe_c => be_strobe_c , -- in
data_strobe_c => data_strobe_c, -- in
ns_idle => ns_idle , -- in
Linear_flash_brst_rd_flag => Linear_flash_brst_rd_flag,
Linear_flash_rd_data_ack => Linear_flash_rd_data_ack,
last_addr => last_addr1, -- 10-12-2012
stop_oen => stop_oen ,-- 10-12-2012
cycle_end => cycle_End ,
axi_arsize => axi_arsize,
axi_trans_size_reg => axi_trans_size_reg
);
-------------------------------------------------------------------------------
-- Instantiate the IO register block to memory
-- IO registers will be instantiated based on the parameter settings
-------------------------------------------------------------------------------
IO_REGISTERS_I: entity emc_common_v3_0.io_registers
generic map (
--C_FLASH_SYNC_RD => C_FLASH_SYNC_RD,
C_INCLUDE_NEGEDGE_IOREGS => C_INCLUDE_NEGEDGE_IOREGS,
C_IPIF_AWIDTH => C_IPIF_AWIDTH,
C_MAX_MEM_WIDTH => C_MAX_MEM_WIDTH,
C_NUM_BANKS_MEM => C_NUM_BANKS_MEM
)
port map (
Linear_flash_brst_rd_flag=> Linear_flash_brst_rd_flag, -- 1/28/2013
Clk => Bus2IP_Clk, --in std_logic
RdClk => RdClk, --in std_logic
Rst => Bus2IP_Reset, --in std_logic
Mem_A_int => mem_a_int, --in std_logic_vector
Mem_DQ_I_int => mem_dq_i_int, --out std_logic_vector
Mem_DQ_O_int => mem_dq_o_int, --in std_logic_vector
Mem_DQ_T_int => mem_dq_t_int, --in std_logic_vector
Mem_DQ_PARITY_I_int => mem_dq_parity_i_int, --out std_logic_vector
Mem_DQ_PARITY_O_int => mem_dq_parity_o_int, --in std_logic_vector
Mem_DQ_PARITY_T_int => mem_dq_parity_t_int, --in std_logic_vector
Mem_CEN_int => mem_cen_int, --in std_logic_vector
Mem_OEN_int => mem_oen_int, --in std_logic_vector
Mem_WEN_int => mem_wen_int, --in std_logic;
Mem_QWEN_int => mem_qwen_int, --in std_logic_vector
Mem_BEN_int => mem_ben_int, --in std_logic_vector
Mem_RPN_int => mem_rpn_int, --in std_logic;
Mem_CE_int => mem_ce_int, --in std_logic_vector
Mem_ADV_LDN_int => mem_adv_ldn_int, --in std_logic;
Mem_LBON_int => mem_lbon_int, --in std_logic;
Mem_CKEN_int => mem_cken_int, --in std_logic;
Mem_RNW_int => mem_rnw_int, --in std_logic;
Mem_Addr_rst => Mem_Addr_rst, --in std_logic
--Linear_flash_rd_data_ack => Linear_flash_rd_data_ack, -- out std_logic;
Mem_A => Mem_A, --out std_logic_vector
Mem_DQ_I => Mem_DQ_I, --in std_logic_vector
Mem_DQ_O => Mem_DQ_O, --out std_logic_vector
Mem_DQ_T => Mem_DQ_T, --out std_logic_vector
Mem_DQ_PRTY_I => Mem_DQ_PRTY_I, --in std_logic_vector
Mem_DQ_PRTY_O => Mem_DQ_PRTY_O, --out std_logic_vector
Mem_DQ_PRTY_T => Mem_DQ_PRTY_T, --out std_logic_vector
Mem_CEN => Mem_CEN, --out std_logic_vector
Mem_OEN => Mem_OEN, --out std_logic_vector
Mem_WEN => Mem_WEN, --out std_logic;
Mem_QWEN => Mem_QWEN, --out std_logic_vector
Mem_BEN => Mem_BEN, --out std_logic_vector
Mem_RPN => Mem_RPN, --out std_logic;
Mem_CE => Mem_CE, --out std_logic_vector
Mem_ADV_LDN => Mem_ADV_LDN, --out std_logic;
Mem_LBON => Mem_LBON, --out std_logic;
Mem_CKEN => Mem_CKEN, --out std_logic;
Mem_RNW => Mem_RNW --out std_logic
--Mem_WAIT => Mem_WAIT, --in std_logic
--Mem_Flash_clk => Mem_Flash_clk --in std_logic
);
synch_mem12 <= synch_mem1;
end architecture imp;
-------------------------------------------------------------------------------
-- End of File emc.vhd
-------------------------------------------------------------------------------
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/ld_arith_reg.vhd
|
8
|
14864
|
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/01 -- First version
--
-- FO 11/14/01 -- Cosmetic improvements
--
-- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/ld_arith_reg.vhd
|
8
|
14864
|
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/01 -- First version
--
-- FO 11/14/01 -- Cosmetic improvements
--
-- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/counter_f.vhd
|
14
|
9766
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
INFERRED_GEN : if (true) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_emc_v3_0/a61d85ec/hdl/src/vhdl/counter_f.vhd
|
14
|
9766
|
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
INFERRED_GEN : if (true) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/synth/design_1_mdm_1_0.vhd
|
2
|
62904
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mdm:3.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mdm_v3_2;
USE mdm_v3_2.MDM;
ENTITY design_1_mdm_1_0 IS
PORT (
Debug_SYS_Rst : OUT STD_LOGIC;
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC
);
END design_1_mdm_1_0;
ARCHITECTURE design_1_mdm_1_0_arch OF design_1_mdm_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_mdm_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT MDM IS
GENERIC (
C_FAMILY : STRING;
C_JTAG_CHAIN : INTEGER;
C_USE_BSCAN : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_INTERCONNECT : INTEGER;
C_MB_DBG_PORTS : INTEGER;
C_USE_UART : INTEGER;
C_DBG_REG_ACCESS : INTEGER;
C_DBG_MEM_ACCESS : INTEGER;
C_USE_CROSS_TRIGGER : INTEGER;
C_TRACE_OUTPUT : INTEGER;
C_TRACE_DATA_WIDTH : INTEGER;
C_TRACE_CLK_FREQ_HZ : INTEGER;
C_TRACE_CLK_OUT_PHASE : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_THREAD_ID_WIDTH : INTEGER;
C_DATA_SIZE : INTEGER;
C_M_AXIS_DATA_WIDTH : INTEGER;
C_M_AXIS_ID_WIDTH : INTEGER
);
PORT (
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
M_AXI_ACLK : IN STD_LOGIC;
M_AXI_ARESETN : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_ARESETN : IN STD_LOGIC;
Interrupt : OUT STD_LOGIC;
Ext_BRK : OUT STD_LOGIC;
Ext_NM_BRK : OUT STD_LOGIC;
Debug_SYS_Rst : OUT STD_LOGIC;
Trig_In_0 : IN STD_LOGIC;
Trig_Ack_In_0 : OUT STD_LOGIC;
Trig_Out_0 : OUT STD_LOGIC;
Trig_Ack_Out_0 : IN STD_LOGIC;
Trig_In_1 : IN STD_LOGIC;
Trig_Ack_In_1 : OUT STD_LOGIC;
Trig_Out_1 : OUT STD_LOGIC;
Trig_Ack_Out_1 : IN STD_LOGIC;
Trig_In_2 : IN STD_LOGIC;
Trig_Ack_In_2 : OUT STD_LOGIC;
Trig_Out_2 : OUT STD_LOGIC;
Trig_Ack_Out_2 : IN STD_LOGIC;
Trig_In_3 : IN STD_LOGIC;
Trig_Ack_In_3 : OUT STD_LOGIC;
Trig_Out_3 : OUT STD_LOGIC;
Trig_Ack_Out_3 : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
M_AXI_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWLOCK : OUT STD_LOGIC;
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARLOCK : OUT STD_LOGIC;
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RREADY : OUT STD_LOGIC;
LMB_Data_Addr_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_0 : OUT STD_LOGIC;
LMB_Ready_0 : IN STD_LOGIC;
LMB_Byte_Enable_0 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_0 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_0 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_0 : OUT STD_LOGIC;
LMB_Write_Strobe_0 : OUT STD_LOGIC;
LMB_CE_0 : IN STD_LOGIC;
LMB_UE_0 : IN STD_LOGIC;
LMB_Wait_0 : IN STD_LOGIC;
LMB_Data_Addr_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_1 : OUT STD_LOGIC;
LMB_Ready_1 : IN STD_LOGIC;
LMB_Byte_Enable_1 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_1 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_1 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_1 : OUT STD_LOGIC;
LMB_Write_Strobe_1 : OUT STD_LOGIC;
LMB_CE_1 : IN STD_LOGIC;
LMB_UE_1 : IN STD_LOGIC;
LMB_Wait_1 : IN STD_LOGIC;
LMB_Data_Addr_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_2 : OUT STD_LOGIC;
LMB_Ready_2 : IN STD_LOGIC;
LMB_Byte_Enable_2 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_2 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_2 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_2 : OUT STD_LOGIC;
LMB_Write_Strobe_2 : OUT STD_LOGIC;
LMB_CE_2 : IN STD_LOGIC;
LMB_UE_2 : IN STD_LOGIC;
LMB_Wait_2 : IN STD_LOGIC;
LMB_Data_Addr_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_3 : OUT STD_LOGIC;
LMB_Ready_3 : IN STD_LOGIC;
LMB_Byte_Enable_3 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_3 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_3 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_3 : OUT STD_LOGIC;
LMB_Write_Strobe_3 : OUT STD_LOGIC;
LMB_CE_3 : IN STD_LOGIC;
LMB_UE_3 : IN STD_LOGIC;
LMB_Wait_3 : IN STD_LOGIC;
LMB_Data_Addr_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_4 : OUT STD_LOGIC;
LMB_Ready_4 : IN STD_LOGIC;
LMB_Byte_Enable_4 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_4 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_4 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_4 : OUT STD_LOGIC;
LMB_Write_Strobe_4 : OUT STD_LOGIC;
LMB_CE_4 : IN STD_LOGIC;
LMB_UE_4 : IN STD_LOGIC;
LMB_Wait_4 : IN STD_LOGIC;
LMB_Data_Addr_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_5 : OUT STD_LOGIC;
LMB_Ready_5 : IN STD_LOGIC;
LMB_Byte_Enable_5 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_5 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_5 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_5 : OUT STD_LOGIC;
LMB_Write_Strobe_5 : OUT STD_LOGIC;
LMB_CE_5 : IN STD_LOGIC;
LMB_UE_5 : IN STD_LOGIC;
LMB_Wait_5 : IN STD_LOGIC;
LMB_Data_Addr_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_6 : OUT STD_LOGIC;
LMB_Ready_6 : IN STD_LOGIC;
LMB_Byte_Enable_6 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_6 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_6 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_6 : OUT STD_LOGIC;
LMB_Write_Strobe_6 : OUT STD_LOGIC;
LMB_CE_6 : IN STD_LOGIC;
LMB_UE_6 : IN STD_LOGIC;
LMB_Wait_6 : IN STD_LOGIC;
LMB_Data_Addr_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_7 : OUT STD_LOGIC;
LMB_Ready_7 : IN STD_LOGIC;
LMB_Byte_Enable_7 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_7 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_7 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_7 : OUT STD_LOGIC;
LMB_Write_Strobe_7 : OUT STD_LOGIC;
LMB_CE_7 : IN STD_LOGIC;
LMB_UE_7 : IN STD_LOGIC;
LMB_Wait_7 : IN STD_LOGIC;
LMB_Data_Addr_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_8 : OUT STD_LOGIC;
LMB_Ready_8 : IN STD_LOGIC;
LMB_Byte_Enable_8 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_8 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_8 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_8 : OUT STD_LOGIC;
LMB_Write_Strobe_8 : OUT STD_LOGIC;
LMB_CE_8 : IN STD_LOGIC;
LMB_UE_8 : IN STD_LOGIC;
LMB_Wait_8 : IN STD_LOGIC;
LMB_Data_Addr_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_9 : OUT STD_LOGIC;
LMB_Ready_9 : IN STD_LOGIC;
LMB_Byte_Enable_9 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_9 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_9 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_9 : OUT STD_LOGIC;
LMB_Write_Strobe_9 : OUT STD_LOGIC;
LMB_CE_9 : IN STD_LOGIC;
LMB_UE_9 : IN STD_LOGIC;
LMB_Wait_9 : IN STD_LOGIC;
LMB_Data_Addr_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_10 : OUT STD_LOGIC;
LMB_Ready_10 : IN STD_LOGIC;
LMB_Byte_Enable_10 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_10 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_10 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_10 : OUT STD_LOGIC;
LMB_Write_Strobe_10 : OUT STD_LOGIC;
LMB_CE_10 : IN STD_LOGIC;
LMB_UE_10 : IN STD_LOGIC;
LMB_Wait_10 : IN STD_LOGIC;
LMB_Data_Addr_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_11 : OUT STD_LOGIC;
LMB_Ready_11 : IN STD_LOGIC;
LMB_Byte_Enable_11 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_11 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_11 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_11 : OUT STD_LOGIC;
LMB_Write_Strobe_11 : OUT STD_LOGIC;
LMB_CE_11 : IN STD_LOGIC;
LMB_UE_11 : IN STD_LOGIC;
LMB_Wait_11 : IN STD_LOGIC;
LMB_Data_Addr_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_12 : OUT STD_LOGIC;
LMB_Ready_12 : IN STD_LOGIC;
LMB_Byte_Enable_12 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_12 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_12 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_12 : OUT STD_LOGIC;
LMB_Write_Strobe_12 : OUT STD_LOGIC;
LMB_CE_12 : IN STD_LOGIC;
LMB_UE_12 : IN STD_LOGIC;
LMB_Wait_12 : IN STD_LOGIC;
LMB_Data_Addr_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_13 : OUT STD_LOGIC;
LMB_Ready_13 : IN STD_LOGIC;
LMB_Byte_Enable_13 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_13 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_13 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_13 : OUT STD_LOGIC;
LMB_Write_Strobe_13 : OUT STD_LOGIC;
LMB_CE_13 : IN STD_LOGIC;
LMB_UE_13 : IN STD_LOGIC;
LMB_Wait_13 : IN STD_LOGIC;
LMB_Data_Addr_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_14 : OUT STD_LOGIC;
LMB_Ready_14 : IN STD_LOGIC;
LMB_Byte_Enable_14 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_14 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_14 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_14 : OUT STD_LOGIC;
LMB_Write_Strobe_14 : OUT STD_LOGIC;
LMB_CE_14 : IN STD_LOGIC;
LMB_UE_14 : IN STD_LOGIC;
LMB_Wait_14 : IN STD_LOGIC;
LMB_Data_Addr_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_15 : OUT STD_LOGIC;
LMB_Ready_15 : IN STD_LOGIC;
LMB_Byte_Enable_15 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_15 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_15 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_15 : OUT STD_LOGIC;
LMB_Write_Strobe_15 : OUT STD_LOGIC;
LMB_CE_15 : IN STD_LOGIC;
LMB_UE_15 : IN STD_LOGIC;
LMB_Wait_15 : IN STD_LOGIC;
LMB_Data_Addr_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_16 : OUT STD_LOGIC;
LMB_Ready_16 : IN STD_LOGIC;
LMB_Byte_Enable_16 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_16 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_16 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_16 : OUT STD_LOGIC;
LMB_Write_Strobe_16 : OUT STD_LOGIC;
LMB_CE_16 : IN STD_LOGIC;
LMB_UE_16 : IN STD_LOGIC;
LMB_Wait_16 : IN STD_LOGIC;
LMB_Data_Addr_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_17 : OUT STD_LOGIC;
LMB_Ready_17 : IN STD_LOGIC;
LMB_Byte_Enable_17 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_17 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_17 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_17 : OUT STD_LOGIC;
LMB_Write_Strobe_17 : OUT STD_LOGIC;
LMB_CE_17 : IN STD_LOGIC;
LMB_UE_17 : IN STD_LOGIC;
LMB_Wait_17 : IN STD_LOGIC;
LMB_Data_Addr_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_18 : OUT STD_LOGIC;
LMB_Ready_18 : IN STD_LOGIC;
LMB_Byte_Enable_18 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_18 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_18 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_18 : OUT STD_LOGIC;
LMB_Write_Strobe_18 : OUT STD_LOGIC;
LMB_CE_18 : IN STD_LOGIC;
LMB_UE_18 : IN STD_LOGIC;
LMB_Wait_18 : IN STD_LOGIC;
LMB_Data_Addr_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_19 : OUT STD_LOGIC;
LMB_Ready_19 : IN STD_LOGIC;
LMB_Byte_Enable_19 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_19 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_19 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_19 : OUT STD_LOGIC;
LMB_Write_Strobe_19 : OUT STD_LOGIC;
LMB_CE_19 : IN STD_LOGIC;
LMB_UE_19 : IN STD_LOGIC;
LMB_Wait_19 : IN STD_LOGIC;
LMB_Data_Addr_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_20 : OUT STD_LOGIC;
LMB_Ready_20 : IN STD_LOGIC;
LMB_Byte_Enable_20 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_20 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_20 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_20 : OUT STD_LOGIC;
LMB_Write_Strobe_20 : OUT STD_LOGIC;
LMB_CE_20 : IN STD_LOGIC;
LMB_UE_20 : IN STD_LOGIC;
LMB_Wait_20 : IN STD_LOGIC;
LMB_Data_Addr_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_21 : OUT STD_LOGIC;
LMB_Ready_21 : IN STD_LOGIC;
LMB_Byte_Enable_21 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_21 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_21 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_21 : OUT STD_LOGIC;
LMB_Write_Strobe_21 : OUT STD_LOGIC;
LMB_CE_21 : IN STD_LOGIC;
LMB_UE_21 : IN STD_LOGIC;
LMB_Wait_21 : IN STD_LOGIC;
LMB_Data_Addr_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_22 : OUT STD_LOGIC;
LMB_Ready_22 : IN STD_LOGIC;
LMB_Byte_Enable_22 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_22 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_22 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_22 : OUT STD_LOGIC;
LMB_Write_Strobe_22 : OUT STD_LOGIC;
LMB_CE_22 : IN STD_LOGIC;
LMB_UE_22 : IN STD_LOGIC;
LMB_Wait_22 : IN STD_LOGIC;
LMB_Data_Addr_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_23 : OUT STD_LOGIC;
LMB_Ready_23 : IN STD_LOGIC;
LMB_Byte_Enable_23 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_23 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_23 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_23 : OUT STD_LOGIC;
LMB_Write_Strobe_23 : OUT STD_LOGIC;
LMB_CE_23 : IN STD_LOGIC;
LMB_UE_23 : IN STD_LOGIC;
LMB_Wait_23 : IN STD_LOGIC;
LMB_Data_Addr_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_24 : OUT STD_LOGIC;
LMB_Ready_24 : IN STD_LOGIC;
LMB_Byte_Enable_24 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_24 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_24 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_24 : OUT STD_LOGIC;
LMB_Write_Strobe_24 : OUT STD_LOGIC;
LMB_CE_24 : IN STD_LOGIC;
LMB_UE_24 : IN STD_LOGIC;
LMB_Wait_24 : IN STD_LOGIC;
LMB_Data_Addr_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_25 : OUT STD_LOGIC;
LMB_Ready_25 : IN STD_LOGIC;
LMB_Byte_Enable_25 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_25 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_25 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_25 : OUT STD_LOGIC;
LMB_Write_Strobe_25 : OUT STD_LOGIC;
LMB_CE_25 : IN STD_LOGIC;
LMB_UE_25 : IN STD_LOGIC;
LMB_Wait_25 : IN STD_LOGIC;
LMB_Data_Addr_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_26 : OUT STD_LOGIC;
LMB_Ready_26 : IN STD_LOGIC;
LMB_Byte_Enable_26 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_26 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_26 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_26 : OUT STD_LOGIC;
LMB_Write_Strobe_26 : OUT STD_LOGIC;
LMB_CE_26 : IN STD_LOGIC;
LMB_UE_26 : IN STD_LOGIC;
LMB_Wait_26 : IN STD_LOGIC;
LMB_Data_Addr_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_27 : OUT STD_LOGIC;
LMB_Ready_27 : IN STD_LOGIC;
LMB_Byte_Enable_27 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_27 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_27 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_27 : OUT STD_LOGIC;
LMB_Write_Strobe_27 : OUT STD_LOGIC;
LMB_CE_27 : IN STD_LOGIC;
LMB_UE_27 : IN STD_LOGIC;
LMB_Wait_27 : IN STD_LOGIC;
LMB_Data_Addr_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_28 : OUT STD_LOGIC;
LMB_Ready_28 : IN STD_LOGIC;
LMB_Byte_Enable_28 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_28 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_28 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_28 : OUT STD_LOGIC;
LMB_Write_Strobe_28 : OUT STD_LOGIC;
LMB_CE_28 : IN STD_LOGIC;
LMB_UE_28 : IN STD_LOGIC;
LMB_Wait_28 : IN STD_LOGIC;
LMB_Data_Addr_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_29 : OUT STD_LOGIC;
LMB_Ready_29 : IN STD_LOGIC;
LMB_Byte_Enable_29 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_29 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_29 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_29 : OUT STD_LOGIC;
LMB_Write_Strobe_29 : OUT STD_LOGIC;
LMB_CE_29 : IN STD_LOGIC;
LMB_UE_29 : IN STD_LOGIC;
LMB_Wait_29 : IN STD_LOGIC;
LMB_Data_Addr_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_30 : OUT STD_LOGIC;
LMB_Ready_30 : IN STD_LOGIC;
LMB_Byte_Enable_30 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_30 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_30 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_30 : OUT STD_LOGIC;
LMB_Write_Strobe_30 : OUT STD_LOGIC;
LMB_CE_30 : IN STD_LOGIC;
LMB_UE_30 : IN STD_LOGIC;
LMB_Wait_30 : IN STD_LOGIC;
LMB_Data_Addr_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Addr_Strobe_31 : OUT STD_LOGIC;
LMB_Ready_31 : IN STD_LOGIC;
LMB_Byte_Enable_31 : OUT STD_LOGIC_VECTOR(0 TO 3);
LMB_Data_Read_31 : IN STD_LOGIC_VECTOR(0 TO 31);
LMB_Data_Write_31 : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Read_Strobe_31 : OUT STD_LOGIC;
LMB_Write_Strobe_31 : OUT STD_LOGIC;
LMB_CE_31 : IN STD_LOGIC;
LMB_UE_31 : IN STD_LOGIC;
LMB_Wait_31 : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TID : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
TRACE_CLK_OUT : OUT STD_LOGIC;
TRACE_CLK : IN STD_LOGIC;
TRACE_CTL : OUT STD_LOGIC;
TRACE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Dbg_Clk_0 : OUT STD_LOGIC;
Dbg_TDI_0 : OUT STD_LOGIC;
Dbg_TDO_0 : IN STD_LOGIC;
Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_0 : OUT STD_LOGIC;
Dbg_Shift_0 : OUT STD_LOGIC;
Dbg_Update_0 : OUT STD_LOGIC;
Dbg_Rst_0 : OUT STD_LOGIC;
Dbg_Trig_In_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_0 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_0 : OUT STD_LOGIC;
Dbg_TrData_0 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_0 : OUT STD_LOGIC;
Dbg_TrValid_0 : IN STD_LOGIC;
Dbg_Clk_1 : OUT STD_LOGIC;
Dbg_TDI_1 : OUT STD_LOGIC;
Dbg_TDO_1 : IN STD_LOGIC;
Dbg_Reg_En_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_1 : OUT STD_LOGIC;
Dbg_Shift_1 : OUT STD_LOGIC;
Dbg_Update_1 : OUT STD_LOGIC;
Dbg_Rst_1 : OUT STD_LOGIC;
Dbg_Trig_In_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_1 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_1 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_1 : OUT STD_LOGIC;
Dbg_TrData_1 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_1 : OUT STD_LOGIC;
Dbg_TrValid_1 : IN STD_LOGIC;
Dbg_Clk_2 : OUT STD_LOGIC;
Dbg_TDI_2 : OUT STD_LOGIC;
Dbg_TDO_2 : IN STD_LOGIC;
Dbg_Reg_En_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_2 : OUT STD_LOGIC;
Dbg_Shift_2 : OUT STD_LOGIC;
Dbg_Update_2 : OUT STD_LOGIC;
Dbg_Rst_2 : OUT STD_LOGIC;
Dbg_Trig_In_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_2 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_2 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_2 : OUT STD_LOGIC;
Dbg_TrData_2 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_2 : OUT STD_LOGIC;
Dbg_TrValid_2 : IN STD_LOGIC;
Dbg_Clk_3 : OUT STD_LOGIC;
Dbg_TDI_3 : OUT STD_LOGIC;
Dbg_TDO_3 : IN STD_LOGIC;
Dbg_Reg_En_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_3 : OUT STD_LOGIC;
Dbg_Shift_3 : OUT STD_LOGIC;
Dbg_Update_3 : OUT STD_LOGIC;
Dbg_Rst_3 : OUT STD_LOGIC;
Dbg_Trig_In_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_3 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_3 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_3 : OUT STD_LOGIC;
Dbg_TrData_3 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_3 : OUT STD_LOGIC;
Dbg_TrValid_3 : IN STD_LOGIC;
Dbg_Clk_4 : OUT STD_LOGIC;
Dbg_TDI_4 : OUT STD_LOGIC;
Dbg_TDO_4 : IN STD_LOGIC;
Dbg_Reg_En_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_4 : OUT STD_LOGIC;
Dbg_Shift_4 : OUT STD_LOGIC;
Dbg_Update_4 : OUT STD_LOGIC;
Dbg_Rst_4 : OUT STD_LOGIC;
Dbg_Trig_In_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_4 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_4 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_4 : OUT STD_LOGIC;
Dbg_TrData_4 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_4 : OUT STD_LOGIC;
Dbg_TrValid_4 : IN STD_LOGIC;
Dbg_Clk_5 : OUT STD_LOGIC;
Dbg_TDI_5 : OUT STD_LOGIC;
Dbg_TDO_5 : IN STD_LOGIC;
Dbg_Reg_En_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_5 : OUT STD_LOGIC;
Dbg_Shift_5 : OUT STD_LOGIC;
Dbg_Update_5 : OUT STD_LOGIC;
Dbg_Rst_5 : OUT STD_LOGIC;
Dbg_Trig_In_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_5 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_5 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_5 : OUT STD_LOGIC;
Dbg_TrData_5 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_5 : OUT STD_LOGIC;
Dbg_TrValid_5 : IN STD_LOGIC;
Dbg_Clk_6 : OUT STD_LOGIC;
Dbg_TDI_6 : OUT STD_LOGIC;
Dbg_TDO_6 : IN STD_LOGIC;
Dbg_Reg_En_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_6 : OUT STD_LOGIC;
Dbg_Shift_6 : OUT STD_LOGIC;
Dbg_Update_6 : OUT STD_LOGIC;
Dbg_Rst_6 : OUT STD_LOGIC;
Dbg_Trig_In_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_6 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_6 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_6 : OUT STD_LOGIC;
Dbg_TrData_6 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_6 : OUT STD_LOGIC;
Dbg_TrValid_6 : IN STD_LOGIC;
Dbg_Clk_7 : OUT STD_LOGIC;
Dbg_TDI_7 : OUT STD_LOGIC;
Dbg_TDO_7 : IN STD_LOGIC;
Dbg_Reg_En_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_7 : OUT STD_LOGIC;
Dbg_Shift_7 : OUT STD_LOGIC;
Dbg_Update_7 : OUT STD_LOGIC;
Dbg_Rst_7 : OUT STD_LOGIC;
Dbg_Trig_In_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_7 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_7 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_7 : OUT STD_LOGIC;
Dbg_TrData_7 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_7 : OUT STD_LOGIC;
Dbg_TrValid_7 : IN STD_LOGIC;
Dbg_Clk_8 : OUT STD_LOGIC;
Dbg_TDI_8 : OUT STD_LOGIC;
Dbg_TDO_8 : IN STD_LOGIC;
Dbg_Reg_En_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_8 : OUT STD_LOGIC;
Dbg_Shift_8 : OUT STD_LOGIC;
Dbg_Update_8 : OUT STD_LOGIC;
Dbg_Rst_8 : OUT STD_LOGIC;
Dbg_Trig_In_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_8 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_8 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_8 : OUT STD_LOGIC;
Dbg_TrData_8 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_8 : OUT STD_LOGIC;
Dbg_TrValid_8 : IN STD_LOGIC;
Dbg_Clk_9 : OUT STD_LOGIC;
Dbg_TDI_9 : OUT STD_LOGIC;
Dbg_TDO_9 : IN STD_LOGIC;
Dbg_Reg_En_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_9 : OUT STD_LOGIC;
Dbg_Shift_9 : OUT STD_LOGIC;
Dbg_Update_9 : OUT STD_LOGIC;
Dbg_Rst_9 : OUT STD_LOGIC;
Dbg_Trig_In_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_9 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_9 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_9 : OUT STD_LOGIC;
Dbg_TrData_9 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_9 : OUT STD_LOGIC;
Dbg_TrValid_9 : IN STD_LOGIC;
Dbg_Clk_10 : OUT STD_LOGIC;
Dbg_TDI_10 : OUT STD_LOGIC;
Dbg_TDO_10 : IN STD_LOGIC;
Dbg_Reg_En_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_10 : OUT STD_LOGIC;
Dbg_Shift_10 : OUT STD_LOGIC;
Dbg_Update_10 : OUT STD_LOGIC;
Dbg_Rst_10 : OUT STD_LOGIC;
Dbg_Trig_In_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_10 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_10 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_10 : OUT STD_LOGIC;
Dbg_TrData_10 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_10 : OUT STD_LOGIC;
Dbg_TrValid_10 : IN STD_LOGIC;
Dbg_Clk_11 : OUT STD_LOGIC;
Dbg_TDI_11 : OUT STD_LOGIC;
Dbg_TDO_11 : IN STD_LOGIC;
Dbg_Reg_En_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_11 : OUT STD_LOGIC;
Dbg_Shift_11 : OUT STD_LOGIC;
Dbg_Update_11 : OUT STD_LOGIC;
Dbg_Rst_11 : OUT STD_LOGIC;
Dbg_Trig_In_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_11 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_11 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_11 : OUT STD_LOGIC;
Dbg_TrData_11 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_11 : OUT STD_LOGIC;
Dbg_TrValid_11 : IN STD_LOGIC;
Dbg_Clk_12 : OUT STD_LOGIC;
Dbg_TDI_12 : OUT STD_LOGIC;
Dbg_TDO_12 : IN STD_LOGIC;
Dbg_Reg_En_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_12 : OUT STD_LOGIC;
Dbg_Shift_12 : OUT STD_LOGIC;
Dbg_Update_12 : OUT STD_LOGIC;
Dbg_Rst_12 : OUT STD_LOGIC;
Dbg_Trig_In_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_12 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_12 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_12 : OUT STD_LOGIC;
Dbg_TrData_12 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_12 : OUT STD_LOGIC;
Dbg_TrValid_12 : IN STD_LOGIC;
Dbg_Clk_13 : OUT STD_LOGIC;
Dbg_TDI_13 : OUT STD_LOGIC;
Dbg_TDO_13 : IN STD_LOGIC;
Dbg_Reg_En_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_13 : OUT STD_LOGIC;
Dbg_Shift_13 : OUT STD_LOGIC;
Dbg_Update_13 : OUT STD_LOGIC;
Dbg_Rst_13 : OUT STD_LOGIC;
Dbg_Trig_In_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_13 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_13 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_13 : OUT STD_LOGIC;
Dbg_TrData_13 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_13 : OUT STD_LOGIC;
Dbg_TrValid_13 : IN STD_LOGIC;
Dbg_Clk_14 : OUT STD_LOGIC;
Dbg_TDI_14 : OUT STD_LOGIC;
Dbg_TDO_14 : IN STD_LOGIC;
Dbg_Reg_En_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_14 : OUT STD_LOGIC;
Dbg_Shift_14 : OUT STD_LOGIC;
Dbg_Update_14 : OUT STD_LOGIC;
Dbg_Rst_14 : OUT STD_LOGIC;
Dbg_Trig_In_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_14 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_14 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_14 : OUT STD_LOGIC;
Dbg_TrData_14 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_14 : OUT STD_LOGIC;
Dbg_TrValid_14 : IN STD_LOGIC;
Dbg_Clk_15 : OUT STD_LOGIC;
Dbg_TDI_15 : OUT STD_LOGIC;
Dbg_TDO_15 : IN STD_LOGIC;
Dbg_Reg_En_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_15 : OUT STD_LOGIC;
Dbg_Shift_15 : OUT STD_LOGIC;
Dbg_Update_15 : OUT STD_LOGIC;
Dbg_Rst_15 : OUT STD_LOGIC;
Dbg_Trig_In_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_15 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_15 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_15 : OUT STD_LOGIC;
Dbg_TrData_15 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_15 : OUT STD_LOGIC;
Dbg_TrValid_15 : IN STD_LOGIC;
Dbg_Clk_16 : OUT STD_LOGIC;
Dbg_TDI_16 : OUT STD_LOGIC;
Dbg_TDO_16 : IN STD_LOGIC;
Dbg_Reg_En_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_16 : OUT STD_LOGIC;
Dbg_Shift_16 : OUT STD_LOGIC;
Dbg_Update_16 : OUT STD_LOGIC;
Dbg_Rst_16 : OUT STD_LOGIC;
Dbg_Trig_In_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_16 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_16 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_16 : OUT STD_LOGIC;
Dbg_TrData_16 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_16 : OUT STD_LOGIC;
Dbg_TrValid_16 : IN STD_LOGIC;
Dbg_Clk_17 : OUT STD_LOGIC;
Dbg_TDI_17 : OUT STD_LOGIC;
Dbg_TDO_17 : IN STD_LOGIC;
Dbg_Reg_En_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_17 : OUT STD_LOGIC;
Dbg_Shift_17 : OUT STD_LOGIC;
Dbg_Update_17 : OUT STD_LOGIC;
Dbg_Rst_17 : OUT STD_LOGIC;
Dbg_Trig_In_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_17 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_17 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_17 : OUT STD_LOGIC;
Dbg_TrData_17 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_17 : OUT STD_LOGIC;
Dbg_TrValid_17 : IN STD_LOGIC;
Dbg_Clk_18 : OUT STD_LOGIC;
Dbg_TDI_18 : OUT STD_LOGIC;
Dbg_TDO_18 : IN STD_LOGIC;
Dbg_Reg_En_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_18 : OUT STD_LOGIC;
Dbg_Shift_18 : OUT STD_LOGIC;
Dbg_Update_18 : OUT STD_LOGIC;
Dbg_Rst_18 : OUT STD_LOGIC;
Dbg_Trig_In_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_18 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_18 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_18 : OUT STD_LOGIC;
Dbg_TrData_18 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_18 : OUT STD_LOGIC;
Dbg_TrValid_18 : IN STD_LOGIC;
Dbg_Clk_19 : OUT STD_LOGIC;
Dbg_TDI_19 : OUT STD_LOGIC;
Dbg_TDO_19 : IN STD_LOGIC;
Dbg_Reg_En_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_19 : OUT STD_LOGIC;
Dbg_Shift_19 : OUT STD_LOGIC;
Dbg_Update_19 : OUT STD_LOGIC;
Dbg_Rst_19 : OUT STD_LOGIC;
Dbg_Trig_In_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_19 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_19 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_19 : OUT STD_LOGIC;
Dbg_TrData_19 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_19 : OUT STD_LOGIC;
Dbg_TrValid_19 : IN STD_LOGIC;
Dbg_Clk_20 : OUT STD_LOGIC;
Dbg_TDI_20 : OUT STD_LOGIC;
Dbg_TDO_20 : IN STD_LOGIC;
Dbg_Reg_En_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_20 : OUT STD_LOGIC;
Dbg_Shift_20 : OUT STD_LOGIC;
Dbg_Update_20 : OUT STD_LOGIC;
Dbg_Rst_20 : OUT STD_LOGIC;
Dbg_Trig_In_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_20 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_20 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_20 : OUT STD_LOGIC;
Dbg_TrData_20 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_20 : OUT STD_LOGIC;
Dbg_TrValid_20 : IN STD_LOGIC;
Dbg_Clk_21 : OUT STD_LOGIC;
Dbg_TDI_21 : OUT STD_LOGIC;
Dbg_TDO_21 : IN STD_LOGIC;
Dbg_Reg_En_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_21 : OUT STD_LOGIC;
Dbg_Shift_21 : OUT STD_LOGIC;
Dbg_Update_21 : OUT STD_LOGIC;
Dbg_Rst_21 : OUT STD_LOGIC;
Dbg_Trig_In_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_21 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_21 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_21 : OUT STD_LOGIC;
Dbg_TrData_21 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_21 : OUT STD_LOGIC;
Dbg_TrValid_21 : IN STD_LOGIC;
Dbg_Clk_22 : OUT STD_LOGIC;
Dbg_TDI_22 : OUT STD_LOGIC;
Dbg_TDO_22 : IN STD_LOGIC;
Dbg_Reg_En_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_22 : OUT STD_LOGIC;
Dbg_Shift_22 : OUT STD_LOGIC;
Dbg_Update_22 : OUT STD_LOGIC;
Dbg_Rst_22 : OUT STD_LOGIC;
Dbg_Trig_In_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_22 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_22 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_22 : OUT STD_LOGIC;
Dbg_TrData_22 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_22 : OUT STD_LOGIC;
Dbg_TrValid_22 : IN STD_LOGIC;
Dbg_Clk_23 : OUT STD_LOGIC;
Dbg_TDI_23 : OUT STD_LOGIC;
Dbg_TDO_23 : IN STD_LOGIC;
Dbg_Reg_En_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_23 : OUT STD_LOGIC;
Dbg_Shift_23 : OUT STD_LOGIC;
Dbg_Update_23 : OUT STD_LOGIC;
Dbg_Rst_23 : OUT STD_LOGIC;
Dbg_Trig_In_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_23 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_23 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_23 : OUT STD_LOGIC;
Dbg_TrData_23 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_23 : OUT STD_LOGIC;
Dbg_TrValid_23 : IN STD_LOGIC;
Dbg_Clk_24 : OUT STD_LOGIC;
Dbg_TDI_24 : OUT STD_LOGIC;
Dbg_TDO_24 : IN STD_LOGIC;
Dbg_Reg_En_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_24 : OUT STD_LOGIC;
Dbg_Shift_24 : OUT STD_LOGIC;
Dbg_Update_24 : OUT STD_LOGIC;
Dbg_Rst_24 : OUT STD_LOGIC;
Dbg_Trig_In_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_24 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_24 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_24 : OUT STD_LOGIC;
Dbg_TrData_24 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_24 : OUT STD_LOGIC;
Dbg_TrValid_24 : IN STD_LOGIC;
Dbg_Clk_25 : OUT STD_LOGIC;
Dbg_TDI_25 : OUT STD_LOGIC;
Dbg_TDO_25 : IN STD_LOGIC;
Dbg_Reg_En_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_25 : OUT STD_LOGIC;
Dbg_Shift_25 : OUT STD_LOGIC;
Dbg_Update_25 : OUT STD_LOGIC;
Dbg_Rst_25 : OUT STD_LOGIC;
Dbg_Trig_In_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_25 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_25 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_25 : OUT STD_LOGIC;
Dbg_TrData_25 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_25 : OUT STD_LOGIC;
Dbg_TrValid_25 : IN STD_LOGIC;
Dbg_Clk_26 : OUT STD_LOGIC;
Dbg_TDI_26 : OUT STD_LOGIC;
Dbg_TDO_26 : IN STD_LOGIC;
Dbg_Reg_En_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_26 : OUT STD_LOGIC;
Dbg_Shift_26 : OUT STD_LOGIC;
Dbg_Update_26 : OUT STD_LOGIC;
Dbg_Rst_26 : OUT STD_LOGIC;
Dbg_Trig_In_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_26 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_26 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_26 : OUT STD_LOGIC;
Dbg_TrData_26 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_26 : OUT STD_LOGIC;
Dbg_TrValid_26 : IN STD_LOGIC;
Dbg_Clk_27 : OUT STD_LOGIC;
Dbg_TDI_27 : OUT STD_LOGIC;
Dbg_TDO_27 : IN STD_LOGIC;
Dbg_Reg_En_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_27 : OUT STD_LOGIC;
Dbg_Shift_27 : OUT STD_LOGIC;
Dbg_Update_27 : OUT STD_LOGIC;
Dbg_Rst_27 : OUT STD_LOGIC;
Dbg_Trig_In_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_27 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_27 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_27 : OUT STD_LOGIC;
Dbg_TrData_27 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_27 : OUT STD_LOGIC;
Dbg_TrValid_27 : IN STD_LOGIC;
Dbg_Clk_28 : OUT STD_LOGIC;
Dbg_TDI_28 : OUT STD_LOGIC;
Dbg_TDO_28 : IN STD_LOGIC;
Dbg_Reg_En_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_28 : OUT STD_LOGIC;
Dbg_Shift_28 : OUT STD_LOGIC;
Dbg_Update_28 : OUT STD_LOGIC;
Dbg_Rst_28 : OUT STD_LOGIC;
Dbg_Trig_In_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_28 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_28 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_28 : OUT STD_LOGIC;
Dbg_TrData_28 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_28 : OUT STD_LOGIC;
Dbg_TrValid_28 : IN STD_LOGIC;
Dbg_Clk_29 : OUT STD_LOGIC;
Dbg_TDI_29 : OUT STD_LOGIC;
Dbg_TDO_29 : IN STD_LOGIC;
Dbg_Reg_En_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_29 : OUT STD_LOGIC;
Dbg_Shift_29 : OUT STD_LOGIC;
Dbg_Update_29 : OUT STD_LOGIC;
Dbg_Rst_29 : OUT STD_LOGIC;
Dbg_Trig_In_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_29 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_29 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_29 : OUT STD_LOGIC;
Dbg_TrData_29 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_29 : OUT STD_LOGIC;
Dbg_TrValid_29 : IN STD_LOGIC;
Dbg_Clk_30 : OUT STD_LOGIC;
Dbg_TDI_30 : OUT STD_LOGIC;
Dbg_TDO_30 : IN STD_LOGIC;
Dbg_Reg_En_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_30 : OUT STD_LOGIC;
Dbg_Shift_30 : OUT STD_LOGIC;
Dbg_Update_30 : OUT STD_LOGIC;
Dbg_Rst_30 : OUT STD_LOGIC;
Dbg_Trig_In_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_30 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_30 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_30 : OUT STD_LOGIC;
Dbg_TrData_30 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_30 : OUT STD_LOGIC;
Dbg_TrValid_30 : IN STD_LOGIC;
Dbg_Clk_31 : OUT STD_LOGIC;
Dbg_TDI_31 : OUT STD_LOGIC;
Dbg_TDO_31 : IN STD_LOGIC;
Dbg_Reg_En_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Capture_31 : OUT STD_LOGIC;
Dbg_Shift_31 : OUT STD_LOGIC;
Dbg_Update_31 : OUT STD_LOGIC;
Dbg_Rst_31 : OUT STD_LOGIC;
Dbg_Trig_In_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out_31 : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out_31 : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_TrClk_31 : OUT STD_LOGIC;
Dbg_TrData_31 : IN STD_LOGIC_VECTOR(0 TO 35);
Dbg_TrReady_31 : OUT STD_LOGIC;
Dbg_TrValid_31 : IN STD_LOGIC;
bscan_ext_tdi : IN STD_LOGIC;
bscan_ext_reset : IN STD_LOGIC;
bscan_ext_shift : IN STD_LOGIC;
bscan_ext_update : IN STD_LOGIC;
bscan_ext_capture : IN STD_LOGIC;
bscan_ext_sel : IN STD_LOGIC;
bscan_ext_drck : IN STD_LOGIC;
bscan_ext_tdo : OUT STD_LOGIC;
Ext_JTAG_DRCK : OUT STD_LOGIC;
Ext_JTAG_RESET : OUT STD_LOGIC;
Ext_JTAG_SEL : OUT STD_LOGIC;
Ext_JTAG_CAPTURE : OUT STD_LOGIC;
Ext_JTAG_SHIFT : OUT STD_LOGIC;
Ext_JTAG_UPDATE : OUT STD_LOGIC;
Ext_JTAG_TDI : OUT STD_LOGIC;
Ext_JTAG_TDO : IN STD_LOGIC
);
END COMPONENT MDM;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "MDM,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_mdm_1_0_arch : ARCHITECTURE IS "design_1_mdm_1_0,MDM,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_mdm_1_0_arch: ARCHITECTURE IS "design_1_mdm_1_0,MDM,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mdm,x_ipVersion=3.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_JTAG_CHAIN=2,C_USE_BSCAN=0,C_USE_CONFIG_RESET=0,C_INTERCONNECT=2,C_MB_DBG_PORTS=1,C_USE_UART=0,C_DBG_REG_ACCESS=0,C_DBG_MEM_ACCESS=0,C_USE_CROSS_TRIGGER=0,C_TRACE_OUTPUT=0,C_TRACE_DATA_WIDTH=32,C_TRACE_CLK_FREQ_HZ=200000000,C_TRACE_CLK_OUT_PHASE=90,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ACLK_FREQ_HZ=100000000,C_M_AXI_ADDR_WIDTH=32,C_M_AXI_DATA_WIDTH=32,C_M_AXI_THREAD_ID_WIDTH=1,C_DATA_SIZE=32,C_M_AXIS_DATA_WIDTH=32,C_M_AXIS_ID_WIDTH=7}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Debug_SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Rst_0: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST";
BEGIN
U0 : MDM
GENERIC MAP (
C_FAMILY => "artix7",
C_JTAG_CHAIN => 2,
C_USE_BSCAN => 0,
C_USE_CONFIG_RESET => 0,
C_INTERCONNECT => 2,
C_MB_DBG_PORTS => 1,
C_USE_UART => 0,
C_DBG_REG_ACCESS => 0,
C_DBG_MEM_ACCESS => 0,
C_USE_CROSS_TRIGGER => 0,
C_TRACE_OUTPUT => 0,
C_TRACE_DATA_WIDTH => 32,
C_TRACE_CLK_FREQ_HZ => 200000000,
C_TRACE_CLK_OUT_PHASE => 90,
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_THREAD_ID_WIDTH => 1,
C_DATA_SIZE => 32,
C_M_AXIS_DATA_WIDTH => 32,
C_M_AXIS_ID_WIDTH => 7
)
PORT MAP (
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
S_AXI_ACLK => '0',
S_AXI_ARESETN => '0',
M_AXI_ACLK => '0',
M_AXI_ARESETN => '0',
M_AXIS_ACLK => '0',
M_AXIS_ARESETN => '0',
Debug_SYS_Rst => Debug_SYS_Rst,
Trig_In_0 => '0',
Trig_Ack_Out_0 => '0',
Trig_In_1 => '0',
Trig_Ack_Out_1 => '0',
Trig_In_2 => '0',
Trig_Ack_Out_2 => '0',
Trig_In_3 => '0',
Trig_Ack_Out_3 => '0',
S_AXI_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_AWVALID => '0',
S_AXI_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
S_AXI_WVALID => '0',
S_AXI_BREADY => '0',
S_AXI_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXI_ARVALID => '0',
S_AXI_RREADY => '0',
M_AXI_AWREADY => '0',
M_AXI_WREADY => '0',
M_AXI_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_BVALID => '0',
M_AXI_ARREADY => '0',
M_AXI_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_RLAST => '0',
M_AXI_RVALID => '0',
LMB_Ready_0 => '0',
LMB_Data_Read_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_0 => '0',
LMB_UE_0 => '0',
LMB_Wait_0 => '0',
LMB_Ready_1 => '0',
LMB_Data_Read_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_1 => '0',
LMB_UE_1 => '0',
LMB_Wait_1 => '0',
LMB_Ready_2 => '0',
LMB_Data_Read_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_2 => '0',
LMB_UE_2 => '0',
LMB_Wait_2 => '0',
LMB_Ready_3 => '0',
LMB_Data_Read_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_3 => '0',
LMB_UE_3 => '0',
LMB_Wait_3 => '0',
LMB_Ready_4 => '0',
LMB_Data_Read_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_4 => '0',
LMB_UE_4 => '0',
LMB_Wait_4 => '0',
LMB_Ready_5 => '0',
LMB_Data_Read_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_5 => '0',
LMB_UE_5 => '0',
LMB_Wait_5 => '0',
LMB_Ready_6 => '0',
LMB_Data_Read_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_6 => '0',
LMB_UE_6 => '0',
LMB_Wait_6 => '0',
LMB_Ready_7 => '0',
LMB_Data_Read_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_7 => '0',
LMB_UE_7 => '0',
LMB_Wait_7 => '0',
LMB_Ready_8 => '0',
LMB_Data_Read_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_8 => '0',
LMB_UE_8 => '0',
LMB_Wait_8 => '0',
LMB_Ready_9 => '0',
LMB_Data_Read_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_9 => '0',
LMB_UE_9 => '0',
LMB_Wait_9 => '0',
LMB_Ready_10 => '0',
LMB_Data_Read_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_10 => '0',
LMB_UE_10 => '0',
LMB_Wait_10 => '0',
LMB_Ready_11 => '0',
LMB_Data_Read_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_11 => '0',
LMB_UE_11 => '0',
LMB_Wait_11 => '0',
LMB_Ready_12 => '0',
LMB_Data_Read_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_12 => '0',
LMB_UE_12 => '0',
LMB_Wait_12 => '0',
LMB_Ready_13 => '0',
LMB_Data_Read_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_13 => '0',
LMB_UE_13 => '0',
LMB_Wait_13 => '0',
LMB_Ready_14 => '0',
LMB_Data_Read_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_14 => '0',
LMB_UE_14 => '0',
LMB_Wait_14 => '0',
LMB_Ready_15 => '0',
LMB_Data_Read_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_15 => '0',
LMB_UE_15 => '0',
LMB_Wait_15 => '0',
LMB_Ready_16 => '0',
LMB_Data_Read_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_16 => '0',
LMB_UE_16 => '0',
LMB_Wait_16 => '0',
LMB_Ready_17 => '0',
LMB_Data_Read_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_17 => '0',
LMB_UE_17 => '0',
LMB_Wait_17 => '0',
LMB_Ready_18 => '0',
LMB_Data_Read_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_18 => '0',
LMB_UE_18 => '0',
LMB_Wait_18 => '0',
LMB_Ready_19 => '0',
LMB_Data_Read_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_19 => '0',
LMB_UE_19 => '0',
LMB_Wait_19 => '0',
LMB_Ready_20 => '0',
LMB_Data_Read_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_20 => '0',
LMB_UE_20 => '0',
LMB_Wait_20 => '0',
LMB_Ready_21 => '0',
LMB_Data_Read_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_21 => '0',
LMB_UE_21 => '0',
LMB_Wait_21 => '0',
LMB_Ready_22 => '0',
LMB_Data_Read_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_22 => '0',
LMB_UE_22 => '0',
LMB_Wait_22 => '0',
LMB_Ready_23 => '0',
LMB_Data_Read_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_23 => '0',
LMB_UE_23 => '0',
LMB_Wait_23 => '0',
LMB_Ready_24 => '0',
LMB_Data_Read_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_24 => '0',
LMB_UE_24 => '0',
LMB_Wait_24 => '0',
LMB_Ready_25 => '0',
LMB_Data_Read_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_25 => '0',
LMB_UE_25 => '0',
LMB_Wait_25 => '0',
LMB_Ready_26 => '0',
LMB_Data_Read_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_26 => '0',
LMB_UE_26 => '0',
LMB_Wait_26 => '0',
LMB_Ready_27 => '0',
LMB_Data_Read_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_27 => '0',
LMB_UE_27 => '0',
LMB_Wait_27 => '0',
LMB_Ready_28 => '0',
LMB_Data_Read_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_28 => '0',
LMB_UE_28 => '0',
LMB_Wait_28 => '0',
LMB_Ready_29 => '0',
LMB_Data_Read_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_29 => '0',
LMB_UE_29 => '0',
LMB_Wait_29 => '0',
LMB_Ready_30 => '0',
LMB_Data_Read_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_30 => '0',
LMB_UE_30 => '0',
LMB_Wait_30 => '0',
LMB_Ready_31 => '0',
LMB_Data_Read_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
LMB_CE_31 => '0',
LMB_UE_31 => '0',
LMB_Wait_31 => '0',
M_AXIS_TREADY => '1',
TRACE_CLK => '0',
Dbg_Clk_0 => Dbg_Clk_0,
Dbg_TDI_0 => Dbg_TDI_0,
Dbg_TDO_0 => Dbg_TDO_0,
Dbg_Reg_En_0 => Dbg_Reg_En_0,
Dbg_Capture_0 => Dbg_Capture_0,
Dbg_Shift_0 => Dbg_Shift_0,
Dbg_Update_0 => Dbg_Update_0,
Dbg_Rst_0 => Dbg_Rst_0,
Dbg_Trig_In_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_0 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_0 => '0',
Dbg_TDO_1 => '0',
Dbg_Trig_In_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_1 => '0',
Dbg_TDO_2 => '0',
Dbg_Trig_In_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_2 => '0',
Dbg_TDO_3 => '0',
Dbg_Trig_In_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_3 => '0',
Dbg_TDO_4 => '0',
Dbg_Trig_In_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_4 => '0',
Dbg_TDO_5 => '0',
Dbg_Trig_In_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_5 => '0',
Dbg_TDO_6 => '0',
Dbg_Trig_In_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_6 => '0',
Dbg_TDO_7 => '0',
Dbg_Trig_In_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_7 => '0',
Dbg_TDO_8 => '0',
Dbg_Trig_In_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_8 => '0',
Dbg_TDO_9 => '0',
Dbg_Trig_In_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_9 => '0',
Dbg_TDO_10 => '0',
Dbg_Trig_In_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_10 => '0',
Dbg_TDO_11 => '0',
Dbg_Trig_In_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_11 => '0',
Dbg_TDO_12 => '0',
Dbg_Trig_In_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_12 => '0',
Dbg_TDO_13 => '0',
Dbg_Trig_In_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_13 => '0',
Dbg_TDO_14 => '0',
Dbg_Trig_In_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_14 => '0',
Dbg_TDO_15 => '0',
Dbg_Trig_In_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_15 => '0',
Dbg_TDO_16 => '0',
Dbg_Trig_In_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_16 => '0',
Dbg_TDO_17 => '0',
Dbg_Trig_In_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_17 => '0',
Dbg_TDO_18 => '0',
Dbg_Trig_In_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_18 => '0',
Dbg_TDO_19 => '0',
Dbg_Trig_In_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_19 => '0',
Dbg_TDO_20 => '0',
Dbg_Trig_In_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_20 => '0',
Dbg_TDO_21 => '0',
Dbg_Trig_In_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_21 => '0',
Dbg_TDO_22 => '0',
Dbg_Trig_In_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_22 => '0',
Dbg_TDO_23 => '0',
Dbg_Trig_In_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_23 => '0',
Dbg_TDO_24 => '0',
Dbg_Trig_In_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_24 => '0',
Dbg_TDO_25 => '0',
Dbg_Trig_In_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_25 => '0',
Dbg_TDO_26 => '0',
Dbg_Trig_In_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_26 => '0',
Dbg_TDO_27 => '0',
Dbg_Trig_In_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_27 => '0',
Dbg_TDO_28 => '0',
Dbg_Trig_In_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_28 => '0',
Dbg_TDO_29 => '0',
Dbg_Trig_In_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_29 => '0',
Dbg_TDO_30 => '0',
Dbg_Trig_In_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_30 => '0',
Dbg_TDO_31 => '0',
Dbg_Trig_In_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Ack_Out_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_TrData_31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 36)),
Dbg_TrValid_31 => '0',
bscan_ext_tdi => '0',
bscan_ext_reset => '0',
bscan_ext_shift => '0',
bscan_ext_update => '0',
bscan_ext_capture => '0',
bscan_ext_sel => '0',
bscan_ext_drck => '0',
Ext_JTAG_TDO => '0'
);
END design_1_mdm_1_0_arch;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/upcnt_n.vhd
|
44
|
7144
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/066de7cd/hdl/src/vhdl/upcnt_n.vhd
|
44
|
7144
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_v10_v3_0/d6c0f905/hdl/vhdl/lmb_v10.vhd
|
4
|
9111
|
-------------------------------------------------------------------------------
-- lmb_v10.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: lmb_v10.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_v10.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- goran 2002-01-30 First Version
-- paulo 2002-04-10 Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
-- roland 2010-02-13 UE, CE and Wait signals added
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer := 4;
C_LMB_DWIDTH : integer := 32;
C_LMB_AWIDTH : integer := 32;
C_EXT_RESET_HIGH : integer := 1
);
port (
-- Global Ports
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
-- LMB master signals
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
-- LMB slave signals
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
-- LMB output signals
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end entity lmb_v10;
library unisim;
use unisim.all;
architecture IMP of lmb_v10 is
component FDS is
port(
Q : out std_logic;
D : in std_logic;
C : in std_logic;
S : in std_logic);
end component FDS;
signal sys_rst_i : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Driving the reset signal
-----------------------------------------------------------------------------
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input;
end process SYS_RST_PROC;
POR_FF_I : FDS
port map (
Q => LMB_Rst,
D => '0',
C => LMB_Clk,
S => sys_rst_i);
-----------------------------------------------------------------------------
-- Drive all Master to Slave signals
-----------------------------------------------------------------------------
LMB_ABus <= M_ABus;
LMB_ReadStrobe <= M_ReadStrobe;
LMB_WriteStrobe <= M_WriteStrobe;
LMB_AddrStrobe <= M_AddrStrobe;
LMB_BE <= M_BE;
LMB_WriteDBus <= M_DBus;
-----------------------------------------------------------------------------
-- Drive all the Slave to Master signals
-----------------------------------------------------------------------------
Ready_ORing : process (Sl_Ready) is
variable i : std_logic;
begin -- process Ready_ORing
i := '0';
for S in Sl_Ready'range loop
i := i or Sl_Ready(S);
end loop; -- S
LMB_Ready <= i;
end process Ready_ORing;
Wait_ORing : process (Sl_Wait) is
variable i : std_logic;
begin -- process Wait_ORing
i := '0';
for S in Sl_Wait'range loop
i := i or Sl_Wait(S);
end loop; -- S
LMB_Wait <= i;
end process Wait_ORing;
SI_UE_ORing : process (Sl_UE) is
variable i : std_logic;
begin -- process UE_ORing
i := '0';
for S in Sl_UE'range loop
i := i or Sl_UE(S);
end loop; -- S
LMB_UE <= i;
end process SI_UE_ORing;
SI_CE_ORing : process (Sl_CE) is
variable i : std_logic;
begin -- process CE_ORing
i := '0';
for S in Sl_CE'range loop
i := i or Sl_CE(S);
end loop; -- S
LMB_CE <= i;
end process SI_CE_ORing;
DBus_Oring : process (Sl_Ready, Sl_DBus) is
variable Res : std_logic_vector(0 to C_LMB_DWIDTH-1);
variable Tmp : std_logic_vector(Sl_DBus'range);
variable tmp_or : std_logic;
begin -- process DBus_Oring
if (C_LMB_NUM_SLAVES = 1) then
LMB_ReadDBus <= Sl_DBus;
else
-- First gating all data signals with their resp. ready signal
for I in 0 to C_LMB_NUM_SLAVES-1 loop
for J in 0 to C_LMB_DWIDTH-1 loop
tmp(I*C_LMB_DWIDTH + J) := Sl_Ready(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
end loop; -- J
end loop; -- I
-- then oring the tmp signals together
for J in 0 to C_LMB_DWIDTH-1 loop
tmp_or := '0';
for I in 0 to C_LMB_NUM_SLAVES-1 loop
tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
end loop; -- J
res(J) := tmp_or;
end loop; -- I
LMB_ReadDBus <= Res;
end if;
end process DBus_Oring;
end architecture IMP;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lmb_v10_v3_0/d6c0f905/hdl/vhdl/lmb_v10.vhd
|
4
|
9111
|
-------------------------------------------------------------------------------
-- lmb_v10.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: lmb_v10.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_v10.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- goran 2002-01-30 First Version
-- paulo 2002-04-10 Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
-- roland 2010-02-13 UE, CE and Wait signals added
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer := 4;
C_LMB_DWIDTH : integer := 32;
C_LMB_AWIDTH : integer := 32;
C_EXT_RESET_HIGH : integer := 1
);
port (
-- Global Ports
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
-- LMB master signals
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
-- LMB slave signals
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
-- LMB output signals
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end entity lmb_v10;
library unisim;
use unisim.all;
architecture IMP of lmb_v10 is
component FDS is
port(
Q : out std_logic;
D : in std_logic;
C : in std_logic;
S : in std_logic);
end component FDS;
signal sys_rst_i : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Driving the reset signal
-----------------------------------------------------------------------------
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input;
end process SYS_RST_PROC;
POR_FF_I : FDS
port map (
Q => LMB_Rst,
D => '0',
C => LMB_Clk,
S => sys_rst_i);
-----------------------------------------------------------------------------
-- Drive all Master to Slave signals
-----------------------------------------------------------------------------
LMB_ABus <= M_ABus;
LMB_ReadStrobe <= M_ReadStrobe;
LMB_WriteStrobe <= M_WriteStrobe;
LMB_AddrStrobe <= M_AddrStrobe;
LMB_BE <= M_BE;
LMB_WriteDBus <= M_DBus;
-----------------------------------------------------------------------------
-- Drive all the Slave to Master signals
-----------------------------------------------------------------------------
Ready_ORing : process (Sl_Ready) is
variable i : std_logic;
begin -- process Ready_ORing
i := '0';
for S in Sl_Ready'range loop
i := i or Sl_Ready(S);
end loop; -- S
LMB_Ready <= i;
end process Ready_ORing;
Wait_ORing : process (Sl_Wait) is
variable i : std_logic;
begin -- process Wait_ORing
i := '0';
for S in Sl_Wait'range loop
i := i or Sl_Wait(S);
end loop; -- S
LMB_Wait <= i;
end process Wait_ORing;
SI_UE_ORing : process (Sl_UE) is
variable i : std_logic;
begin -- process UE_ORing
i := '0';
for S in Sl_UE'range loop
i := i or Sl_UE(S);
end loop; -- S
LMB_UE <= i;
end process SI_UE_ORing;
SI_CE_ORing : process (Sl_CE) is
variable i : std_logic;
begin -- process CE_ORing
i := '0';
for S in Sl_CE'range loop
i := i or Sl_CE(S);
end loop; -- S
LMB_CE <= i;
end process SI_CE_ORing;
DBus_Oring : process (Sl_Ready, Sl_DBus) is
variable Res : std_logic_vector(0 to C_LMB_DWIDTH-1);
variable Tmp : std_logic_vector(Sl_DBus'range);
variable tmp_or : std_logic;
begin -- process DBus_Oring
if (C_LMB_NUM_SLAVES = 1) then
LMB_ReadDBus <= Sl_DBus;
else
-- First gating all data signals with their resp. ready signal
for I in 0 to C_LMB_NUM_SLAVES-1 loop
for J in 0 to C_LMB_DWIDTH-1 loop
tmp(I*C_LMB_DWIDTH + J) := Sl_Ready(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
end loop; -- J
end loop; -- I
-- then oring the tmp signals together
for J in 0 to C_LMB_DWIDTH-1 loop
tmp_or := '0';
for I in 0 to C_LMB_NUM_SLAVES-1 loop
tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
end loop; -- J
res(J) := tmp_or;
end loop; -- I
LMB_ReadDBus <= Res;
end if;
end process DBus_Oring;
end architecture IMP;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/a3d1bdff/hdl/src/vhdl/uartlite_rx.vhd
|
6
|
24708
|
-------------------------------------------------------------------------------
-- uartlite_rx - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: uartlite_rx.vhd
-- Version: v2.0
-- Description: UART Lite Receive Interface Module
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_srl_fifo_v1_0;
library lib_cdc_v1_0;
use lib_cdc_v1_0.cdc_sync;
-- dynshreg_i_f refered from proc_common_v4_0
-- srl_fifo_f refered from proc_common_v4_0
use lib_srl_fifo_v1_0.srl_fifo_f;
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- UART Lite generics
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
--
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
-- System Signals
-- Clk -- Clock signal
-- Rst -- Reset signal
-- UART Lite interface
-- RX -- Receive Data
-- Internal UART interface signals
-- EN_16x_Baud -- Enable signal which is 16x times baud rate
-- Read_RX_FIFO -- Read receive FIFO
-- Reset_RX_FIFO -- Reset receive FIFO
-- RX_Data -- Receive data output
-- RX_Data_Present -- Receive data present
-- RX_Buffer_Full -- Receive buffer full
-- RX_Frame_Error -- Receive frame error
-- RX_Overrun_Error -- Receive overrun error
-- RX_Parity_Error -- Receive parity error
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity uartlite_rx is
generic
(
C_FAMILY : string := "virtex7";
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
Clk : in std_logic;
Reset : in std_logic;
EN_16x_Baud : in std_logic;
RX : in std_logic;
Read_RX_FIFO : in std_logic;
Reset_RX_FIFO : in std_logic;
RX_Data : out std_logic_vector(0 to C_DATA_BITS-1);
RX_Data_Present : out std_logic;
RX_Buffer_Full : out std_logic;
RX_Frame_Error : out std_logic;
RX_Overrun_Error : out std_logic;
RX_Parity_Error : out std_logic
);
end entity uartlite_rx;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of uartlite_rx is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
type bo2sl_type is array(boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
---------------------------------------------------------------------------
-- Constant declarations
---------------------------------------------------------------------------
constant SERIAL_TO_PAR_LENGTH : integer :=
C_DATA_BITS + C_USE_PARITY;
constant STOP_BIT_POS : integer := SERIAL_TO_PAR_LENGTH;
constant DATA_LSB_POS : integer := SERIAL_TO_PAR_LENGTH;
constant CALC_PAR_POS : integer := SERIAL_TO_PAR_LENGTH;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
signal start_Edge_Detected : boolean;
signal start_Edge_Detected_Bit : std_logic;
signal running : boolean;
signal recycle : std_logic;
signal sample_Point : std_logic;
signal stop_Bit_Position : std_logic;
signal fifo_Write : std_logic;
signal fifo_din : std_logic_vector(0 to SERIAL_TO_PAR_LENGTH);
signal serial_to_Par : std_logic_vector(1 to SERIAL_TO_PAR_LENGTH);
signal calc_parity : std_logic;
signal parity : std_logic;
signal RX_Buffer_Full_I : std_logic;
signal RX_D1 : std_logic;
signal RX_D2 : std_logic;
signal rx_1 : std_logic;
signal rx_2 : std_logic;
signal rx_3 : std_logic;
signal rx_4 : std_logic;
signal rx_5 : std_logic;
signal rx_6 : std_logic;
signal rx_7 : std_logic;
signal rx_8 : std_logic;
signal rx_9 : std_logic;
signal rx_Data_Empty : std_logic := '0';
signal fifo_wr : std_logic;
signal fifo_rd : std_logic;
signal RX_FIFO_Reset : std_logic;
signal valid_rx : std_logic;
signal valid_start : std_logic;
signal frame_err_ocrd : std_logic;
signal frame_err : std_logic;
begin -- architecture RTL
---------------------------------------------------------------------------
-- RX_SAMPLING : Double sample RX to avoid meta-stability
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => RX,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => RX_D2,
scndry_vect_out => open
);
-- RX_SAMPLING: process (Clk) is
-- begin -- process RX_Sampling
-- if Clk'event and Clk = '1' then -- rising clock edge
-- if Reset = '1' then -- synchronous reset (active high)
-- RX_D1 <= '1';
-- RX_D2 <= '1';
-- else
-- RX_D1 <= RX;
-- RX_D2 <= RX_D1;
-- end if;
-- end if;
-- end process RX_SAMPLING;
-------------------------------------------------------------------------------
-- Detect a falling edge on RX and start a new reception if idle
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- detect the start of the frame
---------------------------------------------------------------------------
RX_DFFS : process (Clk) is
begin -- process Prev_RX_DFFS
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
rx_1 <= '0';
rx_2 <= '0';
rx_3 <= '0';
rx_4 <= '0';
rx_5 <= '0';
rx_6 <= '0';
rx_7 <= '0';
rx_8 <= '0';
rx_9 <= '0';
elsif (EN_16x_Baud = '1') then
rx_1 <= RX_D2;
rx_2 <= rx_1;
rx_3 <= rx_2;
rx_4 <= rx_3;
rx_5 <= rx_4;
rx_6 <= rx_5;
rx_7 <= rx_6;
rx_8 <= rx_7;
rx_9 <= rx_8;
end if;
end if;
end process RX_DFFS;
---------------------------------------------------------------------------
-- Start bit valid when RX is continuously low for atleast 8 samples
---------------------------------------------------------------------------
valid_start <= rx_8 or rx_7 or rx_6 or rx_5 or
rx_4 or rx_3 or rx_2 or rx_1;
---------------------------------------------------------------------------
-- START_EDGE_DFF : Start a new reception if idle
---------------------------------------------------------------------------
START_EDGE_DFF : process (Clk) is
begin -- process Start_Edge_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then
start_Edge_Detected <= false;
elsif (EN_16x_Baud = '1') then
start_Edge_Detected <= ((not running) and
(frame_err_ocrd = '0') and
(rx_9 = '1') and
(valid_start = '0'));
end if;
end if;
end process START_EDGE_DFF;
---------------------------------------------------------------------------
-- FRAME_ERR_CAPTURE : frame_err_ocrd is '1' when a frame error is occured
-- and deasserted when the next low to high on RX
---------------------------------------------------------------------------
FRAME_ERR_CAPTURE : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
frame_err_ocrd <= '0';
elsif (frame_err = '1') then
frame_err_ocrd <= '1';
elsif (RX_D2 = '1') then
frame_err_ocrd <= '0';
end if;
end if;
end process FRAME_ERR_CAPTURE;
---------------------------------------------------------------------------
-- VALID_XFER : valid_rx is '1' when a valid start edge detected
---------------------------------------------------------------------------
VALID_XFER : process (Clk) is
begin -- process valid_rx_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
valid_rx <= '0';
elsif (start_Edge_Detected = true) then
valid_rx <= '1';
elsif (fifo_Write = '1') then
valid_rx <= '0';
end if;
end if;
end process VALID_XFER;
---------------------------------------------------------------------------
-- RUNNING_DFF : Running is '1' during a reception
---------------------------------------------------------------------------
RUNNING_DFF : process (Clk) is
begin -- process Running_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
running <= false;
elsif (EN_16x_Baud = '1') then
if (start_Edge_Detected) then
running <= true;
elsif ((sample_Point = '1') and (stop_Bit_Position = '1')) then
running <= false;
end if;
end if;
end if;
end process RUNNING_DFF;
---------------------------------------------------------------------------
-- Boolean to std logic conversion of start edge
---------------------------------------------------------------------------
start_Edge_Detected_Bit <= '1' when start_Edge_Detected else '0';
---------------------------------------------------------------------------
-- After the start edge is detected, generate recycle to generate sample
-- point
---------------------------------------------------------------------------
recycle <= (valid_rx and (not stop_Bit_Position) and
(start_Edge_Detected_Bit or sample_Point));
-------------------------------------------------------------------------
-- DELAY_16_I : Keep regenerating new values into the 16 clock delay,
-- Starting with the first start_Edge_Detected_Bit and for every new
-- sample_points until stop_Bit_Position is reached
-------------------------------------------------------------------------
DELAY_16_I : entity axi_uartlite_v2_0.dynshreg_i_f
generic map
(
C_DEPTH => 16,
C_DWIDTH => 1,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Clken => EN_16x_Baud,
Addr => "1111",
Din(0) => recycle,
Dout(0) => sample_Point
);
---------------------------------------------------------------------------
-- STOP_BIT_HANDLER : Detect when the stop bit is received
---------------------------------------------------------------------------
STOP_BIT_HANDLER : process (Clk) is
begin -- process Stop_Bit_Handler
if Clk'event and Clk = '1' then -- rising clock edge
if (Reset = '1') then -- synchronous reset (active high)
stop_Bit_Position <= '0';
elsif (EN_16x_Baud = '1') then
if (stop_Bit_Position = '0') then
-- Start bit has reached the end of the shift register
-- (Stop bit position)
stop_Bit_Position <= sample_Point and
fifo_din(STOP_BIT_POS);
elsif (sample_Point = '1') then
-- if stop_Bit_Position is 1 clear it at next sample_Point
stop_Bit_Position <= '0';
end if;
end if;
end if;
end process STOP_BIT_HANDLER;
USING_PARITY_NO : if (C_USE_PARITY = 0) generate
RX_Parity_Error <= '0' ;
end generate USING_PARITY_NO;
---------------------------------------------------------------------------
-- USING_PARITY : Generate parity handling when C_USE_PARITY = 1
---------------------------------------------------------------------------
USING_PARITY : if (C_USE_PARITY = 1) generate
PARITY_DFF: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1' or start_Edge_Detected_Bit = '1') then
parity <= bo2sl(C_ODD_PARITY = 1);
elsif (EN_16x_Baud = '1') then
parity <= calc_parity;
end if;
end if;
end process PARITY_DFF;
calc_parity <= parity when (stop_Bit_Position or
(not sample_Point)) = '1'
else parity xor RX_D2;
RX_Parity_Error <= (EN_16x_Baud and sample_Point) and
(fifo_din(CALC_PAR_POS)) and not stop_Bit_Position
when running and (RX_D2 /= parity) else '0';
end generate USING_PARITY;
fifo_din(0) <= RX_D2 and not Reset;
---------------------------------------------------------------------------
-- SERIAL_TO_PARALLEL : Serial to parrallel conversion data part
---------------------------------------------------------------------------
SERIAL_TO_PARALLEL : for i in 1 to serial_to_Par'length generate
serial_to_Par(i) <= fifo_din(i) when (stop_Bit_Position or
not sample_Point) = '1'
else fifo_din(i-1);
BIT_I: Process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (Reset = '1') then
fifo_din(i) <= '0'; -- Bit STOP_BIT_POS resets to '0';
else -- others to '1'
if (start_Edge_Detected_Bit = '1') then
fifo_din(i) <= bo2sl(i=1); -- Bit 1 resets to '1';
-- others to '0'
elsif (EN_16x_Baud = '1') then
fifo_din(i) <= serial_to_Par(i);
end if;
end if;
end if;
end process BIT_I;
end generate SERIAL_TO_PARALLEL;
--------------------------------------------------------------------------
-- FIFO_WRITE_DFF : Write in the received word when the stop_bit has been
-- received and it is a '1'
--------------------------------------------------------------------------
FIFO_WRITE_DFF : process (Clk) is
begin -- process FIFO_Write_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then -- synchronous reset (active high)
fifo_Write <= '0';
else
fifo_Write <= stop_Bit_Position and RX_D2 and sample_Point
and EN_16x_Baud;
end if;
end if;
end process FIFO_WRITE_DFF;
frame_err <= stop_Bit_Position and sample_Point and EN_16x_Baud
and not RX_D2;
RX_Frame_Error <= frame_err;
--------------------------------------------------------------------------
-- Write RX FIFO when FIFO is not full when valid data is reveived
--------------------------------------------------------------------------
fifo_wr <= fifo_Write and (not RX_Buffer_Full_I) and valid_rx;
--------------------------------------------------------------------------
-- Read RX FIFO when FIFO is not empty when AXI reads data from RX FIFO
--------------------------------------------------------------------------
fifo_rd <= Read_RX_FIFO and (not rx_Data_Empty);
--------------------------------------------------------------------------
-- Reset RX FIFO when requested from the control register or system reset
--------------------------------------------------------------------------
RX_FIFO_Reset <= Reset_RX_FIFO or Reset;
---------------------------------------------------------------------------
-- SRL_FIFO_I : Receive FIFO Interface
---------------------------------------------------------------------------
SRL_FIFO_I : entity lib_srl_fifo_v1_0.srl_fifo_f
generic map
(
C_DWIDTH => C_DATA_BITS,
C_DEPTH => 16,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Reset => RX_FIFO_Reset,
FIFO_Write => fifo_wr,
Data_In => fifo_din((DATA_LSB_POS-C_DATA_BITS + 1) to DATA_LSB_POS),
FIFO_Read => fifo_rd,
Data_Out => RX_Data,
FIFO_Full => RX_Buffer_Full_I,
FIFO_Empty => rx_Data_Empty,
Addr => open
);
RX_Data_Present <= not rx_Data_Empty;
RX_Overrun_Error <= RX_Buffer_Full_I and fifo_Write; -- Note that if
-- the RX FIFO is read on the same cycle as it is written while full,
-- there is no loss of data. However this case is not optimized and
-- is also reported as an overrun.
RX_Buffer_Full <= RX_Buffer_Full_I;
end architecture RTL;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/rx_statemachine.vhd
|
4
|
43053
|
-------------------------------------------------------------------------------
-- rx_statemachine - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : rx_statemachine.vhd
-- Version : v2.0
-- Description : This file contains the receive control state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Emac_rx_rd_data -- RX FIFO read data to controller
-- Rcv_en -- Receive enable
-- RxBusFifoRdAck -- RX FIFO read ack
-- BusFifoEmpty -- RX FIFO empty
-- Collision -- Collision detected
-- DataValid -- Data valid from PHY
-- RxError -- Receive error
-- BusFifoData -- RX FIFO data
-- CrcOk -- CRC correct in the receive data
-- BusFifoRd -- RX FIFO read
-- RxAbortRst -- Receive abort
-- RxCrcRst -- Receive CRC reset
-- RxCrcEn -- RX CRC enable
-- Rx_addr_en -- Receive address enable
-- Rx_start -- Receive start
-- Rx_done -- Receive complete
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write read enable
-- Rx_idle -- RX idle
-- Mac_addr_ram_addr_rd -- MAC Addr RAM read address
-- Mac_addr_ram_data -- MAC Addr RAM read data
-- Rx_buffer_ready -- RX buffer ready to accept new packet
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity rx_statemachine is
generic (
C_DUPLEX : integer := 1
-- 1 = full duplex, 0 = half duplex
);
port (
Clk : in std_logic;
Rst : in std_logic;
Emac_rx_rd_data_d1 : in std_logic_vector(0 to 5); -- 03-26-04
Receive_enable : out std_logic; -- 03-26-04
RxBusFifoRdAck : in std_logic;
BusFifoEmpty : in std_logic;
Collision : in std_logic;
DataValid : in std_logic;
RxError : in std_logic;
BusFifoData : in std_logic_vector(0 to 3);
CrcOk : in std_logic;
BusFifoRd : out std_logic;
RxAbortRst : out std_logic;
RxCrcRst : out std_logic;
RxCrcEn : out std_logic;
Rx_addr_en : out std_logic;
Rx_start : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_idle : out std_logic;
Mac_addr_ram_addr_rd : out std_logic_vector(0 to 3);
Mac_addr_ram_data : in std_logic_vector (0 to 3);
Rx_buffer_ready : in std_logic
);
end rx_statemachine;
architecture imp of rx_statemachine is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
signal idle : std_logic; -- state 0
signal waitForSfd1 : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal waitForSfd2 : std_logic; -- state 3
signal startReadDestAdrNib : std_logic; -- state 4
signal rdDestAddrNib_eq_0 : std_logic;
signal rdDestAddrNib_eq_12 : std_logic;
signal startReadDataNib : std_logic; -- state 17
signal crcCheck : std_logic; -- state 18
signal rxDone : std_logic; -- state 20
signal receiveRst : std_logic; -- state 21
signal rxCollision : std_logic; -- state 22
signal idle_D : std_logic; -- state 0
signal waitForSfd1_D : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty_D : std_logic; -- state 2
signal waitForSfd2_D : std_logic; -- state 3
signal startReadDestAdrNib_D : std_logic; -- state 4
signal startReadDataNib_D : std_logic; -- state 17
signal crcCheck_D : std_logic; -- state 18
signal rxDone_D : std_logic; -- state 20
signal receiveRst_D : std_logic; -- state 21
signal rxCollision_D : std_logic; -- state 22
signal goto_idle_1 : std_logic; -- state 0
signal goto_idle_2 : std_logic; -- state 0
signal goto_idle_3 : std_logic; -- state 0
signal goto_idle_4 : std_logic; -- state 0
signal goto_waitForSfd1 : std_logic; -- state 1
signal goto_sfd1CheckBusFifoEmpty_1 : std_logic; -- state 2
signal goto_sfd1CheckBusFifoEmpty_2 : std_logic; -- state 2
signal goto_waitForSfd2 : std_logic; -- state 3
signal goto_startReadDestAdrNib_1 : std_logic; -- state 4
signal goto_readDestAdrNib1 : std_logic; -- state 5
signal goto_startReadDataNib_2 : std_logic; -- state 17
signal goto_crcCheck : std_logic; -- state 18
signal goto_rxDone_3 : std_logic; -- state 20
signal goto_receiveRst_1 : std_logic; -- state 21
signal goto_receiveRst_2 : std_logic; -- state 21
signal goto_receiveRst_3 : std_logic; -- state 21
signal goto_receiveRst_5 : std_logic; -- state 21
signal goto_receiveRst_9 : std_logic; -- state 21
signal goto_receiveRst_10 : std_logic; -- state 21
signal goto_receiveRst_14 : std_logic; -- state 21
signal goto_rxCollision_1 : std_logic; -- state 22
signal goto_rxCollision_2 : std_logic; -- state 22
signal goto_rxCollision_5 : std_logic; -- state 22
signal stay_idle : std_logic; -- state 0
signal stay_sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal stay_startReadDestAdrNib : std_logic; -- state 4
signal stay_startReadDataNib : std_logic; -- state 17
signal state_machine_rst : std_logic;
signal full_half_n : std_logic;
signal checkingBroadcastAdr_i : std_logic;
signal checkingBroadcastAdr_reg : std_logic;
signal busFifoData_is_5 : std_logic;
signal busFifoData_is_13 : std_logic;
signal busFifoData_not_5 : std_logic;
signal busFifoData_not_13 : std_logic;
signal bcastAddrGood : std_logic;
signal ucastAddrGood : std_logic;
signal crcokr1 : std_logic;
signal crcokin : std_logic;
signal rxCrcEn_i : std_logic;
signal mac_addr_ram_addr_rd_D : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t_q : std_logic_vector(0 to 3);
signal rxDone_i : std_logic;
signal preamble_valid : std_logic;
signal preamble_error_reg : std_logic;
signal preamble_error : std_logic;
signal busFifoData_is_5_d1 : std_logic;
signal busFifoData_is_5_d2 : std_logic;
signal busFifoData_is_5_d3 : std_logic;
signal pkt_length_cnt : integer range 0 to 127;
signal crc_rst : std_logic;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDS
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- CRC check
----------------------------------------------------------------------------
crcokin <= ((CrcOk -- set
or crcokr1) -- keep
and (not(rxCrcEn_i) or CrcOk)); -- clear when 0
crcokdelay: FDR
port map (
Q => crcokr1, --[out]
C => Clk, --[in]
D => crcokin, --[in]
R => crc_rst --[in]
);
-- Added this to reset CRCokr1 before starting the next packet reception.
crc_rst <= Rst or (not CrcOk and crcokr1);
-- RX Complete indicator
Rx_done <= rxDone_i; -- added Rx_done output for ping pong control
-- Generate rxdone only if received framelength is greater than minimum
-- frame length
rxDone_i <= '1' when rxDone='1' and pkt_length_cnt=0 else
'0';
-- Check start of Frame
-- If receive data=5
busFifoData_is_5 <= not(BusFifoData(0)) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=5
busFifoData_not_5 <= not(busFifoData_is_5);
-- If receive data=13
busFifoData_is_13 <= BusFifoData(0) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=13
busFifoData_not_13 <= not(busFifoData_is_13);
-- State Machine Reset
state_machine_rst <= Rst;
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
goto_idle_1 <= rxDone;
goto_idle_2 <= receiveRst;
goto_idle_3 <= waitForSfd1 and (not(DataValid) or busFifoData_not_5);
goto_idle_4 <= waitForSfd2 and (not(DataValid) or
(busFifoData_not_5 and busFifoData_not_13));
stay_idle <= idle and not(goto_waitForSfd1);
idle_D <= goto_idle_1 or goto_idle_2 or goto_idle_3 or goto_idle_4
or stay_idle;
state0a: FDS
port map (
Q => idle, --[out]
C => Clk, --[in]
D => idle_D, --[in]
S => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd1 state
----------------------------------------------------------------------------
goto_waitForSfd1 <= idle and (RxBusFifoRdAck or not(BusFifoEmpty))
and (Rx_buffer_ready);
waitForSfd1_D <= goto_waitForSfd1;
state1a: FDR
port map (
Q => waitForSfd1, --[out]
C => Clk, --[in]
D => waitForSfd1_D, --[in]
R => state_machine_rst --[in]
);
Rx_idle <= idle or waitForSfd1;
----------------------------------------------------------------------------
-- sfd1CheckBusFifoEmpty state
----------------------------------------------------------------------------
goto_sfd1CheckBusFifoEmpty_1 <= waitForSfd1 and busFifoData_is_5
and DataValid;
goto_sfd1CheckBusFifoEmpty_2 <= waitForSfd2 and busFifoData_is_5
and DataValid;
stay_sfd1CheckBusFifoEmpty <= sfd1CheckBusFifoEmpty and
not(goto_rxCollision_1) and
not(goto_receiveRst_1) and
not(goto_waitForSfd2);
sfd1CheckBusFifoEmpty_D <= goto_sfd1CheckBusFifoEmpty_1 or
goto_sfd1CheckBusFifoEmpty_2 or
stay_sfd1CheckBusFifoEmpty;
state2a: FDR
port map (
Q => sfd1CheckBusFifoEmpty, --[out]
C => Clk, --[in]
D => sfd1CheckBusFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd2 state
----------------------------------------------------------------------------
goto_waitForSfd2 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1) and
not(goto_receiveRst_1) and (RxBusFifoRdAck or
not(BusFifoEmpty)) and
busFifoData_is_5;
waitForSfd2_D <= goto_waitForSfd2;
state3a: FDR
port map (
Q => waitForSfd2, --[out]
C => Clk, --[in]
D => waitForSfd2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--startReadDestAdrNib state
----------------------------------------------------------------------------
goto_startReadDestAdrNib_1 <= waitForSfd2 and busFifoData_is_13
and preamble_valid
and DataValid;
stay_startReadDestAdrNib <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
not(goto_readDestAdrNib1);
startReadDestAdrNib_D <= goto_startReadDestAdrNib_1 or
stay_startReadDestAdrNib;
state4a: FDR
port map (
Q => startReadDestAdrNib, --[out]
C => Clk, --[in]
D => startReadDestAdrNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--readDestAdrNib1 state
----------------------------------------------------------------------------
goto_readDestAdrNib1 <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
RxBusFifoRdAck;
rdDestAddrNib_eq_0 <= bo2sl(rdDestAddrNib_D_t_q = "0000");
rdDestAddrNib_eq_12 <= bo2sl(rdDestAddrNib_D_t_q = "1011");
----------------------------------------------------------------------------
-- STATE_REG_PROCESS
----------------------------------------------------------------------------
-- Registeting the read destination address.
----------------------------------------------------------------------------
STATE_REG_PROCESS : process (Clk)
begin
if (Clk'event and Clk='1') then
if (state_machine_rst = '1' or
goto_startReadDestAdrNib_1 = '1') then
rdDestAddrNib_D_t_q <= "0000";
else
rdDestAddrNib_D_t_q <= rdDestAddrNib_D_t;
end if;
end if;
end process STATE_REG_PROCESS;
----------------------------------------------------------------------------
-- FSM_CMB_PROCESS
----------------------------------------------------------------------------
-- This process generate read destination address for the MAC address RAM
-- for the received frame.
----------------------------------------------------------------------------
FSM_CMB_PROCESS : process (startReadDestAdrNib,goto_rxCollision_2,
goto_receiveRst_2,RxBusFifoRdAck,goto_receiveRst_3,bcastAddrGood,
ucastAddrGood,goto_receiveRst_5,
rdDestAddrNib_D_t_q)
begin
----
rdDestAddrNib_D_t <= rdDestAddrNib_D_t_q;
case (rdDestAddrNib_D_t_q) is
when "0000" =>
if (startReadDestAdrNib and not(goto_rxCollision_2) and
not(goto_receiveRst_2) and RxBusFifoRdAck) = '1' then
rdDestAddrNib_D_t <= "0001";
else
rdDestAddrNib_D_t <= "0000";
end if;
when "0001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0001";
end if;
when "0010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0010";
end if;
when "0011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0011";
end if;
when "0100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0101";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0100";
end if;
when "0101" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0110";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0101";
end if;
when "0110" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0111";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0110";
end if;
when "0111" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0111";
end if;
when "1000" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1001";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1000";
end if;
when "1001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1001";
end if;
when "1010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1010";
end if;
when "1011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1011";
end if;
when "1100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1100";
end if;
when others => null;
end case;
end process FSM_CMB_PROCESS;
----------------------------------------------------------------------------
--startReadDataNib state
----------------------------------------------------------------------------
goto_startReadDataNib_2 <= rdDestAddrNib_eq_12 and RxBusFifoRdAck and
(bcastAddrGood or ucastAddrGood) and not(goto_receiveRst_5) and
not(goto_receiveRst_3);
stay_startReadDataNib <= startReadDataNib and not(goto_rxCollision_5)
and not(goto_receiveRst_9) and DataValid;
startReadDataNib_D <= goto_startReadDataNib_2
or stay_startReadDataNib;
state17a: FDR
port map (
Q => startReadDataNib, --[out]
C => Clk, --[in]
D => startReadDataNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--crcCheck state
----------------------------------------------------------------------------
goto_crcCheck <= startReadDataNib and not(DataValid) ;
goto_receiveRst_1 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1)
and RxError;
goto_receiveRst_2 <= startReadDestAdrNib and not(goto_rxCollision_2)
and RxError;
goto_receiveRst_9 <= startReadDataNib and not(goto_rxCollision_5)
and RxError;
crcCheck_D <= goto_crcCheck or goto_receiveRst_1 or
goto_receiveRst_2 or
goto_receiveRst_9;
state18a: FDR
port map (
Q => crcCheck, --[out]
C => Clk, --[in]
D => crcCheck_D, --[in]
R => state_machine_rst --[in]
);
-------------------------------------------------------------------------------
--rxDone state
-------------------------------------------------------------------------------
--goto_rxDone_3 <= writeFinalData ;
goto_rxDone_3 <= crcCheck and crcokr1;
rxDone_D <= goto_rxDone_3 ;
state20a: FDR
port map (
Q => rxDone, --[out]
C => Clk, --[in]
D => rxDone_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--rxCollision state
----------------------------------------------------------------------------
full_half_n <= '1'when C_DUPLEX = 1 else
'0';
goto_rxCollision_1 <= sfd1CheckBusFifoEmpty and Collision
and not(full_half_n);
goto_rxCollision_2 <= startReadDestAdrNib and Collision
and not(full_half_n);
goto_rxCollision_5 <= startReadDataNib and Collision
and not(full_half_n);
rxCollision_D <= goto_rxCollision_1 or goto_rxCollision_2 or
goto_rxCollision_5;
state21a: FDR
port map (
Q => rxCollision, --[out]
C => Clk, --[in]
D => rxCollision_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--receiveRst state
----------------------------------------------------------------------------
goto_receiveRst_3 <= not rdDestAddrNib_eq_0 and not(DataValid);
goto_receiveRst_5 <= not rdDestAddrNib_eq_0 and
not(BusFifoEmpty) and
not(bcastAddrGood or ucastAddrGood);
goto_receiveRst_10<= crcCheck and not(crcokr1);
goto_receiveRst_14<= rxCollision;
receiveRst_D <= goto_receiveRst_3 or
goto_receiveRst_5 or
goto_receiveRst_10 or
goto_receiveRst_14 or
preamble_error_reg;
state22a: FDR
port map (
Q => receiveRst, --[out]
C => Clk, --[in]
D => receiveRst_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- end of states
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- BROADCAST_ADDR_REG
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
BROADCAST_ADDR_REG : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
checkingBroadcastAdr_reg <= '0';
else
checkingBroadcastAdr_reg <= checkingBroadcastAdr_i;
end if;
end if;
end process BROADCAST_ADDR_REG;
----------------------------------------------------------------------------
-- RX_FSMD_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
RX_FSMD_PROCESS : process( DataValid,RxBusFifoRdAck,idle,
startReadDestAdrNib, startReadDataNib,
sfd1CheckBusFifoEmpty, rxDone, receiveRst,
waitForSfd2, Emac_rx_rd_data_d1,
checkingBroadcastAdr_reg, rdDestAddrNib_eq_0,
rdDestAddrNib_D_t_q)
begin
-- Reset RX CRC in idle state
if (idle = '1') then
RxCrcRst <= '1';
else
RxCrcRst <= '0';
end if;
-- RX CRC enable
if ((( startReadDestAdrNib or (not rdDestAddrNib_eq_0) or
(startReadDataNib and DataValid))
and RxBusFifoRdAck) = '1') then
RxCrcEn <= '1';
rxCrcEn_i <= '1';
else
RxCrcEn <= '0';
rxCrcEn_i <= '0';
end if;
-- RX buffer FIFO read enable
if ((idle = '1') or
(sfd1CheckBusFifoEmpty = '1') or
(not rdDestAddrNib_eq_0 = '1') or
(rxDone = '1') or -- 03-26-04
(startReadDestAdrNib = '1') or
(startReadDataNib = '1')) and (RxBusFifoRdAck = '0')then
BusFifoRd <= '1';
else
BusFifoRd <= '0';
end if;
-- RX abort reset
if (receiveRst = '1') then
RxAbortRst <= '1';
else
RxAbortRst <= '0';
end if;
-- RX buffer address enable
if RxBusFifoRdAck = '1' and
(
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) then
Rx_addr_en <= '1'; --enable address increment
else
Rx_addr_en <= '0';
end if;
-- Generate RX start after SFD is detected
if (waitForSfd2 = '1')then
Rx_start <= '1'; -- reset address to 0 for start of receive
else
Rx_start <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') or
((
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) and (RxBusFifoRdAck = '1')
) then
Rx_DPM_ce <= '1';
else
Rx_DPM_ce <= '0';
end if;
-- RX buffer read/write enable
if (startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1') then
Rx_DPM_wr_rd_n <= '1';
else
Rx_DPM_wr_rd_n <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') then
checkingBroadcastAdr_i <= '0'; -- reset
-- 06-09-04 Use delayed data for compare
elsif (rdDestAddrNib_D_t_q = x"1" and
Emac_rx_rd_data_d1(0 to 3) = x"f") then
checkingBroadcastAdr_i <= '1'; -- set
else
checkingBroadcastAdr_i <= checkingBroadcastAdr_reg; -- stay the same
end if;
end process RX_FSMD_PROCESS;
-- write data to Receive DPRAM
Rx_DPM_wr_data <= BusFifoData;
----------------------------------------------------------------------------
-- MARAR_PROC
----------------------------------------------------------------------------
-- This process generate MAC RAM address to get mac addres to compare with
-- incoming frame destination address
----------------------------------------------------------------------------
MARAR_PROC : process (rdDestAddrNib_D_t, idle_D, startReadDestAdrNib_D)
begin
case rdDestAddrNib_D_t is
when "0001" => mac_addr_ram_addr_rd_D <= x"0";
when "0010" => mac_addr_ram_addr_rd_D <= x"1";
when "0011" => mac_addr_ram_addr_rd_D <= x"2";
when "0100" => mac_addr_ram_addr_rd_D <= x"3";
when "0101" => mac_addr_ram_addr_rd_D <= x"4";
when "0110" => mac_addr_ram_addr_rd_D <= x"5";
when "0111" => mac_addr_ram_addr_rd_D <= x"6";
when "1000" => mac_addr_ram_addr_rd_D <= x"7";
when "1001" => mac_addr_ram_addr_rd_D <= x"8";
when "1010" => mac_addr_ram_addr_rd_D <= x"9";
when "1011" => mac_addr_ram_addr_rd_D <= x"a";
when "1100" => mac_addr_ram_addr_rd_D <= x"b";
when others => mac_addr_ram_addr_rd_D <= x"0";
end case;
-- Reset the address in idle or start of new frame
if (idle_D or startReadDestAdrNib_D) = '1' then
mac_addr_ram_addr_rd_D <= x"0";
end if;
end process MARAR_PROC;
----------------------------------------------------------------------------
-- OUTPUT_REG
----------------------------------------------------------------------------
-- Registerit the mac_addr_ram_addr_rd
----------------------------------------------------------------------------
OUTPUT_REG:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Mac_addr_ram_addr_rd <= (others => '0');
else
Mac_addr_ram_addr_rd <= mac_addr_ram_addr_rd_D;
end if;
end if;
end process OUTPUT_REG;
----------------------------------------------------------------------------
-- Check if the incoming packet is broadcast packet
----------------------------------------------------------------------------
bcastAddrGood <= '1' when checkingBroadcastAdr_i = '1' and
Emac_rx_rd_data_d1(0 to 3) = x"F" else -- 03-26-04
'0';
----------------------------------------------------------------------------
-- Check if the incoming packet is unicast and address matches to core
-- MAC address
----------------------------------------------------------------------------
ucastAddrGood <= '1' when checkingBroadcastAdr_i = '0' and
(Emac_rx_rd_data_d1(0 to 3) = Mac_addr_ram_data)
else -- 03-26-04
'0';
-- Genarate Receive enable
Receive_enable <= not(crcCheck or rxDone or receiveRst);
----------------------------------------------------------------------------
-- PROCESS : PKT_LENGTH_COUNTER
----------------------------------------------------------------------------
-- This counter is used to check if the receive packet length is greater
-- minimum packet length (64 byte - 128 nibble)
----------------------------------------------------------------------------
PKT_LENGTH_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' or preamble_error_reg = '1' ) then
pkt_length_cnt <= 0;
elsif goto_readDestAdrNib1 = '1' then -- load the counter for
pkt_length_cnt <= 127; -- minimum packet length
elsif (rxCrcEn_i='1') then -- Enable Down Counter
if (pkt_length_cnt = 0) then
pkt_length_cnt <= 0;
else
pkt_length_cnt <= pkt_length_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : SFD_CHECK_REG
----------------------------------------------------------------------------
-- This process registers the preamble nibble to checl if atleast last 2
-- preamble nibbles are valid before the SFD nibble.
----------------------------------------------------------------------------
SFD_CHECK_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
busFifoData_is_5_d1 <= '0';
busFifoData_is_5_d2 <= '0';
busFifoData_is_5_d3 <= '0';
elsif RxBusFifoRdAck = '1' then
busFifoData_is_5_d1 <= busFifoData_is_5;
busFifoData_is_5_d2 <= busFifoData_is_5_d1;
busFifoData_is_5_d3 <= busFifoData_is_5_d2;
end if;
end if;
end process;
preamble: FDR
port map (
Q => preamble_error_reg, --[out]
C => Clk, --[in]
D => preamble_error, --[in]
R => state_machine_rst --[in]
);
-- Premable valid
preamble_valid <= (busFifoData_is_5_d1) and
busFifoData_is_13;
-- Premable Error
preamble_error <= (not busFifoData_is_5 and
busFifoData_is_5_d1 and
not busFifoData_is_13) and waitForSfd2 ;
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/rx_statemachine.vhd
|
4
|
43053
|
-------------------------------------------------------------------------------
-- rx_statemachine - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : rx_statemachine.vhd
-- Version : v2.0
-- Description : This file contains the receive control state machine.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.all;
-- synopsys translate_off
-- Library XilinxCoreLib;
--library simprim;
-- synopsys translate_on
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- Emac_rx_rd_data -- RX FIFO read data to controller
-- Rcv_en -- Receive enable
-- RxBusFifoRdAck -- RX FIFO read ack
-- BusFifoEmpty -- RX FIFO empty
-- Collision -- Collision detected
-- DataValid -- Data valid from PHY
-- RxError -- Receive error
-- BusFifoData -- RX FIFO data
-- CrcOk -- CRC correct in the receive data
-- BusFifoRd -- RX FIFO read
-- RxAbortRst -- Receive abort
-- RxCrcRst -- Receive CRC reset
-- RxCrcEn -- RX CRC enable
-- Rx_addr_en -- Receive address enable
-- Rx_start -- Receive start
-- Rx_done -- Receive complete
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write read enable
-- Rx_idle -- RX idle
-- Mac_addr_ram_addr_rd -- MAC Addr RAM read address
-- Mac_addr_ram_data -- MAC Addr RAM read data
-- Rx_buffer_ready -- RX buffer ready to accept new packet
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity rx_statemachine is
generic (
C_DUPLEX : integer := 1
-- 1 = full duplex, 0 = half duplex
);
port (
Clk : in std_logic;
Rst : in std_logic;
Emac_rx_rd_data_d1 : in std_logic_vector(0 to 5); -- 03-26-04
Receive_enable : out std_logic; -- 03-26-04
RxBusFifoRdAck : in std_logic;
BusFifoEmpty : in std_logic;
Collision : in std_logic;
DataValid : in std_logic;
RxError : in std_logic;
BusFifoData : in std_logic_vector(0 to 3);
CrcOk : in std_logic;
BusFifoRd : out std_logic;
RxAbortRst : out std_logic;
RxCrcRst : out std_logic;
RxCrcEn : out std_logic;
Rx_addr_en : out std_logic;
Rx_start : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_idle : out std_logic;
Mac_addr_ram_addr_rd : out std_logic_vector(0 to 3);
Mac_addr_ram_data : in std_logic_vector (0 to 3);
Rx_buffer_ready : in std_logic
);
end rx_statemachine;
architecture imp of rx_statemachine is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
signal idle : std_logic; -- state 0
signal waitForSfd1 : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal waitForSfd2 : std_logic; -- state 3
signal startReadDestAdrNib : std_logic; -- state 4
signal rdDestAddrNib_eq_0 : std_logic;
signal rdDestAddrNib_eq_12 : std_logic;
signal startReadDataNib : std_logic; -- state 17
signal crcCheck : std_logic; -- state 18
signal rxDone : std_logic; -- state 20
signal receiveRst : std_logic; -- state 21
signal rxCollision : std_logic; -- state 22
signal idle_D : std_logic; -- state 0
signal waitForSfd1_D : std_logic; -- state 1
signal sfd1CheckBusFifoEmpty_D : std_logic; -- state 2
signal waitForSfd2_D : std_logic; -- state 3
signal startReadDestAdrNib_D : std_logic; -- state 4
signal startReadDataNib_D : std_logic; -- state 17
signal crcCheck_D : std_logic; -- state 18
signal rxDone_D : std_logic; -- state 20
signal receiveRst_D : std_logic; -- state 21
signal rxCollision_D : std_logic; -- state 22
signal goto_idle_1 : std_logic; -- state 0
signal goto_idle_2 : std_logic; -- state 0
signal goto_idle_3 : std_logic; -- state 0
signal goto_idle_4 : std_logic; -- state 0
signal goto_waitForSfd1 : std_logic; -- state 1
signal goto_sfd1CheckBusFifoEmpty_1 : std_logic; -- state 2
signal goto_sfd1CheckBusFifoEmpty_2 : std_logic; -- state 2
signal goto_waitForSfd2 : std_logic; -- state 3
signal goto_startReadDestAdrNib_1 : std_logic; -- state 4
signal goto_readDestAdrNib1 : std_logic; -- state 5
signal goto_startReadDataNib_2 : std_logic; -- state 17
signal goto_crcCheck : std_logic; -- state 18
signal goto_rxDone_3 : std_logic; -- state 20
signal goto_receiveRst_1 : std_logic; -- state 21
signal goto_receiveRst_2 : std_logic; -- state 21
signal goto_receiveRst_3 : std_logic; -- state 21
signal goto_receiveRst_5 : std_logic; -- state 21
signal goto_receiveRst_9 : std_logic; -- state 21
signal goto_receiveRst_10 : std_logic; -- state 21
signal goto_receiveRst_14 : std_logic; -- state 21
signal goto_rxCollision_1 : std_logic; -- state 22
signal goto_rxCollision_2 : std_logic; -- state 22
signal goto_rxCollision_5 : std_logic; -- state 22
signal stay_idle : std_logic; -- state 0
signal stay_sfd1CheckBusFifoEmpty : std_logic; -- state 2
signal stay_startReadDestAdrNib : std_logic; -- state 4
signal stay_startReadDataNib : std_logic; -- state 17
signal state_machine_rst : std_logic;
signal full_half_n : std_logic;
signal checkingBroadcastAdr_i : std_logic;
signal checkingBroadcastAdr_reg : std_logic;
signal busFifoData_is_5 : std_logic;
signal busFifoData_is_13 : std_logic;
signal busFifoData_not_5 : std_logic;
signal busFifoData_not_13 : std_logic;
signal bcastAddrGood : std_logic;
signal ucastAddrGood : std_logic;
signal crcokr1 : std_logic;
signal crcokin : std_logic;
signal rxCrcEn_i : std_logic;
signal mac_addr_ram_addr_rd_D : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t : std_logic_vector(0 to 3);
signal rdDestAddrNib_D_t_q : std_logic_vector(0 to 3);
signal rxDone_i : std_logic;
signal preamble_valid : std_logic;
signal preamble_error_reg : std_logic;
signal preamble_error : std_logic;
signal busFifoData_is_5_d1 : std_logic;
signal busFifoData_is_5_d2 : std_logic;
signal busFifoData_is_5_d3 : std_logic;
signal pkt_length_cnt : integer range 0 to 127;
signal crc_rst : std_logic;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDS
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------
-- CRC check
----------------------------------------------------------------------------
crcokin <= ((CrcOk -- set
or crcokr1) -- keep
and (not(rxCrcEn_i) or CrcOk)); -- clear when 0
crcokdelay: FDR
port map (
Q => crcokr1, --[out]
C => Clk, --[in]
D => crcokin, --[in]
R => crc_rst --[in]
);
-- Added this to reset CRCokr1 before starting the next packet reception.
crc_rst <= Rst or (not CrcOk and crcokr1);
-- RX Complete indicator
Rx_done <= rxDone_i; -- added Rx_done output for ping pong control
-- Generate rxdone only if received framelength is greater than minimum
-- frame length
rxDone_i <= '1' when rxDone='1' and pkt_length_cnt=0 else
'0';
-- Check start of Frame
-- If receive data=5
busFifoData_is_5 <= not(BusFifoData(0)) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=5
busFifoData_not_5 <= not(busFifoData_is_5);
-- If receive data=13
busFifoData_is_13 <= BusFifoData(0) and BusFifoData(1) and
not(BusFifoData(2)) and BusFifoData(3);
-- If receive data/=13
busFifoData_not_13 <= not(busFifoData_is_13);
-- State Machine Reset
state_machine_rst <= Rst;
----------------------------------------------------------------------------
-- idle state
----------------------------------------------------------------------------
goto_idle_1 <= rxDone;
goto_idle_2 <= receiveRst;
goto_idle_3 <= waitForSfd1 and (not(DataValid) or busFifoData_not_5);
goto_idle_4 <= waitForSfd2 and (not(DataValid) or
(busFifoData_not_5 and busFifoData_not_13));
stay_idle <= idle and not(goto_waitForSfd1);
idle_D <= goto_idle_1 or goto_idle_2 or goto_idle_3 or goto_idle_4
or stay_idle;
state0a: FDS
port map (
Q => idle, --[out]
C => Clk, --[in]
D => idle_D, --[in]
S => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd1 state
----------------------------------------------------------------------------
goto_waitForSfd1 <= idle and (RxBusFifoRdAck or not(BusFifoEmpty))
and (Rx_buffer_ready);
waitForSfd1_D <= goto_waitForSfd1;
state1a: FDR
port map (
Q => waitForSfd1, --[out]
C => Clk, --[in]
D => waitForSfd1_D, --[in]
R => state_machine_rst --[in]
);
Rx_idle <= idle or waitForSfd1;
----------------------------------------------------------------------------
-- sfd1CheckBusFifoEmpty state
----------------------------------------------------------------------------
goto_sfd1CheckBusFifoEmpty_1 <= waitForSfd1 and busFifoData_is_5
and DataValid;
goto_sfd1CheckBusFifoEmpty_2 <= waitForSfd2 and busFifoData_is_5
and DataValid;
stay_sfd1CheckBusFifoEmpty <= sfd1CheckBusFifoEmpty and
not(goto_rxCollision_1) and
not(goto_receiveRst_1) and
not(goto_waitForSfd2);
sfd1CheckBusFifoEmpty_D <= goto_sfd1CheckBusFifoEmpty_1 or
goto_sfd1CheckBusFifoEmpty_2 or
stay_sfd1CheckBusFifoEmpty;
state2a: FDR
port map (
Q => sfd1CheckBusFifoEmpty, --[out]
C => Clk, --[in]
D => sfd1CheckBusFifoEmpty_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- waitForSfd2 state
----------------------------------------------------------------------------
goto_waitForSfd2 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1) and
not(goto_receiveRst_1) and (RxBusFifoRdAck or
not(BusFifoEmpty)) and
busFifoData_is_5;
waitForSfd2_D <= goto_waitForSfd2;
state3a: FDR
port map (
Q => waitForSfd2, --[out]
C => Clk, --[in]
D => waitForSfd2_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--startReadDestAdrNib state
----------------------------------------------------------------------------
goto_startReadDestAdrNib_1 <= waitForSfd2 and busFifoData_is_13
and preamble_valid
and DataValid;
stay_startReadDestAdrNib <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
not(goto_readDestAdrNib1);
startReadDestAdrNib_D <= goto_startReadDestAdrNib_1 or
stay_startReadDestAdrNib;
state4a: FDR
port map (
Q => startReadDestAdrNib, --[out]
C => Clk, --[in]
D => startReadDestAdrNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--readDestAdrNib1 state
----------------------------------------------------------------------------
goto_readDestAdrNib1 <= startReadDestAdrNib and
not(goto_rxCollision_2) and
not(goto_receiveRst_2) and
RxBusFifoRdAck;
rdDestAddrNib_eq_0 <= bo2sl(rdDestAddrNib_D_t_q = "0000");
rdDestAddrNib_eq_12 <= bo2sl(rdDestAddrNib_D_t_q = "1011");
----------------------------------------------------------------------------
-- STATE_REG_PROCESS
----------------------------------------------------------------------------
-- Registeting the read destination address.
----------------------------------------------------------------------------
STATE_REG_PROCESS : process (Clk)
begin
if (Clk'event and Clk='1') then
if (state_machine_rst = '1' or
goto_startReadDestAdrNib_1 = '1') then
rdDestAddrNib_D_t_q <= "0000";
else
rdDestAddrNib_D_t_q <= rdDestAddrNib_D_t;
end if;
end if;
end process STATE_REG_PROCESS;
----------------------------------------------------------------------------
-- FSM_CMB_PROCESS
----------------------------------------------------------------------------
-- This process generate read destination address for the MAC address RAM
-- for the received frame.
----------------------------------------------------------------------------
FSM_CMB_PROCESS : process (startReadDestAdrNib,goto_rxCollision_2,
goto_receiveRst_2,RxBusFifoRdAck,goto_receiveRst_3,bcastAddrGood,
ucastAddrGood,goto_receiveRst_5,
rdDestAddrNib_D_t_q)
begin
----
rdDestAddrNib_D_t <= rdDestAddrNib_D_t_q;
case (rdDestAddrNib_D_t_q) is
when "0000" =>
if (startReadDestAdrNib and not(goto_rxCollision_2) and
not(goto_receiveRst_2) and RxBusFifoRdAck) = '1' then
rdDestAddrNib_D_t <= "0001";
else
rdDestAddrNib_D_t <= "0000";
end if;
when "0001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0001";
end if;
when "0010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0010";
end if;
when "0011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0011";
end if;
when "0100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0101";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0100";
end if;
when "0101" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0110";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0101";
end if;
when "0110" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0111";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0110";
end if;
when "0111" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "0111";
end if;
when "1000" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1001";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1000";
end if;
when "1001" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1010";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1001";
end if;
when "1010" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1011";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1010";
end if;
when "1011" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "1100";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1011";
end if;
when "1100" =>
if (RxBusFifoRdAck and (bcastAddrGood or ucastAddrGood) and
not(goto_receiveRst_5) and not(goto_receiveRst_3)) = '1' then
rdDestAddrNib_D_t <= "0000";
elsif goto_receiveRst_5='1' or goto_receiveRst_3='1' then
rdDestAddrNib_D_t <= "0000";
else
rdDestAddrNib_D_t <= "1100";
end if;
when others => null;
end case;
end process FSM_CMB_PROCESS;
----------------------------------------------------------------------------
--startReadDataNib state
----------------------------------------------------------------------------
goto_startReadDataNib_2 <= rdDestAddrNib_eq_12 and RxBusFifoRdAck and
(bcastAddrGood or ucastAddrGood) and not(goto_receiveRst_5) and
not(goto_receiveRst_3);
stay_startReadDataNib <= startReadDataNib and not(goto_rxCollision_5)
and not(goto_receiveRst_9) and DataValid;
startReadDataNib_D <= goto_startReadDataNib_2
or stay_startReadDataNib;
state17a: FDR
port map (
Q => startReadDataNib, --[out]
C => Clk, --[in]
D => startReadDataNib_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--crcCheck state
----------------------------------------------------------------------------
goto_crcCheck <= startReadDataNib and not(DataValid) ;
goto_receiveRst_1 <= sfd1CheckBusFifoEmpty and not(goto_rxCollision_1)
and RxError;
goto_receiveRst_2 <= startReadDestAdrNib and not(goto_rxCollision_2)
and RxError;
goto_receiveRst_9 <= startReadDataNib and not(goto_rxCollision_5)
and RxError;
crcCheck_D <= goto_crcCheck or goto_receiveRst_1 or
goto_receiveRst_2 or
goto_receiveRst_9;
state18a: FDR
port map (
Q => crcCheck, --[out]
C => Clk, --[in]
D => crcCheck_D, --[in]
R => state_machine_rst --[in]
);
-------------------------------------------------------------------------------
--rxDone state
-------------------------------------------------------------------------------
--goto_rxDone_3 <= writeFinalData ;
goto_rxDone_3 <= crcCheck and crcokr1;
rxDone_D <= goto_rxDone_3 ;
state20a: FDR
port map (
Q => rxDone, --[out]
C => Clk, --[in]
D => rxDone_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--rxCollision state
----------------------------------------------------------------------------
full_half_n <= '1'when C_DUPLEX = 1 else
'0';
goto_rxCollision_1 <= sfd1CheckBusFifoEmpty and Collision
and not(full_half_n);
goto_rxCollision_2 <= startReadDestAdrNib and Collision
and not(full_half_n);
goto_rxCollision_5 <= startReadDataNib and Collision
and not(full_half_n);
rxCollision_D <= goto_rxCollision_1 or goto_rxCollision_2 or
goto_rxCollision_5;
state21a: FDR
port map (
Q => rxCollision, --[out]
C => Clk, --[in]
D => rxCollision_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
--receiveRst state
----------------------------------------------------------------------------
goto_receiveRst_3 <= not rdDestAddrNib_eq_0 and not(DataValid);
goto_receiveRst_5 <= not rdDestAddrNib_eq_0 and
not(BusFifoEmpty) and
not(bcastAddrGood or ucastAddrGood);
goto_receiveRst_10<= crcCheck and not(crcokr1);
goto_receiveRst_14<= rxCollision;
receiveRst_D <= goto_receiveRst_3 or
goto_receiveRst_5 or
goto_receiveRst_10 or
goto_receiveRst_14 or
preamble_error_reg;
state22a: FDR
port map (
Q => receiveRst, --[out]
C => Clk, --[in]
D => receiveRst_D, --[in]
R => state_machine_rst --[in]
);
----------------------------------------------------------------------------
-- end of states
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- BROADCAST_ADDR_REG
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
BROADCAST_ADDR_REG : process (Clk)
begin --
if (Clk'event and Clk = '1') then -- rising clock edge
if (Rst = '1') then
checkingBroadcastAdr_reg <= '0';
else
checkingBroadcastAdr_reg <= checkingBroadcastAdr_i;
end if;
end if;
end process BROADCAST_ADDR_REG;
----------------------------------------------------------------------------
-- RX_FSMD_PROCESS
----------------------------------------------------------------------------
-- This process generate control signals for the state machine.
----------------------------------------------------------------------------
RX_FSMD_PROCESS : process( DataValid,RxBusFifoRdAck,idle,
startReadDestAdrNib, startReadDataNib,
sfd1CheckBusFifoEmpty, rxDone, receiveRst,
waitForSfd2, Emac_rx_rd_data_d1,
checkingBroadcastAdr_reg, rdDestAddrNib_eq_0,
rdDestAddrNib_D_t_q)
begin
-- Reset RX CRC in idle state
if (idle = '1') then
RxCrcRst <= '1';
else
RxCrcRst <= '0';
end if;
-- RX CRC enable
if ((( startReadDestAdrNib or (not rdDestAddrNib_eq_0) or
(startReadDataNib and DataValid))
and RxBusFifoRdAck) = '1') then
RxCrcEn <= '1';
rxCrcEn_i <= '1';
else
RxCrcEn <= '0';
rxCrcEn_i <= '0';
end if;
-- RX buffer FIFO read enable
if ((idle = '1') or
(sfd1CheckBusFifoEmpty = '1') or
(not rdDestAddrNib_eq_0 = '1') or
(rxDone = '1') or -- 03-26-04
(startReadDestAdrNib = '1') or
(startReadDataNib = '1')) and (RxBusFifoRdAck = '0')then
BusFifoRd <= '1';
else
BusFifoRd <= '0';
end if;
-- RX abort reset
if (receiveRst = '1') then
RxAbortRst <= '1';
else
RxAbortRst <= '0';
end if;
-- RX buffer address enable
if RxBusFifoRdAck = '1' and
(
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) then
Rx_addr_en <= '1'; --enable address increment
else
Rx_addr_en <= '0';
end if;
-- Generate RX start after SFD is detected
if (waitForSfd2 = '1')then
Rx_start <= '1'; -- reset address to 0 for start of receive
else
Rx_start <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') or
((
(startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1')
) and (RxBusFifoRdAck = '1')
) then
Rx_DPM_ce <= '1';
else
Rx_DPM_ce <= '0';
end if;
-- RX buffer read/write enable
if (startReadDestAdrNib = '1') or -- 03-26-04
(not rdDestAddrNib_eq_0 = '1') or
(startReadDataNib = '1') then
Rx_DPM_wr_rd_n <= '1';
else
Rx_DPM_wr_rd_n <= '0';
end if;
-- RX buffer chip enable
if (idle = '1') then
checkingBroadcastAdr_i <= '0'; -- reset
-- 06-09-04 Use delayed data for compare
elsif (rdDestAddrNib_D_t_q = x"1" and
Emac_rx_rd_data_d1(0 to 3) = x"f") then
checkingBroadcastAdr_i <= '1'; -- set
else
checkingBroadcastAdr_i <= checkingBroadcastAdr_reg; -- stay the same
end if;
end process RX_FSMD_PROCESS;
-- write data to Receive DPRAM
Rx_DPM_wr_data <= BusFifoData;
----------------------------------------------------------------------------
-- MARAR_PROC
----------------------------------------------------------------------------
-- This process generate MAC RAM address to get mac addres to compare with
-- incoming frame destination address
----------------------------------------------------------------------------
MARAR_PROC : process (rdDestAddrNib_D_t, idle_D, startReadDestAdrNib_D)
begin
case rdDestAddrNib_D_t is
when "0001" => mac_addr_ram_addr_rd_D <= x"0";
when "0010" => mac_addr_ram_addr_rd_D <= x"1";
when "0011" => mac_addr_ram_addr_rd_D <= x"2";
when "0100" => mac_addr_ram_addr_rd_D <= x"3";
when "0101" => mac_addr_ram_addr_rd_D <= x"4";
when "0110" => mac_addr_ram_addr_rd_D <= x"5";
when "0111" => mac_addr_ram_addr_rd_D <= x"6";
when "1000" => mac_addr_ram_addr_rd_D <= x"7";
when "1001" => mac_addr_ram_addr_rd_D <= x"8";
when "1010" => mac_addr_ram_addr_rd_D <= x"9";
when "1011" => mac_addr_ram_addr_rd_D <= x"a";
when "1100" => mac_addr_ram_addr_rd_D <= x"b";
when others => mac_addr_ram_addr_rd_D <= x"0";
end case;
-- Reset the address in idle or start of new frame
if (idle_D or startReadDestAdrNib_D) = '1' then
mac_addr_ram_addr_rd_D <= x"0";
end if;
end process MARAR_PROC;
----------------------------------------------------------------------------
-- OUTPUT_REG
----------------------------------------------------------------------------
-- Registerit the mac_addr_ram_addr_rd
----------------------------------------------------------------------------
OUTPUT_REG:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Mac_addr_ram_addr_rd <= (others => '0');
else
Mac_addr_ram_addr_rd <= mac_addr_ram_addr_rd_D;
end if;
end if;
end process OUTPUT_REG;
----------------------------------------------------------------------------
-- Check if the incoming packet is broadcast packet
----------------------------------------------------------------------------
bcastAddrGood <= '1' when checkingBroadcastAdr_i = '1' and
Emac_rx_rd_data_d1(0 to 3) = x"F" else -- 03-26-04
'0';
----------------------------------------------------------------------------
-- Check if the incoming packet is unicast and address matches to core
-- MAC address
----------------------------------------------------------------------------
ucastAddrGood <= '1' when checkingBroadcastAdr_i = '0' and
(Emac_rx_rd_data_d1(0 to 3) = Mac_addr_ram_data)
else -- 03-26-04
'0';
-- Genarate Receive enable
Receive_enable <= not(crcCheck or rxDone or receiveRst);
----------------------------------------------------------------------------
-- PROCESS : PKT_LENGTH_COUNTER
----------------------------------------------------------------------------
-- This counter is used to check if the receive packet length is greater
-- minimum packet length (64 byte - 128 nibble)
----------------------------------------------------------------------------
PKT_LENGTH_COUNTER : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' or preamble_error_reg = '1' ) then
pkt_length_cnt <= 0;
elsif goto_readDestAdrNib1 = '1' then -- load the counter for
pkt_length_cnt <= 127; -- minimum packet length
elsif (rxCrcEn_i='1') then -- Enable Down Counter
if (pkt_length_cnt = 0) then
pkt_length_cnt <= 0;
else
pkt_length_cnt <= pkt_length_cnt - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- PROCESS : SFD_CHECK_REG
----------------------------------------------------------------------------
-- This process registers the preamble nibble to checl if atleast last 2
-- preamble nibbles are valid before the SFD nibble.
----------------------------------------------------------------------------
SFD_CHECK_REG : process(Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = '1' ) then
busFifoData_is_5_d1 <= '0';
busFifoData_is_5_d2 <= '0';
busFifoData_is_5_d3 <= '0';
elsif RxBusFifoRdAck = '1' then
busFifoData_is_5_d1 <= busFifoData_is_5;
busFifoData_is_5_d2 <= busFifoData_is_5_d1;
busFifoData_is_5_d3 <= busFifoData_is_5_d2;
end if;
end if;
end process;
preamble: FDR
port map (
Q => preamble_error_reg, --[out]
C => Clk, --[in]
D => preamble_error, --[in]
R => state_machine_rst --[in]
);
-- Premable valid
preamble_valid <= (busFifoData_is_5_d1) and
busFifoData_is_13;
-- Premable Error
preamble_error <= (not busFifoData_is_5 and
busFifoData_is_5_d1 and
not busFifoData_is_13) and waitForSfd2 ;
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAEchoExample/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_uartlite_v2_0/a3d1bdff/hdl/src/vhdl/axi_uartlite.vhd
|
6
|
17013
|
-------------------------------------------------------------------------------
-- axi_uartlite - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- -- ** (c) Copyright [2007] - [2011] Xilinx, Inc. All rights reserved.*
-- -- ** *
-- -- ** This file contains confidential and proprietary information *
-- -- ** of Xilinx, Inc. and is protected under U.S. and *
-- -- ** international copyright and other intellectual property *
-- -- ** laws. *
-- -- ** *
-- -- ** DISCLAIMER *
-- -- ** This disclaimer is not a license and does not grant any *
-- -- ** rights to the materials distributed herewith. Except as *
-- -- ** otherwise provided in a valid license issued to you by *
-- -- ** Xilinx, and to the maximum extent permitted by applicable *
-- -- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- -- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- -- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- -- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- -- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- -- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- -- ** including negligence, or under any other theory of *
-- -- ** liability) for any loss or damage of any kind or nature *
-- -- ** related to, arising under or in connection with these *
-- -- ** materials, including for any direct, or any indirect, *
-- -- ** special, incidental, or consequential loss or damage *
-- -- ** (including loss of data, profits, goodwill, or any type of *
-- -- ** loss or damage suffered as a result of any action brought *
-- -- ** by a third party) even if such damage or loss was *
-- -- ** reasonably foreseeable or Xilinx had been advised of the *
-- -- ** possibility of the same. *
-- -- ** *
-- -- ** CRITICAL APPLICATIONS *
-- -- ** Xilinx products are not designed or intended to be fail- *
-- -- ** safe, or for use in any application requiring fail-safe *
-- -- ** performance, such as life-support or safety devices or *
-- -- ** systems, Class III medical devices, nuclear facilities, *
-- -- ** applications related to the deployment of airbags, or any *
-- -- ** other applications that could lead to death, personal *
-- -- ** injury, or severe property or environmental damage *
-- -- ** (individually and collectively, "Critical *
-- -- ** Applications"). Customer assumes the sole risk and *
-- -- ** liability of any use of Xilinx products in Critical *
-- -- ** Applications, subject only to applicable laws and *
-- -- ** regulations governing limitations on product liability. *
-- -- ** *
-- -- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- -- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_uartlite.vhd
-- Version: v1.02.a
-- Description: AXI UART Lite Interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_lite_ipif_v3_0;
-- SLV64_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0.ipif_pkg.SLV64_ARRAY_TYPE;
-- INTEGER_ARRAY_TYPE refered from ipif_pkg
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
-- calc_num_ce comoponent refered from ipif_pkg
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0.axi_lite_ipif;
library axi_uartlite_v2_0;
-- uartlite_core refered from axi_uartlite_v2_0
use axi_uartlite_v2_0.uartlite_core;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics :
-------------------------------------------------------------------------------
-- System generics
-- C_FAMILY -- Xilinx FPGA Family
-- C_S_AXI_ACLK_FREQ_HZ -- System clock frequency driving UART lite
-- peripheral in Hz
-- AXI generics
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
--
-- UART Lite generics
-- C_BAUDRATE -- Baud rate of UART Lite in bits per second
-- C_DATA_BITS -- The number of data bits in the serial frame
-- C_USE_PARITY -- Determines whether parity is used or not
-- C_ODD_PARITY -- If parity is used determines whether parity
-- is even or odd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports :
-------------------------------------------------------------------------------
--System signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- Interrupt -- UART Interrupt
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
--UARTLite Interface Signals
-- rx -- Receive Data
-- tx -- Transmit Data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Section
-------------------------------------------------------------------------------
entity axi_uartlite is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
C_S_AXI_ACLK_FREQ_HZ : integer := 100_000_000;
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 4;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- UARTLite Parameters
C_BAUDRATE : integer := 9600;
C_DATA_BITS : integer range 5 to 8 := 8;
C_USE_PARITY : integer range 0 to 1 := 0;
C_ODD_PARITY : integer range 0 to 1 := 0
);
port
(
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
interrupt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector
(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(31 downto 0);
s_axi_wstrb : in std_logic_vector
(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- UARTLite Interface Signals
rx : in std_logic;
tx : out std_logic
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
-------------------------------------------------------------------------------
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
end entity axi_uartlite;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture RTL of axi_uartlite is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
--------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------
constant ZEROES : std_logic_vector(31 downto 0)
:= X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- UARTLite registers Base Address
ZEROES & X"00000000",
ZEROES & (X"00000000" or X"0000000F")
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 4
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"0000000F";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 0;
--------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0)
:= (others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
signal bus2ip_data : std_logic_vector
(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal bus2ip_cs : std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1 downto 0);
signal bus2ip_rdce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
signal bus2ip_wrce : std_logic_vector
(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
begin -- architecture IMP
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
bus2ip_reset <= not bus2ip_resetn;
--------------------------------------------------------------------------
-- ip2bus_data assignment - as core is using maximum upto 8 bits
--------------------------------------------------------------------------
ip2bus_data((C_S_AXI_DATA_WIDTH-1) downto 8) <= (others => '0');
--------------------------------------------------------------------------
-- Instansiating the UART core
--------------------------------------------------------------------------
UARTLITE_CORE_I : entity axi_uartlite_v2_0.uartlite_core
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_BAUDRATE => C_BAUDRATE,
C_DATA_BITS => C_DATA_BITS,
C_USE_PARITY => C_USE_PARITY,
C_ODD_PARITY => C_ODD_PARITY
)
port map
(
Clk => bus2ip_clk,
Reset => bus2ip_reset,
bus2ip_data => bus2ip_data(7 downto 0),
bus2ip_rdce => bus2ip_rdce(3 downto 0),
bus2ip_wrce => bus2ip_wrce(3 downto 0),
bus2ip_cs => bus2ip_cs(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error,
SIn_DBus => ip2bus_data(7 downto 0),
RX => rx,
TX => tx,
Interrupt => Interrupt
);
--------------------------------------------------------------------------
-- Instantiate AXI lite IPIF
--------------------------------------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => open,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => open,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
end architecture RTL;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lib_bmg_v1_0/1cb7cddc/hdl/src/vhdl/blk_mem_gen_wrapper.vhd
|
4
|
30610
|
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library blk_mem_gen_v8_2;
use blk_mem_gen_v8_2.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex7";
c_xdevicefamily : string := "virtex7";
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
-- directly passing C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until clka = '1';
-- wait until clka = '0';
-- Wait until clka = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
-- douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
-- doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr <= '0' ; -- : out std_logic;
-- sbiterr <= '0' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_2.blk_mem_gen_v8_2
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- New features in 2015.1
C_EN_DEEPSLEEP_PIN => 0 ,
C_EN_SHUTDOWN_PIN => 0 ,
C_USE_URAM => 0 ,
C_EN_RDADDRA_CHG => 0 ,
C_EN_RDADDRB_CHG => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
SHUTDOWN => '0' ,
DEEPSLEEP => '0' ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rmii_rx_agile.vhd
|
4
|
15461
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_rx_agile.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_rx_agile is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Rx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Rmii2Mac_rx_clk : out std_logic;
Rmii2Mac_crs : out std_logic;
Rmii2Mac_rx_dv : out std_logic;
Rmii2Mac_rx_er : out std_logic;
Rmii2Mac_rxd : out std_logic_vector(3 downto 0);
------------------ RMII <--> PHY --------------------------------
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0)
);
end rmii_rx_agile;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_rx_agile is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
component rx_fifo_loader
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0);
Rx_fifo_wr_en : out std_logic;
Rx_10 : out std_logic;
Rx_100 : out std_logic;
Rx_data : out std_logic_vector(7 downto 0);
Rx_error : out std_logic;
Rx_data_valid : out std_logic;
Rx_cary_sense : out std_logic;
Rx_end_of_packet : out std_logic
);
end component;
component rx_fifo
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_fifo_wr_en : in std_logic;
Rx_fifo_rd_en : in std_logic;
Rx_fifo_input : in std_logic_vector(15 downto 0);
Rx_fifo_mt_n : out std_logic;
Rx_fifo_full : out std_logic;
Rx_fifo_output : out std_logic_vector(15 downto 0)
);
end component;
component rx_fifo_disposer
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constant Declarations
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
signal rx_fifo_wr_en : std_logic;
signal rx_fifo_rd_en : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_mt_n : std_logic;
signal rx_10 : std_logic;
signal rx_100 : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_data_valid : std_logic;
signal rx_cary_sense : std_logic;
signal rx_error : std_logic;
signal rx_end_of_packet : std_logic;
signal rx_mii_eop : std_logic_vector(1 downto 0);
signal rx_mii_crs : std_logic_vector(1 downto 0);
signal rx_mii_er : std_logic_vector(1 downto 0);
signal rx_mii_dv : std_logic_vector(1 downto 0);
signal rx_mii_data : std_logic_vector(7 downto 0);
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
Rmii2Mac_crs <= rx_cary_sense;
------------------------------------------------------------------------------
-- Component Instantiations
------------------------------------------------------------------------------
I_RX_FIFO_LOADER : rx_fifo_loader
generic map(
C_RESET_ACTIVE => C_RESET_ACTIVE
)
port map (
Sync_rst_n => Sync_rst_n,
Ref_Clk => Ref_Clk,
Phy2Rmii_crs_dv => Phy2Rmii_crs_dv,
Phy2Rmii_rx_er => Phy2Rmii_rx_er,
Phy2Rmii_rxd => Phy2Rmii_rxd,
Rx_fifo_wr_en => rx_fifo_wr_en,
Rx_10 => rx_10,
Rx_100 => rx_100,
Rx_data => rx_data,
Rx_error => rx_error,
Rx_data_valid => rx_data_valid,
Rx_cary_sense => rx_cary_sense,
Rx_end_of_packet => rx_end_of_packet
);
I_RX_FIFO : rx_fifo
generic map(
C_RESET_ACTIVE => C_RESET_ACTIVE
)
port map (
Sync_rst_n => Sync_rst_n,
Ref_Clk => Ref_Clk,
Rx_fifo_wr_en => rx_fifo_wr_en,
Rx_fifo_rd_en => rx_fifo_rd_en,
Rx_fifo_input(15) => rx_end_of_packet,
Rx_fifo_input(14) => rx_cary_sense,
Rx_fifo_input(13) => rx_error,
Rx_fifo_input(12) => rx_data_valid,
Rx_fifo_input(11) => rx_data(7),
Rx_fifo_input(10) => rx_data(6),
Rx_fifo_input(9) => rx_data(5),
Rx_fifo_input(8) => rx_data(4),
Rx_fifo_input(7) => rx_end_of_packet,
Rx_fifo_input(6) => rx_cary_sense,
Rx_fifo_input(5) => rx_error,
Rx_fifo_input(4) => rx_data_valid,
Rx_fifo_input(3) => rx_data(3),
Rx_fifo_input(2) => rx_data(2),
Rx_fifo_input(1) => rx_data(1),
Rx_fifo_input(0) => rx_data(0),
Rx_fifo_mt_n => rx_fifo_mt_n,
Rx_fifo_full => rx_fifo_full,
Rx_fifo_output(15) => rx_mii_eop(1),
Rx_fifo_output(14) => rx_mii_crs(1),
Rx_fifo_output(13) => rx_mii_er(1),
Rx_fifo_output(12) => rx_mii_dv(1),
Rx_fifo_output(11) => rx_mii_data(7),
Rx_fifo_output(10) => rx_mii_data(6),
Rx_fifo_output(9) => rx_mii_data(5),
Rx_fifo_output(8) => rx_mii_data(4),
Rx_fifo_output(7) => rx_mii_eop(0),
Rx_fifo_output(6) => rx_mii_crs(0),
Rx_fifo_output(5) => rx_mii_er(0),
Rx_fifo_output(4) => rx_mii_dv(0),
Rx_fifo_output(3) => rx_mii_data(3),
Rx_fifo_output(2) => rx_mii_data(2),
Rx_fifo_output(1) => rx_mii_data(1),
Rx_fifo_output(0) => rx_mii_data(0)
);
I_RX_FIFO_DISPOSER : rx_fifo_disposer
generic map(
C_RESET_ACTIVE => C_RESET_ACTIVE
)
port map (
Sync_rst_n => Sync_rst_n,
Ref_Clk => Ref_Clk,
Rx_10 => rx_10,
Rx_100 => rx_100,
Rmii_rx_eop => rx_mii_eop,
Rmii_rx_crs => rx_mii_crs,
Rmii_rx_er => rx_mii_er,
Rmii_rx_dv => rx_mii_dv,
Rmii_rx_data => rx_mii_data,
Rx_fifo_mt_n => rx_fifo_mt_n,
Rx_fifo_rd_en => rx_fifo_rd_en,
-- Rmii2mac_crs => Rmii2mac_crs,
Rmii2mac_crs => open,
Rmii2mac_rx_clk => Rmii2mac_rx_clk,
Rmii2mac_rx_er => Rmii2mac_rx_er,
Rmii2mac_rx_dv => Rmii2mac_rx_dv,
Rmii2mac_rxd => Rmii2mac_rxd
);
end simulation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rmii_rx_agile.vhd
|
4
|
15461
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_rx_agile.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't fit
-- -- align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or destination
-- Port_name2 -- description of port
--
------------------------------------------------------------------------------
entity rmii_rx_agile is
generic (
C_RESET_ACTIVE : std_logic
);
port (
Rx_speed_100 : in std_logic;
------------------ System Signals -------------------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII --------------------------------
Rmii2Mac_rx_clk : out std_logic;
Rmii2Mac_crs : out std_logic;
Rmii2Mac_rx_dv : out std_logic;
Rmii2Mac_rx_er : out std_logic;
Rmii2Mac_rxd : out std_logic_vector(3 downto 0);
------------------ RMII <--> PHY --------------------------------
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0)
);
end rmii_rx_agile;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_rx_agile is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
component rx_fifo_loader
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0);
Rx_fifo_wr_en : out std_logic;
Rx_10 : out std_logic;
Rx_100 : out std_logic;
Rx_data : out std_logic_vector(7 downto 0);
Rx_error : out std_logic;
Rx_data_valid : out std_logic;
Rx_cary_sense : out std_logic;
Rx_end_of_packet : out std_logic
);
end component;
component rx_fifo
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_fifo_wr_en : in std_logic;
Rx_fifo_rd_en : in std_logic;
Rx_fifo_input : in std_logic_vector(15 downto 0);
Rx_fifo_mt_n : out std_logic;
Rx_fifo_full : out std_logic;
Rx_fifo_output : out std_logic_vector(15 downto 0)
);
end component;
component rx_fifo_disposer
generic (
C_RESET_ACTIVE : std_logic
);
port (
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
Rx_10 : in std_logic;
Rx_100 : in std_logic;
Rmii_rx_eop : in std_logic_vector(1 downto 0);
Rmii_rx_crs : in std_logic_vector(1 downto 0);
Rmii_rx_er : in std_logic_vector(1 downto 0);
Rmii_rx_dv : in std_logic_vector(1 downto 0);
Rmii_rx_data : in std_logic_vector(7 downto 0);
Rx_fifo_mt_n : in std_logic;
Rx_fifo_rd_en : out std_logic;
Rmii2mac_crs : out std_logic;
Rmii2mac_rx_clk : out std_logic;
Rmii2mac_rx_er : out std_logic;
Rmii2mac_rx_dv : out std_logic;
Rmii2mac_rxd : out std_logic_vector(3 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should be
-- collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a register.
-- If no constants are required, simply state this in a comment below the file
-- section separation comments.
------------------------------------------------------------------------------
-- No Constant Declarations
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
signal rx_fifo_wr_en : std_logic;
signal rx_fifo_rd_en : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_mt_n : std_logic;
signal rx_10 : std_logic;
signal rx_100 : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_data_valid : std_logic;
signal rx_cary_sense : std_logic;
signal rx_error : std_logic;
signal rx_end_of_packet : std_logic;
signal rx_mii_eop : std_logic_vector(1 downto 0);
signal rx_mii_crs : std_logic_vector(1 downto 0);
signal rx_mii_er : std_logic_vector(1 downto 0);
signal rx_mii_dv : std_logic_vector(1 downto 0);
signal rx_mii_data : std_logic_vector(7 downto 0);
begin
------------------------------------------------------------------------------
-- Concurrent Signal Assignments
------------------------------------------------------------------------------
Rmii2Mac_crs <= rx_cary_sense;
------------------------------------------------------------------------------
-- Component Instantiations
------------------------------------------------------------------------------
I_RX_FIFO_LOADER : rx_fifo_loader
generic map(
C_RESET_ACTIVE => C_RESET_ACTIVE
)
port map (
Sync_rst_n => Sync_rst_n,
Ref_Clk => Ref_Clk,
Phy2Rmii_crs_dv => Phy2Rmii_crs_dv,
Phy2Rmii_rx_er => Phy2Rmii_rx_er,
Phy2Rmii_rxd => Phy2Rmii_rxd,
Rx_fifo_wr_en => rx_fifo_wr_en,
Rx_10 => rx_10,
Rx_100 => rx_100,
Rx_data => rx_data,
Rx_error => rx_error,
Rx_data_valid => rx_data_valid,
Rx_cary_sense => rx_cary_sense,
Rx_end_of_packet => rx_end_of_packet
);
I_RX_FIFO : rx_fifo
generic map(
C_RESET_ACTIVE => C_RESET_ACTIVE
)
port map (
Sync_rst_n => Sync_rst_n,
Ref_Clk => Ref_Clk,
Rx_fifo_wr_en => rx_fifo_wr_en,
Rx_fifo_rd_en => rx_fifo_rd_en,
Rx_fifo_input(15) => rx_end_of_packet,
Rx_fifo_input(14) => rx_cary_sense,
Rx_fifo_input(13) => rx_error,
Rx_fifo_input(12) => rx_data_valid,
Rx_fifo_input(11) => rx_data(7),
Rx_fifo_input(10) => rx_data(6),
Rx_fifo_input(9) => rx_data(5),
Rx_fifo_input(8) => rx_data(4),
Rx_fifo_input(7) => rx_end_of_packet,
Rx_fifo_input(6) => rx_cary_sense,
Rx_fifo_input(5) => rx_error,
Rx_fifo_input(4) => rx_data_valid,
Rx_fifo_input(3) => rx_data(3),
Rx_fifo_input(2) => rx_data(2),
Rx_fifo_input(1) => rx_data(1),
Rx_fifo_input(0) => rx_data(0),
Rx_fifo_mt_n => rx_fifo_mt_n,
Rx_fifo_full => rx_fifo_full,
Rx_fifo_output(15) => rx_mii_eop(1),
Rx_fifo_output(14) => rx_mii_crs(1),
Rx_fifo_output(13) => rx_mii_er(1),
Rx_fifo_output(12) => rx_mii_dv(1),
Rx_fifo_output(11) => rx_mii_data(7),
Rx_fifo_output(10) => rx_mii_data(6),
Rx_fifo_output(9) => rx_mii_data(5),
Rx_fifo_output(8) => rx_mii_data(4),
Rx_fifo_output(7) => rx_mii_eop(0),
Rx_fifo_output(6) => rx_mii_crs(0),
Rx_fifo_output(5) => rx_mii_er(0),
Rx_fifo_output(4) => rx_mii_dv(0),
Rx_fifo_output(3) => rx_mii_data(3),
Rx_fifo_output(2) => rx_mii_data(2),
Rx_fifo_output(1) => rx_mii_data(1),
Rx_fifo_output(0) => rx_mii_data(0)
);
I_RX_FIFO_DISPOSER : rx_fifo_disposer
generic map(
C_RESET_ACTIVE => C_RESET_ACTIVE
)
port map (
Sync_rst_n => Sync_rst_n,
Ref_Clk => Ref_Clk,
Rx_10 => rx_10,
Rx_100 => rx_100,
Rmii_rx_eop => rx_mii_eop,
Rmii_rx_crs => rx_mii_crs,
Rmii_rx_er => rx_mii_er,
Rmii_rx_dv => rx_mii_dv,
Rmii_rx_data => rx_mii_data,
Rx_fifo_mt_n => rx_fifo_mt_n,
Rx_fifo_rd_en => rx_fifo_rd_en,
-- Rmii2mac_crs => Rmii2mac_crs,
Rmii2mac_crs => open,
Rmii2mac_rx_clk => Rmii2mac_rx_clk,
Rmii2mac_rx_er => Rmii2mac_rx_er,
Rmii2mac_rx_dv => Rmii2mac_rx_dv,
Rmii2mac_rxd => Rmii2mac_rxd
);
end simulation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/MicroblazeTemplate/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/lib_cdc_v1_0/ea79928f/hdl/src/vhdl/cdc_sync.vhd
|
32
|
49938
|
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
signal srst_d1 : std_logic := '0';
signal srst_d2 : std_logic := '0';
signal srst_d3 : std_logic := '0';
signal srst_d4 : std_logic := '0';
signal srst_d5 : std_logic := '0';
signal srst_d6 : std_logic := '0';
signal srst_d7 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
s_rst_d1 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d1,
C => scndry_aclk,
D => '1',
R => scndry_reset2
);
s_rst_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d2,
C => scndry_aclk,
D => srst_d1,
R => scndry_reset2
);
s_rst_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d3,
C => scndry_aclk,
D => srst_d2,
R => scndry_reset2
);
s_rst_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d4,
C => scndry_aclk,
D => srst_d3,
R => scndry_reset2
);
s_rst_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d5,
C => scndry_aclk,
D => srst_d4,
R => scndry_reset2
);
s_rst_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d6,
C => scndry_aclk,
D => srst_d5,
R => scndry_reset2
);
s_rst_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d7,
C => scndry_aclk,
D => srst_d6,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3);
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4);
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5);
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6);
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7);
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/mii_to_rmii_v2_0/8a85492a/hdl/src/vhdl/rmii_rx_fixed.vhd
|
4
|
44001
|
-----------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-----------------------------------------------------------------------
-- Filename: rmii_rx_fixed.vhd
--
-- Version: v1.01.a
-- Description: Top level of RMII(reduced media independent interface)
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------
-- Include comments indicating reasons why packages are being used
-- Don't use ".all" - indicate which parts of the packages are used in the
-- "use" statement
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- include library containing the entities you're configuring
------------------------------------------------------------------------------
library mii_to_rmii_v2_0;
use mii_to_rmii_v2_0.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_GEN1 -- description of generic, if description doesn't
-- -- fit align with first part of description
-- C_GEN2 -- description of generic
--
-- Definition of Ports:
-- Port_name1 -- description of port, indicate source or
-- Port_name2 -- destination description of port
--
------------------------------------------------------------------------------
entity rmii_rx_fixed is
generic (
C_RESET_ACTIVE : std_logic := '0';
C_SPEED_100 : std_logic := '1'
);
port (
Rx_speed_100 : in std_logic;
------------------ System Signals ---------------------
Sync_rst_n : in std_logic;
Ref_Clk : in std_logic;
------------------ MII <--> RMII ----------------------
Rmii2Mac_rx_clk : out std_logic;
Rmii2Mac_crs : out std_logic;
Rmii2Mac_rx_dv : out std_logic;
Rmii2Mac_rx_er : out std_logic;
Rmii2Mac_rxd : out std_logic_vector(3 downto 0);
------------------ RMII <--> PHY ----------------------
Phy2Rmii_crs_dv : in std_logic;
Phy2Rmii_rx_er : in std_logic;
Phy2Rmii_rxd : in std_logic_vector(1 downto 0)
);
end rmii_rx_fixed;
------------------------------------------------------------------------------
-- Configurations
------------------------------------------------------------------------------
-- No Configurations
------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------
architecture simulation of rmii_rx_fixed is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of simulation : architecture is "yes";
------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------------
-- Note that global constants and parameters (such as RESET_ACTIVE, default
-- values for address and data --widths, initialization values, etc.) should
-- be collected into a global package or include file.
-- Constants are all uppercase.
-- Constants or parameters should be used for all numeric values except for
-- single "0" or "1" values.
-- Constants should also be used when denoting a bit location within a
-- register. If no constants are required, simply state this in a comment
-- below the file section separation comments.
------------------------------------------------------------------------------
-- No Constants
------------------------------------------------------------------------------
-- Signal and Type Declarations
------------------------------------------------------------------------------
-- No Signal or Types
------------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------------
-- No Components
begin
------------------------------------------------------------------------------
--
-- Conditional Generate for FIXED speed throughput of 10 Mb/s
--
------------------------------------------------------------------------------
RX_10_MBPS : if (C_SPEED_100 = '0') generate
--------------------------------------------------------------------------
-- Signal and Type Declarations
--------------------------------------------------------------------------
type F_LDR_TYPE is (
IDLE,
RXD_DIB0_0,
RXD_DIB0_1,
RXD_DIB0_2,
RXD_DIB0_3,
RXD_DIB0_4,
RXD_DIB0_5,
RXD_DIB0_6,
RXD_DIB0_7,
RXD_DIB0_8,
RXD_DIB0_9,
RXD_DIB1_0,
RXD_DIB1_1,
RXD_DIB1_2,
RXD_DIB1_3,
RXD_DIB1_4,
RXD_DIB1_5,
RXD_DIB1_6,
RXD_DIB1_7,
RXD_DIB1_8,
RXD_DIB1_9
);
type F_UNLDR_TYPE is (
RX_CLK_L0,
RX_CLK_L1,
RX_CLK_L2,
RX_CLK_L3,
RX_CLK_L4,
RX_CLK_L5,
RX_CLK_L6,
RX_CLK_L7,
RX_CLK_L8,
RX_CLK_L9,
RX_CLK_H0,
RX_CLK_H1,
RX_CLK_H2,
RX_CLK_H3,
RX_CLK_H4,
RX_CLK_H5,
RX_CLK_H6,
RX_CLK_H7,
RX_CLK_H8,
RX_CLK_H9
);
signal fifo_ldr_cs : F_LDR_TYPE;
signal fifo_ldr_ns : F_LDR_TYPE;
signal fifo_unldr_cs : F_UNLDR_TYPE;
signal fifo_unldr_ns : F_UNLDR_TYPE;
signal rmii2Mac_crs_i : std_logic;
signal rmii2Mac_rx_er_i : std_logic;
signal rx_begin_packet : std_logic_vector(1 downto 0);
signal rx_beg_of_packet : std_logic;
signal rx_end_packet : std_logic_vector(1 downto 0);
signal rx_end_of_packet : std_logic;
signal phy2Rmii_crs_dv_sr : std_logic_vector(22 downto 0);
signal rx_out_mux_sel : std_logic;
signal rx_out_reg_en : std_logic;
signal phy2Rmii_rxd_d1 : std_logic_vector(3 downto 0);
signal fIFO_Reset : std_logic;
signal fIFO_Write : std_logic;
signal fIFO_Data_In : std_logic_vector(4 downto 0);
signal fIFO_Read : std_logic;
signal fIFO_Data_Out : std_logic_vector(4 downto 0);
signal fIFO_Data_Exists : std_logic;
signal fifo_din_dv : std_logic;
signal rxd_smpl_dibit : std_logic;
begin
--------------------------------------------------------------------------
-- Component Instaniations
--------------------------------------------------------------------------
SRL_FIFO_I_1 : entity mii_to_rmii_v2_0.srl_fifo(IMP)
generic map (
C_DATA_BITS => 5,
C_DEPTH => 16
)
port map (
Clk => Ref_Clk, -- in
Reset => fIFO_Reset, -- in
FIFO_Write => fIFO_Write, -- in
Data_In => fIFO_Data_In, -- in
FIFO_Read => fIFO_Read, -- out
Data_Out => fIFO_Data_Out, -- out
FIFO_Full => open, -- out
Data_Exists => fIFO_Data_Exists, -- out
Addr => open
);
--------------------------------------------------------------------------
-- FIFO_RESET_PROCESS
--------------------------------------------------------------------------
FIFO_RESET_PROCESS : process ( sync_rst_n )
begin
if (sync_rst_n = C_RESET_ACTIVE) then
fIFO_Reset <= '1';
else
fIFO_Reset <= '0';
end if;
end process;
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
Rmii2Mac_crs <= rmii2Mac_crs_i;
rx_beg_of_packet <= rx_begin_packet(0) and not rx_begin_packet(1);
rx_end_of_packet <= rx_end_packet(0) and not rx_end_packet(1);
fIFO_Data_In <= fifo_din_dv & phy2Rmii_rxd_d1;
--------------------------------------------------------------------------
-- RX_CARRY_SENSE_PROCESS
--------------------------------------------------------------------------
RX_CARRY_SENSE_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
rmii2Mac_crs_i <= '0';
else
rmii2Mac_crs_i <= ( phy2Rmii_crs_dv_sr(1) and rmii2Mac_crs_i ) or
(phy2Rmii_crs_dv_sr(1) and not
phy2Rmii_crs_dv_sr(21) );
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RMII_CRS_DV_PIPELINE_PROCESS
--------------------------------------------------------------------------
RMII_CRS_DV_PIPELINE_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
phy2Rmii_crs_dv_sr <= (others => '0');
else
phy2Rmii_crs_dv_sr <= phy2Rmii_crs_dv_sr(21 downto 0) &
Phy2Rmii_crs_dv;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- FIFO_DIN_DV_PROCESS
--------------------------------------------------------------------------
FIFO_DIN_DV_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if ( Sync_rst_n = '0' ) then
fifo_din_dv <= '0';
elsif ( rx_beg_of_packet = '1' ) then
fifo_din_dv <= '1';
elsif ( rx_end_of_packet = '1' ) then
fifo_din_dv <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_IN_REG_PROCESS
--------------------------------------------------------------------------
RX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
phy2Rmii_rxd_d1 <= (others => '0');
elsif (rxd_smpl_dibit = '1') then
phy2Rmii_rxd_d1(1 downto 0) <= phy2Rmii_rxd_d1(3 downto 2);
phy2Rmii_rxd_d1(3 downto 2) <= Phy2Rmii_rxd;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_BEGIN_OF_PACKET_PROCESS
--------------------------------------------------------------------------
RX_BEGIN_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (( Sync_rst_n = '0' ) or ( rx_end_of_packet = '1' )) then
rx_begin_packet <= "00";
else
rx_begin_packet(1) <= rx_begin_packet(0);
if ( ( Phy2Rmii_crs_dv = '1' ) and
( Phy2Rmii_rxd = "01" ) and
( rx_beg_of_packet = '0' ) ) then
rx_begin_packet(0) <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_END_OF_PACKET_PROCESS
--------------------------------------------------------------------------
RX_END_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (( Sync_rst_n = '0' ) or ( rx_beg_of_packet = '1' )) then
rx_end_packet <= "00";
else
rx_end_packet(1) <= rx_end_packet(0);
if ( ( phy2Rmii_crs_dv_sr(9) = '0' ) and
( phy2Rmii_crs_dv = '0' ) and
( rx_end_of_packet = '0' ) ) then
rx_end_packet(0) <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_ERROR_PROCESS
--------------------------------------------------------------------------
RX_ERROR_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
rmii2Mac_rx_er_i <= '0';
else
rmii2Mac_rx_er_i <= Phy2Rmii_rx_er;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_OUT_REG_PROCESS
--------------------------------------------------------------------------
RX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Mac_rx_er <= '0';
Rmii2Mac_rx_dv <= '0';
Rmii2Mac_rxd <= (others => '0');
elsif (rx_out_reg_en = '1') then
if (rx_out_mux_sel = '1') then
Rmii2Mac_rx_er <= rmii2Mac_rx_er_i;
Rmii2Mac_rx_dv <= fIFO_Data_Out(4);
Rmii2Mac_rxd <= fIFO_Data_Out(3 downto 0);
else
Rmii2Mac_rx_er <= rmii2Mac_rx_er_i;
Rmii2Mac_rx_dv <= '0';
Rmii2Mac_rxd <= (others => '0');
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- STATE_MACHS_SYNC_PROCESS
--------------------------------------------------------------------------
STATE_MACHS_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
fifo_ldr_cs <= IDLE;
fifo_unldr_cs <= RX_CLK_L0;
else
fifo_ldr_cs <= fifo_ldr_ns;
fifo_unldr_cs <= fifo_unldr_ns;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- FIFO_LOADER_NEXT_STATE_PROCESS
--------------------------------------------------------------------------
FIFO_LOADER_NEXT_STATE_PROCESS : process (
fifo_ldr_cs,
fifo_din_dv
)
begin
case fifo_ldr_cs is
when IDLE =>
if (fifo_din_dv = '1') then
fifo_ldr_ns <= RXD_DIB0_0;
else
fifo_ldr_ns <= IDLE;
end if;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_0 =>
fifo_ldr_ns <= RXD_DIB0_1;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_1 =>
fifo_ldr_ns <= RXD_DIB0_2;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_2 =>
fifo_ldr_ns <= RXD_DIB0_3;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_3 =>
fifo_ldr_ns <= RXD_DIB0_4;
rxd_smpl_dibit <= '1';
fIFO_Write <= '0';
when RXD_DIB0_4 =>
fifo_ldr_ns <= RXD_DIB0_5;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_5 =>
fifo_ldr_ns <= RXD_DIB0_6;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_6 =>
fifo_ldr_ns <= RXD_DIB0_7;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_7 =>
fifo_ldr_ns <= RXD_DIB0_8;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_8 =>
fifo_ldr_ns <= RXD_DIB0_9;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB0_9 =>
fifo_ldr_ns <= RXD_DIB1_0;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_0 =>
fifo_ldr_ns <= RXD_DIB1_1;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_1 =>
fifo_ldr_ns <= RXD_DIB1_2;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_2 =>
fifo_ldr_ns <= RXD_DIB1_3;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_3 =>
fifo_ldr_ns <= RXD_DIB1_4;
rxd_smpl_dibit <= '1';
fIFO_Write <= '0';
when RXD_DIB1_4 =>
fifo_ldr_ns <= RXD_DIB1_5;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_5 =>
fifo_ldr_ns <= RXD_DIB1_6;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_6 =>
fifo_ldr_ns <= RXD_DIB1_7;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_7 =>
fifo_ldr_ns <= RXD_DIB1_8;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_8 =>
fifo_ldr_ns <= RXD_DIB1_9;
rxd_smpl_dibit <= '0';
fIFO_Write <= '0';
when RXD_DIB1_9 =>
if (fifo_din_dv = '1') then
fifo_ldr_ns <= RXD_DIB0_0;
else
fifo_ldr_ns <= IDLE;
end if;
rxd_smpl_dibit <= '0';
fIFO_Write <= '1';
end case;
end process;
--------------------------------------------------------------------------
-- FIFO_UNLOADER_NEXT_STATE_PROCESS
--------------------------------------------------------------------------
FIFO_UNLOADER_NEXT_STATE_PROCESS : process (
fifo_unldr_cs,
fIFO_Data_Exists
)
begin
case fifo_unldr_cs is
when RX_CLK_L0 =>
fifo_unldr_ns <= RX_CLK_L1;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L1 =>
fifo_unldr_ns <= RX_CLK_L2;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L2 =>
fifo_unldr_ns <= RX_CLK_L3;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L3 =>
fifo_unldr_ns <= RX_CLK_L4;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L4 =>
fifo_unldr_ns <= RX_CLK_L5;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L5 =>
fifo_unldr_ns <= RX_CLK_L6;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L6 =>
fifo_unldr_ns <= RX_CLK_L7;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L7 =>
fifo_unldr_ns <= RX_CLK_L8;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L8 =>
fifo_unldr_ns <= RX_CLK_L9;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_L9 =>
fifo_unldr_ns <= RX_CLK_H0;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H0 =>
fifo_unldr_ns <= RX_CLK_H1;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H1 =>
fifo_unldr_ns <= RX_CLK_H2;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H2 =>
fifo_unldr_ns <= RX_CLK_H3;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H3 =>
fifo_unldr_ns <= RX_CLK_H4;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H4 =>
fifo_unldr_ns <= RX_CLK_H5;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H5 =>
fifo_unldr_ns <= RX_CLK_H6;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H6 =>
fifo_unldr_ns <= RX_CLK_H7;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H7 =>
fifo_unldr_ns <= RX_CLK_H8;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= fIFO_Data_Exists;
rx_out_mux_sel <= '0';
when RX_CLK_H8 =>
fifo_unldr_ns <= RX_CLK_H9;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX_CLK_H9 =>
fifo_unldr_ns <= RX_CLK_L0;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '1';
fIFO_Read <= '0';
rx_out_mux_sel <= '1';
end case;
end process;
end generate;
------------------------------------------------------------------------------
--
-- Conditional Generate for FIXED speed throughput of 100 Mb/s
--
------------------------------------------------------------------------------
RX_100_MBPS : if (C_SPEED_100 = '1') generate
--------------------------------------------------------------------------
-- Signal and Type Declarations
--------------------------------------------------------------------------
type F_LDR_TYPE is (
IDLE_NO_WR,
RX_NO_WR,
RX_WR
);
signal fifo_ldr_cs : F_LDR_TYPE;
signal fifo_ldr_ns : F_LDR_TYPE;
type FLSHR_TYPE is (
FLSHR_IDLE_L,
FLSHR_IDLE_H,
RX100_CLK_L,
RX100_CLK_H
);
signal fifo_flshr_cs : FLSHR_TYPE;
signal fifo_flshr_ns : FLSHR_TYPE;
signal rmii2Mac_crs_i : std_logic;
signal rmii2Mac_rx_er_d3 : std_logic;
signal rmii2Mac_rx_er_d2 : std_logic;
signal rmii2Mac_rx_er_d1 : std_logic;
signal rx_begin_packet : std_logic_vector(1 downto 0);
signal rx_beg_of_packet : std_logic;
signal rx_end_packet : std_logic_vector(1 downto 0);
signal rx_end_of_packet : std_logic;
signal phy2Rmii_crs_dv_d4 : std_logic;
signal phy2Rmii_crs_dv_d3 : std_logic;
signal phy2Rmii_crs_dv_d2 : std_logic;
signal phy2Rmii_crs_dv_d1 : std_logic;
signal rx_out_mux_sel : std_logic;
signal rx_out_reg_en : std_logic;
signal phy2Rmii_rxd_d3 : std_logic_vector(3 downto 0);
signal phy2Rmii_rxd_d2 : std_logic_vector(3 downto 0);
signal phy2Rmii_rxd_d1 : std_logic_vector(3 downto 0);
signal fIFO_Reset : std_logic;
signal fIFO_Write : std_logic;
signal fIFO_Data_In : std_logic_vector(4 downto 0);
signal fIFO_Read : std_logic;
signal fIFO_Data_Out : std_logic_vector(4 downto 0);
signal fIFO_Full : std_logic;
signal fIFO_Data_Exists : std_logic;
signal fifo_din_dv : std_logic;
--CR#618005
attribute shreg_extract : string;
attribute shreg_extract of phy2Rmii_crs_dv_d1 : signal is "no";
attribute shreg_extract of phy2Rmii_rxd_d1 : signal is "no";
attribute shreg_extract of rmii2Mac_rx_er_d1 : signal is "no";
--------------------------------------------------------------------------
-- Component Declarations
--------------------------------------------------------------------------
component srl_fifo
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end component;
begin
--------------------------------------------------------------------------
-- Component Instaniations
--------------------------------------------------------------------------
I_SRL_FIFO : srl_fifo
generic map (
C_DATA_BITS => 5,
C_DEPTH => 16
)
port map (
Clk => Ref_Clk,
Reset => fIFO_Reset,
FIFO_Write => fIFO_Write,
Data_In => fIFO_Data_In,
FIFO_Read => fIFO_Read,
Data_Out => fIFO_Data_Out,
FIFO_Full => fIFO_Full,
Data_Exists => fIFO_Data_Exists,
Addr => open
);
--------------------------------------------------------------------------
-- Concurrent Signal Assignments
--------------------------------------------------------------------------
Rmii2Mac_crs <= rmii2Mac_crs_i;
rx_beg_of_packet <= rx_begin_packet(0) and not rx_begin_packet(1);
rx_end_of_packet <= rx_end_packet(0) and not rx_end_packet(1);
fIFO_Reset <= not sync_rst_n;
fIFO_Data_In <= fifo_din_dv & phy2Rmii_rxd_d3;
--------------------------------------------------------------------------
-- RX_CARRY_SENSE_PROCESS
--------------------------------------------------------------------------
RX_CARRY_SENSE_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
rmii2Mac_crs_i <= '0';
else
rmii2Mac_crs_i <= ( Phy2Rmii_crs_dv_d2 and rmii2Mac_crs_i ) or
( Phy2Rmii_crs_dv_d2 and not phy2Rmii_crs_dv_d4 );
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RMII_CRS_DV_PIPELINE_PROCESS
--------------------------------------------------------------------------
RMII_CRS_DV_PIPELINE_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
phy2Rmii_crs_dv_d4 <= '0';
phy2Rmii_crs_dv_d3 <= '0';
phy2Rmii_crs_dv_d2 <= '0';
phy2Rmii_crs_dv_d1 <= '0';
else
phy2Rmii_crs_dv_d4 <= phy2Rmii_crs_dv_d3;
phy2Rmii_crs_dv_d3 <= phy2Rmii_crs_dv_d2;
phy2Rmii_crs_dv_d2 <= phy2Rmii_crs_dv_d1;
phy2Rmii_crs_dv_d1 <= Phy2Rmii_crs_dv;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- FIFO_DIN_DV_PROCESS
--------------------------------------------------------------------------
FIFO_DIN_DV_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if ( Sync_rst_n = '0' ) then
fifo_din_dv <= '0';
elsif ( rx_beg_of_packet = '1') then
fifo_din_dv <= '1';
elsif ( ( Phy2Rmii_crs_dv_d2 = '0' ) and
( phy2Rmii_crs_dv_d3 = '0' ) ) then
fifo_din_dv <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_IN_REG_PROCESS
--------------------------------------------------------------------------
RX_IN_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
phy2Rmii_rxd_d3 <= (others => '0');
phy2Rmii_rxd_d2 <= (others => '0');
phy2Rmii_rxd_d1 <= (others => '0');
else
phy2Rmii_rxd_d3 <= phy2Rmii_rxd_d2;
phy2Rmii_rxd_d2 <= phy2Rmii_rxd_d1;
phy2Rmii_rxd_d1(1 downto 0) <= phy2Rmii_rxd_d1(3 downto 2);
phy2Rmii_rxd_d1(3 downto 2) <= Phy2Rmii_rxd;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_BEGIN_OF_PACKET_PROCESS
--------------------------------------------------------------------------
RX_BEGIN_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (( Sync_rst_n = '0' ) or ( rx_end_of_packet = '1' )) then
rx_begin_packet <= "00";
else
rx_begin_packet(1) <= rx_begin_packet(0);
if ( ( Phy2Rmii_crs_dv_d2 = '1' ) and
( Phy2Rmii_rxd_d2(3 downto 2) = "01" ) and
( rx_beg_of_packet = '0' ) ) then
rx_begin_packet(0) <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_END_OF_PACKET_PROCESS
--------------------------------------------------------------------------
RX_END_OF_PACKET_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (( Sync_rst_n = '0' ) or ( rx_beg_of_packet = '1' )) then
rx_end_packet <= "00";
else
rx_end_packet(1) <= rx_end_packet(0);
if ( ( Phy2Rmii_crs_dv_d2 = '0' ) and
( phy2Rmii_crs_dv_d3 = '0' ) and
( rx_end_of_packet = '0' ) ) then
rx_end_packet(0) <= '1';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_ERROR_PROCESS
--------------------------------------------------------------------------
RX_ERROR_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (Sync_rst_n = '0') then
rmii2Mac_rx_er_d3 <= '0';
rmii2Mac_rx_er_d2 <= '0';
rmii2Mac_rx_er_d1 <= '0';
else
rmii2Mac_rx_er_d3 <= rmii2Mac_rx_er_d2;
rmii2Mac_rx_er_d2 <= rmii2Mac_rx_er_d1;
rmii2Mac_rx_er_d1 <= Phy2Rmii_rx_er;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- RX_OUT_REG_PROCESS
--------------------------------------------------------------------------
RX_OUT_REG_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
Rmii2Mac_rx_er <= '0';
Rmii2Mac_rx_dv <= '0';
Rmii2Mac_rxd <= (others => '0');
elsif (rx_out_reg_en = '1') then
if ( rx_out_mux_sel = '1' ) then
Rmii2Mac_rx_er <= rmii2Mac_rx_er_d3;
Rmii2Mac_rx_dv <= '1';
Rmii2Mac_rxd <= fIFO_Data_Out(3 downto 0);
else
Rmii2Mac_rx_er <= '0';
Rmii2Mac_rx_dv <= '0';
Rmii2Mac_rxd <= (others => '0');
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- STATE_MACHS_SYNC_PROCESS
--------------------------------------------------------------------------
STATE_MACHS_SYNC_PROCESS : process ( Ref_Clk )
begin
if (Ref_Clk'event and Ref_Clk = '1') then
if (sync_rst_n = C_RESET_ACTIVE) then
fifo_ldr_cs <= IDLE_NO_WR;
fifo_flshr_cs <= FLSHR_IDLE_L;
else
fifo_ldr_cs <= fifo_ldr_ns;
fifo_flshr_cs <= fifo_flshr_ns;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- FIFO_LOADER_NEXT_STATE_PROCESS
--------------------------------------------------------------------------
FIFO_LOADER_NEXT_STATE_PROCESS : process (
fifo_ldr_cs,
rx_beg_of_packet,
rx_end_of_packet
)
begin
case fifo_ldr_cs is
when IDLE_NO_WR =>
if (rx_beg_of_packet = '1') then
fifo_ldr_ns <= RX_WR;
else
fifo_ldr_ns <= IDLE_NO_WR;
end if;
fIFO_Write <= '0';
when RX_NO_WR =>
if (rx_end_of_packet = '1') then
fifo_ldr_ns <= IDLE_NO_WR;
else
fifo_ldr_ns <= RX_WR;
end if;
fIFO_Write <= '0';
when RX_WR =>
if (rx_end_of_packet = '1') then
fifo_ldr_ns <= IDLE_NO_WR;
fIFO_Write <= '0';
else
fifo_ldr_ns <= RX_NO_WR;
fIFO_Write <= '1';
end if;
end case;
end process;
--------------------------------------------------------------------------
-- FIFO_FLUSHER_NEXT_STATE_PROCESS
--------------------------------------------------------------------------
FIFO_FLUSHER_NEXT_STATE_PROCESS : process (
fifo_flshr_cs,
fIFO_Data_Exists
)
begin
case fifo_flshr_cs is
when FLSHR_IDLE_L =>
if (fIFO_Data_Exists = '1') then
fifo_flshr_ns <= RX100_CLK_H;
else
fifo_flshr_ns <= FLSHR_IDLE_H;
end if;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when FLSHR_IDLE_H =>
if (fIFO_Data_Exists = '1') then
fifo_flshr_ns <= RX100_CLK_L;
else
fifo_flshr_ns <= FLSHR_IDLE_L;
end if;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '1';
fIFO_Read <= '0';
rx_out_mux_sel <= '0';
when RX100_CLK_L =>
if (fIFO_Data_Exists = '0') then
fifo_flshr_ns <= FLSHR_IDLE_H;
else
fifo_flshr_ns <= RX100_CLK_H;
end if;
Rmii2Mac_rx_clk <= '0';
rx_out_reg_en <= '0';
fIFO_Read <= '0';
rx_out_mux_sel <= '1';
when RX100_CLK_H =>
if (fIFO_Data_Exists = '0') then
fifo_flshr_ns <= FLSHR_IDLE_L;
else
fifo_flshr_ns <= RX100_CLK_L;
end if;
Rmii2Mac_rx_clk <= '1';
rx_out_reg_en <= '1';
fIFO_Read <= '1';
rx_out_mux_sel <= '1';
end case;
end process;
end generate;
end simulation;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGATCPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/axi_ethernetlite_v3_0/d0d8aabb/hdl/src/vhdl/axi_ethernetlite.vhd
|
4
|
41624
|
-------------------------------------------------------------------------------
-- axi_ethernetlite - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename : axi_ethernetlite.vhd
-- Version : v2.0
-- Description : This is the top level wrapper file for the Ethernet
-- Lite function It provides a 10 or 100 Mbs full or half
-- duplex Ethernet bus with an interface to an AXI Interface.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-- PVK 07/29/2010 First Version
-- ^^^^^^
-- Removed ARLOCK and AWLOCK, AWPROT, ARPROT signals from the list.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
use axi_ethernetlite_v3_0.axi_interface;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
--
-- C_FAMILY -- Target device family
-- C_S_AXI_ACLK_PERIOD_PS -- The period of the AXI clock in ps
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width - allowed value - 32 only
-- C_S_AXI_DATA_WIDTH -- AXI data bus width - allowed value - 32 or 64 only
-- C_S_AXI_ID_WIDTH -- AXI Identification TAG width - 1 to 16
-- C_S_AXI_PROTOCOL -- AXI protocol type
--
-- C_DUPLEX -- 1 = Full duplex, 0 = Half duplex
-- C_TX_PING_PONG -- 1 = Ping-pong memory used for transmit buffer
-- 0 = Pong memory not used for transmit buffer
-- C_RX_PING_PONG -- 1 = Ping-pong memory used for receive buffer
-- 0 = Pong memory not used for receive buffer
-- C_INCLUDE_MDIO -- 1 = Include MDIO Innterface,
-- 0 = No MDIO Interface
-- C_INCLUDE_INTERNAL_LOOPBACK -- 1 = Include Internal Loopback logic,
-- 0 = Internal Loopback logic disabled
-- C_INCLUDE_GLOBAL_BUFFERS -- 1 = Include global buffers for PHY clocks
-- 0 = Use normal input buffers for PHY clocks
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset - active low
-- -- interrupts
-- ip2intc_irpt -- Interrupt to processor
--==================================
-- axi write address Channel Signals
--==================================
-- s_axi_awid -- AXI Write Address ID
-- s_axi_awaddr -- AXI Write address - 32 bit
-- s_axi_awlen -- AXI Write Data Length
-- s_axi_awsize -- AXI Burst Size - allowed values
-- -- 000 - byte burst
-- -- 001 - half word
-- -- 010 - word
-- -- 011 - double word
-- -- NA for all remaining values
-- s_axi_awburst -- AXI Burst Type
-- -- 00 - Fixed
-- -- 01 - Incr
-- -- 10 - Wrap
-- -- 11 - Reserved
-- s_axi_awcache -- AXI Cache Type
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
--===============================
-- axi write data channel Signals
--===============================
-- s_axi_wdata -- AXI Write data width
-- s_axi_wstrb -- AXI Write strobes
-- s_axi_wlast -- AXI Last write indicator signal
-- s_axi_wvalid -- AXI Write valid
-- s_axi_wready -- AXI Write ready
--================================
-- axi write data response Signals
--================================
-- s_axi_bid -- AXI Write Response channel number
-- s_axi_bresp -- AXI Write response
-- -- 00 - Okay
-- -- 01 - ExOkay
-- -- 10 - Slave Error
-- -- 11 - Decode Error
-- s_axi_bvalid -- AXI Write response valid
-- s_axi_bready -- AXI Response ready
--=================================
-- axi read address Channel Signals
--=================================
-- s_axi_arid -- AXI Read ID
-- s_axi_araddr -- AXI Read address
-- s_axi_arlen -- AXI Read Data length
-- s_axi_arsize -- AXI Read Size
-- s_axi_arburst -- AXI Read Burst length
-- s_axi_arcache -- AXI Read Cache
-- s_axi_arprot -- AXI Read Protection
-- s_axi_rvalid -- AXI Read valid
-- s_axi_rready -- AXI Read ready
--==============================
-- axi read data channel Signals
--==============================
-- s_axi_rid -- AXI Read Channel ID
-- s_axi_rdata -- AXI Read data
-- s_axi_rresp -- AXI Read response
-- s_axi_rlast -- AXI Read Data Last signal
-- s_axi_rvalid -- AXI Read address valid
-- s_axi_rready -- AXI Read address ready
--
-- -- ethernet
-- phy_tx_clk -- Ethernet tranmit clock
-- phy_rx_clk -- Ethernet receive clock
-- phy_crs -- Ethernet carrier sense
-- phy_dv -- Ethernet receive data valid
-- phy_rx_data -- Ethernet receive data
-- phy_col -- Ethernet collision indicator
-- phy_rx_er -- Ethernet receive error
-- phy_rst_n -- Ethernet PHY Reset
-- phy_tx_en -- Ethernet transmit enable
-- phy_tx_data -- Ethernet transmit data
-- phy_mdio_i -- Ethernet PHY MDIO data input
-- phy_mdio_o -- Ethernet PHY MDIO data output
-- phy_mdio_t -- Ethernet PHY MDIO data 3-state control
-- phy_mdc -- Ethernet PHY management clock
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity axi_ethernetlite is
generic
(
C_FAMILY : string := "virtex6";
C_INSTANCE : string := "axi_ethernetlite_inst";
C_S_AXI_ACLK_PERIOD_PS : integer := 10000;
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ID_WIDTH : integer := 4;
C_S_AXI_PROTOCOL : string := "AXI4";
C_INCLUDE_MDIO : integer := 1;
C_INCLUDE_INTERNAL_LOOPBACK : integer := 0;
C_INCLUDE_GLOBAL_BUFFERS : integer := 1;
C_DUPLEX : integer range 0 to 1:= 1;
C_TX_PING_PONG : integer range 0 to 1:= 0;
C_RX_PING_PONG : integer range 0 to 1:= 0
);
port
(
-- -- AXI Slave signals ------------------------------------------------------
-- -- AXI Global System Signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
ip2intc_irpt : out std_logic;
-- -- axi slave burst Interface
-- -- axi write address Channel Signals
s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_awaddr : in std_logic_vector(12 downto 0); -- (C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- -- axi write data Channel Signals
s_axi_wdata : in std_logic_vector(31 downto 0); -- (C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
--(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- -- axi write response Channel Signals
s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- -- axi read address Channel Signals
s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_araddr : in std_logic_vector(12 downto 0); -- (C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- -- axi read data Channel Signals
s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0); -- (C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- -- Ethernet Interface
phy_tx_clk : in std_logic;
phy_rx_clk : in std_logic;
phy_crs : in std_logic;
phy_dv : in std_logic;
phy_rx_data : in std_logic_vector (3 downto 0);
phy_col : in std_logic;
phy_rx_er : in std_logic;
phy_rst_n : out std_logic;
phy_tx_en : out std_logic;
phy_tx_data : out std_logic_vector (3 downto 0);
phy_mdio_i : in std_logic;
phy_mdio_o : out std_logic;
phy_mdio_t : out std_logic;
phy_mdc : out std_logic
);
-- XST attributes
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
--Psfutil attributes
attribute ASSIGNMENT : string;
attribute ADDRESS : string;
attribute PAIR : string;
end axi_ethernetlite;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_ethernetlite is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Parameters captured for webtalk
-- C_FAMILY
-- C_S_AXI_ACLK_PERIOD_PS
-- C_S_AXI_DATA_WIDTH
-- C_S_AXI_PROTOCOL
-- C_INCLUDE_MDIO
-- C_INCLUDE_INTERNAL_LOOPBACK
-- C_INCLUDE_GLOBAL_BUFFERS
-- C_DUPLEX
-- C_TX_PING_PONG
-- C_RX_PING_PONG
-- constant C_CORE_GENERATION_INFO : string := C_INSTANCE & ",axi_ethernetlite,{"
-- & "c_family=" & C_FAMILY
-- & ",C_INSTANCE = " & C_INSTANCE
-- & ",c_s_axi_protocol=" & C_S_AXI_PROTOCOL
-- & ",c_s_axi_aclk_period_ps=" & integer'image(C_S_AXI_ACLK_PERIOD_PS)
-- & ",c_s_axi_data_width=" & integer'image(C_S_AXI_DATA_WIDTH)
-- & ",c_include_mdio=" & integer'image(C_INCLUDE_MDIO)
-- & ",c_include_internal_loopback=" & integer'image(C_INCLUDE_INTERNAL_LOOPBACK)
-- & ",c_include_global_buffers=" & integer'image(C_INCLUDE_GLOBAL_BUFFERS)
-- & ",c_duplex=" & integer'image(C_DUPLEX)
-- & ",c_tx_ping_pong=" & integer'image(C_TX_PING_PONG)
-- & ",c_rx_ping_pong=" & integer'image(C_RX_PING_PONG)
-- & "}";
--
-- attribute CORE_GENERATION_INFO : string;
-- attribute CORE_GENERATION_INFO of imp : architecture is C_CORE_GENERATION_INFO;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant NODE_MAC : bit_vector := x"00005e00FACE";
-------------------------------------------------------------------------------
-- Signal declaration Section
-------------------------------------------------------------------------------
signal phy_rx_clk_i : std_logic;
signal phy_tx_clk_i : std_logic;
signal phy_rx_clk_ib : std_logic;
signal phy_tx_clk_ib : std_logic;
signal phy_rx_data_i : std_logic_vector(3 downto 0);
signal phy_tx_data_i : std_logic_vector(3 downto 0);
signal phy_tx_data_i_cdc : std_logic_vector(3 downto 0);
signal phy_dv_i : std_logic;
signal phy_rx_er_i : std_logic;
signal phy_tx_en_i : std_logic;
signal phy_tx_en_i_cdc : std_logic;
signal Loopback : std_logic;
signal phy_rx_data_in : std_logic_vector (3 downto 0);
signal phy_rx_data_in_cdc : std_logic_vector (3 downto 0);
signal phy_dv_in : std_logic;
signal phy_dv_in_cdc : std_logic;
signal phy_rx_data_reg : std_logic_vector(3 downto 0);
signal phy_rx_er_reg : std_logic;
signal phy_dv_reg : std_logic;
signal phy_tx_clk_core : std_logic;
signal phy_rx_clk_core : std_logic;
-- IPIC Signals
signal temp_Bus2IP_Addr: std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal bus2ip_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal Bus2IP_Data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_rdce : std_logic;
signal bus2ip_wrce : std_logic;
signal ip2bus_data : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal bus2ip_burst : std_logic;
signal bus2ip_be : std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
signal bus_rst_tx_sync_core : std_logic;
--signal bus_rst_rx_sync : std_logic;
signal bus_rst_rx_sync_core : std_logic;
signal bus_rst : std_logic;
signal ip2bus_errack : std_logic;
component FDRE
port
(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component BUFG
port (
O : out std_ulogic;
I : in std_ulogic := '0'
);
end component;
component BUFGMUX
port (
O : out std_ulogic;
I0 : in std_ulogic := '0';
I1 : in std_ulogic := '0';
S : in std_ulogic
);
end component;
component BUF
port(
O : out std_ulogic;
I : in std_ulogic
);
end component;
COMPONENT IBUF
PORT(i : IN std_logic;
o : OUT std_logic);
END COMPONENT;
-- attribute IOB : string;
begin -- this is the begin between declarations and architecture body
-- PHY Reset
PHY_rst_n <= S_AXI_ARESETN ;
-- Bus Reset
bus_rst <= not S_AXI_ARESETN ;
BUS_RST_RX_SYNC_CORE_I: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => bus_rst,
prmry_ack => open,
scndry_out => bus_rst_rx_sync_core,
scndry_aclk => phy_rx_clk_core,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
BUS_RST_TX_SYNC_CORE_I: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => bus_rst,
prmry_ack => open,
scndry_out => bus_rst_tx_sync_core,
scndry_aclk => phy_tx_clk_core,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- LOOPBACK_GEN :- Include MDIO interface if the parameter
-- C_INCLUDE_INTERNAL_LOOPBACK = 1
----------------------------------------------------------------------------
LOOPBACK_GEN: if C_INCLUDE_INTERNAL_LOOPBACK = 1 generate
begin
-------------------------------------------------------------------------
-- INCLUDE_BUFG_GEN :- Include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 1
-------------------------------------------------------------------------
INCLUDE_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 1 generate
begin
-------------------------------------------------------------------------
-- IBUF for TX/RX clocks
-------------------------------------------------------------------------
TX_IBUF_INST: IBUF
port map (
O => phy_tx_clk_ib,
I => PHY_tx_clk
);
RX_IBUF_INST: IBUF
port map (
O => phy_rx_clk_ib,
I => PHY_rx_clk
);
-------------------------------------------------------------------------
-- BUFG for TX clock
-------------------------------------------------------------------------
CLOCK_BUFG_TX: BUFG
port map (
O => phy_tx_clk_core, --[out]
I => PHY_tx_clk_ib --[in]
);
-------------------------------------------------------------------------
-- BUFGMUX for clock muxing in Loopback mode
-------------------------------------------------------------------------
CLOCK_MUX: BUFGMUX
port map (
O => phy_rx_clk_core, --[out]
I0 => PHY_rx_clk_ib, --[in]
I1 => phy_tx_clk_ib, --[in]
S => Loopback --[in]
);
end generate INCLUDE_BUFG_GEN;
-------------------------------------------------------------------------
-- NO_BUFG_GEN :- Dont include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 0
-------------------------------------------------------------------------
NO_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 0 generate
begin
phy_tx_clk_core <= PHY_tx_clk;
-------------------------------------------------------------------------
-- BUFGMUX for clock muxing in Loopback mode
-------------------------------------------------------------------------
CLOCK_MUX: BUFGMUX
port map (
O => phy_rx_clk_core, --[out]
I0 => PHY_rx_clk, --[in]
I1 => phy_tx_clk_core, --[in]
S => Loopback --[in]
);
end generate NO_BUFG_GEN;
-------------------------------------------------------------------------
-- Internal Loopback generation logic
-------------------------------------------------------------------------
phy_rx_data_in <= phy_tx_data_i when Loopback = '1' else
phy_rx_data_reg;
phy_dv_in <= phy_tx_en_i when Loopback = '1' else
phy_dv_reg;
-- No receive error is generated in internal loopback
phy_rx_er_i <= '0' when Loopback = '1' else
phy_rx_er_reg;
-- Transmit and Receive clocks
phy_tx_clk_i <= phy_tx_clk_core;--not(phy_tx_clk_core);
phy_rx_clk_i <= phy_rx_clk_core;--not(phy_rx_clk_core);
----------------------------------------------------------------------------
-- CDC module for syncing phy_dv_in in rx_clk domain
----------------------------------------------------------------------------
CDC_PHY_DV_IN: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => phy_dv_in,
prmry_ack => open,
scndry_out => phy_dv_in_cdc,
scndry_aclk => phy_rx_clk_i,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
--BUS_RST_RX_SYNC_I: entity lib_cdc_v1_0.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 1,
-- C_FLOP_INPUT => 0,
-- C_VECTOR_WIDTH => 1,
-- C_MTBF_STAGES => 4
-- )
-- port map(
-- prmry_aclk => '1',
-- prmry_resetn => '1',
-- prmry_in => bus_rst,
-- prmry_ack => open,
-- scndry_out => bus_rst_rx_sync,
-- scndry_aclk => phy_rx_clk_i,
-- scndry_resetn => '1',
-- prmry_vect_in => (OTHERS => '0'),
-- scndry_vect_out => open
-- );
-------------------------------------------------------------------------
-- Registering RX signal
-------------------------------------------------------------------------
DV_FF: FDR
port map (
Q => phy_dv_i, --[out]
C => phy_rx_clk_i, --[in]
D => phy_dv_in_cdc, --[in]
R => bus_rst_rx_sync_core); --[in]
----------------------------------------------------------------------------
-- CDC module for syncing phy_rx_data_in in rx_clk domain
----------------------------------------------------------------------------
CDC_PHY_RX_DATA_IN: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 4,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => '1',
prmry_ack => open,
scndry_out => open,
scndry_aclk => phy_rx_clk_i,
scndry_resetn => '1',
prmry_vect_in => phy_rx_data_in,
scndry_vect_out => phy_rx_data_in_cdc
);
-------------------------------------------------------------------------
-- Registering RX data input with clock mux output
-------------------------------------------------------------------------
RX_REG_GEN: for i in 3 downto 0 generate
begin
RX_FF_LOOP: FDRE
port map (
Q => phy_rx_data_i(i), --[out]
C => phy_rx_clk_i, --[in]
CE => '1', --[in]
D => phy_rx_data_in_cdc(i), --[in]
R => bus_rst_rx_sync_core); --[in]
end generate RX_REG_GEN;
end generate LOOPBACK_GEN;
----------------------------------------------------------------------------
-- NO_LOOPBACK_GEN :- Include MDIO interface if the parameter
-- C_INCLUDE_INTERNAL_LOOPBACK = 0
----------------------------------------------------------------------------
NO_LOOPBACK_GEN: if C_INCLUDE_INTERNAL_LOOPBACK = 0 generate
begin
-------------------------------------------------------------------------
-- INCLUDE_BUFG_GEN :- Include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 1
-------------------------------------------------------------------------
INCLUDE_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 1 generate
begin
-------------------------------------------------------------------------
-- IBUF for TX/RX clocks
-------------------------------------------------------------------------
TX_IBUF_INST: IBUF
port map (
O => phy_tx_clk_ib,
I => PHY_tx_clk
);
RX_IBUF_INST: IBUF
port map (
O => phy_rx_clk_ib,
I => PHY_rx_clk
);
-------------------------------------------------------------------------
-- BUFG for clock muxing
-------------------------------------------------------------------------
CLOCK_BUFG_TX: BUFG
port map (
O => phy_tx_clk_core, --[out]
I => PHY_tx_clk_ib --[in]
);
-------------------------------------------------------------------------
-- BUFG for clock muxing
-------------------------------------------------------------------------
CLOCK_BUFG_RX: BUFG
port map (
O => phy_rx_clk_core, --[out]
I => PHY_rx_clk_ib --[in]
);
end generate INCLUDE_BUFG_GEN;
-------------------------------------------------------------------------
-- NO_BUFG_GEN :- Dont include Global Buffer for PHY clocks
-- C_INCLUDE_GLOBAL_BUFFERS = 0
-------------------------------------------------------------------------
NO_BUFG_GEN: if C_INCLUDE_GLOBAL_BUFFERS = 0 generate
begin
phy_tx_clk_core <= PHY_tx_clk;
phy_rx_clk_core <= PHY_rx_clk;
end generate NO_BUFG_GEN;
-- Transmit and Receive clocks for core
phy_tx_clk_i <= phy_tx_clk_core;--not(phy_tx_clk_core);
phy_rx_clk_i <= phy_rx_clk_core;--not(phy_rx_clk_core);
-- TX/RX internal signals
phy_rx_data_i <= phy_rx_data_reg;
phy_rx_er_i <= phy_rx_er_reg;
phy_dv_i <= phy_dv_reg;
end generate NO_LOOPBACK_GEN;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_en in tx_clk domain
----------------------------------------------------------------------------
CDC_PHY_TX_EN_O: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => PHY_tx_en_i,
prmry_ack => open,
scndry_out => PHY_tx_en_i_cdc,
scndry_aclk => phy_tx_clk_core,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_data_out in tx_clk domain
----------------------------------------------------------------------------
CDC_PHY_TX_DATA_OUT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 4,
C_MTBF_STAGES => 2
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => '1',
prmry_ack => open,
scndry_out => open,
scndry_aclk => phy_tx_clk_core,
scndry_resetn => '1',
prmry_vect_in => phy_tx_data_i,
scndry_vect_out => phy_tx_data_i_cdc
);
----------------------------------------------------------------------------
-- Registering the Ethernet data signals
----------------------------------------------------------------------------
IOFFS_GEN: for i in 3 downto 0 generate
-- attribute IOB of RX_FF_I : label is "true";
-- attribute IOB of TX_FF_I : label is "true";
begin
RX_FF_I: FDRE
port map (
Q => phy_rx_data_reg(i), --[out]
C => phy_rx_clk_core, --[in]
CE => '1', --[in]
D => PHY_rx_data(i), --[in]
R => bus_rst_rx_sync_core); --[in]
TX_FF_I: FDRE
port map (
Q => PHY_tx_data(i), --[out]
C => phy_tx_clk_core, --[in]
CE => '1', --[in]
D => phy_tx_data_i_cdc(i), --[in]
R => bus_rst_tx_sync_core); --[in]
end generate IOFFS_GEN;
----------------------------------------------------------------------------
-- Registering the Ethernet control signals
----------------------------------------------------------------------------
IOFFS_GEN2: if(true) generate
-- attribute IOB of DVD_FF : label is "true";
-- attribute IOB of RER_FF : label is "true";
-- attribute IOB of TEN_FF : label is "true";
begin
DVD_FF: FDRE
port map (
Q => phy_dv_reg, --[out]
C => phy_rx_clk_core, --[in]
CE => '1', --[in]
D => PHY_dv, --[in]
R => bus_rst_rx_sync_core); --[in]
RER_FF: FDRE
port map (
Q => phy_rx_er_reg, --[out]
C => phy_rx_clk_core, --[in]
CE => '1', --[in]
D => PHY_rx_er, --[in]
R => bus_rst_rx_sync_core); --[in]
TEN_FF: FDRE
port map (
Q => PHY_tx_en, --[out]
C => phy_tx_clk_core, --[in]
CE => '1', --[in]
D => PHY_tx_en_i_cdc, --[in]
R => bus_rst_tx_sync_core); --[in]
end generate IOFFS_GEN2;
----------------------------------------------------------------------------
-- XEMAC Module
----------------------------------------------------------------------------
XEMAC_I : entity axi_ethernetlite_v3_0.xemac
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ACLK_PERIOD_PS => C_S_AXI_ACLK_PERIOD_PS,
C_DUPLEX => C_DUPLEX,
C_RX_PING_PONG => C_RX_PING_PONG,
C_TX_PING_PONG => C_TX_PING_PONG,
C_INCLUDE_MDIO => C_INCLUDE_MDIO,
NODE_MAC => NODE_MAC
)
port map
(
Clk => S_AXI_ACLK,
Rst => bus_rst,
IP2INTC_Irpt => IP2INTC_Irpt,
-- Bus2IP Signals
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Bus2IP_Burst => bus2ip_burst,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce,
-- IP2Bus Signals
IP2Bus_Data => ip2bus_data,
IP2Bus_Error => ip2bus_errack,
-- EMAC Signals
PHY_tx_clk => phy_tx_clk_i,
PHY_rx_clk => phy_rx_clk_i,
PHY_crs => PHY_crs,
PHY_dv => phy_dv_i,
PHY_rx_data => phy_rx_data_i,
PHY_col => PHY_col,
PHY_rx_er => phy_rx_er_i,
PHY_tx_en => PHY_tx_en_i,
PHY_tx_data => PHY_tx_data_i,
PHY_MDIO_I => phy_mdio_i,
PHY_MDIO_O => phy_mdio_o,
PHY_MDIO_T => phy_mdio_t,
PHY_MDC => phy_mdc,
Loopback => Loopback
);
I_AXI_NATIVE_IPIF: entity axi_ethernetlite_v3_0.axi_interface
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWID => s_axi_awid,
S_AXI_AWLEN => s_axi_awlen,
S_AXI_AWSIZE => s_axi_awsize,
S_AXI_AWBURST => s_axi_awburst,
S_AXI_AWCACHE => s_axi_awcache,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WLAST => s_axi_wlast,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BID => s_axi_bid,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARID => s_axi_arid,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARLEN => s_axi_arlen,
S_AXI_ARSIZE => s_axi_arsize,
S_AXI_ARBURST => s_axi_arburst,
S_AXI_ARCACHE => s_axi_arcache,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RID => s_axi_rid,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RLAST => s_axi_rlast,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals ------------------------------------
-- Controls to the IP/IPIF modules
-- IP Interconnect (IPIC) port signals
IP2Bus_Data => ip2bus_data,
IP2Bus_Error => ip2bus_errack,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Bus2IP_Burst => bus2ip_burst,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
------------------------------------------------------------------------------------------
end imp;
|
gpl-3.0
|
AlistairCheeseman/WindTunnelApparatus
|
Firmware/Tests/FPGA/FPGAUDPtest/GSMBS2015.2.srcs/sources_1/ipshared/xilinx.com/emc_common_v3_0/d241abca/hdl/src/vhdl/io_registers.vhd
|
4
|
22661
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: io_registers.vhd
-- Description: This file contains the IO registers for the EMC
-- design.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- emc.vhd
-- -- ipic_if.vhd
-- -- addr_counter_mux.vhd
-- -- counters.vhd
-- -- select_param.vhd
-- -- mem_state_machine.vhd
-- -- mem_steer.vhd
-- -- io_registers.vhd
-------------------------------------------------------------------------------
-- Author: NSK
-- History:
-- NSK 02/01/08 First Version
-- ^^^^^^^^^^
-- This file is based on version v3_01_c updated to fixed CR #466745: -
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE. This is used to cpture the Mem_DQ_I
-- 1. If C_MEM_DQ_CAPTURE_NEGEDGE=0 Mem_DQ_I will be captured on +ve edge
-- (same as version v3_01_c)
-- 2. If C_MEM_DQ_CAPTURE_NEGEDGE=1 Mem_DQ_I will be captured on -ve edge (new)
-- ~~~~~~~~~
-- NSK 02/12/08 Updated
-- ^^^^^^^^
-- Added generic C_MEM_DQ_CAPTURE_NEGEDGE in comment "Definition of Generics"
-- section.
-- ~~~~~~~~
-- NSK 03/03/08 Updated
-- ^^^^^^^^
-- 1. Removed generic C_MEM_DQ_CAPTURE_NEGEDGE.
-- 2. Added the port RdClk used as clock to capture the data from memory.
-- ~~~~~~~~
-- NSK 05/08/08 version v3_00_a
-- ^^^^^^^^
-- 1. This file is same as in version v3_02_a.
-- 2. Upgraded to version v3.00.a to have proper versioning to fix CR #472164.
-- 3. No change in design.
-- ~~~~~~~~
-- ^^^^^^^^
-- KSB 08/08/08 version v4_00_a
-- 1. This file is same as in version v3_00_a.
-- 2. Upgraded to version v4.00.a
-- ~~~~~~~~
-- SK 02/11/10 version v5_01_a
-- ^^^^^^^^
-- 1. Registered the IP2Bus_RdAck and IP2Bus_Data signals.
-- 2. Reduced utilization
-- ~~~~~~~~
-- ~~~~~~
-- Sateesh 2011
-- ^^^^^^
-- -- Added Sync burst support for the Numonyx flash during read
-- ~~~~~~
-- ~~~~~~
-- SK 10/20/12
-- ^^^^^^
-- -- Fixed CR 672770 - BRESP signal is driven X during netlist simulation
-- -- Fixed CR 673491 - Flash transactions generates extra read cycle after the actual reads are over
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_INCLUDE_NEGEDGE_IOREGS -- include negative edge IO registers
-- C_IPIF_AWIDTH -- width of processor address bus
-- C_MAX_MEM_WIDTH -- maximum data width of memory banks
-- C_NUM_BANKS_MEM -- number of memory banks
--
-- Definition of Ports:
-- -- Internal memory signals
-- Mem_A_int -- Internal Memory address inputs
-- Mem_DQ_I_int -- Internal Memory input data bus
-- Mem_DQ_O_int -- Internal Memory output data bus
-- Mem_DQ_T_int -- Internal Memory data output enable
-- Mem_CEN_int -- Internal Memory chip select
-- Mem_OEN_int -- Internal Memory output enable
-- Mem_WEN_int -- Internal Memory write enable
-- Mem_QWEN_int -- Internal Memory qualified write enable
-- Mem_BEN_int -- Internal Memory byte enables
-- Mem_RPN_int -- Internal Memory reset/power down
-- Mem_CE_int -- Internal Memory chip enable
-- Mem_ADV_LDN_int -- Internal Memory counter
-- advance/load (=0)
-- Mem_LBON_int -- Internal Memory linear/interleaved
-- burst order (=0)
-- Mem_CKEN_int -- Internal Memory clock enable (=0)
-- Mem_RNW_int -- Internal Memory read not write
--
-- -- Memory signals
-- Mem_A -- Memory address inputs
-- Mem_DQ_I -- Memory input data bus
-- Mem_DQ_O -- Memory output data bus
-- Mem_DQ_T -- Memory data output enable
-- Mem_CEN -- Memory chip select
-- Mem_OEN -- Memory output enable
-- Mem_WEN -- Memory write enable
-- Mem_QWEN -- Memory qualified write enable
-- Mem_BEN -- Memory byte enables
-- Mem_RPN -- Memory reset/power down
-- Mem_CE -- Memory chip enable
-- Mem_ADV_LDN -- Memory counter advance/load (=0)
-- Mem_LBON -- Memory linear/interleaved burst
-- order (=0)
-- Mem_CKEN -- Memory clock enable (=0)
-- Mem_RNW -- Memory read not write
--
-- --- Clock & Reset
-- Clk -- System Clock
-- RdClk -- Read Clock
-- Rst -- System Reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity io_registers is
generic (
C_INCLUDE_NEGEDGE_IOREGS : integer range 0 to 1;
C_IPIF_AWIDTH : integer;
C_MAX_MEM_WIDTH : integer;
C_NUM_BANKS_MEM : integer;
C_FAMILY : string := "virtex6"
);
port (
-- Internal memory signals
Mem_A_int : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Mem_DQ_I_int : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_O_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_T_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_PARITY_I_int : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PARITY_O_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PARITY_T_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_CEN_int : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_OEN_int : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_WEN_int : in std_logic;
Mem_QWEN_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_BEN_int : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_RPN_int : in std_logic;
Mem_CE_int : in std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_ADV_LDN_int : in std_logic;
Mem_LBON_int : in std_logic;
Mem_CKEN_int : in std_logic;
Mem_RNW_int : in std_logic;
Mem_Addr_rst : in std_logic;
-- Memory signals
Mem_A : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
Mem_DQ_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
Mem_DQ_PRTY_I : in std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_O : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_DQ_PRTY_T : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_CEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_OEN : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_WEN : out std_logic;
Mem_QWEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_BEN : out std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
Mem_RPN : out std_logic;
Mem_CE : out std_logic_vector(0 to C_NUM_BANKS_MEM-1);
Mem_ADV_LDN : out std_logic;
Mem_LBON : out std_logic;
Mem_CKEN : out std_logic;
Mem_RNW : out std_logic;
Linear_flash_brst_rd_flag : in std_logic;
-- Clock & Reset
Clk : in std_logic;
RdClk : in std_logic;
Rst : in std_logic
);
end entity io_registers;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of io_registers is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
signal mem_a_reg : std_logic_vector(0 to C_IPIF_AWIDTH-1);
--signal mem_a_reg1 : std_logic_vector(0 to C_IPIF_AWIDTH-1);
signal mem_dq_o_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_t_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal mem_dq_paity_o_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_dq_paity_t_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_cen_reg : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_oen_reg : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_wen_reg : std_logic;
signal mem_qwen_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_ben_reg : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
signal mem_rpn_reg : std_logic;
signal mem_ce_reg : std_logic_vector(0 to C_NUM_BANKS_MEM-1);
signal mem_adv_ldn_reg : std_logic;
signal mem_lbon_reg : std_logic;
signal mem_cken_reg : std_logic;
signal mem_rnw_reg : std_logic;
signal rd_data_ack : std_logic;
signal rd_data_ack_int : std_logic;
signal one_hot_rd_data_d1 : std_logic;
signal one_hot_rd_data_d2 : std_logic;
signal Mem_DQ_I_v : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal Mem_DQ_I_v1 : std_logic_vector(0 to C_MAX_MEM_WIDTH-1);
signal Mem_DQ_PARITY_I_io : std_logic_vector(0 to C_MAX_MEM_WIDTH/8-1);
-------------------------------------------------------------------------------
-- Component declarations
-------------------------------------------------------------------------------
attribute KEEP : string;
attribute KEEP of mem_wen_reg : signal is "true";
attribute IOB : string;
attribute IOB of Mem_DQ_I_v : signal is "true";
attribute IOB of Mem_DQ_PARITY_I_io : signal is "true";
attribute IOB of mem_dq_o_reg : signal is "true";
attribute IOB of mem_dq_t_reg : signal is "true";
attribute IOB of mem_dq_paity_o_reg : signal is "true";
attribute IOB of mem_dq_paity_t_reg : signal is "true";
attribute IOB of mem_ce_reg : signal is "true";
attribute IOB of mem_cen_reg : signal is "true";
attribute IOB of mem_oen_reg : signal is "true";
attribute IOB of mem_ben_reg : signal is "true";
attribute IOB of mem_qwen_reg : signal is "true";
attribute IOB of mem_rpn_reg : signal is "true";
attribute IOB of mem_rnw_reg : signal is "true";
attribute IOB of mem_wen_reg : signal is "true";
--Ports tied to zero
attribute IOB of mem_adv_ldn_reg : signal is "true";
attribute IOB of mem_lbon_reg : signal is "true";
attribute IOB of mem_cken_reg : signal is "true";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- OUTPUTS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Instantiate the positive clock edge output register.
-- This is always present due to combinational logic on the memory control
-- signals.
-------------------------------------------------------------------------------
POSEDGE_OUTPUTREGS_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
mem_dq_o_reg <= (others => '0');
mem_dq_t_reg <= (others => '1');
mem_dq_paity_o_reg <= (others => '0');
mem_dq_paity_t_reg <= (others => '1');
mem_cen_reg <= (others => '1');
mem_oen_reg <= (others => '1');
mem_wen_reg <= '1';
mem_qwen_reg <= (others => '1');
mem_ben_reg <= (others => '1');
mem_rpn_reg <= '0';
mem_ce_reg <= (others => '0');
mem_adv_ldn_reg <= '0';
mem_lbon_reg <= '0';
mem_cken_reg <= '0';
mem_rnw_reg <= '0';
else
mem_dq_o_reg <= Mem_DQ_O_int;
mem_dq_t_reg <= Mem_DQ_T_int;
mem_dq_paity_o_reg <= Mem_DQ_PARITY_O_int;
mem_dq_paity_t_reg <= Mem_DQ_PARITY_T_int;
mem_cen_reg <= Mem_CEN_int;
mem_oen_reg <= Mem_OEN_int;
mem_wen_reg <= Mem_WEN_int;
mem_qwen_reg <= Mem_QWEN_int;
mem_ben_reg <= Mem_BEN_int;
mem_rpn_reg <= Mem_RPN_int;
mem_ce_reg <= Mem_CE_int;
mem_adv_ldn_reg <= Mem_ADV_LDN_int;
mem_lbon_reg <= Mem_LBON_int;
mem_cken_reg <= Mem_CKEN_int;
mem_rnw_reg <= Mem_RNW_int;
end if;
end if;
end process POSEDGE_OUTPUTREGS_PROCESS;
-------------------------------------------------------------------------------
-- MEM_ADDR_PROCESS: This process is added to fix CR: 214725
--
-------------------------------------------------------------------------------
--MEM_ADDR_PROCESS: process(clk)
--begin
-- if Clk'event and Clk = '1' then
-- if (Mem_Addr_rst = '1') then
-- mem_a_reg <= (others => '0');
-- --mem_a_reg1 <= (others => '0');
-- else
-- mem_a_reg <= Mem_A_int;
-- --mem_a_reg <= mem_a_reg1 ;
-- end if;
-- end if;
--end process MEM_ADDR_PROCESS;
mem_a_reg <= (others => '0') when (Mem_Addr_rst = '1') else Mem_A_int;
-------------------------------------------------------------------------------
-- Instantiate the negative clock edge output register if design has been
-- configured to do so.
-------------------------------------------------------------------------------
NEGEDGE_OUTPUT_REGS_GEN: if C_INCLUDE_NEGEDGE_IOREGS = 1 generate
begin
NEGEDGE_OUTPUTREGS_PROCESS: process(Clk)
begin
if Clk'event and Clk = '0' then
if Rst = '1' then
Mem_A <= (others => '0');
Mem_DQ_O <= (others => '0');
Mem_DQ_T <= (others => '1');
Mem_DQ_PRTY_O <= (others => '0');
Mem_DQ_PRTY_T <= (others => '1');
Mem_CEN <= (others => '1');
Mem_OEN <= (others => '1');
Mem_WEN <= '1';
Mem_QWEN <= (others => '1');
Mem_BEN <= (others => '1');
Mem_RPN <= '0';
Mem_CE <= (others => '0');
Mem_ADV_LDN <= '0';
Mem_LBON <= '0';
Mem_CKEN <= '0';
Mem_RNW <= '0';
else
Mem_A <= mem_a_reg;
Mem_DQ_O <= mem_dq_o_reg;
Mem_DQ_T <= mem_dq_t_reg;
Mem_DQ_PRTY_O <= mem_dq_paity_o_reg;
Mem_DQ_PRTY_T <= mem_dq_paity_t_reg;
Mem_CEN <= mem_cen_reg;
Mem_OEN <= mem_oen_reg;
Mem_WEN <= mem_wen_reg;
Mem_QWEN <= mem_qwen_reg;
Mem_BEN <= mem_ben_reg;
Mem_RPN <= mem_rpn_reg;
Mem_CE <= mem_ce_reg;
Mem_ADV_LDN <= mem_adv_ldn_reg;
Mem_LBON <= mem_lbon_reg;
Mem_CKEN <= mem_cken_reg;
Mem_RNW <= mem_rnw_reg;
end if;
end if;
end process NEGEDGE_OUTPUTREGS_PROCESS;
end generate NEGEDGE_OUTPUT_REGS_GEN;
-------------------------------------------------------------------------------
-- Pass the values through if there are no negative io registers
-------------------------------------------------------------------------------
NO_NEGEDGE_OUTPUT_REGS_GEN: if C_INCLUDE_NEGEDGE_IOREGS = 0 generate
begin
Mem_A <= mem_a_reg;
Mem_DQ_O <= mem_dq_o_reg;
Mem_DQ_T <= mem_dq_t_reg;
Mem_DQ_PRTY_O <= mem_dq_paity_o_reg;
Mem_DQ_PRTY_T <= mem_dq_paity_t_reg;
Mem_CEN <= mem_cen_reg;
Mem_OEN <= mem_oen_reg;
Mem_WEN <= mem_wen_reg;
Mem_QWEN <= mem_qwen_reg;
Mem_BEN <= mem_ben_reg;
Mem_RPN <= mem_rpn_reg;
Mem_CE <= mem_ce_reg;
Mem_ADV_LDN <= mem_adv_ldn_reg;
Mem_LBON <= mem_lbon_reg;
Mem_CKEN <= mem_cken_reg;
Mem_RNW <= mem_rnw_reg;
end generate NO_NEGEDGE_OUTPUT_REGS_GEN;
-------------------------------------------------------------------------------
-- Registers the input memory data port signals.
-------------------------------------------------------------------------------
INPUTREGS_PROCESS: process(RdClk)
begin
if RdClk'event and RdClk = '1' then
if Rst = '1' then
Mem_DQ_I_v <= (others => '0');
Mem_DQ_I_v1 <= (others => '0');
Mem_DQ_PARITY_I_io <= (others => '0');
else
Mem_DQ_I_v <= Mem_DQ_I;
Mem_DQ_I_v1 <= Mem_DQ_I_v;
Mem_DQ_PARITY_I_io <= Mem_DQ_PRTY_I;
end if;
end if;
end process INPUTREGS_PROCESS;
Mem_DQ_I_int <= Mem_DQ_I_v1 when (Linear_flash_brst_rd_flag = '1') else Mem_DQ_I_v;
Mem_DQ_PARITY_I_int <= Mem_DQ_PARITY_I_io;
end architecture imp;
-------------------------------------------------------------------------------
-- End of File io_registers.vhd.
-------------------------------------------------------------------------------
|
gpl-3.0
|
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