AWfaw/ai-hdlcoder-dataset · Datasets at Hugging Face

repo_name stringlengths 6 79	path stringlengths 5 236	copies stringclasses 54 values	size stringlengths 1 8	content stringlengths 0 1.04M ⌀	license stringclasses 15 values
Darkin47/Zynq-TX-UTT	Vivado_HLS/image_contrast_adj/solution1/impl/vhdl/doHistStretch_fdiv_32ns_32ns_32_16.vhd	5	3100	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity doHistStretch_fdiv_32ns_32ns_32_16 is generic ( ID : integer := 2; NUM_STAGE : integer := 16; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of doHistStretch_fdiv_32ns_32ns_32_16 is --------------------- Component --------------------- component doHistStretch_ap_fdiv_14_no_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- doHistStretch_ap_fdiv_14_no_dsp_32_u : component doHistStretch_ap_fdiv_14_no_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;	gpl-3.0
Darkin47/Zynq-TX-UTT	Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/utt.fr/dohiststretch_v1_0/hdl/vhdl/doHistStretch_fdiv_32ns_32ns_32_16.vhd	5	3100	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity doHistStretch_fdiv_32ns_32ns_32_16 is generic ( ID : integer := 2; NUM_STAGE : integer := 16; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of doHistStretch_fdiv_32ns_32ns_32_16 is --------------------- Component --------------------- component doHistStretch_ap_fdiv_14_no_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- doHistStretch_ap_fdiv_14_no_dsp_32_u : component doHistStretch_ap_fdiv_14_no_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;	gpl-3.0
Darkin47/Zynq-TX-UTT	Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_pcc.vhd	3	103944	------------------------------------------------------------------------------- -- axi_datamover_pcc.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_pcc.vhd -- -- Description: -- This file implements the DataMover Predictive Command Calculator (PCC). -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_strb_gen2; ------------------------------------------------------------------------------- entity axi_datamover_pcc is generic ( C_IS_MM2S : Integer range 0 to 1 := 0; -- This parameter tells the PCC module if it is a MM2S -- instance or a S2MM instance. -- 0 = S2MM Instance -- 1 = MM2S Instance C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE Aligment output ports C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the LS address bus used for -- Muxing/Demuxing data to/from a wider AXI4 data bus C_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Sets the width of the AXi Address Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Stream Data width that -- is being supported by the PCC C_MAX_BURST_LEN : Integer range 2 to 256 := 16; -- Indicates the max allowed burst length to use for -- AXI4 transfer calculations C_CMD_WIDTH : Integer := 68; -- Sets the width of the input command port C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the input command C_BTT_USED : Integer range 8 to 23 := 16; -- Sets the width of the used portion of the BTT field -- of the input command C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates if the Indeterminate BTT mode is enabled C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32; -- Indicates the Native transfer width to use for all -- transfer calculations. This will either be the DataMover -- input Stream width or the AXI4 MMap data width depending -- on DataMover parameterization. C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 -- Indicates the width of the starting address offset -- bus passed to Store and Forward functions ); port ( -- Clock and Reset input ---------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------------- -- Master Command FIFO/Register Interface -------------------------------------------- -- cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- -- The next command value available from the Command FIFO/Register -- -- cache2mstr_command : in std_logic_vector(7 downto 0); -- -- The next command value available from the Command FIFO/Register -- cmd2mstr_cmd_valid : in std_logic; -- -- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry -- -- mst2cmd_cmd_ready : out std_logic; -- -- Handshake bit indicating the Command Calculator is ready to accept -- -- another command -- -------------------------------------------------------------------------------------- -- Address Channel Controller Interface ----------------------------------- -- mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- The next command address to put on the AXI MMap ADDR -- -- mstr2addr_len : out std_logic_vector(7 downto 0); -- -- The next command length to put on the AXI MMap LEN -- -- mstr2addr_size : out std_logic_vector(2 downto 0); -- -- The next command size to put on the AXI MMap SIZE -- -- mstr2addr_burst : out std_logic_vector(1 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cache : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_user : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_cmd_cmplt : out std_logic; -- -- The indication to the Address Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2addr_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calcualtion error -- -- mstr2addr_cmd_valid : out std_logic; -- -- The next command valid indication to the Address Channel -- -- Controller for the AXI MMap -- -- addr2mstr_cmd_ready : In std_logic; -- -- Indication from the Address Channel Controller that the -- -- command is being accepted -- --------------------------------------------------------------------------- -- Data Channel Controller Interface ------------------------------------------------ -- mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap data -- -- width). -- -- mstr2data_len : out std_logic_vector(7 downto 0); -- -- The LEN value output to the Address Channel -- -- mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The starting strobe value to use for the data transfer -- -- mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The endiing (LAST) strobe value to use for the data transfer -- -- mstr2data_drr : out std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2data_eof : out std_logic; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2data_sequential : Out std_logic; -- -- The next sequential tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2data_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2data_cmd_cmplt : out std_logic; -- -- The indication to the Data Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2data_cmd_valid : out std_logic; -- -- The next command valid indication to the Data Channel -- -- Controller for the AXI MMap -- -- data2mstr_cmd_ready : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- command is being accepted on the AXI Address -- -- Channel -- -- mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the MM2S DRE -- -- mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the MM2S DRE -- ------------------------------------------------------------------------------------- -- Output flag indicating that a calculation error has occured ---------------------- -- calc_error : Out std_logic; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- ------------------------------------------------------------------------------------- -- Special DRE Controller Interface -------------------------------------------- -- dre2mstr_cmd_ready : In std_logic ; -- -- Indication from the S2MM DRE Controller that it can -- -- accept another command. -- -- mstr2dre_cmd_valid : out std_logic ; -- -- The next command valid indication to the S2MM DRE -- -- Controller. -- -- mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The source (S2MM Stream) alignment for the S2MM DRE -- -- mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The destinstion (S2MM MMap) alignment for the S2MM DRE -- -- mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; -- -- The BTT value output to the S2MM DRE. This is needed for -- -- Scatter operations. -- -- mstr2dre_drr : out std_logic ; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : out std_logic ; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2dre_cmd_cmplt : Out std_logic ; -- -- The last child tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2dre_calc_error : out std_logic ; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- ------------------------------------------------------------------------------------- -- Store and Forward Support Start Offset --------------------------------------------- -- mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) -- -- Relays the starting address offset for a transfer to the Store and Forward -- -- functions incorporating upsizer/downsizer logic -- --------------------------------------------------------------------------------------- ); end entity axi_datamover_pcc; architecture implementation of axi_datamover_pcc is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declarations ------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_dbeat_residue_width -- -- Function Description: -- Calculates the number of Least significant bits of the BTT field -- that are unused for the LEN calculation -- ------------------------------------------------------------------- function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream begin case bytes_per_beat is when 1 => temp_dbeat_residue_width := 0; when 2 => temp_dbeat_residue_width := 1; when 4 => temp_dbeat_residue_width := 2; when 8 => temp_dbeat_residue_width := 3; when 16 => temp_dbeat_residue_width := 4; when 32 => temp_dbeat_residue_width := 5; when 64 => temp_dbeat_residue_width := 6; when others => -- 128-byte transfers temp_dbeat_residue_width := 7; end case; Return (temp_dbeat_residue_width); end function funct_get_dbeat_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_burstcnt_offset -- -- Function Description: -- Calculates the bit offset from the residue bits needed to detirmine -- the load value for the burst counter. -- ------------------------------------------------------------------- function funct_get_burst_residue_width (max_burst_len : integer) return integer is Variable temp_burst_residue_width : Integer := 0; begin case max_burst_len is when 256 => temp_burst_residue_width := 8; when 128 => temp_burst_residue_width := 7; when 64 => temp_burst_residue_width := 6; when 32 => temp_burst_residue_width := 5; when 16 => temp_burst_residue_width := 4; when 8 => temp_burst_residue_width := 3; when 4 => temp_burst_residue_width := 2; when others => -- assume 2 dbeats temp_burst_residue_width := 1; end case; Return (temp_burst_residue_width); end function funct_get_burst_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_axi_size -- -- Function Description: -- Calculates the AXI SIZE Qualifier based on the data width. -- ------------------------------------------------------------------- function func_get_axi_size (native_dwidth : integer) return std_logic_vector is Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000"; Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001"; Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010"; Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011"; Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100"; Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101"; Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110"; Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111"; Variable temp_size : std_logic_vector(2 downto 0) := (others => '0'); begin case native_dwidth is when 8 => temp_size := AXI_SIZE_1BYTE; when 16 => temp_size := AXI_SIZE_2BYTE; when 32 => temp_size := AXI_SIZE_4BYTE; when 64 => temp_size := AXI_SIZE_8BYTE; when 128 => temp_size := AXI_SIZE_16BYTE; when 256 => temp_size := AXI_SIZE_32BYTE; when 512 => temp_size := AXI_SIZE_64BYTE; when others => -- 1024 bit dwidth temp_size := AXI_SIZE_128BYTE; end case; Return (temp_size); end function func_get_axi_size; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_ls_index -- -- Function Description: -- Calculates the Ls index of the Store and Forward -- starting offset bus based on the User Stream Width. -- ------------------------------------------------------------------- function funct_get_sf_offset_ls_index (stream_width : integer) return integer is Variable lvar_temp_ls_index : Integer := 0; begin case stream_width is when 8 => lvar_temp_ls_index := 0; when 16 => lvar_temp_ls_index := 1; when 32 => lvar_temp_ls_index := 2; when 64 => lvar_temp_ls_index := 3; when 128 => lvar_temp_ls_index := 4; when 256 => lvar_temp_ls_index := 5; when 512 => lvar_temp_ls_index := 6; when others => -- 1024 lvar_temp_ls_index := 7; end case; Return (lvar_temp_ls_index); end function funct_get_sf_offset_ls_index; -- Constant Declarations ---------------------------------------- Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address) Constant CMD_BTT_WIDTH : integer := C_BTT_USED; Constant CMD_BTT_LS_INDEX : integer := 0; Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1; Constant CMD_TYPE_INDEX : integer := 23; Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1; Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2; Constant CMD_DSA_WIDTH : integer := 6; Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1; Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1; Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH; Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1; Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH; Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH; Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1; ---------------------------------------------------------------------------------------- -- Command calculation constants Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH); Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8; Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN; Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURSTBYTES_PER_DBEAT; Constant LEN_WIDTH : integer := 8; -- 8 bits fixed Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1; Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT); Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN); Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH; Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH); Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH); Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH); Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH); Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH); Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH; Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH); Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH); Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH); Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH); Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1; -- Type Declarations -------------------------------------------- type PCC_SM_STATE_TYPE is ( INIT, WAIT_FOR_CMD, CALC_1, CALC_2, CALC_3, WAIT_ON_XFER_PUSH, CHK_IF_DONE, ERROR_TRAP ); -- Signal Declarations -------------------------------------------- Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT; Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT; signal sig_sm_halt_ns : std_logic := '0'; signal sig_sm_halt_reg : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0'; signal sig_sm_pop_input_reg_ns : std_logic := '0'; signal sig_sm_pop_input_reg : std_logic := '0'; signal sig_sm_ld_calc1_reg_ns : std_logic := '0'; signal sig_sm_ld_calc1_reg : std_logic := '0'; signal sig_sm_ld_calc2_reg_ns : std_logic := '0'; signal sig_sm_ld_calc2_reg : std_logic := '0'; signal sig_sm_ld_calc3_reg_ns : std_logic := '0'; signal sig_sm_ld_calc3_reg : std_logic := '0'; signal sig_parent_done : std_logic := '0'; signal sig_ld_xfer_reg : std_logic := '0'; signal sig_ld_xfer_reg_tmp : std_logic := '0'; signal sig_btt_raw : std_logic := '0'; signal sig_btt_is_zero : std_logic := '0'; signal sig_btt_is_zero_reg : std_logic := '0'; -- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0'); -- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0'); -- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); -- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); ---------------------------------------------------------------------------------------- -- Burst Buster signals signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_last_xfer_valid_im1 : std_logic := '0'; signal sig_brst_cnt_eq_zero_im0 : std_logic := '0'; signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0'; signal sig_brst_cnt_eq_one_im0 : std_logic := '0'; signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0'; signal sig_brst_residue_eq_zero : std_logic := '0'; signal sig_brst_residue_eq_zero_reg : std_logic := '0'; signal sig_no_btt_residue_im0 : std_logic := '0'; signal sig_no_btt_residue_ireg1 : std_logic := '0'; signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); -- Input command register signal sig_push_input_reg : std_logic := '0'; signal sig_pop_input_reg : std_logic := '0'; signal sig_input_burst_type_reg : std_logic := '0'; signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_input_drr_reg : std_logic := '0'; signal sig_input_eof_reg : std_logic := '0'; signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_input_reg_empty : std_logic := '0'; signal sig_input_reg_full : std_logic := '0'; -- Output qualifier Register -- signal sig_ld_output : std_logic := '0'; signal sig_push_xfer_reg : std_logic := '0'; signal sig_pop_xfer_reg : std_logic := '0'; signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_type_reg : std_logic := '0'; signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_drr_reg : std_logic := '0'; signal sig_xfer_eof_reg : std_logic := '0'; signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_is_seq_reg : std_logic := '0'; signal sig_xfer_cmd_cmplt_reg : std_logic := '0'; signal sig_xfer_calc_err_reg : std_logic := '0'; signal sig_xfer_reg_empty : std_logic := '0'; signal sig_xfer_reg_full : std_logic := '0'; -- Address Counter signal sig_ld_addr_cntr : std_logic := '0'; signal sig_incr_addr_cntr : std_logic := '0'; signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); -- misc signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0); signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_type_slice : std_logic := '0'; signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_drr_slice : std_logic := '0'; signal sig_cmd_eof_slice : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_calc_error_pushed : std_logic := '0'; -- PCC2 stuff signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_im2 : std_logic := '0'; signal sig_first_xfer_im0 : std_logic := '0'; signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover : std_logic := '0'; signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_ld_btt_cntr : std_logic := '0'; signal sig_decr_btt_cntr : std_logic := '0'; signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2data_valid : std_logic := '0'; signal sig_clr_cmd2data_valid : std_logic := '0'; signal sig_cmd2addr_valid : std_logic := '0'; signal sig_clr_cmd2addr_valid : std_logic := '0'; signal sig_btt_lt_b2mbaa_im0 : std_logic := '0'; signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0'; signal sig_btt_eq_b2mbaa_im0 : std_logic := '0'; signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0'; signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0'; -- Unaligned start address support signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_aligned_im0 : std_logic := '0'; signal sig_addr_aligned_ireg1 : std_logic := '0'; -- S2MM DRE Support signal sig_cmd2dre_valid : std_logic := '0'; signal sig_clr_cmd2dre_valid : std_logic := '0'; signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dre_eof_reg : std_logic := '0'; -- Long Timing path breakup intermediate registers signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_ireg3 : std_logic := '0'; signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover_im3 : std_logic := '0'; signal sig_mmap_reset_reg : std_logic := '0'; ---------------------------------------------------------- begin --(architecture implementation) -- Assign calculation error output calc_error <= sig_calc_error_reg; -- Assign the ready output to the Command FIFO mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and sig_input_reg_empty and not(sig_calc_error_pushed); -- Assign the Address Channel Controller Qualifiers mstr2addr_tag <= sig_xfer_tag_reg ; mstr2addr_addr <= sig_xfer_addr_reg; mstr2addr_len <= sig_xfer_len_reg ; mstr2addr_size <= sig_xfer_size ; mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported mstr2addr_cmd_valid <= sig_cmd2addr_valid; mstr2addr_calc_error <= sig_xfer_calc_err_reg; mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Assign the Data Channel Controller Qualifiers mstr2data_tag <= sig_xfer_tag_reg ; mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0); mstr2data_len <= sig_xfer_len_reg ; mstr2data_strt_strb <= sig_xfer_strt_strb_reg; mstr2data_last_strb <= sig_xfer_end_strb_reg ; mstr2data_drr <= sig_xfer_drr_reg ; mstr2data_eof <= sig_xfer_eof_reg ; mstr2data_sequential <= sig_xfer_is_seq_reg ; mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; mstr2data_cmd_valid <= sig_cmd2data_valid ; mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_calc_error <= sig_xfer_calc_err_reg ; -- Assign the DRE Controller Qualifiers mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE ------------------------------------------------------------ -- If Generate -- -- Label: DO_MM2S_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the MM2S use case. -- ------------------------------------------------------------ DO_MM2S_CASE : if (C_IS_MM2S = 1) generate begin mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE end generate DO_MM2S_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: DO_S2MM_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the S2MM use case. -- ------------------------------------------------------------ DO_S2MM_CASE : if (C_IS_MM2S = 0) generate begin mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE end generate DO_S2MM_CASE; -- Store and Forward Support Start Offset (used by Packer/Unpacker logic) mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX); -- Start internal logic. -- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines) sig_cmd_user_slice <= cache2mstr_command(7 downto 4); sig_cmd_cache_slice <= cache2mstr_command(3 downto 0); sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX); sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX); sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX); sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX); sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX); sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX); -- Check for a zero length BTT (error condition) sig_btt_is_zero <= '1' when (sig_cmd_btt_slice = BTT_ZEROS) Else '0'; sig_xfer_size <= SIZE_TO_USE; ----------------------------------------------------------------- -- Reset fanout control ----------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RESET_REG -- -- Process Description: -- Registers the input reset to reduce fanout. This module -- has a high number of register bits to reset. -- ------------------------------------------------------------- IMP_RESET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_reset_reg <= mmap_reset; end if; end process IMP_RESET_REG; ----------------------------------------------------------------- -- Input xfer register design sig_push_input_reg <= not(sig_sm_halt_reg) and cmd2mstr_cmd_valid and sig_input_reg_empty and not(sig_calc_error_reg); sig_pop_input_reg <= sig_sm_pop_input_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_INPUT_QUAL -- -- Process Description: -- Implements the input command qualifier holding register -- ------------------------------------------------------------- REG_INPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_input_reg = '1' or sig_calc_error_pushed = '1') then sig_input_cache_type_reg <= (others => '0'); sig_input_user_type_reg <= (others => '0'); sig_input_burst_type_reg <= '0'; sig_input_tag_reg <= (others => '0'); sig_input_dsa_reg <= (others => '0'); sig_input_drr_reg <= '0'; sig_input_eof_reg <= '0'; sig_input_reg_empty <= '1'; sig_input_reg_full <= '0'; elsif (sig_push_input_reg = '1') then sig_input_cache_type_reg <= sig_cmd_cache_slice; sig_input_user_type_reg <= sig_cmd_user_slice; sig_input_burst_type_reg <= sig_cmd_type_slice; sig_input_tag_reg <= sig_cmd_tag_slice; sig_input_dsa_reg <= sig_cmd_dsa_slice; sig_input_drr_reg <= sig_cmd_drr_slice; sig_input_eof_reg <= sig_cmd_eof_slice; sig_input_reg_empty <= '0'; sig_input_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_INPUT_QUAL; ---------------------------------------------------------------------- -- Calculation Error Logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_FLOP -- -- Process Description: -- Implements the flop for the Calc Error flag, Once set, -- the flag cannot be cleared until a reset is issued. -- ------------------------------------------------------------- IMP_CALC_ERROR_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_reg <= '0'; elsif (sig_push_input_reg = '1' and sig_calc_error_reg = '0') then sig_calc_error_reg <= sig_btt_is_zero; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_PUSHED -- -- Process Description: -- Implements the flop for generating a flag indicating the -- calculation error flag has been pushed to the addr and data -- controllers. -- ------------------------------------------------------------- IMP_CALC_ERROR_PUSHED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_pushed <= '0'; elsif (sig_push_xfer_reg = '1' and sig_calc_error_pushed = '0') then sig_calc_error_pushed <= sig_calc_error_reg; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_PUSHED; --------------------------------------------------------------------- -- Strobe Generator Logic sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3 When (sig_first_xfer_im0 = '1') Else (others => '1'); sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3 When (sig_xfer_len_eq_0_ireg3 = '1' and sig_first_xfer_im0 = '1') else sig_xfer_end_strb_ireg3 When (sig_last_xfer_valid_im1 = '1') Else (others => '1'); ---------------------------------------------------------- -- Intermediate registers for STBGEN Fmax path ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_REGS -- -- Process Description: -- Intermediate registers for Strobegen inputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_strbgen_addr_ireg2 <= (others => '0'); sig_strbgen_bytes_ireg2 <= (others => '0'); sig_finish_addr_offset_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ; sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ; sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_REGS; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_OUT_REGS -- -- Process Description: -- Intermediate registers for Strobegen outputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_OUT_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_xfer_strt_strb_ireg3 <= (others => '0'); sig_xfer_end_strb_ireg3 <= (others => '0'); sig_xfer_len_eq_0_ireg3 <= '0'; elsif (sig_sm_ld_calc3_reg = '1') then sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2; sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ; sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_OUT_REGS; ------------------------------------------------------------ -- Instance: I_STRT_STRB_GEN -- -- Description: -- Strobe generator instance. Generates strobe bits for -- a designated starting byte lane and the number of bytes -- to be transfered (for that data beat). -- ------------------------------------------------------------ I_STRT_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 0 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1 ) port map ( start_addr_offset => sig_strbgen_addr_ireg2 , end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0 num_valid_bytes => sig_strbgen_bytes_ireg2 , strb_out => sig_xfer_strt_strb_im2 ); -- The ending address offset is 1 less than the calculated -- starting address for the next sequential transfer. sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) - STRBGEN_ADDR_SLICE_1); ------------------------------------------------------------ -- Instance: I_END_STRB_GEN -- -- Description: -- End Strobe generator instance. Generates asserted strobe -- bits from byte offset 0 to the ending byte offset. -- ------------------------------------------------------------ I_END_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 1 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ) port map ( start_addr_offset => STRBGEN_ADDR_0 , end_addr_offset => sig_last_addr_offset_im2 , num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1 strb_out => sig_xfer_end_strb_im2 ); ----------------------------------------------------------------- -- Output xfer register design sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty); -- Data taking xfer after Addr and DRE sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or -- Addr taking xfer after Data and DRE (sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or -- DRE taking xfer after Data and ADDR (sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or -- data and Addr taking xfer after DRE (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or -- Addr and DRE taking xfer after Data (sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or -- Data and DRE taking xfer after Addr (sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or -- Addr, Data, and DRE all taking xfer (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_OUTPUT_QUAL -- -- Process Description: -- Implements the output xfer qualifier holding register -- ------------------------------------------------------------- REG_OUTPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or (sig_pop_xfer_reg = '1' and sig_push_xfer_reg = '0')) then -- sig_xfer_cache_reg <= (others => '0'); -- sig_xfer_user_reg <= (others => '0'); -- sig_xfer_addr_reg <= (others => '0'); -- sig_xfer_type_reg <= '0'; -- sig_xfer_len_reg <= (others => '0'); -- sig_xfer_tag_reg <= (others => '0'); -- sig_xfer_dsa_reg <= (others => '0'); -- sig_xfer_drr_reg <= '0'; -- sig_xfer_eof_reg <= '0'; -- sig_xfer_strt_strb_reg <= (others => '0'); -- sig_xfer_end_strb_reg <= (others => '0'); -- sig_xfer_is_seq_reg <= '0'; -- sig_xfer_cmd_cmplt_reg <= '0'; -- sig_xfer_calc_err_reg <= '0'; -- sig_xfer_btt_reg <= (others => '0'); -- sig_xfer_dre_eof_reg <= '0'; sig_xfer_reg_empty <= '1'; sig_xfer_reg_full <= '0'; elsif (sig_push_xfer_reg = '1') then -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else -- sig_xfer_addr_reg <= sig_xfer_address_im0 ; -- end if; -- sig_xfer_type_reg <= sig_input_burst_type_reg ; -- sig_xfer_cache_reg <= sig_input_cache_type_reg ; -- sig_xfer_user_reg <= sig_input_user_type_reg ; -- sig_xfer_len_reg <= sig_xfer_len_im2 ; -- sig_xfer_tag_reg <= sig_input_tag_reg ; -- sig_xfer_dsa_reg <= sig_input_dsa_reg ; -- sig_xfer_drr_reg <= sig_input_drr_reg and -- sig_first_xfer_im0 ; -- sig_xfer_eof_reg <= sig_input_eof_reg and -- sig_last_xfer_valid_im1 ; -- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; -- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; -- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; -- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or -- sig_calc_error_reg ; -- sig_xfer_calc_err_reg <= sig_calc_error_reg ; -- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; -- sig_xfer_dre_eof_reg <= sig_input_eof_reg ; sig_xfer_reg_empty <= '0'; sig_xfer_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_OUTPUT_QUAL; -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else sig_addr_cntr_lsh_kh ; -- end if; sig_xfer_type_reg <= sig_input_burst_type_reg ; sig_xfer_cache_reg <= sig_input_cache_type_reg ; sig_xfer_user_reg <= sig_input_user_type_reg ; sig_xfer_len_reg <= sig_xfer_len_im2 ; sig_xfer_tag_reg <= sig_input_tag_reg ; sig_xfer_dsa_reg <= sig_input_dsa_reg ; sig_xfer_drr_reg <= sig_input_drr_reg and sig_first_xfer_im0 ; sig_xfer_eof_reg <= sig_input_eof_reg and sig_last_xfer_valid_im1 ; sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or sig_calc_error_reg ; sig_xfer_calc_err_reg <= sig_calc_error_reg ; sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; sig_xfer_dre_eof_reg <= sig_input_eof_reg ; -------------------------------------------------------------- -- BTT Counter Logic sig_ld_btt_cntr <= sig_ld_addr_cntr; -- sig_decr_btt_cntr <= sig_incr_addr_cntr; -- above signal is using the incr_addr_cntr signal and hence cannot be -- used if burst type is Fixed sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_CNTR -- -- Process Description: -- Bytes to transfer counter implementation. -- ------------------------------------------------------------- IMP_BTT_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_btt_cntr_im0 <= (others => '0'); elsif (sig_ld_btt_cntr = '1') then sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice); Elsif (sig_decr_btt_cntr = '1') Then sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH); else null; -- hold current state end if; end if; end process IMP_BTT_CNTR; -- Convert to logic vector for the S2MM DRE use -- The DRE will only use this value prior to the first -- decrement of the BTT Counter. Using this saves a separate -- BTT register. sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0); -- Rip the Burst Count slice from BTT counter value sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX); sig_brst_cnt_eq_zero_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_0) Else '0'; sig_brst_cnt_eq_one_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_1) Else '0'; -- Rip the BTT residue field from the BTT counter value sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0); -- Check for transfer length residue of zero prior to subtracting 1 sig_no_btt_residue_im0 <= '1' when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Unaligned address compensation -- Add the number of starting address offset byte positions to the -- final byte change value needed to calculate the AXI LEN field sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0); sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 + RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH); -- adjust the address increment down by 1 byte to compensate -- for the LEN requirement of being N-1 data beats sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE; -- Rip the new transfer length value sig_xfer_len_im2 <= STD_LOGIC_VECTOR( RESIZE( sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto DBEAT_RESIDUE_WIDTH), LEN_WIDTH) ); -- Check to see if the new xfer length is zero (1 data beat) sig_xfer_len_eq_0_im2 <= '1' when (sig_xfer_len_im2 = XFER_LEN_ZERO) Else '0'; -- Check for Last transfer condition --sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and --sig_no_btt_residue_im0 and sig_no_btt_residue_ireg1 and -- sig_addr_aligned_im0) or -- always the last databeat case sig_addr_aligned_ireg1) or -- always the last databeat case -- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining ((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining -- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0))); (sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1))); ---------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------- -- -- General Address Counter Logic (applies to any address width of 32 or greater -- The address counter is divided into 2 16-bit segements for 32-bit address support. As the -- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit -- addressing. -- ---------------------------------------------------------------------------------------------------- -- Rip the LS bits of the LS Address Counter for the StrobeGen -- starting address offset sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); -- Check if the calcualted address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat sig_addr_incr_ge_bpdb_im1 <= '1' When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH)) Else '0'; -- If the calculated address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat, then clip the -- strobegen byte value to the number of bytes per data beat, else use the -- increment value. sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1)) when (sig_addr_incr_ge_bpdb_im1 = '1') else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0)); -------------------------------------------------------------------------- -- Address Counter logic sig_ld_addr_cntr <= sig_push_input_reg; -- don't increment address cntr if type is '0' (non-incrementing) sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and -- sig_input_burst_type_reg; sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0); sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) - RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH); sig_addr_aligned_im0 <= '1' when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less -- than or equal to the remaining bytes to transfer. If it is, then at least -- two tranfers have to be scheduled. sig_btt_lt_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; sig_btt_eq_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_REG1 -- -- Process Description: -- Intermediate register stage 1 for Address Counter -- derivative calculations. -- ------------------------------------------------------------- IMP_IM_REG1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_bytes_to_mbaa_ireg1 <= (others => '0'); sig_addr_aligned_ireg1 <= '0' ; sig_btt_lt_b2mbaa_ireg1 <= '0' ; sig_btt_eq_b2mbaa_ireg1 <= '0' ; sig_brst_cnt_eq_zero_ireg1 <= '0' ; sig_brst_cnt_eq_one_ireg1 <= '0' ; sig_no_btt_residue_ireg1 <= '0' ; elsif (sig_sm_ld_calc1_reg = '1') then sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ; sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ; sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ; sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ; sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0; sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ; sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ; else null; -- hold state end if; end if; end process IMP_IM_REG1; -- Select the address counter increment value to use sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) --When (sig_btt_lt_b2mbaa_im0 = '1') When (sig_btt_lt_b2mbaa_ireg1 = '1') --else sig_bytes_to_mbaa_im0 else sig_bytes_to_mbaa_ireg1 when (sig_first_xfer_im0 = '1') else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH); -- calculate the next starting address after the current -- xfer completes sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1; -- Predict next transfer's address offset for the Strobe Generator sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- Determine if an address count lsh rollover is going to occur when -- jumping to the next starting address by comparing the MS bit of the -- current address lsh to the MS bit of the predicted address lsh . -- A transition of a '1' to a '0' is a rollover. sig_addr_lsh_rollover_im3 <= '1' when ( (sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and (sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0') ) Else '0'; ---------------------------------------------------------- -- Intermediate registers for reducing the Address Counter -- Increment timing path ---------------------------------------------------------- -- calculate the next starting address after the current -- xfer completes using intermediate register values sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2; sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_ADDRINC_REG -- -- Process Description: -- Intermediate registers for address counter increment to -- break long timing paths. -- ------------------------------------------------------------- IMP_IM_ADDRINC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1; else null; -- hold state end if; end if; end process IMP_IM_ADDRINC_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_PREDICT_ADDR_REG -- -- Process Description: -- Intermediate register for predicted address to break up -- long timing paths. -- ------------------------------------------------------------- IMP_IM_PREDICT_ADDR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_predict_addr_lsh_ireg3 <= (others => '0'); elsif (sig_sm_ld_calc3_reg = '1') then sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2; else null; -- hold state end if; end if; end process IMP_IM_PREDICT_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_ADDR_STUFF -- -- Process Description: -- Implements a general register for address counter related -- things. -- ------------------------------------------------------------- REG_ADDR_STUFF : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_adjusted_addr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1; else null; -- hold state end if; end if; end process REG_ADDR_STUFF; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_LSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_LSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_lsh_im0 <= (others => '0'); sig_addr_cntr_lsh_kh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0)); sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice; Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3; else null; -- hold current state end if; end if; end process IMP_LSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_MSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_im0_msh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1') then sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE; else null; -- hold current state end if; end if; end process IMP_MSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIRST_XFER_FLOP -- -- Process Description: -- Implements the register flop for the first transfer flag. -- ------------------------------------------------------------- IMP_FIRST_XFER_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_incr_addr_cntr = '1') then sig_first_xfer_im0 <= '0'; elsif (sig_ld_addr_cntr = '1') then sig_first_xfer_im0 <= '1'; else null; -- hold current state end if; end if; end process IMP_FIRST_XFER_FLOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_32 -- -- If Generate Description: -- Implements the Address segment merge logic for the 32-bit -- address width case. The address counter segments are split -- into two 16-bit sections to improve Fmax convergence. -- -- ------------------------------------------------------------ GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate begin -- Populate the transfer address value by concatonating the -- address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); end generate GEN_ADDR_32; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_32_LE_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 32 bits and less than -- or equal to 48 bits. In this case, an additional counter segment -- is implemented (segment 3) that is variable width of 1 -- to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and C_ADDR_WIDTH <= 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; begin -- Populate the transfer address value by concatonating the -- 3 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Adress Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter MSH (Segment 2) is at max value and will rollover -- at the next increment interval for the counter. Registering -- this signal and using it for the Seg 3 increment logic only -- works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 counter to go to -- max and the next increment operation that can bump segment 3. -- ------------------------------------------------------------- IMP_SEG2_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; end if; end if; end process IMP_SEG2_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; end generate GEN_ADDR_GT_32_LE_48; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 48 bits and less than -- or equal to 64. In this case, an additional 2 counter segments -- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits -- and segment 4 is variable width of 1 to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48; Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH); Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; signal lsig_acntr_seg3_eq_max : std_logic := '0'; signal lsig_acntr_seg3_eq_max_reg : std_logic := '0'; signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0'); begin -- Populate the transfer address value by concatonating the -- 4 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) & STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Address Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; -- See if the Segment 3 of the Address Counter is at a max value lsig_acntr_seg3_eq_max <= '1' when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_3_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter segments 2 and 3 are at max value and will rollover -- at the next increment interval for the counter. Registering -- these signals and using themt for the Seg 3/4 increment logic -- only works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 or 3 counter to go -- to max and the next increment operation. -- ------------------------------------------------------------- IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; lsig_acntr_seg3_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max; end if; end if; end process IMP_SEG2_3_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG4_ADDR_CNTR -- -- Process Description: -- Segment 4 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG4_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg4_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto SEG4_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1' and lsig_acntr_seg3_eq_max_reg = '1') then lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE; else null; -- hold current state end if; end if; end process IMP_SEG4_ADDR_CNTR; end generate GEN_ADDR_GT_48; -- Addr and data Cntlr FIFO interface handshake logic ------------------------------ sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready; sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready; sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DATA_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Data Controller Module. -- ------------------------------------------------------------- CMD2DATA_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2data_valid = '1') then sig_cmd2data_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2data_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DATA_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2ADDR_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Address Controller Module. -- ------------------------------------------------------------- CMD2ADDR_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2addr_valid = '1') then sig_cmd2addr_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2addr_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2ADDR_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DRE_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the DRE Module (S2MM DRE Only). -- -- Note that the S2MM DRE only needs to be loaded with a command -- for each parent command, not every child command. -- ------------------------------------------------------------- CMD2DRE_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2dre_valid = '1') then sig_cmd2dre_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1' and sig_first_xfer_im0 = '1') then sig_cmd2dre_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DRE_VALID_FLOP; ------------------------------------------------------------------------- -- PCC State machine Logic ------------------------------------------------------------- -- Combinational Process -- -- Label: PCC_SM_COMBINATIONAL -- -- Process Description: -- PCC State Machine combinational implementation -- ------------------------------------------------------------- PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state , sig_parent_done , sig_push_input_reg , sig_pop_xfer_reg , sig_calc_error_pushed) begin -- SM Defaults sig_pcc_sm_state_ns <= INIT; sig_sm_halt_ns <= '0'; sig_sm_ld_xfer_reg_ns <= '0'; sig_sm_pop_input_reg_ns <= '0'; sig_sm_ld_calc1_reg_ns <= '0'; sig_sm_ld_calc2_reg_ns <= '0'; sig_sm_ld_calc3_reg_ns <= '0'; case sig_pcc_sm_state is -------------------------------------------- when INIT => sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_halt_ns <= '1'; -------------------------------------------- when WAIT_FOR_CMD => If (sig_push_input_reg = '1') Then sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; else sig_pcc_sm_state_ns <= WAIT_FOR_CMD; End if; -------------------------------------------- when CALC_1 => sig_pcc_sm_state_ns <= CALC_2; sig_sm_ld_calc2_reg_ns <= '1'; -------------------------------------------- when CALC_2 => sig_pcc_sm_state_ns <= CALC_3; sig_sm_ld_calc3_reg_ns <= '1'; -------------------------------------------- when CALC_3 => sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; sig_sm_ld_xfer_reg_ns <= '1'; -------------------------------------------- when WAIT_ON_XFER_PUSH => if (sig_pop_xfer_reg = '1') then sig_pcc_sm_state_ns <= CHK_IF_DONE; else -- wait until output register is loaded sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; end if; -------------------------------------------- when CHK_IF_DONE => If (sig_calc_error_pushed = '1') then -- Internal error, go to trap sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; elsif (sig_parent_done = '1') Then -- done with parent command sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_pop_input_reg_ns <= '1'; else -- Still breaking up parent command sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; end if; -------------------------------------------- when ERROR_TRAP => sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; -------------------------------------------- when others => sig_pcc_sm_state_ns <= INIT; end case; end process PCC_SM_COMBINATIONAL; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PCC_SM_REGISTERED -- -- Process Description: -- PCC State Machine registered implementation -- ------------------------------------------------------------- PCC_SM_REGISTERED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_pcc_sm_state <= INIT; sig_sm_halt_reg <= '1' ; sig_sm_pop_input_reg <= '0' ; sig_sm_ld_calc1_reg <= '0' ; sig_sm_ld_calc2_reg <= '0' ; sig_sm_ld_calc3_reg <= '0' ; else sig_pcc_sm_state <= sig_pcc_sm_state_ns ; sig_sm_halt_reg <= sig_sm_halt_ns ; sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns; sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ; sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ; sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ; end if; end if; end process PCC_SM_REGISTERED; ------------------------------------------------------------------ -- Transfer Register Load Enable logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: LD_XFER_REG_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- LD_XFER_REG_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_xfer_reg = '1') then sig_ld_xfer_reg <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP; LD_XFER_REG_FLOP1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_xfer_reg = '1') then sig_ld_xfer_reg_tmp <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg_tmp <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP1; ------------------------------------------------------------------ -- Parent Done flag logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PARENT_DONE_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- PARENT_DONE_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_input_reg = '1') then sig_parent_done <= '0'; Elsif (sig_ld_xfer_reg_tmp = '1') Then sig_parent_done <= sig_last_xfer_valid_im1; else null; -- hold current state end if; end if; end process PARENT_DONE_FLOP; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_1_data_stream_1_V.vhd	4	4629	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_1_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_1_data_stream_1_V_shiftReg; architecture rtl of FIFO_image_filter_img_1_data_stream_1_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_1_data_stream_1_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_1_data_stream_1_V is component FIFO_image_filter_img_1_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_1_data_stream_1_V_shiftReg : FIFO_image_filter_img_1_data_stream_1_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_src0_data_stream_0_V.vhd	2	4621	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_src0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_src0_data_stream_0_V_shiftReg; architecture rtl of FIFO_image_filter_src0_data_stream_0_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_src0_data_stream_0_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_src0_data_stream_0_V is component FIFO_image_filter_src0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_src0_data_stream_0_V_shiftReg : FIFO_image_filter_src0_data_stream_0_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_src0_data_stream_0_V.vhd	2	4621	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_src0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_src0_data_stream_0_V_shiftReg; architecture rtl of FIFO_image_filter_src0_data_stream_0_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_src0_data_stream_0_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_src0_data_stream_0_V is component FIFO_image_filter_src0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_src0_data_stream_0_V_shiftReg : FIFO_image_filter_src0_data_stream_0_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/lite_ecc_reg.vhd	7	68156	------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- * AXI-Lite ECC Register Interface Signals * -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- * Memory Controller Interface Signals * -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/image_filter.vhd	2	183530	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter is port ( INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0); INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0); INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0); INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0); rows : IN STD_LOGIC_VECTOR (31 downto 0); cols : IN STD_LOGIC_VECTOR (31 downto 0); ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; ap_start : IN STD_LOGIC; INPUT_STREAM_TVALID : IN STD_LOGIC; INPUT_STREAM_TREADY : OUT STD_LOGIC; OUTPUT_STREAM_TVALID : OUT STD_LOGIC; OUTPUT_STREAM_TREADY : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC ); end; architecture behav of image_filter is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "image_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.666670,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=6.112860,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=59,HLS_SYN_DSP=3,HLS_SYN_FF=7667,HLS_SYN_LUT=13162}"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_true : BOOLEAN := true; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_const_logic_1 : STD_LOGIC := '1'; signal ap_rst_n_inv : STD_LOGIC; signal image_filter_Block_proc_U0_ap_start : STD_LOGIC; signal image_filter_Block_proc_U0_ap_done : STD_LOGIC; signal image_filter_Block_proc_U0_ap_continue : STD_LOGIC; signal image_filter_Block_proc_U0_ap_idle : STD_LOGIC; signal image_filter_Block_proc_U0_ap_ready : STD_LOGIC; signal image_filter_Block_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0); signal image_filter_Block_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0); signal image_filter_Block_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_4 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_5 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_6 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_7 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_8 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_9 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_10 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_11 : STD_LOGIC_VECTOR (11 downto 0); signal ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel : STD_LOGIC; signal p_dst_cols_V_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_dst_cols_V_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_dst_cols_V_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_full_n : STD_LOGIC; signal ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel : STD_LOGIC; signal p_src_cols_V_2_loc_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_src_cols_V_2_loc_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_cols_V_2_loc_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_full_n : STD_LOGIC; signal ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel : STD_LOGIC; signal p_src_rows_V_2_loc_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_src_rows_V_2_loc_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_rows_V_2_loc_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel : STD_LOGIC; signal p_src_cols_V_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_src_cols_V_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_cols_V_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V : STD_LOGIC; signal p_dst_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_p_dst_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_dst_cols_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel : STD_LOGIC; signal p_dst_rows_V_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_dst_rows_V_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_dst_rows_V_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V : STD_LOGIC; signal p_dst_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_p_dst_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_dst_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel : STD_LOGIC; signal p_src_rows_V_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_src_rows_V_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_rows_V_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 : STD_LOGIC; signal p_src_rows_V_channel1_full_n : STD_LOGIC; signal ap_reg_ready_p_src_rows_V_channel1_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_rows_V_channel1_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 : STD_LOGIC; signal p_src_cols_V_channel1_full_n : STD_LOGIC; signal ap_reg_ready_p_src_cols_V_channel1_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_cols_V_channel1_full_n : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_start : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_done : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_continue : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_idle : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_ready : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_start : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_done : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_continue : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_idle : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_ready : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_read2 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_read16 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_read17 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_4 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_5 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_6 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_7 : STD_LOGIC_VECTOR (11 downto 0); signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V : STD_LOGIC; signal src0_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_src0_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_src0_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V : STD_LOGIC; signal src0_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_src0_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_src0_cols_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V : STD_LOGIC; signal src1_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_src1_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_src1_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V : STD_LOGIC; signal src1_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_src1_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_src1_cols_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V : STD_LOGIC; signal mask_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_mask_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_mask_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V : STD_LOGIC; signal mask_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_mask_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_mask_cols_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V : STD_LOGIC; signal dmask_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_dmask_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_dmask_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V : STD_LOGIC; signal dmask_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_dmask_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_dmask_cols_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_start : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_done : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_continue : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_idle : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_ready : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_p_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_p_read2 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_p_read6 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_p_read7 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0); signal ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V : STD_LOGIC; signal gray_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_gray_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_gray_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V : STD_LOGIC; signal gray_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_gray_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_gray_cols_V_full_n : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_start : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_done : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_continue : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_idle : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_ready : STD_LOGIC; signal image_filter_FAST_t_opr_U0_p_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_FAST_t_opr_U0_p_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_FAST_t_opr_U0_p_src_data_stream_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_FAST_t_opr_U0_p_src_data_stream_V_empty_n : STD_LOGIC; signal image_filter_FAST_t_opr_U0_p_src_data_stream_V_read : STD_LOGIC; signal image_filter_FAST_t_opr_U0_p_mask_data_stream_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_FAST_t_opr_U0_p_mask_data_stream_V_full_n : STD_LOGIC; signal image_filter_FAST_t_opr_U0_p_mask_data_stream_V_write : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_start : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_done : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_continue : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_idle : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_ready : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_p_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Dilate_0_0_1080_1920_U0_p_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_empty_n : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_read : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_full_n : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_write : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_start : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_done : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_continue : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_idle : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_ready : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_empty_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_read : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_empty_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_read : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_empty_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_read : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_empty_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_read : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_write : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_full_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_write : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_full_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_write : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_start : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_done : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_continue : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_idle : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_ready : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_hs_continue : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_U_ap_dummy_ce : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_2_loc_channel1_write : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_2_loc_channel1_empty_n : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_read : STD_LOGIC; signal p_src_cols_V_2_loc_channel_U_ap_dummy_ce : STD_LOGIC; signal p_src_cols_V_2_loc_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_2_loc_channel_write : STD_LOGIC; signal p_src_cols_V_2_loc_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_2_loc_channel_empty_n : STD_LOGIC; signal p_src_cols_V_2_loc_channel_read : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_U_ap_dummy_ce : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_2_loc_channel1_write : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_2_loc_channel1_empty_n : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_read : STD_LOGIC; signal p_src_rows_V_2_loc_channel_U_ap_dummy_ce : STD_LOGIC; signal p_src_rows_V_2_loc_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_2_loc_channel_write : STD_LOGIC; signal p_src_rows_V_2_loc_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_2_loc_channel_empty_n : STD_LOGIC; signal p_src_rows_V_2_loc_channel_read : STD_LOGIC; signal p_dst_cols_V_channel_U_ap_dummy_ce : STD_LOGIC; signal p_dst_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_cols_V_channel_write : STD_LOGIC; signal p_dst_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_cols_V_channel_empty_n : STD_LOGIC; signal p_dst_cols_V_channel_read : STD_LOGIC; signal p_dst_cols_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_cols_V_write : STD_LOGIC; signal p_dst_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_cols_V_empty_n : STD_LOGIC; signal p_dst_cols_V_read : STD_LOGIC; signal p_dst_rows_V_channel_U_ap_dummy_ce : STD_LOGIC; signal p_dst_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_rows_V_channel_write : STD_LOGIC; signal p_dst_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_rows_V_channel_empty_n : STD_LOGIC; signal p_dst_rows_V_channel_read : STD_LOGIC; signal p_dst_rows_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_rows_V_write : STD_LOGIC; signal p_dst_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_rows_V_empty_n : STD_LOGIC; signal p_dst_rows_V_read : STD_LOGIC; signal p_src_cols_V_channel_U_ap_dummy_ce : STD_LOGIC; signal p_src_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_channel_write : STD_LOGIC; signal p_src_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_channel_empty_n : STD_LOGIC; signal p_src_cols_V_channel_read : STD_LOGIC; signal p_src_rows_V_channel_U_ap_dummy_ce : STD_LOGIC; signal p_src_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_channel_write : STD_LOGIC; signal p_src_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_channel_empty_n : STD_LOGIC; signal p_src_rows_V_channel_read : STD_LOGIC; signal p_src_rows_V_channel1_U_ap_dummy_ce : STD_LOGIC; signal p_src_rows_V_channel1_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_channel1_write : STD_LOGIC; signal p_src_rows_V_channel1_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_channel1_empty_n : STD_LOGIC; signal p_src_rows_V_channel1_read : STD_LOGIC; signal p_src_cols_V_channel1_U_ap_dummy_ce : STD_LOGIC; signal p_src_cols_V_channel1_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_channel1_write : STD_LOGIC; signal p_src_cols_V_channel1_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_channel1_empty_n : STD_LOGIC; signal p_src_cols_V_channel1_read : STD_LOGIC; signal p_src_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal p_src_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_0_V_full_n : STD_LOGIC; signal p_src_data_stream_0_V_write : STD_LOGIC; signal p_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_0_V_empty_n : STD_LOGIC; signal p_src_data_stream_0_V_read : STD_LOGIC; signal p_src_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC; signal p_src_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_1_V_full_n : STD_LOGIC; signal p_src_data_stream_1_V_write : STD_LOGIC; signal p_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_1_V_empty_n : STD_LOGIC; signal p_src_data_stream_1_V_read : STD_LOGIC; signal p_src_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC; signal p_src_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_2_V_full_n : STD_LOGIC; signal p_src_data_stream_2_V_write : STD_LOGIC; signal p_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_2_V_empty_n : STD_LOGIC; signal p_src_data_stream_2_V_read : STD_LOGIC; signal src0_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal src0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_0_V_full_n : STD_LOGIC; signal src0_data_stream_0_V_write : STD_LOGIC; signal src0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_0_V_empty_n : STD_LOGIC; signal src0_data_stream_0_V_read : STD_LOGIC; signal src0_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC; signal src0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_1_V_full_n : STD_LOGIC; signal src0_data_stream_1_V_write : STD_LOGIC; signal src0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_1_V_empty_n : STD_LOGIC; signal src0_data_stream_1_V_read : STD_LOGIC; signal src0_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC; signal src0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_2_V_full_n : STD_LOGIC; signal src0_data_stream_2_V_write : STD_LOGIC; signal src0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_2_V_empty_n : STD_LOGIC; signal src0_data_stream_2_V_read : STD_LOGIC; signal src1_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal src1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_0_V_full_n : STD_LOGIC; signal src1_data_stream_0_V_write : STD_LOGIC; signal src1_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_0_V_empty_n : STD_LOGIC; signal src1_data_stream_0_V_read : STD_LOGIC; signal src1_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC; signal src1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_1_V_full_n : STD_LOGIC; signal src1_data_stream_1_V_write : STD_LOGIC; signal src1_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_1_V_empty_n : STD_LOGIC; signal src1_data_stream_1_V_read : STD_LOGIC; signal src1_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC; signal src1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_2_V_full_n : STD_LOGIC; signal src1_data_stream_2_V_write : STD_LOGIC; signal src1_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_2_V_empty_n : STD_LOGIC; signal src1_data_stream_2_V_read : STD_LOGIC; signal src0_rows_V_U_ap_dummy_ce : STD_LOGIC; signal src0_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal src0_rows_V_write : STD_LOGIC; signal src0_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal src0_rows_V_empty_n : STD_LOGIC; signal src0_rows_V_read : STD_LOGIC; signal src0_cols_V_U_ap_dummy_ce : STD_LOGIC; signal src0_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal src0_cols_V_write : STD_LOGIC; signal src0_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal src0_cols_V_empty_n : STD_LOGIC; signal src0_cols_V_read : STD_LOGIC; signal src1_rows_V_U_ap_dummy_ce : STD_LOGIC; signal src1_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal src1_rows_V_write : STD_LOGIC; signal src1_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal src1_rows_V_empty_n : STD_LOGIC; signal src1_rows_V_read : STD_LOGIC; signal src1_cols_V_U_ap_dummy_ce : STD_LOGIC; signal src1_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal src1_cols_V_write : STD_LOGIC; signal src1_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal src1_cols_V_empty_n : STD_LOGIC; signal src1_cols_V_read : STD_LOGIC; signal mask_rows_V_U_ap_dummy_ce : STD_LOGIC; signal mask_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal mask_rows_V_write : STD_LOGIC; signal mask_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal mask_rows_V_empty_n : STD_LOGIC; signal mask_rows_V_read : STD_LOGIC; signal mask_cols_V_U_ap_dummy_ce : STD_LOGIC; signal mask_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal mask_cols_V_write : STD_LOGIC; signal mask_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal mask_cols_V_empty_n : STD_LOGIC; signal mask_cols_V_read : STD_LOGIC; signal dmask_rows_V_U_ap_dummy_ce : STD_LOGIC; signal dmask_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal dmask_rows_V_write : STD_LOGIC; signal dmask_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal dmask_rows_V_empty_n : STD_LOGIC; signal dmask_rows_V_read : STD_LOGIC; signal dmask_cols_V_U_ap_dummy_ce : STD_LOGIC; signal dmask_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal dmask_cols_V_write : STD_LOGIC; signal dmask_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal dmask_cols_V_empty_n : STD_LOGIC; signal dmask_cols_V_read : STD_LOGIC; signal gray_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal gray_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal gray_data_stream_0_V_full_n : STD_LOGIC; signal gray_data_stream_0_V_write : STD_LOGIC; signal gray_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal gray_data_stream_0_V_empty_n : STD_LOGIC; signal gray_data_stream_0_V_read : STD_LOGIC; signal gray_rows_V_U_ap_dummy_ce : STD_LOGIC; signal gray_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal gray_rows_V_write : STD_LOGIC; signal gray_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal gray_rows_V_empty_n : STD_LOGIC; signal gray_rows_V_read : STD_LOGIC; signal gray_cols_V_U_ap_dummy_ce : STD_LOGIC; signal gray_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal gray_cols_V_write : STD_LOGIC; signal gray_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal gray_cols_V_empty_n : STD_LOGIC; signal gray_cols_V_read : STD_LOGIC; signal mask_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal mask_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal mask_data_stream_0_V_full_n : STD_LOGIC; signal mask_data_stream_0_V_write : STD_LOGIC; signal mask_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal mask_data_stream_0_V_empty_n : STD_LOGIC; signal mask_data_stream_0_V_read : STD_LOGIC; signal dmask_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal dmask_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal dmask_data_stream_0_V_full_n : STD_LOGIC; signal dmask_data_stream_0_V_write : STD_LOGIC; signal dmask_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal dmask_data_stream_0_V_empty_n : STD_LOGIC; signal dmask_data_stream_0_V_read : STD_LOGIC; signal p_dst_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_0_V_full_n : STD_LOGIC; signal p_dst_data_stream_0_V_write : STD_LOGIC; signal p_dst_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_0_V_empty_n : STD_LOGIC; signal p_dst_data_stream_0_V_read : STD_LOGIC; signal p_dst_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_1_V_full_n : STD_LOGIC; signal p_dst_data_stream_1_V_write : STD_LOGIC; signal p_dst_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_1_V_empty_n : STD_LOGIC; signal p_dst_data_stream_1_V_read : STD_LOGIC; signal p_dst_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_2_V_full_n : STD_LOGIC; signal p_dst_data_stream_2_V_write : STD_LOGIC; signal p_dst_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_2_V_empty_n : STD_LOGIC; signal p_dst_data_stream_2_V_read : STD_LOGIC; signal ap_reg_procdone_image_filter_Block_proc_U0 : STD_LOGIC := '0'; signal ap_sig_hs_done : STD_LOGIC; signal ap_reg_procdone_image_filter_AXIvideo2Mat_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_FAST_t_opr_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_Mat2AXIvideo_U0 : STD_LOGIC := '0'; signal ap_CS : STD_LOGIC; signal ap_sig_top_allready : STD_LOGIC; component image_filter_Block_proc IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; rows : IN STD_LOGIC_VECTOR (31 downto 0); cols : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_4 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_5 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_6 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_7 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_8 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_9 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_10 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_11 : OUT STD_LOGIC_VECTOR (11 downto 0) ); end component; component image_filter_AXIvideo2Mat IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0); INPUT_STREAM_TVALID : IN STD_LOGIC; INPUT_STREAM_TREADY : OUT STD_LOGIC; INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0); INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0); INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0); img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); img_data_stream_0_V_full_n : IN STD_LOGIC; img_data_stream_0_V_write : OUT STD_LOGIC; img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); img_data_stream_1_V_full_n : IN STD_LOGIC; img_data_stream_1_V_write : OUT STD_LOGIC; img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); img_data_stream_2_V_full_n : IN STD_LOGIC; img_data_stream_2_V_write : OUT STD_LOGIC ); end component; component image_filter_Block_Mat_exit1220_proc1 IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (11 downto 0); p_read2 : IN STD_LOGIC_VECTOR (11 downto 0); p_read16 : IN STD_LOGIC_VECTOR (11 downto 0); p_read17 : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_0_V_empty_n : IN STD_LOGIC; p_src_data_stream_0_V_read : OUT STD_LOGIC; p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_1_V_empty_n : IN STD_LOGIC; p_src_data_stream_1_V_read : OUT STD_LOGIC; p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_2_V_empty_n : IN STD_LOGIC; p_src_data_stream_2_V_read : OUT STD_LOGIC; src0_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_0_V_full_n : IN STD_LOGIC; src0_data_stream_0_V_write : OUT STD_LOGIC; src0_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_1_V_full_n : IN STD_LOGIC; src0_data_stream_1_V_write : OUT STD_LOGIC; src0_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_2_V_full_n : IN STD_LOGIC; src0_data_stream_2_V_write : OUT STD_LOGIC; src1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src1_data_stream_0_V_full_n : IN STD_LOGIC; src1_data_stream_0_V_write : OUT STD_LOGIC; src1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src1_data_stream_1_V_full_n : IN STD_LOGIC; src1_data_stream_1_V_write : OUT STD_LOGIC; src1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src1_data_stream_2_V_full_n : IN STD_LOGIC; src1_data_stream_2_V_write : OUT STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_4 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_5 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_6 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_7 : OUT STD_LOGIC_VECTOR (11 downto 0) ); end component; component image_filter_Block_Mat_exit1222_proc1 IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (11 downto 0); p_read2 : IN STD_LOGIC_VECTOR (11 downto 0); p_read6 : IN STD_LOGIC_VECTOR (11 downto 0); p_read7 : IN STD_LOGIC_VECTOR (11 downto 0); src0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_0_V_empty_n : IN STD_LOGIC; src0_data_stream_0_V_read : OUT STD_LOGIC; src0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_1_V_empty_n : IN STD_LOGIC; src0_data_stream_1_V_read : OUT STD_LOGIC; src0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_2_V_empty_n : IN STD_LOGIC; src0_data_stream_2_V_read : OUT STD_LOGIC; gray_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); gray_data_stream_0_V_full_n : IN STD_LOGIC; gray_data_stream_0_V_write : OUT STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0) ); end component; component image_filter_FAST_t_opr IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_V_empty_n : IN STD_LOGIC; p_src_data_stream_V_read : OUT STD_LOGIC; p_mask_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_mask_data_stream_V_full_n : IN STD_LOGIC; p_mask_data_stream_V_write : OUT STD_LOGIC ); end component; component image_filter_Dilate_0_0_1080_1920_s IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_V_empty_n : IN STD_LOGIC; p_src_data_stream_V_read : OUT STD_LOGIC; p_dst_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_V_full_n : IN STD_LOGIC; p_dst_data_stream_V_write : OUT STD_LOGIC ); end component; component image_filter_PaintMask_32_0_1080_1920_s IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_0_V_empty_n : IN STD_LOGIC; p_src_data_stream_0_V_read : OUT STD_LOGIC; p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_1_V_empty_n : IN STD_LOGIC; p_src_data_stream_1_V_read : OUT STD_LOGIC; p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_2_V_empty_n : IN STD_LOGIC; p_src_data_stream_2_V_read : OUT STD_LOGIC; p_mask_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_mask_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_mask_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_mask_data_stream_V_empty_n : IN STD_LOGIC; p_mask_data_stream_V_read : OUT STD_LOGIC; p_dst_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_dst_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_0_V_full_n : IN STD_LOGIC; p_dst_data_stream_0_V_write : OUT STD_LOGIC; p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_1_V_full_n : IN STD_LOGIC; p_dst_data_stream_1_V_write : OUT STD_LOGIC; p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_2_V_full_n : IN STD_LOGIC; p_dst_data_stream_2_V_write : OUT STD_LOGIC ); end component; component image_filter_Mat2AXIvideo IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_0_V_empty_n : IN STD_LOGIC; img_data_stream_0_V_read : OUT STD_LOGIC; img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_1_V_empty_n : IN STD_LOGIC; img_data_stream_1_V_read : OUT STD_LOGIC; img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_2_V_empty_n : IN STD_LOGIC; img_data_stream_2_V_read : OUT STD_LOGIC; OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); OUTPUT_STREAM_TVALID : OUT STD_LOGIC; OUTPUT_STREAM_TREADY : IN STD_LOGIC; OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component FIFO_image_filter_p_src_cols_V_2_loc_channel1 IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_cols_V_2_loc_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_rows_V_2_loc_channel1 IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_rows_V_2_loc_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_cols_V_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_rows_V_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_cols_V_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_rows_V_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_rows_V_channel1 IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_cols_V_channel1 IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_data_stream_1_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_data_stream_2_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_data_stream_1_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_data_stream_2_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_data_stream_1_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_data_stream_2_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_mask_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_mask_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_dmask_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_dmask_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_gray_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_gray_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_gray_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_mask_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_dmask_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_data_stream_1_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_data_stream_2_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; begin image_filter_Block_proc_U0 : component image_filter_Block_proc port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Block_proc_U0_ap_start, ap_done => image_filter_Block_proc_U0_ap_done, ap_continue => image_filter_Block_proc_U0_ap_continue, ap_idle => image_filter_Block_proc_U0_ap_idle, ap_ready => image_filter_Block_proc_U0_ap_ready, rows => image_filter_Block_proc_U0_rows, cols => image_filter_Block_proc_U0_cols, ap_return_0 => image_filter_Block_proc_U0_ap_return_0, ap_return_1 => image_filter_Block_proc_U0_ap_return_1, ap_return_2 => image_filter_Block_proc_U0_ap_return_2, ap_return_3 => image_filter_Block_proc_U0_ap_return_3, ap_return_4 => image_filter_Block_proc_U0_ap_return_4, ap_return_5 => image_filter_Block_proc_U0_ap_return_5, ap_return_6 => image_filter_Block_proc_U0_ap_return_6, ap_return_7 => image_filter_Block_proc_U0_ap_return_7, ap_return_8 => image_filter_Block_proc_U0_ap_return_8, ap_return_9 => image_filter_Block_proc_U0_ap_return_9, ap_return_10 => image_filter_Block_proc_U0_ap_return_10, ap_return_11 => image_filter_Block_proc_U0_ap_return_11); image_filter_AXIvideo2Mat_U0 : component image_filter_AXIvideo2Mat port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_AXIvideo2Mat_U0_ap_start, ap_done => image_filter_AXIvideo2Mat_U0_ap_done, ap_continue => image_filter_AXIvideo2Mat_U0_ap_continue, ap_idle => image_filter_AXIvideo2Mat_U0_ap_idle, ap_ready => image_filter_AXIvideo2Mat_U0_ap_ready, INPUT_STREAM_TDATA => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA, INPUT_STREAM_TVALID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID, INPUT_STREAM_TREADY => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY, INPUT_STREAM_TKEEP => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP, INPUT_STREAM_TSTRB => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB, INPUT_STREAM_TUSER => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER, INPUT_STREAM_TLAST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST, INPUT_STREAM_TID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID, INPUT_STREAM_TDEST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST, img_rows_V_read => image_filter_AXIvideo2Mat_U0_img_rows_V_read, img_cols_V_read => image_filter_AXIvideo2Mat_U0_img_cols_V_read, img_data_stream_0_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din, img_data_stream_0_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n, img_data_stream_0_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write, img_data_stream_1_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din, img_data_stream_1_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n, img_data_stream_1_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write, img_data_stream_2_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din, img_data_stream_2_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n, img_data_stream_2_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write); image_filter_Block_Mat_exit1220_proc1_U0 : component image_filter_Block_Mat_exit1220_proc1 port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Block_Mat_exit1220_proc1_U0_ap_start, ap_done => image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_continue => image_filter_Block_Mat_exit1220_proc1_U0_ap_continue, ap_idle => image_filter_Block_Mat_exit1220_proc1_U0_ap_idle, ap_ready => image_filter_Block_Mat_exit1220_proc1_U0_ap_ready, p_read => image_filter_Block_Mat_exit1220_proc1_U0_p_read, p_read2 => image_filter_Block_Mat_exit1220_proc1_U0_p_read2, p_read16 => image_filter_Block_Mat_exit1220_proc1_U0_p_read16, p_read17 => image_filter_Block_Mat_exit1220_proc1_U0_p_read17, p_src_data_stream_0_V_dout => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_dout, p_src_data_stream_0_V_empty_n => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_empty_n, p_src_data_stream_0_V_read => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_read, p_src_data_stream_1_V_dout => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_dout, p_src_data_stream_1_V_empty_n => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_empty_n, p_src_data_stream_1_V_read => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_read, p_src_data_stream_2_V_dout => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_dout, p_src_data_stream_2_V_empty_n => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_empty_n, p_src_data_stream_2_V_read => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_read, src0_data_stream_0_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_din, src0_data_stream_0_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_full_n, src0_data_stream_0_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_write, src0_data_stream_1_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_din, src0_data_stream_1_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_full_n, src0_data_stream_1_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_write, src0_data_stream_2_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_din, src0_data_stream_2_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_full_n, src0_data_stream_2_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_write, src1_data_stream_0_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_din, src1_data_stream_0_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_full_n, src1_data_stream_0_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_write, src1_data_stream_1_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_din, src1_data_stream_1_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_full_n, src1_data_stream_1_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_write, src1_data_stream_2_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_din, src1_data_stream_2_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_full_n, src1_data_stream_2_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_write, ap_return_0 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_0, ap_return_1 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_1, ap_return_2 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_2, ap_return_3 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_3, ap_return_4 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_4, ap_return_5 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_5, ap_return_6 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_6, ap_return_7 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_7); image_filter_Block_Mat_exit1222_proc1_U0 : component image_filter_Block_Mat_exit1222_proc1 port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Block_Mat_exit1222_proc1_U0_ap_start, ap_done => image_filter_Block_Mat_exit1222_proc1_U0_ap_done, ap_continue => image_filter_Block_Mat_exit1222_proc1_U0_ap_continue, ap_idle => image_filter_Block_Mat_exit1222_proc1_U0_ap_idle, ap_ready => image_filter_Block_Mat_exit1222_proc1_U0_ap_ready, p_read => image_filter_Block_Mat_exit1222_proc1_U0_p_read, p_read2 => image_filter_Block_Mat_exit1222_proc1_U0_p_read2, p_read6 => image_filter_Block_Mat_exit1222_proc1_U0_p_read6, p_read7 => image_filter_Block_Mat_exit1222_proc1_U0_p_read7, src0_data_stream_0_V_dout => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_dout, src0_data_stream_0_V_empty_n => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_empty_n, src0_data_stream_0_V_read => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_read, src0_data_stream_1_V_dout => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_dout, src0_data_stream_1_V_empty_n => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_empty_n, src0_data_stream_1_V_read => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_read, src0_data_stream_2_V_dout => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_dout, src0_data_stream_2_V_empty_n => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_empty_n, src0_data_stream_2_V_read => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_read, gray_data_stream_0_V_din => image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_din, gray_data_stream_0_V_full_n => image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_full_n, gray_data_stream_0_V_write => image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_write, ap_return_0 => image_filter_Block_Mat_exit1222_proc1_U0_ap_return_0, ap_return_1 => image_filter_Block_Mat_exit1222_proc1_U0_ap_return_1); image_filter_FAST_t_opr_U0 : component image_filter_FAST_t_opr port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_FAST_t_opr_U0_ap_start, ap_done => image_filter_FAST_t_opr_U0_ap_done, ap_continue => image_filter_FAST_t_opr_U0_ap_continue, ap_idle => image_filter_FAST_t_opr_U0_ap_idle, ap_ready => image_filter_FAST_t_opr_U0_ap_ready, p_src_rows_V_read => image_filter_FAST_t_opr_U0_p_src_rows_V_read, p_src_cols_V_read => image_filter_FAST_t_opr_U0_p_src_cols_V_read, p_src_data_stream_V_dout => image_filter_FAST_t_opr_U0_p_src_data_stream_V_dout, p_src_data_stream_V_empty_n => image_filter_FAST_t_opr_U0_p_src_data_stream_V_empty_n, p_src_data_stream_V_read => image_filter_FAST_t_opr_U0_p_src_data_stream_V_read, p_mask_data_stream_V_din => image_filter_FAST_t_opr_U0_p_mask_data_stream_V_din, p_mask_data_stream_V_full_n => image_filter_FAST_t_opr_U0_p_mask_data_stream_V_full_n, p_mask_data_stream_V_write => image_filter_FAST_t_opr_U0_p_mask_data_stream_V_write); image_filter_Dilate_0_0_1080_1920_U0 : component image_filter_Dilate_0_0_1080_1920_s port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Dilate_0_0_1080_1920_U0_ap_start, ap_done => image_filter_Dilate_0_0_1080_1920_U0_ap_done, ap_continue => image_filter_Dilate_0_0_1080_1920_U0_ap_continue, ap_idle => image_filter_Dilate_0_0_1080_1920_U0_ap_idle, ap_ready => image_filter_Dilate_0_0_1080_1920_U0_ap_ready, p_src_rows_V_read => image_filter_Dilate_0_0_1080_1920_U0_p_src_rows_V_read, p_src_cols_V_read => image_filter_Dilate_0_0_1080_1920_U0_p_src_cols_V_read, p_src_data_stream_V_dout => image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_dout, p_src_data_stream_V_empty_n => image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_empty_n, p_src_data_stream_V_read => image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_read, p_dst_data_stream_V_din => image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_din, p_dst_data_stream_V_full_n => image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_full_n, p_dst_data_stream_V_write => image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_write); image_filter_PaintMask_32_0_1080_1920_U0 : component image_filter_PaintMask_32_0_1080_1920_s port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_PaintMask_32_0_1080_1920_U0_ap_start, ap_done => image_filter_PaintMask_32_0_1080_1920_U0_ap_done, ap_continue => image_filter_PaintMask_32_0_1080_1920_U0_ap_continue, ap_idle => image_filter_PaintMask_32_0_1080_1920_U0_ap_idle, ap_ready => image_filter_PaintMask_32_0_1080_1920_U0_ap_ready, p_src_rows_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_rows_V_read, p_src_cols_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_cols_V_read, p_src_data_stream_0_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_dout, p_src_data_stream_0_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_empty_n, p_src_data_stream_0_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_read, p_src_data_stream_1_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_dout, p_src_data_stream_1_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_empty_n, p_src_data_stream_1_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_read, p_src_data_stream_2_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_dout, p_src_data_stream_2_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_empty_n, p_src_data_stream_2_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_read, p_mask_rows_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_rows_V_read, p_mask_cols_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_cols_V_read, p_mask_data_stream_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_dout, p_mask_data_stream_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_empty_n, p_mask_data_stream_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_read, p_dst_rows_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_rows_V_read, p_dst_cols_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_cols_V_read, p_dst_data_stream_0_V_din => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_din, p_dst_data_stream_0_V_full_n => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_full_n, p_dst_data_stream_0_V_write => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_write, p_dst_data_stream_1_V_din => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_din, p_dst_data_stream_1_V_full_n => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_full_n, p_dst_data_stream_1_V_write => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_write, p_dst_data_stream_2_V_din => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_din, p_dst_data_stream_2_V_full_n => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_full_n, p_dst_data_stream_2_V_write => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_write); image_filter_Mat2AXIvideo_U0 : component image_filter_Mat2AXIvideo port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Mat2AXIvideo_U0_ap_start, ap_done => image_filter_Mat2AXIvideo_U0_ap_done, ap_continue => image_filter_Mat2AXIvideo_U0_ap_continue, ap_idle => image_filter_Mat2AXIvideo_U0_ap_idle, ap_ready => image_filter_Mat2AXIvideo_U0_ap_ready, img_rows_V_read => image_filter_Mat2AXIvideo_U0_img_rows_V_read, img_cols_V_read => image_filter_Mat2AXIvideo_U0_img_cols_V_read, img_data_stream_0_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout, img_data_stream_0_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n, img_data_stream_0_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read, img_data_stream_1_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout, img_data_stream_1_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n, img_data_stream_1_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read, img_data_stream_2_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout, img_data_stream_2_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n, img_data_stream_2_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read, OUTPUT_STREAM_TDATA => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA, OUTPUT_STREAM_TVALID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID, OUTPUT_STREAM_TREADY => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY, OUTPUT_STREAM_TKEEP => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP, OUTPUT_STREAM_TSTRB => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB, OUTPUT_STREAM_TUSER => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER, OUTPUT_STREAM_TLAST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST, OUTPUT_STREAM_TID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID, OUTPUT_STREAM_TDEST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST); p_src_cols_V_2_loc_channel1_U : component FIFO_image_filter_p_src_cols_V_2_loc_channel1 port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_cols_V_2_loc_channel1_U_ap_dummy_ce, if_write_ce => p_src_cols_V_2_loc_channel1_U_ap_dummy_ce, if_din => p_src_cols_V_2_loc_channel1_din, if_full_n => p_src_cols_V_2_loc_channel1_full_n, if_write => p_src_cols_V_2_loc_channel1_write, if_dout => p_src_cols_V_2_loc_channel1_dout, if_empty_n => p_src_cols_V_2_loc_channel1_empty_n, if_read => p_src_cols_V_2_loc_channel1_read); p_src_cols_V_2_loc_channel_U : component FIFO_image_filter_p_src_cols_V_2_loc_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_cols_V_2_loc_channel_U_ap_dummy_ce, if_write_ce => p_src_cols_V_2_loc_channel_U_ap_dummy_ce, if_din => p_src_cols_V_2_loc_channel_din, if_full_n => p_src_cols_V_2_loc_channel_full_n, if_write => p_src_cols_V_2_loc_channel_write, if_dout => p_src_cols_V_2_loc_channel_dout, if_empty_n => p_src_cols_V_2_loc_channel_empty_n, if_read => p_src_cols_V_2_loc_channel_read); p_src_rows_V_2_loc_channel1_U : component FIFO_image_filter_p_src_rows_V_2_loc_channel1 port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_rows_V_2_loc_channel1_U_ap_dummy_ce, if_write_ce => p_src_rows_V_2_loc_channel1_U_ap_dummy_ce, if_din => p_src_rows_V_2_loc_channel1_din, if_full_n => p_src_rows_V_2_loc_channel1_full_n, if_write => p_src_rows_V_2_loc_channel1_write, if_dout => p_src_rows_V_2_loc_channel1_dout, if_empty_n => p_src_rows_V_2_loc_channel1_empty_n, if_read => p_src_rows_V_2_loc_channel1_read); p_src_rows_V_2_loc_channel_U : component FIFO_image_filter_p_src_rows_V_2_loc_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_rows_V_2_loc_channel_U_ap_dummy_ce, if_write_ce => p_src_rows_V_2_loc_channel_U_ap_dummy_ce, if_din => p_src_rows_V_2_loc_channel_din, if_full_n => p_src_rows_V_2_loc_channel_full_n, if_write => p_src_rows_V_2_loc_channel_write, if_dout => p_src_rows_V_2_loc_channel_dout, if_empty_n => p_src_rows_V_2_loc_channel_empty_n, if_read => p_src_rows_V_2_loc_channel_read); p_dst_cols_V_channel_U : component FIFO_image_filter_p_dst_cols_V_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_cols_V_channel_U_ap_dummy_ce, if_write_ce => p_dst_cols_V_channel_U_ap_dummy_ce, if_din => p_dst_cols_V_channel_din, if_full_n => p_dst_cols_V_channel_full_n, if_write => p_dst_cols_V_channel_write, if_dout => p_dst_cols_V_channel_dout, if_empty_n => p_dst_cols_V_channel_empty_n, if_read => p_dst_cols_V_channel_read); p_dst_cols_V_U : component FIFO_image_filter_p_dst_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_cols_V_U_ap_dummy_ce, if_write_ce => p_dst_cols_V_U_ap_dummy_ce, if_din => p_dst_cols_V_din, if_full_n => p_dst_cols_V_full_n, if_write => p_dst_cols_V_write, if_dout => p_dst_cols_V_dout, if_empty_n => p_dst_cols_V_empty_n, if_read => p_dst_cols_V_read); p_dst_rows_V_channel_U : component FIFO_image_filter_p_dst_rows_V_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_rows_V_channel_U_ap_dummy_ce, if_write_ce => p_dst_rows_V_channel_U_ap_dummy_ce, if_din => p_dst_rows_V_channel_din, if_full_n => p_dst_rows_V_channel_full_n, if_write => p_dst_rows_V_channel_write, if_dout => p_dst_rows_V_channel_dout, if_empty_n => p_dst_rows_V_channel_empty_n, if_read => p_dst_rows_V_channel_read); p_dst_rows_V_U : component FIFO_image_filter_p_dst_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_rows_V_U_ap_dummy_ce, if_write_ce => p_dst_rows_V_U_ap_dummy_ce, if_din => p_dst_rows_V_din, if_full_n => p_dst_rows_V_full_n, if_write => p_dst_rows_V_write, if_dout => p_dst_rows_V_dout, if_empty_n => p_dst_rows_V_empty_n, if_read => p_dst_rows_V_read); p_src_cols_V_channel_U : component FIFO_image_filter_p_src_cols_V_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_cols_V_channel_U_ap_dummy_ce, if_write_ce => p_src_cols_V_channel_U_ap_dummy_ce, if_din => p_src_cols_V_channel_din, if_full_n => p_src_cols_V_channel_full_n, if_write => p_src_cols_V_channel_write, if_dout => p_src_cols_V_channel_dout, if_empty_n => p_src_cols_V_channel_empty_n, if_read => p_src_cols_V_channel_read); p_src_rows_V_channel_U : component FIFO_image_filter_p_src_rows_V_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_rows_V_channel_U_ap_dummy_ce, if_write_ce => p_src_rows_V_channel_U_ap_dummy_ce, if_din => p_src_rows_V_channel_din, if_full_n => p_src_rows_V_channel_full_n, if_write => p_src_rows_V_channel_write, if_dout => p_src_rows_V_channel_dout, if_empty_n => p_src_rows_V_channel_empty_n, if_read => p_src_rows_V_channel_read); p_src_rows_V_channel1_U : component FIFO_image_filter_p_src_rows_V_channel1 port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_rows_V_channel1_U_ap_dummy_ce, if_write_ce => p_src_rows_V_channel1_U_ap_dummy_ce, if_din => p_src_rows_V_channel1_din, if_full_n => p_src_rows_V_channel1_full_n, if_write => p_src_rows_V_channel1_write, if_dout => p_src_rows_V_channel1_dout, if_empty_n => p_src_rows_V_channel1_empty_n, if_read => p_src_rows_V_channel1_read); p_src_cols_V_channel1_U : component FIFO_image_filter_p_src_cols_V_channel1 port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_cols_V_channel1_U_ap_dummy_ce, if_write_ce => p_src_cols_V_channel1_U_ap_dummy_ce, if_din => p_src_cols_V_channel1_din, if_full_n => p_src_cols_V_channel1_full_n, if_write => p_src_cols_V_channel1_write, if_dout => p_src_cols_V_channel1_dout, if_empty_n => p_src_cols_V_channel1_empty_n, if_read => p_src_cols_V_channel1_read); p_src_data_stream_0_V_U : component FIFO_image_filter_p_src_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_data_stream_0_V_U_ap_dummy_ce, if_write_ce => p_src_data_stream_0_V_U_ap_dummy_ce, if_din => p_src_data_stream_0_V_din, if_full_n => p_src_data_stream_0_V_full_n, if_write => p_src_data_stream_0_V_write, if_dout => p_src_data_stream_0_V_dout, if_empty_n => p_src_data_stream_0_V_empty_n, if_read => p_src_data_stream_0_V_read); p_src_data_stream_1_V_U : component FIFO_image_filter_p_src_data_stream_1_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_data_stream_1_V_U_ap_dummy_ce, if_write_ce => p_src_data_stream_1_V_U_ap_dummy_ce, if_din => p_src_data_stream_1_V_din, if_full_n => p_src_data_stream_1_V_full_n, if_write => p_src_data_stream_1_V_write, if_dout => p_src_data_stream_1_V_dout, if_empty_n => p_src_data_stream_1_V_empty_n, if_read => p_src_data_stream_1_V_read); p_src_data_stream_2_V_U : component FIFO_image_filter_p_src_data_stream_2_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_data_stream_2_V_U_ap_dummy_ce, if_write_ce => p_src_data_stream_2_V_U_ap_dummy_ce, if_din => p_src_data_stream_2_V_din, if_full_n => p_src_data_stream_2_V_full_n, if_write => p_src_data_stream_2_V_write, if_dout => p_src_data_stream_2_V_dout, if_empty_n => p_src_data_stream_2_V_empty_n, if_read => p_src_data_stream_2_V_read); src0_data_stream_0_V_U : component FIFO_image_filter_src0_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_data_stream_0_V_U_ap_dummy_ce, if_write_ce => src0_data_stream_0_V_U_ap_dummy_ce, if_din => src0_data_stream_0_V_din, if_full_n => src0_data_stream_0_V_full_n, if_write => src0_data_stream_0_V_write, if_dout => src0_data_stream_0_V_dout, if_empty_n => src0_data_stream_0_V_empty_n, if_read => src0_data_stream_0_V_read); src0_data_stream_1_V_U : component FIFO_image_filter_src0_data_stream_1_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_data_stream_1_V_U_ap_dummy_ce, if_write_ce => src0_data_stream_1_V_U_ap_dummy_ce, if_din => src0_data_stream_1_V_din, if_full_n => src0_data_stream_1_V_full_n, if_write => src0_data_stream_1_V_write, if_dout => src0_data_stream_1_V_dout, if_empty_n => src0_data_stream_1_V_empty_n, if_read => src0_data_stream_1_V_read); src0_data_stream_2_V_U : component FIFO_image_filter_src0_data_stream_2_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_data_stream_2_V_U_ap_dummy_ce, if_write_ce => src0_data_stream_2_V_U_ap_dummy_ce, if_din => src0_data_stream_2_V_din, if_full_n => src0_data_stream_2_V_full_n, if_write => src0_data_stream_2_V_write, if_dout => src0_data_stream_2_V_dout, if_empty_n => src0_data_stream_2_V_empty_n, if_read => src0_data_stream_2_V_read); src1_data_stream_0_V_U : component FIFO_image_filter_src1_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_data_stream_0_V_U_ap_dummy_ce, if_write_ce => src1_data_stream_0_V_U_ap_dummy_ce, if_din => src1_data_stream_0_V_din, if_full_n => src1_data_stream_0_V_full_n, if_write => src1_data_stream_0_V_write, if_dout => src1_data_stream_0_V_dout, if_empty_n => src1_data_stream_0_V_empty_n, if_read => src1_data_stream_0_V_read); src1_data_stream_1_V_U : component FIFO_image_filter_src1_data_stream_1_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_data_stream_1_V_U_ap_dummy_ce, if_write_ce => src1_data_stream_1_V_U_ap_dummy_ce, if_din => src1_data_stream_1_V_din, if_full_n => src1_data_stream_1_V_full_n, if_write => src1_data_stream_1_V_write, if_dout => src1_data_stream_1_V_dout, if_empty_n => src1_data_stream_1_V_empty_n, if_read => src1_data_stream_1_V_read); src1_data_stream_2_V_U : component FIFO_image_filter_src1_data_stream_2_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_data_stream_2_V_U_ap_dummy_ce, if_write_ce => src1_data_stream_2_V_U_ap_dummy_ce, if_din => src1_data_stream_2_V_din, if_full_n => src1_data_stream_2_V_full_n, if_write => src1_data_stream_2_V_write, if_dout => src1_data_stream_2_V_dout, if_empty_n => src1_data_stream_2_V_empty_n, if_read => src1_data_stream_2_V_read); src0_rows_V_U : component FIFO_image_filter_src0_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_rows_V_U_ap_dummy_ce, if_write_ce => src0_rows_V_U_ap_dummy_ce, if_din => src0_rows_V_din, if_full_n => src0_rows_V_full_n, if_write => src0_rows_V_write, if_dout => src0_rows_V_dout, if_empty_n => src0_rows_V_empty_n, if_read => src0_rows_V_read); src0_cols_V_U : component FIFO_image_filter_src0_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_cols_V_U_ap_dummy_ce, if_write_ce => src0_cols_V_U_ap_dummy_ce, if_din => src0_cols_V_din, if_full_n => src0_cols_V_full_n, if_write => src0_cols_V_write, if_dout => src0_cols_V_dout, if_empty_n => src0_cols_V_empty_n, if_read => src0_cols_V_read); src1_rows_V_U : component FIFO_image_filter_src1_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_rows_V_U_ap_dummy_ce, if_write_ce => src1_rows_V_U_ap_dummy_ce, if_din => src1_rows_V_din, if_full_n => src1_rows_V_full_n, if_write => src1_rows_V_write, if_dout => src1_rows_V_dout, if_empty_n => src1_rows_V_empty_n, if_read => src1_rows_V_read); src1_cols_V_U : component FIFO_image_filter_src1_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_cols_V_U_ap_dummy_ce, if_write_ce => src1_cols_V_U_ap_dummy_ce, if_din => src1_cols_V_din, if_full_n => src1_cols_V_full_n, if_write => src1_cols_V_write, if_dout => src1_cols_V_dout, if_empty_n => src1_cols_V_empty_n, if_read => src1_cols_V_read); mask_rows_V_U : component FIFO_image_filter_mask_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => mask_rows_V_U_ap_dummy_ce, if_write_ce => mask_rows_V_U_ap_dummy_ce, if_din => mask_rows_V_din, if_full_n => mask_rows_V_full_n, if_write => mask_rows_V_write, if_dout => mask_rows_V_dout, if_empty_n => mask_rows_V_empty_n, if_read => mask_rows_V_read); mask_cols_V_U : component FIFO_image_filter_mask_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => mask_cols_V_U_ap_dummy_ce, if_write_ce => mask_cols_V_U_ap_dummy_ce, if_din => mask_cols_V_din, if_full_n => mask_cols_V_full_n, if_write => mask_cols_V_write, if_dout => mask_cols_V_dout, if_empty_n => mask_cols_V_empty_n, if_read => mask_cols_V_read); dmask_rows_V_U : component FIFO_image_filter_dmask_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => dmask_rows_V_U_ap_dummy_ce, if_write_ce => dmask_rows_V_U_ap_dummy_ce, if_din => dmask_rows_V_din, if_full_n => dmask_rows_V_full_n, if_write => dmask_rows_V_write, if_dout => dmask_rows_V_dout, if_empty_n => dmask_rows_V_empty_n, if_read => dmask_rows_V_read); dmask_cols_V_U : component FIFO_image_filter_dmask_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => dmask_cols_V_U_ap_dummy_ce, if_write_ce => dmask_cols_V_U_ap_dummy_ce, if_din => dmask_cols_V_din, if_full_n => dmask_cols_V_full_n, if_write => dmask_cols_V_write, if_dout => dmask_cols_V_dout, if_empty_n => dmask_cols_V_empty_n, if_read => dmask_cols_V_read); gray_data_stream_0_V_U : component FIFO_image_filter_gray_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => gray_data_stream_0_V_U_ap_dummy_ce, if_write_ce => gray_data_stream_0_V_U_ap_dummy_ce, if_din => gray_data_stream_0_V_din, if_full_n => gray_data_stream_0_V_full_n, if_write => gray_data_stream_0_V_write, if_dout => gray_data_stream_0_V_dout, if_empty_n => gray_data_stream_0_V_empty_n, if_read => gray_data_stream_0_V_read); gray_rows_V_U : component FIFO_image_filter_gray_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => gray_rows_V_U_ap_dummy_ce, if_write_ce => gray_rows_V_U_ap_dummy_ce, if_din => gray_rows_V_din, if_full_n => gray_rows_V_full_n, if_write => gray_rows_V_write, if_dout => gray_rows_V_dout, if_empty_n => gray_rows_V_empty_n, if_read => gray_rows_V_read); gray_cols_V_U : component FIFO_image_filter_gray_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => gray_cols_V_U_ap_dummy_ce, if_write_ce => gray_cols_V_U_ap_dummy_ce, if_din => gray_cols_V_din, if_full_n => gray_cols_V_full_n, if_write => gray_cols_V_write, if_dout => gray_cols_V_dout, if_empty_n => gray_cols_V_empty_n, if_read => gray_cols_V_read); mask_data_stream_0_V_U : component FIFO_image_filter_mask_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => mask_data_stream_0_V_U_ap_dummy_ce, if_write_ce => mask_data_stream_0_V_U_ap_dummy_ce, if_din => mask_data_stream_0_V_din, if_full_n => mask_data_stream_0_V_full_n, if_write => mask_data_stream_0_V_write, if_dout => mask_data_stream_0_V_dout, if_empty_n => mask_data_stream_0_V_empty_n, if_read => mask_data_stream_0_V_read); dmask_data_stream_0_V_U : component FIFO_image_filter_dmask_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => dmask_data_stream_0_V_U_ap_dummy_ce, if_write_ce => dmask_data_stream_0_V_U_ap_dummy_ce, if_din => dmask_data_stream_0_V_din, if_full_n => dmask_data_stream_0_V_full_n, if_write => dmask_data_stream_0_V_write, if_dout => dmask_data_stream_0_V_dout, if_empty_n => dmask_data_stream_0_V_empty_n, if_read => dmask_data_stream_0_V_read); p_dst_data_stream_0_V_U : component FIFO_image_filter_p_dst_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_data_stream_0_V_U_ap_dummy_ce, if_write_ce => p_dst_data_stream_0_V_U_ap_dummy_ce, if_din => p_dst_data_stream_0_V_din, if_full_n => p_dst_data_stream_0_V_full_n, if_write => p_dst_data_stream_0_V_write, if_dout => p_dst_data_stream_0_V_dout, if_empty_n => p_dst_data_stream_0_V_empty_n, if_read => p_dst_data_stream_0_V_read); p_dst_data_stream_1_V_U : component FIFO_image_filter_p_dst_data_stream_1_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_data_stream_1_V_U_ap_dummy_ce, if_write_ce => p_dst_data_stream_1_V_U_ap_dummy_ce, if_din => p_dst_data_stream_1_V_din, if_full_n => p_dst_data_stream_1_V_full_n, if_write => p_dst_data_stream_1_V_write, if_dout => p_dst_data_stream_1_V_dout, if_empty_n => p_dst_data_stream_1_V_empty_n, if_read => p_dst_data_stream_1_V_read); p_dst_data_stream_2_V_U : component FIFO_image_filter_p_dst_data_stream_2_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_data_stream_2_V_U_ap_dummy_ce, if_write_ce => p_dst_data_stream_2_V_U_ap_dummy_ce, if_din => p_dst_data_stream_2_V_din, if_full_n => p_dst_data_stream_2_V_full_n, if_write => p_dst_data_stream_2_V_write, if_dout => p_dst_data_stream_2_V_dout, if_empty_n => p_dst_data_stream_2_V_empty_n, if_read => p_dst_data_stream_2_V_read); -- ap_reg_procdone_image_filter_AXIvideo2Mat_U0 assign process. -- ap_reg_procdone_image_filter_AXIvideo2Mat_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_done)) then ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 assign process. -- ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done)) then ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 assign process. -- ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done)) then ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Block_proc_U0 assign process. -- ap_reg_procdone_image_filter_Block_proc_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0; elsif ((image_filter_Block_proc_U0_ap_done = ap_const_logic_1)) then ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 assign process. -- ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_Dilate_0_0_1080_1920_U0_ap_done)) then ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_FAST_t_opr_U0 assign process. -- ap_reg_procdone_image_filter_FAST_t_opr_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_FAST_t_opr_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_FAST_t_opr_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_FAST_t_opr_U0_ap_done)) then ap_reg_procdone_image_filter_FAST_t_opr_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Mat2AXIvideo_U0 assign process. -- ap_reg_procdone_image_filter_Mat2AXIvideo_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 assign process. -- ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_PaintMask_32_0_1080_1920_U0_ap_done)) then ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_dmask_cols_V_full_n assign process. -- ap_reg_ready_dmask_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_dmask_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_dmask_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = dmask_cols_V_full_n))) then ap_reg_ready_dmask_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_dmask_rows_V_full_n assign process. -- ap_reg_ready_dmask_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_dmask_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_dmask_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = dmask_rows_V_full_n))) then ap_reg_ready_dmask_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_gray_cols_V_full_n assign process. -- ap_reg_ready_gray_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_gray_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_continue))) then ap_reg_ready_gray_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = gray_cols_V_full_n))) then ap_reg_ready_gray_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_gray_rows_V_full_n assign process. -- ap_reg_ready_gray_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_gray_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_continue))) then ap_reg_ready_gray_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = gray_rows_V_full_n))) then ap_reg_ready_gray_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_mask_cols_V_full_n assign process. -- ap_reg_ready_mask_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_mask_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_mask_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = mask_cols_V_full_n))) then ap_reg_ready_mask_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_mask_rows_V_full_n assign process. -- ap_reg_ready_mask_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_mask_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_mask_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = mask_rows_V_full_n))) then ap_reg_ready_mask_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_dst_cols_V_channel_full_n assign process. -- ap_reg_ready_p_dst_cols_V_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (p_dst_cols_V_channel_full_n = ap_const_logic_1))) then ap_reg_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_dst_cols_V_full_n assign process. -- ap_reg_ready_p_dst_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_dst_cols_V_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_dst_cols_V_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_dst_cols_V_full_n))) then ap_reg_ready_p_dst_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_dst_rows_V_channel_full_n assign process. -- ap_reg_ready_p_dst_rows_V_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_dst_rows_V_channel_full_n))) then ap_reg_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_dst_rows_V_full_n assign process. -- ap_reg_ready_p_dst_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_dst_rows_V_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_dst_rows_V_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_dst_rows_V_full_n))) then ap_reg_ready_p_dst_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n assign process. -- ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_2_loc_channel1_full_n))) then ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_cols_V_2_loc_channel_full_n assign process. -- ap_reg_ready_p_src_cols_V_2_loc_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_2_loc_channel_full_n))) then ap_reg_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_cols_V_channel1_full_n assign process. -- ap_reg_ready_p_src_cols_V_channel1_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_channel1_full_n))) then ap_reg_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_cols_V_channel_full_n assign process. -- ap_reg_ready_p_src_cols_V_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_cols_V_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_cols_V_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_channel_full_n))) then ap_reg_ready_p_src_cols_V_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n assign process. -- ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_2_loc_channel1_full_n))) then ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_rows_V_2_loc_channel_full_n assign process. -- ap_reg_ready_p_src_rows_V_2_loc_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_2_loc_channel_full_n))) then ap_reg_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_rows_V_channel1_full_n assign process. -- ap_reg_ready_p_src_rows_V_channel1_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_channel1_full_n))) then ap_reg_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_rows_V_channel_full_n assign process. -- ap_reg_ready_p_src_rows_V_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_rows_V_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_rows_V_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_channel_full_n))) then ap_reg_ready_p_src_rows_V_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_src0_cols_V_full_n assign process. -- ap_reg_ready_src0_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_src0_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_src0_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src0_cols_V_full_n))) then ap_reg_ready_src0_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_src0_rows_V_full_n assign process. -- ap_reg_ready_src0_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_src0_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_src0_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src0_rows_V_full_n))) then ap_reg_ready_src0_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_src1_cols_V_full_n assign process. -- ap_reg_ready_src1_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_src1_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_src1_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src1_cols_V_full_n))) then ap_reg_ready_src1_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_src1_rows_V_full_n assign process. -- ap_reg_ready_src1_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_src1_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_src1_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src1_rows_V_full_n))) then ap_reg_ready_src1_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_CS assign process. -- ap_CS_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then ap_CS <= ap_const_logic_0; end if; end process; INPUT_STREAM_TREADY <= image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY; OUTPUT_STREAM_TDATA <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA; OUTPUT_STREAM_TDEST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST; OUTPUT_STREAM_TID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID; OUTPUT_STREAM_TKEEP <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP; OUTPUT_STREAM_TLAST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST; OUTPUT_STREAM_TSTRB <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB; OUTPUT_STREAM_TUSER <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER; OUTPUT_STREAM_TVALID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_dmask_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_dmask_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_dmask_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_dmask_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_mask_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_mask_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_mask_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_mask_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src0_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_src0_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src0_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_src0_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src1_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_src1_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src1_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_src1_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V_assign_proc : process(image_filter_Block_Mat_exit1222_proc1_U0_ap_done, ap_reg_ready_gray_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_gray_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V <= image_filter_Block_Mat_exit1222_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V_assign_proc : process(image_filter_Block_Mat_exit1222_proc1_U0_ap_done, ap_reg_ready_gray_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_gray_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V <= image_filter_Block_Mat_exit1222_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_dst_cols_V_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_cols_V_channel_full_n) begin if ((ap_reg_ready_p_dst_cols_V_channel_full_n = ap_const_logic_1)) then ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_dst_rows_V_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_rows_V_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_dst_rows_V_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_2_loc_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_2_loc_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_channel1_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_channel1_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_2_loc_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_2_loc_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_channel1_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_channel1_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 <= image_filter_Block_proc_U0_ap_done; end if; end process; ap_done <= ap_sig_hs_done; -- ap_idle assign process. -- ap_idle_assign_proc : process(image_filter_Block_proc_U0_ap_idle, image_filter_AXIvideo2Mat_U0_ap_idle, image_filter_Block_Mat_exit1220_proc1_U0_ap_idle, image_filter_Block_Mat_exit1222_proc1_U0_ap_idle, image_filter_FAST_t_opr_U0_ap_idle, image_filter_Dilate_0_0_1080_1920_U0_ap_idle, image_filter_PaintMask_32_0_1080_1920_U0_ap_idle, image_filter_Mat2AXIvideo_U0_ap_idle, p_src_cols_V_2_loc_channel1_empty_n, p_src_cols_V_2_loc_channel_empty_n, p_src_rows_V_2_loc_channel1_empty_n, p_src_rows_V_2_loc_channel_empty_n, p_dst_cols_V_channel_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_channel_empty_n, p_dst_rows_V_empty_n, p_src_cols_V_channel_empty_n, p_src_rows_V_channel_empty_n, p_src_rows_V_channel1_empty_n, p_src_cols_V_channel1_empty_n, src0_rows_V_empty_n, src0_cols_V_empty_n, src1_rows_V_empty_n, src1_cols_V_empty_n, mask_rows_V_empty_n, mask_cols_V_empty_n, dmask_rows_V_empty_n, dmask_cols_V_empty_n, gray_rows_V_empty_n, gray_cols_V_empty_n) begin if (((image_filter_Block_proc_U0_ap_idle = ap_const_logic_1) and (ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_idle) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_idle) and (ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_idle) and (ap_const_logic_1 = image_filter_FAST_t_opr_U0_ap_idle) and (ap_const_logic_1 = image_filter_Dilate_0_0_1080_1920_U0_ap_idle) and (ap_const_logic_1 = image_filter_PaintMask_32_0_1080_1920_U0_ap_idle) and (ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_idle) and (ap_const_logic_0 = p_src_cols_V_2_loc_channel1_empty_n) and (ap_const_logic_0 = p_src_cols_V_2_loc_channel_empty_n) and (ap_const_logic_0 = p_src_rows_V_2_loc_channel1_empty_n) and (ap_const_logic_0 = p_src_rows_V_2_loc_channel_empty_n) and (ap_const_logic_0 = p_dst_cols_V_channel_empty_n) and (ap_const_logic_0 = p_dst_cols_V_empty_n) and (ap_const_logic_0 = p_dst_rows_V_channel_empty_n) and (ap_const_logic_0 = p_dst_rows_V_empty_n) and (ap_const_logic_0 = p_src_cols_V_channel_empty_n) and (ap_const_logic_0 = p_src_rows_V_channel_empty_n) and (ap_const_logic_0 = p_src_rows_V_channel1_empty_n) and (ap_const_logic_0 = p_src_cols_V_channel1_empty_n) and (ap_const_logic_0 = src0_rows_V_empty_n) and (ap_const_logic_0 = src0_cols_V_empty_n) and (ap_const_logic_0 = src1_rows_V_empty_n) and (ap_const_logic_0 = src1_cols_V_empty_n) and (ap_const_logic_0 = mask_rows_V_empty_n) and (ap_const_logic_0 = mask_cols_V_empty_n) and (ap_const_logic_0 = dmask_rows_V_empty_n) and (ap_const_logic_0 = dmask_cols_V_empty_n) and (ap_const_logic_0 = gray_rows_V_empty_n) and (ap_const_logic_0 = gray_cols_V_empty_n))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready <= ap_sig_top_allready; -- ap_rst_n_inv assign process. -- ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; ap_sig_hs_continue <= ap_const_logic_1; -- ap_sig_hs_done assign process. -- ap_sig_hs_done_assign_proc : process(image_filter_Mat2AXIvideo_U0_ap_done) begin if ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then ap_sig_hs_done <= ap_const_logic_1; else ap_sig_hs_done <= ap_const_logic_0; end if; end process; -- ap_sig_ready_dmask_cols_V_full_n assign process. -- ap_sig_ready_dmask_cols_V_full_n_assign_proc : process(dmask_cols_V_full_n, ap_reg_ready_dmask_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_dmask_cols_V_full_n)) then ap_sig_ready_dmask_cols_V_full_n <= dmask_cols_V_full_n; else ap_sig_ready_dmask_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_dmask_rows_V_full_n assign process. -- ap_sig_ready_dmask_rows_V_full_n_assign_proc : process(dmask_rows_V_full_n, ap_reg_ready_dmask_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_dmask_rows_V_full_n)) then ap_sig_ready_dmask_rows_V_full_n <= dmask_rows_V_full_n; else ap_sig_ready_dmask_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_gray_cols_V_full_n assign process. -- ap_sig_ready_gray_cols_V_full_n_assign_proc : process(gray_cols_V_full_n, ap_reg_ready_gray_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_gray_cols_V_full_n)) then ap_sig_ready_gray_cols_V_full_n <= gray_cols_V_full_n; else ap_sig_ready_gray_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_gray_rows_V_full_n assign process. -- ap_sig_ready_gray_rows_V_full_n_assign_proc : process(gray_rows_V_full_n, ap_reg_ready_gray_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_gray_rows_V_full_n)) then ap_sig_ready_gray_rows_V_full_n <= gray_rows_V_full_n; else ap_sig_ready_gray_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_mask_cols_V_full_n assign process. -- ap_sig_ready_mask_cols_V_full_n_assign_proc : process(mask_cols_V_full_n, ap_reg_ready_mask_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_mask_cols_V_full_n)) then ap_sig_ready_mask_cols_V_full_n <= mask_cols_V_full_n; else ap_sig_ready_mask_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_mask_rows_V_full_n assign process. -- ap_sig_ready_mask_rows_V_full_n_assign_proc : process(mask_rows_V_full_n, ap_reg_ready_mask_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_mask_rows_V_full_n)) then ap_sig_ready_mask_rows_V_full_n <= mask_rows_V_full_n; else ap_sig_ready_mask_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_dst_cols_V_channel_full_n assign process. -- ap_sig_ready_p_dst_cols_V_channel_full_n_assign_proc : process(p_dst_cols_V_channel_full_n, ap_reg_ready_p_dst_cols_V_channel_full_n) begin if ((ap_reg_ready_p_dst_cols_V_channel_full_n = ap_const_logic_0)) then ap_sig_ready_p_dst_cols_V_channel_full_n <= p_dst_cols_V_channel_full_n; else ap_sig_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_dst_cols_V_full_n assign process. -- ap_sig_ready_p_dst_cols_V_full_n_assign_proc : process(p_dst_cols_V_full_n, ap_reg_ready_p_dst_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_dst_cols_V_full_n)) then ap_sig_ready_p_dst_cols_V_full_n <= p_dst_cols_V_full_n; else ap_sig_ready_p_dst_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_dst_rows_V_channel_full_n assign process. -- ap_sig_ready_p_dst_rows_V_channel_full_n_assign_proc : process(p_dst_rows_V_channel_full_n, ap_reg_ready_p_dst_rows_V_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_dst_rows_V_channel_full_n)) then ap_sig_ready_p_dst_rows_V_channel_full_n <= p_dst_rows_V_channel_full_n; else ap_sig_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_dst_rows_V_full_n assign process. -- ap_sig_ready_p_dst_rows_V_full_n_assign_proc : process(p_dst_rows_V_full_n, ap_reg_ready_p_dst_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_dst_rows_V_full_n)) then ap_sig_ready_p_dst_rows_V_full_n <= p_dst_rows_V_full_n; else ap_sig_ready_p_dst_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n assign process. -- ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n_assign_proc : process(p_src_cols_V_2_loc_channel1_full_n, ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n)) then ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n <= p_src_cols_V_2_loc_channel1_full_n; else ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_cols_V_2_loc_channel_full_n assign process. -- ap_sig_ready_p_src_cols_V_2_loc_channel_full_n_assign_proc : process(p_src_cols_V_2_loc_channel_full_n, ap_reg_ready_p_src_cols_V_2_loc_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_2_loc_channel_full_n)) then ap_sig_ready_p_src_cols_V_2_loc_channel_full_n <= p_src_cols_V_2_loc_channel_full_n; else ap_sig_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_cols_V_channel1_full_n assign process. -- ap_sig_ready_p_src_cols_V_channel1_full_n_assign_proc : process(p_src_cols_V_channel1_full_n, ap_reg_ready_p_src_cols_V_channel1_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_channel1_full_n)) then ap_sig_ready_p_src_cols_V_channel1_full_n <= p_src_cols_V_channel1_full_n; else ap_sig_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_cols_V_channel_full_n assign process. -- ap_sig_ready_p_src_cols_V_channel_full_n_assign_proc : process(p_src_cols_V_channel_full_n, ap_reg_ready_p_src_cols_V_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_channel_full_n)) then ap_sig_ready_p_src_cols_V_channel_full_n <= p_src_cols_V_channel_full_n; else ap_sig_ready_p_src_cols_V_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n assign process. -- ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n_assign_proc : process(p_src_rows_V_2_loc_channel1_full_n, ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n)) then ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n <= p_src_rows_V_2_loc_channel1_full_n; else ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_rows_V_2_loc_channel_full_n assign process. -- ap_sig_ready_p_src_rows_V_2_loc_channel_full_n_assign_proc : process(p_src_rows_V_2_loc_channel_full_n, ap_reg_ready_p_src_rows_V_2_loc_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_2_loc_channel_full_n)) then ap_sig_ready_p_src_rows_V_2_loc_channel_full_n <= p_src_rows_V_2_loc_channel_full_n; else ap_sig_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_rows_V_channel1_full_n assign process. -- ap_sig_ready_p_src_rows_V_channel1_full_n_assign_proc : process(p_src_rows_V_channel1_full_n, ap_reg_ready_p_src_rows_V_channel1_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_channel1_full_n)) then ap_sig_ready_p_src_rows_V_channel1_full_n <= p_src_rows_V_channel1_full_n; else ap_sig_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_rows_V_channel_full_n assign process. -- ap_sig_ready_p_src_rows_V_channel_full_n_assign_proc : process(p_src_rows_V_channel_full_n, ap_reg_ready_p_src_rows_V_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_channel_full_n)) then ap_sig_ready_p_src_rows_V_channel_full_n <= p_src_rows_V_channel_full_n; else ap_sig_ready_p_src_rows_V_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_src0_cols_V_full_n assign process. -- ap_sig_ready_src0_cols_V_full_n_assign_proc : process(src0_cols_V_full_n, ap_reg_ready_src0_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_src0_cols_V_full_n)) then ap_sig_ready_src0_cols_V_full_n <= src0_cols_V_full_n; else ap_sig_ready_src0_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_src0_rows_V_full_n assign process. -- ap_sig_ready_src0_rows_V_full_n_assign_proc : process(src0_rows_V_full_n, ap_reg_ready_src0_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_src0_rows_V_full_n)) then ap_sig_ready_src0_rows_V_full_n <= src0_rows_V_full_n; else ap_sig_ready_src0_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_src1_cols_V_full_n assign process. -- ap_sig_ready_src1_cols_V_full_n_assign_proc : process(src1_cols_V_full_n, ap_reg_ready_src1_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_src1_cols_V_full_n)) then ap_sig_ready_src1_cols_V_full_n <= src1_cols_V_full_n; else ap_sig_ready_src1_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_src1_rows_V_full_n assign process. -- ap_sig_ready_src1_rows_V_full_n_assign_proc : process(src1_rows_V_full_n, ap_reg_ready_src1_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_src1_rows_V_full_n)) then ap_sig_ready_src1_rows_V_full_n <= src1_rows_V_full_n; else ap_sig_ready_src1_rows_V_full_n <= ap_const_logic_1; end if; end process; ap_sig_top_allready <= image_filter_AXIvideo2Mat_U0_ap_ready; dmask_cols_V_U_ap_dummy_ce <= ap_const_logic_1; dmask_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_7; dmask_cols_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; dmask_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V; dmask_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; dmask_data_stream_0_V_din <= image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_din; dmask_data_stream_0_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_read; dmask_data_stream_0_V_write <= image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_write; dmask_rows_V_U_ap_dummy_ce <= ap_const_logic_1; dmask_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_6; dmask_rows_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; dmask_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V; gray_cols_V_U_ap_dummy_ce <= ap_const_logic_1; gray_cols_V_din <= image_filter_Block_Mat_exit1222_proc1_U0_ap_return_1; gray_cols_V_read <= image_filter_FAST_t_opr_U0_ap_ready; gray_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V; gray_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; gray_data_stream_0_V_din <= image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_din; gray_data_stream_0_V_read <= image_filter_FAST_t_opr_U0_p_src_data_stream_V_read; gray_data_stream_0_V_write <= image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_write; gray_rows_V_U_ap_dummy_ce <= ap_const_logic_1; gray_rows_V_din <= image_filter_Block_Mat_exit1222_proc1_U0_ap_return_0; gray_rows_V_read <= image_filter_FAST_t_opr_U0_ap_ready; gray_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA <= INPUT_STREAM_TDATA; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST <= INPUT_STREAM_TDEST; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID <= INPUT_STREAM_TID; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP <= INPUT_STREAM_TKEEP; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST <= INPUT_STREAM_TLAST; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB <= INPUT_STREAM_TSTRB; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER <= INPUT_STREAM_TUSER; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID <= INPUT_STREAM_TVALID; image_filter_AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1; image_filter_AXIvideo2Mat_U0_ap_start <= (ap_start and p_src_cols_V_channel_empty_n and p_src_rows_V_channel_empty_n); image_filter_AXIvideo2Mat_U0_img_cols_V_read <= p_src_cols_V_channel_dout; image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n <= p_src_data_stream_0_V_full_n; image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n <= p_src_data_stream_1_V_full_n; image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n <= p_src_data_stream_2_V_full_n; image_filter_AXIvideo2Mat_U0_img_rows_V_read <= p_src_rows_V_channel_dout; -- image_filter_Block_Mat_exit1220_proc1_U0_ap_continue assign process. -- image_filter_Block_Mat_exit1220_proc1_U0_ap_continue_assign_proc : process(ap_sig_ready_src0_rows_V_full_n, ap_sig_ready_src0_cols_V_full_n, ap_sig_ready_src1_rows_V_full_n, ap_sig_ready_src1_cols_V_full_n, ap_sig_ready_mask_rows_V_full_n, ap_sig_ready_mask_cols_V_full_n, ap_sig_ready_dmask_rows_V_full_n, ap_sig_ready_dmask_cols_V_full_n) begin if (((ap_const_logic_1 = ap_sig_ready_src0_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_src0_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_src1_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_src1_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_mask_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_mask_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_dmask_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_dmask_cols_V_full_n))) then image_filter_Block_Mat_exit1220_proc1_U0_ap_continue <= ap_const_logic_1; else image_filter_Block_Mat_exit1220_proc1_U0_ap_continue <= ap_const_logic_0; end if; end process; image_filter_Block_Mat_exit1220_proc1_U0_ap_start <= (p_src_cols_V_2_loc_channel_empty_n and p_src_rows_V_2_loc_channel_empty_n and p_src_rows_V_channel1_empty_n and p_src_cols_V_channel1_empty_n); image_filter_Block_Mat_exit1220_proc1_U0_p_read <= p_src_rows_V_2_loc_channel_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_read16 <= p_src_rows_V_channel1_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_read17 <= p_src_cols_V_channel1_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_read2 <= p_src_cols_V_2_loc_channel_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_dout <= p_src_data_stream_0_V_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_empty_n <= p_src_data_stream_0_V_empty_n; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_dout <= p_src_data_stream_1_V_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_empty_n <= p_src_data_stream_1_V_empty_n; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_dout <= p_src_data_stream_2_V_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_empty_n <= p_src_data_stream_2_V_empty_n; image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_full_n <= src0_data_stream_0_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_full_n <= src0_data_stream_1_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_full_n <= src0_data_stream_2_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_full_n <= src1_data_stream_0_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_full_n <= src1_data_stream_1_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_full_n <= src1_data_stream_2_V_full_n; -- image_filter_Block_Mat_exit1222_proc1_U0_ap_continue assign process. -- image_filter_Block_Mat_exit1222_proc1_U0_ap_continue_assign_proc : process(ap_sig_ready_gray_rows_V_full_n, ap_sig_ready_gray_cols_V_full_n) begin if (((ap_const_logic_1 = ap_sig_ready_gray_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_gray_cols_V_full_n))) then image_filter_Block_Mat_exit1222_proc1_U0_ap_continue <= ap_const_logic_1; else image_filter_Block_Mat_exit1222_proc1_U0_ap_continue <= ap_const_logic_0; end if; end process; image_filter_Block_Mat_exit1222_proc1_U0_ap_start <= (p_src_cols_V_2_loc_channel1_empty_n and p_src_rows_V_2_loc_channel1_empty_n and src0_rows_V_empty_n and src0_cols_V_empty_n); image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_full_n <= gray_data_stream_0_V_full_n; image_filter_Block_Mat_exit1222_proc1_U0_p_read <= p_src_rows_V_2_loc_channel1_dout; image_filter_Block_Mat_exit1222_proc1_U0_p_read2 <= p_src_cols_V_2_loc_channel1_dout; image_filter_Block_Mat_exit1222_proc1_U0_p_read6 <= src0_rows_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_p_read7 <= src0_cols_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_dout <= src0_data_stream_0_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_empty_n <= src0_data_stream_0_V_empty_n; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_dout <= src0_data_stream_1_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_empty_n <= src0_data_stream_1_V_empty_n; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_dout <= src0_data_stream_2_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_empty_n <= src0_data_stream_2_V_empty_n; -- image_filter_Block_proc_U0_ap_continue assign process. -- image_filter_Block_proc_U0_ap_continue_assign_proc : process(ap_sig_ready_p_dst_cols_V_channel_full_n, ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n, ap_sig_ready_p_src_cols_V_2_loc_channel_full_n, ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n, ap_sig_ready_p_src_rows_V_2_loc_channel_full_n, ap_sig_ready_p_src_cols_V_channel_full_n, ap_sig_ready_p_dst_cols_V_full_n, ap_sig_ready_p_dst_rows_V_channel_full_n, ap_sig_ready_p_dst_rows_V_full_n, ap_sig_ready_p_src_rows_V_channel_full_n, ap_sig_ready_p_src_rows_V_channel1_full_n, ap_sig_ready_p_src_cols_V_channel1_full_n) begin if (((ap_sig_ready_p_dst_cols_V_channel_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_2_loc_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_2_loc_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_dst_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_p_dst_rows_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_dst_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_channel1_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_channel1_full_n))) then image_filter_Block_proc_U0_ap_continue <= ap_const_logic_1; else image_filter_Block_proc_U0_ap_continue <= ap_const_logic_0; end if; end process; image_filter_Block_proc_U0_ap_start <= ap_start; image_filter_Block_proc_U0_cols <= cols; image_filter_Block_proc_U0_rows <= rows; image_filter_Dilate_0_0_1080_1920_U0_ap_continue <= ap_const_logic_1; image_filter_Dilate_0_0_1080_1920_U0_ap_start <= (mask_rows_V_empty_n and mask_cols_V_empty_n); image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_full_n <= dmask_data_stream_0_V_full_n; image_filter_Dilate_0_0_1080_1920_U0_p_src_cols_V_read <= mask_cols_V_dout; image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_dout <= mask_data_stream_0_V_dout; image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_empty_n <= mask_data_stream_0_V_empty_n; image_filter_Dilate_0_0_1080_1920_U0_p_src_rows_V_read <= mask_rows_V_dout; image_filter_FAST_t_opr_U0_ap_continue <= ap_const_logic_1; image_filter_FAST_t_opr_U0_ap_start <= (gray_rows_V_empty_n and gray_cols_V_empty_n); image_filter_FAST_t_opr_U0_p_mask_data_stream_V_full_n <= mask_data_stream_0_V_full_n; image_filter_FAST_t_opr_U0_p_src_cols_V_read <= gray_cols_V_dout; image_filter_FAST_t_opr_U0_p_src_data_stream_V_dout <= gray_data_stream_0_V_dout; image_filter_FAST_t_opr_U0_p_src_data_stream_V_empty_n <= gray_data_stream_0_V_empty_n; image_filter_FAST_t_opr_U0_p_src_rows_V_read <= gray_rows_V_dout; image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY; image_filter_Mat2AXIvideo_U0_ap_continue <= ap_sig_hs_continue; image_filter_Mat2AXIvideo_U0_ap_start <= (p_dst_cols_V_channel_empty_n and p_dst_rows_V_channel_empty_n); image_filter_Mat2AXIvideo_U0_img_cols_V_read <= p_dst_cols_V_channel_dout; image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout <= p_dst_data_stream_0_V_dout; image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n <= p_dst_data_stream_0_V_empty_n; image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout <= p_dst_data_stream_1_V_dout; image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n <= p_dst_data_stream_1_V_empty_n; image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout <= p_dst_data_stream_2_V_dout; image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n <= p_dst_data_stream_2_V_empty_n; image_filter_Mat2AXIvideo_U0_img_rows_V_read <= p_dst_rows_V_channel_dout; image_filter_PaintMask_32_0_1080_1920_U0_ap_continue <= ap_const_logic_1; image_filter_PaintMask_32_0_1080_1920_U0_ap_start <= (p_dst_cols_V_empty_n and p_dst_rows_V_empty_n and src1_rows_V_empty_n and src1_cols_V_empty_n and dmask_rows_V_empty_n and dmask_cols_V_empty_n); image_filter_PaintMask_32_0_1080_1920_U0_p_dst_cols_V_read <= p_dst_cols_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_full_n <= p_dst_data_stream_0_V_full_n; image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_full_n <= p_dst_data_stream_1_V_full_n; image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_full_n <= p_dst_data_stream_2_V_full_n; image_filter_PaintMask_32_0_1080_1920_U0_p_dst_rows_V_read <= p_dst_rows_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_mask_cols_V_read <= dmask_cols_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_dout <= dmask_data_stream_0_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_empty_n <= dmask_data_stream_0_V_empty_n; image_filter_PaintMask_32_0_1080_1920_U0_p_mask_rows_V_read <= dmask_rows_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_cols_V_read <= src1_cols_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_dout <= src1_data_stream_0_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_empty_n <= src1_data_stream_0_V_empty_n; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_dout <= src1_data_stream_1_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_empty_n <= src1_data_stream_1_V_empty_n; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_dout <= src1_data_stream_2_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_empty_n <= src1_data_stream_2_V_empty_n; image_filter_PaintMask_32_0_1080_1920_U0_p_src_rows_V_read <= src1_rows_V_dout; mask_cols_V_U_ap_dummy_ce <= ap_const_logic_1; mask_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_5; mask_cols_V_read <= image_filter_Dilate_0_0_1080_1920_U0_ap_ready; mask_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V; mask_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; mask_data_stream_0_V_din <= image_filter_FAST_t_opr_U0_p_mask_data_stream_V_din; mask_data_stream_0_V_read <= image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_read; mask_data_stream_0_V_write <= image_filter_FAST_t_opr_U0_p_mask_data_stream_V_write; mask_rows_V_U_ap_dummy_ce <= ap_const_logic_1; mask_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_4; mask_rows_V_read <= image_filter_Dilate_0_0_1080_1920_U0_ap_ready; mask_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V; p_dst_cols_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1; p_dst_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_5; p_dst_cols_V_channel_read <= image_filter_Mat2AXIvideo_U0_ap_ready; p_dst_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel; p_dst_cols_V_din <= image_filter_Block_proc_U0_ap_return_4; p_dst_cols_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; p_dst_cols_V_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V; p_dst_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_data_stream_0_V_din <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_din; p_dst_data_stream_0_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read; p_dst_data_stream_0_V_write <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_write; p_dst_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_data_stream_1_V_din <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_din; p_dst_data_stream_1_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read; p_dst_data_stream_1_V_write <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_write; p_dst_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_data_stream_2_V_din <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_din; p_dst_data_stream_2_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read; p_dst_data_stream_2_V_write <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_write; p_dst_rows_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1; p_dst_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_3; p_dst_rows_V_channel_read <= image_filter_Mat2AXIvideo_U0_ap_ready; p_dst_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel; p_dst_rows_V_din <= image_filter_Block_proc_U0_ap_return_2; p_dst_rows_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; p_dst_rows_V_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V; p_src_cols_V_2_loc_channel1_U_ap_dummy_ce <= ap_const_logic_1; p_src_cols_V_2_loc_channel1_din <= image_filter_Block_proc_U0_ap_return_9; p_src_cols_V_2_loc_channel1_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready; p_src_cols_V_2_loc_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1; p_src_cols_V_2_loc_channel_U_ap_dummy_ce <= ap_const_logic_1; p_src_cols_V_2_loc_channel_din <= image_filter_Block_proc_U0_ap_return_8; p_src_cols_V_2_loc_channel_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready; p_src_cols_V_2_loc_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel; p_src_cols_V_channel1_U_ap_dummy_ce <= ap_const_logic_1; p_src_cols_V_channel1_din <= image_filter_Block_proc_U0_ap_return_11; p_src_cols_V_channel1_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready; p_src_cols_V_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1; p_src_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1; p_src_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_1; p_src_cols_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready; p_src_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel; p_src_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; p_src_data_stream_0_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din; p_src_data_stream_0_V_read <= image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_read; p_src_data_stream_0_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write; p_src_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1; p_src_data_stream_1_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din; p_src_data_stream_1_V_read <= image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_read; p_src_data_stream_1_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write; p_src_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1; p_src_data_stream_2_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din; p_src_data_stream_2_V_read <= image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_read; p_src_data_stream_2_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write; p_src_rows_V_2_loc_channel1_U_ap_dummy_ce <= ap_const_logic_1; p_src_rows_V_2_loc_channel1_din <= image_filter_Block_proc_U0_ap_return_7; p_src_rows_V_2_loc_channel1_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready; p_src_rows_V_2_loc_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1; p_src_rows_V_2_loc_channel_U_ap_dummy_ce <= ap_const_logic_1; p_src_rows_V_2_loc_channel_din <= image_filter_Block_proc_U0_ap_return_6; p_src_rows_V_2_loc_channel_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready; p_src_rows_V_2_loc_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel; p_src_rows_V_channel1_U_ap_dummy_ce <= ap_const_logic_1; p_src_rows_V_channel1_din <= image_filter_Block_proc_U0_ap_return_10; p_src_rows_V_channel1_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready; p_src_rows_V_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1; p_src_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1; p_src_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_0; p_src_rows_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready; p_src_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel; src0_cols_V_U_ap_dummy_ce <= ap_const_logic_1; src0_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_1; src0_cols_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready; src0_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V; src0_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; src0_data_stream_0_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_din; src0_data_stream_0_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_read; src0_data_stream_0_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_write; src0_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1; src0_data_stream_1_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_din; src0_data_stream_1_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_read; src0_data_stream_1_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_write; src0_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1; src0_data_stream_2_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_din; src0_data_stream_2_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_read; src0_data_stream_2_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_write; src0_rows_V_U_ap_dummy_ce <= ap_const_logic_1; src0_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_0; src0_rows_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready; src0_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V; src1_cols_V_U_ap_dummy_ce <= ap_const_logic_1; src1_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_3; src1_cols_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; src1_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V; src1_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; src1_data_stream_0_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_din; src1_data_stream_0_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_read; src1_data_stream_0_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_write; src1_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1; src1_data_stream_1_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_din; src1_data_stream_1_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_read; src1_data_stream_1_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_write; src1_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1; src1_data_stream_2_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_din; src1_data_stream_2_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_read; src1_data_stream_2_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_write; src1_rows_V_U_ap_dummy_ce <= ap_const_logic_1; src1_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_2; src1_rows_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; src1_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V; end behav;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd	3	24145	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_noqueue.vhd -- Description: This entity is the no queue version -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Stream Data Width C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; C_ASYNC : integer range 0 to 1 := 0; C_SG_WORDS_TO_FETCH : integer range 8 to 13 := 8; C_ENABLE_CDMA : integer range 0 to 1 := 0; C_ENABLE_CH1 : integer range 0 to 1 := 0; C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_primary_aclk : in std_logic ; m_axi_sg_aresetn : in std_logic ; -- p_reset_n : in std_logic ; -- -- Channel Control -- desc_flush : in std_logic ; -- ch1_cntrl_strm_stop : in std_logic ; ftch_active : in std_logic ; -- ftch_queue_empty : out std_logic ; -- ftch_queue_full : out std_logic ; -- sof_ftch_desc : in std_logic ; desc2_flush : in std_logic ; -- ftch2_active : in std_logic ; -- ftch2_queue_empty : out std_logic ; -- ftch2_queue_full : out std_logic ; -- -- writing_nxtdesc_in : in std_logic ; -- writing_curdesc_out : out std_logic ; -- writing2_curdesc_out : out std_logic ; -- -- DataMover Command -- ftch_cmnd_wr : in std_logic ; -- ftch_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- MM2S Stream In from DataMover -- m_axis_mm2s_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_mm2s_tlast : in std_logic ; -- m_axis_mm2s_tvalid : in std_logic ; -- m_axis_mm2s_tready : out std_logic ; -- m_axis2_mm2s_tready : out std_logic ; -- data_concat : in std_logic_vector -- (95 downto 0) ; -- data_concat_mcdma : in std_logic_vector -- (63 downto 0) ; -- next_bd : in std_logic_vector (31 downto 0); data_concat_tlast : in std_logic ; -- data_concat_valid : in std_logic ; -- -- -- Channel 1 AXI Fetch Stream Out -- m_axis_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_ftch_tvalid : out std_logic ; -- m_axis_ftch_tready : in std_logic ; -- m_axis_ftch_tlast : out std_logic ; -- m_axis_ftch_tdata_new : out std_logic_vector -- (96+31C_ENABLE_CDMA downto 0); -- m_axis_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ftch_tvalid_new : out std_logic ; -- m_axis_ftch_desc_available : out std_logic ; m_axis2_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis2_ftch_tvalid : out std_logic ; -- m_axis2_ftch_tready : in std_logic ; -- m_axis2_ftch_tlast : out std_logic ; -- m_axis2_ftch_tdata_new : out std_logic_vector -- (96+31C_ENABLE_CDMA downto 0); -- m_axis2_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis2_ftch_tdata_mcdma_nxt : out std_logic_vector -- (31 downto 0); -- m_axis2_ftch_tvalid_new : out std_logic ; -- m_axis2_ftch_desc_available : out std_logic ; m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (31 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- (3 downto 0); -- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic := '0'; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_sg_ftch_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel 1 internal signals signal curdesc_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_tvalid : std_logic := '0'; signal ftch_tvalid : std_logic := '0'; signal ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ftch_tlast : std_logic := '0'; signal ftch_tready : std_logic := '0'; -- Misc Signals signal writing_curdesc : std_logic := '0'; signal writing_nxtdesc : std_logic := '0'; signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0'); signal writing_lsb : std_logic := '0'; signal writing_msb : std_logic := '0'; signal ftch_active_int : std_logic := '0'; signal ftch_tvalid_mult : std_logic := '0'; signal ftch_tdata_mult : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ftch_tlast_mult : std_logic := '0'; signal counter : std_logic_vector (3 downto 0) := (others => '0'); signal wr_cntl : std_logic := '0'; signal ftch_tdata_new : std_logic_vector (96+31*C_ENABLE_CDMA downto 0); signal queue_wren, queue_rden : std_logic := '0'; signal queue_din : std_logic_vector (32 downto 0); signal queue_dout : std_logic_vector (32 downto 0); signal queue_empty, queue_full : std_logic := '0'; signal sof_ftch_desc_del, sof_ftch_desc_pulse : std_logic := '0'; signal sof_ftch_desc_del1 : std_logic := '0'; signal queue_sinit : std_logic := '0'; signal data_concat_mcdma_nxt : std_logic_vector (31 downto 0) := (others => '0'); signal current_bd : std_logic_vector (31 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin queue_sinit <= not m_axi_sg_aresetn; ftch_active_int <= ftch_active or ftch2_active; CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate begin ftch_tdata_new (95 downto 0) <= data_concat;-- when (ftch_active = '1') else (others =>'0'); ftch_tdata_new (127 downto 96) <= current_bd; end generate CDMA_FIELDS; DMA_FIELDS : if C_ENABLE_CDMA = 0 generate begin ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0'); ftch_tdata_new (96 downto 65) <= current_bd; end generate DMA_FIELDS; --------------------------------------------------------------------------- -- Write current descriptor to FIFO or out channel port --------------------------------------------------------------------------- NXT_BD_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate begin NEXT_BD_S2MM : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then data_concat_mcdma_nxt <= (others => '0'); elsif (ftch2_active = '1') then data_concat_mcdma_nxt <= next_bd; end if; end if; end process NEXT_BD_S2MM; end generate NXT_BD_MCDMA; WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then current_bd <= (others => '0'); -- -- -- Write LSB Address on command write elsif(ftch_cmnd_wr = '1' and ftch_active_int = '1')then current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST + DATAMOVER_CMD_ADDRLSB_BIT downto DATAMOVER_CMD_ADDRLSB_BIT); end if; end if; end process WRITE_CURDESC_PROCESS; GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate begin ftch_tvalid_mult <= m_axis_mm2s_tvalid; ftch_tdata_mult <= m_axis_mm2s_tdata; ftch_tlast_mult <= m_axis_mm2s_tlast; wr_cntl <= m_axis_mm2s_tvalid; m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= "0000"; m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; end generate GEN_MULT_CHANNEL; GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate begin ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid; ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata; ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast; CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 and C_ENABLE_CH1 = 1 generate begin SOF_DEL_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sof_ftch_desc_del <= '0'; else sof_ftch_desc_del <= sof_ftch_desc; end if; end if; end process SOF_DEL_PROCESS; SOF_DEL1_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then sof_ftch_desc_del1 <= '0'; elsif (m_axis_mm2s_tvalid = '1') then sof_ftch_desc_del1 <= sof_ftch_desc; end if; end if; end process SOF_DEL1_PROCESS; sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1); queue_wren <= not queue_full and sof_ftch_desc and m_axis_mm2s_tvalid and ftch_active; queue_rden <= not queue_empty and m_axis_mm2s_cntrl_tready; queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast; queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata; I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1.axi_sg_cntrl_strm generic map( C_PRMRY_IS_ACLK_ASYNC => C_ASYNC , C_PRMY_CMDFIFO_DEPTH => 16, --FETCH_QUEUE_DEPTH , C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_FAMILY => C_FAMILY ) port map( -- Secondary clock / reset m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Primary clock / reset axi_prmry_aclk => m_axi_primary_aclk , p_reset_n => p_reset_n , -- MM2S Error mm2s_stop => ch1_cntrl_strm_stop , -- Control Stream input cntrlstrm_fifo_wren => queue_wren , cntrlstrm_fifo_full => queue_full , cntrlstrm_fifo_din => queue_din , -- Memory Map to Stream Control Stream Interface m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); end generate CONTROL_STREAM; NO_CONTROL_STREAM : if C_SG_WORDS_TO_FETCH /= 13 or C_ENABLE_CH1 = 0 generate begin m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= "0000"; m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; end generate NO_CONTROL_STREAM; end generate GEN_NOMULT_CHANNEL; --------------------------------------------------------------------------- -- Map internal stream to external --------------------------------------------------------------------------- ftch_tready <= (m_axis_ftch_tready and ftch_active) or (m_axis2_ftch_tready and ftch2_active); m_axis_ftch_tdata_new <= ftch_tdata_new; m_axis_ftch_tdata_mcdma_new <= data_concat_mcdma; m_axis_ftch_tvalid_new <= data_concat_valid and ftch_active; m_axis_ftch_desc_available <= data_concat_tlast and ftch_active; REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH = 13 generate begin LATCH_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then m_axis2_ftch_tvalid_new <= '0'; m_axis2_ftch_desc_available <= '0'; else m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active; m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active; end if; end if; end process LATCH_PROCESS; LATCH2_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then m_axis2_ftch_tdata_new <= (others => '0'); elsif (data_concat_valid = '1' and ftch2_active = '1') then m_axis2_ftch_tdata_new <= ftch_tdata_new; end if; end if; end process LATCH2_PROCESS; end generate REG_FOR_STS_CNTRL; NO_REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH /= 13 generate begin m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active; m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active; m_axis2_ftch_tdata_new <= ftch_tdata_new; m_axis2_ftch_tdata_mcdma_new <= data_concat_mcdma; m_axis2_ftch_tdata_mcdma_nxt <= data_concat_mcdma_nxt; end generate NO_REG_FOR_STS_CNTRL; m_axis_mm2s_tready <= ftch_tready; m_axis2_mm2s_tready <= ftch_tready; --------------------------------------------------------------------------- -- generate psuedo empty flag for Idle generation --------------------------------------------------------------------------- Q_EMPTY_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then if(m_axi_sg_aresetn = '0' or desc_flush = '1')then ftch_queue_empty <= '1'; -- Else on valid and ready modify empty flag elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1' and ftch_active = '1')then -- On last mark as empty if(ftch_tlast = '1' )then ftch_queue_empty <= '1'; -- Otherwise mark as not empty else ftch_queue_empty <= '0'; end if; end if; end if; end process Q_EMPTY_PROCESS; Q2_EMPTY_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then if(m_axi_sg_aresetn = '0' or desc2_flush = '1')then ftch2_queue_empty <= '1'; -- Else on valid and ready modify empty flag elsif(ftch_tvalid = '1' and m_axis2_ftch_tready = '1' and ftch2_active = '1')then -- On last mark as empty if(ftch_tlast = '1' )then ftch2_queue_empty <= '1'; -- Otherwise mark as not empty else ftch2_queue_empty <= '0'; end if; end if; end if; end process Q2_EMPTY_PROCESS; -- do not need to indicate full to axi_sg_ftch_sm. Only -- needed for queue case to allow other channel to be serviced -- if it had queue room ftch_queue_full <= '0'; ftch2_queue_full <= '0'; -- If writing curdesc out then flag for proper mux selection writing_curdesc <= curdesc_tvalid; -- Map intnal signal to port writing_curdesc_out <= writing_curdesc and ftch_active; writing2_curdesc_out <= writing_curdesc and ftch2_active; -- Map port to internal signal writing_nxtdesc <= writing_nxtdesc_in; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/image_filter_Dilate_0_0_1080_1920_s.vhd	2	92940	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter_Dilate_0_0_1080_1920_s is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_V_empty_n : IN STD_LOGIC; p_src_data_stream_V_read : OUT STD_LOGIC; p_dst_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_V_full_n : IN STD_LOGIC; p_dst_data_stream_V_write : OUT STD_LOGIC ); end; architecture behav of image_filter_Dilate_0_0_1080_1920_s is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (4 downto 0) := "00001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (4 downto 0) := "00010"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (4 downto 0) := "00100"; constant ap_ST_pp0_stg0_fsm_3 : STD_LOGIC_VECTOR (4 downto 0) := "01000"; constant ap_ST_st12_fsm_4 : STD_LOGIC_VECTOR (4 downto 0) := "10000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv11_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000000101"; constant ap_const_lv11_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; constant ap_const_lv11_7FD : STD_LOGIC_VECTOR (10 downto 0) := "11111111101"; constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv11_7FF : STD_LOGIC_VECTOR (10 downto 0) := "11111111111"; constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; constant ap_const_lv11_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100"; constant ap_const_lv12_FFC : STD_LOGIC_VECTOR (11 downto 0) := "111111111100"; constant ap_const_lv12_FFF : STD_LOGIC_VECTOR (11 downto 0) := "111111111111"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv12_FFB : STD_LOGIC_VECTOR (11 downto 0) := "111111111011"; constant ap_const_lv12_FFA : STD_LOGIC_VECTOR (11 downto 0) := "111111111010"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000"; signal ap_done_reg : STD_LOGIC := '0'; signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_24 : BOOLEAN; signal p_025_0_i_i_reg_263 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_bdd_48 : BOOLEAN; signal heightloop_fu_324_p2 : STD_LOGIC_VECTOR (10 downto 0); signal heightloop_reg_1240 : STD_LOGIC_VECTOR (10 downto 0); signal widthloop_fu_330_p2 : STD_LOGIC_VECTOR (10 downto 0); signal widthloop_reg_1245 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_14_cast_fu_342_p1 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_14_cast_reg_1250 : STD_LOGIC_VECTOR (11 downto 0); signal p_neg226_i_i_cast_fu_350_p2 : STD_LOGIC_VECTOR (1 downto 0); signal p_neg226_i_i_cast_reg_1255 : STD_LOGIC_VECTOR (1 downto 0); signal ref_fu_356_p2 : STD_LOGIC_VECTOR (10 downto 0); signal ref_reg_1261 : STD_LOGIC_VECTOR (10 downto 0); signal ref_cast_fu_362_p1 : STD_LOGIC_VECTOR (11 downto 0); signal ref_cast_reg_1267 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_2_i_fu_366_p2 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_2_i_reg_1272 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_2_i1_fu_376_p2 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_2_i1_reg_1277 : STD_LOGIC_VECTOR (1 downto 0); signal i_V_fu_391_p2 : STD_LOGIC_VECTOR (10 downto 0); signal i_V_reg_1286 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_76 : BOOLEAN; signal tmp_17_fu_397_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_reg_1291 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_16_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_reg_1296 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_fu_436_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_1301 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_104_reg_1306 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_105_fu_457_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_105_reg_1310 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_108_fu_473_p3 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_108_reg_1316 : STD_LOGIC_VECTOR (1 downto 0); signal or_cond_i1_fu_506_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_i1_reg_1322 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_110_reg_1327 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_111_fu_520_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_111_reg_1332 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_112_fu_524_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_112_reg_1337 : STD_LOGIC_VECTOR (1 downto 0); signal or_cond_i2_fu_553_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_i2_reg_1344 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_114_reg_1349 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_115_fu_567_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_115_reg_1354 : STD_LOGIC_VECTOR (1 downto 0); signal sel_tmp8_fu_575_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_reg_1359 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC; signal ap_sig_bdd_116 : BOOLEAN; signal sel_tmp3_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp3_reg_1364 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp4_fu_602_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp4_reg_1369 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp7_fu_607_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp7_reg_1374 : STD_LOGIC_VECTOR (0 downto 0); signal locy_2_t_fu_625_p2 : STD_LOGIC_VECTOR (1 downto 0); signal locy_2_t_reg_1379 : STD_LOGIC_VECTOR (1 downto 0); signal brmerge_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0); signal brmerge_reg_1383 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_fu_638_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_reg_1387 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_pp0_stg0_fsm_3 : STD_LOGIC; signal ap_sig_bdd_135 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond2_reg_1419 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_bdd_154 : BOOLEAN; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal or_cond219_i_i_reg_1396 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_bdd_172 : BOOLEAN; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0); signal j_V_fu_643_p2 : STD_LOGIC_VECTOR (10 downto 0); signal or_cond219_i_i_fu_665_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_117_fu_676_p1 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_117_reg_1400 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_i_fu_698_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_reg_1405 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_i_fu_703_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_i_reg_1409 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_120_reg_1414 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond2_fu_723_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_29_fu_729_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_29_reg_1423 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal col_assign_fu_734_p2 : STD_LOGIC_VECTOR (1 downto 0); signal col_assign_reg_1427 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_col_assign_reg_1427_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0); signal k_buf_0_val_0_addr_reg_1433 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_1_addr_reg_1439 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_2_addr_reg_1445 : STD_LOGIC_VECTOR (10 downto 0); signal col_assign_1_fu_762_p2 : STD_LOGIC_VECTOR (1 downto 0); signal col_assign_1_reg_1451 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0); signal k_buf_0_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_2_0_reg_1457 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_0_reg_1464 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_2_0_reg_1471 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_0_1_reg_1477 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_0_1_6_reg_1483 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_1_6_reg_1490 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_2_lo_reg_1496 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_0_2_reg_1501 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_1_fu_1033_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_128_1_reg_1506 : STD_LOGIC_VECTOR (0 downto 0); signal src_kernel_win_0_val_0_1_lo_reg_1511 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_1_lo_reg_1517 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_1_1_reg_1523 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_0_2_lo_reg_1529 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_1_2_reg_1534 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_2_fu_1080_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_128_2_reg_1539 : STD_LOGIC_VECTOR (0 downto 0); signal temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_2_1_reg_1544 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_0_address0 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_0_ce0 : STD_LOGIC; signal k_buf_0_val_0_address1 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_0_ce1 : STD_LOGIC; signal k_buf_0_val_0_we1 : STD_LOGIC; signal k_buf_0_val_0_d1 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_1_address0 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_1_ce0 : STD_LOGIC; signal k_buf_0_val_1_address1 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_1_ce1 : STD_LOGIC; signal k_buf_0_val_1_we1 : STD_LOGIC; signal k_buf_0_val_1_d1 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_2_address0 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_2_ce0 : STD_LOGIC; signal k_buf_0_val_2_address1 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_2_ce1 : STD_LOGIC; signal k_buf_0_val_2_we1 : STD_LOGIC; signal k_buf_0_val_2_d1 : STD_LOGIC_VECTOR (7 downto 0); signal p_012_0_i_i_reg_252 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_cseq_ST_st12_fsm_4 : STD_LOGIC; signal ap_sig_bdd_355 : BOOLEAN; signal tmp_69_fu_755_p1 : STD_LOGIC_VECTOR (63 downto 0); signal src_kernel_win_0_val_0_1_fu_106 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_0_0_fu_934_p3 : STD_LOGIC_VECTOR (7 downto 0); signal col_buf_0_val_0_0_9_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_0_2_fu_110 : STD_LOGIC_VECTOR (7 downto 0); signal col_buf_0_val_0_0_3_fu_114 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_2_1_fu_118 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_1_fu_122 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_0_fu_946_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_11_fu_1006_p3 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_2_fu_126 : STD_LOGIC_VECTOR (7 downto 0); signal col_buf_0_val_0_0_5_fu_130 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_2_2_fu_134 : STD_LOGIC_VECTOR (7 downto 0); signal col_buf_0_val_0_0_6_fu_138 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_1_fu_142 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_8_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_2_fu_146 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_6_fu_868_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_7_fu_150 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_4_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_0_0_fu_166 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_0_1_fu_170 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_0_2_fu_174 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_fu_316_p1 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_100_fu_320_p1 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_14_fu_336_p2 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_101_fu_346_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_102_fu_372_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_15_cast_cast_fu_382_p1 : STD_LOGIC_VECTOR (11 downto 0); signal ImagLoc_y_fu_403_p2 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_103_fu_415_p4 : STD_LOGIC_VECTOR (10 downto 0); signal icmp_fu_425_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_25_fu_431_p2 : STD_LOGIC_VECTOR (0 downto 0); signal p_i_i_fu_450_p3 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_i5_fu_461_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_106_fu_466_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_107_fu_470_p1 : STD_LOGIC_VECTOR (1 downto 0); signal y_1_fu_481_p2 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_109_fu_487_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i1_fu_501_p2 : STD_LOGIC_VECTOR (0 downto 0); signal rev_fu_495_p2 : STD_LOGIC_VECTOR (0 downto 0); signal y_1_1_fu_528_p2 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_113_fu_534_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i2_fu_548_p2 : STD_LOGIC_VECTOR (0 downto 0); signal rev1_fu_542_p2 : STD_LOGIC_VECTOR (0 downto 0); signal locy_fu_571_p2 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_s_fu_585_p3 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_80_fu_591_p3 : STD_LOGIC_VECTOR (1 downto 0); signal locy_1_t_fu_597_p2 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_81_fu_613_p3 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_82_fu_619_p3 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_116_fu_649_p4 : STD_LOGIC_VECTOR (9 downto 0); signal icmp2_fu_659_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_18_cast_fu_634_p1 : STD_LOGIC_VECTOR (11 downto 0); signal ImagLoc_x_fu_670_p2 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_119_fu_684_p3 : STD_LOGIC_VECTOR (0 downto 0); signal rev2_fu_692_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_fu_717_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_118_fu_680_p1 : STD_LOGIC_VECTOR (1 downto 0); signal p_assign_fu_739_p3 : STD_LOGIC_VECTOR (10 downto 0); signal p_assign_1_i_fu_745_p3 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_121_fu_751_p1 : STD_LOGIC_VECTOR (1 downto 0); signal sel_tmp1_fu_833_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0); signal right_border_buf_0_val_1_2_3_fu_838_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_5_fu_860_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_0_1_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_fu_929_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp6_fu_941_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp2_fu_984_p2 : STD_LOGIC_VECTOR (0 downto 0); signal col_buf_0_val_0_0_2_fu_976_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_fu_998_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_0_2_fu_1021_p2 : STD_LOGIC_VECTOR (0 downto 0); signal temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_1_1_fu_1055_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_128_1_2_fu_1070_p2 : STD_LOGIC_VECTOR (0 downto 0); signal temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_2_1_fu_1095_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_128_2_2_fu_1107_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0); component image_filter_FAST_t_opr_k_buf_val_0_V IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (10 downto 0); ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR (7 downto 0); address1 : IN STD_LOGIC_VECTOR (10 downto 0); ce1 : IN STD_LOGIC; we1 : IN STD_LOGIC; d1 : IN STD_LOGIC_VECTOR (7 downto 0) ); end component; begin k_buf_0_val_0_U : component image_filter_FAST_t_opr_k_buf_val_0_V generic map ( DataWidth => 8, AddressRange => 1920, AddressWidth => 11) port map ( clk => ap_clk, reset => ap_rst, address0 => k_buf_0_val_0_address0, ce0 => k_buf_0_val_0_ce0, q0 => k_buf_0_val_0_q0, address1 => k_buf_0_val_0_address1, ce1 => k_buf_0_val_0_ce1, we1 => k_buf_0_val_0_we1, d1 => k_buf_0_val_0_d1); k_buf_0_val_1_U : component image_filter_FAST_t_opr_k_buf_val_0_V generic map ( DataWidth => 8, AddressRange => 1920, AddressWidth => 11) port map ( clk => ap_clk, reset => ap_rst, address0 => k_buf_0_val_1_address0, ce0 => k_buf_0_val_1_ce0, q0 => k_buf_0_val_1_q0, address1 => k_buf_0_val_1_address1, ce1 => k_buf_0_val_1_ce1, we1 => k_buf_0_val_1_we1, d1 => k_buf_0_val_1_d1); k_buf_0_val_2_U : component image_filter_FAST_t_opr_k_buf_val_0_V generic map ( DataWidth => 8, AddressRange => 1920, AddressWidth => 11) port map ( clk => ap_clk, reset => ap_rst, address0 => k_buf_0_val_2_address0, ce0 => k_buf_0_val_2_ce0, q0 => k_buf_0_val_2_q0, address1 => k_buf_0_val_2_address1, ce1 => k_buf_0_val_2_ce1, we1 => k_buf_0_val_2_we1, d1 => k_buf_0_val_2_d1); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_done_reg assign process. -- ap_done_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_done_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_continue)) then ap_done_reg <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then ap_done_reg <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_19_fu_638_p2))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then if (not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2))) then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; elsif ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; end if; end if; end if; end process; -- p_012_0_i_i_reg_252 assign process. -- p_012_0_i_i_reg_252_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_4)) then p_012_0_i_i_reg_252 <= i_V_reg_1286; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then p_012_0_i_i_reg_252 <= ap_const_lv11_0; end if; end if; end process; -- p_025_0_i_i_reg_263 assign process. -- p_025_0_i_i_reg_263_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then p_025_0_i_i_reg_263 <= j_V_fu_643_p2; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then p_025_0_i_i_reg_263 <= ap_const_lv11_0; end if; end if; end process; -- src_kernel_win_0_val_0_1_fu_106 assign process. -- src_kernel_win_0_val_0_1_fu_106_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then src_kernel_win_0_val_0_1_fu_106 <= right_border_buf_0_val_2_0_reg_1457; elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then src_kernel_win_0_val_0_1_fu_106 <= col_buf_0_val_0_0_9_fu_989_p3; elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then src_kernel_win_0_val_0_1_fu_106 <= src_kernel_win_0_val_0_0_fu_934_p3; end if; end if; end process; -- src_kernel_win_0_val_1_1_fu_122 assign process. -- src_kernel_win_0_val_1_1_fu_122_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_0_reg_1464; elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_2_11_fu_1006_p3; elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then src_kernel_win_0_val_1_1_fu_122 <= src_kernel_win_0_val_1_0_fu_946_p3; end if; end if; end process; -- src_kernel_win_0_val_2_1_fu_118 assign process. -- src_kernel_win_0_val_2_1_fu_118_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and not((col_assign_1_reg_1451 = ap_const_lv2_1)) and not((col_assign_1_reg_1451 = ap_const_lv2_0)))) then src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_2_fu_174; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_0))) then src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_0_fu_166; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_1))) then src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_1_fu_170; elsif (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1))))) then src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_2_q0; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0))) then src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_0_q0; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1))) then src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_1_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 <= col_assign_1_reg_1451; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5; ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 <= ap_reg_ppstg_or_cond2_reg_1419_pp0_it1; ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 <= src_kernel_win_0_val_0_1_6_reg_1483; ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4; ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 <= src_kernel_win_0_val_0_1_lo_reg_1511; ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5; ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 <= ap_reg_ppstg_tmp_120_reg_1414_pp0_it1; ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it1; ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it2; ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it3; ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 <= ap_reg_ppstg_tmp_i_reg_1405_pp0_it1; src_kernel_win_0_val_0_1_6_reg_1483 <= src_kernel_win_0_val_0_1_fu_106; src_kernel_win_0_val_1_1_6_reg_1490 <= src_kernel_win_0_val_1_1_fu_122; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then ap_reg_ppstg_col_assign_reg_1427_pp0_it1 <= col_assign_reg_1427; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 <= or_cond219_i_i_reg_1396; ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 <= or_cond2_reg_1419; ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 <= tmp_120_reg_1414; ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 <= tmp_19_reg_1387; ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 <= tmp_29_reg_1423; ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 <= tmp_i_reg_1405; tmp_19_reg_1387 <= tmp_19_fu_638_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then brmerge_reg_1383 <= brmerge_fu_630_p2; locy_2_t_reg_1379 <= locy_2_t_fu_625_p2; sel_tmp3_reg_1364 <= sel_tmp3_fu_579_p2; sel_tmp4_reg_1369 <= sel_tmp4_fu_602_p2; sel_tmp7_reg_1374 <= sel_tmp7_fu_607_p2; sel_tmp8_reg_1359 <= sel_tmp8_fu_575_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)) and (ap_const_lv1_0 = or_cond2_reg_1419) and (ap_const_lv1_0 = tmp_120_reg_1414) and (ap_const_lv1_0 = tmp_i_reg_1405))) then col_assign_1_reg_1451 <= col_assign_1_fu_762_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)) and (ap_const_lv1_0 = tmp_29_fu_729_p2))) then col_assign_reg_1427 <= col_assign_fu_734_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then col_buf_0_val_0_0_3_fu_114 <= k_buf_0_val_0_q0; right_border_buf_0_val_0_2_fu_174 <= k_buf_0_val_2_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1))) then col_buf_0_val_0_0_5_fu_130 <= k_buf_0_val_0_q0; right_border_buf_0_val_0_1_fu_170 <= k_buf_0_val_2_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) then col_buf_0_val_0_0_6_fu_138 <= k_buf_0_val_0_q0; right_border_buf_0_val_0_0_fu_166 <= k_buf_0_val_2_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then heightloop_reg_1240 <= heightloop_fu_324_p2; p_neg226_i_i_cast_reg_1255 <= p_neg226_i_i_cast_fu_350_p2; ref_cast_reg_1267(0) <= ref_cast_fu_362_p1(0); ref_cast_reg_1267(1) <= ref_cast_fu_362_p1(1); ref_cast_reg_1267(2) <= ref_cast_fu_362_p1(2); ref_cast_reg_1267(3) <= ref_cast_fu_362_p1(3); ref_cast_reg_1267(4) <= ref_cast_fu_362_p1(4); ref_cast_reg_1267(5) <= ref_cast_fu_362_p1(5); ref_cast_reg_1267(6) <= ref_cast_fu_362_p1(6); ref_cast_reg_1267(7) <= ref_cast_fu_362_p1(7); ref_cast_reg_1267(8) <= ref_cast_fu_362_p1(8); ref_cast_reg_1267(9) <= ref_cast_fu_362_p1(9); ref_cast_reg_1267(10) <= ref_cast_fu_362_p1(10); ref_reg_1261 <= ref_fu_356_p2; tmp_14_cast_reg_1250(0) <= tmp_14_cast_fu_342_p1(0); tmp_14_cast_reg_1250(1) <= tmp_14_cast_fu_342_p1(1); tmp_14_cast_reg_1250(2) <= tmp_14_cast_fu_342_p1(2); tmp_14_cast_reg_1250(3) <= tmp_14_cast_fu_342_p1(3); tmp_14_cast_reg_1250(4) <= tmp_14_cast_fu_342_p1(4); tmp_14_cast_reg_1250(5) <= tmp_14_cast_fu_342_p1(5); tmp_14_cast_reg_1250(6) <= tmp_14_cast_fu_342_p1(6); tmp_14_cast_reg_1250(7) <= tmp_14_cast_fu_342_p1(7); tmp_14_cast_reg_1250(8) <= tmp_14_cast_fu_342_p1(8); tmp_14_cast_reg_1250(9) <= tmp_14_cast_fu_342_p1(9); tmp_14_cast_reg_1250(10) <= tmp_14_cast_fu_342_p1(10); tmp_2_i1_reg_1277 <= tmp_2_i1_fu_376_p2; tmp_2_i_reg_1272 <= tmp_2_i_fu_366_p2; widthloop_reg_1245 <= widthloop_fu_330_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then i_V_reg_1286 <= i_V_fu_391_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)))) then k_buf_0_val_0_addr_reg_1433 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_1_addr_reg_1439 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_2_addr_reg_1445 <= tmp_69_fu_755_p1(11 - 1 downto 0); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then or_cond219_i_i_reg_1396 <= or_cond219_i_i_fu_665_p2; or_cond_i_reg_1409 <= or_cond_i_fu_703_p2; tmp_117_reg_1400 <= tmp_117_fu_676_p1; tmp_120_reg_1414 <= ImagLoc_x_fu_670_p2(11 downto 11); tmp_i_reg_1405 <= tmp_i_fu_698_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then or_cond2_reg_1419 <= or_cond2_fu_723_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((tmp_16_fu_386_p2 = ap_const_lv1_0)))) then or_cond_i1_reg_1322 <= or_cond_i1_fu_506_p2; or_cond_i2_reg_1344 <= or_cond_i2_fu_553_p2; or_cond_reg_1301 <= or_cond_fu_436_p2; tmp_104_reg_1306 <= ImagLoc_y_fu_403_p2(11 downto 11); tmp_105_reg_1310 <= tmp_105_fu_457_p1; tmp_108_reg_1316 <= tmp_108_fu_473_p3; tmp_110_reg_1327 <= y_1_fu_481_p2(11 downto 11); tmp_111_reg_1332 <= tmp_111_fu_520_p1; tmp_112_reg_1337 <= tmp_112_fu_524_p1; tmp_114_reg_1349 <= y_1_1_fu_528_p2(11 downto 11); tmp_115_reg_1354 <= tmp_115_fu_567_p1; tmp_17_reg_1291 <= tmp_17_fu_397_p2; tmp_23_reg_1296 <= tmp_23_fu_409_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then right_border_buf_0_val_1_0_reg_1464 <= k_buf_0_val_1_q0; right_border_buf_0_val_2_0_reg_1457 <= k_buf_0_val_0_q0; src_kernel_win_0_val_2_0_reg_1471 <= k_buf_0_val_2_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then right_border_buf_0_val_1_2_1_fu_142 <= right_border_buf_0_val_1_2_8_fu_877_p3; right_border_buf_0_val_1_2_2_fu_146 <= right_border_buf_0_val_1_2_6_fu_868_p3; right_border_buf_0_val_1_2_7_fu_150 <= right_border_buf_0_val_1_2_4_fu_851_p3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3)))) then src_kernel_win_0_val_0_1_lo_reg_1511 <= src_kernel_win_0_val_0_1_fu_106; src_kernel_win_0_val_1_1_lo_reg_1517 <= src_kernel_win_0_val_1_1_fu_122; temp_0_i_i_i_057_i_i_1_1_1_reg_1523 <= temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it4)))) then src_kernel_win_0_val_0_2_fu_110 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4)))) then src_kernel_win_0_val_0_2_lo_reg_1529 <= src_kernel_win_0_val_0_2_fu_110; temp_0_i_i_i_057_i_i_1_1_2_reg_1534 <= temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3; tmp_128_2_reg_1539 <= tmp_128_2_fu_1080_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)))) then src_kernel_win_0_val_1_2_fu_126 <= src_kernel_win_0_val_1_1_fu_122; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2)))) then src_kernel_win_0_val_1_2_lo_reg_1496 <= src_kernel_win_0_val_1_2_fu_126; temp_0_i_i_i_057_i_i_1_0_2_reg_1501 <= temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3; tmp_128_1_reg_1506 <= tmp_128_1_fu_1033_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then src_kernel_win_0_val_2_2_fu_134 <= src_kernel_win_0_val_2_1_fu_118; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1)))) then temp_0_i_i_i_057_i_i_1_0_1_reg_1477 <= temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5)))) then temp_0_i_i_i_057_i_i_1_2_1_reg_1544 <= temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)))) then tmp_29_reg_1423 <= tmp_29_fu_729_p2; end if; end if; end process; tmp_14_cast_reg_1250(11) <= '0'; ref_cast_reg_1267(11) <= '0'; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_48, tmp_16_fu_386_p2, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not(ap_sig_bdd_48)) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if ((tmp_16_fu_386_p2 = ap_const_lv1_0)) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_st3_fsm_2; end if; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3; when ap_ST_pp0_stg0_fsm_3 => if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4)))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3; elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4))))) then ap_NS_fsm <= ap_ST_st12_fsm_4; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3; end if; when ap_ST_st12_fsm_4 => ap_NS_fsm <= ap_ST_st2_fsm_1; when others => ap_NS_fsm <= "XXXXX"; end case; end process; ImagLoc_x_fu_670_p2 <= std_logic_vector(unsigned(tmp_18_cast_fu_634_p1) + unsigned(ap_const_lv12_FFF)); ImagLoc_y_fu_403_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFC)); -- ap_done assign process. -- ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2) begin if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_116 assign process. -- ap_sig_bdd_116_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_116 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_bdd_135 assign process. -- ap_sig_bdd_135_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_135 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_154 assign process. -- ap_sig_bdd_154_assign_proc : process(p_src_data_stream_V_empty_n, brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) begin ap_sig_bdd_154 <= ((p_src_data_stream_V_empty_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1))); end process; -- ap_sig_bdd_172 assign process. -- ap_sig_bdd_172_assign_proc : process(p_dst_data_stream_V_full_n, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6) begin ap_sig_bdd_172 <= ((p_dst_data_stream_V_full_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6))); end process; -- ap_sig_bdd_24 assign process. -- ap_sig_bdd_24_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_24 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_355 assign process. -- ap_sig_bdd_355_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_355 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); end process; -- ap_sig_bdd_48 assign process. -- ap_sig_bdd_48_assign_proc : process(ap_start, ap_done_reg) begin ap_sig_bdd_48 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1)); end process; -- ap_sig_bdd_76 assign process. -- ap_sig_bdd_76_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_76 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_cseq_ST_pp0_stg0_fsm_3 assign process. -- ap_sig_cseq_ST_pp0_stg0_fsm_3_assign_proc : process(ap_sig_bdd_135) begin if (ap_sig_bdd_135) then ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st12_fsm_4 assign process. -- ap_sig_cseq_ST_st12_fsm_4_assign_proc : process(ap_sig_bdd_355) begin if (ap_sig_bdd_355) then ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_1; else ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_24) begin if (ap_sig_bdd_24) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_76) begin if (ap_sig_bdd_76) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st3_fsm_2 assign process. -- ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_116) begin if (ap_sig_bdd_116) then ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0; end if; end process; brmerge_fu_630_p2 <= (tmp_23_reg_1296 or or_cond_reg_1301); col_assign_1_fu_762_p2 <= std_logic_vector(unsigned(tmp_121_fu_751_p1) + unsigned(p_neg226_i_i_cast_reg_1255)); col_assign_fu_734_p2 <= std_logic_vector(unsigned(tmp_118_fu_680_p1) + unsigned(p_neg226_i_i_cast_reg_1255)); col_buf_0_val_0_0_2_fu_976_p3 <= col_buf_0_val_0_0_5_fu_130 when (sel_tmp_fu_971_p2(0) = '1') else col_buf_0_val_0_0_3_fu_114; col_buf_0_val_0_0_9_fu_989_p3 <= col_buf_0_val_0_0_6_fu_138 when (sel_tmp2_fu_984_p2(0) = '1') else col_buf_0_val_0_0_2_fu_976_p3; heightloop_fu_324_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_5)); i_V_fu_391_p2 <= std_logic_vector(unsigned(p_012_0_i_i_reg_252) + unsigned(ap_const_lv11_1)); icmp2_fu_659_p2 <= "0" when (tmp_116_fu_649_p4 = ap_const_lv10_0) else "1"; icmp_fu_425_p2 <= "1" when (signed(tmp_103_fu_415_p4) > signed(ap_const_lv11_0)) else "0"; j_V_fu_643_p2 <= std_logic_vector(unsigned(p_025_0_i_i_reg_263) + unsigned(ap_const_lv11_1)); k_buf_0_val_0_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_0_address1 <= k_buf_0_val_0_addr_reg_1433; -- k_buf_0_val_0_ce0 assign process. -- k_buf_0_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then k_buf_0_val_0_ce0 <= ap_const_logic_1; else k_buf_0_val_0_ce0 <= ap_const_logic_0; end if; end process; -- k_buf_0_val_0_ce1 assign process. -- k_buf_0_val_0_ce1_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then k_buf_0_val_0_ce1 <= ap_const_logic_1; else k_buf_0_val_0_ce1 <= ap_const_logic_0; end if; end process; k_buf_0_val_0_d1 <= p_src_data_stream_V_dout; -- k_buf_0_val_0_we1 assign process. -- k_buf_0_val_0_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))))) then k_buf_0_val_0_we1 <= ap_const_logic_1; else k_buf_0_val_0_we1 <= ap_const_logic_0; end if; end process; k_buf_0_val_1_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_1_address1 <= k_buf_0_val_1_addr_reg_1439; -- k_buf_0_val_1_ce0 assign process. -- k_buf_0_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then k_buf_0_val_1_ce0 <= ap_const_logic_1; else k_buf_0_val_1_ce0 <= ap_const_logic_0; end if; end process; -- k_buf_0_val_1_ce1 assign process. -- k_buf_0_val_1_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then k_buf_0_val_1_ce1 <= ap_const_logic_1; else k_buf_0_val_1_ce1 <= ap_const_logic_0; end if; end process; k_buf_0_val_1_d1 <= k_buf_0_val_0_q0; -- k_buf_0_val_1_we1 assign process. -- k_buf_0_val_1_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then k_buf_0_val_1_we1 <= ap_const_logic_1; else k_buf_0_val_1_we1 <= ap_const_logic_0; end if; end process; k_buf_0_val_2_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_2_address1 <= k_buf_0_val_2_addr_reg_1445; -- k_buf_0_val_2_ce0 assign process. -- k_buf_0_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then k_buf_0_val_2_ce0 <= ap_const_logic_1; else k_buf_0_val_2_ce0 <= ap_const_logic_0; end if; end process; -- k_buf_0_val_2_ce1 assign process. -- k_buf_0_val_2_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then k_buf_0_val_2_ce1 <= ap_const_logic_1; else k_buf_0_val_2_ce1 <= ap_const_logic_0; end if; end process; k_buf_0_val_2_d1 <= k_buf_0_val_1_q0; -- k_buf_0_val_2_we1 assign process. -- k_buf_0_val_2_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then k_buf_0_val_2_we1 <= ap_const_logic_1; else k_buf_0_val_2_we1 <= ap_const_logic_0; end if; end process; locy_1_t_fu_597_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_80_fu_591_p3)); locy_2_t_fu_625_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_82_fu_619_p3)); locy_fu_571_p2 <= std_logic_vector(unsigned(tmp_105_reg_1310) - unsigned(tmp_108_reg_1316)); or_cond219_i_i_fu_665_p2 <= (tmp_17_reg_1291 and icmp2_fu_659_p2); or_cond2_fu_723_p2 <= (tmp_26_fu_717_p2 and tmp_i_fu_698_p2); or_cond_fu_436_p2 <= (icmp_fu_425_p2 and tmp_25_fu_431_p2); or_cond_i1_fu_506_p2 <= (tmp_i1_fu_501_p2 and rev_fu_495_p2); or_cond_i2_fu_553_p2 <= (tmp_i2_fu_548_p2 and rev1_fu_542_p2); or_cond_i_fu_703_p2 <= (tmp_i_fu_698_p2 and rev2_fu_692_p2); p_assign_1_i_fu_745_p3 <= tmp_117_reg_1400 when (or_cond_i_reg_1409(0) = '1') else p_assign_fu_739_p3; p_assign_fu_739_p3 <= ap_const_lv11_0 when (tmp_120_reg_1414(0) = '1') else tmp_2_i_reg_1272; p_dst_data_stream_V_din <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 when (tmp_128_2_2_fu_1107_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_2_1_reg_1544; -- p_dst_data_stream_V_write assign process. -- p_dst_data_stream_V_write_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if ((not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then p_dst_data_stream_V_write <= ap_const_logic_1; else p_dst_data_stream_V_write <= ap_const_logic_0; end if; end process; p_i_i_fu_450_p3 <= ap_const_lv11_2 when (tmp_25_fu_431_p2(0) = '1') else ref_reg_1261; p_neg226_i_i_cast_fu_350_p2 <= (tmp_101_fu_346_p1 xor ap_const_lv2_3); -- p_src_data_stream_V_read assign process. -- p_src_data_stream_V_read_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then p_src_data_stream_V_read <= ap_const_logic_1; else p_src_data_stream_V_read <= ap_const_logic_0; end if; end process; ref_cast_fu_362_p1 <= std_logic_vector(resize(unsigned(ref_fu_356_p2),12)); ref_fu_356_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_7FF)); rev1_fu_542_p2 <= (tmp_113_fu_534_p3 xor ap_const_lv1_1); rev2_fu_692_p2 <= (tmp_119_fu_684_p3 xor ap_const_lv1_1); rev_fu_495_p2 <= (tmp_109_fu_487_p3 xor ap_const_lv1_1); right_border_buf_0_val_1_2_11_fu_1006_p3 <= right_border_buf_0_val_1_2_1_fu_142 when (sel_tmp2_fu_984_p2(0) = '1') else right_border_buf_0_val_1_2_fu_998_p3; right_border_buf_0_val_1_2_3_fu_838_p3 <= right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp1_fu_833_p2(0) = '1') else k_buf_0_val_1_q0; right_border_buf_0_val_1_2_4_fu_851_p3 <= right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp5_fu_846_p2(0) = '1') else right_border_buf_0_val_1_2_3_fu_838_p3; right_border_buf_0_val_1_2_5_fu_860_p3 <= k_buf_0_val_1_q0 when (sel_tmp1_fu_833_p2(0) = '1') else right_border_buf_0_val_1_2_2_fu_146; right_border_buf_0_val_1_2_6_fu_868_p3 <= right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp5_fu_846_p2(0) = '1') else right_border_buf_0_val_1_2_5_fu_860_p3; right_border_buf_0_val_1_2_8_fu_877_p3 <= k_buf_0_val_1_q0 when (sel_tmp5_fu_846_p2(0) = '1') else right_border_buf_0_val_1_2_1_fu_142; right_border_buf_0_val_1_2_fu_998_p3 <= right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp_fu_971_p2(0) = '1') else right_border_buf_0_val_1_2_7_fu_150; sel_tmp1_fu_833_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1) else "0"; sel_tmp2_fu_984_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0) else "0"; sel_tmp3_fu_579_p2 <= "1" when (locy_fu_571_p2 = ap_const_lv2_1) else "0"; sel_tmp4_fu_602_p2 <= "1" when (tmp_112_reg_1337 = tmp_80_fu_591_p3) else "0"; sel_tmp5_fu_846_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0) else "0"; sel_tmp6_fu_941_p3 <= right_border_buf_0_val_2_0_reg_1457 when (sel_tmp4_reg_1369(0) = '1') else src_kernel_win_0_val_2_0_reg_1471; sel_tmp7_fu_607_p2 <= "1" when (locy_1_t_fu_597_p2 = ap_const_lv2_1) else "0"; sel_tmp8_fu_575_p2 <= "1" when (tmp_105_reg_1310 = tmp_108_reg_1316) else "0"; sel_tmp9_fu_929_p3 <= right_border_buf_0_val_2_0_reg_1457 when (sel_tmp8_reg_1359(0) = '1') else src_kernel_win_0_val_2_0_reg_1471; sel_tmp_fu_971_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1) else "0"; src_kernel_win_0_val_0_0_fu_934_p3 <= right_border_buf_0_val_1_0_reg_1464 when (sel_tmp3_reg_1364(0) = '1') else sel_tmp9_fu_929_p3; src_kernel_win_0_val_1_0_fu_946_p3 <= right_border_buf_0_val_1_0_reg_1464 when (sel_tmp7_reg_1374(0) = '1') else sel_tmp6_fu_941_p3; temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 <= src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_1_fu_904_p2(0) = '1') else src_kernel_win_0_val_2_2_fu_134; temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 <= src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_2_fu_1021_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_0_1_reg_1477; temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 <= src_kernel_win_0_val_1_1_6_reg_1490 when (tmp_128_1_1_fu_1055_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_1_fu_1050_p3; temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 <= src_kernel_win_0_val_1_1_lo_reg_1517 when (tmp_128_1_2_fu_1070_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_1_1_reg_1523; temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 <= src_kernel_win_0_val_1_2_lo_reg_1496 when (tmp_128_1_reg_1506(0) = '1') else temp_0_i_i_i_057_i_i_1_0_2_reg_1501; temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 when (tmp_128_2_1_fu_1095_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_2_fu_1090_p3; temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 <= src_kernel_win_0_val_0_2_lo_reg_1529 when (tmp_128_2_reg_1539(0) = '1') else temp_0_i_i_i_057_i_i_1_1_2_reg_1534; tmp_100_fu_320_p1 <= p_src_cols_V_read(11 - 1 downto 0); tmp_101_fu_346_p1 <= p_src_cols_V_read(2 - 1 downto 0); tmp_102_fu_372_p1 <= p_src_rows_V_read(2 - 1 downto 0); tmp_103_fu_415_p4 <= ImagLoc_y_fu_403_p2(11 downto 1); tmp_105_fu_457_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0); tmp_106_fu_466_p1 <= ImagLoc_y_fu_403_p2(2 - 1 downto 0); tmp_107_fu_470_p1 <= ref_reg_1261(2 - 1 downto 0); tmp_108_fu_473_p3 <= tmp_106_fu_466_p1 when (tmp_i5_fu_461_p2(0) = '1') else tmp_107_fu_470_p1; tmp_109_fu_487_p3 <= y_1_fu_481_p2(11 downto 11); tmp_111_fu_520_p1 <= y_1_fu_481_p2(2 - 1 downto 0); tmp_112_fu_524_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0); tmp_113_fu_534_p3 <= y_1_1_fu_528_p2(11 downto 11); tmp_115_fu_567_p1 <= y_1_1_fu_528_p2(2 - 1 downto 0); tmp_116_fu_649_p4 <= p_025_0_i_i_reg_263(10 downto 1); tmp_117_fu_676_p1 <= ImagLoc_x_fu_670_p2(11 - 1 downto 0); tmp_118_fu_680_p1 <= ImagLoc_x_fu_670_p2(2 - 1 downto 0); tmp_119_fu_684_p3 <= ImagLoc_x_fu_670_p2(11 downto 11); tmp_121_fu_751_p1 <= p_assign_1_i_fu_745_p3(2 - 1 downto 0); tmp_128_0_1_fu_904_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(src_kernel_win_0_val_2_2_fu_134)) else "0"; tmp_128_0_2_fu_1021_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(temp_0_i_i_i_057_i_i_1_0_1_reg_1477)) else "0"; tmp_128_1_1_fu_1055_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_6_reg_1490) > unsigned(temp_0_i_i_i_057_i_i_1_1_fu_1050_p3)) else "0"; tmp_128_1_2_fu_1070_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_lo_reg_1517) > unsigned(temp_0_i_i_i_057_i_i_1_1_1_reg_1523)) else "0"; tmp_128_1_fu_1033_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_2_fu_126) > unsigned(temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3)) else "0"; tmp_128_2_1_fu_1095_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5) > unsigned(temp_0_i_i_i_057_i_i_1_2_fu_1090_p3)) else "0"; tmp_128_2_2_fu_1107_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6) > unsigned(temp_0_i_i_i_057_i_i_1_2_1_reg_1544)) else "0"; tmp_128_2_fu_1080_p2 <= "1" when (unsigned(src_kernel_win_0_val_0_2_fu_110) > unsigned(temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3)) else "0"; tmp_14_cast_fu_342_p1 <= std_logic_vector(resize(unsigned(tmp_14_fu_336_p2),12)); tmp_14_fu_336_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FD)); tmp_15_cast_cast_fu_382_p1 <= std_logic_vector(resize(unsigned(p_012_0_i_i_reg_252),12)); tmp_16_fu_386_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) < unsigned(heightloop_reg_1240)) else "0"; tmp_17_fu_397_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) > unsigned(ap_const_lv11_4)) else "0"; tmp_18_cast_fu_634_p1 <= std_logic_vector(resize(unsigned(p_025_0_i_i_reg_263),12)); tmp_19_fu_638_p2 <= "1" when (unsigned(p_025_0_i_i_reg_263) < unsigned(widthloop_reg_1245)) else "0"; tmp_23_fu_409_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ap_const_lv12_FFF)) else "0"; tmp_25_fu_431_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ref_cast_reg_1267)) else "0"; tmp_26_fu_717_p2 <= "0" when (p_025_0_i_i_reg_263 = ap_const_lv11_0) else "1"; tmp_29_fu_729_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(tmp_14_cast_reg_1250)) else "0"; tmp_2_i1_fu_376_p2 <= std_logic_vector(unsigned(tmp_102_fu_372_p1) + unsigned(ap_const_lv2_3)); tmp_2_i_fu_366_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FF)); tmp_69_fu_755_p1 <= std_logic_vector(resize(unsigned(p_assign_1_i_fu_745_p3),64)); tmp_80_fu_591_p3 <= tmp_111_reg_1332 when (or_cond_i1_reg_1322(0) = '1') else tmp_s_fu_585_p3; tmp_81_fu_613_p3 <= ap_const_lv2_0 when (tmp_114_reg_1349(0) = '1') else tmp_2_i1_reg_1277; tmp_82_fu_619_p3 <= tmp_115_reg_1354 when (or_cond_i2_reg_1344(0) = '1') else tmp_81_fu_613_p3; tmp_fu_316_p1 <= p_src_rows_V_read(11 - 1 downto 0); tmp_i1_fu_501_p2 <= "1" when (signed(y_1_fu_481_p2) < signed(p_src_rows_V_read)) else "0"; tmp_i2_fu_548_p2 <= "1" when (signed(y_1_1_fu_528_p2) < signed(p_src_rows_V_read)) else "0"; tmp_i5_fu_461_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(p_src_rows_V_read)) else "0"; tmp_i_fu_698_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(p_src_cols_V_read)) else "0"; tmp_s_fu_585_p3 <= ap_const_lv2_0 when (tmp_110_reg_1327(0) = '1') else tmp_2_i1_reg_1277; widthloop_fu_330_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_2)); y_1_1_fu_528_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFA)); y_1_fu_481_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFB)); end behav;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_dre.vhd	6	88906	------------------------------------------------------------------------------- -- axi_datamover_s2mm_dre.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_dre.vhd -- -- Description: -- This VHDL design implements a 64 bit wide (8 byte lane) function that -- realigns an arbitrarily aligned input data stream to an arbitrarily aligned -- output data stream. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n; use axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n; use axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_dre is Generic ( C_DWIDTH : Integer := 64; -- Sets the native data width of the DRE C_ALIGN_WIDTH : Integer := 3 -- Sets the width of the alignment control inputs -- Should be log2(C_DWIDTH) ); port ( -- Clock and Reset Input ---------------------------------------------- -- dre_clk : In std_logic; -- dre_rst : In std_logic; -- ---------------------------------------------------------------------- -- Alignment Control (Independent from Stream Input timing) ---------- -- dre_align_ready : Out std_logic; -- dre_align_valid : In std_logic; -- dre_use_autodest : In std_logic; -- dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); -- dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); -- ---------------------------------------------------------------------- -- Flush Control (Aligned to input Stream timing) -------------------- -- dre_flush : In std_logic; -- ---------------------------------------------------------------------- -- Stream Input Channel ---------------------------------------------- -- dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); -- dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); -- dre_in_tlast : In std_logic; -- dre_in_tvalid : In std_logic; -- dre_in_tready : Out std_logic; -- ---------------------------------------------------------------------- -- Stream Output Channel --------------------------------------------- -- dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); -- dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); -- dre_out_tlast : Out std_logic; -- dre_out_tvalid : Out std_logic; -- dre_out_tready : In std_logic -- ---------------------------------------------------------------------- ); end entity axi_datamover_s2mm_dre; architecture implementation of axi_datamover_s2mm_dre is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Functions ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_index -- -- Function Description: -- This function calculates the bus bit index corresponding -- to the MSB of the Slice lane index input and the Slice width. -- ------------------------------------------------------------------- function get_start_index (lane_index : integer; lane_width : integer) return integer is Variable bit_index_start : Integer := 0; begin bit_index_start := lane_indexlane_width; return(bit_index_start); end function get_start_index; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_index -- -- Function Description: -- This function calculates the bus bit index corresponding -- to the LSB of the Slice lane index input and the Slice width. -- ------------------------------------------------------------------- function get_end_index (lane_index : integer; lane_width : integer) return integer is Variable bit_index_end : Integer := 0; begin bit_index_end := (lane_indexlane_width) + (lane_width-1); return(bit_index_end); end function get_end_index; -- Constants Constant BYTE_WIDTH : integer := 8; -- bits Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH; Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1; Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1; Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0'); Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH; Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH; Constant NO_STRB_SET_VALUE : integer := 0; -- Types type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of std_logic_vector(SLICE_WIDTH-1 downto 0); -- Signals signal sig_input_data_reg : sig_byte_lane_type; signal sig_delay_data_reg : sig_byte_lane_type; signal sig_output_data_reg : sig_byte_lane_type; signal sig_pass_mux_bus : sig_byte_lane_type; signal sig_delay_mux_bus : sig_byte_lane_type; signal sig_final_mux_bus : sig_byte_lane_type; Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0'); Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0'); Signal sig_dre_flush_i : std_logic := '0'; Signal sig_pipeline_halt : std_logic := '0'; Signal sig_dre_tvalid_i : std_logic := '0'; Signal sig_input_accept : std_logic := '0'; Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0'); signal sig_final_mux_has_tlast : std_logic := '0'; signal sig_tlast_out : std_logic := '0'; Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0'); Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0'); Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0'); Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0'); Signal sig_auto_flush : std_logic := '0'; Signal sig_flush_db1 : std_logic := '0'; Signal sig_flush_db2 : std_logic := '0'; signal sig_flush_db1_complete : std_logic := '0'; signal sig_flush_db2_complete : std_logic := '0'; signal sig_output_xfer : std_logic := '0'; signal sig_advance_pipe_data : std_logic := '0'; Signal sig_flush_reg : std_logic := '0'; Signal sig_input_flush_stall : std_logic := '0'; Signal sig_cntl_accept : std_logic := '0'; Signal sig_dre_halted : std_logic := '0'; begin --(architecture implementation) -- Misc port assignments dre_align_ready <= sig_dre_halted or sig_flush_db2_complete ; dre_in_tready <= sig_input_accept ; dre_out_tstrb <= sig_dre_strb_out_i ; dre_out_tdata <= sig_dre_data_out_i ; dre_out_tvalid <= sig_dre_tvalid_i ; dre_out_tlast <= sig_tlast_out ; -- Internal logic sig_cntl_accept <= dre_align_valid and (sig_dre_halted or sig_flush_db2_complete); sig_pipeline_halt <= sig_dre_halted or (sig_dre_tvalid_i and not(dre_out_tready)); sig_output_xfer <= sig_dre_tvalid_i and dre_out_tready; sig_advance_pipe_data <= (dre_in_tvalid or sig_dre_flush_i) and not(sig_pipeline_halt); sig_dre_flush_i <= sig_auto_flush ; sig_input_accept <= dre_in_tvalid and not(sig_pipeline_halt) and not(sig_input_flush_stall); sig_flush_db1_complete <= sig_flush_db1 and not(sig_pipeline_halt); sig_flush_db2_complete <= sig_flush_db2 and not(sig_pipeline_halt); sig_auto_flush <= sig_flush_db1 or sig_flush_db2; sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation sig_last_written_strb <= sig_dre_strb_out_i; ------------------------------------------------------------------------------------ -- DRE Halted logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DRE_HALTED_FLOP -- -- Process Description: -- Implements a flop for the Halted state flag. All DRE -- operation is halted until a new alignment control is -- loaded. The DRE automatically goes into halted state -- at reset and at completion of a flush operation. -- ------------------------------------------------------------- IMP_DRE_HALTED_FLOP : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or (sig_flush_db2_complete = '1' and dre_align_valid = '0'))then sig_dre_halted <= '1'; -- default to halted state elsif (sig_cntl_accept = '1') then sig_dre_halted <= '0'; else null; -- hold current state end if; end if; end process IMP_DRE_HALTED_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_FLUSH_IN -- -- Process Description: -- Input Register for the flush command -- ------------------------------------------------------------- REG_FLUSH_IN : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or sig_flush_db2 = '1') then sig_flush_reg <= '0'; elsif (sig_input_accept = '1') then sig_flush_reg <= dre_flush; else null; -- hold current state end if; end if; end process REG_FLUSH_IN; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_FINAL_MUX_TLAST_OR -- -- Process Description: -- Look at all associated tlast bits in the Final Mux output -- and detirmine if any are set. -- -- ------------------------------------------------------------- DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus) Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0); begin lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX); for tlast_index in 1 to NUM_BYTE_LANES-1 loop lvar_finalmux_or(tlast_index) := lvar_finalmux_or(tlast_index-1) or sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX); end loop; sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1); end process DO_FINAL_MUX_TLAST_OR; ------------------------------------------------------------------------ ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: GEN_FLUSH_DB1 -- -- Process Description: -- Creates the first sequential flag indicating that the DRE needs to flush out -- current contents before allowing any new inputs. This is -- triggered by the receipt of the TLAST. -- ------------------------------------------------------------- GEN_FLUSH_DB1 : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then If (dre_rst = '1' or sig_flush_db2_complete = '1') Then sig_flush_db1 <= '0'; Elsif (sig_input_accept = '1') Then sig_flush_db1 <= dre_flush or dre_in_tlast; else null; -- hold state end if; -- else -- null; end if; end process GEN_FLUSH_DB1; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: GEN_FLUSH_DB2 -- -- Process Description: -- Creates a second sequential flag indicating that the DRE -- is flushing out current contents. This is -- triggered by the assertion of the first sequential flush -- flag. -- ------------------------------------------------------------- GEN_FLUSH_DB2 : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then If (dre_rst = '1' or sig_flush_db2_complete = '1') Then sig_flush_db2 <= '0'; elsif (sig_pipeline_halt = '0') then sig_flush_db2 <= sig_flush_db1; else null; -- hold state end if; -- else -- null; end if; end process GEN_FLUSH_DB2; ------------------------------------------------------------- -- Combinational Process -- -- Label: CALC_DEST_STRB_ALIGN -- -- Process Description: -- This process calculates the byte lane position of the -- left-most STRB that is unasserted on the DRE output STRB bus. -- The resulting value is used as the Destination Alignment -- Vector for the DRE. -- ------------------------------------------------------------- CALC_DEST_STRB_ALIGN : process (sig_last_written_strb) Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES; Variable lvar_strb_hole_detected : Boolean; Variable lvar_first_strb_assert_found : Boolean; Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES; Begin lvar_loop_count := NUM_BYTE_LANES; lvar_last_strb_hole_position := 0; lvar_strb_hole_detected := FALSE; lvar_first_strb_assert_found := FALSE; -- Search through the output STRB bus starting with the MSByte while (lvar_loop_count > 0) loop If (sig_last_written_strb(lvar_loop_count-1) = '0' and lvar_first_strb_assert_found = FALSE) Then lvar_strb_hole_detected := TRUE; lvar_last_strb_hole_position := lvar_loop_count-1; Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then lvar_first_strb_assert_found := true; else null; -- do nothing End if; lvar_loop_count := lvar_loop_count - 1; End loop; -- now assign the encoder output value to the bit position of the last Strobe encountered If (lvar_strb_hole_detected) Then sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH)); else sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH)); End if; end process CALC_DEST_STRB_ALIGN; ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- For Generate -- -- Label: FORMAT_OUTPUT_DATA_STRB -- -- For Generate Description: -- Connect the output Data and Strobe ports to the appropriate -- bits in the sig_output_data_reg. -- ------------------------------------------------------------ FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate begin sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto get_start_index(byte_lane_index, BYTE_WIDTH)) <= sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0); sig_dre_strb_out_i(byte_lane_index) <= sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2); end generate FORMAT_OUTPUT_DATA_STRB; ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ --------------------------------------------------------------------------------- -- Registers ------------------------------------------------------------ -- For Generate -- -- Label: GEN_INPUT_REG -- -- For Generate Description: -- -- Implements a programble number of input register slices. -- -- ------------------------------------------------------------ GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate begin ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_INPUTREG_SLICE -- -- Process Description: -- Implement a single register slice for the Input Register. -- ------------------------------------------------------------- DO_INPUTREG_SLICE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or sig_flush_db1_complete = '1' or -- clear on reset or if (dre_in_tvalid = '1' and sig_pipeline_halt = '0' and -- the pipe is being advanced and dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded sig_input_data_reg(slice_index) <= ZEROED_SLICE; elsif (dre_in_tstrb(slice_index) = '1' and sig_input_accept = '1') then sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) & dre_in_tstrb(slice_index) & dre_in_tdata((slice_index8)+7 downto slice_index8); else null; -- don't change state end if; end if; end process DO_INPUTREG_SLICE; end generate GEN_INPUT_REG; ------------------------------------------------------------ -- For Generate -- -- Label: GEN_DELAY_REG -- -- For Generate Description: -- -- Implements a programble number of output register slices -- -- ------------------------------------------------------------ GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate begin ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_DELAYREG_SLICE -- -- Process Description: -- Implement a single register slice -- ------------------------------------------------------------- DO_DELAYREG_SLICE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or -- clear on reset or if (sig_advance_pipe_data = '1' and -- the pipe is being advanced and sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded sig_delay_data_reg(slice_index) <= ZEROED_SLICE; elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and sig_advance_pipe_data = '1') then sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index); else null; -- don't change state end if; end if; end process DO_DELAYREG_SLICE; end generate GEN_DELAY_REG; ------------------------------------------------------------ -- For Generate -- -- Label: GEN_OUTPUT_REG -- -- For Generate Description: -- -- Implements a programble number of output register slices -- -- ------------------------------------------------------------ GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate begin ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_OUTREG_SLICE -- -- Process Description: -- Implement a single register slice -- ------------------------------------------------------------- DO_OUTREG_SLICE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or -- clear on reset or if (sig_output_xfer = '1' and -- the output is being transfered and sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded sig_output_data_reg(slice_index) <= ZEROED_SLICE; elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and sig_advance_pipe_data = '1') then sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index); else null; -- don't change state end if; end if; end process DO_OUTREG_SLICE; end generate GEN_OUTPUT_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: GEN_TVALID -- -- Process Description: -- This sync process generates the Write request for the -- destination interface. -- ------------------------------------------------------------- GEN_TVALID : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_dre_tvalid_i <= '0'; elsif (sig_advance_pipe_data = '1') then sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or sig_final_mux_has_tlast; -- the Last data beat of a packet Elsif (dre_out_tready = '1' and -- a completed write but no sig_dre_tvalid_i = '1') Then -- new input data so clear -- until more input data shows up sig_dre_tvalid_i <= '0'; else null; -- hold state end if; -- else -- null; end if; end process GEN_TVALID; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: GEN_TLAST_OUT -- -- Process Description: -- This sync process generates the TLAST output for the -- destination interface. -- ------------------------------------------------------------- GEN_TLAST_OUT : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_tlast_out <= '0'; elsif (sig_advance_pipe_data = '1') then sig_tlast_out <= sig_final_mux_has_tlast; Elsif (dre_out_tready = '1' and -- a completed transfer sig_dre_tvalid_i = '1') Then -- so clear tlast sig_tlast_out <= '0'; else null; -- hold state end if; -- else -- null; end if; end process GEN_TLAST_OUT; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MUXFARM_64 -- -- If Generate Description: -- Support Logic and Mux Farm for 64-bit data path case -- -- ------------------------------------------------------------ GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate Signal s_case_i_64 : Integer range 0 to 7 := 0; signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0'); Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0'); Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0'); Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0'); begin ------------------------------------------------------------- -- Combinational Process -- -- Label: FIND_MS_STRB_SET_8 -- -- Process Description: -- This process finds the most significant asserted strobe -- position. This position is used to enable the input flop -- for TLAST that is associated with that byte position. The -- TLAST can then flow through the DRE pipe with the last -- valid byte of data. -- ------------------------------------------------------------- FIND_MS_STRB_SET_8 : process (dre_in_tlast, dre_in_tstrb, sig_tlast_strobes) begin sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static if (dre_in_tlast = '0') then sig_tlast_enables <= "00000000"; elsif (sig_tlast_strobes(7) = '1') then sig_tlast_enables <= "10000000"; elsif (sig_tlast_strobes(6) = '1') then sig_tlast_enables <= "01000000"; elsif (sig_tlast_strobes(5) = '1') then sig_tlast_enables <= "00100000"; elsif (sig_tlast_strobes(4) = '1') then sig_tlast_enables <= "00010000"; elsif (sig_tlast_strobes(3) = '1') then sig_tlast_enables <= "00001000"; elsif (sig_tlast_strobes(2) = '1') then sig_tlast_enables <= "00000100"; elsif (sig_tlast_strobes(1) = '1') then sig_tlast_enables <= "00000010"; else sig_tlast_enables <= "00000001"; end if; end process FIND_MS_STRB_SET_8; --------------------------------------------------------------------------------- -- Shift Case logic -- The new auto-destination alignment is based on the last -- strobe alignment written into the output register. sig_next_auto_dest <= sig_current_dest_align; -- Select the destination alignment to use sig_dest_align_i <= sig_next_auto_dest When (dre_use_autodest = '1') Else dre_dest_align; -- Convert shift case to sld_logic_vector --sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3); sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3)); ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_SHIFT_CASE_64 -- -- Process Description: -- Implements the DRE Control State Calculator -- ------------------------------------------------------------- DO_SHIFT_CASE_64 : process (dre_src_align , sig_dest_align_i, sig_cntl_state_64) begin sig_cntl_state_64 <= dre_src_align & sig_dest_align_i; case sig_cntl_state_64 is when "000000" => s_case_i_64 <= 0; when "000001" => s_case_i_64 <= 7; when "000010" => s_case_i_64 <= 6; when "000011" => s_case_i_64 <= 5; when "000100" => s_case_i_64 <= 4; when "000101" => s_case_i_64 <= 3; when "000110" => s_case_i_64 <= 2; when "000111" => s_case_i_64 <= 1; when "001000" => s_case_i_64 <= 1; when "001001" => s_case_i_64 <= 0; when "001010" => s_case_i_64 <= 7; when "001011" => s_case_i_64 <= 6; when "001100" => s_case_i_64 <= 5; when "001101" => s_case_i_64 <= 4; when "001110" => s_case_i_64 <= 3; when "001111" => s_case_i_64 <= 2; when "010000" => s_case_i_64 <= 2; when "010001" => s_case_i_64 <= 1; when "010010" => s_case_i_64 <= 0; when "010011" => s_case_i_64 <= 7; when "010100" => s_case_i_64 <= 6; when "010101" => s_case_i_64 <= 5; when "010110" => s_case_i_64 <= 4; when "010111" => s_case_i_64 <= 3; when "011000" => s_case_i_64 <= 3; when "011001" => s_case_i_64 <= 2; when "011010" => s_case_i_64 <= 1; when "011011" => s_case_i_64 <= 0; when "011100" => s_case_i_64 <= 7; when "011101" => s_case_i_64 <= 6; when "011110" => s_case_i_64 <= 5; when "011111" => s_case_i_64 <= 4; when "100000" => s_case_i_64 <= 4; when "100001" => s_case_i_64 <= 3; when "100010" => s_case_i_64 <= 2; when "100011" => s_case_i_64 <= 1; when "100100" => s_case_i_64 <= 0; when "100101" => s_case_i_64 <= 7; when "100110" => s_case_i_64 <= 6; when "100111" => s_case_i_64 <= 5; when "101000" => s_case_i_64 <= 5; when "101001" => s_case_i_64 <= 4; when "101010" => s_case_i_64 <= 3; when "101011" => s_case_i_64 <= 2; when "101100" => s_case_i_64 <= 1; when "101101" => s_case_i_64 <= 0; when "101110" => s_case_i_64 <= 7; when "101111" => s_case_i_64 <= 6; when "110000" => s_case_i_64 <= 6; when "110001" => s_case_i_64 <= 5; when "110010" => s_case_i_64 <= 4; when "110011" => s_case_i_64 <= 3; when "110100" => s_case_i_64 <= 2; when "110101" => s_case_i_64 <= 1; when "110110" => s_case_i_64 <= 0; when "110111" => s_case_i_64 <= 7; when "111000" => s_case_i_64 <= 7; when "111001" => s_case_i_64 <= 6; when "111010" => s_case_i_64 <= 5; when "111011" => s_case_i_64 <= 4; when "111100" => s_case_i_64 <= 3; when "111101" => s_case_i_64 <= 2; when "111110" => s_case_i_64 <= 1; when "111111" => s_case_i_64 <= 0; when others => NULL; end case; end process DO_SHIFT_CASE_64; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SHIFT_CASE -- -- Process Description: -- This process registers the Shift Case output from the -- Shift Case Generator. This will be used to control the -- select inputs of the Shift Muxes for the duration of the -- data transfer session. If Pass Through is requested, then -- Shift Case 0 is forced regardless of source and destination -- alignment values. -- ------------------------------------------------------------- REG_SHIFT_CASE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_shift_case_reg <= (others => '0'); elsif (sig_cntl_accept = '1') then sig_shift_case_reg <= sig_shift_case_i; else null; -- hold state end if; -- else -- null; end if; end process REG_SHIFT_CASE; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start PASS Mux Farm Design------------------------------------------------- -- Pass Mux Byte 0 (wire) -- This is a wire so..... sig_pass_mux_bus(0) <= sig_input_data_reg(0); -- Pass Mux Byte 1 (2-1 x8 Mux) I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(0), I0 => sig_input_data_reg(1), I1 => sig_input_data_reg(0), Y => sig_pass_mux_bus(1) ); -- Pass Mux Byte 2 (4-1 x8 Mux) I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(2) , I1 => ZEROED_SLICE , I2 => sig_input_data_reg(0) , I3 => sig_input_data_reg(1) , Y => sig_pass_mux_bus(2) ); -- Pass Mux Byte 3 (4-1 x8 Mux) I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(3) , I1 => sig_input_data_reg(0) , I2 => sig_input_data_reg(1) , I3 => sig_input_data_reg(2) , Y => sig_pass_mux_bus(3) ); -- Pass Mux Byte 4 (8-1 x8 Mux) I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => sig_input_data_reg(4) , I1 => ZEROED_SLICE , I2 => ZEROED_SLICE , I3 => ZEROED_SLICE , I4 => sig_input_data_reg(0) , I5 => sig_input_data_reg(1) , I6 => sig_input_data_reg(2) , I7 => sig_input_data_reg(3) , Y => sig_pass_mux_bus(4) ); -- Pass Mux Byte 5 (8-1 x8 Mux) I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => sig_input_data_reg(5) , I1 => ZEROED_SLICE , I2 => ZEROED_SLICE , I3 => sig_input_data_reg(0) , I4 => sig_input_data_reg(1) , I5 => sig_input_data_reg(2) , I6 => sig_input_data_reg(3) , I7 => sig_input_data_reg(4) , Y => sig_pass_mux_bus(5) ); -- Pass Mux Byte 6 (8-1 x8 Mux) I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => sig_input_data_reg(6) , I1 => ZEROED_SLICE , I2 => sig_input_data_reg(0) , I3 => sig_input_data_reg(1) , I4 => sig_input_data_reg(2) , I5 => sig_input_data_reg(3) , I6 => sig_input_data_reg(4) , I7 => sig_input_data_reg(5) , Y => sig_pass_mux_bus(6) ); -- Pass Mux Byte 7 (8-1 x8 Mux) I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => sig_input_data_reg(7) , I1 => sig_input_data_reg(0) , I2 => sig_input_data_reg(1) , I3 => sig_input_data_reg(2) , I4 => sig_input_data_reg(3) , I5 => sig_input_data_reg(4) , I6 => sig_input_data_reg(5) , I7 => sig_input_data_reg(6) , Y => sig_pass_mux_bus(7) ); -- End PASS Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Delay Mux Farm Design------------------------------------------------- -- Delay Mux Byte 0 (8-1 x8 Mux) I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0) , I0 => ZEROED_SLICE , I1 => sig_input_data_reg(1) , I2 => sig_input_data_reg(2) , I3 => sig_input_data_reg(3) , I4 => sig_input_data_reg(4) , I5 => sig_input_data_reg(5) , I6 => sig_input_data_reg(6) , I7 => sig_input_data_reg(7) , Y => sig_delay_mux_bus(0) ); -- Delay Mux Byte 1 (8-1 x8 Mux) I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => ZEROED_SLICE , I1 => sig_input_data_reg(2) , I2 => sig_input_data_reg(3) , I3 => sig_input_data_reg(4) , I4 => sig_input_data_reg(5) , I5 => sig_input_data_reg(6) , I6 => sig_input_data_reg(7) , I7 => ZEROED_SLICE , Y => sig_delay_mux_bus(1) ); -- Delay Mux Byte 2 (8-1 x8 Mux) I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => ZEROED_SLICE , I1 => sig_input_data_reg(3) , I2 => sig_input_data_reg(4) , I3 => sig_input_data_reg(5) , I4 => sig_input_data_reg(6) , I5 => sig_input_data_reg(7) , I6 => ZEROED_SLICE , I7 => ZEROED_SLICE , Y => sig_delay_mux_bus(2) ); -- Delay Mux Byte 3 (4-1 x8 Mux) I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(7) , I1 => sig_input_data_reg(4) , I2 => sig_input_data_reg(5) , I3 => sig_input_data_reg(6) , Y => sig_delay_mux_bus(3) ); -- Delay Mux Byte 4 (4-1 x8 Mux) I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => ZEROED_SLICE , I1 => sig_input_data_reg(5) , I2 => sig_input_data_reg(6) , I3 => sig_input_data_reg(7) , Y => sig_delay_mux_bus(4) ); -- Delay Mux Byte 5 (2-1 x8 Mux) I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH -- : Integer := 8 ) port map( Sel => sig_shift_case_reg(0), I0 => sig_input_data_reg(7), I1 => sig_input_data_reg(6), Y => sig_delay_mux_bus(5) ); -- Delay Mux Byte 6 (Wire) sig_delay_mux_bus(6) <= sig_input_data_reg(7); -- Delay Mux Byte 7 (Zeroed) sig_delay_mux_bus(7) <= ZEROED_SLICE; -- End Delay Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Final Mux Farm Design------------------------------------------------- -- Final Mux Byte 0 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B0_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 0 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(0) <= '0'; when "001" => sig_final_mux_sel(0) <= '1'; when "010" => sig_final_mux_sel(0) <= '1'; when "011" => sig_final_mux_sel(0) <= '1'; when "100" => sig_final_mux_sel(0) <= '1'; when "101" => sig_final_mux_sel(0) <= '1'; when "110" => sig_final_mux_sel(0) <= '1'; when "111" => sig_final_mux_sel(0) <= '1'; when others => sig_final_mux_sel(0) <= '0'; end case; end process MUX2_1_FINAL_B0_CNTL; I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(0) , I0 => sig_input_data_reg(0), I1 => sig_delay_data_reg(0), Y => sig_final_mux_bus(0) ); -- Final Mux Byte 1 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B1_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 1 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(1) <= '0'; when "001" => sig_final_mux_sel(1) <= '1'; when "010" => sig_final_mux_sel(1) <= '1'; when "011" => sig_final_mux_sel(1) <= '1'; when "100" => sig_final_mux_sel(1) <= '1'; when "101" => sig_final_mux_sel(1) <= '1'; when "110" => sig_final_mux_sel(1) <= '1'; when "111" => sig_final_mux_sel(1) <= '0'; when others => sig_final_mux_sel(1) <= '0'; end case; end process MUX2_1_FINAL_B1_CNTL; I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(1) , I0 => sig_pass_mux_bus(1) , I1 => sig_delay_data_reg(1), Y => sig_final_mux_bus(1) ); -- Final Mux Byte 2 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B2_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 2 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(2) <= '0'; when "001" => sig_final_mux_sel(2) <= '1'; when "010" => sig_final_mux_sel(2) <= '1'; when "011" => sig_final_mux_sel(2) <= '1'; when "100" => sig_final_mux_sel(2) <= '1'; when "101" => sig_final_mux_sel(2) <= '1'; when "110" => sig_final_mux_sel(2) <= '0'; when "111" => sig_final_mux_sel(2) <= '0'; when others => sig_final_mux_sel(2) <= '0'; end case; end process MUX2_1_FINAL_B2_CNTL; I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(2) , I0 => sig_pass_mux_bus(2) , I1 => sig_delay_data_reg(2), Y => sig_final_mux_bus(2) ); -- Final Mux Byte 3 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B3_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 3 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(3) <= '0'; when "001" => sig_final_mux_sel(3) <= '1'; when "010" => sig_final_mux_sel(3) <= '1'; when "011" => sig_final_mux_sel(3) <= '1'; when "100" => sig_final_mux_sel(3) <= '1'; when "101" => sig_final_mux_sel(3) <= '0'; when "110" => sig_final_mux_sel(3) <= '0'; when "111" => sig_final_mux_sel(3) <= '0'; when others => sig_final_mux_sel(3) <= '0'; end case; end process MUX2_1_FINAL_B3_CNTL; I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(3) , I0 => sig_pass_mux_bus(3) , I1 => sig_delay_data_reg(3), Y => sig_final_mux_bus(3) ); -- Final Mux Byte 4 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B4_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 4 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(4) <= '0'; when "001" => sig_final_mux_sel(4) <= '1'; when "010" => sig_final_mux_sel(4) <= '1'; when "011" => sig_final_mux_sel(4) <= '1'; when "100" => sig_final_mux_sel(4) <= '0'; when "101" => sig_final_mux_sel(4) <= '0'; when "110" => sig_final_mux_sel(4) <= '0'; when "111" => sig_final_mux_sel(4) <= '0'; when others => sig_final_mux_sel(4) <= '0'; end case; end process MUX2_1_FINAL_B4_CNTL; I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(4) , I0 => sig_pass_mux_bus(4) , I1 => sig_delay_data_reg(4), Y => sig_final_mux_bus(4) ); -- Final Mux Byte 5 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B5_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 5 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(5) <= '0'; when "001" => sig_final_mux_sel(5) <= '1'; when "010" => sig_final_mux_sel(5) <= '1'; when "011" => sig_final_mux_sel(5) <= '0'; when "100" => sig_final_mux_sel(5) <= '0'; when "101" => sig_final_mux_sel(5) <= '0'; when "110" => sig_final_mux_sel(5) <= '0'; when "111" => sig_final_mux_sel(5) <= '0'; when others => sig_final_mux_sel(5) <= '0'; end case; end process MUX2_1_FINAL_B5_CNTL; I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(5) , I0 => sig_pass_mux_bus(5) , I1 => sig_delay_data_reg(5), Y => sig_final_mux_bus(5) ); -- Final Mux Byte 6 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B6_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 6 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(6) <= '0'; when "001" => sig_final_mux_sel(6) <= '1'; when "010" => sig_final_mux_sel(6) <= '0'; when "011" => sig_final_mux_sel(6) <= '0'; when "100" => sig_final_mux_sel(6) <= '0'; when "101" => sig_final_mux_sel(6) <= '0'; when "110" => sig_final_mux_sel(6) <= '0'; when "111" => sig_final_mux_sel(6) <= '0'; when others => sig_final_mux_sel(6) <= '0'; end case; end process MUX2_1_FINAL_B6_CNTL; I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(6) , I0 => sig_pass_mux_bus(6) , I1 => sig_delay_data_reg(6), Y => sig_final_mux_bus(6) ); -- Final Mux Byte 7 (wire) sig_final_mux_sel(7) <= '0'; sig_final_mux_bus(7) <= sig_pass_mux_bus(7); -- End Final Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- end generate GEN_MUXFARM_64; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MUXFARM_32 -- -- If Generate Description: -- Support Logic and Mux Farm for 32-bit data path case -- -- ------------------------------------------------------------ GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate Signal s_case_i_32 : Integer range 0 to 3 := 0; signal sig_cntl_state_32 : std_logic_vector(3 downto 0) := (others => '0'); Signal sig_shift_case_i : std_logic_vector(1 downto 0) := (others => '0'); Signal sig_shift_case_reg : std_logic_vector(1 downto 0) := (others => '0'); Signal sig_final_mux_sel : std_logic_vector(3 downto 0) := (others => '0'); begin ------------------------------------------------------------- -- Combinational Process -- -- Label: FIND_MS_STRB_SET_4 -- -- Process Description: -- This process finds the most significant asserted strobe -- position. This position is used to enable the input flop -- for TLAST that is associated with that byte position. The -- TLAST can then flow through the DRE pipe with the last -- valid byte of data. -- ------------------------------------------------------------- FIND_MS_STRB_SET_4 : process (dre_in_tlast, dre_in_tstrb, sig_tlast_strobes) begin sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static if (dre_in_tlast = '0') then sig_tlast_enables <= "0000"; elsif (sig_tlast_strobes(3) = '1') then sig_tlast_enables <= "1000"; elsif (sig_tlast_strobes(2) = '1') then sig_tlast_enables <= "0100"; elsif (sig_tlast_strobes(1) = '1') then sig_tlast_enables <= "0010"; else sig_tlast_enables <= "0001"; end if; end process FIND_MS_STRB_SET_4; --------------------------------------------------------------------------------- -- Shift Case logic -- The new auto-destination alignment is based on the last -- strobe alignment written into the output register. sig_next_auto_dest <= sig_current_dest_align; -- Select the destination alignment to use sig_dest_align_i <= sig_next_auto_dest When (dre_use_autodest = '1') Else dre_dest_align; -- Convert shift case to sld_logic_vector --sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2); sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2)); ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_SHIFT_CASE_32 -- -- Process Description: -- Implements the DRE Control State Calculator -- ------------------------------------------------------------- DO_SHIFT_CASE_32 : process (dre_src_align , sig_dest_align_i, sig_cntl_state_32) begin sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0); case sig_cntl_state_32 is when "0000" => s_case_i_32 <= 0; when "0001" => s_case_i_32 <= 3; when "0010" => s_case_i_32 <= 2; when "0011" => s_case_i_32 <= 1; when "0100" => s_case_i_32 <= 1; when "0101" => s_case_i_32 <= 0; when "0110" => s_case_i_32 <= 3; when "0111" => s_case_i_32 <= 2; when "1000" => s_case_i_32 <= 2; when "1001" => s_case_i_32 <= 1; when "1010" => s_case_i_32 <= 0; when "1011" => s_case_i_32 <= 3; when "1100" => s_case_i_32 <= 3; when "1101" => s_case_i_32 <= 2; when "1110" => s_case_i_32 <= 1; when "1111" => s_case_i_32 <= 0; when others => NULL; end case; end process DO_SHIFT_CASE_32; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SHIFT_CASE -- -- Process Description: -- This process registers the Shift Case output from the -- Shift Case Generator. This will be used to control the -- select inputs of the Shift Muxes for the duration of the -- data transfer session. If Pass Through is requested, then -- Shift Case 0 is forced regardless of source and destination -- alignment values. -- ------------------------------------------------------------- REG_SHIFT_CASE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_shift_case_reg <= (others => '0'); elsif (sig_cntl_accept = '1') then sig_shift_case_reg <= sig_shift_case_i; else null; -- hold state end if; -- else -- null; end if; end process REG_SHIFT_CASE; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start PASS Mux Farm Design------------------------------------------------- -- Pass Mux Byte 0 (wire) -- This is a wire so..... sig_pass_mux_bus(0) <= sig_input_data_reg(0); -- Pass Mux Byte 1 (2-1 x8 Mux) I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(0), I0 => sig_input_data_reg(1), I1 => sig_input_data_reg(0), Y => sig_pass_mux_bus(1) ); -- Pass Mux Byte 2 (4-1 x8 Mux) I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(2) , I1 => ZEROED_SLICE , I2 => sig_input_data_reg(0) , I3 => sig_input_data_reg(1) , Y => sig_pass_mux_bus(2) ); -- Pass Mux Byte 3 (4-1 x8 Mux) I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(3) , I1 => sig_input_data_reg(0) , I2 => sig_input_data_reg(1) , I3 => sig_input_data_reg(2) , Y => sig_pass_mux_bus(3) ); -- End PASS Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Delay Mux Farm Design------------------------------------------------- -- Delay Mux Byte 0 (4-1 x8 Mux) I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => ZEROED_SLICE , I1 => sig_input_data_reg(1) , I2 => sig_input_data_reg(2) , I3 => sig_input_data_reg(3) , Y => sig_delay_mux_bus(0) ); -- Delay Mux Byte 1 (2-1 x8 Mux) I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(0), I0 => sig_input_data_reg(3), I1 => sig_input_data_reg(2), Y => sig_delay_mux_bus(1) ); -- Delay Mux Byte 2 (Wire) sig_delay_mux_bus(2) <= sig_input_data_reg(3); -- Delay Mux Byte 3 (Zeroed) sig_delay_mux_bus(3) <= ZEROED_SLICE; -- End Delay Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Final Mux Farm Design------------------------------------------------- -- Final Mux Slice 0 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B0_CNTL -- -- Process Description: -- This process generates the Select Control for Slice 0 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "00" => sig_final_mux_sel(0) <= '0'; when "01" => sig_final_mux_sel(0) <= '1'; when "10" => sig_final_mux_sel(0) <= '1'; when "11" => sig_final_mux_sel(0) <= '1'; when others => sig_final_mux_sel(0) <= '0'; end case; end process MUX2_1_FINAL_B0_CNTL; I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(0) , I0 => sig_pass_mux_bus(0) , I1 => sig_delay_data_reg(0), Y => sig_final_mux_bus(0) ); -- Final Mux Slice 1 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B1_CNTL -- -- Process Description: -- This process generates the Select Control for slice 1 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "00" => sig_final_mux_sel(1) <= '0'; when "01" => sig_final_mux_sel(1) <= '1'; when "10" => sig_final_mux_sel(1) <= '1'; when "11" => sig_final_mux_sel(1) <= '0'; when others => sig_final_mux_sel(1) <= '0'; end case; end process MUX2_1_FINAL_B1_CNTL; I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(1) , I0 => sig_pass_mux_bus(1) , I1 => sig_delay_data_reg(1), Y => sig_final_mux_bus(1) ); -- Final Mux Slice 2 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B2_CNTL -- -- Process Description: -- This process generates the Select Control for Slice 2 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "00" => sig_final_mux_sel(2) <= '0'; when "01" => sig_final_mux_sel(2) <= '1'; when "10" => sig_final_mux_sel(2) <= '0'; when "11" => sig_final_mux_sel(2) <= '0'; when others => sig_final_mux_sel(2) <= '0'; end case; end process MUX2_1_FINAL_B2_CNTL; I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(2) , I0 => sig_pass_mux_bus(2) , I1 => sig_delay_data_reg(2), Y => sig_final_mux_bus(2) ); -- Final Mux Slice 3 (wire) sig_final_mux_sel(3) <= '0'; sig_final_mux_bus(3) <= sig_pass_mux_bus(3); -- End Final Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- end generate GEN_MUXFARM_32; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MUXFARM_16 -- -- If Generate Description: -- Support Logic and Mux Farm for 16-bit data path case -- -- ------------------------------------------------------------ GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate Signal s_case_i_16 : Integer range 0 to 1 := 0; signal sig_cntl_state_16 : std_logic_vector(1 downto 0) := (others => '0'); Signal sig_shift_case_i : std_logic := '0'; Signal sig_shift_case_reg : std_logic := '0'; Signal sig_final_mux_sel : std_logic_vector(1 downto 0) := (others => '0'); begin ------------------------------------------------------------- -- Combinational Process -- -- Label: FIND_MS_STRB_SET_2 -- -- Process Description: -- This process finds the most significant asserted strobe -- position. This position is used to enable the input flop -- for TLAST that is associated with that byte position. The -- TLAST can then flow through the DRE pipe with the last -- valid byte of data. -- ------------------------------------------------------------- FIND_MS_STRB_SET_2 : process (dre_in_tlast, dre_in_tstrb, sig_tlast_strobes) begin sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static if (dre_in_tlast = '0') then sig_tlast_enables <= "00"; elsif (sig_tlast_strobes(1) = '1') then sig_tlast_enables <= "10"; else sig_tlast_enables <= "01"; end if; end process FIND_MS_STRB_SET_2; --------------------------------------------------------------------------------- -- Shift Case logic -- The new auto-destination alignment is based on the last -- strobe alignment written into the output register. sig_next_auto_dest <= sig_current_dest_align; -- Select the destination alignment to use sig_dest_align_i <= sig_next_auto_dest When (dre_use_autodest = '1') Else dre_dest_align; -- Convert shift case to std_logic sig_shift_case_i <= '1' When s_case_i_16 = 1 Else '0'; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_SHIFT_CASE_16 -- -- Process Description: -- Implements the DRE Control State Calculator -- ------------------------------------------------------------- DO_SHIFT_CASE_16 : process (dre_src_align , sig_dest_align_i, sig_cntl_state_16) begin sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0); case sig_cntl_state_16 is when "00" => s_case_i_16 <= 0; when "01" => s_case_i_16 <= 1; when "10" => s_case_i_16 <= 1; when "11" => s_case_i_16 <= 0; when others => NULL; end case; end process DO_SHIFT_CASE_16; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SHIFT_CASE -- -- Process Description: -- This process registers the Shift Case output from the -- Shift Case Generator. This will be used to control the -- select inputs of the Shift Muxes for the duration of the -- data transfer session. If Pass Through is requested, then -- Shift Case 0 is forced regardless of source and destination -- alignment values. -- ------------------------------------------------------------- REG_SHIFT_CASE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_shift_case_reg <= '0'; elsif (sig_cntl_accept = '1') then sig_shift_case_reg <= sig_shift_case_i; else null; -- hold state end if; -- else -- null; end if; end process REG_SHIFT_CASE; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start PASS Mux Farm Design------------------------------------------------- -- Pass Mux Byte 0 (wire) -- This is a wire so..... sig_pass_mux_bus(0) <= sig_input_data_reg(0); -- Pass Mux Byte 1 (2-1 x8 Mux) I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg, I0 => sig_input_data_reg(1), I1 => sig_input_data_reg(0), Y => sig_pass_mux_bus(1) ); -- End PASS Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Delay Mux Farm Design------------------------------------------------- -- Delay Mux Slice 0 (Wire) sig_delay_mux_bus(0) <= sig_input_data_reg(1); -- Delay Mux Slice 1 (Zeroed) sig_delay_mux_bus(1) <= ZEROED_SLICE; -- End Delay Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Final Mux Farm Design------------------------------------------------- -- Final Mux Slice 0 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B0_CNTL -- -- Process Description: -- This process generates the Select Control for Slice 0 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when '0' => sig_final_mux_sel(0) <= '0'; when others => sig_final_mux_sel(0) <= '1'; end case; end process MUX2_1_FINAL_B0_CNTL; I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(0) , I0 => sig_pass_mux_bus(0) , I1 => sig_delay_data_reg(0), Y => sig_final_mux_bus(0) ); -- Final Mux Slice 1 (wire) sig_final_mux_sel(1) <= '0'; sig_final_mux_bus(1) <= sig_pass_mux_bus(1); -- End Final Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- end generate GEN_MUXFARM_16; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/axi_bram_ctrl_top.vhd	6	43430	------------------------------------------------------------------------------- -- axi_bram_ctrl_top.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_bram_ctrl_top.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller IP core. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl_top.vhd (v4_0) -- \| -- \|-- full_axi.vhd -- \| -- sng_port_arb.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- wr_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \| -- rd_chnl.vhd -- \| -- wrap_brst.vhd -- \| -- ua_narrow.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- checkbit_handler_64.vhd -- \| -- (same helper components as checkbit_handler) -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- correct_one_bit_64.vhd -- \| -- ecc_gen.vhd -- \| -- \|-- axi_lite.vhd -- \| -- lite_ecc_reg.vhd -- \| -- axi_lite_if.vhd -- \| -- checkbit_handler.vhd -- \| -- xor18.vhd -- \| -- parity.vhd -- \| -- correct_one_bit.vhd -- \| -- ecc_gen.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/9/2011 v1.03a -- ~~~~~~ -- Update Create_Size_Default function to support 512 & 1024-bit BRAM. -- Replace usage of Create_Size_Default function. -- ^^^^^^ -- JLJ 2/15/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter on full_axi module. -- Update ECC signal sizes for 128-bit support. -- ^^^^^^ -- JLJ 2/16/2011 v1.03a -- ~~~~~~ -- Update WE size based on 128-bit ECC configuration. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Add C_ECC_TYPE top level parameter on axi_lite module. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Set C_ECC_TYPE = 1 for Hsiao DV regressions. -- ^^^^^^ -- JLJ 2/24/2011 v1.03a -- ~~~~~~ -- Move Find_ECC_Size function to package. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove C_FAMILY from top level. -- Remove C_FAMILY in axi_lite sub module. -- ^^^^^^ -- JLJ 6/23/2011 v1.03a -- ~~~~~~ -- Migrate 9-bit ECC to 16-bit ECC for 128-bit BRAM data width. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; library work; use work.axi_lite; use work.full_axi; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity axi_bram_ctrl_top is generic ( -- AXI Parameters C_BRAM_ADDR_WIDTH : integer := 12; -- Width of AXI address bus (in bits) C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1; -- Support for narrow burst operations C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_TYPE : integer := 1; C_FAULT_INJECT : integer := 0; -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE : integer := 1 -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) -- Reserved parameters for future implementations. -- C_ENABLE_AXI_CTRL_REG_IF : integer := 1; -- By default the ECC AXI-Lite register interface is enabled -- C_CE_FAILING_REGISTERS : integer := 1; -- Enable CE (correctable error) failing registers -- C_UE_FAILING_REGISTERS : integer := 1; -- Enable UE (uncorrectable error) failing registers -- C_ECC_STATUS_REGISTERS : integer := 1; -- Enable ECC status registers -- C_ECC_ONOFF_REGISTER : integer := 1; -- Enable ECC on/off control register -- C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; ECC_Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- AXI Write Address Channel Signals (AW) S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWLEN : in std_logic_vector(7 downto 0); S_AXI_AWSIZE : in std_logic_vector(2 downto 0); S_AXI_AWBURST : in std_logic_vector(1 downto 0); S_AXI_AWLOCK : in std_logic; S_AXI_AWCACHE : in std_logic_vector(3 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; -- AXI Write Data Channel Signals (W) S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); S_AXI_WLAST : in std_logic; S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; -- AXI Write Data Response Channel Signals (B) S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; -- AXI Read Address Channel Signals (AR) S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARLEN : in std_logic_vector(7 downto 0); S_AXI_ARSIZE : in std_logic_vector(2 downto 0); S_AXI_ARBURST : in std_logic_vector(1 downto 0); S_AXI_ARLOCK : in std_logic; S_AXI_ARCACHE : in std_logic_vector(3 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; -- AXI Read Data Channel Signals (R) S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RLAST : out std_logic; S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- AXI-Lite ECC Register Interface Signals -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_ACLK : in std_logic; -- S_AXI_CTRL_ARESETN : in std_logic; -- AXI-Lite Write Address Channel Signals (AW) S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic; -- BRAM Interface Signals (Port A) BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_En_A : out std_logic; BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- BRAM Interface Signals (Port B) BRAM_Rst_B : out std_logic; BRAM_Clk_B : out std_logic; BRAM_En_B : out std_logic; BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC8(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) ); end entity axi_bram_ctrl_top; ------------------------------------------------------------------------------- architecture implementation of axi_bram_ctrl_top is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Model behavior of AXI Interconnect in simulation for wrapping of ID values. constant C_SIM_ONLY : std_logic := '1'; -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; -- Create top level constant to assign fixed value to ARSIZE and AWSIZE -- when narrow bursting is parameterized out of the IP core instantiation. -- constant AXI_FIXED_SIZE_WO_NARROW : std_logic_vector (2 downto 0) := Create_Size_Default; -- v1.03a constant AXI_FIXED_SIZE_WO_NARROW : integer := log2 (C_S_AXI_DATA_WIDTH/8); -- Only instantiate logic based on C_S_AXI_PROTOCOL. constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Determine external ECC width. -- Use function defined in axi_bram_ctrl_funcs package. constant C_ECC_WIDTH : integer := Find_ECC_Size (C_ECC, C_S_AXI_DATA_WIDTH); constant C_ECC_FULL_BIT_WIDTH : integer := Find_ECC_Full_Bit_Size (C_ECC, C_S_AXI_DATA_WIDTH); -- Set internal parameters for ECC register enabling when C_ECC = 1 constant C_ENABLE_AXI_CTRL_REG_IF_I : integer := C_ECC; constant C_CE_FAILING_REGISTERS_I : integer := C_ECC; constant C_UE_FAILING_REGISTERS_I : integer := 0; -- Remove all UE registers -- Catastrophic error indicated with ECC_UE & Interrupt flags. constant C_ECC_STATUS_REGISTERS_I : integer := C_ECC; constant C_ECC_ONOFF_REGISTER_I : integer := C_ECC; constant C_CE_COUNTER_WIDTH : integer := 8 * C_ECC; -- Counter only sized when C_ECC = 1. -- Selects CE counter width/threshold to assert ECC_Interrupt -- Hard coded at 8-bits to capture and count up to 256 correctable errors. --constant C_ECC_TYPE : integer := 1; -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- -- Internal BRAM Signals -- Port A signal bram_en_a_int : std_logic := '0'; signal bram_we_a_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0'); signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); signal bram_rddata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port B signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_en_b_int : std_logic := '0'; signal bram_we_b_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0'); signal bram_wrdata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); signal bram_rddata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); signal axi_awsize_int : std_logic_vector(2 downto 0) := (others => '0'); signal axi_arsize_int : std_logic_vector(2 downto 0) := (others => '0'); signal S_AXI_ARREADY_int : std_logic := '0'; signal S_AXI_AWREADY_int : std_logic := '0'; signal S_AXI_RID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal S_AXI_BID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin -- * BRAM Port A Output Signals * BRAM_Rst_A <= not (S_AXI_ARESETN); BRAM_Clk_A <= S_AXI_ACLK; BRAM_En_A <= bram_en_a_int; BRAM_WE_A ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_a_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0); BRAM_Addr_A <= bram_addr_a_int; bram_rddata_a_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)); BRAM_WrData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH-1 downto 0); -- Added for 13.3 -- Drive unused upper ECC bits to '0' -- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case. GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate begin BRAM_WrData_A ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0'); BRAM_WrData_A ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0); end generate GEN_128_ECC_WR; GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate begin BRAM_WrData_A ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0); end generate GEN_ECC_WR; -- * BRAM Port B Output Signals * GEN_PORT_B: if (C_SINGLE_PORT_BRAM = 0) generate begin BRAM_Rst_B <= not (S_AXI_ARESETN); BRAM_WE_B ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_b_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0); BRAM_Addr_B <= bram_addr_b_int; BRAM_En_B <= bram_en_b_int; bram_rddata_b_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)); BRAM_WrData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH-1 downto 0); -- 13.3 -- BRAM_WrData_B <= bram_wrdata_b_int; -- Added for 13.3 -- Drive unused upper ECC bits to '0' -- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case. GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate begin BRAM_WrData_B ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0'); BRAM_WrData_B ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0); end generate GEN_128_ECC_WR; GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate begin BRAM_WrData_B ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0); end generate GEN_ECC_WR; end generate GEN_PORT_B; GEN_NO_PORT_B: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_Rst_B <= '0'; BRAM_WE_B <= (others => '0'); BRAM_WrData_B <= (others => '0'); BRAM_Addr_B <= (others => '0'); BRAM_En_B <= '0'; end generate GEN_NO_PORT_B; --------------------------------------------------------------------------- -- -- Generate: GEN_BRAM_CLK_B -- Purpose: Only drive BRAM_Clk_B when dual port BRAM is enabled. -- --------------------------------------------------------------------------- GEN_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 0) generate begin BRAM_Clk_B <= S_AXI_ACLK; end generate GEN_BRAM_CLK_B; --------------------------------------------------------------------------- -- -- Generate: GEN_NO_BRAM_CLK_B -- Purpose: Drive default value for BRAM_Clk_B when single port -- BRAM is enabled and no clock is necessary on the inactive -- BRAM port. -- --------------------------------------------------------------------------- GEN_NO_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_Clk_B <= '0'; end generate GEN_NO_BRAM_CLK_B; --------------------------------------------------------------------------- -- Generate top level ARSIZE and AWSIZE signals for rd_chnl and wr_chnl -- respectively, based on design parameter setting of generic, -- C_S_AXI_SUPPORTS_NARROW_BURST. --------------------------------------------------------------------------- -- -- Generate: GEN_W_NARROW -- Purpose: Create internal AWSIZE and ARSIZE signal for write and -- read channel modules based on top level AXI signal inputs. -- --------------------------------------------------------------------------- GEN_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 1) and (IF_IS_AXI4) generate begin axi_awsize_int <= S_AXI_AWSIZE; axi_arsize_int <= S_AXI_ARSIZE; end generate GEN_W_NARROW; --------------------------------------------------------------------------- -- -- Generate: GEN_WO_NARROW -- Purpose: Create internal AWSIZE and ARSIZE signal for write and -- read channel modules based on hard coded -- value that indicates all AXI transfers will be equal in -- size to the AXI data bus. -- --------------------------------------------------------------------------- GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 0) or (IF_IS_AXI4LITE) generate begin -- axi_awsize_int <= AXI_FIXED_SIZE_WO_NARROW; -- When AXI-LITE (no narrow transfers supported) -- axi_arsize_int <= AXI_FIXED_SIZE_WO_NARROW; -- v1.03a axi_awsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3)); axi_arsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3)); end generate GEN_WO_NARROW; S_AXI_ARREADY <= S_AXI_ARREADY_int; S_AXI_AWREADY <= S_AXI_AWREADY_int; --------------------------------------------------------------------------- -- -- Generate: GEN_AXI_LITE -- Purpose: Create internal signals for lower level write and read -- channel modules to discard unused AXI signals when the -- AXI protocol is set up for AXI-LITE. -- --------------------------------------------------------------------------- GEN_AXI4LITE: if (IF_IS_AXI4LITE) generate begin -- For simulation purposes ONLY -- AXI Interconnect handles this in real system topologies. S_AXI_BID <= S_AXI_BID_int; S_AXI_RID <= S_AXI_RID_int; ----------------------------------------------------------------------- -- -- Generate: GEN_SIM_ONLY -- Purpose: Mimic behavior of AXI Interconnect in simulation. -- In real hardware system, AXI Interconnect stores and -- wraps value of ARID to RID and AWID to BID. -- ----------------------------------------------------------------------- GEN_SIM_ONLY: if (C_SIM_ONLY = '1') generate begin ------------------------------------------------------------------- -- Must register and wrap the AWID signal REG_BID: process (S_AXI_ACLK) begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if (S_AXI_ARESETN = C_RESET_ACTIVE) then S_AXI_BID_int <= (others => '0'); elsif (S_AXI_AWVALID = '1') and (S_AXI_AWREADY_int = '1') then S_AXI_BID_int <= S_AXI_AWID; else S_AXI_BID_int <= S_AXI_BID_int; end if; end if; end process REG_BID; ------------------------------------------------------------------- -- Must register and wrap the ARID signal REG_RID: process (S_AXI_ACLK) begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if (S_AXI_ARESETN = C_RESET_ACTIVE) then S_AXI_RID_int <= (others => '0'); elsif (S_AXI_ARVALID = '1') and (S_AXI_ARREADY_int = '1') then S_AXI_RID_int <= S_AXI_ARID; else S_AXI_RID_int <= S_AXI_RID_int; end if; end if; end process REG_RID; ------------------------------------------------------------------- end generate GEN_SIM_ONLY; --------------------------------------------------------------------------- -- -- Generate: GEN_HW -- Purpose: Drive default values of RID and BID. In real system -- these are left unconnected and AXI Interconnect is -- responsible for values. -- --------------------------------------------------------------------------- GEN_HW: if (C_SIM_ONLY = '0') generate begin S_AXI_BID_int <= (others => '0'); S_AXI_RID_int <= (others => '0'); end generate GEN_HW; --------------------------------------------------------------------------- -- Instance: I_AXI_LITE -- -- Description: -- This module is for the AXI-Lite -- instantiation of the BRAM controller interface. -- -- Responsible for shared address pipelining between the -- write address (AW) and read address (AR) channels. -- Controls (seperately) the data flows for the write data -- (W), write response (B), and read data (R) channels. -- -- Creates a shared port to BRAM (for all read and write -- transactions) or dual BRAM port utilization based on a -- generic parameter setting. -- -- Instantiates ECC register block if enabled and -- generates ECC logic, when enabled. -- -- --------------------------------------------------------------------------- I_AXI_LITE : entity work.axi_lite generic map ( C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , -- C_FAMILY => C_FAMILY , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC => C_ECC , C_ECC_TYPE => C_ECC_TYPE , -- v1.03a C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths) C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC C_FAULT_INJECT => C_FAULT_INJECT , C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , ECC_Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , AXI_AWADDR => S_AXI_AWADDR , AXI_AWVALID => S_AXI_AWVALID , AXI_AWREADY => S_AXI_AWREADY_int , AXI_WDATA => S_AXI_WDATA , AXI_WSTRB => S_AXI_WSTRB , AXI_WVALID => S_AXI_WVALID , AXI_WREADY => S_AXI_WREADY , AXI_BRESP => S_AXI_BRESP , AXI_BVALID => S_AXI_BVALID , AXI_BREADY => S_AXI_BREADY , AXI_ARADDR => S_AXI_ARADDR , AXI_ARVALID => S_AXI_ARVALID , AXI_ARREADY => S_AXI_ARREADY_int , AXI_RDATA => S_AXI_RDATA , AXI_RRESP => S_AXI_RRESP , AXI_RLAST => S_AXI_RLAST , AXI_RVALID => S_AXI_RVALID , AXI_RREADY => S_AXI_RREADY , -- Add AXI-Lite ECC Register Ports -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK , -- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN , AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , BRAM_En_A => bram_en_a_int , BRAM_WE_A => bram_we_a_int , BRAM_Addr_A => bram_addr_a_int , BRAM_WrData_A => bram_wrdata_a_int , BRAM_RdData_A => bram_rddata_a_int , BRAM_En_B => bram_en_b_int , BRAM_WE_B => bram_we_b_int , BRAM_Addr_B => bram_addr_b_int , BRAM_WrData_B => bram_wrdata_b_int , BRAM_RdData_B => bram_rddata_b_int ); end generate GEN_AXI4LITE; --------------------------------------------------------------------------- -- -- Generate: GEN_AXI -- Purpose: Only create internal signals for lower level write and read -- channel modules to assign AXI signals when the -- AXI protocol is set up for non AXI-LITE IF connections. -- For AXI4, all AXI signals are assigned to lower level modules. -- -- For AXI-Lite connections, generate statement above will -- create default values on these signals (assigned here). -- --------------------------------------------------------------------------- GEN_AXI4: if (IF_IS_AXI4) generate begin --------------------------------------------------------------------------- -- Instance: I_FULL_AXI -- -- Description: -- Full AXI BRAM controller logic. -- Instantiates wr_chnl and rd_chnl modules. -- If enabled, ECC register interface is included. -- --------------------------------------------------------------------------- I_FULL_AXI : entity work.full_axi generic map ( C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC => C_ECC , C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths) C_ECC_TYPE => C_ECC_TYPE , -- v1.03a C_FAULT_INJECT => C_FAULT_INJECT , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , ECC_Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , S_AXI_AWID => S_AXI_AWID , S_AXI_AWADDR => S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH-1 downto 0), S_AXI_AWLEN => S_AXI_AWLEN , S_AXI_AWSIZE => axi_awsize_int , S_AXI_AWBURST => S_AXI_AWBURST , S_AXI_AWLOCK => S_AXI_AWLOCK , S_AXI_AWCACHE => S_AXI_AWCACHE , S_AXI_AWPROT => S_AXI_AWPROT , S_AXI_AWVALID => S_AXI_AWVALID , S_AXI_AWREADY => S_AXI_AWREADY_int , S_AXI_WDATA => S_AXI_WDATA , S_AXI_WSTRB => S_AXI_WSTRB , S_AXI_WLAST => S_AXI_WLAST , S_AXI_WVALID => S_AXI_WVALID , S_AXI_WREADY => S_AXI_WREADY , S_AXI_BID => S_AXI_BID , S_AXI_BRESP => S_AXI_BRESP , S_AXI_BVALID => S_AXI_BVALID , S_AXI_BREADY => S_AXI_BREADY , S_AXI_ARID => S_AXI_ARID , S_AXI_ARADDR => S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH-1 downto 0), S_AXI_ARLEN => S_AXI_ARLEN , S_AXI_ARSIZE => axi_arsize_int , S_AXI_ARBURST => S_AXI_ARBURST , S_AXI_ARLOCK => S_AXI_ARLOCK , S_AXI_ARCACHE => S_AXI_ARCACHE , S_AXI_ARPROT => S_AXI_ARPROT , S_AXI_ARVALID => S_AXI_ARVALID , S_AXI_ARREADY => S_AXI_ARREADY_int , S_AXI_RID => S_AXI_RID , S_AXI_RDATA => S_AXI_RDATA , S_AXI_RRESP => S_AXI_RRESP , S_AXI_RLAST => S_AXI_RLAST , S_AXI_RVALID => S_AXI_RVALID , S_AXI_RREADY => S_AXI_RREADY , -- Add AXI-Lite ECC Register Ports -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK , -- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN , S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , BRAM_En_A => bram_en_a_int , BRAM_WE_A => bram_we_a_int , BRAM_WrData_A => bram_wrdata_a_int , BRAM_Addr_A => bram_addr_a_int , BRAM_RdData_A => bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) , BRAM_En_B => bram_en_b_int , BRAM_WE_B => bram_we_b_int , BRAM_Addr_B => bram_addr_b_int , BRAM_WrData_B => bram_wrdata_b_int , BRAM_RdData_B => bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ); -- v1.02a -- Seperate instantiations for wr_chnl and rd_chnl moved to -- full_axi module. end generate GEN_AXI4; end architecture implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/demo/ipi_proj/srcs/ip/fmc_imageon_hdmi_in_v2_01_a/src/fmc_imageon_hdmi_in.vhd	7	9295	------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2011 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Aug 31, 2011 -- Design Name: FMC-IMAGEON -- Module Name: fmc_imageon_hdmi_in.vhd -- Project Name: FMC-IMAGEON -- Target Devices: Spartan-6, Virtex-6 -- Artix-7, Kintex-7, Virtex-7, Zynq -- Avnet Boards: FMC-IMAGEON -- -- Tool versions: ISE 14.3 -- -- Description: FMC-IMAGEON HDMI input interface. -- -- Dependencies: -- -- Revision: Aug 31, 2011: 1.01 Initial version -- Nov 11, 2011: 1.02 Add CCIR656 decode logic -- Remove VSYNC/HSYNC ports -- Feb 06, 2012: 1.03 Fix sync de-embed logic -- Change IOB attribute from "TRUE" to "FORCE" -- Oct 19, 2012: 2.01a Remove XSVI bus interface -- Remove xsvi_ prefixes to video_ -- Rename active_video to de -- Change IP_GROUP to FMC-IMAGEON -- ------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fmc_imageon_hdmi_in is Generic ( C_DATA_WIDTH : integer := 16; C_FAMILY : string := "virtex6" ); Port ( clk : in std_logic; -- IO Pins io_hdmii_spdif : in std_logic; io_hdmii_video : in std_logic_vector(15 downto 0); -- Audio Port audio_spdif : out std_logic; -- Video Ports -- video_vsync : out std_logic; -- video_hsync : out std_logic; video_vblank : out std_logic; video_hblank : out std_logic; video_de : out std_logic; video_data : out std_logic_vector((C_DATA_WIDTH-1) downto 0); -- Debug Port debug_o : out std_logic_vector(23 downto 0) ); end fmc_imageon_hdmi_in; architecture rtl of fmc_imageon_hdmi_in is -- -- IOB registers -- signal spdif_r : std_logic; signal video_r : std_logic_vector (15 downto 0); attribute IOB : string; attribute IOB of spdif_r: signal is "FORCE"; attribute IOB of video_r: signal is "FORCE"; -- -- Input Delay -- signal video_d1 : std_logic_vector(15 downto 0); signal video_d2 : std_logic_vector(15 downto 0); signal video_d3 : std_logic_vector(15 downto 0); signal video_d4 : std_logic_vector(15 downto 0); -- -- CCIR656 Decode Logic -- signal sc : std_logic; signal sav_va : std_logic; signal eav_va : std_logic; signal sav_vb : std_logic; signal eav_vb : std_logic; signal sav_va_d1 : std_logic; signal sav_va_d2 : std_logic; signal sav_va_d3 : std_logic; signal sav_va_d4 : std_logic; signal sav_vb_d1 : std_logic; signal sav_vb_d2 : std_logic; signal sav_vb_d3 : std_logic; signal sav_vb_d4 : std_logic; signal sync_code : std_logic; signal vblank : std_logic; signal hblank : std_logic; signal de : std_logic; begin -- -- IOB registers -- io_iregs_l : process (clk) begin if Rising_Edge(clk) then spdif_r <= io_hdmii_spdif; video_r <= io_hdmii_video; end if; end process; -- -- Input Delay -- input_delay_l : process (clk) begin if Rising_Edge(clk) then -- Delay DATA by 4 cycles to have a 4 cycle view of data video_d1 <= video_r; video_d2 <= video_d1; video_d3 <= video_d2; video_d4 <= video_d3; end if; end process; -- -- CCIR656 Decode Logic -- ccir656_decode_l : process ( video_r, video_d1, video_d2, video_d3, video_d4 ) begin -- Sync Code sc <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") ) then sc <= '1'; end if; -- Start of Active Video (active line) sav_va <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") and (video_r = X"8080") ) then sav_va <= '1'; end if; -- End of Active Video (active line) eav_va <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") and (video_r = X"9D9D") ) then eav_va <= '1'; end if; -- Start of Inactive Video (blank line) sav_vb <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") and (video_r = X"ABAB") ) then sav_vb <= '1'; end if; -- End of Inactive Video (blank line) eav_vb <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d2 = X"0000") and (video_r = X"B6B6") ) then eav_vb <= '1'; end if; end process; ccir656_syncgen_l : process (clk) begin if Rising_Edge(clk) then -- Delay SAV by 4 cycles sav_va_d1 <= sav_va; sav_va_d2 <= sav_va_d1; sav_va_d3 <= sav_va_d2; sav_va_d4 <= sav_va_d3; -- sav_vb_d1 <= sav_vb; sav_vb_d2 <= sav_vb_d1; sav_vb_d3 <= sav_vb_d2; sav_vb_d4 <= sav_vb_d3; -- Create generic Sync Code event indicator (for use with ChipScope) sync_code <= sc; -- Create DE strobe based on SAV/EAV events if ( sav_va_d4 = '1' ) then de <= '1'; end if; if ( eav_va = '1' or eav_vb = '1' ) then de <= '0'; end if; -- Create VBLANK strobes based on SAV events --if ( sav_vb = '1' ) then if ( sav_vb = '1' or eav_vb = '1' ) then vblank <= '1'; end if; if ( sav_va = '1' ) then vblank <= '0'; end if; -- Create HBLANK strobes based on SAV/EAV events if ( sav_va_d4 = '1' or sav_vb_d4 = '1' ) then hblank <= '0'; end if; if ( eav_va = '1' or eav_vb = '1' ) then hblank <= '1'; end if; end if; end process; -- -- Video Ports -- VIDEO_PORTS_16BIT_GEN : if (C_DATA_WIDTH = 16) generate video_ports_16bit_oregs_l : process (clk) begin if rising_edge( clk ) then -- video_vsync <= '0'; -- video_hsync <= '0'; video_vblank <= vblank; video_hblank <= hblank; video_de <= de; video_data <= video_d4; end if; end process; end generate VIDEO_PORTS_16BIT_GEN; -- -- Audio Port -- audio_spdif <= spdif_r; -- -- Debug Port -- Can be used to connect to ChipScope for debugging. -- Having a port makes these signals accessible for debug via EDK. -- debug_l : process (clk) begin if Rising_Edge(clk) then debug_o(15 downto 0) <= video_r; debug_o( 16) <= spdif_r; debug_o( 17) <= de; debug_o( 18) <= hblank; debug_o( 19) <= vblank; debug_o( 20) <= sav_va; debug_o( 21) <= sav_vb; debug_o( 22) <= eav_va or eav_vb; debug_o( 23) <= sync_code; end if; end process; end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_mm2s_omit_wrap.vhd	18	16390	------------------------------------------------------------------------------- -- axi_datamover_mm2s_omit_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_omit_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Omit Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_omit_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 0; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Lite MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 0; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input -------------------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------- -- MM2S Halt request input control------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ----------------------------------------------------------- -- Error discrete output ---------------------------------- mm2s_err : Out std_logic; -- -- Composite Error indication -- ----------------------------------------------------------- -- Optional MM2S Command and Status clock and Reset ----------- -- Only used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- --------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ---------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- ---------------------------------------------------------------- -- Address Posting contols ------------------------------------- mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- ---------------------------------------------------------------- -- MM2S AXI Address Channel I/O -------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- MM2S AXI MMap Read Data Channel I/O ------------------------------------------ mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- ---------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ----------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ----------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ---------------------------------------------------------------------- ); end entity axi_datamover_mm2s_omit_wrap; architecture implementation of axi_datamover_mm2s_omit_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; begin --(architecture implementation) mm2s_dbg_data <= X"BEEF0000" ; -- 32 bit Constant indicating OMIT type -- Just tie off output ports mm2s_halt_cmplt <= mm2s_halt ; mm2s_err <= '0' ; mm2s_cmd_wready <= '0' ; mm2s_sts_wvalid <= '0' ; mm2s_sts_wdata <= (others => '0'); mm2s_sts_wstrb <= (others => '0'); mm2s_sts_wlast <= '0' ; mm2s_arid <= (others => '0'); mm2s_araddr <= (others => '0'); mm2s_arlen <= (others => '0'); mm2s_arsize <= (others => '0'); mm2s_arburst <= (others => '0'); mm2s_arprot <= (others => '0'); mm2s_arcache <= (others => '0'); mm2s_aruser <= (others => '0'); mm2s_arvalid <= '0' ; mm2s_rready <= '0' ; mm2s_strm_wdata <= (others => '0'); mm2s_strm_wstrb <= (others => '0'); mm2s_strm_wlast <= '0' ; mm2s_strm_wvalid <= '0' ; mm2s_addr_req_posted <= '0' ; mm2s_rd_xfer_cmplt <= '0' ; -- Input ports are ignored end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/acme/ipi_proj/srcs/ip/vsrc_sel_v1_0/vhdl/video_src_sel.vhd	6	8306	-- ************************************************************************* -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2010 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port: "_i" -- device pins: "_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Library UNISIM; use UNISIM.vcomponents.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity vsrc_sel is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_CHANNELS : integer := 1 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ -- User logic ports video_clk_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_clk_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); de_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); de_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_clk : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); de : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_sel : in std_logic ); attribute MAX_FANOUT : string; attribute SIGIS : string; -- attribute SIGIS of Bus2IP_Clk : signal is "CLK"; -- attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity vsrc_sel; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of vsrc_sel is begin de <= de_1 when video_sel = '0' else de_2; hsync <= hsync_1 when video_sel = '0' else hsync_2; vsync <= vsync_1 when video_sel = '0' else vsync_2; VIDEO_SEL_GEN:for i in 0 to C_NUM_CHANNELS-1 generate begin BUFGMUX_INST : BUFGMUX generic map ( CLK_SEL_TYPE => "SYNC" -- Not supported. Must be "SYNC". ) port map ( O => video_clk(i), -- 1-bit output: Clock buffer output I0 => video_clk_1(i), -- 1-bit input: Clock buffer input (S=0) I1 => video_clk_2(i), -- 1-bit input: Clock buffer input (S=1) S => video_sel-- 1-bit input: Clock buffer select ); end generate VIDEO_SEL_GEN; end IMP;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd	5	92755	------------------------------------------------------------------------------- -- axi_datamover_s2mm_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_full_wrap.vhd -- -- Description: -- This file implements the DataMover S2MM FULL Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all ; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset ; use axi_datamover_v5_1.axi_datamover_cmd_status ; use axi_datamover_v5_1.axi_datamover_pcc ; use axi_datamover_v5_1.axi_datamover_ibttcc ; use axi_datamover_v5_1.axi_datamover_indet_btt ; use axi_datamover_v5_1.axi_datamover_s2mm_realign ; use axi_datamover_v5_1.axi_datamover_addr_cntl ; use axi_datamover_v5_1.axi_datamover_wrdata_cntl ; use axi_datamover_v5_1.axi_datamover_wr_status_cntl; Use axi_datamover_v5_1.axi_datamover_skid2mm_buf ; Use axi_datamover_v5_1.axi_datamover_skid_buf ; Use axi_datamover_v5_1.axi_datamover_wr_sf ; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_full_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 1; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) General Purpose Store and Forward function -- 0 = Omit GP Store and Forward -- 1 = Include GP Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and Reset inputs ---------------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- ------------------------------------------------------------------- -- S2MM Primary Reset input --------------------------------------- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------- -- S2MM Halt request input control -------------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------------- -- S2MM Error discrete output ------------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------------- -- Optional Command and Status Clock and Reset ------------------- -- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 -- -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls --------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O --------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ----------------------------------------- s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ----------------------------------------------- s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ----------------------------------------------------------------- ); end entity axi_datamover_s2mm_full_wrap; architecture implementation of axi_datamover_s2mm_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_wdemux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Write Strobe demux select control. -- ------------------------------------------------------------------- function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_wdemux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin if (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_status_width -- -- Function Description: -- This function sets the width of the Status pipe depending on the -- Store and Forward inclusion or ommision. -- ------------------------------------------------------------------- function funct_set_status_width (store_forward_enabled : integer) return integer is Variable temp_status_bit_width : Integer := 8; begin If (store_forward_enabled = 1) Then temp_status_bit_width := 32; Else temp_status_bit_width := 8; End if; Return (temp_status_bit_width); end function funct_set_status_width; ------------------------------------------------------------------- -- Function -- -- Function Name: get_bits_needed -- -- Function Description: -- -- ------------------------------------------------------------------- function get_bits_needed (max_bytes : integer) return integer is Variable fvar_temp_bit_width : Integer := 1; begin if (max_bytes <= 1) then fvar_temp_bit_width := 1; elsif (max_bytes <= 3) then fvar_temp_bit_width := 2; elsif (max_bytes <= 7) then fvar_temp_bit_width := 3; elsif (max_bytes <= 15) then fvar_temp_bit_width := 4; elsif (max_bytes <= 31) then fvar_temp_bit_width := 5; elsif (max_bytes <= 63) then fvar_temp_bit_width := 6; elsif (max_bytes <= 127) then fvar_temp_bit_width := 7; elsif (max_bytes <= 255) then fvar_temp_bit_width := 8; elsif (max_bytes <= 511) then fvar_temp_bit_width := 9; elsif (max_bytes <= 1023) then fvar_temp_bit_width := 10; elsif (max_bytes <= 2047) then fvar_temp_bit_width := 11; elsif (max_bytes <= 4095) then fvar_temp_bit_width := 12; elsif (max_bytes <= 8191) then fvar_temp_bit_width := 13; else -- 8k - 16K fvar_temp_bit_width := 14; end if; Return (fvar_temp_bit_width); end function get_bits_needed; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_need_realigner -- -- Function Description: -- Determines if the Realigner module needs to be included. -- ------------------------------------------------------------------- function funct_need_realigner (indet_btt_enabled : integer; dre_included : integer; gp_sf_included : integer) return integer is Variable temp_val : Integer := 0; begin If ((indet_btt_enabled = 1) or (dre_included = 1) or (gp_sf_included = 1)) Then temp_val := 1; else temp_val := 0; End if; Return (temp_val); end function funct_need_realigner; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for S2MM -- modules downstream from the upsizing Store and Forward. If -- Store and forward is present, then the effective Stream width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Stream width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled > 0) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_bytes_per_dbeat -- -- Function Description: -- This function calculates the number of bytes transfered per -- databeat on the MMap AXI4 Write Data Channel by the S2MM. The -- value is based on input parameterization of included functions -- in the S2MM block. -- ------------------------------------------------------------------- function funct_get_bytes_per_dbeat (ibtt_enabled : integer ; gpsf_enabled : integer ; stream_dwidth : integer ; mmap_dwidth : integer ) return integer is Variable fvar_temp_bytes_per_xfer : Integer := 4; begin If (ibtt_enabled > 0 or gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width fvar_temp_bytes_per_xfer := mmap_dwidth/8; Else -- transfers will be in stream data widths (may be narrow transfers on mmap) fvar_temp_bytes_per_xfer := stream_dwidth/8; End if; Return (fvar_temp_bytes_per_xfer); end function funct_get_bytes_per_dbeat; -- Constant Declarations ---------------------------------------- Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT; Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH, C_S2MM_SDATA_WIDTH, SF_ENABLED); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant IS_NOT_MM2S : integer range 0 to 1 := 0; Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID; Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH; Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH; Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH; Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH; Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32); Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO; Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH; Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC; Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH); Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED; Constant BITS_PER_BYTE : integer := 8; Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1; Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT; Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ; Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF , ENABLE_GP_SF , S2MM_SDATA_WIDTH , S2MM_MDATA_WIDTH); Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEATS2MM_BURST_SIZE; Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST); Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going -- full thresholding -- in WSC Constant WSC_STATUS_WIDTH : integer range 8 to 32 := funct_set_status_width(ENABLE_INDET_BTT_SF); Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED; Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF , INCLUDE_S2MM_DRE , ENABLE_GP_SF); -- Calculates the minimum needed depth of the GP Store and Forward FIFO -- based on the S2MM pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE; -- Assigns the depth of the optional GP Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH, S2MM_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_last : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2addr_data_rdy : std_logic := '0'; signal sig_data2all_tlast_error : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2wsc_calc_error : std_logic := '0'; signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0'); signal sig_data2wsc_cmd_empty : std_logic := '0'; signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2wsc_status_ready : std_logic := '0'; signal sig_wsc2stat_status_valid : std_logic := '0'; signal sig_wsc2mstr_halt_pipe : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wvalid : std_logic := '0'; signal sig_skid2data_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_skid2axi_wvalid : std_logic := '0'; signal sig_axi2skid_wready : std_logic := '0'; signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_skid2axi_wlast : std_logic := '0'; signal sig_data2wsc_sof : std_logic := '0'; signal sig_data2wsc_eof : std_logic := '0'; signal sig_data2wsc_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_data2wsc_eop : std_logic := '0'; signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2pcc_xfer_valid : std_logic := '0'; signal sig_pcc2sf_xfer_ready : std_logic := '0'; signal sig_sf2pcc_cmd_cmplt : std_logic := '0'; signal sig_sf2pcc_packet_eop : std_logic := '0'; signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0'); signal sig_dre2ibtt_tvalid : std_logic := '0'; signal sig_ibtt2dre_tready : std_logic := '0'; signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tlast : std_logic := '0'; signal sig_dre2ibtt_eop : std_logic := '0'; signal sig_dre2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2dre_cmd_valid : std_logic := '0'; signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2dre_drr : std_logic := '0'; signal sig_mstr2dre_eof : std_logic := '0'; signal sig_mstr2dre_cmd_cmplt : std_logic := '0'; signal sig_mstr2dre_calc_error : std_logic := '0'; signal sig_realign2wdc_eop_error : std_logic := '0'; signal sig_dre2all_halted : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_wsc2rst_stop_cmplt : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal skid2dre_wvalid : std_logic := '0'; signal dre2skid_wready : std_logic := '0'; signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal skid2dre_wlast : std_logic := '0'; signal sig_s2mm_allow_addr_req : std_logic := '0'; signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_s2mm_addr_req_posted : std_logic := '0'; signal sig_s2mm_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_ibtt2wdc_error : std_logic := '0'; signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal s2mm_awcache_int : std_logic_vector (3 downto 0); signal s2mm_awuser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug/Test Port Assignments s2mm_dbg_data <= sig_dbg_data_mux_out; -- Note that only the s2mm_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (s2mm_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2wsc_status_ready; sig_dbg_data_1(7) <= sig_wsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error --sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADD_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen adds in the EOP status marker to the debug -- vector data when Indet BTT Store and Forward is enabled. -- ------------------------------------------------------------ GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate begin sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker end generate GEN_ADD_DEBUG_EOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen zeros the debug vector bit used for the EOP -- status marker when Indet BTT Store and Forward is not -- enabled. -- ------------------------------------------------------------ GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate begin sig_dbg_data_1(19) <= '0' ; -- EOP Marker end generate GEN_NO_DEBUG_EOP; ---- End of Debug/Test Support -------------------------------- -- Assign the Address posting control outputs s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ; s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ; s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ; s2mm_wr_len <= sig_s2mm_wr_len ; -- Write Data Channel I/O s2mm_wvalid <= sig_skid2axi_wvalid; sig_axi2skid_wready <= s2mm_wready ; s2mm_wdata <= sig_skid2axi_wdata ; s2mm_wlast <= sig_skid2axi_wlast ; GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate begin s2mm_wstrb <= sig_skid2axi_wstrb ; end generate GEN_S2MM_TKEEP_ENABLE2; GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate begin s2mm_wstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE2; GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= s2mm_cmd_wdata(79 downto 72); -- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE2; -- Internal error output discrete s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ) port map ( primary_aclk => s2mm_aclk , primary_aresetn => s2mm_aresetn , secondary_awclk => s2mm_cmdsts_awclk , secondary_aresetn => s2mm_cmdsts_aresetn , halt_req => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => sig_wsc2rst_stop_cmplt , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO , C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , secondary_awclk => s2mm_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => s2mm_cmd_wvalid , cmd_wready => s2mm_cmd_wready , cmd_wdata => sig_s2mm_cmd_wdata , cache_data => sig_s2mm_cache_data , sts_wvalid => s2mm_sts_wvalid , sts_wready => s2mm_sts_wready , sts_wdata => s2mm_sts_wdata , sts_wstrb => s2mm_sts_wstrb , sts_wlast => s2mm_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_wsc2stat_status , stat2mstr_status_ready => sig_stat2wsc_status_ready , mst2stst_status_valid => sig_wsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_WR_STATUS_CNTLR -- -- Description: -- Write Status Controller Block -- ------------------------------------------------------------ I_WR_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_wr_status_cntl generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2wsc_stop_request => sig_rst2all_stop_request , wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt , addr2wsc_addr_posted => sig_addr2data_addr_posted , s2mm_bresp => s2mm_bresp , s2mm_bvalid => s2mm_bvalid , s2mm_bready => s2mm_bready , calc2wsc_calc_error => sig_calc2dm_calc_err , addr2wsc_calc_error => sig_addr2wsc_calc_error , addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_error => sig_data2wsc_calc_err , data2wsc_last_error => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , data2wsc_valid => sig_data2wsc_valid , wsc2data_ready => sig_wsc2data_ready , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2stat_status => sig_wsc2stat_status , stat2wsc_status_ready => sig_stat2wsc_status_ready , wsc2stat_status_valid => sig_wsc2stat_status_valid , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_PCC -- -- If Generate Description: -- Include the normal Predictive Command Calculator function, -- Store and Forward is not an included feature. -- -- ------------------------------------------------------------ GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate begin ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_NOT_MM2S , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => open , mstr2data_dre_dest_align => open , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_PCC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_IBTTCC -- -- If Generate Description: -- Include the Indeterminate BTT Command Calculator function, -- Store and Forward is enabled in the S2MM. -- -- ------------------------------------------------------------ GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_MSTR_SFCC -- -- Description: -- Instantiates the Store and Forward Command Calculator -- Block. -- ------------------------------------------------------------ I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1.axi_datamover_ibttcc generic map ( C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_IBTTCC; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate begin ------------------------------------------------------------ -- Instance: I_S2MM_STRM_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registerd Slave Stream inputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_wvalid , s_ready => s2mm_strm_wready , s_data => s2mm_strm_wdata , s_strb => s2mm_strm_wstrb , s_last => s2mm_strm_wlast , -- Master Side (Stream Data Output m_valid => skid2dre_wvalid , m_ready => dre2skid_wready , m_data => skid2dre_wdata , m_strb => skid2dre_wstrb , m_last => skid2dre_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate begin skid2dre_wvalid <= s2mm_strm_wvalid; s2mm_strm_wready <= dre2skid_wready; skid2dre_wdata <= s2mm_strm_wdata; skid2dre_wstrb <= s2mm_strm_wstrb; skid2dre_wlast <= s2mm_strm_wlast; end generate DISABLE_AXIS_SKID; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_REALIGNER -- -- If Generate Description: -- Omit the S2MM Realignment Engine -- -- ------------------------------------------------------------ GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate begin -- Set to Always ready for DRE to PCC Command Interface sig_dre2mstr_cmd_ready <= LOGIC_HIGH; -- Without DRE and Scatter, the end of packet is the TLAST --sig_dre2ibtt_eop <= skid2dre_wlast ; sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version -- Cant't detect undrrun/overrun here sig_realign2wdc_eop_error <= '0'; ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate begin ------------------------------------------------------------ -- Instance: I_NO_REALIGN_SKID_BUF -- -- Description: -- Instance for a Skid Buffer which provides for -- Fmax timing improvement between the Null Absorber and -- the Write Data controller when the Realigner is not -- present (no DRE and no Store and Forward case). -- ------------------------------------------------------------ I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Null Absorber Input) s_valid => skid2dre_wvalid , s_ready => dre2skid_wready , s_data => skid2dre_wdata , s_strb => skid2dre_wstrb , s_last => skid2dre_wlast , -- Master Side (Stream Data Output to WData Cntlr) m_valid => sig_dre2ibtt_tvalid , m_ready => sig_ibtt2dre_tready , m_data => sig_dre2ibtt_tdata , m_strb => sig_dre2ibtt_tstrb , m_last => sig_dre2ibtt_tlast ); end generate ENABLE_NOREALIGNER_SKID; DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate begin sig_dre2ibtt_tvalid <= skid2dre_wvalid; dre2skid_wready <= sig_ibtt2dre_tready; sig_dre2ibtt_tdata <= skid2dre_wdata; sig_dre2ibtt_tstrb <= skid2dre_wstrb; sig_dre2ibtt_tlast <= skid2dre_wlast; end generate DISABLE_NOREALIGNER_SKID; end generate GEN_NO_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_REALIGNER -- -- If Generate Description: -- Include the S2MM realigner Module. It hosts the S2MM DRE -- and the Scatter Block. -- -- Note that the General Purpose Store and Forward Module -- needs the Scatter function to detect input overrun and -- underrun events on the AXI Stream input. Thus the Realigner -- is included whenever the GP Store and Forward is enabled. -- ------------------------------------------------------------ GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_REALIGNER -- -- Description: -- Instance for the S2MM Data Realignment Module. -- ------------------------------------------------------------ I_S2MM_REALIGNER : entity axi_datamover_v5_1.axi_datamover_s2mm_realign generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_INCLUDE_DRE => INCLUDE_S2MM_DRE , C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER , C_BTT_USED => S2MM_BTT_USED , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , -- Write Data Controller or Store and Forward I/O ------- wdc2dre_wready => sig_ibtt2dre_tready , dre2wdc_wvalid => sig_dre2ibtt_tvalid , dre2wdc_wdata => sig_dre2ibtt_tdata , dre2wdc_wstrb => sig_dre2ibtt_tstrb , dre2wdc_wlast => sig_dre2ibtt_tlast , dre2wdc_eop => sig_dre2ibtt_eop , -- Starting offset output ------------------------------- dre2sf_strt_offset => sig_sf_strt_addr_offset , -- AXI Slave Stream In ----------------------------------- s2mm_strm_wready => dre2skid_wready , s2mm_strm_wvalid => skid2dre_wvalid , s2mm_strm_wdata => skid2dre_wdata , s2mm_strm_wstrb => skid2dre_wstrb , s2mm_strm_wlast => skid2dre_wlast , -- Command Calculator Interface -------------------------- dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset , -- Premature TLAST assertion error flag dre2all_tlast_error => sig_realign2wdc_eop_error , -- DRE Halted Status dre2all_halted => sig_dre2all_halted ); end generate GEN_INCLUDE_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT_SF -- -- If Generate Description: -- Include the Indeterminate BTT Logic with specialized -- Store and Forward function, This also requires the -- Scatter Engine in the Realigner module. -- -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate begin -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; ------------------------------------------------------------ -- Instance: I_INDET_BTT -- -- Description: -- Instance for the Indeterminate BTT with Store and Forward -- module. -- ------------------------------------------------------------ I_INDET_BTT : entity axi_datamover_v5_1.axi_datamover_indet_btt generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_DRE => INCLUDE_S2MM_DRE , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted, ibtt2wdc_eop => sig_ibtt2wdc_eop , ibtt2wdc_tdata => sig_ibtt2wdc_tdata , ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb , ibtt2wdc_tlast => sig_ibtt2wdc_tlast , ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid , wdc2ibtt_tready => sig_wdc2ibtt_tready , dre2ibtt_tvalid => sig_dre2ibtt_tvalid , ibtt2dre_tready => sig_ibtt2dre_tready , dre2ibtt_tdata => sig_dre2ibtt_tdata , dre2ibtt_tstrb => sig_dre2ibtt_tstrb , dre2ibtt_tlast => sig_dre2ibtt_tlast , dre2ibtt_eop => sig_dre2ibtt_eop , dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ); end generate GEN_ENABLE_INDET_BTT_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_SF -- -- If Generate Description: -- Bypasses any store and Forward functions. -- -- ------------------------------------------------------------ GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 0) generate begin -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; -- Housekeep unused signal in this case sig_ok_to_post_wr_addr <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; -- Just pass DRE signals through sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ; sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ; sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ; sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ; sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ; sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ; sig_ibtt2wdc_stbs_asserted <= (others => '0') ; -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; end generate GEN_NO_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_GP_SF -- -- If Generate Description: -- Include the General Purpose Store and Forward module. -- This If Generate can only be enabled when -- Indeterminate BTT mode is not enabled. The General Purpose -- Store and Forward is instantiated in place of the Indet -- BTT Store and Forward. -- ------------------------------------------------------------ GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 1) generate begin -- Merge the external address posting control with the -- SF address posting control. sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and sig_ok_to_post_wr_addr ; -- Zero these out since Indet BTT is not enabled, they -- are only used by the WDC in that mode sig_ibtt2wdc_stbs_asserted <= (others => '0') ; sig_ibtt2wdc_eop <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; ------------------------------------------------------------ -- Instance: I_S2MM_GP_SF -- -- Description: -- Instance for the S2MM (Write) General Purpose Store and -- Forward Module. This module can only be enabled when -- Indeterminate BTT mode is not enabled. It is connected -- in place of the IBTT Module when GP SF is enabled. -- ------------------------------------------------------------ I_S2MM_GP_SF : entity axi_datamover_v5_1.axi_datamover_wr_sf generic map ( C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ----------------------------- aclk => s2mm_aclk , reset => sig_mmap_rst , -- Slave Stream Input -------------------------------- sf2sin_tready => sig_ibtt2dre_tready , sin2sf_tvalid => sig_dre2ibtt_tvalid , sin2sf_tdata => sig_dre2ibtt_tdata , sin2sf_tkeep => sig_dre2ibtt_tstrb , sin2sf_tlast => sig_dre2ibtt_tlast , sin2sf_error => sig_realign2wdc_eop_error , -- Starting Address Offset Input --------------------- sin2sf_strt_addr_offset => sig_sf_strt_addr_offset , -- DataMover Write Side Address Pipelining Control Interface -------- ok_to_post_wr_addr => sig_ok_to_post_wr_addr , wr_addr_posted => sig_s2mm_addr_req_posted , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , wr_ld_nxt_len => sig_s2mm_ld_nxt_len , wr_len => sig_s2mm_wr_len , -- Write Side Stream Out to DataMover S2MM ------------- sout2sf_tready => sig_wdc2ibtt_tready , sf2sout_tvalid => sig_ibtt2wdc_tvalid , sf2sout_tdata => sig_ibtt2wdc_tdata , sf2sout_tkeep => sig_ibtt2wdc_tstrb , sf2sout_tlast => sig_ibtt2wdc_tlast , sf2sout_error => sig_ibtt2wdc_error ); end generate GEN_INCLUDE_GP_SF; ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_ADDR_ID => S2MM_AWID_VALUE , C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => s2mm_awid , addr2axi_aaddr => s2mm_awaddr , addr2axi_alen => s2mm_awlen , addr2axi_asize => s2mm_awsize , addr2axi_aburst => s2mm_awburst , addr2axi_aprot => s2mm_awprot , addr2axi_avalid => s2mm_awvalid , addr2axi_acache => s2mm_awcache_int , addr2axi_auser => s2mm_awuser_int , axi2addr_aready => s2mm_awready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , -- mstr2addr_cache_info => sig_cache2mstr_command , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_s2mm_allow_addr_req , addr_req_posted => sig_s2mm_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2wsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_WR_DATA_CNTL -- -- Description: -- Write Data Controller Block -- ------------------------------------------------------------ I_WR_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_wrdata_cntl generic map ( C_REALIGNER_INCLUDED => ADD_REALIGNER , C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len , s2mm_wr_len => sig_s2mm_wr_len , data2skid_saddr_lsb => sig_data2skid_addr_lsb , data2skid_wdata => sig_data2skid_wdata , data2skid_wstrb => sig_data2skid_wstrb , data2skid_wlast => sig_data2skid_wlast , data2skid_wvalid => sig_data2skid_wvalid , skid2data_wready => sig_skid2data_wready , s2mm_strm_wvalid => sig_ibtt2wdc_tvalid , s2mm_strm_wready => sig_wdc2ibtt_tready , s2mm_strm_wdata => sig_ibtt2wdc_tdata , s2mm_strm_wstrb => sig_ibtt2wdc_tstrb , s2mm_strm_wlast => sig_ibtt2wdc_tlast , s2mm_strm_eop => sig_ibtt2wdc_eop , s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted, realign2wdc_eop_error => sig_ibtt2wdc_error , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2all_tlast_error => sig_data2all_tlast_error , data2all_dcntlr_halted => sig_data2all_dcntlr_halted, data2skid_halt => sig_data2skid_halt , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_err => sig_data2wsc_calc_err , data2wsc_last_err => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , wsc2data_ready => sig_wsc2data_ready , data2wsc_valid => sig_data2wsc_valid , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); --ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate --begin ------------------------------------------------------------ -- Instance: I_S2MM_MMAP_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registered outputs and supports bi-dir throttling. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- ------------------------------------------------------------ I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid2mm_buf generic map ( C_MDATA_WIDTH => S2MM_MDATA_WIDTH , C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH ) port map ( -- System Ports ACLK => s2mm_aclk , ARST => sig_stream_rst , -- Slave Side (Wr Data Controller Input Side ) S_ADDR_LSB => sig_data2skid_addr_lsb, S_VALID => sig_data2skid_wvalid , S_READY => sig_skid2data_wready , S_Data => sig_data2skid_wdata , S_STRB => sig_data2skid_wstrb , S_Last => sig_data2skid_wlast , -- Master Side (MMap Write Data Output Side) M_VALID => sig_skid2axi_wvalid , M_READY => sig_axi2skid_wready , M_Data => sig_skid2axi_wdata , M_STRB => sig_skid2axi_wstrb , M_Last => sig_skid2axi_wlast ); --end generate ENABLE_AXIMMAP_SKID; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/vhdl/FIFO_image_filter_img_0_data_stream_1_V.vhd	4	4629	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_0_data_stream_1_V_shiftReg; architecture rtl of FIFO_image_filter_img_0_data_stream_1_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_1_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_0_data_stream_1_V is component FIFO_image_filter_img_0_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_0_data_stream_1_V_shiftReg : FIFO_image_filter_img_0_data_stream_1_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_q_mngr.vhd	3	39575	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ********************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_q_mngr.vhd -- Description: This entity is the descriptor update queue manager -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_q_mngr is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- --*******************************-- -- -- Channel 1 Control -- -- --*******************************-- -- ch1_updt_curdesc_wren : out std_logic ; -- ch1_updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_updt_active : in std_logic ; -- ch1_updt_queue_empty : out std_logic ; -- ch1_updt_ioc : out std_logic ; -- ch1_updt_ioc_irq_set : in std_logic ; -- -- ch1_dma_interr : out std_logic ; -- ch1_dma_slverr : out std_logic ; -- ch1_dma_decerr : out std_logic ; -- ch1_dma_interr_set : in std_logic ; -- ch1_dma_slverr_set : in std_logic ; -- ch1_dma_decerr_set : in std_logic ; -- -- --*******************************-- -- -- Channel 2 Control -- -- --*******************************-- -- ch2_updt_active : in std_logic ; -- -- ch2_updt_curdesc_wren : out std_logic ; -- -- ch2_updt_curdesc : out std_logic_vector -- -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_updt_queue_empty : out std_logic ; -- ch2_updt_ioc : out std_logic ; -- ch2_updt_ioc_irq_set : in std_logic ; -- -- ch2_dma_interr : out std_logic ; -- ch2_dma_slverr : out std_logic ; -- ch2_dma_decerr : out std_logic ; -- ch2_dma_interr_set : in std_logic ; -- ch2_dma_slverr_set : in std_logic ; -- ch2_dma_decerr_set : in std_logic ; -- -- --*******************************-- -- -- Channel 1 Update Interface In -- -- --*******************************-- -- s_axis_ch1_updt_aclk : in std_logic ; -- -- Update Pointer Stream -- s_axis_ch1_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_ch1_updtptr_tvalid : in std_logic ; -- s_axis_ch1_updtptr_tready : out std_logic ; -- s_axis_ch1_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_ch1_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_ch1_updtsts_tvalid : in std_logic ; -- s_axis_ch1_updtsts_tready : out std_logic ; -- s_axis_ch1_updtsts_tlast : in std_logic ; -- -- --*******************************-- -- -- Channel 2 Update Interface In -- -- --*******************************-- -- s_axis_ch2_updt_aclk : in std_logic ; -- -- Update Pointer Stream -- s_axis_ch2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_ch2_updtptr_tvalid : in std_logic ; -- s_axis_ch2_updtptr_tready : out std_logic ; -- s_axis_ch2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_ch2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_ch2_updtsts_tvalid : in std_logic ; -- s_axis_ch2_updtsts_tready : out std_logic ; -- s_axis_ch2_updtsts_tlast : in std_logic ; -- -- --***********************************-- -- -- Update Interface to AXI DataMover -- -- --***********************************-- -- -- S2MM Stream Out To DataMover -- s_axis_s2mm_tdata : out std_logic_vector -- (C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_tlast : out std_logic ; -- s_axis_s2mm_tvalid : out std_logic ; -- s_axis_s2mm_tready : in std_logic -- ); end axi_sg_updt_q_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_q_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_ch1_updt_tlast : std_logic := '0'; signal m_axis_ch1_updt_tvalid : std_logic := '0'; signal m_axis_ch1_updt_tready : std_logic := '0'; signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_ch2_updt_tlast : std_logic := '0'; signal m_axis_ch2_updt_tvalid : std_logic := '0'; signal m_axis_ch2_updt_tready : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin --************************************************************************* -- CHANNEL 1 --************************************************************************* ------------------------------------------------------------------------------- -- If Channel 1 is enabled then instantiate descriptor update logic. ------------------------------------------------------------------------------- -- If Descriptor Update queueing enabled then instantiate Queue Logic GEN_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate begin ------------------------------------------------------------------------------- I_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE , C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE , C_SG2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE , C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_INCLUDE_MM2S => C_INCLUDE_CH1 , C_INCLUDE_S2MM => C_INCLUDE_CH2 , C_FAMILY => C_FAMILY ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , s_axis_updt_aclk => s_axis_ch1_updt_aclk , --****************************-- -- Control and Status -- --****************************-- updt_curdesc_wren => ch1_updt_curdesc_wren , updt_curdesc => ch1_updt_curdesc , updt_active => ch1_updt_active , updt_queue_empty => ch1_updt_queue_empty , updt_ioc => ch1_updt_ioc , updt_ioc_irq_set => ch1_updt_ioc_irq_set , dma_interr => ch1_dma_interr , dma_slverr => ch1_dma_slverr , dma_decerr => ch1_dma_decerr , dma_interr_set => ch1_dma_interr_set , dma_slverr_set => ch1_dma_slverr_set , dma_decerr_set => ch1_dma_decerr_set , -- updt2_curdesc_wren => ch2_updt_curdesc_wren , -- updt2_curdesc => ch2_updt_curdesc , updt2_active => ch2_updt_active , updt2_queue_empty => ch2_updt_queue_empty , updt2_ioc => ch2_updt_ioc , updt2_ioc_irq_set => ch2_updt_ioc_irq_set , dma2_interr => ch2_dma_interr , dma2_slverr => ch2_dma_slverr , dma2_decerr => ch2_dma_decerr , dma2_interr_set => ch2_dma_interr_set , dma2_slverr_set => ch2_dma_slverr_set , dma2_decerr_set => ch2_dma_decerr_set , --****************************-- -- Update Interfaces In -- --****************************-- -- Update Pointer Stream s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata , s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid , s_axis_updtptr_tready => s_axis_ch1_updtptr_tready , s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast , -- Update Status Stream s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata , s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid , s_axis_updtsts_tready => s_axis_ch1_updtsts_tready , s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast , -- Update Pointer Stream s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata , s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready , s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- Update Status Stream s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata , s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready , s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast , --****************************-- -- Update Interfaces Out -- --****************************-- -- S2MM Stream Out To DataMover m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata , m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast , m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid , m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready , -- m_axis2_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis2_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis2_updt_tready => m_axis_ch2_updt_tready ); end generate GEN_QUEUE; --************************************************************************* -- CHANNEL 1 - NO DESCRIPTOR QUEUE --************************************************************************* -- No update queue enabled, therefore map internal stream logic -- directly to channel port. GEN_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate begin I_NO_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , --****************************-- -- Control and Status -- --****************************-- updt_curdesc_wren => ch1_updt_curdesc_wren , updt_curdesc => ch1_updt_curdesc , updt_active => ch1_updt_active , updt_queue_empty => ch1_updt_queue_empty , updt_ioc => ch1_updt_ioc , updt_ioc_irq_set => ch1_updt_ioc_irq_set , dma_interr => ch1_dma_interr , dma_slverr => ch1_dma_slverr , dma_decerr => ch1_dma_decerr , dma_interr_set => ch1_dma_interr_set , dma_slverr_set => ch1_dma_slverr_set , dma_decerr_set => ch1_dma_decerr_set , updt2_active => ch2_updt_active , updt2_queue_empty => ch2_updt_queue_empty , updt2_ioc => ch2_updt_ioc , updt2_ioc_irq_set => ch2_updt_ioc_irq_set , dma2_interr => ch2_dma_interr , dma2_slverr => ch2_dma_slverr , dma2_decerr => ch2_dma_decerr , dma2_interr_set => ch2_dma_interr_set , dma2_slverr_set => ch2_dma_slverr_set , dma2_decerr_set => ch2_dma_decerr_set , --****************************-- -- Update Interfaces In -- --****************************-- -- Update Pointer Stream s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata , s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid , s_axis_updtptr_tready => s_axis_ch1_updtptr_tready , s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast , -- Update Status Stream s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata , s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid , s_axis_updtsts_tready => s_axis_ch1_updtsts_tready , s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast , -- Update Pointer Stream s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata , s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready , s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- Update Status Stream s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata , s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready , s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast , --****************************-- -- Update Interfaces Out -- --****************************-- -- S2MM Stream Out To DataMover m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata , m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast , m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid , m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready , -- m_axis_updt_tdata => m_axis_ch1_updt_tdata , -- m_axis_updt_tlast => m_axis_ch1_updt_tlast , -- m_axis_updt_tvalid => m_axis_ch1_updt_tvalid , -- m_axis_updt_tready => m_axis_ch1_updt_tready , -- S2MM Stream Out To DataMover -- m_axis2_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis2_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis2_updt_tready => m_axis_ch2_updt_tready ); end generate GEN_NO_QUEUE; -- Channel 1 NOT included therefore tie ch1 outputs off --GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate --begin -- ch1_updt_curdesc_wren <= '0'; -- ch1_updt_curdesc <= (others => '0'); -- ch1_updt_queue_empty <= '1'; -- ch1_updt_ioc <= '0'; -- ch1_dma_interr <= '0'; -- ch1_dma_slverr <= '0'; -- ch1_dma_decerr <= '0'; -- m_axis_ch1_updt_tdata <= (others => '0'); -- m_axis_ch1_updt_tlast <= '0'; -- m_axis_ch1_updt_tvalid <= '0'; -- s_axis_ch1_updtptr_tready <= '0'; -- s_axis_ch1_updtsts_tready <= '0'; --end generate GEN_NO_CH1_UPDATE_Q_IF; --************************************************************************* -- CHANNEL 2 --************************************************************************* ------------------------------------------------------------------------------- -- If Channel 2 is enabled then instantiate descriptor update logic. ------------------------------------------------------------------------------- --GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate -- --begin -- -- --********************************************************************* -- -- CHANNEL 2 - DESCRIPTOR QUEUE -- --********************************************************************* -- -- If Descriptor Update queueing enabled then instantiate Queue Logic -- GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate -- begin -- --------------------------------------------------------------------------- -- I_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue -- generic map( -- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , -- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , -- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , -- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , -- C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE , -- C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE , -- C_FAMILY => C_FAMILY -- ) -- port map( -- --------------------------------------------------------------- -- -- AXI Scatter Gather Interface -- --------------------------------------------------------------- -- m_axi_sg_aclk => m_axi_sg_aclk , -- m_axi_sg_aresetn => m_axi_sg_aresetn , -- s_axis_updt_aclk => s_axis_ch2_updt_aclk , -- -- --****************************-- -- -- Control and Status -- -- --****************************-- -- updt_curdesc_wren => ch2_updt_curdesc_wren , -- updt_curdesc => ch2_updt_curdesc , -- updt_active => ch2_updt_active , -- updt_queue_empty => ch2_updt_queue_empty , -- updt_ioc => ch2_updt_ioc , -- updt_ioc_irq_set => ch2_updt_ioc_irq_set , -- -- dma_interr => ch2_dma_interr , -- dma_slverr => ch2_dma_slverr , -- dma_decerr => ch2_dma_decerr , -- dma_interr_set => ch2_dma_interr_set , -- dma_slverr_set => ch2_dma_slverr_set , -- dma_decerr_set => ch2_dma_decerr_set , -- -- --****************************-- -- -- Update Interfaces In -- -- --****************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata , -- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , -- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready , -- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- -- -- Update Status Stream -- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata , -- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , -- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready , -- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast , -- -- --****************************-- -- -- Update Interfaces Out -- -- --****************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis_updt_tready => m_axis_ch2_updt_tready -- ); -- -- end generate GEN_CH2_QUEUE; -- -- -- --************************************************************************* -- -- CHANNEL 2 - NO DESCRIPTOR QUEUE -- --************************************************************************* -- -- -- No update queue enabled, therefore map internal stream logic -- -- directly to channel port. -- GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate -- I_NO_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue -- generic map( -- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , -- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , -- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , -- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH -- ) -- port map( -- --------------------------------------------------------------- -- -- AXI Scatter Gather Interface -- --------------------------------------------------------------- -- m_axi_sg_aclk => m_axi_sg_aclk , -- m_axi_sg_aresetn => m_axi_sg_aresetn , -- -- --****************************-- -- -- Control and Status -- -- --****************************-- -- updt_curdesc_wren => ch2_updt_curdesc_wren , -- updt_curdesc => ch2_updt_curdesc , -- updt_active => ch2_updt_active , -- updt_queue_empty => ch2_updt_queue_empty , -- updt_ioc => ch2_updt_ioc , -- updt_ioc_irq_set => ch2_updt_ioc_irq_set , -- -- dma_interr => ch2_dma_interr , -- dma_slverr => ch2_dma_slverr , -- dma_decerr => ch2_dma_decerr , -- dma_interr_set => ch2_dma_interr_set , -- dma_slverr_set => ch2_dma_slverr_set , -- dma_decerr_set => ch2_dma_decerr_set , -- -- --****************************-- -- -- Update Interfaces In -- -- --****************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata , -- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , -- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready , -- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- -- -- Update Status Stream -- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata , -- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , -- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready , -- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast , -- -- --****************************-- -- -- Update Interfaces Out -- -- --******************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis_updt_tready => m_axis_ch2_updt_tready -- ); -- -- end generate GEN_CH2_NO_QUEUE; -- --end generate GEN_CH2_UPDATE_Q_IF; -- ---- Channel 2 NOT included therefore tie ch2 outputs off --GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate --begin -- ch2_updt_curdesc_wren <= '0'; -- ch2_updt_curdesc <= (others => '0'); -- ch2_updt_queue_empty <= '1'; -- -- ch2_updt_ioc <= '0'; -- ch2_dma_interr <= '0'; -- ch2_dma_slverr <= '0'; -- ch2_dma_decerr <= '0'; -- -- m_axis_ch2_updt_tdata <= (others => '0'); -- m_axis_ch2_updt_tlast <= '0'; -- m_axis_ch2_updt_tvalid <= '0'; -- -- s_axis_ch2_updtptr_tready <= '0'; -- s_axis_ch2_updtsts_tready <= '0'; -- --end generate GEN_NO_CH2_UPDATE_Q_IF; ------------------------------------------------------------------------------- -- MUX For DataMover ------------------------------------------------------------------------------- --TO_DATAMVR_MUX : process(ch1_updt_active, -- ch2_updt_active, -- m_axis_ch1_updt_tdata, -- m_axis_ch1_updt_tlast, -- m_axis_ch1_updt_tvalid, -- m_axis_ch2_updt_tdata, -- m_axis_ch2_updt_tlast, -- m_axis_ch2_updt_tvalid) -- begin -- if(ch1_updt_active = '1')then -- s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata; -- s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast; -- s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid; -- elsif(ch2_updt_active = '1')then -- s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata; -- s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast; -- s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid; -- else -- s_axis_s2mm_tdata <= (others => '0'); -- s_axis_s2mm_tlast <= '0'; -- s_axis_s2mm_tvalid <= '0'; -- end if; -- end process TO_DATAMVR_MUX; -- --m_axis_ch1_updt_tready <= s_axis_s2mm_tready; --m_axis_ch2_updt_tready <= s_axis_s2mm_tready; -- end implementation;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_gray_rows_V.vhd	2	4556	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_gray_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_gray_rows_V_shiftReg; architecture rtl of FIFO_image_filter_gray_rows_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_gray_rows_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_gray_rows_V is component FIFO_image_filter_gray_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_gray_rows_V_shiftReg : FIFO_image_filter_gray_rows_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;	gpl-3.0
freecores/usb_fpga_1_11	examples/usb-fpga-1.11/1.11c/ucecho/fpga/ucecho.vhd	42	580	library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out unsigned(7 downto 0); CLK : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; pb <= pb_buf; end if; end process dpUCECHO; end RTL;	gpl-3.0
freecores/usb_fpga_1_11	examples/usb-fpga-1.2/ucecho/fpga/ucecho.vhd	42	580	library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out unsigned(7 downto 0); CLK : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; pb <= pb_buf; end if; end process dpUCECHO; end RTL;	gpl-3.0
freecores/usb_fpga_1_11	examples/usb-fpga-1.15/1.15a/ucecho/fpga/ucecho.vhd	42	580	library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out unsigned(7 downto 0); CLK : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; pb <= pb_buf; end if; end process dpUCECHO; end RTL;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_strb_gen2.vhd	18	101757	------------------------------------------------------------------------------- -- axi_datamover_strb_gen2.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_strb_gen2.vhd -- -- Description: -- Second generation AXI Strobe Generator module. This design leverages -- look up table approach vs real-time calculation. This design method is -- used to reduce logic levels and improve final Fmax timing. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_strb_gen2 is generic ( C_OP_MODE : Integer range 0 to 1 := 0; -- 0 = offset/length mode -- 1 = offset/offset mode, C_STRB_WIDTH : Integer := 8; -- number of addr bits needed C_OFFSET_WIDTH : Integer := 3; -- log2(C_STRB_WIDTH) C_NUM_BYTES_WIDTH : Integer := 4 -- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0) -- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1) ); port ( -- Starting offset input ----------------------------------------------------- -- start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); -- -- Specifies the starting address offset of the strobe value -- ------------------------------------------------------------------------------ -- used in both offset/offset and offset/length modes -- Endig Offset Input -------------------------------------------------------- -- end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); -- -- Specifies the ending address offset of the strobe value -- -- used in only offset/offset mode (C_OP_MODE = 1) -- ------------------------------------------------------------------------------ -- Number of valid Bytes input (from starting offset) ------------------------ -- num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); -- -- Specifies the number of valid bytes from starting offset -- -- used in only offset/length mode (C_OP_MODE = 0) -- ------------------------------------------------------------------------------ -- Generated Strobe output --------------------------------------------------- -- strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) -- ------------------------------------------------------------------------------ ); end entity axi_datamover_strb_gen2; architecture implementation of axi_datamover_strb_gen2 is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_2 -- -- Function Description: -- returns the 2-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_2 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "11"; when others => var_start_vector := "10"; end case; Return (var_start_vector); end function get_start_2; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_2 -- -- Function Description: -- Returns the 2-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_2 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "01"; when others => var_end_vector := "11"; end case; Return (var_end_vector); end function get_end_2; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_4 -- -- Function Description: -- returns the 4-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_4 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "1111"; when 1 => var_start_vector := "1110"; when 2 => var_start_vector := "1100"; when others => var_start_vector := "1000"; end case; Return (var_start_vector); end function get_start_4; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_4 -- -- Function Description: -- Returns the 4-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_4 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "0001"; when 1 => var_end_vector := "0011"; when 2 => var_end_vector := "0111"; when others => var_end_vector := "1111"; end case; Return (var_end_vector); end function get_end_4; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_8 -- -- Function Description: -- returns the 8-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_8 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "11111111"; when 1 => var_start_vector := "11111110"; when 2 => var_start_vector := "11111100"; when 3 => var_start_vector := "11111000"; when 4 => var_start_vector := "11110000"; when 5 => var_start_vector := "11100000"; when 6 => var_start_vector := "11000000"; when others => var_start_vector := "10000000"; end case; Return (var_start_vector); end function get_start_8; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_8 -- -- Function Description: -- Returns the 8-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_8 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "00000001"; when 1 => var_end_vector := "00000011"; when 2 => var_end_vector := "00000111"; when 3 => var_end_vector := "00001111"; when 4 => var_end_vector := "00011111"; when 5 => var_end_vector := "00111111"; when 6 => var_end_vector := "01111111"; when others => var_end_vector := "11111111"; end case; Return (var_end_vector); end function get_end_8; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_16 -- -- Function Description: -- returns the 16-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_16 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "1111111111111111"; when 1 => var_start_vector := "1111111111111110"; when 2 => var_start_vector := "1111111111111100"; when 3 => var_start_vector := "1111111111111000"; when 4 => var_start_vector := "1111111111110000"; when 5 => var_start_vector := "1111111111100000"; when 6 => var_start_vector := "1111111111000000"; when 7 => var_start_vector := "1111111110000000"; when 8 => var_start_vector := "1111111100000000"; when 9 => var_start_vector := "1111111000000000"; when 10 => var_start_vector := "1111110000000000"; when 11 => var_start_vector := "1111100000000000"; when 12 => var_start_vector := "1111000000000000"; when 13 => var_start_vector := "1110000000000000"; when 14 => var_start_vector := "1100000000000000"; when others => var_start_vector := "1000000000000000"; end case; Return (var_start_vector); end function get_start_16; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_16 -- -- Function Description: -- Returns the 16-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_16 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "0000000000000001"; when 1 => var_end_vector := "0000000000000011"; when 2 => var_end_vector := "0000000000000111"; when 3 => var_end_vector := "0000000000001111"; when 4 => var_end_vector := "0000000000011111"; when 5 => var_end_vector := "0000000000111111"; when 6 => var_end_vector := "0000000001111111"; when 7 => var_end_vector := "0000000011111111"; when 8 => var_end_vector := "0000000111111111"; when 9 => var_end_vector := "0000001111111111"; when 10 => var_end_vector := "0000011111111111"; when 11 => var_end_vector := "0000111111111111"; when 12 => var_end_vector := "0001111111111111"; when 13 => var_end_vector := "0011111111111111"; when 14 => var_end_vector := "0111111111111111"; when others => var_end_vector := "1111111111111111"; end case; Return (var_end_vector); end function get_end_16; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_32 -- -- Function Description: -- returns the 32-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_32 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "11111111111111111111111111111111"; when 1 => var_start_vector := "11111111111111111111111111111110"; when 2 => var_start_vector := "11111111111111111111111111111100"; when 3 => var_start_vector := "11111111111111111111111111111000"; when 4 => var_start_vector := "11111111111111111111111111110000"; when 5 => var_start_vector := "11111111111111111111111111100000"; when 6 => var_start_vector := "11111111111111111111111111000000"; when 7 => var_start_vector := "11111111111111111111111110000000"; when 8 => var_start_vector := "11111111111111111111111100000000"; when 9 => var_start_vector := "11111111111111111111111000000000"; when 10 => var_start_vector := "11111111111111111111110000000000"; when 11 => var_start_vector := "11111111111111111111100000000000"; when 12 => var_start_vector := "11111111111111111111000000000000"; when 13 => var_start_vector := "11111111111111111110000000000000"; when 14 => var_start_vector := "11111111111111111100000000000000"; when 15 => var_start_vector := "11111111111111111000000000000000"; when 16 => var_start_vector := "11111111111111110000000000000000"; when 17 => var_start_vector := "11111111111111100000000000000000"; when 18 => var_start_vector := "11111111111111000000000000000000"; when 19 => var_start_vector := "11111111111110000000000000000000"; when 20 => var_start_vector := "11111111111100000000000000000000"; when 21 => var_start_vector := "11111111111000000000000000000000"; when 22 => var_start_vector := "11111111110000000000000000000000"; when 23 => var_start_vector := "11111111100000000000000000000000"; when 24 => var_start_vector := "11111111000000000000000000000000"; when 25 => var_start_vector := "11111110000000000000000000000000"; when 26 => var_start_vector := "11111100000000000000000000000000"; when 27 => var_start_vector := "11111000000000000000000000000000"; when 28 => var_start_vector := "11110000000000000000000000000000"; when 29 => var_start_vector := "11100000000000000000000000000000"; when 30 => var_start_vector := "11000000000000000000000000000000"; when others => var_start_vector := "10000000000000000000000000000000"; end case; Return (var_start_vector); end function get_start_32; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_32 -- -- Function Description: -- Returns the 32-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_32 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "00000000000000000000000000000001"; when 1 => var_end_vector := "00000000000000000000000000000011"; when 2 => var_end_vector := "00000000000000000000000000000111"; when 3 => var_end_vector := "00000000000000000000000000001111"; when 4 => var_end_vector := "00000000000000000000000000011111"; when 5 => var_end_vector := "00000000000000000000000000111111"; when 6 => var_end_vector := "00000000000000000000000001111111"; when 7 => var_end_vector := "00000000000000000000000011111111"; when 8 => var_end_vector := "00000000000000000000000111111111"; when 9 => var_end_vector := "00000000000000000000001111111111"; when 10 => var_end_vector := "00000000000000000000011111111111"; when 11 => var_end_vector := "00000000000000000000111111111111"; when 12 => var_end_vector := "00000000000000000001111111111111"; when 13 => var_end_vector := "00000000000000000011111111111111"; when 14 => var_end_vector := "00000000000000000111111111111111"; when 15 => var_end_vector := "00000000000000001111111111111111"; when 16 => var_end_vector := "00000000000000011111111111111111"; when 17 => var_end_vector := "00000000000000111111111111111111"; when 18 => var_end_vector := "00000000000001111111111111111111"; when 19 => var_end_vector := "00000000000011111111111111111111"; when 20 => var_end_vector := "00000000000111111111111111111111"; when 21 => var_end_vector := "00000000001111111111111111111111"; when 22 => var_end_vector := "00000000011111111111111111111111"; when 23 => var_end_vector := "00000000111111111111111111111111"; when 24 => var_end_vector := "00000001111111111111111111111111"; when 25 => var_end_vector := "00000011111111111111111111111111"; when 26 => var_end_vector := "00000111111111111111111111111111"; when 27 => var_end_vector := "00001111111111111111111111111111"; when 28 => var_end_vector := "00011111111111111111111111111111"; when 29 => var_end_vector := "00111111111111111111111111111111"; when 30 => var_end_vector := "01111111111111111111111111111111"; when others => var_end_vector := "11111111111111111111111111111111"; end case; Return (var_end_vector); end function get_end_32; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_64 -- -- Function Description: -- returns the 64-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_64 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111"; when 1 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110"; when 2 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100"; when 3 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000"; when 4 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000"; when 5 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000"; when 6 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000"; when 7 => var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000"; when 8 => var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000"; when 9 => var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000"; when 10 => var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000"; when 11 => var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000"; when 12 => var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000"; when 13 => var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000"; when 14 => var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000"; when 15 => var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000"; when 16 => var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000"; when 17 => var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000"; when 18 => var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000"; when 19 => var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000"; when 20 => var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000"; when 21 => var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000"; when 22 => var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000"; when 23 => var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000"; when 24 => var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000"; when 25 => var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000"; when 26 => var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000"; when 27 => var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000"; when 28 => var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000"; when 29 => var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000"; when 30 => var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000"; when 31 => var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000"; when 32 => var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000"; when 33 => var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000"; when 34 => var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000"; when 35 => var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000"; when 36 => var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000"; when 37 => var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000"; when 38 => var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000"; when 39 => var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000"; when 40 => var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000"; when 41 => var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000"; when 42 => var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000"; when 43 => var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000"; when 44 => var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000"; when 45 => var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000"; when 46 => var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000"; when 47 => var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000"; when 48 => var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000"; when 49 => var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000"; when 50 => var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000"; when 51 => var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000"; when 52 => var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000"; when 53 => var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000"; when 54 => var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000"; when 55 => var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000"; when 56 => var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000"; when 57 => var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000"; when 58 => var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000"; when 59 => var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000"; when 60 => var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000"; when 61 => var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000"; when 62 => var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000"; when others => var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000"; end case; Return (var_start_vector); end function get_start_64; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_64 -- -- Function Description: -- Returns the 64-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_64 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001"; when 1 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011"; when 2 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111"; when 3 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111"; when 4 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111"; when 5 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111"; when 6 => var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111"; when 7 => var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111"; when 8 => var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111"; when 9 => var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111"; when 10 => var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111"; when 11 => var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111"; when 12 => var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111"; when 13 => var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111"; when 14 => var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111"; when 15 => var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111"; when 16 => var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111"; when 17 => var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111"; when 18 => var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111"; when 19 => var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111"; when 20 => var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111"; when 21 => var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111"; when 22 => var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111"; when 23 => var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111"; when 24 => var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111"; when 25 => var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111"; when 26 => var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111"; when 27 => var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111"; when 28 => var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111"; when 29 => var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111"; when 30 => var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111"; when 31 => var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111"; when 32 => var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111"; when 33 => var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111"; when 34 => var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111"; when 35 => var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111"; when 36 => var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111"; when 37 => var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111"; when 38 => var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111"; when 39 => var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111"; when 40 => var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111"; when 41 => var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111"; when 42 => var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111"; when 43 => var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111"; when 44 => var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111"; when 45 => var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111"; when 46 => var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111"; when 47 => var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111"; when 48 => var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111"; when 49 => var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111"; when 50 => var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111"; when 51 => var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111"; when 52 => var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111"; when 53 => var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111"; when 54 => var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111"; when 55 => var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111"; when 56 => var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111"; when 57 => var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111"; when 58 => var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111"; when 59 => var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111"; when 60 => var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111"; when 61 => var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111"; when 62 => var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111"; when others => var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111"; end case; Return (var_end_vector); end function get_end_64; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_128 -- -- Function Description: -- returns the 128-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_128 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector(127 downto 0) := (others => '1'); when 1 => var_start_vector(127 downto 1) := (others => '1'); var_start_vector( 0 downto 0) := (others => '0'); when 2 => var_start_vector(127 downto 2) := (others => '1'); var_start_vector( 1 downto 0) := (others => '0'); when 3 => var_start_vector(127 downto 3) := (others => '1'); var_start_vector( 2 downto 0) := (others => '0'); when 4 => var_start_vector(127 downto 4) := (others => '1'); var_start_vector( 3 downto 0) := (others => '0'); when 5 => var_start_vector(127 downto 5) := (others => '1'); var_start_vector( 4 downto 0) := (others => '0'); when 6 => var_start_vector(127 downto 6) := (others => '1'); var_start_vector( 5 downto 0) := (others => '0'); when 7 => var_start_vector(127 downto 7) := (others => '1'); var_start_vector( 6 downto 0) := (others => '0'); when 8 => var_start_vector(127 downto 8) := (others => '1'); var_start_vector( 7 downto 0) := (others => '0'); when 9 => var_start_vector(127 downto 9) := (others => '1'); var_start_vector( 8 downto 0) := (others => '0'); when 10 => var_start_vector(127 downto 10) := (others => '1'); var_start_vector( 9 downto 0) := (others => '0'); when 11 => var_start_vector(127 downto 11) := (others => '1'); var_start_vector( 10 downto 0) := (others => '0'); when 12 => var_start_vector(127 downto 12) := (others => '1'); var_start_vector( 11 downto 0) := (others => '0'); when 13 => var_start_vector(127 downto 13) := (others => '1'); var_start_vector( 12 downto 0) := (others => '0'); when 14 => var_start_vector(127 downto 14) := (others => '1'); var_start_vector( 13 downto 0) := (others => '0'); when 15 => var_start_vector(127 downto 15) := (others => '1'); var_start_vector( 14 downto 0) := (others => '0'); when 16 => var_start_vector(127 downto 16) := (others => '1'); var_start_vector( 15 downto 0) := (others => '0'); when 17 => var_start_vector(127 downto 17) := (others => '1'); var_start_vector( 16 downto 0) := (others => '0'); when 18 => var_start_vector(127 downto 18) := (others => '1'); var_start_vector( 17 downto 0) := (others => '0'); when 19 => var_start_vector(127 downto 19) := (others => '1'); var_start_vector( 18 downto 0) := (others => '0'); when 20 => var_start_vector(127 downto 20) := (others => '1'); var_start_vector( 19 downto 0) := (others => '0'); when 21 => var_start_vector(127 downto 21) := (others => '1'); var_start_vector( 20 downto 0) := (others => '0'); when 22 => var_start_vector(127 downto 22) := (others => '1'); var_start_vector( 21 downto 0) := (others => '0'); when 23 => var_start_vector(127 downto 23) := (others => '1'); var_start_vector( 22 downto 0) := (others => '0'); when 24 => var_start_vector(127 downto 24) := (others => '1'); var_start_vector( 23 downto 0) := (others => '0'); when 25 => var_start_vector(127 downto 25) := (others => '1'); var_start_vector( 24 downto 0) := (others => '0'); when 26 => var_start_vector(127 downto 26) := (others => '1'); var_start_vector( 25 downto 0) := (others => '0'); when 27 => var_start_vector(127 downto 27) := (others => '1'); var_start_vector( 26 downto 0) := (others => '0'); when 28 => var_start_vector(127 downto 28) := (others => '1'); var_start_vector( 27 downto 0) := (others => '0'); when 29 => var_start_vector(127 downto 29) := (others => '1'); var_start_vector( 28 downto 0) := (others => '0'); when 30 => var_start_vector(127 downto 30) := (others => '1'); var_start_vector( 29 downto 0) := (others => '0'); when 31 => var_start_vector(127 downto 31) := (others => '1'); var_start_vector( 30 downto 0) := (others => '0'); when 32 => var_start_vector(127 downto 32) := (others => '1'); var_start_vector( 31 downto 0) := (others => '0'); when 33 => var_start_vector(127 downto 33) := (others => '1'); var_start_vector( 32 downto 0) := (others => '0'); when 34 => var_start_vector(127 downto 34) := (others => '1'); var_start_vector( 33 downto 0) := (others => '0'); when 35 => var_start_vector(127 downto 35) := (others => '1'); var_start_vector( 34 downto 0) := (others => '0'); when 36 => var_start_vector(127 downto 36) := (others => '1'); var_start_vector( 35 downto 0) := (others => '0'); when 37 => var_start_vector(127 downto 37) := (others => '1'); var_start_vector( 36 downto 0) := (others => '0'); when 38 => var_start_vector(127 downto 38) := (others => '1'); var_start_vector( 37 downto 0) := (others => '0'); when 39 => var_start_vector(127 downto 39) := (others => '1'); var_start_vector( 38 downto 0) := (others => '0'); when 40 => var_start_vector(127 downto 40) := (others => '1'); var_start_vector( 39 downto 0) := (others => '0'); when 41 => var_start_vector(127 downto 41) := (others => '1'); var_start_vector( 40 downto 0) := (others => '0'); when 42 => var_start_vector(127 downto 42) := (others => '1'); var_start_vector( 41 downto 0) := (others => '0'); when 43 => var_start_vector(127 downto 43) := (others => '1'); var_start_vector( 42 downto 0) := (others => '0'); when 44 => var_start_vector(127 downto 44) := (others => '1'); var_start_vector( 43 downto 0) := (others => '0'); when 45 => var_start_vector(127 downto 45) := (others => '1'); var_start_vector( 44 downto 0) := (others => '0'); when 46 => var_start_vector(127 downto 46) := (others => '1'); var_start_vector( 45 downto 0) := (others => '0'); when 47 => var_start_vector(127 downto 47) := (others => '1'); var_start_vector( 46 downto 0) := (others => '0'); when 48 => var_start_vector(127 downto 48) := (others => '1'); var_start_vector( 47 downto 0) := (others => '0'); when 49 => var_start_vector(127 downto 49) := (others => '1'); var_start_vector( 48 downto 0) := (others => '0'); when 50 => var_start_vector(127 downto 50) := (others => '1'); var_start_vector( 49 downto 0) := (others => '0'); when 51 => var_start_vector(127 downto 51) := (others => '1'); var_start_vector( 50 downto 0) := (others => '0'); when 52 => var_start_vector(127 downto 52) := (others => '1'); var_start_vector( 51 downto 0) := (others => '0'); when 53 => var_start_vector(127 downto 53) := (others => '1'); var_start_vector( 52 downto 0) := (others => '0'); when 54 => var_start_vector(127 downto 54) := (others => '1'); var_start_vector( 53 downto 0) := (others => '0'); when 55 => var_start_vector(127 downto 55) := (others => '1'); var_start_vector( 54 downto 0) := (others => '0'); when 56 => var_start_vector(127 downto 56) := (others => '1'); var_start_vector( 55 downto 0) := (others => '0'); when 57 => var_start_vector(127 downto 57) := (others => '1'); var_start_vector( 56 downto 0) := (others => '0'); when 58 => var_start_vector(127 downto 58) := (others => '1'); var_start_vector( 57 downto 0) := (others => '0'); when 59 => var_start_vector(127 downto 59) := (others => '1'); var_start_vector( 58 downto 0) := (others => '0'); when 60 => var_start_vector(127 downto 60) := (others => '1'); var_start_vector( 59 downto 0) := (others => '0'); when 61 => var_start_vector(127 downto 61) := (others => '1'); var_start_vector( 60 downto 0) := (others => '0'); when 62 => var_start_vector(127 downto 62) := (others => '1'); var_start_vector( 61 downto 0) := (others => '0'); when 63 => var_start_vector(127 downto 63) := (others => '1'); var_start_vector( 62 downto 0) := (others => '0'); when 64 => var_start_vector(127 downto 64) := (others => '1'); var_start_vector( 63 downto 0) := (others => '0'); when 65 => var_start_vector(127 downto 65) := (others => '1'); var_start_vector( 64 downto 0) := (others => '0'); when 66 => var_start_vector(127 downto 66) := (others => '1'); var_start_vector( 65 downto 0) := (others => '0'); when 67 => var_start_vector(127 downto 67) := (others => '1'); var_start_vector( 66 downto 0) := (others => '0'); when 68 => var_start_vector(127 downto 68) := (others => '1'); var_start_vector( 67 downto 0) := (others => '0'); when 69 => var_start_vector(127 downto 69) := (others => '1'); var_start_vector( 68 downto 0) := (others => '0'); when 70 => var_start_vector(127 downto 70) := (others => '1'); var_start_vector( 69 downto 0) := (others => '0'); when 71 => var_start_vector(127 downto 71) := (others => '1'); var_start_vector( 70 downto 0) := (others => '0'); when 72 => var_start_vector(127 downto 72) := (others => '1'); var_start_vector( 71 downto 0) := (others => '0'); when 73 => var_start_vector(127 downto 73) := (others => '1'); var_start_vector( 72 downto 0) := (others => '0'); when 74 => var_start_vector(127 downto 74) := (others => '1'); var_start_vector( 73 downto 0) := (others => '0'); when 75 => var_start_vector(127 downto 75) := (others => '1'); var_start_vector( 74 downto 0) := (others => '0'); when 76 => var_start_vector(127 downto 76) := (others => '1'); var_start_vector( 75 downto 0) := (others => '0'); when 77 => var_start_vector(127 downto 77) := (others => '1'); var_start_vector( 76 downto 0) := (others => '0'); when 78 => var_start_vector(127 downto 78) := (others => '1'); var_start_vector( 77 downto 0) := (others => '0'); when 79 => var_start_vector(127 downto 79) := (others => '1'); var_start_vector( 78 downto 0) := (others => '0'); when 80 => var_start_vector(127 downto 80) := (others => '1'); var_start_vector( 79 downto 0) := (others => '0'); when 81 => var_start_vector(127 downto 81) := (others => '1'); var_start_vector( 80 downto 0) := (others => '0'); when 82 => var_start_vector(127 downto 82) := (others => '1'); var_start_vector( 81 downto 0) := (others => '0'); when 83 => var_start_vector(127 downto 83) := (others => '1'); var_start_vector( 82 downto 0) := (others => '0'); when 84 => var_start_vector(127 downto 84) := (others => '1'); var_start_vector( 83 downto 0) := (others => '0'); when 85 => var_start_vector(127 downto 85) := (others => '1'); var_start_vector( 84 downto 0) := (others => '0'); when 86 => var_start_vector(127 downto 86) := (others => '1'); var_start_vector( 85 downto 0) := (others => '0'); when 87 => var_start_vector(127 downto 87) := (others => '1'); var_start_vector( 86 downto 0) := (others => '0'); when 88 => var_start_vector(127 downto 88) := (others => '1'); var_start_vector( 87 downto 0) := (others => '0'); when 89 => var_start_vector(127 downto 89) := (others => '1'); var_start_vector( 88 downto 0) := (others => '0'); when 90 => var_start_vector(127 downto 90) := (others => '1'); var_start_vector( 89 downto 0) := (others => '0'); when 91 => var_start_vector(127 downto 91) := (others => '1'); var_start_vector( 90 downto 0) := (others => '0'); when 92 => var_start_vector(127 downto 92) := (others => '1'); var_start_vector( 91 downto 0) := (others => '0'); when 93 => var_start_vector(127 downto 93) := (others => '1'); var_start_vector( 92 downto 0) := (others => '0'); when 94 => var_start_vector(127 downto 94) := (others => '1'); var_start_vector( 93 downto 0) := (others => '0'); when 95 => var_start_vector(127 downto 95) := (others => '1'); var_start_vector( 94 downto 0) := (others => '0'); when 96 => var_start_vector(127 downto 96) := (others => '1'); var_start_vector( 95 downto 0) := (others => '0'); when 97 => var_start_vector(127 downto 97) := (others => '1'); var_start_vector( 96 downto 0) := (others => '0'); when 98 => var_start_vector(127 downto 98) := (others => '1'); var_start_vector( 97 downto 0) := (others => '0'); when 99 => var_start_vector(127 downto 99) := (others => '1'); var_start_vector( 98 downto 0) := (others => '0'); when 100 => var_start_vector(127 downto 100) := (others => '1'); var_start_vector( 99 downto 0) := (others => '0'); when 101 => var_start_vector(127 downto 101) := (others => '1'); var_start_vector(100 downto 0) := (others => '0'); when 102 => var_start_vector(127 downto 102) := (others => '1'); var_start_vector(101 downto 0) := (others => '0'); when 103 => var_start_vector(127 downto 103) := (others => '1'); var_start_vector(102 downto 0) := (others => '0'); when 104 => var_start_vector(127 downto 104) := (others => '1'); var_start_vector(103 downto 0) := (others => '0'); when 105 => var_start_vector(127 downto 105) := (others => '1'); var_start_vector(104 downto 0) := (others => '0'); when 106 => var_start_vector(127 downto 106) := (others => '1'); var_start_vector(105 downto 0) := (others => '0'); when 107 => var_start_vector(127 downto 107) := (others => '1'); var_start_vector(106 downto 0) := (others => '0'); when 108 => var_start_vector(127 downto 108) := (others => '1'); var_start_vector(107 downto 0) := (others => '0'); when 109 => var_start_vector(127 downto 109) := (others => '1'); var_start_vector(108 downto 0) := (others => '0'); when 110 => var_start_vector(127 downto 110) := (others => '1'); var_start_vector(109 downto 0) := (others => '0'); when 111 => var_start_vector(127 downto 111) := (others => '1'); var_start_vector(110 downto 0) := (others => '0'); when 112 => var_start_vector(127 downto 112) := (others => '1'); var_start_vector(111 downto 0) := (others => '0'); when 113 => var_start_vector(127 downto 113) := (others => '1'); var_start_vector(112 downto 0) := (others => '0'); when 114 => var_start_vector(127 downto 114) := (others => '1'); var_start_vector(113 downto 0) := (others => '0'); when 115 => var_start_vector(127 downto 115) := (others => '1'); var_start_vector(114 downto 0) := (others => '0'); when 116 => var_start_vector(127 downto 116) := (others => '1'); var_start_vector(115 downto 0) := (others => '0'); when 117 => var_start_vector(127 downto 117) := (others => '1'); var_start_vector(116 downto 0) := (others => '0'); when 118 => var_start_vector(127 downto 118) := (others => '1'); var_start_vector(117 downto 0) := (others => '0'); when 119 => var_start_vector(127 downto 119) := (others => '1'); var_start_vector(118 downto 0) := (others => '0'); when 120 => var_start_vector(127 downto 120) := (others => '1'); var_start_vector(119 downto 0) := (others => '0'); when 121 => var_start_vector(127 downto 121) := (others => '1'); var_start_vector(120 downto 0) := (others => '0'); when 122 => var_start_vector(127 downto 122) := (others => '1'); var_start_vector(121 downto 0) := (others => '0'); when 123 => var_start_vector(127 downto 123) := (others => '1'); var_start_vector(122 downto 0) := (others => '0'); when 124 => var_start_vector(127 downto 124) := (others => '1'); var_start_vector(123 downto 0) := (others => '0'); when 125 => var_start_vector(127 downto 125) := (others => '1'); var_start_vector(124 downto 0) := (others => '0'); when 126 => var_start_vector(127 downto 126) := (others => '1'); var_start_vector(125 downto 0) := (others => '0'); when others => var_start_vector(127 downto 127) := (others => '1'); var_start_vector(126 downto 0) := (others => '0'); end case; Return (var_start_vector); end function get_start_128; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_128 -- -- Function Description: -- Returns the 128-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_128 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector(127 downto 1) := (others => '0'); var_end_vector( 0 downto 0) := (others => '1'); when 1 => var_end_vector(127 downto 2) := (others => '0'); var_end_vector( 1 downto 0) := (others => '1'); when 2 => var_end_vector(127 downto 3) := (others => '0'); var_end_vector( 2 downto 0) := (others => '1'); when 3 => var_end_vector(127 downto 4) := (others => '0'); var_end_vector( 3 downto 0) := (others => '1'); when 4 => var_end_vector(127 downto 5) := (others => '0'); var_end_vector( 4 downto 0) := (others => '1'); when 5 => var_end_vector(127 downto 6) := (others => '0'); var_end_vector( 5 downto 0) := (others => '1'); when 6 => var_end_vector(127 downto 7) := (others => '0'); var_end_vector( 6 downto 0) := (others => '1'); when 7 => var_end_vector(127 downto 8) := (others => '0'); var_end_vector( 7 downto 0) := (others => '1'); when 8 => var_end_vector(127 downto 9) := (others => '0'); var_end_vector( 8 downto 0) := (others => '1'); when 9 => var_end_vector(127 downto 10) := (others => '0'); var_end_vector( 9 downto 0) := (others => '1'); when 10 => var_end_vector(127 downto 11) := (others => '0'); var_end_vector( 10 downto 0) := (others => '1'); when 11 => var_end_vector(127 downto 12) := (others => '0'); var_end_vector( 11 downto 0) := (others => '1'); when 12 => var_end_vector(127 downto 13) := (others => '0'); var_end_vector( 12 downto 0) := (others => '1'); when 13 => var_end_vector(127 downto 14) := (others => '0'); var_end_vector( 13 downto 0) := (others => '1'); when 14 => var_end_vector(127 downto 15) := (others => '0'); var_end_vector( 14 downto 0) := (others => '1'); when 15 => var_end_vector(127 downto 16) := (others => '0'); var_end_vector( 15 downto 0) := (others => '1'); when 16 => var_end_vector(127 downto 17) := (others => '0'); var_end_vector( 16 downto 0) := (others => '1'); when 17 => var_end_vector(127 downto 18) := (others => '0'); var_end_vector( 17 downto 0) := (others => '1'); when 18 => var_end_vector(127 downto 19) := (others => '0'); var_end_vector( 18 downto 0) := (others => '1'); when 19 => var_end_vector(127 downto 20) := (others => '0'); var_end_vector( 19 downto 0) := (others => '1'); when 20 => var_end_vector(127 downto 21) := (others => '0'); var_end_vector( 20 downto 0) := (others => '1'); when 21 => var_end_vector(127 downto 22) := (others => '0'); var_end_vector( 21 downto 0) := (others => '1'); when 22 => var_end_vector(127 downto 23) := (others => '0'); var_end_vector( 22 downto 0) := (others => '1'); when 23 => var_end_vector(127 downto 24) := (others => '0'); var_end_vector( 23 downto 0) := (others => '1'); when 24 => var_end_vector(127 downto 25) := (others => '0'); var_end_vector( 24 downto 0) := (others => '1'); when 25 => var_end_vector(127 downto 26) := (others => '0'); var_end_vector( 25 downto 0) := (others => '1'); when 26 => var_end_vector(127 downto 27) := (others => '0'); var_end_vector( 26 downto 0) := (others => '1'); when 27 => var_end_vector(127 downto 28) := (others => '0'); var_end_vector( 27 downto 0) := (others => '1'); when 28 => var_end_vector(127 downto 29) := (others => '0'); var_end_vector( 28 downto 0) := (others => '1'); when 29 => var_end_vector(127 downto 30) := (others => '0'); var_end_vector( 29 downto 0) := (others => '1'); when 30 => var_end_vector(127 downto 31) := (others => '0'); var_end_vector( 30 downto 0) := (others => '1'); when 31 => var_end_vector(127 downto 32) := (others => '0'); var_end_vector( 31 downto 0) := (others => '1'); when 32 => var_end_vector(127 downto 33) := (others => '0'); var_end_vector( 32 downto 0) := (others => '1'); when 33 => var_end_vector(127 downto 34) := (others => '0'); var_end_vector( 33 downto 0) := (others => '1'); when 34 => var_end_vector(127 downto 35) := (others => '0'); var_end_vector( 34 downto 0) := (others => '1'); when 35 => var_end_vector(127 downto 36) := (others => '0'); var_end_vector( 35 downto 0) := (others => '1'); when 36 => var_end_vector(127 downto 37) := (others => '0'); var_end_vector( 36 downto 0) := (others => '1'); when 37 => var_end_vector(127 downto 38) := (others => '0'); var_end_vector( 37 downto 0) := (others => '1'); when 38 => var_end_vector(127 downto 39) := (others => '0'); var_end_vector( 38 downto 0) := (others => '1'); when 39 => var_end_vector(127 downto 40) := (others => '0'); var_end_vector( 39 downto 0) := (others => '1'); when 40 => var_end_vector(127 downto 41) := (others => '0'); var_end_vector( 40 downto 0) := (others => '1'); when 41 => var_end_vector(127 downto 42) := (others => '0'); var_end_vector( 41 downto 0) := (others => '1'); when 42 => var_end_vector(127 downto 43) := (others => '0'); var_end_vector( 42 downto 0) := (others => '1'); when 43 => var_end_vector(127 downto 44) := (others => '0'); var_end_vector( 43 downto 0) := (others => '1'); when 44 => var_end_vector(127 downto 45) := (others => '0'); var_end_vector( 44 downto 0) := (others => '1'); when 45 => var_end_vector(127 downto 46) := (others => '0'); var_end_vector( 45 downto 0) := (others => '1'); when 46 => var_end_vector(127 downto 47) := (others => '0'); var_end_vector( 46 downto 0) := (others => '1'); when 47 => var_end_vector(127 downto 48) := (others => '0'); var_end_vector( 47 downto 0) := (others => '1'); when 48 => var_end_vector(127 downto 49) := (others => '0'); var_end_vector( 48 downto 0) := (others => '1'); when 49 => var_end_vector(127 downto 50) := (others => '0'); var_end_vector( 49 downto 0) := (others => '1'); when 50 => var_end_vector(127 downto 51) := (others => '0'); var_end_vector( 50 downto 0) := (others => '1'); when 51 => var_end_vector(127 downto 52) := (others => '0'); var_end_vector( 51 downto 0) := (others => '1'); when 52 => var_end_vector(127 downto 53) := (others => '0'); var_end_vector( 52 downto 0) := (others => '1'); when 53 => var_end_vector(127 downto 54) := (others => '0'); var_end_vector( 53 downto 0) := (others => '1'); when 54 => var_end_vector(127 downto 55) := (others => '0'); var_end_vector( 54 downto 0) := (others => '1'); when 55 => var_end_vector(127 downto 56) := (others => '0'); var_end_vector( 55 downto 0) := (others => '1'); when 56 => var_end_vector(127 downto 57) := (others => '0'); var_end_vector( 56 downto 0) := (others => '1'); when 57 => var_end_vector(127 downto 58) := (others => '0'); var_end_vector( 57 downto 0) := (others => '1'); when 58 => var_end_vector(127 downto 59) := (others => '0'); var_end_vector( 58 downto 0) := (others => '1'); when 59 => var_end_vector(127 downto 60) := (others => '0'); var_end_vector( 59 downto 0) := (others => '1'); when 60 => var_end_vector(127 downto 61) := (others => '0'); var_end_vector( 60 downto 0) := (others => '1'); when 61 => var_end_vector(127 downto 62) := (others => '0'); var_end_vector( 61 downto 0) := (others => '1'); when 62 => var_end_vector(127 downto 63) := (others => '0'); var_end_vector( 62 downto 0) := (others => '1'); when 63 => var_end_vector(127 downto 64) := (others => '0'); var_end_vector( 63 downto 0) := (others => '1'); when 64 => var_end_vector(127 downto 65) := (others => '0'); var_end_vector( 64 downto 0) := (others => '1'); when 65 => var_end_vector(127 downto 66) := (others => '0'); var_end_vector( 65 downto 0) := (others => '1'); when 66 => var_end_vector(127 downto 67) := (others => '0'); var_end_vector( 66 downto 0) := (others => '1'); when 67 => var_end_vector(127 downto 68) := (others => '0'); var_end_vector( 67 downto 0) := (others => '1'); when 68 => var_end_vector(127 downto 69) := (others => '0'); var_end_vector( 68 downto 0) := (others => '1'); when 69 => var_end_vector(127 downto 70) := (others => '0'); var_end_vector( 69 downto 0) := (others => '1'); when 70 => var_end_vector(127 downto 71) := (others => '0'); var_end_vector( 70 downto 0) := (others => '1'); when 71 => var_end_vector(127 downto 72) := (others => '0'); var_end_vector( 71 downto 0) := (others => '1'); when 72 => var_end_vector(127 downto 73) := (others => '0'); var_end_vector( 72 downto 0) := (others => '1'); when 73 => var_end_vector(127 downto 74) := (others => '0'); var_end_vector( 73 downto 0) := (others => '1'); when 74 => var_end_vector(127 downto 75) := (others => '0'); var_end_vector( 74 downto 0) := (others => '1'); when 75 => var_end_vector(127 downto 76) := (others => '0'); var_end_vector( 75 downto 0) := (others => '1'); when 76 => var_end_vector(127 downto 77) := (others => '0'); var_end_vector( 76 downto 0) := (others => '1'); when 77 => var_end_vector(127 downto 78) := (others => '0'); var_end_vector( 77 downto 0) := (others => '1'); when 78 => var_end_vector(127 downto 79) := (others => '0'); var_end_vector( 78 downto 0) := (others => '1'); when 79 => var_end_vector(127 downto 80) := (others => '0'); var_end_vector( 79 downto 0) := (others => '1'); when 80 => var_end_vector(127 downto 81) := (others => '0'); var_end_vector( 80 downto 0) := (others => '1'); when 81 => var_end_vector(127 downto 82) := (others => '0'); var_end_vector( 81 downto 0) := (others => '1'); when 82 => var_end_vector(127 downto 83) := (others => '0'); var_end_vector( 82 downto 0) := (others => '1'); when 83 => var_end_vector(127 downto 84) := (others => '0'); var_end_vector( 83 downto 0) := (others => '1'); when 84 => var_end_vector(127 downto 85) := (others => '0'); var_end_vector( 84 downto 0) := (others => '1'); when 85 => var_end_vector(127 downto 86) := (others => '0'); var_end_vector( 85 downto 0) := (others => '1'); when 86 => var_end_vector(127 downto 87) := (others => '0'); var_end_vector( 86 downto 0) := (others => '1'); when 87 => var_end_vector(127 downto 88) := (others => '0'); var_end_vector( 87 downto 0) := (others => '1'); when 88 => var_end_vector(127 downto 89) := (others => '0'); var_end_vector( 88 downto 0) := (others => '1'); when 89 => var_end_vector(127 downto 90) := (others => '0'); var_end_vector( 89 downto 0) := (others => '1'); when 90 => var_end_vector(127 downto 91) := (others => '0'); var_end_vector( 90 downto 0) := (others => '1'); when 91 => var_end_vector(127 downto 92) := (others => '0'); var_end_vector( 91 downto 0) := (others => '1'); when 92 => var_end_vector(127 downto 93) := (others => '0'); var_end_vector( 92 downto 0) := (others => '1'); when 93 => var_end_vector(127 downto 94) := (others => '0'); var_end_vector( 93 downto 0) := (others => '1'); when 94 => var_end_vector(127 downto 95) := (others => '0'); var_end_vector( 94 downto 0) := (others => '1'); when 95 => var_end_vector(127 downto 96) := (others => '0'); var_end_vector( 95 downto 0) := (others => '1'); when 96 => var_end_vector(127 downto 97) := (others => '0'); var_end_vector( 96 downto 0) := (others => '1'); when 97 => var_end_vector(127 downto 98) := (others => '0'); var_end_vector( 97 downto 0) := (others => '1'); when 98 => var_end_vector(127 downto 99) := (others => '0'); var_end_vector( 98 downto 0) := (others => '1'); when 99 => var_end_vector(127 downto 100) := (others => '0'); var_end_vector( 99 downto 0) := (others => '1'); when 100 => var_end_vector(127 downto 101) := (others => '0'); var_end_vector(100 downto 0) := (others => '1'); when 101 => var_end_vector(127 downto 102) := (others => '0'); var_end_vector(101 downto 0) := (others => '1'); when 102 => var_end_vector(127 downto 103) := (others => '0'); var_end_vector(102 downto 0) := (others => '1'); when 103 => var_end_vector(127 downto 104) := (others => '0'); var_end_vector(103 downto 0) := (others => '1'); when 104 => var_end_vector(127 downto 105) := (others => '0'); var_end_vector(104 downto 0) := (others => '1'); when 105 => var_end_vector(127 downto 106) := (others => '0'); var_end_vector(105 downto 0) := (others => '1'); when 106 => var_end_vector(127 downto 107) := (others => '0'); var_end_vector(106 downto 0) := (others => '1'); when 107 => var_end_vector(127 downto 108) := (others => '0'); var_end_vector(107 downto 0) := (others => '1'); when 108 => var_end_vector(127 downto 109) := (others => '0'); var_end_vector(108 downto 0) := (others => '1'); when 109 => var_end_vector(127 downto 110) := (others => '0'); var_end_vector(109 downto 0) := (others => '1'); when 110 => var_end_vector(127 downto 111) := (others => '0'); var_end_vector(110 downto 0) := (others => '1'); when 111 => var_end_vector(127 downto 112) := (others => '0'); var_end_vector(111 downto 0) := (others => '1'); when 112 => var_end_vector(127 downto 113) := (others => '0'); var_end_vector(112 downto 0) := (others => '1'); when 113 => var_end_vector(127 downto 114) := (others => '0'); var_end_vector(113 downto 0) := (others => '1'); when 114 => var_end_vector(127 downto 115) := (others => '0'); var_end_vector(114 downto 0) := (others => '1'); when 115 => var_end_vector(127 downto 116) := (others => '0'); var_end_vector(115 downto 0) := (others => '1'); when 116 => var_end_vector(127 downto 117) := (others => '0'); var_end_vector(116 downto 0) := (others => '1'); when 117 => var_end_vector(127 downto 118) := (others => '0'); var_end_vector(117 downto 0) := (others => '1'); when 118 => var_end_vector(127 downto 119) := (others => '0'); var_end_vector(118 downto 0) := (others => '1'); when 119 => var_end_vector(127 downto 120) := (others => '0'); var_end_vector(119 downto 0) := (others => '1'); when 120 => var_end_vector(127 downto 121) := (others => '0'); var_end_vector(120 downto 0) := (others => '1'); when 121 => var_end_vector(127 downto 122) := (others => '0'); var_end_vector(121 downto 0) := (others => '1'); when 122 => var_end_vector(127 downto 123) := (others => '0'); var_end_vector(122 downto 0) := (others => '1'); when 123 => var_end_vector(127 downto 124) := (others => '0'); var_end_vector(123 downto 0) := (others => '1'); when 124 => var_end_vector(127 downto 125) := (others => '0'); var_end_vector(124 downto 0) := (others => '1'); when 125 => var_end_vector(127 downto 126) := (others => '0'); var_end_vector(125 downto 0) := (others => '1'); when 126 => var_end_vector(127 downto 127) := (others => '0'); var_end_vector(126 downto 0) := (others => '1'); when others => var_end_vector(127 downto 0) := (others => '1'); end case; Return (var_end_vector); end function get_end_128; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_clip_value -- -- Function Description: -- Returns a value that cannot exceed a clip value. -- ------------------------------------------------------------------- function funct_clip_value (input_value : natural; max_value : natural) return natural is Variable temp_value : Natural := 0; begin If (input_value <= max_value) Then temp_value := input_value; Else temp_value := max_value; End if; Return (temp_value); end function funct_clip_value; -- Constants Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom -- if op Mode = 1 -- Signals signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); begin --(architecture implementation) -- Assign the output strobe value strb_out <= sig_ouput_stbs ; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OFF_OFF_CASE -- -- If Generate Description: -- Calculates the internal start and end offsets for the -- case when start and end offsets are being provided. -- -- ------------------------------------------------------------ GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate begin sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH); sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH); end generate GEN_OFF_OFF_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OFF_LEN_CASE -- -- If Generate Description: -- Calculates the internal start and end offsets for the -- case when start offset and length are being provided. -- ------------------------------------------------------------ GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate -- Local Constants Declarations Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH; Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH); Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH); Constant MAX_VALUE : natural := C_STRB_WIDTH-1; -- local signals signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_end_addr_int : integer := 0; signal lsig_strt_addr_int : integer := 0; begin lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH); lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH); lsig_length_adjust_us <= L_ZERO When (lsig_num_valid_bytes_us = L_ZERO) Else L_ONE; lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us; lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us; lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us); lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us); sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH); sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ; end generate GEN_OFF_LEN_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_1BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 1-bit strobe width case. -- -- ------------------------------------------------------------ GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate begin sig_ouput_stbs <= (others => '1') ; end generate GEN_1BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_2BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 2-bit strobe width case. -- -- ------------------------------------------------------------ GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 1; Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_2(lsig_start_offset); lsig_end_vect <= get_end_2(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_2BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_4BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 4-bit strobe width case. -- -- ------------------------------------------------------------ GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 3; Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_4(lsig_start_offset); lsig_end_vect <= get_end_4(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_4BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_8BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 8-bit strobe width case. -- -- ------------------------------------------------------------ GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 7; Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_8(lsig_start_offset); lsig_end_vect <= get_end_8(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_8BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_16BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 16-bit strobe width case. -- -- ------------------------------------------------------------ GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 15; Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_16(lsig_start_offset); lsig_end_vect <= get_end_16(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_16BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_32BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 32-bit strobe width case. -- -- ------------------------------------------------------------ GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 31; Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_32(lsig_start_offset); lsig_end_vect <= get_end_32(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_32BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_64BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 64-bit strobe width case. -- -- ------------------------------------------------------------ GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 63; Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_64(lsig_start_offset); lsig_end_vect <= get_end_64(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_64BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_128BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 64-bit strobe width case. -- -- ------------------------------------------------------------ GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 127; Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_128(lsig_start_offset); lsig_end_vect <= get_end_128(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_128BIT_CASE; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_mm2s_sm.vhd	2	28379	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_mm2s_sm.vhd -- Description: This entity contains the MM2S DMA Controller State Machine -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.clog2; ------------------------------------------------------------------------------- entity axi_dma_mm2s_sm is generic ( C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for MM2S Read Port C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Width of Buffer Length, Transferred Bytes, and BTT fields C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1; -- Depth of DataMover command FIFO C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control and Status -- mm2s_run_stop : in std_logic ; -- mm2s_keyhole : in std_logic ; mm2s_ftch_idle : in std_logic ; -- mm2s_stop : in std_logic ; -- mm2s_cmnd_idle : out std_logic ; -- mm2s_sts_idle : out std_logic ; -- mm2s_desc_flush : out std_logic ; -- -- -- MM2S Descriptor Fetch Request (from mm2s_sm) -- desc_available : in std_logic ; -- desc_fetch_req : out std_logic ; -- desc_fetch_done : in std_logic ; -- desc_update_done : in std_logic ; -- updt_pending : in std_logic ; packet_in_progress : in std_logic ; -- -- -- DataMover Command -- mm2s_cmnd_wr : out std_logic ; -- mm2s_cmnd_data : out std_logic_vector -- ((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); -- mm2s_cmnd_pending : in std_logic ; -- -- -- Descriptor Fields -- mm2s_cache_info : in std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- mm2s_desc_baddress : in std_logic_vector -- (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- mm2s_desc_blength : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- mm2s_desc_blength_v : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- mm2s_desc_blength_s : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- mm2s_desc_eof : in std_logic ; -- mm2s_desc_sof : in std_logic -- ); end axi_dma_mm2s_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_mm2s_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0'); -- DataMover Command Destination Stream Offset constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant MM2S_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH) := (others => '0'); -- Queued commands counter width constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1); -- Queued commands zero count constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- type SG_MM2S_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, -- EXECUTE_XFER, WAIT_STATUS ); signal mm2s_cs : SG_MM2S_STATE_TYPE; signal mm2s_ns : SG_MM2S_STATE_TYPE; -- State Machine Signals signal desc_fetch_req_cmb : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal mm2s_cmnd_wr_i : std_logic := '0'; attribute mark_debug of mm2s_cmnd_wr_i : signal is "true"; signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0'); signal count_incr : std_logic := '0'; signal count_decr : std_logic := '0'; signal mm2s_desc_flush_i : std_logic := '0'; signal queue_more : std_logic := '0'; signal burst_type : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin mm2s_cmnd_wr <= mm2s_cmnd_wr_i; mm2s_desc_flush <= mm2s_desc_flush_i; -- Flush any fetch descriptors if stopped due to errors or soft reset -- or if not in middle of packet and run/stop clears mm2s_desc_flush_i <= '1' when (mm2s_stop = '1') or (packet_in_progress = '0' and mm2s_run_stop = '0') else '0'; burst_type <= '1' and (not mm2s_keyhole); -- A 0 on mm2s_kyhole means increment type burst -- 1 means fixed burst ------------------------------------------------------------------------------- -- MM2S Transfer State Machine ------------------------------------------------------------------------------- MM2S_MACHINE : process(mm2s_cs, mm2s_run_stop, packet_in_progress, desc_available, updt_pending, -- desc_fetch_done, desc_update_done, mm2s_cmnd_pending, mm2s_stop, mm2s_desc_flush_i -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; write_cmnd_cmb <= '0'; mm2s_cmnd_idle <= '0'; mm2s_ns <= mm2s_cs; case mm2s_cs is ------------------------------------------------------------------- when IDLE => -- Running or Stopped but in middle of xfer and Descriptor -- data available, No errors logged, and Room to queue more -- commands, then fetch descriptor -- if (updt_pending = '1') then -- mm2s_ns <= IDLE; if( (mm2s_run_stop = '1' or packet_in_progress = '1') -- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then if (C_SG_INCLUDE_DESC_QUEUE = 0) then -- coverage off mm2s_ns <= WAIT_STATUS; write_cmnd_cmb <= '1'; -- coverage on else mm2s_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; end if; else mm2s_cmnd_idle <= '1'; write_cmnd_cmb <= '0'; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- error detected or run/stop cleared if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then mm2s_ns <= IDLE; -- descriptor fetch complete -- elsif(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; -- mm2s_ns <= EXECUTE_XFER; elsif(mm2s_cmnd_pending = '0')then desc_fetch_req_cmb <= '0'; if (updt_pending = '0') then if(C_SG_INCLUDE_DESC_QUEUE = 1)then mm2s_ns <= IDLE; -- coverage off write_cmnd_cmb <= '1'; -- coverage on else mm2s_ns <= WAIT_STATUS; end if; end if; else mm2s_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '0'; end if; ------------------------------------------------------------------- -- when EXECUTE_XFER => -- -- error detected -- if(mm2s_stop = '1')then -- mm2s_ns <= IDLE; -- -- Write another command if there is not one already pending -- elsif(mm2s_cmnd_pending = '0')then -- if (updt_pending = '0') then -- write_cmnd_cmb <= '1'; -- end if; -- if(C_SG_INCLUDE_DESC_QUEUE = 1)then -- mm2s_ns <= IDLE; -- else -- mm2s_ns <= WAIT_STATUS; -- end if; -- else -- mm2s_ns <= EXECUTE_XFER; -- end if; -- ------------------------------------------------------------------- -- coverage off when WAIT_STATUS => -- wait until desc update complete or error occurs if(desc_update_done = '1' or mm2s_stop = '1')then mm2s_ns <= IDLE; else mm2s_ns <= WAIT_STATUS; end if; -- coverage on ------------------------------------------------------------------- -- coverage off when others => mm2s_ns <= IDLE; -- coverage on end case; end process MM2S_MACHINE; ------------------------------------------------------------------------------- -- register state machine states ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_cs <= IDLE; else mm2s_cs <= mm2s_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- register state machine signals ------------------------------------------------------------------------------- --SM_SIG_REGISTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- desc_fetch_req <= '0' ; -- else -- if (C_SG_INCLUDE_DESC_QUEUE = 0) then -- desc_fetch_req <= '1'; --desc_fetch_req_cmb ; -- else -- desc_fetch_req <= desc_fetch_req_cmb ; -- end if; -- end if; -- end if; -- end process SM_SIG_REGISTER; desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else desc_fetch_req_cmb ; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to mm2s_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_cmnd_wr_i <= '0'; -- mm2s_cmnd_data <= (others => '0'); -- Fetch SM issued a command write -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in mm2s_sg_if. elsif(write_cmnd_cmb = '1')then mm2s_cmnd_wr_i <= '1'; -- mm2s_cmnd_data <= mm2s_cache_info -- & mm2s_desc_blength_v -- & mm2s_desc_blength_s -- & MM2S_CMD_RSVD -- -- Command Tag -- & '0' -- & '0' -- & mm2s_desc_eof -- Cat. EOF to CMD Tag -- & mm2s_desc_eof -- Cat. IOC to CMD Tag -- -- Command -- & mm2s_desc_baddress -- & mm2s_desc_sof -- & mm2s_desc_eof -- & MM2S_CMD_DSA -- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697 -- & PAD_VALUE -- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); else mm2s_cmnd_wr_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; mm2s_cmnd_data <= mm2s_cache_info & mm2s_desc_blength_v & mm2s_desc_blength_s & MM2S_CMD_RSVD -- Command Tag & '0' & '0' & mm2s_desc_eof -- Cat. EOF to CMD Tag & mm2s_desc_eof -- Cat. IOC to CMD Tag -- Command & mm2s_desc_baddress & mm2s_desc_sof & mm2s_desc_eof & MM2S_CMD_DSA & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697 & PAD_VALUE & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to mm2s_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_cmnd_wr_i <= '0'; -- mm2s_cmnd_data <= (others => '0'); -- Fetch SM issued a command write -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in mm2s_sg_if. elsif(write_cmnd_cmb = '1')then mm2s_cmnd_wr_i <= '1'; -- mm2s_cmnd_data <= mm2s_cache_info -- & mm2s_desc_blength_v -- & mm2s_desc_blength_s -- & MM2S_CMD_RSVD -- -- Command Tag -- & '0' -- & '0' -- & mm2s_desc_eof -- Cat. EOF to CMD Tag -- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF) -- -- Command -- & mm2s_desc_baddress -- & mm2s_desc_sof -- & mm2s_desc_eof -- & MM2S_CMD_DSA -- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697 -- & mm2s_desc_blength; else mm2s_cmnd_wr_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; mm2s_cmnd_data <= mm2s_cache_info & mm2s_desc_blength_v & mm2s_desc_blength_s & MM2S_CMD_RSVD -- Command Tag & '0' & '0' & mm2s_desc_eof -- Cat. EOF to CMD Tag & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF) -- Command & mm2s_desc_baddress & mm2s_desc_sof & mm2s_desc_eof & MM2S_CMD_DSA & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697 & mm2s_desc_blength; end generate GEN_CMD_BTT_EQL_23; ------------------------------------------------------------------------------- -- Counter for keepting track of pending commands/status in primary datamover -- Use this to determine if primary datamover for mm2s is Idle. ------------------------------------------------------------------------------- -- increment with each command written count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0' else '0'; -- decrement with each status received count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1' else '0'; -- count number of queued commands to keep track of what datamover is still -- working on --CMD2STS_COUNTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then -- cmnds_queued <= (others => '0'); -- elsif(count_incr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1); -- elsif(count_decr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1); -- end if; -- end if; -- end process CMD2STS_COUNTER; QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then cmnds_queued_shift <= (others => '0'); elsif(count_incr = '1')then cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1'; elsif(count_decr = '1')then cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1); end if; end if; end process CMD2STS_COUNTER1; end generate QUEUE_COUNT; NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin -- coverage off CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then cmnds_queued_shift(0) <= '0'; elsif(count_incr = '1')then cmnds_queued_shift (0) <= '1'; elsif(count_decr = '1')then cmnds_queued_shift (0) <= '0'; end if; end if; end process CMD2STS_COUNTER1; end generate NOQUEUE_COUNT; -- coverage on -- Indicate status is idle when no cmnd/sts queued --mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000" -- else '0'; mm2s_sts_idle <= not cmnds_queued_shift (0); ------------------------------------------------------------------------------- -- Queue only the amount of commands that can be queued on descriptor update -- else lock up can occur. Note datamover command fifo depth is set to number -- of descriptors to queue. ------------------------------------------------------------------------------- --QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; -- else -- queue_more <= '0'; -- end if; -- end if; -- end process QUEUE_MORE_PROCESS; QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then queue_more <= '0'; -- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; else queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1)); end if; end if; end process QUEUE_MORE_PROCESS; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_rdmux.vhd	13	69082	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_rdmux.vhd -- -- Description: -- This file implements the DataMover Master Read Data Multiplexer. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_sg_rdmux is generic ( C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the select control bus C_MMAP_DWIDTH : Integer range 32 to 1024 := 32; -- Indicates the width of the AXI4 Data Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32 -- Indicates the width of the AXI Stream Data Channel ); port ( -- AXI MMap Data Channel Input ----------------------------------------------- -- mmap_read_data_in : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); -- -- AXI Read data input -- ------------------------------------------------------------------------------- -- AXI Master Stream --------------------------------------------------------- -- mux_data_out : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- --Mux data output -- ------------------------------------------------------------------------------- -- Command Calculator Interface ----------------------------------------------- -- mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap Data -- -- Width). -- ------------------------------------------------------------------------------- ); end entity axi_sg_rdmux; architecture implementation of axi_sg_rdmux is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Decalarations ------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_mux_sel_width -- -- Function Description: -- Calculates the number of needed bits for the Mux Select control -- based on the number of input channels to the mux. -- -- Note that the number of input mux channels are always a -- power of 2. -- ------------------------------------------------------------------- function func_mux_sel_width (num_channels : integer) return integer is Variable var_sel_width : integer := 0; begin case num_channels is when 2 => var_sel_width := 1; when 4 => var_sel_width := 2; when 8 => var_sel_width := 3; when 16 => var_sel_width := 4; when 32 => var_sel_width := 5; when 64 => var_sel_width := 6; when 128 => var_sel_width := 7; when others => var_sel_width := 0; end case; Return (var_sel_width); end function func_mux_sel_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_sel_ls_index -- -- Function Description: -- Calculates the LS index of the select field to rip from the -- input select bus. -- -- Note that the number of input mux channels are always a -- power of 2. -- ------------------------------------------------------------------- function func_sel_ls_index (channel_width : integer) return integer is Variable var_sel_ls_index : integer := 0; begin case channel_width is when 8 => var_sel_ls_index := 0; when 16 => var_sel_ls_index := 1; when 32 => var_sel_ls_index := 2; when 64 => var_sel_ls_index := 3; when 128 => var_sel_ls_index := 4; when 256 => var_sel_ls_index := 5; when 512 => var_sel_ls_index := 6; when others => -- 1024-bit channel case var_sel_ls_index := 7; end case; Return (var_sel_ls_index); end function func_sel_ls_index; -- Constant Decalarations ------------------------------------------------- Constant CHANNEL_DWIDTH : integer := C_STREAM_DWIDTH; Constant NUM_MUX_CHANNELS : integer := C_MMAP_DWIDTH/CHANNEL_DWIDTH; Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS); Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(CHANNEL_DWIDTH); -- Signal Declarations -------------------------------------------- signal sig_rdmux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin --(architecture implementation) -- Assign the Output data port mux_data_out <= sig_rdmux_dout; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_STRM_EQ_MMAP -- -- If Generate Description: -- This IfGen implements the case where the Stream Data Width is -- the same as the Memory Map read Data width. -- -- ------------------------------------------------------------ GEN_STRM_EQ_MMAP : if (NUM_MUX_CHANNELS = 1) generate begin sig_rdmux_dout <= mmap_read_data_in; end generate GEN_STRM_EQ_MMAP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_2XN -- -- If Generate Description: -- 2 channel input mux case -- -- ------------------------------------------------------------ GEN_2XN : if (NUM_MUX_CHANNELS = 2) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_2XN_NUX -- -- Process Description: -- Implement the 2XN Mux -- ------------------------------------------------------------- DO_2XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when others => -- 1 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH2)-1 downto CHANNEL_DWIDTH1); end case; end process DO_2XN_NUX; end generate GEN_2XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_4XN -- -- If Generate Description: -- 4 channel input mux case -- -- ------------------------------------------------------------ GEN_4XN : if (NUM_MUX_CHANNELS = 4) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_4XN_NUX -- -- Process Description: -- Implement the 4XN Mux -- ------------------------------------------------------------- DO_4XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH2)-1 downto CHANNEL_DWIDTH1); when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH3)-1 downto CHANNEL_DWIDTH2); when others => -- 3 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH4)-1 downto CHANNEL_DWIDTH3); end case; end process DO_4XN_NUX; end generate GEN_4XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_8XN -- -- If Generate Description: -- 8 channel input mux case -- -- ------------------------------------------------------------ GEN_8XN : if (NUM_MUX_CHANNELS = 8) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_8XN_NUX -- -- Process Description: -- Implement the 8XN Mux -- ------------------------------------------------------------- DO_8XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH2)-1 downto CHANNEL_DWIDTH1); when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH3)-1 downto CHANNEL_DWIDTH2); when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH4)-1 downto CHANNEL_DWIDTH3); when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH5)-1 downto CHANNEL_DWIDTH4); when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH6)-1 downto CHANNEL_DWIDTH5); when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH7)-1 downto CHANNEL_DWIDTH6); when others => -- 7 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH8)-1 downto CHANNEL_DWIDTH7); end case; end process DO_8XN_NUX; end generate GEN_8XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_16XN -- -- If Generate Description: -- 16 channel input mux case -- -- ------------------------------------------------------------ GEN_16XN : if (NUM_MUX_CHANNELS = 16) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_16XN_NUX -- -- Process Description: -- Implement the 16XN Mux -- ------------------------------------------------------------- DO_16XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH2)-1 downto CHANNEL_DWIDTH1); when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH3)-1 downto CHANNEL_DWIDTH2); when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH4)-1 downto CHANNEL_DWIDTH3); when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH5)-1 downto CHANNEL_DWIDTH4); when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH6)-1 downto CHANNEL_DWIDTH5); when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH7)-1 downto CHANNEL_DWIDTH6); when 7 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH8)-1 downto CHANNEL_DWIDTH7); when 8 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH9)-1 downto CHANNEL_DWIDTH8); when 9 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH10)-1 downto CHANNEL_DWIDTH9); when 10 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH11)-1 downto CHANNEL_DWIDTH10); when 11 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH12)-1 downto CHANNEL_DWIDTH11); when 12 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH13)-1 downto CHANNEL_DWIDTH12); when 13 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH14)-1 downto CHANNEL_DWIDTH13); when 14 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH15)-1 downto CHANNEL_DWIDTH14); when others => -- 15 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH16)-1 downto CHANNEL_DWIDTH15); end case; end process DO_16XN_NUX; end generate GEN_16XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_32XN -- -- If Generate Description: -- 32 channel input mux case -- -- ------------------------------------------------------------ GEN_32XN : if (NUM_MUX_CHANNELS = 32) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_32XN_NUX -- -- Process Description: -- Implement the 32XN Mux -- ------------------------------------------------------------- DO_32XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH2)-1 downto CHANNEL_DWIDTH1); when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH3)-1 downto CHANNEL_DWIDTH2); when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH4)-1 downto CHANNEL_DWIDTH3); when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH5)-1 downto CHANNEL_DWIDTH4); when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH6)-1 downto CHANNEL_DWIDTH5); when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH7)-1 downto CHANNEL_DWIDTH6); when 7 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH8)-1 downto CHANNEL_DWIDTH7); when 8 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH9)-1 downto CHANNEL_DWIDTH8); when 9 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH10)-1 downto CHANNEL_DWIDTH9); when 10 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH11)-1 downto CHANNEL_DWIDTH10); when 11 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH12)-1 downto CHANNEL_DWIDTH11); when 12 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH13)-1 downto CHANNEL_DWIDTH12); when 13 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH14)-1 downto CHANNEL_DWIDTH13); when 14 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH15)-1 downto CHANNEL_DWIDTH14); when 15 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH16)-1 downto CHANNEL_DWIDTH15); when 16 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH17)-1 downto CHANNEL_DWIDTH16); when 17 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH18)-1 downto CHANNEL_DWIDTH17); when 18 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH19)-1 downto CHANNEL_DWIDTH18); when 19 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH20)-1 downto CHANNEL_DWIDTH19); when 20 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH21)-1 downto CHANNEL_DWIDTH20); when 21 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH22)-1 downto CHANNEL_DWIDTH21); when 22 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH23)-1 downto CHANNEL_DWIDTH22); when 23 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH24)-1 downto CHANNEL_DWIDTH23); when 24 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH25)-1 downto CHANNEL_DWIDTH24); when 25 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH26)-1 downto CHANNEL_DWIDTH25); when 26 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH27)-1 downto CHANNEL_DWIDTH26); when 27 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH28)-1 downto CHANNEL_DWIDTH27); when 28 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH29)-1 downto CHANNEL_DWIDTH28); when 29 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH30)-1 downto CHANNEL_DWIDTH29); when 30 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH31)-1 downto CHANNEL_DWIDTH30); when others => -- 31 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH32)-1 downto CHANNEL_DWIDTH31); end case; end process DO_32XN_NUX; end generate GEN_32XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_64XN -- -- If Generate Description: -- 64 channel input mux case -- -- ------------------------------------------------------------ GEN_64XN : if (NUM_MUX_CHANNELS = 64) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_64XN_NUX -- -- Process Description: -- Implement the 64XN Mux -- ------------------------------------------------------------- DO_64XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ; when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH2)-1 downto CHANNEL_DWIDTH1) ; when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH3)-1 downto CHANNEL_DWIDTH2) ; when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH4)-1 downto CHANNEL_DWIDTH3) ; when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH5)-1 downto CHANNEL_DWIDTH4) ; when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH6)-1 downto CHANNEL_DWIDTH5) ; when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH7)-1 downto CHANNEL_DWIDTH6) ; when 7 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH8)-1 downto CHANNEL_DWIDTH7) ; when 8 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH9)-1 downto CHANNEL_DWIDTH8) ; when 9 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH10)-1 downto CHANNEL_DWIDTH9) ; when 10 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH11)-1 downto CHANNEL_DWIDTH10); when 11 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH12)-1 downto CHANNEL_DWIDTH11); when 12 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH13)-1 downto CHANNEL_DWIDTH12); when 13 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH14)-1 downto CHANNEL_DWIDTH13); when 14 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH15)-1 downto CHANNEL_DWIDTH14); when 15 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH16)-1 downto CHANNEL_DWIDTH15); when 16 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH17)-1 downto CHANNEL_DWIDTH16); when 17 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH18)-1 downto CHANNEL_DWIDTH17); when 18 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH19)-1 downto CHANNEL_DWIDTH18); when 19 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH20)-1 downto CHANNEL_DWIDTH19); when 20 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH21)-1 downto CHANNEL_DWIDTH20); when 21 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH22)-1 downto CHANNEL_DWIDTH21); when 22 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH23)-1 downto CHANNEL_DWIDTH22); when 23 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH24)-1 downto CHANNEL_DWIDTH23); when 24 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH25)-1 downto CHANNEL_DWIDTH24); when 25 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH26)-1 downto CHANNEL_DWIDTH25); when 26 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH27)-1 downto CHANNEL_DWIDTH26); when 27 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH28)-1 downto CHANNEL_DWIDTH27); when 28 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH29)-1 downto CHANNEL_DWIDTH28); when 29 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH30)-1 downto CHANNEL_DWIDTH29); when 30 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH31)-1 downto CHANNEL_DWIDTH30); when 31 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH32)-1 downto CHANNEL_DWIDTH31); when 32 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH33)-1 downto CHANNEL_DWIDTH32); when 33 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH34)-1 downto CHANNEL_DWIDTH33); when 34 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH35)-1 downto CHANNEL_DWIDTH34); when 35 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH36)-1 downto CHANNEL_DWIDTH35); when 36 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH37)-1 downto CHANNEL_DWIDTH36); when 37 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH38)-1 downto CHANNEL_DWIDTH37); when 38 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH39)-1 downto CHANNEL_DWIDTH38); when 39 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH40)-1 downto CHANNEL_DWIDTH39); when 40 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH41)-1 downto CHANNEL_DWIDTH40); when 41 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH42)-1 downto CHANNEL_DWIDTH41); when 42 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH43)-1 downto CHANNEL_DWIDTH42); when 43 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH44)-1 downto CHANNEL_DWIDTH43); when 44 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH45)-1 downto CHANNEL_DWIDTH44); when 45 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH46)-1 downto CHANNEL_DWIDTH45); when 46 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH47)-1 downto CHANNEL_DWIDTH46); when 47 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH48)-1 downto CHANNEL_DWIDTH47); when 48 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH49)-1 downto CHANNEL_DWIDTH48); when 49 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH50)-1 downto CHANNEL_DWIDTH49); when 50 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH51)-1 downto CHANNEL_DWIDTH50); when 51 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH52)-1 downto CHANNEL_DWIDTH51); when 52 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH53)-1 downto CHANNEL_DWIDTH52); when 53 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH54)-1 downto CHANNEL_DWIDTH53); when 54 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH55)-1 downto CHANNEL_DWIDTH54); when 55 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH56)-1 downto CHANNEL_DWIDTH55); when 56 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH57)-1 downto CHANNEL_DWIDTH56); when 57 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH58)-1 downto CHANNEL_DWIDTH57); when 58 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH59)-1 downto CHANNEL_DWIDTH58); when 59 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH60)-1 downto CHANNEL_DWIDTH59); when 60 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH61)-1 downto CHANNEL_DWIDTH60); when 61 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH62)-1 downto CHANNEL_DWIDTH61); when 62 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH63)-1 downto CHANNEL_DWIDTH62); when others => -- 63 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH64)-1 downto CHANNEL_DWIDTH63); end case; end process DO_64XN_NUX; end generate GEN_64XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_128XN -- -- If Generate Description: -- 128 channel input mux case -- -- ------------------------------------------------------------ GEN_128XN : if (NUM_MUX_CHANNELS = 128) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_128XN_NUX -- -- Process Description: -- Implement the 64XN Mux -- ------------------------------------------------------------- DO_128XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ; when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH2)-1 downto CHANNEL_DWIDTH1) ; when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH3)-1 downto CHANNEL_DWIDTH2) ; when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH4)-1 downto CHANNEL_DWIDTH3) ; when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH5)-1 downto CHANNEL_DWIDTH4) ; when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH6)-1 downto CHANNEL_DWIDTH5) ; when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH7)-1 downto CHANNEL_DWIDTH6) ; when 7 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH8)-1 downto CHANNEL_DWIDTH7) ; when 8 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH9)-1 downto CHANNEL_DWIDTH8) ; when 9 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH10)-1 downto CHANNEL_DWIDTH9) ; when 10 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH11)-1 downto CHANNEL_DWIDTH10); when 11 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH12)-1 downto CHANNEL_DWIDTH11); when 12 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH13)-1 downto CHANNEL_DWIDTH12); when 13 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH14)-1 downto CHANNEL_DWIDTH13); when 14 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH15)-1 downto CHANNEL_DWIDTH14); when 15 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH16)-1 downto CHANNEL_DWIDTH15); when 16 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH17)-1 downto CHANNEL_DWIDTH16); when 17 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH18)-1 downto CHANNEL_DWIDTH17); when 18 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH19)-1 downto CHANNEL_DWIDTH18); when 19 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH20)-1 downto CHANNEL_DWIDTH19); when 20 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH21)-1 downto CHANNEL_DWIDTH20); when 21 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH22)-1 downto CHANNEL_DWIDTH21); when 22 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH23)-1 downto CHANNEL_DWIDTH22); when 23 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH24)-1 downto CHANNEL_DWIDTH23); when 24 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH25)-1 downto CHANNEL_DWIDTH24); when 25 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH26)-1 downto CHANNEL_DWIDTH25); when 26 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH27)-1 downto CHANNEL_DWIDTH26); when 27 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH28)-1 downto CHANNEL_DWIDTH27); when 28 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH29)-1 downto CHANNEL_DWIDTH28); when 29 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH30)-1 downto CHANNEL_DWIDTH29); when 30 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH31)-1 downto CHANNEL_DWIDTH30); when 31 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH32)-1 downto CHANNEL_DWIDTH31); when 32 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH33)-1 downto CHANNEL_DWIDTH32); when 33 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH34)-1 downto CHANNEL_DWIDTH33); when 34 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH35)-1 downto CHANNEL_DWIDTH34); when 35 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH36)-1 downto CHANNEL_DWIDTH35); when 36 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH37)-1 downto CHANNEL_DWIDTH36); when 37 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH38)-1 downto CHANNEL_DWIDTH37); when 38 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH39)-1 downto CHANNEL_DWIDTH38); when 39 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH40)-1 downto CHANNEL_DWIDTH39); when 40 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH41)-1 downto CHANNEL_DWIDTH40); when 41 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH42)-1 downto CHANNEL_DWIDTH41); when 42 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH43)-1 downto CHANNEL_DWIDTH42); when 43 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH44)-1 downto CHANNEL_DWIDTH43); when 44 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH45)-1 downto CHANNEL_DWIDTH44); when 45 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH46)-1 downto CHANNEL_DWIDTH45); when 46 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH47)-1 downto CHANNEL_DWIDTH46); when 47 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH48)-1 downto CHANNEL_DWIDTH47); when 48 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH49)-1 downto CHANNEL_DWIDTH48); when 49 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH50)-1 downto CHANNEL_DWIDTH49); when 50 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH51)-1 downto CHANNEL_DWIDTH50); when 51 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH52)-1 downto CHANNEL_DWIDTH51); when 52 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH53)-1 downto CHANNEL_DWIDTH52); when 53 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH54)-1 downto CHANNEL_DWIDTH53); when 54 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH55)-1 downto CHANNEL_DWIDTH54); when 55 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH56)-1 downto CHANNEL_DWIDTH55); when 56 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH57)-1 downto CHANNEL_DWIDTH56); when 57 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH58)-1 downto CHANNEL_DWIDTH57); when 58 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH59)-1 downto CHANNEL_DWIDTH58); when 59 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH60)-1 downto CHANNEL_DWIDTH59); when 60 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH61)-1 downto CHANNEL_DWIDTH60); when 61 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH62)-1 downto CHANNEL_DWIDTH61); when 62 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH63)-1 downto CHANNEL_DWIDTH62); when 63 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH64)-1 downto CHANNEL_DWIDTH63); when 64 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH65)-1 downto CHANNEL_DWIDTH64) ; when 65 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH66)-1 downto CHANNEL_DWIDTH65) ; when 66 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH67)-1 downto CHANNEL_DWIDTH66) ; when 67 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH68)-1 downto CHANNEL_DWIDTH67) ; when 68 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH69)-1 downto CHANNEL_DWIDTH68) ; when 69 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH70)-1 downto CHANNEL_DWIDTH69) ; when 70 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH71)-1 downto CHANNEL_DWIDTH70) ; when 71 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH72)-1 downto CHANNEL_DWIDTH71) ; when 72 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH73)-1 downto CHANNEL_DWIDTH72) ; when 73 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH74)-1 downto CHANNEL_DWIDTH73) ; when 74 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH75)-1 downto CHANNEL_DWIDTH74) ; when 75 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH76)-1 downto CHANNEL_DWIDTH75) ; when 76 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH77)-1 downto CHANNEL_DWIDTH76) ; when 77 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH78)-1 downto CHANNEL_DWIDTH77) ; when 78 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH79)-1 downto CHANNEL_DWIDTH78) ; when 79 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH80)-1 downto CHANNEL_DWIDTH79) ; when 80 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH81)-1 downto CHANNEL_DWIDTH80) ; when 81 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH82)-1 downto CHANNEL_DWIDTH81) ; when 82 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH83)-1 downto CHANNEL_DWIDTH82) ; when 83 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH84)-1 downto CHANNEL_DWIDTH83) ; when 84 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH85)-1 downto CHANNEL_DWIDTH84) ; when 85 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH86)-1 downto CHANNEL_DWIDTH85) ; when 86 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH87)-1 downto CHANNEL_DWIDTH86) ; when 87 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH88)-1 downto CHANNEL_DWIDTH87) ; when 88 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH89)-1 downto CHANNEL_DWIDTH88) ; when 89 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH90)-1 downto CHANNEL_DWIDTH89) ; when 90 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH91)-1 downto CHANNEL_DWIDTH90) ; when 91 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH92)-1 downto CHANNEL_DWIDTH91) ; when 92 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH93)-1 downto CHANNEL_DWIDTH92) ; when 93 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH94)-1 downto CHANNEL_DWIDTH93) ; when 94 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH95)-1 downto CHANNEL_DWIDTH94) ; when 95 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH96)-1 downto CHANNEL_DWIDTH95) ; when 96 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH97 )-1 downto CHANNEL_DWIDTH96 ) ; when 97 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH98 )-1 downto CHANNEL_DWIDTH97 ) ; when 98 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH99 )-1 downto CHANNEL_DWIDTH98 ) ; when 99 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH100)-1 downto CHANNEL_DWIDTH99 ) ; when 100 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH101)-1 downto CHANNEL_DWIDTH100) ; when 101 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH102)-1 downto CHANNEL_DWIDTH101) ; when 102 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH103)-1 downto CHANNEL_DWIDTH102) ; when 103 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH104)-1 downto CHANNEL_DWIDTH103) ; when 104 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH105)-1 downto CHANNEL_DWIDTH104) ; when 105 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH106)-1 downto CHANNEL_DWIDTH105) ; when 106 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH107)-1 downto CHANNEL_DWIDTH106) ; when 107 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH108)-1 downto CHANNEL_DWIDTH107) ; when 108 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH109)-1 downto CHANNEL_DWIDTH108) ; when 109 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH110)-1 downto CHANNEL_DWIDTH109) ; when 110 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH111)-1 downto CHANNEL_DWIDTH110) ; when 111 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH112)-1 downto CHANNEL_DWIDTH111) ; when 112 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH113)-1 downto CHANNEL_DWIDTH112) ; when 113 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH114)-1 downto CHANNEL_DWIDTH113) ; when 114 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH115)-1 downto CHANNEL_DWIDTH114) ; when 115 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH116)-1 downto CHANNEL_DWIDTH115) ; when 116 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH117)-1 downto CHANNEL_DWIDTH116) ; when 117 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH118)-1 downto CHANNEL_DWIDTH117) ; when 118 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH119)-1 downto CHANNEL_DWIDTH118) ; when 119 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH120)-1 downto CHANNEL_DWIDTH119) ; when 120 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH121)-1 downto CHANNEL_DWIDTH120) ; when 121 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH122)-1 downto CHANNEL_DWIDTH121) ; when 122 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH123)-1 downto CHANNEL_DWIDTH122) ; when 123 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH124)-1 downto CHANNEL_DWIDTH123) ; when 124 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH125)-1 downto CHANNEL_DWIDTH124) ; when 125 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH126)-1 downto CHANNEL_DWIDTH125) ; when 126 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH127)-1 downto CHANNEL_DWIDTH126) ; when others => -- 127 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH128)-1 downto CHANNEL_DWIDTH127) ; end case; end process DO_128XN_NUX; end generate GEN_128XN; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/coregen_comp_defs.vhd	4	13824	------------------------------------------------------------------------------- -- coregen_comp_defs - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: coregen_comp_defs.vhd -- Version: initial -- Description: -- Component declarations for all black box netlists generated by -- running COREGEN and AXI BRAM CTRL when XST elaborated the client core -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- coregen_comp_defs.vhd ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; PACKAGE coregen_comp_defs IS ------------------------------------------------------------------------------------- -- Start Block Memory Generator Component for blk_mem_gen_v8_2 -- Component declaration for blk_mem_gen_v8_2 pulled from the blk_mem_gen_v8_2.v -- Verilog file used to match paramter order for NCSIM compatibility ------------------------------------------------------------------------------------- component blk_mem_gen_v8_2 generic ( ---------------------------------------------------------------------------- -- Generic Declarations ---------------------------------------------------------------------------- --Device Family & Elaboration Directory Parameters: C_FAMILY : STRING := "virtex4"; C_XDEVICEFAMILY : STRING := "virtex4"; -- C_ELABORATION_DIR : STRING := ""; C_INTERFACE_TYPE : INTEGER := 0; C_AXI_TYPE : INTEGER := 1; C_AXI_SLAVE_TYPE : INTEGER := 0; C_HAS_AXI_ID : INTEGER := 0; C_AXI_ID_WIDTH : INTEGER := 4; --General Memory Parameters: C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 9; C_ALGORITHM : INTEGER := 0; C_PRIM_TYPE : INTEGER := 3; --Memory Initialization Parameters: C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := "111111111"; C_RST_TYPE : STRING := "SYNC"; --Port A Parameters: --Reset Parameters: C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := "0"; --Enable Parameters: C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; --Byte Write Enable Parameters: C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; --Write Mode: C_WRITE_MODE_A : STRING := "WRITE_FIRST"; --Data-Addr Width Parameters: C_WRITE_WIDTH_A : INTEGER := 4; C_READ_WIDTH_A : INTEGER := 4; C_WRITE_DEPTH_A : INTEGER := 4096; C_READ_DEPTH_A : INTEGER := 4096; C_ADDRA_WIDTH : INTEGER := 12; --Port B Parameters: --Reset Parameters: C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := "0"; --Enable Parameters: C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; --Byte Write Enable Parameters: C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; --Write Mode: C_WRITE_MODE_B : STRING := "WRITE_FIRST"; --Data-Addr Width Parameters: C_WRITE_WIDTH_B : INTEGER := 4; C_READ_WIDTH_B : INTEGER := 4; C_WRITE_DEPTH_B : INTEGER := 4096; C_READ_DEPTH_B : INTEGER := 4096; C_ADDRB_WIDTH : INTEGER := 12; --Output Registers/ Pipelining Parameters: C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; --Input/Output Registers for SoftECC : C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; --ECC Parameters C_USE_ECC : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; --Simulation Model Parameters: C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 0; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( ---------------------------------------------------------------------------- -- Input and Output Declarations ---------------------------------------------------------------------------- -- Native BMG Input and Output Port Declarations --Port A: CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '0'; REGCEA : IN STD_LOGIC := '0'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); --Port B: CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '0'; REGCEB : IN STD_LOGIC := '0'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); --ECC: INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); -- AXI BMG Input and Output Port Declarations -- AXI Global Signals S_AClk : IN STD_LOGIC := '0'; S_ARESETN : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Write (write side) S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN STD_LOGIC := '0'; S_AXI_AWREADY : OUT STD_LOGIC; S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WLAST : IN STD_LOGIC := '0'; S_AXI_WVALID : IN STD_LOGIC := '0'; S_AXI_WREADY : OUT STD_LOGIC; S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Read (Write side) S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN STD_LOGIC := '0'; S_AXI_ARREADY : OUT STD_LOGIC; S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); S_AXI_RLAST : OUT STD_LOGIC; S_AXI_RVALID : OUT STD_LOGIC; S_AXI_RREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Sideband Signals S_AXI_INJECTSBITERR : IN STD_LOGIC := '0'; S_AXI_INJECTDBITERR : IN STD_LOGIC := '0'; S_AXI_SBITERR : OUT STD_LOGIC; S_AXI_DBITERR : OUT STD_LOGIC; S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END COMPONENT; --blk_mem_gen_v8_2 END coregen_comp_defs;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_reset.vhd	12	23104	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_reset.vhd -- -- Description: -- This file implements the DataMover Reset module. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_sg_reset is generic ( C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0 -- 0 = Use Synchronous Command/Statys User Interface -- 1 = Use Asynchronous Command/Statys User Interface ); port ( -- Primary Clock and Reset Inputs ----------------- -- primary_aclk : in std_logic; -- primary_aresetn : in std_logic; -- --------------------------------------------------- -- Async operation clock and reset from User ------ -- Used for Command/Status User interface -- -- synchronization when C_STSCMD_IS_ASYNC = 1 -- -- secondary_awclk : in std_logic; -- secondary_aresetn : in std_logic; -- --------------------------------------------------- -- Halt request input control ------------------------------- halt_req : in std_logic; -- -- Active high soft shutdown request (can be a pulse) -- -- -- Halt Complete status flag -- halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Soft Shutdown internal interface ------------------------------------------------ -- flush_stop_request : Out std_logic; -- -- Active high soft stop request to modules -- -- data_cntlr_stopped : in std_logic; -- -- Active high flag indicating the data controller is flushed and stopped -- -- addr_cntlr_stopped : in std_logic; -- -- Active high flag indicating the address controller is flushed and stopped -- -- aux1_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 1 module -- -- Tie high if unused -- -- aux2_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 2 module -- -- Tie high if unused -- ------------------------------------------------------------------------------------ -- HW Reset outputs to reset groups ------------------------------------- -- cmd_stat_rst_user : Out std_logic; -- -- The reset to the Command/Status Module User interface side -- -- cmd_stat_rst_int : Out std_logic; -- -- The reset to the Command/Status Module internal interface side -- -- mmap_rst : Out std_logic; -- -- The reset to the Memory Map interface side -- -- stream_rst : Out std_logic -- -- The reset to the Stream interface side -- -------------------------------------------------------------------------- ); end entity axi_sg_reset; architecture implementation of axi_sg_reset is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Signals signal sig_cmd_stat_rst_user_n : std_logic := '0'; signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0'; signal sig_cmd_stat_rst_int_reg_n : std_logic := '0'; signal sig_mmap_rst_reg_n : std_logic := '0'; signal sig_stream_rst_reg_n : std_logic := '0'; signal sig_syncd_sec_rst : std_logic := '0'; -- soft shutdown support signal sig_internal_reset : std_logic := '0'; signal sig_s_h_halt_reg : std_logic := '0'; signal sig_halt_cmplt : std_logic := '0'; -- additional CDC synchronization signals signal sig_sec_neg_edge_plus_delay : std_logic := '0'; signal sig_secondary_aresetn_reg : std_logic := '0'; signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0'; signal sig_prim2sec_rst_reg2_n : std_logic := '0'; begin --(architecture implementation) -- Assign outputs cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n); cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; mmap_rst <= not(sig_mmap_rst_reg_n) or sig_syncd_sec_rst; stream_rst <= not(sig_stream_rst_reg_n) or sig_syncd_sec_rst; -- Internal logic Implmentation ------------------------------------------------------------ -- If Generate -- -- Label: GEN_SYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Synchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate begin sig_syncd_sec_rst <= '0'; sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from); end generate GEN_SYNC_CMDSTAT_RESET; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ASYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Asynchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate signal sig_sec_reset_in_reg_n : std_logic := '0'; -- Secondary reset pulse stretcher signal sig_secondary_dly1 : std_logic := '0'; signal sig_secondary_dly2 : std_logic := '0'; signal sig_neg_edge_detect : std_logic := '0'; signal sig_sec2prim_reset : std_logic := '0'; signal sig_sec2prim_reset_reg : std_logic := '0'; signal sig_sec2prim_reset_reg2 : std_logic := '0'; signal sig_sec2prim_rst_syncro1 : std_logic := '0'; signal sig_sec2prim_rst_syncro2 : std_logic := '0'; begin -- Generate the reset in the primary clock domain. Use the longer -- of the pulse stretched reset or the actual reset. sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or sig_sec2prim_rst_syncro2; -- Check for falling edge of secondary_aresetn input sig_neg_edge_detect <= '1' when (sig_sec_reset_in_reg_n = '1' and secondary_aresetn = '0') else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSE_STRETCH_FLOPS -- -- Process Description: -- This process implements a 3 clock wide pulse whenever the -- secondary reset is asserted -- ------------------------------------------------------------- IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then If (sig_secondary_dly2 = '1') Then sig_secondary_dly1 <= '0' ; sig_secondary_dly2 <= '0' ; Elsif (sig_neg_edge_detect = '1') Then sig_secondary_dly1 <= '1'; else sig_secondary_dly2 <= sig_secondary_dly1 ; End if; end if; end process IMP_PUSE_STRETCH_FLOPS; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_NEG_EDGE -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- negative edge detection, -- ------------------------------------------------------------- SYNC_NEG_EDGE : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or sig_secondary_dly1 or sig_secondary_dly2; end if; end process SYNC_NEG_EDGE; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO -- -- Process Description: -- This process registers the secondary reset input to -- the primary clock domain. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_sec2prim_reset_reg <= sig_sec_neg_edge_plus_delay ; sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg; end if; end process SEC2PRIM_RST_SYNCRO; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SEC_RST -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- secondary reset input, -- ------------------------------------------------------------- REG_SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_secondary_aresetn_reg <= secondary_aresetn; end if; end process REG_SEC_RST; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO_2 -- -- Process Description: -- Second stage (destination) synchronizers for the secondary -- reset CDC to the primary clock. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then -- CDC sig_sec2prim_rst_syncro1 <= not(secondary_aresetn); sig_sec2prim_rst_syncro1 <= not(sig_secondary_aresetn_reg); sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1; end if; end process SEC2PRIM_RST_SYNCRO_2; -- Generate the Command and Status side reset sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and sig_prim2sec_rst_reg2_n; -- CDC sig_cmd_stat_rst_user_reg_n_cdc_from; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_RESET_ASYNC -- -- Process Description: -- This process registers the secondary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_RESET_ASYNC : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_reset_in_reg_n <= secondary_aresetn; end if; end process REG_RESET_ASYNC; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_PRIM2SEC_RST -- -- Process Description: -- Second (destination clock) stage synchronizers for CDC of -- primary reset input, -- ------------------------------------------------------------- SYNC_PRIM2SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from; sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to; end if; end process SYNC_PRIM2SEC_RST; -- end generate GEN_ASYNC_CMDSTAT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_PRIM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_PRIM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn; end if; end process REG_CMDSTAT_PRIM_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_INT_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status internal interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_INT_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_int_reg_n <= primary_aresetn; end if; end process REG_CMDSTAT_INT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_MMAP_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Memory Map interface reset. -- ------------------------------------------------------------- REG_MMAP_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_rst_reg_n <= primary_aresetn; end if; end process REG_MMAP_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_STREAM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Stream interface reset. -- ------------------------------------------------------------- REG_STREAM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_stream_rst_reg_n <= primary_aresetn; end if; end process REG_STREAM_RESET; -- Soft Shutdown logic ------------------------------------------------------ sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; flush_stop_request <= sig_s_h_halt_reg; halt_cmplt <= sig_halt_cmplt; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_HALT_REQ -- -- Process Description: -- Implements a sample and hold flop for the halt request -- input. Can only be cleared on a HW reset. -- ------------------------------------------------------------- REG_HALT_REQ : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_s_h_halt_reg <= '0'; elsif (halt_req = '1') then sig_s_h_halt_reg <= '1'; else null; -- hold current state end if; end if; end process REG_HALT_REQ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_CMPLT -- -- Process Description: -- Implements a the flop for the halt complete status -- output. Can only be cleared on a HW reset. -- ------------------------------------------------------------- IMP_HALT_CMPLT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_halt_cmplt <= '0'; elsif (data_cntlr_stopped = '1' and addr_cntlr_stopped = '1' and aux1_stopped = '1' and aux2_stopped = '1') then sig_halt_cmplt <= '1'; else null; -- hold current state end if; end if; end process IMP_HALT_CMPLT; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_mssai_skid_buf.vhd	6	24680	------------------------------------------------------------------------------- -- axi_datamover_mssai_skid_buf.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mssai_skid_buf.vhd -- -- Description: -- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode that -- also incorporates the MS Strobe Asserted detection function needed by the -- module. This provides a register isolation of the MS asserted strobe index -- Scatter needed to improve Fmax. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; Use axi_datamover_v5_1.axi_datamover_ms_strb_set; ------------------------------------------------------------------------------- entity axi_datamover_mssai_skid_buf is generic ( C_WDATA_WIDTH : INTEGER range 8 to 1024 := 32 ; -- Width of the Stream Data bus (in bits) C_INDEX_WIDTH : Integer range 1 to 8 := 2 -- Sets the width of the MS asserted strobe index output value ); port ( -- Clock and Reset Ports ----------------------- aclk : In std_logic ; -- arst : In std_logic ; -- ------------------------------------------------ -- Shutdown control (assert for 1 clk pulse) --- skid_stop : In std_logic ; -- ------------------------------------------------ -- Slave Side (Stream Data Input) ------------------------------------ s_valid : In std_logic ; -- s_ready : Out std_logic ; -- s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- s_last : In std_logic ; -- ---------------------------------------------------------------------- -- Master Side (Stream Data Output ----------------------------------- m_valid : Out std_logic ; -- m_ready : In std_logic ; -- m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- m_last : Out std_logic ; -- -- m_mssa_index : Out std_logic_vector(C_INDEX_WIDTH-1 downto 0); -- m_strb_error : Out std_logic -- ---------------------------------------------------------------------- ); end entity axi_datamover_mssai_skid_buf; architecture implementation of axi_datamover_mssai_skid_buf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Constant declarations ------------------------- Constant STROBE_WIDTH : integer := C_WDATA_WIDTH/8; -- Signals declarations ------------------------- Signal sig_reset_reg : std_logic := '0'; signal sig_spcl_s_ready_set : std_logic := '0'; signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_reg : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_skid_reg : std_logic := '0'; signal sig_skid_reg_en : std_logic := '0'; signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_mux_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_skid_mux_out : std_logic := '0'; signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_reg_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_reg_out : std_logic := '0'; signal sig_data_reg_out_en : std_logic := '0'; signal sig_m_valid_out : std_logic := '0'; signal sig_m_valid_dup : std_logic := '0'; signal sig_m_valid_comb : std_logic := '0'; signal sig_s_ready_out : std_logic := '0'; signal sig_s_ready_comb : std_logic := '0'; signal sig_stop_request : std_logic := '0'; signal sig_stopped : std_logic := '0'; signal sig_sready_stop : std_logic := '0'; signal sig_sready_early_stop : std_logic := '0'; signal sig_sready_stop_set : std_logic := '0'; signal sig_sready_stop_reg : std_logic := '0'; signal sig_mvalid_stop_reg : std_logic := '0'; signal sig_mvalid_stop : std_logic := '0'; signal sig_mvalid_early_stop : std_logic := '0'; signal sig_mvalid_stop_set : std_logic := '0'; signal sig_slast_with_stop : std_logic := '0'; signal sig_sstrb_stop_mask : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_sstrb_with_stop : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_mssa_index_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_mssa_index_reg_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_error : std_logic := '0'; signal sig_strb_error_reg_out : std_logic := '0'; -- Fmax improvements signal sig_s_ready_dup : std_logic := '0'; signal sig_s_ready_dup2 : std_logic := '0'; signal sig_s_ready_dup3 : std_logic := '0'; signal sig_s_ready_dup4 : std_logic := '0'; signal sig_skid_mux_sel : std_logic := '0'; signal sig_skid_mux_sel2 : std_logic := '0'; signal sig_skid_mux_sel3 : std_logic := '0'; signal sig_skid_mux_sel4 : std_logic := '0'; -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup2 : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup3 : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup4 : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup2 : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup3 : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup4 : signal is "no"; begin --(architecture implementation) m_valid <= sig_m_valid_out; s_ready <= sig_s_ready_out; m_strb <= sig_strb_reg_out; m_last <= sig_last_reg_out; m_data <= sig_data_reg_out; m_mssa_index <= sig_mssa_index_reg_out; m_strb_error <= sig_strb_error_reg_out; -- Special shutdown logic version of Slast. -- A halt request forces a tlast through the skig buffer sig_slast_with_stop <= s_last or sig_stop_request; sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask; -- Assign the special s_ready FLOP set signal sig_spcl_s_ready_set <= sig_reset_reg; -- Generate the ouput register load enable control sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup); -- Generate the skid input register load enable control sig_skid_reg_en <= sig_s_ready_dup; -- Generate the skid mux select control sig_skid_mux_sel2 <= not(sig_s_ready_dup2); sig_skid_mux_sel3 <= not(sig_s_ready_dup3); sig_skid_mux_sel4 <= not(sig_s_ready_dup4); -- Skid Mux sig_data_skid_mux_out <= sig_data_skid_reg When (sig_skid_mux_sel2 = '1') Else s_data; sig_strb_skid_mux_out <= sig_strb_skid_reg When (sig_skid_mux_sel3 = '1') Else sig_sstrb_with_stop; sig_last_skid_mux_out <= sig_last_skid_reg When (sig_skid_mux_sel4 = '1') Else sig_slast_with_stop; -- m_valid combinational logic sig_m_valid_comb <= s_valid or (sig_m_valid_dup and (not(sig_s_ready_dup) or not(m_ready))); -- s_ready combinational logic sig_s_ready_comb <= m_ready or (sig_s_ready_dup and (not(sig_m_valid_dup) or not(s_valid))); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_THE_RST -- -- Process Description: -- Register input reset -- ------------------------------------------------------------- REG_THE_RST : process (aclk) begin if (aclk'event and aclk = '1') then sig_reset_reg <= arst; end if; end process REG_THE_RST; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_READY_FLOP -- -- Process Description: -- Registers s_ready handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- S_READY_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_sready_stop = '1' or sig_sready_early_stop = '1') then -- Special stop condition sig_s_ready_out <= '0'; sig_s_ready_dup <= '0'; sig_s_ready_dup2 <= '0'; sig_s_ready_dup3 <= '0'; sig_s_ready_dup4 <= '0'; Elsif (sig_spcl_s_ready_set = '1') Then sig_s_ready_out <= '1'; sig_s_ready_dup <= '1'; sig_s_ready_dup2 <= '1'; sig_s_ready_dup3 <= '1'; sig_s_ready_dup4 <= '1'; else sig_s_ready_out <= sig_s_ready_comb; sig_s_ready_dup <= sig_s_ready_comb; sig_s_ready_dup2 <= sig_s_ready_comb; sig_s_ready_dup3 <= sig_s_ready_comb; sig_s_ready_dup4 <= sig_s_ready_comb; end if; end if; end process S_READY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: M_VALID_FLOP -- -- Process Description: -- Registers m_valid handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- M_VALID_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA sig_mvalid_stop = '1' or sig_mvalid_stop_set = '1') then -- Special stop condition sig_m_valid_out <= '0'; sig_m_valid_dup <= '0'; else sig_m_valid_out <= sig_m_valid_comb; sig_m_valid_dup <= sig_m_valid_comb; end if; end if; end process M_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_DATA_REG -- -- Process Description: -- This process implements the skid register for the -- Skid Buffer Data signals. Note that reset has been removed -- to reduce route of resets for very wide data buses. -- ------------------------------------------------------------- SKID_DATA_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (sig_skid_reg_en = '1') then sig_data_skid_reg <= s_data; else null; -- hold current state end if; end if; end process SKID_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_CNTL_REG -- -- Process Description: -- This process implements the skid registers for the -- Skid Buffer control signals -- ------------------------------------------------------------- SKID_CNTL_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_strb_skid_reg <= (others => '0'); sig_last_skid_reg <= '0'; elsif (sig_skid_reg_en = '1') then sig_strb_skid_reg <= sig_sstrb_with_stop; sig_last_skid_reg <= sig_slast_with_stop; else null; -- hold current state end if; end if; end process SKID_CNTL_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_DATA_REG -- -- Process Description: -- This process implements the output register for the -- Skid Buffer Data signals. Note that reset has been removed -- to reduce route of resets for very wide data buses. -- ------------------------------------------------------------- OUTPUT_DATA_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (sig_data_reg_out_en = '1') then sig_data_reg_out <= sig_data_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_CNTL_REG -- -- Process Description: -- This process implements the output registers for the -- Skid Buffer Control signals. -- ------------------------------------------------------------- OUTPUT_CNTL_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_mvalid_stop_reg = '1') then sig_strb_reg_out <= (others => '0'); sig_last_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_strb_reg_out <= sig_strb_skid_mux_out; sig_last_reg_out <= sig_last_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_CNTL_REG; -------- Special Stop Logic -------------------------------------- sig_sready_stop <= sig_sready_stop_reg; sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately sig_sready_stop_set <= sig_sready_early_stop; sig_mvalid_stop <= sig_mvalid_stop_reg; sig_mvalid_early_stop <= sig_m_valid_dup and m_ready and skid_stop; sig_mvalid_stop_set <= sig_mvalid_early_stop or (sig_stop_request and not(sig_m_valid_dup)) or (sig_m_valid_dup and m_ready and sig_stop_request); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STOP_REQ_FLOP -- -- Process Description: -- This process implements the Stop request flop. It is a -- sample and hold register that can only be cleared by reset. -- ------------------------------------------------------------- IMP_STOP_REQ_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_stop_request <= '0'; sig_sstrb_stop_mask <= (others => '0'); elsif (skid_stop = '1') then sig_stop_request <= '1'; sig_sstrb_stop_mask <= (others => '1'); else null; -- hold current state end if; end if; end process IMP_STOP_REQ_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_SREADY_FLOP -- -- Process Description: -- This process implements the flag to clear the s_ready -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_SREADY_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_sready_stop_reg <= '0'; elsif (sig_sready_stop_set = '1') then sig_sready_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_SREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_MVALID_FLOP -- -- Process Description: -- This process implements the flag to clear the m_valid -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_MVALID_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_mvalid_stop_reg <= '0'; elsif (sig_mvalid_stop_set = '1') then sig_mvalid_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_MVALID_FLOP; ---------------------------------------------------------------------------- -- Logic for the detection of the most significant asserted strobe bit and -- the formulation of the index of that strobe bit. ---------------------------------------------------------------------------- ------------------------------------------------------------ -- Instance: I_MSSAI_DETECTION -- -- Description: -- This module detects the most significant asserted strobe -- and outputs the bit index of the strobe. -- ------------------------------------------------------------ I_MSSAI_DETECTION : entity axi_datamover_v5_1.axi_datamover_ms_strb_set generic map ( C_STRB_WIDTH => STROBE_WIDTH , C_INDEX_WIDTH => C_INDEX_WIDTH ) port map ( -- Input Stream Strobes strbs_in => sig_strb_skid_mux_out , -- Index of the most significant strobe asserted ms_strb_index => sig_mssa_index_out , -- Output flag for a detected error associated Strobe assertions strb_error => sig_strb_error ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSSAI_REG -- -- Process Description: -- This process implements the output register for the -- Skid Buffer's MSSAI value and the strobe error bit -- that is needed by the Scatter module. -- ------------------------------------------------------------- IMP_MSSAI_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_mvalid_stop_reg = '1') then sig_mssa_index_reg_out <= (others => '0'); sig_strb_error_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_mssa_index_reg_out <= sig_mssa_index_out; sig_strb_error_reg_out <= sig_strb_error; else null; -- hold current state end if; end if; end process IMP_MSSAI_REG; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_wrdata_cntl.vhd	5	91465	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_wrdata_cntl.vhd -- -- Description: -- This file implements the DataMover Master Write Data Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_fifo; ------------------------------------------------------------------------------- entity axi_sg_wrdata_cntl is generic ( C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0; -- Indicates the Data Realignment function is included (external -- to this module) C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates the INDET BTT function is included (external -- to this module) C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1; -- Sets the width of the data2wsc_bytes_rcvd port used for -- relaying the actual number of bytes received when Idet BTT is -- enabled (C_ENABLE_INDET_BTT = 1) C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the LS bits of the transfer address that -- are being used to Demux write data to a wider AXI4 Write -- Data Bus C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4; -- Sets the depth of the internal command fifo used for the -- command queue C_MMAP_DWIDTH : Integer range 32 to 1024 := 32; -- Indicates the native data width of the Read Data port C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Stream output data port C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Indicates the width of the Tag field of the input command C_FAMILY : String := "virtex7" -- Indicates the device family of the target FPGA ); port ( -- Clock and Reset inputs ---------------------------------------------- -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------------ -- Soft Shutdown internal interface ------------------------------------ -- rst2data_stop_request : in std_logic; -- -- Active high soft stop request to modules -- -- data2addr_stop_req : Out std_logic; -- -- Active high signal requesting the Address Controller -- -- to stop posting commands to the AXI Read Address Channel -- -- data2rst_stop_cmplt : Out std_logic; -- -- Active high indication that the Data Controller has completed -- -- any pending transfers committed by the Address Controller -- -- after a stop has been requested by the Reset module. -- ------------------------------------------------------------------------ -- Store and Forward support signals for external User logic ------------ -- wr_xfer_cmplt : Out std_logic; -- -- Active high indication that the Data Controller has completed -- -- a single write data transfer on the AXI4 Write Data Channel. -- -- This signal is escentially echos the assertion of wlast sent -- -- to the AXI4. -- -- s2mm_ld_nxt_len : out std_logic; -- -- Active high pulse indicating a new xfer length has been queued -- -- to the WDC Cmd FIFO -- -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- -- Bus indicating the AXI LEN value associated with the xfer command -- -- loaded into the WDC Command FIFO. -- ------------------------------------------------------------------------- -- AXI Write Data Channel Skid buffer I/O --------------------------------------- -- data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- Write DATA output to skid buffer -- -- data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- Write DATA output to skid buffer -- -- data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- Write DATA output to skid buffer -- -- data2skid_wlast : Out std_logic; -- -- Write LAST output to skid buffer -- -- data2skid_wvalid : Out std_logic; -- -- Write VALID output to skid buffer -- -- skid2data_wready : In std_logic; -- -- Write READY input from skid buffer -- ---------------------------------------------------------------------------------- -- AXI Slave Stream In ----------------------------------------------------------- -- s2mm_strm_wvalid : In std_logic; -- -- AXI Stream VALID input -- -- s2mm_strm_wready : Out Std_logic; -- -- AXI Stream READY Output -- -- s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- AXI Stream data input -- -- s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- AXI Stream STRB input -- -- s2mm_strm_wlast : In std_logic; -- -- AXI Stream LAST input -- ---------------------------------------------------------------------------------- -- Stream input sideband signal from Indeterminate BTT and/or DRE ---------------- -- s2mm_strm_eop : In std_logic; -- -- Stream End of Packet marker input. This is only used when Indeterminate -- -- BTT mode is enable. Otherwise it is ignored -- -- -- s2mm_stbs_asserted : in std_logic_vector(7 downto 0); -- -- Indicates the number of asserted WSTRB bits for the -- -- associated input stream data beat -- -- -- -- Realigner Underrun/overrun error flag used in non Indeterminate BTT -- -- Mode -- realign2wdc_eop_error : In std_logic ; -- -- Asserted active high and will only clear with reset. It is only used -- -- when Indeterminate BTT is not enabled and the Realigner Module is -- -- instantiated upstream from the WDC. The Realigner will detect overrun -- -- underrun conditions and will will relay these conditions via this signal. -- ---------------------------------------------------------------------------------- -- Command Calculator Interface -------------------------------------------------- -- mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- The next command start address LSbs to use for the write strb -- -- demux (only used if Stream data width is less than the MMap Dwidth). -- -- mstr2data_len : In std_logic_vector(7 downto 0); -- -- The LEN value output to the Address Channel -- -- mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- The starting strobe value to use for the first stream data beat -- -- mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- The endiing (LAST) strobe value to use for the last stream -- -- data beat -- -- mstr2data_drr : In std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2data_eof : In std_logic; -- -- The endiing tranfer of a sequence of transfers -- -- mstr2data_sequential : In std_logic; -- -- The next sequential tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2data_calc_error : In std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2data_cmd_cmplt : In std_logic; -- -- The final child tranfer of a parent command fetched from -- -- the Command FIFO (not necessarily an EOF command) -- -- mstr2data_cmd_valid : In std_logic; -- -- The next command valid indication to the Data Channel -- -- Controller for the AXI MMap -- -- data2mstr_cmd_ready : Out std_logic ; -- -- Indication from the Data Channel Controller that the -- -- command is being accepted on the AXI Address -- -- Channel -- ---------------------------------------------------------------------------------- -- Address Controller Interface -------------------------------------------------- -- addr2data_addr_posted : In std_logic ; -- -- Indication from the Address Channel Controller to the -- -- Data Controller that an address has been posted to the -- -- AXI Address Channel -- -- -- data2addr_data_rdy : out std_logic; -- -- Indication that the Data Channel is ready to send the first -- -- databeat of the next command on the write data channel. -- -- This is used for the "wait for data" feature which keeps the -- -- address controller from issuing a transfer request until the -- -- corresponding data valid is asserted on the stream input. The -- -- WDC will continue to assert the output until an assertion on -- -- the addr2data_addr_posted is received. -- --------------------------------------------------------------------------------- -- Premature TLAST assertion error flag ------------------------------------------ -- data2all_tlast_error : Out std_logic; -- -- When asserted, this indicates the data controller detected -- -- a premature TLAST assertion on the incoming data stream. -- --------------------------------------------------------------------------------- -- Data Controller Halted Status ------------------------------------------------- -- data2all_dcntlr_halted : Out std_logic; -- -- When asserted, this indicates the data controller has satisfied -- -- all pending transfers queued by the Address Controller and is halted. -- ---------------------------------------------------------------------------------- -- Input Stream Skid Buffer Halt control ----------------------------------------- -- data2skid_halt : Out std_logic; -- -- The data controller asserts this output for 1 primary clock period -- -- The pulse commands the MM2S Stream skid buffer to tun off outputs -- -- at the next tlast transmission. -- ---------------------------------------------------------------------------------- -- Write Status Controller Interface --------------------------------------------- -- data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The command tag -- -- data2wsc_calc_err : Out std_logic ; -- -- Indication that the current command out from the Cntl FIFO -- -- has a calculation error -- -- data2wsc_last_err : Out std_logic ; -- -- Indication that the current write transfer encountered a premature -- -- TLAST assertion on the incoming Stream Channel -- -- data2wsc_cmd_cmplt : Out std_logic ; -- -- Indication by the Data Channel Controller that the -- -- corresponding status is the last status for a command -- -- pulled from the command FIFO -- -- wsc2data_ready : in std_logic; -- -- Input from the Write Status Module indicating that the -- -- Status Reg/FIFO is ready to accept data -- -- data2wsc_valid : Out std_logic; -- -- Output to the Command/Status Module indicating that the -- -- Data Controller has valid tag and err indicators to write -- -- to the Status module -- -- data2wsc_eop : Out std_logic; -- -- Output to the Write Status Controller indicating that the -- -- associated command status also corresponds to a End of Packet -- -- marker for the input Stream. This is only used when Inderminate -- -- BTT is enabled in the S2MM. -- -- data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); -- -- Output to the Write Status Controller indicating the actual -- -- number of bytes received from the Stream input for the -- -- corresponding command status. This is only used when Inderminate -- -- BTT is enabled in the S2MM. -- -- wsc2mstr_halt_pipe : In std_logic -- -- Indication to Halt the Data and Address Command pipeline due -- -- to the Status FIFO going full or an internal error being logged -- ---------------------------------------------------------------------------------- ); end entity axi_sg_wrdata_cntl; architecture implementation of axi_sg_wrdata_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declaration ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_dbeat_residue_width -- -- Function Description: -- Calculates the number of Least significant bits of the BTT field -- that are unused for the LEN calculation -- ------------------------------------------------------------------- -- coverage off function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream begin case bytes_per_beat is when 128 => -- 1024 bits -- Added per Per CR616409 temp_dbeat_residue_width := 7; -- Added per Per CR616409 when 64 => -- 512 bits -- Added per Per CR616409 temp_dbeat_residue_width := 6; -- Added per Per CR616409 when 32 => -- 256 bits temp_dbeat_residue_width := 5; when 16 => -- 128 bits temp_dbeat_residue_width := 4; when 8 => -- 64 bits temp_dbeat_residue_width := 3; when 4 => -- 32 bits temp_dbeat_residue_width := 2; when 2 => -- 16 bits temp_dbeat_residue_width := 1; when others => -- assume 1-byte transfers temp_dbeat_residue_width := 0; end case; Return (temp_dbeat_residue_width); end function funct_get_dbeat_residue_width; -- coverage on ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_cnt_width -- -- Function Description: -- Sets a count width based on a fifo depth. A depth of 4 or less -- is a special case which requires a minimum count width of 3 bits. -- ------------------------------------------------------------------- function funct_set_cnt_width (fifo_depth : integer) return integer is Variable temp_cnt_width : Integer := 4; begin if (fifo_depth <= 4) then temp_cnt_width := 3; -- coverage off elsif (fifo_depth <= 8) then temp_cnt_width := 4; elsif (fifo_depth <= 16) then temp_cnt_width := 5; elsif (fifo_depth <= 32) then temp_cnt_width := 6; else -- fifo depth <= 64 temp_cnt_width := 7; end if; -- coverage on Return (temp_cnt_width); end function funct_set_cnt_width; -- Constant Declarations -------------------------------------------- Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8; Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0'); Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH; Constant LEN_WIDTH : integer := 8; Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; Constant DRR_WIDTH : integer := 1; Constant EOF_WIDTH : integer := 1; Constant CALC_ERR_WIDTH : integer := 1; Constant CMD_CMPLT_WIDTH : integer := 1; Constant SEQUENTIAL_WIDTH : integer := 1; Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field SADDR_LSB_WIDTH + -- LS Address field width LEN_WIDTH + -- LEN field STRB_WIDTH + -- Starting Strobe field STRB_WIDTH + -- Ending Strobe field DRR_WIDTH + -- DRE Re-alignment Request Flag Field EOF_WIDTH + -- EOF flag field SEQUENTIAL_WIDTH + -- Sequential command flag CMD_CMPLT_WIDTH + -- Command Complete Flag CALC_ERR_WIDTH; -- Calc error flag Constant TAG_STRT_INDEX : integer := 0; Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH; Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH; Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH; Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH; Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH; Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH; Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH; Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH; Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH; Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8; Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH); Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH); Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '1'); -- Signal Declarations -------------------------------------------- signal sig_get_next_dqual : std_logic := '0'; signal sig_last_mmap_dbeat : std_logic := '0'; signal sig_last_mmap_dbeat_reg : std_logic := '0'; signal sig_mmap2data_ready : std_logic := '0'; signal sig_data2mmap_valid : std_logic := '0'; signal sig_data2mmap_last : std_logic := '0'; signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_ld_new_cmd : std_logic := '0'; signal sig_ld_new_cmd_reg : std_logic := '0'; signal sig_cmd_cmplt_reg : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_posted : std_logic := '0'; signal sig_dqual_rdy : std_logic := '0'; signal sig_good_mmap_dbeat : std_logic := '0'; signal sig_first_dbeat : std_logic := '0'; signal sig_last_dbeat : std_logic := '0'; signal sig_single_dbeat : std_logic := '0'; signal sig_new_len_eq_0 : std_logic := '0'; signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0'); Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0; signal sig_dbeat_cntr_eq_0 : std_logic := '0'; signal sig_dbeat_cntr_eq_1 : std_logic := '0'; signal sig_wsc_ready : std_logic := '0'; signal sig_push_to_wsc : std_logic := '0'; signal sig_push_to_wsc_cmplt : std_logic := '0'; signal sig_set_push2wsc : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_tlast_error : std_logic := '0'; signal sig_tlast_error_strbs : std_logic := '0'; signal sig_end_stbs_match_err : std_logic := '0'; signal sig_tlast_error_reg : std_logic := '0'; signal sig_cmd_is_eof : std_logic := '0'; signal sig_push_err2wsc : std_logic := '0'; signal sig_tlast_error_ovrrun : std_logic := '0'; signal sig_tlast_error_undrrun : std_logic := '0'; signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_next_eof_reg : std_logic := '0'; signal sig_next_sequential_reg : std_logic := '0'; signal sig_next_cmd_cmplt_reg : std_logic := '0'; signal sig_next_calc_error_reg : std_logic := '0'; signal sig_pop_dqual_reg : std_logic := '0'; signal sig_push_dqual_reg : std_logic := '0'; signal sig_dqual_reg_empty : std_logic := '0'; signal sig_dqual_reg_full : std_logic := '0'; signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_posted_cntr_eq_0 : std_logic := '0'; signal sig_addr_posted_cntr_max : std_logic := '0'; signal sig_decr_addr_posted_cntr : std_logic := '0'; signal sig_incr_addr_posted_cntr : std_logic := '0'; signal sig_addr_posted_cntr_eq_1 : std_logic := '0'; signal sig_apc_going2zero : std_logic := '0'; signal sig_aposted_cntr_ready : std_logic := '0'; signal sig_addr_chan_rdy : std_logic := '0'; Signal sig_no_posted_cmds : std_logic := '0'; signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_ls_addr_cntr : std_logic := '0'; signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0'); Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_drr : std_logic := '0'; signal sig_fifo_next_eof : std_logic := '0'; signal sig_fifo_next_cmd_cmplt : std_logic := '0'; signal sig_fifo_next_sequential : std_logic := '0'; signal sig_fifo_next_calc_error : std_logic := '0'; signal sig_cmd_fifo_empty : std_logic := '0'; signal sig_fifo_wr_cmd_valid : std_logic := '0'; signal sig_fifo_wr_cmd_ready : std_logic := '0'; signal sig_fifo_rd_cmd_valid : std_logic := '0'; signal sig_fifo_rd_cmd_ready : std_logic := '0'; signal sig_sequential_push : std_logic := '0'; signal sig_clr_dqual_reg : std_logic := '0'; signal sig_tlast_err_stop : std_logic := '0'; signal sig_halt_reg : std_logic := '0'; signal sig_halt_reg_dly1 : std_logic := '0'; signal sig_halt_reg_dly2 : std_logic := '0'; signal sig_halt_reg_dly3 : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_stop_wvalid : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_s2mm_strm_wready : std_logic := '0'; signal sig_s2mm_strm_wready_del : std_logic := '0'; signal sig_good_strm_dbeat : std_logic := '0'; signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_wfd_simult_clr_set : std_logic := '0'; signal sig_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_spcl_push_err2wsc : std_logic := '0'; begin --(architecture implementation) -- Command calculator handshake data2mstr_cmd_ready <= sig_data2mstr_cmd_ready; -- Write Data Channel Skid Buffer Port assignments sig_mmap2data_ready <= skid2data_wready ; data2skid_wvalid <= sig_data2mmap_valid ; data2skid_wlast <= sig_data2mmap_last ; data2skid_wdata <= sig_data2mmap_data ; data2skid_saddr_lsb <= sig_addr_lsb_reg ; -- AXI MM2S Stream Channel Port assignments sig_data2mmap_data <= s2mm_strm_wdata ; -- Premature TLAST assertion indication data2all_tlast_error <= sig_tlast_error_reg ; -- Stream Input Ready Handshake s2mm_strm_wready <= sig_s2mm_strm_wready ; sig_good_strm_dbeat <= s2mm_strm_wvalid and sig_s2mm_strm_wready; -- sig_s2mm_strm_wready_del; sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and sig_dqual_rdy; -- Write Status Block interface signals data2wsc_valid <= sig_push_to_wsc and not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror sig_wsc_ready <= wsc2data_ready ; data2wsc_tag <= sig_data2wsc_tag ; data2wsc_calc_err <= sig_data2wsc_calc_err ; data2wsc_last_err <= sig_data2wsc_last_err ; data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ; -- Address Channel Controller synchro pulse input sig_addr_posted <= addr2data_addr_posted; -- Request to halt the Address Channel Controller data2addr_stop_req <= sig_halt_reg or sig_tlast_error_reg; -- Halted flag to the reset module data2rst_stop_cmplt <= sig_data2rst_stop_cmplt; -- Indicate the Write Data Controller is always ready data2addr_data_rdy <= '1'; -- Write Transfer Completed Status output wr_xfer_cmplt <= sig_wr_xfer_cmplt ; -- New LEN value is being loaded s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len; -- The new LEN value s2mm_wr_len <= sig_s2mm_wr_len; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_CMPLT_FLAG -- -- Process Description: -- Implements the status flag indicating that a write data -- transfer has completed. This is an echo of a wlast assertion -- and a qualified data beat on the AXI4 Write Data Channel. -- ------------------------------------------------------------- IMP_WR_CMPLT_FLAG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wr_xfer_cmplt <= '0'; sig_s2mm_strm_wready_del <= '0'; else sig_wr_xfer_cmplt <= sig_data2mmap_last and sig_good_strm_dbeat; sig_s2mm_strm_wready_del <= sig_s2mm_strm_wready; end if; end if; end process IMP_WR_CMPLT_FLAG; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Omits any Indeterminate BTT Support logic and includes -- any error detection needed in Non Indeterminate BTT mode. -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate begin sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb; -- Just housekeep the output port signals data2wsc_eop <= '0'; data2wsc_bytes_rcvd <= (others => '0'); -- WRSTRB logic ------------------------------ -- Generate the Write Strobes for the MMap Write Data Channel -- for the non Indeterminate BTT Case data2skid_wstrb <= (others => '1') when mmap_reset = '0' else (others => '0'); --sig_strt_strb_reg -- data2skid_wstrb <= sig_strt_strb_reg -- When (sig_first_dbeat = '1') -- Else sig_last_strb_reg -- When (sig_last_dbeat = '1') -- Else (others => '1'); -- Generate the Stream Ready for the Stream input side sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested (sig_mmap2data_ready and sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path sig_dqual_rdy and not(sig_calc_error_reg) and not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection -- MMap Write Data Channel Valid Handshaking sig_data2mmap_valid <= (s2mm_strm_wvalid or sig_tlast_error_reg or -- force valid if TLAST error sig_halt_reg ) and -- force valid if halt requested sig_addr_chan_rdy and -- xfers are commited on the address channel and sig_dqual_rdy and -- there are commands in the command fifo not(sig_calc_error_reg) and not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk -- or when the soft shutdown has completed ------------------------------------------------------------ -- If Generate -- -- Label: GEN_LOCAL_ERR_DETECT -- -- If Generate Description: -- Implements the local overrun and underrun detection when -- the S2MM Realigner is not included. -- -- ------------------------------------------------------------ GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate begin ------- Input Stream TLAST assertion error ------------------------------- sig_tlast_error_ovrrun <= sig_cmd_is_eof and sig_dbeat_cntr_eq_0 and sig_good_mmap_dbeat and not(s2mm_strm_wlast); sig_tlast_error_undrrun <= s2mm_strm_wlast and sig_good_mmap_dbeat and (not(sig_dbeat_cntr_eq_0) or not(sig_cmd_is_eof)); sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value (s2mm_strm_wlast = '1') and -- at TLAST assertion (sig_good_mmap_dbeat = '1')) -- Qualified databeat Else '0'; sig_tlast_error <= (sig_tlast_error_ovrrun or sig_tlast_error_undrrun or sig_end_stbs_match_err) and not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown -- Just housekeep this when local TLAST error detection is used sig_spcl_push_err2wsc <= '0'; end generate GEN_LOCAL_ERR_DETECT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_EXTERN_ERR_DETECT -- -- If Generate Description: -- Omits the local overrun and underrun detection and relies -- on the S2MM Realigner for the detection. -- ------------------------------------------------------------ GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate begin sig_tlast_error_undrrun <= '0'; -- not used here sig_tlast_error_ovrrun <= '0'; -- not used here sig_end_stbs_match_err <= '0'; -- not used here sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown -- Special case for pushing error status when timing is such that no -- addresses have been posted to AXI and a TLAST error has been detected -- by the Realigner module and propagated in from the Stream input side. sig_spcl_push_err2wsc <= sig_tlast_error_reg and not(sig_tlast_err_stop) and not(sig_addr_chan_rdy ); end generate GEN_EXTERN_ERR_DETECT; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERR_REG -- -- Process Description: -- Implements a sample and hold flop for the flag indicating -- that the input Stream TLAST assertion was not at the expected -- data beat relative to the commanded number of databeats -- from the associated command from the SCC or PCC. ------------------------------------------------------------- IMP_TLAST_ERR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_tlast_error_reg <= '0'; -- coverage off elsif (sig_tlast_error = '1') then sig_tlast_error_reg <= '1'; -- coverage on else null; -- hold current state end if; end if; end process IMP_TLAST_ERR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERROR_STOP -- -- Process Description: -- Implements the flop to generate a stop flag once the TLAST -- error condition has been relayed to the Write Status -- Controller. This stop flag is used to prevent any more -- pushes to the Write Status Controller. -- ------------------------------------------------------------- IMP_TLAST_ERROR_STOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_tlast_err_stop <= '0'; -- coverage off elsif (sig_tlast_error_reg = '1' and sig_push_to_wsc_cmplt = '1') then sig_tlast_err_stop <= '1'; -- coverage on else null; -- Hold State end if; end if; end process IMP_TLAST_ERROR_STOP; end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INDET_BTT -- -- If Generate Description: -- Includes any Indeterminate BTT Support logic. Primarily -- this is a counter for the input stream bytes received. The -- received byte count is relayed to the Write Status Controller -- for each parent command completed. -- When a packet completion is indicated via the EOP marker -- assertion, the status to the Write Status Controller also -- indicates the EOP condition. -- Note that underrun and overrun detection/error flagging -- is disabled in Indeterminate BTT Mode. -- ------------------------------------------------------------ -- GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate -- -- -- local constants -- Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH; -- Constant NUM_ZEROS_WIDTH : integer := 8; -- Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8; -- Constant STRBGEN_ADDR_SLICE_WIDTH : integer := -- funct_get_dbeat_residue_width(BYTES_PER_DBEAT); -- -- Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); -- -- -- -- -- local signals -- signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0'); -- signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0'); -- signal lsig_ld_byte_cntr : std_logic := '0'; -- signal lsig_incr_byte_cntr : std_logic := '0'; -- signal lsig_clr_byte_cntr : std_logic := '0'; -- signal lsig_end_of_cmd_reg : std_logic := '0'; -- signal lsig_eop_s_h_reg : std_logic := '0'; -- signal lsig_eop_reg : std_logic := '0'; -- signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); -- signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); -- -- -- -- -- begin -- -- -- -- Assign the outputs to the Write Status Controller -- data2wsc_eop <= lsig_eop_reg and -- not(sig_next_calc_error_reg); -- -- data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr); -- -- -- -- -- WRSTRB logic ------------------------------ -- -- -- -- --sig_strbgen_bytes <= (others => '1'); -- set to the max value -- -- -- -- set the length to the max number of bytes per databeat -- sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1)); -- -- -- -- -- -- -- sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb), -- STRBGEN_ADDR_SLICE_WIDTH)) ; -- -- -- -- -- ------------------------------------------------------------ -- -- Instance: I_STRT_STRB_GEN -- -- -- -- Description: -- -- Strobe generator used to generate the starting databeat -- -- strobe value for soft shutdown case where the S2MM has to -- -- flush out all of the transfers that have been committed -- -- to the AXI Write address channel. Starting Strobes must -- -- match the committed address offest for each transfer. -- -- -- ------------------------------------------------------------ -- I_STRT_STRB_GEN : entity axi_sg_v4_1.axi_sg_strb_gen2 -- generic map ( -- -- C_OP_MODE => 0 , -- 0 = Offset/Length mode -- C_STRB_WIDTH => BYTES_PER_DBEAT , -- C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , -- C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1 -- -- ) -- port map ( -- -- start_addr_offset => sig_strbgen_addr , -- end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0 -- num_valid_bytes => sig_strbgen_bytes , -- strb_out => sig_sfhalt_next_strt_strb -- -- ); -- -- -- -- -- -- -- -- -- Generate the WSTRB to use during soft shutdown -- sig_halt_strb <= sig_strt_strb_reg -- When (sig_first_dbeat = '1' or -- sig_single_dbeat = '1') -- Else (others => '1'); -- -- -- -- -- Generate the Write Strobes for the MMap Write Data Channel -- -- for the Indeterminate BTT case. Strobes come from the Stream -- -- input from the Indeterminate BTT module during normal operation. -- -- However, during soft shutdown, those strobes become unpredictable -- -- so generated strobes have to be used. -- data2skid_wstrb <= sig_halt_strb -- When (sig_halt_reg = '1') -- -- Else s2mm_strm_wstrb; -- -- -- -- -- Generate the Stream Ready for the Stream input side -- sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested -- (sig_mmap2data_ready and -- MMap is accepting the xfers -- sig_addr_chan_rdy and -- xfers are commited on the address channel and -- sig_dqual_rdy and -- there are commands in the command fifo -- not(sig_calc_error_reg) and -- No internal error -- not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk -- -- or when the soft shutdown has completed -- -- -- -- MMap Write Data Channel Valid Handshaking -- sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid -- sig_halt_reg ) and -- force valid if halt requested -- sig_addr_chan_rdy and -- xfers are commited on the address channel and -- sig_dqual_rdy and -- there are commands in the command fifo -- not(sig_calc_error_reg) and -- No internal error -- not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk -- -- or when the soft shutdown has completed -- -- -- -- -- TLAST Error housekeeping for Indeterminate BTT Mode -- -- There is no Underrun/overrun in Stroe and Forward mode -- -- sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT -- sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT -- sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT -- sig_tlast_error <= '0'; -- Not used with Indeterminate BTT -- sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT -- sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT -- -- -- -- -- -- ------------------------------------------------------------- -- -- Synchronous Process with Sync Reset -- -- -- -- Label: IMP_EOP_REG_FLOP -- -- -- -- Process Description: -- -- Register the End of Packet marker. -- -- -- ------------------------------------------------------------- -- IMP_EOP_REG_FLOP : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- if (mmap_reset = '1') then -- -- lsig_end_of_cmd_reg <= '0'; -- lsig_eop_reg <= '0'; -- -- -- Elsif (sig_good_strm_dbeat = '1') Then -- -- -- lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and -- s2mm_strm_wlast; -- -- lsig_eop_reg <= s2mm_strm_eop; -- -- else -- -- null; -- hold current state -- -- end if; -- end if; -- end process IMP_EOP_REG_FLOP; -- -- -- -- -- -- ----- Byte Counter Logic ----------------------------------------------- -- -- The Byte counter reflects the actual byte count received on the -- -- Stream input for each parent command loaded into the S2MM command -- -- FIFO. Thus it counts input bytes until the command complete qualifier -- -- is set and the TLAST input from the Stream input. -- -- -- lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start -- not(sig_good_strm_dbeat); -- immediately after the previous one finished. -- -- -- lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts -- sig_good_strm_dbeat; -- immediately after the previous one finished. -- -- lsig_incr_byte_cntr <= sig_good_strm_dbeat; -- -- -- lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted), -- BYTE_CNTR_WIDTH); -- -- ------------------------------------------------------------- -- -- Synchronous Process with Sync Reset -- -- -- -- Label: IMP_BYTE_CMTR -- -- -- -- Process Description: -- -- Keeps a running byte count per burst packet loaded into the -- -- xfer FIFO. It is based on the strobes set on the incoming -- -- Stream dbeat. -- -- -- ------------------------------------------------------------- -- IMP_BYTE_CMTR : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- if (mmap_reset = '1' or -- lsig_clr_byte_cntr = '1') then -- -- lsig_byte_cntr <= (others => '0'); -- -- elsif (lsig_ld_byte_cntr = '1') then -- -- lsig_byte_cntr <= lsig_byte_cntr_incr_value; -- -- elsif (lsig_incr_byte_cntr = '1') then -- -- lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value; -- -- else -- null; -- hold current value -- end if; -- end if; -- end process IMP_BYTE_CMTR; -- -- -- -- -- -- end generate GEN_INDET_BTT; -- -- Internal logic ------------------------------ sig_good_mmap_dbeat <= sig_mmap2data_ready and sig_data2mmap_valid; sig_last_mmap_dbeat <= sig_good_mmap_dbeat and sig_data2mmap_last; sig_get_next_dqual <= sig_last_mmap_dbeat; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_LAST_DBEAT -- -- Process Description: -- This implements a FLOP that creates a pulse -- indicating the LAST signal for an outgoing write data channel -- has been sent. Note that it is possible to have back to -- back LAST databeats. -- ------------------------------------------------------------- REG_LAST_DBEAT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_last_mmap_dbeat_reg <= '0'; else sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat; end if; end if; end process REG_LAST_DBEAT; ----- Write Status Interface Stuff -------------------------- sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready; sig_set_push2wsc <= (sig_good_mmap_dbeat and sig_dbeat_cntr_eq_0) or sig_push_err2wsc or sig_spcl_push_err2wsc; -- Special case from CR616212 ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_INTERR_PUSH_FLOP -- -- Process Description: -- Generate a 1 clock wide pulse when a calc error has propagated -- from the Command Calculator. This pulse is used to force a -- push of the error status to the Write Status Controller -- without a AXI transfer completion. -- ------------------------------------------------------------- IMP_INTERR_PUSH_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_push_err2wsc = '1') then sig_push_err2wsc <= '0'; elsif (sig_ld_new_cmd_reg = '1' and sig_calc_error_reg = '1') then sig_push_err2wsc <= '1'; else null; -- hold state end if; end if; end process IMP_INTERR_PUSH_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSH2WSC_FLOP -- -- Process Description: -- Implements a Sample and hold register for the outbound status -- signals to the Write Status Controller (WSC). This register -- has to support back to back transfer completions. -- ------------------------------------------------------------- IMP_PUSH2WSC_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or (sig_push_to_wsc_cmplt = '1' and sig_set_push2wsc = '0')) then sig_push_to_wsc <= '0'; sig_data2wsc_tag <= (others => '0'); sig_data2wsc_calc_err <= '0'; sig_data2wsc_last_err <= '0'; sig_data2wsc_cmd_cmplt <= '0'; elsif (sig_set_push2wsc = '1' and sig_tlast_err_stop = '0') then sig_push_to_wsc <= '1'; sig_data2wsc_tag <= sig_tag_reg ; sig_data2wsc_calc_err <= sig_calc_error_reg ; sig_data2wsc_last_err <= sig_tlast_error_reg or sig_tlast_error ; sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or sig_tlast_error_reg or sig_tlast_error ; else null; -- hold current state end if; end if; end process IMP_PUSH2WSC_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_LD_NEW_CMD_REG -- -- Process Description: -- Registers the flag indicating a new command has been -- loaded. Needs to be a 1 clk wide pulse. -- ------------------------------------------------------------- IMP_LD_NEW_CMD_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_ld_new_cmd_reg = '1') then sig_ld_new_cmd_reg <= '0'; else sig_ld_new_cmd_reg <= sig_ld_new_cmd; end if; end if; end process IMP_LD_NEW_CMD_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_NXT_LEN_REG -- -- Process Description: -- Registers the load control and length value for a command -- passed to the WDC input command interface. The registered -- signals are used for the external Indeterminate BTT support -- ports. -- ------------------------------------------------------------- IMP_NXT_LEN_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_s2mm_ld_nxt_len <= '0'; sig_s2mm_wr_len <= (others => '0'); else sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and sig_data2mstr_cmd_ready; sig_s2mm_wr_len <= mstr2data_len; end if; end if; end process IMP_NXT_LEN_REG; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DATA_CNTL_FIFO -- -- If Generate Description: -- Omits the input data control FIFO if the requested FIFO -- depth is 1. The Data Qualifier Register serves as a -- 1 deep FIFO by itself. -- ------------------------------------------------------------ GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate begin -- Command Calculator Handshake output sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ; -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and -- pre 13.1 sig_aposted_cntr_ready and -- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is -- pre 13.1 -- no calculation error being propagated sig_fifo_wr_cmd_ready <= sig_push_dqual_reg; sig_fifo_next_tag <= mstr2data_tag ; sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ; sig_fifo_next_len <= mstr2data_len ; sig_fifo_next_strt_strb <= mstr2data_strt_strb ; sig_fifo_next_last_strb <= mstr2data_last_strb ; sig_fifo_next_drr <= mstr2data_drr ; sig_fifo_next_eof <= mstr2data_eof ; sig_fifo_next_sequential <= mstr2data_sequential ; sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ; sig_fifo_next_calc_error <= mstr2data_calc_error ; end generate GEN_NO_DATA_CNTL_FIFO; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_DATA_CNTL_FIFO -- -- If Generate Description: -- Includes the input data control FIFO if the requested -- FIFO depth is more than 1. -- ------------------------------------------------------------ GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate begin -- Command Calculator Handshake output sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ; -- pop the fifo when dqual reg is pushed sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- Format the input fifo data word sig_cmd_fifo_data_in <= mstr2data_calc_error & mstr2data_cmd_cmplt & mstr2data_sequential & mstr2data_eof & mstr2data_drr & mstr2data_last_strb & mstr2data_strt_strb & mstr2data_len & mstr2data_saddr_lsb & mstr2data_tag ; -- Rip the output fifo data word sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX); sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto SADDR_LSB_STRT_INDEX); sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto LEN_STRT_INDEX); sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto STRT_STRB_STRT_INDEX); sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto LAST_STRB_STRT_INDEX); sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX); sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX); sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX); sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX); sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX); ------------------------------------------------------------ -- Instance: I_DATA_CNTL_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO -- ------------------------------------------------------------ I_DATA_CNTL_FIFO : entity axi_sg_v4_1.axi_sg_fifo generic map ( C_DWIDTH => DCTL_FIFO_WIDTH , C_DEPTH => C_DATA_CNTL_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_fifo_wr_cmd_valid , fifo_wr_tready => sig_fifo_wr_cmd_ready , fifo_wr_tdata => sig_cmd_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_fifo_rd_cmd_valid , fifo_rd_tready => sig_fifo_rd_cmd_ready , fifo_rd_tdata => sig_cmd_fifo_data_out , fifo_rd_empty => sig_cmd_fifo_empty ); end generate GEN_DATA_CNTL_FIFO; -- Data Qualifier Register ------------------------------------ sig_ld_new_cmd <= sig_push_dqual_reg ; sig_dqual_rdy <= sig_dqual_reg_full ; sig_strt_strb_reg <= sig_next_strt_strb_reg ; sig_last_strb_reg <= sig_next_last_strb_reg ; sig_tag_reg <= sig_next_tag_reg ; sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ; sig_calc_error_reg <= sig_next_calc_error_reg ; sig_cmd_is_eof <= sig_next_eof_reg ; -- new for no bubbles between child requests sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified sig_last_dbeat and -- last data beat of transfer sig_next_sequential_reg;-- next queued command is sequential -- to the current command -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or -- pre 13.1 sig_dqual_reg_empty) and -- pre 13.1 sig_fifo_rd_cmd_valid and -- pre 13.1 sig_aposted_cntr_ready and -- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not -- pre 13.1 -- stalling the command execution pipe sig_push_dqual_reg <= (sig_sequential_push or sig_dqual_reg_empty) and sig_fifo_rd_cmd_valid and sig_aposted_cntr_ready and not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not -- stalling the command execution pipe sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and sig_get_next_dqual and sig_dqual_reg_full ; -- new for no bubbles between child requests sig_clr_dqual_reg <= mmap_reset or (sig_pop_dqual_reg and not(sig_push_dqual_reg)); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DQUAL_REG -- -- Process Description: -- This process implements a register for the Data -- Control and qualifiers. It operates like a 1 deep Sync FIFO. -- ------------------------------------------------------------- IMP_DQUAL_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_clr_dqual_reg = '1') then sig_next_tag_reg <= (others => '0'); sig_next_strt_strb_reg <= (others => '0'); sig_next_last_strb_reg <= (others => '0'); sig_next_eof_reg <= '0' ; sig_next_sequential_reg <= '0' ; sig_next_cmd_cmplt_reg <= '0' ; sig_next_calc_error_reg <= '0' ; sig_dqual_reg_empty <= '1' ; sig_dqual_reg_full <= '0' ; elsif (sig_push_dqual_reg = '1') then sig_next_tag_reg <= sig_fifo_next_tag ; sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ; sig_next_last_strb_reg <= sig_fifo_next_last_strb ; sig_next_eof_reg <= sig_fifo_next_eof ; sig_next_sequential_reg <= sig_fifo_next_sequential ; sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ; sig_next_calc_error_reg <= sig_fifo_next_calc_error ; sig_dqual_reg_empty <= '0'; sig_dqual_reg_full <= '1'; else null; -- don't change state end if; end if; end process IMP_DQUAL_REG; -- Address LS Cntr logic -------------------------- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr); sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH); sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_ADDR_LSB_CNTR -- -- Process Description: -- Implements the LS Address Counter used for controlling -- the Write STRB DeMux during Burst transfers -- ------------------------------------------------------------- DO_ADDR_LSB_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or (sig_pop_dqual_reg = '1'and sig_push_dqual_reg = '0')) then -- Clear the Counter sig_ls_addr_cntr <= (others => '0'); elsif (sig_push_dqual_reg = '1') then -- Load the Counter sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb); elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd; else null; -- Hold Current value end if; end if; end process DO_ADDR_LSB_CNTR; -- Address Posted Counter Logic -------------------------------------- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or sig_apc_going2zero) ; -- Gates data channel xfer handshake sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted sig_incr_addr_posted_cntr <= sig_addr_posted ; sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ; sig_addr_posted_cntr_eq_0 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ZERO) Else '0'; sig_addr_posted_cntr_max <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_MAX) Else '0'; sig_addr_posted_cntr_eq_1 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ONE) Else '0'; sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and sig_decr_addr_posted_cntr and not(sig_incr_addr_posted_cntr); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_POSTED_FIFO_CNTR -- -- Process Description: -- This process implements a counter for the tracking -- if an Address has been posted on the AXI address channel. -- The Data Controller must wait for an address to be posted -- before proceeding with the corresponding data transfer on -- the Data Channel. The counter is also used to track flushing -- operations where all transfers commited on the AXI Address -- Channel have to be completed before a halt can occur. ------------------------------------------------------------- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_addr_posted_cntr <= ADDR_POSTED_ZERO; elsif (sig_incr_addr_posted_cntr = '1' and sig_decr_addr_posted_cntr = '0' and sig_addr_posted_cntr_max = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ; elsif (sig_incr_addr_posted_cntr = '0' and sig_decr_addr_posted_cntr = '1' and sig_addr_posted_cntr_eq_0 = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ; else null; -- don't change state end if; end if; end process IMP_ADDR_POSTED_FIFO_CNTR; ------- First/Middle/Last Dbeat detimination ------------------- sig_new_len_eq_0 <= '1' When (sig_fifo_next_len = LEN_OF_ZERO) else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_FIRST_MID_LAST -- -- Process Description: -- Implements the detection of the First/Mid/Last databeat of -- a transfer. -- ------------------------------------------------------------- DO_FIRST_MID_LAST : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_first_dbeat <= '0'; sig_last_dbeat <= '0'; sig_single_dbeat <= '0'; elsif (sig_ld_new_cmd = '1') then sig_first_dbeat <= not(sig_new_len_eq_0); sig_last_dbeat <= sig_new_len_eq_0; sig_single_dbeat <= sig_new_len_eq_0; Elsif (sig_dbeat_cntr_eq_1 = '1' and sig_good_mmap_dbeat = '1') Then sig_first_dbeat <= '0'; sig_last_dbeat <= '1'; sig_single_dbeat <= '0'; Elsif (sig_dbeat_cntr_eq_0 = '0' and sig_dbeat_cntr_eq_1 = '0' and sig_good_mmap_dbeat = '1') Then sig_first_dbeat <= '0'; sig_last_dbeat <= '0'; sig_single_dbeat <= '0'; else null; -- hold current state end if; end if; end process DO_FIRST_MID_LAST; ------- Data Controller Halted Indication ------------------------------- data2all_dcntlr_halted <= sig_no_posted_cmds or sig_calc_error_reg; ------- Data Beat counter logic ------------------------------- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr); sig_dbeat_cntr_eq_0 <= '1' when (sig_dbeat_cntr_int = 0) Else '0'; sig_dbeat_cntr_eq_1 <= '1' when (sig_dbeat_cntr_int = 1) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_DBEAT_CNTR -- -- Process Description: -- Implements the transfer data beat counter used to track -- progress of the transfer. -- ------------------------------------------------------------- DO_DBEAT_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_dbeat_cntr <= (others => '0'); elsif (sig_ld_new_cmd = '1') then sig_dbeat_cntr <= unsigned(sig_fifo_next_len); Elsif (sig_good_mmap_dbeat = '1' and sig_dbeat_cntr_eq_0 = '0') Then sig_dbeat_cntr <= sig_dbeat_cntr-1; else null; -- Hold current state end if; end if; end process DO_DBEAT_CNTR; ------- Soft Shutdown Logic ------------------------------- -- Formulate the soft shutdown complete flag sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown sig_no_posted_cmds and not(sig_calc_error_reg)) or (sig_halt_reg_dly3 and -- Shutdown after error trap sig_calc_error_reg); -- Generate a gate signal to deassert the WVALID output -- for 1 clock cycle after a WLAST is issued. This only -- occurs when in soft shutdown mode. sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and sig_halt_reg) or sig_data2rst_stop_cmplt; -- Assign the output port skid buf control for the -- input Stream skid buffer data2skid_halt <= sig_data2skid_halt; -- Create a 1 clock wide pulse to tell the input -- stream skid buffer to shut down. sig_data2skid_halt <= sig_halt_reg_dly2 and not(sig_halt_reg_dly3); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG -- -- Process Description: -- Implements the flop for capturing the Halt request from -- the Reset module. -- ------------------------------------------------------------- IMP_HALT_REQ_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg <= '0'; elsif (rst2data_stop_request = '1') then sig_halt_reg <= '1'; else null; -- Hold current State end if; end if; end process IMP_HALT_REQ_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG_DLY -- -- Process Description: -- Implements the flops for delaying the halt request by 3 -- clocks to allow the Address Controller to halt before the -- Data Contoller can safely indicate it has exhausted all -- transfers committed to the AXI Address Channel by the Address -- Controller. -- ------------------------------------------------------------- IMP_HALT_REQ_REG_DLY : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg_dly1 <= '0'; sig_halt_reg_dly2 <= '0'; sig_halt_reg_dly3 <= '0'; else sig_halt_reg_dly1 <= sig_halt_reg; sig_halt_reg_dly2 <= sig_halt_reg_dly1; sig_halt_reg_dly3 <= sig_halt_reg_dly2; end if; end if; end process IMP_HALT_REQ_REG_DLY; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_slice.vhd	19	4781	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; entity axi_datamover_slice is generic ( C_DATA_WIDTH : Integer range 1 to 200 := 64 ); port ( ACLK : in std_logic; ARESET : in std_logic; -- Slave side S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0); S_VALID : in std_logic; S_READY : out std_logic; -- Master side M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0); M_VALID : out std_logic; M_READY : in std_logic ); end entity axi_datamover_slice; architecture working of axi_datamover_slice is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes"; signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0); signal s_ready_i : std_logic; signal m_valid_i : std_logic; signal areset_d : std_logic_vector (1 downto 0); begin -- assign local signal to its output signal S_READY <= s_ready_i; M_VALID <= m_valid_i; process (ACLK) begin if (ACLK'event and ACLK = '1') then areset_d(0) <= ARESET; areset_d(1) <= areset_d(0); end if; end process; -- Save payload data whenever we have a transaction on the slave side process (ACLK) begin if (ACLK'event and ACLK = '1') then if (S_VALID = '1' and s_ready_i = '1') then storage_data <= S_PAYLOAD_DATA; else storage_data <= storage_data; end if; end if; end process; M_PAYLOAD_DATA <= storage_data; -- M_Valid set to high when we have a completed transfer on slave side -- Is removed on a M_READY except if we have a new transfer on the slave side process (ACLK) begin if (ACLK'event and ACLK = '1') then if (areset_d (1) = '1') then m_valid_i <= '0'; elsif (S_VALID = '1') then m_valid_i <= '1'; elsif (M_READY = '1') then m_valid_i <= '0'; else m_valid_i <= m_valid_i; end if; end if; end process; -- Slave Ready is either when Master side drives M_Ready or we have space in our storage data s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0)); end working;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_noqueue.vhd	3	30514	-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ********************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_noqueue.vhd -- Description: This entity provides the descriptor update for the No Queue mode -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 -- 1 IOC bit + 32 Update Status Bits ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- updt2_active : in std_logic ; -- updt2_queue_empty : out std_logic ; -- updt2_ioc : out std_logic ; -- updt2_ioc_irq_set : in std_logic ; -- -- dma2_interr : out std_logic ; -- dma2_slverr : out std_logic ; -- dma2_decerr : out std_logic ; -- dma2_interr_set : in std_logic ; -- dma2_slverr_set : in std_logic ; -- dma2_decerr_set : in std_logic ; -- -- --*****************************-- -- -- Channel Update Interface In -- -- --*****************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- -- Update Pointer Stream -- s_axis2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis2_updtptr_tvalid : in std_logic ; -- s_axis2_updtptr_tready : out std_logic ; -- s_axis2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis2_updtsts_tvalid : in std_logic ; -- s_axis2_updtsts_tready : out std_logic ; -- s_axis2_updtsts_tlast : in std_logic ; -- -- --*****************************-- -- -- Channel Update Interface Out-- -- --*****************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Contstants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal writing_curdesc : std_logic := '0'; signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; signal writing_status : std_logic := '0'; signal curdesc_tready : std_logic := '0'; signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; signal writing_status_re_ch1 : std_logic := '0'; signal writing_status_re_ch2 : std_logic := '0'; signal updt_active_int : std_logic := '0'; signal s_axis_updtptr_tvalid_int : std_logic := '0'; signal s_axis_updtsts_tvalid_int : std_logic := '0'; signal s_axis_updtsts_tlast_int : std_logic := '0'; signal s_axis_updtptr_tdata_int : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s_axis_qual : std_logic := '0'; signal s_axis2_qual : std_logic := '0'; signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); -- signal m_axis_updt_tlast_mm2s : std_logic ; -- signal m_axis_updt_tvalid_mm2s : std_logic ; signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); -- signal m_axis_updt_tlast_s2mm : std_logic ; -- signal m_axis_updt_tvalid_s2mm : std_logic ; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else m_axis_updt_tdata_s2mm; m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else m_axis_updt_tvalid_s2mm; m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else m_axis_updt_tlast_s2mm; updt_active_int <= updt_active or updt2_active; s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid; s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid; s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast; s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active; s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active; -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- the channel REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active or updt2_active; end if; end if; end process REG_ACTIVE; updt_active_re <= (updt_active or updt2_active) and not updt_active_d1; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active_int, s_axis_updtptr_tvalid_int, updt_active, updt2_active, s_axis_qual, s_axis2_qual, s_axis_updtptr_tvalid, s_axis2_updtptr_tvalid, s_axis_updtsts_tvalid_int, m_axis_updt_tready) begin write_curdesc_lsb <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; writing_curdesc <= '0'; curdesc_tready <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or (s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then writing_curdesc <= '1'; pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor when READ_CURDESC_LSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then write_curdesc_lsb <= '1'; -- pntr_ns <= READ_CURDESC_MSB; pntr_ns <= WRITE_STATUS; else -- coverage off pntr_ns <= READ_CURDESC_LSB; -- coverage on end if; -- coverage off --------------------------------------------------------------- -- Get upper current descriptor when READ_CURDESC_MSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. if(s_axis_updtptr_tvalid_int = '1')then write_curdesc_msb <= '1'; pntr_ns <= WRITE_STATUS; else pntr_ns <= READ_CURDESC_MSB; end if; -- coverage on --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => writing_status <= '1'; --s_axis_updtsts_tvalid_int; if((s_axis_qual = '1' and m_axis_updt_tready = '1') or (s_axis2_qual = '1' and m_axis_updt_tready = '1')) then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; -- coverage off when others => pntr_ns <= IDLE; -- coverage on end case; end process CURDESC_PNTR_STATE; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; -- Status stream signals m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status; m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status; s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active; -- Pointer stream signals s_axis_updtptr_tready <= curdesc_tready and updt_active; -- Indicate need for channel service for update state machine updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status); m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status; m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status; s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active; -- Pointer stream signals s_axis2_updtptr_tready <= curdesc_tready and updt2_active; -- Indicate need for channel service for update state machine updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status); --***************************************************************** -- POINTER CAPTURE LOGIC --******************************************************************* s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else s_axis2_updtptr_tdata; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1')then updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1')then updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_lsb = '1')then -- elsif(write_curdesc_msb = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --***************************************************************** -- ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; writing_status_re_ch1 <= writing_status_re and updt_active; writing_status_re_ch2 <= writing_status_re and updt2_active; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re_ch1 = '1')then updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG2_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then updt2_ioc <= '0'; elsif(writing_status_re_ch2 = '1')then updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG2_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then dma2_interr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE2_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then dma2_slverr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE2_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then dma2_decerr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE2_DMADEC_ERROR; end implementation;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_sfifo_autord.vhd	1	19630	------------------------------------------------------------------------------- -- axi_cdma_sfifo_autord.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ********************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_cdma_sfifo_autord.vhd -- Version: initial -- Description: -- This file contains the logic to generate a CoreGen call to create a -- synchronous FIFO as part of the synthesis process of XST. This eliminates -- the need for multiple fixed netlists for various sizes and widths of FIFOs. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library lib_fifo_v1_0; use lib_fifo_v1_0.sync_fifo_fg; ------------------------------------------------------------------------------- entity axi_cdma_sfifo_autord is generic ( C_DWIDTH : integer := 32; C_DEPTH : integer := 128; C_DATA_CNT_WIDTH : integer := 8; C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0; C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0; C_USE_BLKMEM : Integer range 0 to 1 := 1; -- 1 = Use Block RAM -- 0 = USE SRL C_FAMILY : String := "virtex7" ); port ( -- Inputs SFIFO_Sinit : In std_logic; -- Reset SFIFO_Clk : In std_logic; -- Clock SFIFO_Wr_en : In std_logic; -- Write enable SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); -- Write Data input SFIFO_Rd_en : In std_logic; -- Read Enable SFIFO_Clr_Rd_Data_Valid : In std_logic; -- Clear the Read data valid -- Outputs SFIFO_DValid : Out std_logic; -- Read Data Valid indication SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); -- Read Data out SFIFO_Full : Out std_logic; -- FIFO Full flag SFIFO_Empty : Out std_logic; -- FIFO empty flag SFIFO_Almost_full : Out std_logic; -- FIFO almost Full flag SFIFO_Almost_empty : Out std_logic; -- FIFO almost empty flag SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); -- Read count SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); -- Read count minus 1 SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); -- Write count SFIFO_Rd_ack : Out std_logic -- Read acknowledge ); end entity axi_cdma_sfifo_autord; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of axi_cdma_sfifo_autord is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; -- Constant declarations -- none -- Signal declarations signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0'); signal raw_data_count_int : natural := 0; signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0'); signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0'); Signal corrected_empty : std_logic := '0'; Signal corrected_almost_empty : std_logic := '0'; Signal sig_SFIFO_empty : std_logic := '0'; -- backend fifo read ack sample and hold Signal sig_rddata_valid : std_logic := '0'; Signal hold_ff_q : std_logic := '0'; Signal ored_ack_ff_reset : std_logic := '0'; Signal autoread : std_logic := '0'; Signal sig_sfifo_rdack : std_logic := '0'; Signal fifo_read_enable : std_logic := '0'; begin -- Bit ordering translations write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little -- endian. SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to -- Big endian. -- Other port usages and assignments SFIFO_Rd_ack <= sig_sfifo_rdack; SFIFO_Almost_empty <= corrected_almost_empty; SFIFO_Empty <= corrected_empty; SFIFO_Wr_count <= raw_data_cnt_lil_end; SFIFO_Rd_count <= raw_data_count_corr; SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1; SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator fifo_read_enable <= SFIFO_Rd_en; -- or autoread; ------------------------------------------------------------ -- Instance: I_SYNC_FIFOGEN_FIFO -- -- Description: -- Instance for the synchronous fifo from proc common. -- ------------------------------------------------------------ I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.sync_fifo_fg generic map( C_FAMILY => C_FAMILY, -- requred for FIFO Gen C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH, C_ENABLE_RLOCS => 0, C_HAS_DCOUNT => 1, C_HAS_RD_ACK => 1, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 1, C_HAS_WR_ERR => 0, C_MEMORY_TYPE => C_USE_BLKMEM, C_PORTS_DIFFER => 0, C_RD_ACK_LOW => 0, C_READ_DATA_WIDTH => C_DWIDTH, C_READ_DEPTH => C_DEPTH, C_RD_ERR_LOW => 0, C_WR_ACK_LOW => 0, C_WR_ERR_LOW => 0, C_WRITE_DATA_WIDTH => C_DWIDTH, C_WRITE_DEPTH => C_DEPTH, C_PRELOAD_REGS => 1, -- 1 = first word fall through C_PRELOAD_LATENCY => 0, -- 0 = first word fall through C_USE_EMBEDDED_REG => 1 -- 0 ; ) port map( Clk => SFIFO_Clk, Sinit => SFIFO_Sinit, Din => write_data_lil_end, Wr_en => SFIFO_Wr_en, Rd_en => fifo_read_enable, Dout => read_data_lil_end, Almost_full => open, Full => SFIFO_Full, Empty => sig_SFIFO_empty, Rd_ack => sig_sfifo_rdack, Wr_ack => open, Rd_err => open, Wr_err => open, Data_count => raw_data_cnt_lil_end ); ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Read Ack assert & hold logic Needed because.... ------------------------------------------------------------------------------- -- 1) The CoreGen Sync FIFO has to be read once to get valid -- data to the read data port. -- 2) The Read ack from the fifo is only asserted for 1 clock. -- 3) A signal is needed that indicates valid data is at the read -- port of the FIFO and has not yet been used. This signal needs -- to be held until the next read operation occurs or a clear -- signal is received. ored_ack_ff_reset <= fifo_read_enable or SFIFO_Sinit or SFIFO_Clr_Rd_Data_Valid; sig_rddata_valid <= hold_ff_q or sig_sfifo_rdack; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ACK_HOLD_FLOP -- -- Process Description: -- Flop for registering the hold flag -- ------------------------------------------------------------- IMP_ACK_HOLD_FLOP : process (SFIFO_Clk) begin if (SFIFO_Clk'event and SFIFO_Clk = '1') then if (ored_ack_ff_reset = '1') then hold_ff_q <= '0'; else hold_ff_q <= sig_rddata_valid; end if; end if; end process IMP_ACK_HOLD_FLOP; -- generate auto-read enable. This keeps fresh data at the output -- of the FIFO whenever it is available. autoread <= '1' -- create a read strobe when the when (sig_rddata_valid = '0' and -- output data is NOT valid sig_SFIFO_empty = '0') -- and the FIFO is not empty Else '0'; raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end); ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_ALMOST_EMPTY -- -- If Generate Description: -- This IFGen corrects the FIFO Read Count output for the -- auto read function and includes the generation of the -- Almost_Empty flag. -- ------------------------------------------------------------ INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate -- local signals Signal raw_data_count_int_corr : integer := 0; Signal raw_data_count_int_corr_minus1 : integer := 0; begin ------------------------------------------------------------- -- Combinational Process -- -- Label: CORRECT_RD_CNT_IAE -- -- Process Description: -- This process corrects the FIFO Read Count output for the -- auto read function and includes the generation of the -- Almost_Empty flag. -- ------------------------------------------------------------- CORRECT_RD_CNT_IAE : process (sig_rddata_valid, sig_SFIFO_empty, raw_data_count_int) begin if (sig_rddata_valid = '0') then raw_data_count_int_corr <= 0; raw_data_count_int_corr_minus1 <= 0; corrected_empty <= '1'; corrected_almost_empty <= '0'; elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty raw_data_count_int_corr <= 1; raw_data_count_int_corr_minus1 <= 0; corrected_empty <= '0'; corrected_almost_empty <= '1'; Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty raw_data_count_int_corr <= 2; raw_data_count_int_corr_minus1 <= 1; corrected_empty <= '0'; corrected_almost_empty <= '0'; else -- rddata valid and modify rd count from FIFO raw_data_count_int_corr <= raw_data_count_int+1; raw_data_count_int_corr_minus1 <= raw_data_count_int; corrected_empty <= '0'; corrected_almost_empty <= '0'; end if; end process CORRECT_RD_CNT_IAE; raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr, C_DATA_CNT_WIDTH); raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1, C_DATA_CNT_WIDTH); end generate INCLUDE_ALMOST_EMPTY; ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_ALMOST_EMPTY -- -- If Generate Description: -- This process corrects the FIFO Read Count output for the -- auto read function and omits the generation of the -- Almost_Empty flag. -- ------------------------------------------------------------ OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate -- local signals Signal raw_data_count_int_corr : integer := 0; begin corrected_almost_empty <= '0'; -- always low ------------------------------------------------------------- -- Combinational Process -- -- Label: CORRECT_RD_CNT -- -- Process Description: -- This process corrects the FIFO Read Count output for the -- auto read function and omits the generation of the -- Almost_Empty flag. -- ------------------------------------------------------------- CORRECT_RD_CNT : process (sig_rddata_valid, sig_SFIFO_empty, raw_data_count_int) begin if (sig_rddata_valid = '0') then raw_data_count_int_corr <= 0; corrected_empty <= '1'; elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty raw_data_count_int_corr <= 1; corrected_empty <= '0'; Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty raw_data_count_int_corr <= 2; corrected_empty <= '0'; else -- rddata valid and modify rd count from FIFO raw_data_count_int_corr <= raw_data_count_int+1; corrected_empty <= '0'; end if; end process CORRECT_RD_CNT; raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr, C_DATA_CNT_WIDTH); end generate OMIT_ALMOST_EMPTY; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_ALMOST_FULL -- -- If Generate Description: -- This IfGen Includes the generation of the Amost_Full flag. -- -- ------------------------------------------------------------ INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate -- Local Constants Constant ALMOST_FULL_VALUE : integer := 2(C_DATA_CNT_WIDTH-1)-1; begin SFIFO_Almost_full <= '1' When raw_data_count_int = ALMOST_FULL_VALUE Else '0'; end generate INCLUDE_ALMOST_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_ALMOST_FULL -- -- If Generate Description: -- This IfGen Omits the generation of the Amost_Full flag. -- -- ------------------------------------------------------------ OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate begin SFIFO_Almost_full <= '0'; -- always low end generate OMIT_ALMOST_FULL; end imp;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/c2n_playback/vhdl_source/c2n_playback_io.vhd	3	7052	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; entity c2n_playback_io is port ( clock : in std_logic; reset : in std_logic; req : in t_io_req; resp : out t_io_resp; phi2_tick : in std_logic; c64_stopped : in std_logic; c2n_motor : in std_logic; c2n_sense : out std_logic; c2n_out_r : out std_logic; c2n_out_w : out std_logic ); end c2n_playback_io; architecture gideon of c2n_playback_io is signal enabled : std_logic; signal counter : unsigned(23 downto 0); signal error : std_logic; signal status : std_logic_vector(7 downto 0); signal fifo_dout : std_logic_vector(7 downto 0); signal fifo_read : std_logic; signal fifo_full : std_logic; signal fifo_empty : std_logic; signal fifo_almostfull : std_logic; signal fifo_flush : std_logic; signal fifo_write : std_logic; signal pulse : std_logic; signal toggle : std_logic; signal cnt2 : integer range 0 to 63; signal stream_en : std_logic; type t_state is (idle, multi1, multi2, multi3, count_down); signal state : t_state; signal state_enc : std_logic_vector(1 downto 0); signal mode : std_logic; signal sel : std_logic_vector(1 downto 0); signal c2n_out : std_logic; attribute register_duplication : string; attribute register_duplication of stream_en : signal is "no"; begin process(clock) begin if rising_edge(clock) then -- c2n pin out and sync if sel = "00" then c2n_sense <= enabled and not fifo_empty; else c2n_sense <= '0'; end if; stream_en <= enabled and c2n_motor; if fifo_empty='1' and enabled='1' then error <= '1'; end if; -- create a pulse of 50 ticks if cnt2 = 0 then pulse <= '0'; elsif phi2_tick='1' then cnt2 <= cnt2 - 1; end if; -- bus handling resp <= c_io_resp_init; if req.write='1' then resp.ack <= '1'; -- ack for fifo write as well. if req.address(11)='0' then enabled <= req.data(0); if req.data(1)='1' then error <= '0'; end if; fifo_flush <= req.data(2); mode <= req.data(3); sel <= req.data(7 downto 6); end if; elsif req.read='1' then resp.ack <= '1'; resp.data <= status; end if; case state is when idle => if enabled='1' and fifo_empty='0' then if fifo_dout=X"00" then if mode='1' then state <= multi1; else counter <= to_unsigned(256*8, counter'length); state <= count_down; end if; else counter <= unsigned("0000000000000" & fifo_dout & "000"); state <= count_down; end if; else toggle <= '0'; end if; when multi1 => if fifo_empty='0' then counter(7 downto 0) <= unsigned(fifo_dout); state <= multi2; elsif enabled = '0' then state <= idle; end if; when multi2 => if fifo_empty='0' then counter(15 downto 8) <= unsigned(fifo_dout); state <= multi3; elsif enabled = '0' then state <= idle; end if; when multi3 => if fifo_empty='0' then counter(23 downto 16) <= unsigned(fifo_dout); state <= count_down; elsif enabled = '0' then state <= idle; end if; when count_down => if phi2_tick='1' and stream_en='1' and c64_stopped='0' then if (counter = 1) or (counter = 0) then pulse <= '1'; toggle <= not toggle; cnt2 <= 49; state <= idle; else counter <= counter - 1; end if; elsif enabled = '0' then state <= idle; end if; when others => null; end case; if reset='1' then enabled <= '0'; counter <= (others => '0'); pulse <= '0'; error <= '0'; mode <= '0'; sel <= "00"; end if; end if; end process; fifo_write <= req.write and req.address(11); -- 0x800-0xFFF (2K) fifo_read <= '0' when state = count_down else (enabled and not fifo_empty); fifo: entity work.sync_fifo generic map ( g_depth => 2048, -- Actual depth. g_data_width => 8, g_threshold => 1536, g_storage => "block", g_fall_through => true ) port map ( clock => clock, reset => reset, rd_en => fifo_read, wr_en => fifo_write, din => req.data, dout => fifo_dout, flush => fifo_flush, full => fifo_full, almost_full => fifo_almostfull, empty => fifo_empty, count => open ); status(0) <= enabled; status(1) <= error; status(2) <= fifo_full; status(3) <= fifo_almostfull; status(4) <= state_enc(0); status(5) <= state_enc(1); status(6) <= stream_en; status(7) <= fifo_empty; c2n_out <= not pulse; with sel select c2n_out_r <= c2n_out when "00", pulse when "10", '1' when others; c2n_out_w <= pulse when sel="01" else '1'; with state select state_enc <= "00" when idle, "01" when multi1, "01" when multi2, "01" when multi3, "10" when count_down, "11" when others; end gideon;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/usb/vhdl_source/ulpi_host.vhd	3	27625	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.usb_pkg.all; entity ulpi_host is port ( clock : in std_logic; reset : in std_logic; -- Descriptor RAM interface descr_addr : out std_logic_vector(8 downto 0); descr_rdata : in std_logic_vector(31 downto 0); descr_wdata : out std_logic_vector(31 downto 0); descr_en : out std_logic; descr_we : out std_logic; -- Buffer RAM interface buf_addr : out std_logic_vector(10 downto 0); buf_rdata : in std_logic_vector(7 downto 0); buf_wdata : out std_logic_vector(7 downto 0); buf_en : out std_logic; buf_we : out std_logic; -- Transmit Path Interface tx_busy : in std_logic; tx_ack : in std_logic; -- Interface to send tokens and handshakes send_token : out std_logic; send_handsh : out std_logic; tx_pid : out std_logic_vector(3 downto 0); tx_token : out std_logic_vector(10 downto 0); -- Interface to send data packets send_data : out std_logic; no_data : out std_logic; user_data : out std_logic_vector(7 downto 0); user_last : out std_logic; user_valid : out std_logic; user_next : in std_logic; -- Interface to bus initialization unit reset_done : in std_logic; sof_enable : in std_logic; scan_enable : in std_logic := '1'; speed : in std_logic_vector(1 downto 0); abort : in std_logic; -- Receive Path Interface rx_pid : in std_logic_vector(3 downto 0); rx_token : in std_logic_vector(10 downto 0); valid_token : in std_logic; valid_handsh : in std_logic; valid_packet : in std_logic; data_valid : in std_logic; data_start : in std_logic; data_out : in std_logic_vector(7 downto 0); rx_error : in std_logic ); end ulpi_host; architecture functional of ulpi_host is signal frame_div : integer range 0 to 65535; signal frame_cnt : unsigned(13 downto 0) := (others => '0'); signal do_sof : std_logic; constant c_max_transaction : integer := 31; constant c_max_pipe : integer := 31; constant c_timeout_val : integer := 7167; constant c_transaction_offset : unsigned(8 downto 6) := "001"; signal transaction_pntr : integer range 0 to c_max_transaction; signal descr_addr_i : unsigned(8 downto 0); -- could be temporarily pipe addr type t_state is (startup, idle, wait4start, scan_transactions, get_pipe, handle_trans, setup_token, bulk_token, send_data_packet, get_status, wait_for_ack, receive_data, send_ack, update_pipe, update_trans, do_ping ); signal state : t_state; signal substate : integer range 0 to 7; signal trans_in : t_transaction; signal pipe_in : t_pipe; signal trans_cnt : unsigned(10 downto 0); signal trans_len : unsigned(10 downto 0); signal buf_addr_i : unsigned(10 downto 0); -- signal speed : std_logic_vector(1 downto 0) := "11"; signal no_data_i : boolean; signal abort_reg : std_logic; signal tx_put : std_logic; signal tx_last : std_logic; signal need_ping : std_logic; signal fifo_data_in : std_logic_vector(7 downto 0); signal tx_almost_full : std_logic; signal link_busy : std_logic; signal timeout : boolean; signal timeout_cnt : integer range 0 to c_timeout_val; signal first_transfer : boolean; signal terminate : std_logic; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "sequential"; -- attribute keep : string; -- attribute keep of timeout : signal is "true"; signal debug_count : integer range 0 to 1023 := 0; signal debug_error : std_logic := '0'; begin descr_addr <= std_logic_vector(descr_addr_i); buf_addr <= std_logic_vector(buf_addr_i); no_data <= '1' when no_data_i else '0'; buf_wdata <= data_out; -- should be rx_data buf_we <= '1' when (state = receive_data) and (data_valid = '1') else '0'; p_protocol: process(clock) procedure next_transaction is begin if terminate='1' then terminate <= '0'; state <= idle; elsif transaction_pntr = c_max_transaction then transaction_pntr <= 0; state <= idle; -- wait for next sof before rescan else transaction_pntr <= transaction_pntr + 1; substate <= 0; state <= scan_transactions; end if; end procedure; function min(a, b: unsigned) return unsigned is begin if a < b then return a; else return b; end if; end function; variable trans_temp : t_transaction; variable len : unsigned(trans_temp.transfer_length'range); begin if rising_edge(clock) then descr_en <= '0'; descr_we <= '0'; tx_put <= '0'; if abort='1' then abort_reg <= '1'; end if; -- default counter if substate /= 3 then substate <= substate + 1; end if; if timeout_cnt /= 0 then timeout_cnt <= timeout_cnt - 1; if timeout_cnt = 1 then timeout <= false;--true; end if; end if; case state is when startup => tx_pid <= c_pid_reserved; do_sof <= '0'; frame_div <= 7499; if reset_done='1' then state <= idle; if speed = "10" then need_ping <= '1'; end if; end if; when idle => abort_reg <= '0'; if do_sof='1' then do_sof <= '0'; tx_token <= std_logic_vector(frame_cnt(13 downto 3)); tx_pid <= c_pid_sof; if speed = "00" then send_handsh <= '1'; else send_token <= '1'; end if; if speed(1)='1' then frame_cnt <= frame_cnt + 1; else frame_cnt <= frame_cnt + 8; end if; state <= wait4start; end if; when wait4start => if tx_ack='1' then send_token <= '0'; send_handsh <= '0'; send_data <= '0'; -- redundant - will not come here substate <= 0; if scan_enable='1' then state <= scan_transactions; else state <= idle; end if; end if; when scan_transactions => case substate is when 0 => descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr, descr_addr_i'length-c_transaction_offset'length); descr_en <= '1'; when 2 => trans_temp := data_to_t_transaction(descr_rdata); trans_in <= trans_temp; substate <= 0; if trans_temp.state = busy then state <= get_pipe; else -- go for next, unless we are at the end of the list next_transaction; end if; when others => null; end case; when get_pipe => case substate is when 0 => descr_addr_i <= (others => '0'); descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer; descr_en <= '1'; when 2 => pipe_in <= data_to_t_pipe(descr_rdata); first_transfer <= true; state <= handle_trans; --- when others => null; end case; when handle_trans => -- both pipe and transaction records are now valid abort_reg <= '0'; substate <= 0; if do_sof='1' and link_busy='0' then state <= idle; elsif pipe_in.state /= initialized then -- can we use the pipe? trans_in.state <= error; state <= update_trans; else -- yes we can timeout <= false; timeout_cnt <= c_timeout_val; link_busy <= trans_in.link_to_next; case trans_in.transaction_type is when control => -- a control out sequence exists of a setup token -- and then a data0 packet, which should be followed by -- an ack from the device. The next phase of the transaction -- could be either in or out, and defines whether it is a -- control read or a control write. -- By choice, control transfers are implemented using -- two transactions, which are executed in guaranteed -- sequence. -- In this way, each stage has its own buffer. -- Note, the first pipe should be of type OUT, although it is not -- checked. tx_pid <= c_pid_setup; tx_token <= pipe_in.device_endpoint & pipe_in.device_address; send_token <= '1'; state <= setup_token; when bulk \| interrupt => tx_token <= pipe_in.device_endpoint & pipe_in.device_address; state <= bulk_token; send_token <= '1'; timeout <= false; timeout_cnt <= c_timeout_val; if pipe_in.direction = dir_in then tx_pid <= c_pid_in; else -- if need_ping='1' then -- tx_pid <= c_pid_ping; -- state <= do_ping; -- else tx_pid <= c_pid_out; -- end if; end if; if pipe_in.control='1' and first_transfer then pipe_in.data_toggle <= '1'; -- start with data 1 end if; first_transfer <= false; when others => -- not yet supported trans_in.state <= error; state <= update_trans; end case; end if; when setup_token => if tx_ack='1' then send_token <= '0'; tx_pid <= c_pid_data0; -- send setup data immediately send_data <= '1'; buf_en <= '1'; substate <= 0; state <= send_data_packet; end if; -- prepare buffer buf_addr_i <= trans_in.buffer_address; trans_len <= trans_in.transfer_length; -- not cut up trans_cnt <= trans_in.transfer_length; -- not cut up no_data_i <= (trans_in.transfer_length = 0); when do_ping => if tx_ack='1' then send_token <= '0'; end if; -- wait for ack/nack or nyet. if rx_error='1' then trans_in.state <= error; state <= update_trans; elsif abort_reg='1' then pipe_in.state <= aborted; state <= update_pipe; abort_reg <= '0'; elsif valid_handsh='1' then -- maybe an ack? if rx_pid = c_pid_ack then tx_pid <= c_pid_out; send_token <= '1'; state <= bulk_token; elsif rx_pid = c_pid_stall then pipe_in.state <= stalled; trans_in.state <= error; state <= update_pipe; elsif (rx_pid = c_pid_nak) or (rx_pid = c_pid_nyet) then state <= handle_trans; end if; -- all other pids are just ignored elsif timeout then state <= handle_trans; end if; when bulk_token => if tx_ack='1' then send_token <= '0'; if pipe_in.direction = dir_out then if pipe_in.data_toggle = '0' then tx_pid <= c_pid_data0; else tx_pid <= c_pid_data1; end if; send_data <= '1'; buf_en <= '1'; substate <= 0; state <= send_data_packet; else -- input timeout <= false; timeout_cnt <= c_timeout_val; state <= receive_data; buf_en <= '1'; end if; end if; -- prepare buffer buf_addr_i <= trans_in.buffer_address; if pipe_in.direction = dir_out then len := min(trans_in.transfer_length, pipe_in.max_transfer); trans_len <= len; -- possibly cut up trans_cnt <= len; no_data_i <= (trans_in.transfer_length = 0); else trans_len <= (others => '0'); end if; when send_data_packet => case substate is when 0 => if tx_ack='1' then send_data <= '0'; if no_data_i then substate <= 2; end if; else substate <= 0; end if; when 1 => substate <= 1; -- stay! if tx_almost_full='0' then tx_put <= '1'; buf_addr_i <= buf_addr_i + 1; trans_cnt <= trans_cnt - 1; if trans_cnt = 1 then tx_last <= '1'; substate <= 2; buf_en <= '0'; else tx_last <= '0'; end if; end if; when 2 => if tx_busy='1' then substate <= 2; else state <= wait_for_ack; timeout <= false; timeout_cnt <= c_timeout_val; end if; when others => null; end case; when wait_for_ack => if rx_error='1' then trans_in.state <= error; state <= update_trans; elsif abort_reg='1' then pipe_in.state <= aborted; state <= update_pipe; abort_reg <= '0'; elsif valid_handsh='1' then -- maybe an ack? if (rx_pid = c_pid_ack) or (rx_pid = c_pid_nyet) then if rx_pid = c_pid_nyet then need_ping <= '1'; else need_ping <= '0'; end if; if trans_in.transfer_length = trans_len then trans_in.state <= done; if pipe_in.control='1' and trans_in.transaction_type = bulk then state <= get_status; substate <= 0; else state <= update_pipe; end if; else trans_in.state <= busy; state <= handle_trans; end if; trans_in.buffer_address <= buf_addr_i; -- store back trans_in.transfer_length <= trans_in.transfer_length - trans_len; pipe_in.data_toggle <= not pipe_in.data_toggle; elsif rx_pid = c_pid_stall then pipe_in.state <= stalled; trans_in.state <= error; state <= update_pipe; elsif rx_pid = c_pid_nak then terminate <= '0'; --link_busy; -- if control packet, then don't continue with next transaction! state <= update_trans; -- state <= handle_trans; -- just retry and retry, no matter what kind of packet it is, don't send SOF! end if; -- all other pids are just ignored -- elsif do_sof='1' then -- state <= idle; -- test elsif timeout then pipe_in.timeout <= '1'; trans_in.state <= error; state <= update_pipe; -- state <= handle_trans; -- try again end if; when get_status => case substate is when 0 => send_token <= '1'; tx_pid <= c_pid_in; when 1 => if tx_ack='1' then send_token <= '0'; timeout_cnt <= c_timeout_val; timeout <= false; else substate <= 1; -- wait end if; when 2 => if valid_packet='1' or valid_handsh='1' then state <= update_pipe; -- end transaction elsif rx_error='1' or timeout then trans_in.state <= error; state <= update_pipe; -- end transaction else substate <= 2; -- wait end if; when others => null; end case; when receive_data => if data_valid = '1' then timeout <= false; timeout_cnt <= 0; -- does not occur anymore buf_addr_i <= buf_addr_i + 1; trans_len <= trans_len + 1; end if; -------------------------------------------------------------------- if rx_error = '1' or debug_error='1' then -- go back to send the in token again buf_en <= '0'; state <= handle_trans; elsif abort_reg='1' then pipe_in.state <= aborted; state <= update_pipe; abort_reg <= '0'; elsif valid_packet='1' then buf_en <= '0'; trans_in.buffer_address <= buf_addr_i - 2; -- cut off CRC trans_in.transfer_length <= trans_in.transfer_length - (trans_len - 2); if ((trans_len - 2) >= trans_in.transfer_length) or ((trans_len - 2) < pipe_in.max_transfer) then trans_in.state <= done; else trans_in.state <= busy; end if; state <= send_ack; substate <= 0; elsif valid_handsh='1' then buf_en <= '0'; if rx_pid = c_pid_nak then if pipe_in.control='1' then state <= idle; -- retry on next sof, do not go to the next transaction else state <= update_trans; -- is not updated, but is the standard path to go to the next transact. end if; elsif rx_pid = c_pid_stall then trans_in.state <= error; pipe_in.state <= stalled; state <= update_pipe; end if; elsif timeout then -- device doesn't answer, could it have missed my in token? buf_en <= '0'; state <= handle_trans; end if; when send_ack => case substate is when 0 => send_handsh <= '1'; tx_pid <= c_pid_ack; when 1 => if tx_ack='0' then substate <= 1; -- stay here. else send_handsh <= '0'; state <= update_trans; -- if (pipe_in.control='0') and (trans_in.state = done) then -- state <= update_trans; -- elsif (pipe_in.control='1') and (trans_len = 2) then -- no data, thus status already received -- state <= update_trans; -- else -- null; -- -- substate <= 2; -- end if; end if; -- when 2 => -- send status back (no data packet) -- tx_pid <= c_pid_out; -- tx_token <= pipe_in.device_endpoint & pipe_in.device_address; -- send_token <= '1'; -- when 3 => -- wait until token was sent -- if tx_ack='0' then -- substate <= 3; -- else -- send_token <= '0'; -- no_data_i <= true; -- send_data <= '1'; -- tx_pid <= c_pid_data1; -- end if; -- when 4 => -- wait until no data packet was processed -- if tx_ack='0' then -- substate <= 4; -- else -- send_data <= '0'; -- state <= update_trans; -- end if; when others => null; end case; when update_pipe => descr_addr_i <= (others => '0'); descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer; descr_en <= '1'; descr_we <= '1'; descr_wdata <= t_pipe_to_data(pipe_in); state <= update_trans; when update_trans => descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr, descr_addr_i'length-c_transaction_offset'length); descr_wdata <= t_transaction_to_data(trans_in); descr_en <= '1'; descr_we <= '1'; next_transaction; when others => null; end case; --------------------------------------------------- -- DEBUG --------------------------------------------------- -- if state /= receive_data then -- debug_count <= 0; -- debug_error <= '0'; -- elsif debug_count = 1023 then -- debug_error <= '1'; -- else -- debug_count <= debug_count + 1; -- end if; --------------------------------------------------- if frame_div = 0 then do_sof <= sof_enable; if speed(1)='1' then frame_div <= 7499; -- microframes else frame_div <= 59999; -- 1 ms frames end if; else frame_div <= frame_div - 1; end if; if reset_done='0' then state <= startup; end if; if speed /= "10" then -- If not high speed, then we force no ping need_ping <= '0'; end if; if reset = '1' then abort_reg <= '0'; buf_en <= '0'; buf_addr_i <= (others => '0'); trans_len <= (others => '0'); trans_cnt <= (others => '0'); link_busy <= '0'; state <= startup; do_sof <= '0'; frame_div <= 7499; frame_cnt <= (others => '0'); send_token <= '0'; send_data <= '0'; send_handsh <= '0'; need_ping <= '0'; terminate <= '0'; end if; end if; end process; -- Decoupling of ulpi tx bus and our generation of data -- to meet timing of "next" signal -- fifo_data_in <= reset_data when (state = startup) else buf_rdata; fifo_data_in <= buf_rdata; i_srl_tx: entity work.srl_fifo generic map ( Width => 9, Depth => 15, Threshold => 10 ) port map ( clock => clock, reset => reset, GetElement => user_next, PutElement => tx_put, FlushFifo => '0', DataIn(7 downto 0) => fifo_data_in, DataIn(8) => tx_last, DataOut(7 downto 0) => user_data, DataOut(8) => user_last, SpaceInFifo => open, AlmostFull => tx_almost_full, DataInFifo => user_valid ); end functional;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/usb/vhdl_source/token_crc.vhd	3	1863	------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2004, Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : token_crc.vhd ------------------------------------------------------------------------------- -- File : token_crc.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This file is used to calculate the CRC over a USB token ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity token_crc is port ( clock : in std_logic; sync : in std_logic; token_in : in std_logic_vector(10 downto 0); crc : out std_logic_vector(4 downto 0) ); end token_crc; architecture Gideon of token_crc is -- signal crc_reg : std_logic_vector(4 downto 0) := (others => '0'); constant polynom : std_logic_vector(4 downto 0) := "00100"; -- CRC-5 = x5 + x2 + 1 begin process(clock) variable tmp : std_logic_vector(crc'range); variable d : std_logic; begin if rising_edge(clock) then tmp := (others => '1'); for i in token_in'reverse_range loop -- LSB first! d := token_in(i) xor tmp(tmp'high); tmp := tmp(tmp'high-1 downto 0) & d; --'0'; if d = '1' then tmp := tmp xor polynom; end if; end loop; for i in tmp'range loop -- reverse and invert crc(crc'high-i) <= not(tmp(i)); end loop; end if; end process; end Gideon;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/nano_cpu/vhdl_source/nano.vhd	3	6323	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.nano_cpu_pkg.all; use work.io_bus_pkg.all; library unisim; use unisim.vcomponents.all; entity nano is port ( clock : in std_logic; reset : in std_logic; -- i/o interface io_addr : out unsigned(7 downto 0); io_write : out std_logic; io_read : out std_logic; io_wdata : out std_logic_vector(15 downto 0); io_rdata : in std_logic_vector(15 downto 0); stall : in std_logic; -- system interface (to write code into the nano) sys_clock : in std_logic := '0'; sys_reset : in std_logic := '0'; sys_io_req : in t_io_req := c_io_req_init; sys_io_resp : out t_io_resp ); end entity; architecture structural of nano is signal sys_enable : std_logic; -- instruction/data ram signal ram_addr : std_logic_vector(9 downto 0); signal ram_en : std_logic; signal ram_we : std_logic; signal ram_wdata : std_logic_vector(15 downto 0); signal ram_rdata : std_logic_vector(15 downto 0); signal sys_io_req_bram : t_io_req; signal sys_io_resp_bram : t_io_resp; signal sys_io_req_regs : t_io_req; signal sys_io_resp_regs : t_io_resp; signal sys_core_reset : std_logic; signal usb_reset_tig : std_logic; signal usb_core_reset : std_logic; signal bram_reset : std_logic; signal bram_data : std_logic_vector(7 downto 0); begin i_split: entity work.io_bus_splitter generic map ( g_range_lo => 12, g_range_hi => 12, g_ports => 2 ) port map ( clock => sys_clock, req => sys_io_req, resp => sys_io_resp, reqs(0) => sys_io_req_bram, -- 4080000 reqs(1) => sys_io_req_regs, -- 4081000 resps(0) => sys_io_resp_bram, resps(1) => sys_io_resp_regs ); i_core: entity work.nano_cpu port map ( clock => clock, reset => usb_core_reset, -- instruction/data ram ram_addr => ram_addr, ram_en => ram_en, ram_we => ram_we, ram_wdata => ram_wdata, ram_rdata => ram_rdata, -- i/o interface io_addr => io_addr, io_write => io_write, io_read => io_read, io_wdata => io_wdata, io_rdata => io_rdata, stall => stall ); i_buf_ram: RAMB16_S9_S18 generic map ( INIT_00 => X"096CE011A0CA095CC00F29596893E8210968C00F295C6893E93FA0CA0963E947", INIT_01 => X"E9340964E05CE9340894E9340965E8DAC01E295A6832E821089AA0C40974A0CA", INIT_02 => X"D0356824B800A027D82A6827B800C822809559580895A02FD822682F8095E020", INIT_03 => X"E02AA011A0000959B8000957E033A020D83A6820A024B8000958E850D82E682F", INIT_04 => X"C856295D808E4958088EE05051590894A02FD856682FE02AA010A001088FA000", INIT_05 => X"0BF2C0840BF0E845B800E9340966A02DD85B682DE82AA010A000095BA0016860", INIT_06 => X"0BF4E082C079516BC074516AC06F51690BF0808F0BF183F50957A0700BF3A071", INIT_07 => X"D87E687483F5A0726833811FE8C4E082E934E8A0E8850BF4E082E934E89CE885", INIT_08 => X"00000000B800A050B800D8896874A040A073C08C8090E05C83F00957E934091F", INIT_09 => X"E0A6095AE8400962004B15E00050004000450046000000000000000000000008", INIT_0A => X"C0BE6822C8BEE82EE82AA012A00259580890A000E0A6195A295E0891E8400958", INIT_0B => X"49580892B8000958C8BE5163B8000959C8BA5160B800095AC8B651596830A022", INIT_0C => X"C8D85161E0D20957E83CC8CE515A0830C8D9E82EE840095FE0B8C0BC515A8092", INIT_0D => X"8094095AC0E1515E296F6832E0BEE0B6B8000959B800095AC8D65093095EE83C", INIT_0E => X"0894A02EA01E80950976A0C4097280940958E0E980940957C0E729596832B800", INIT_0F => X"B800A0C48900810049670894C8F1809559580895A02FD8F1682FD101682EC117", INIT_10 => X"A055C114809559580895C90959580975A0458095089BA018A045809409590000", INIT_11 => X"0000E0FAC917809559580895A02FD917682F8095095AA019E107C91159580975", INIT_12 => X"0BFDB800894683FE297149580BFE8146496D0BFEB800C926E920B8003BFE0BFF", INIT_13 => X"0957B80083FD297749580BFD91460945814649700BFD8145B8003BFC29774958", INIT_14 => X"0969A07183F30973A07083F2096E83F4096200000000B80083FF83FE83FD83FC", INIT_15 => X"000900080007000600050003000200010000B800A0720963809B809A095B83F0", INIT_16 => X"0038123403B000260023002200210FA00096001300120011000E000D000B000A", INIT_17 => X"00000000000000000000000000000000007F007802EE006156780050003F0330", INIT_3F => X"FF00000000000000000000000000000000000000000000000000000000000000" ) port map ( CLKB => clock, SSRB => reset, ENB => ram_en, WEB => ram_we, ADDRB => ram_addr, DIB => ram_wdata, DIPB => "00", DOB => ram_rdata, CLKA => sys_clock, SSRA => sys_reset, ENA => sys_enable, WEA => sys_io_req_bram.write, ADDRA => std_logic_vector(sys_io_req_bram.address(10 downto 0)), DIA => sys_io_req_bram.data, DIPA => "0", DOA => bram_data ); sys_enable <= sys_io_req_bram.write or sys_io_req_bram.read; bram_reset <= not sys_enable; sys_io_resp_bram.data <= bram_data when sys_io_resp_bram.ack = '1' else X"00"; process(sys_clock) begin if rising_edge(sys_clock) then sys_io_resp_bram.ack <= sys_enable; sys_io_resp_regs <= c_io_resp_init; sys_io_resp_regs.ack <= sys_io_req_regs.write or sys_io_req_regs.read; if sys_io_req_regs.write = '1' then -- any address sys_core_reset <= not sys_io_req_regs.data(0); end if; if sys_reset = '1' then sys_core_reset <= '1'; end if; end if; end process; process(clock) begin if rising_edge(clock) then usb_reset_tig <= sys_core_reset; usb_core_reset <= usb_reset_tig; end if; end process; end architecture;	gpl-3.0
davidhorrocks/1541UltimateII	target/simulation/vhdl_bfm/bram_model_8sp.vhd	5	2053	------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : BRAM model ------------------------------------------------------------------------------- -- File : bram_model_8sp.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This simple BRAM model uses the flat memory model package. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.tl_flat_memory_model_pkg.all; entity bram_model_8sp is generic ( g_given_name : string; g_depth : positive := 18 ); port ( CLK : in std_logic; SSR : in std_logic; EN : in std_logic; WE : in std_logic; ADDR : in std_logic_vector(g_depth-1 downto 0); DI : in std_logic_vector(7 downto 0); DO : out std_logic_vector(7 downto 0) ); end bram_model_8sp; architecture bfm of bram_model_8sp is shared variable this : h_mem_object; signal bound : boolean := false; begin bind: process begin register_mem_model(bram_model_8sp'path_name, g_given_name, this); bound <= true; wait; end process; process(CLK) variable vaddr : std_logic_vector(31 downto 0) := (others => '0'); begin if rising_edge(CLK) then vaddr(g_depth-1 downto 0) := ADDR; if EN='1' then if bound then DO <= read_memory_8(this, vaddr); if WE='1' then write_memory_8(this, vaddr, DI); end if; end if; end if; if SSR='1' then DO <= (others => '0'); end if; end if; end process; end bfm;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/usb2/vhdl_source/usb_io_bank.vhd	5	8681	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity usb_io_bank is port ( clock : in std_logic; reset : in std_logic; -- i/o interface io_addr : in unsigned(7 downto 0); io_write : in std_logic; io_read : in std_logic; io_wdata : in std_logic_vector(15 downto 0); io_rdata : out std_logic_vector(15 downto 0); stall : out std_logic; -- Memory controller and buffer mem_ready : in std_logic; transferred : in unsigned(10 downto 0); -- Register access reg_read : out std_logic := '0'; reg_write : out std_logic := '0'; reg_ack : in std_logic; reg_addr : out std_logic_vector(5 downto 0) := (others => '0'); reg_wdata : out std_logic_vector(7 downto 0) := X"00"; reg_rdata : in std_logic_vector(7 downto 0); status : in std_logic_vector(7 downto 0); -- I/O pins from RX rx_pid : in std_logic_vector(3 downto 0); rx_token : in std_logic_vector(10 downto 0); rx_valid_token : in std_logic; rx_valid_handsh : in std_logic; rx_valid_packet : in std_logic; rx_error : in std_logic; -- I/O pins to TX tx_pid : out std_logic_vector(3 downto 0); tx_token : out std_logic_vector(10 downto 0); tx_send_token : out std_logic; tx_send_handsh : out std_logic; tx_send_data : out std_logic; tx_length : out unsigned(10 downto 0); tx_no_data : out std_logic; tx_chirp_enable : out std_logic; tx_chirp_level : out std_logic; tx_chirp_end : out std_logic; tx_chirp_start : out std_logic; tx_ack : in std_logic ); end entity; architecture gideon of usb_io_bank is signal pulse_in : std_logic_vector(15 downto 0) := (others => '0'); signal pulse_out : std_logic_vector(15 downto 0) := (others => '0'); signal latched : std_logic_vector(15 downto 0) := (others => '0'); signal level_out : std_logic_vector(15 downto 0) := (others => '0'); signal frame_div : integer range 0 to 65535; signal frame_cnt : unsigned(13 downto 0) := (others => '0'); signal stall_i : std_logic := '0'; signal ulpi_access : std_logic; signal tx_chirp_start_i : std_logic; signal tx_chirp_end_i : std_logic; signal filter_cnt : unsigned(7 downto 0); signal filter_st1 : std_logic; signal reset_filter : std_logic; begin pulse_in(0) <= rx_error; pulse_in(1) <= rx_valid_token; pulse_in(2) <= rx_valid_handsh; pulse_in(3) <= rx_valid_packet; pulse_in(4) <= rx_valid_packet or rx_valid_handsh or rx_valid_token or rx_error; pulse_in(7) <= tx_ack; -- tx ack resets lower half of output pulses tx_no_data <= level_out(0); tx_send_token <= pulse_out(0); tx_send_handsh <= pulse_out(1); tx_send_data <= pulse_out(2); tx_chirp_level <= level_out(5); tx_chirp_start <= tx_chirp_start_i; tx_chirp_end <= tx_chirp_end_i; tx_chirp_start_i <= pulse_out(8); tx_chirp_end_i <= pulse_out(9); reset_filter <= pulse_out(14); pulse_in(14) <= filter_st1; pulse_in(13) <= '1' when (status(5 downto 4) = "10") else '0'; process(clock) variable adlo : unsigned(3 downto 0); variable adhi : unsigned(7 downto 4); begin if rising_edge(clock) then adlo := io_addr(3 downto 0); adhi := io_addr(7 downto 4); if tx_ack = '1' then pulse_out(7 downto 0) <= (others => '0'); end if; pulse_out(15 downto 8) <= X"00"; pulse_in(15) <= '0'; if frame_div = 0 then frame_div <= 7499; -- microframes pulse_in(15) <= '1'; frame_cnt <= frame_cnt + 1; else frame_div <= frame_div - 1; end if; if tx_chirp_start_i = '1' then tx_chirp_enable <= '1'; elsif tx_chirp_end_i = '1' then tx_chirp_enable <= '0'; end if; filter_st1 <= '0'; if reset_filter = '1' then filter_cnt <= (others => '0'); elsif status(1) = '0' then filter_cnt <= (others => '0'); else filter_cnt <= filter_cnt + 1; if filter_cnt = 255 and latched(14)='0' then filter_st1 <= '1'; end if; end if; if reg_ack='1' then reg_write <= '0'; reg_read <= '0'; stall_i <= '0'; end if; if io_write='1' then reg_addr <= std_logic_vector(io_addr(5 downto 0)); case adhi is when X"0" => case adlo(3 downto 0) is when X"0" => tx_pid <= io_wdata(tx_pid'range); when X"1" => tx_token <= io_wdata(tx_token'range); when X"2" => tx_length <= unsigned(io_wdata(tx_length'range)); when others => null; end case; when X"1" => pulse_out(to_integer(adlo)) <= '1'; when X"2" => latched(to_integer(adlo)) <= '0'; when X"4" => level_out(to_integer(adlo)) <= '0'; when X"5" => level_out(to_integer(adlo)) <= '1'; when X"C"\|X"D"\|X"E"\|X"F" => reg_wdata <= io_wdata(7 downto 0); reg_write <= '1'; stall_i <= '1'; when others => null; end case; end if; if io_read = '1' then reg_addr <= std_logic_vector(io_addr(5 downto 0)); if io_addr(7 downto 6) = "10" then reg_read <= '1'; stall_i <= '1'; end if; end if; for i in latched'range loop if pulse_in(i)='1' then latched(i) <= '1'; end if; end loop; if reset='1' then tx_pid <= (others => '0'); tx_token <= (others => '0'); tx_length <= (others => '0'); latched <= (others => '0'); level_out <= (others => '0'); reg_read <= '0'; reg_write <= '0'; stall_i <= '0'; tx_chirp_enable <= '0'; end if; end if; end process; ulpi_access <= io_addr(7); stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned process(latched, level_out, rx_pid, rx_token, reg_rdata, io_addr) variable adlo : unsigned(3 downto 0); variable adhi : unsigned(7 downto 4); begin io_rdata <= (others => '0'); adlo := io_addr(3 downto 0); adhi := io_addr(7 downto 4); case adhi is when X"2" => io_rdata(15) <= latched(to_integer(adlo)); when X"3" => case adlo(3 downto 0) is when X"0" => io_rdata <= X"000" & rx_pid; when X"1" => io_rdata <= "00000" & rx_token; when X"2" => io_rdata <= X"00" & status; when X"3" => io_rdata <= "00000" & std_logic_vector(transferred); when others => null; end case; when X"6" => case adlo(3 downto 0) is when X"0" => io_rdata <= "00000" & std_logic_vector(frame_cnt(13 downto 3)); when others => null; end case; when X"7" => io_rdata(15) <= mem_ready; when X"8"\|X"9"\|X"A"\|X"B" => io_rdata <= X"00" & reg_rdata; when others => null; end case; end process; end architecture;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/video/vhdl_source/char_generator_regs.vhd	4	4411	------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010, Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Character Generator Registers ------------------------------------------------------------------------------- -- File : char_generator_regs.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: Registers for the character generator ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; use work.char_generator_pkg.all; entity char_generator_regs is port ( clock : in std_logic; reset : in std_logic; io_req : in t_io_req; io_resp : out t_io_resp; keyb_row : in std_logic_vector(7 downto 0); keyb_col : inout std_logic_vector(7 downto 0); control : out t_chargen_control ); end entity; architecture gideon of char_generator_regs is signal control_i : t_chargen_control := c_chargen_control_init; begin process(clock) begin if rising_edge(clock) then io_resp <= c_io_resp_init; if io_req.write='1' then io_resp.ack <= '1'; case io_req.address(3 downto 0) is when c_chargen_line_clocks_hi => control_i.clocks_per_line(10 downto 8) <= unsigned(io_req.data(2 downto 0)); when c_chargen_line_clocks_lo => control_i.clocks_per_line(7 downto 0) <= unsigned(io_req.data); when c_chargen_char_width => control_i.char_width <= unsigned(io_req.data(2 downto 0)); when c_chargen_char_height => control_i.char_height <= unsigned(io_req.data(3 downto 0)); when c_chargen_chars_per_line => control_i.chars_per_line <= unsigned(io_req.data); when c_chargen_active_lines => control_i.active_lines <= unsigned(io_req.data(5 downto 0)); when c_chargen_x_on_hi => control_i.x_on(11 downto 8) <= unsigned(io_req.data(3 downto 0)); when c_chargen_x_on_lo => control_i.x_on(7 downto 0) <= unsigned(io_req.data); when c_chargen_y_on_hi => control_i.y_on(11 downto 8) <= unsigned(io_req.data(3 downto 0)); when c_chargen_y_on_lo => control_i.y_on(7 downto 0) <= unsigned(io_req.data); when c_chargen_pointer_hi => control_i.pointer(14 downto 8) <= unsigned(io_req.data(6 downto 0)); when c_chargen_pointer_lo => control_i.pointer(7 downto 0) <= unsigned(io_req.data); when c_chargen_perform_sync => control_i.perform_sync <= io_req.data(0); when c_chargen_transparency => control_i.transparent <= io_req.data(3 downto 0); control_i.overlay_on <= io_req.data(7); when c_chargen_keyb_col => keyb_col <= io_req.data; when others => null; end case; elsif io_req.read='1' then io_resp.ack <= '1'; case io_req.address(3 downto 0) is when c_chargen_keyb_row => io_resp.data <= keyb_row; when c_chargen_keyb_col => io_resp.data <= keyb_col; when others => null; end case; end if; if reset='1' then control_i <= c_chargen_control_init; keyb_col <= (others => '1'); end if; end if; end process; control <= control_i; end gideon;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v2_mk1.vhd	5	10827	library work; use work.tl_flat_memory_model_pkg.all; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity harness_v2_mk1 is end harness_v2_mk1; architecture tb of harness_v2_mk1 is constant c_uart_divisor : natural := 434; signal PHI2 : std_logic := '0'; signal RSTn : std_logic := '1'; signal DOTCLK : std_logic := '1'; signal BUFFER_ENn : std_logic := '1'; signal LB_ADDR : std_logic_vector(21 downto 0); signal LB_DATA : std_logic_vector(7 downto 0) := X"00"; signal BA : std_logic := '0'; signal DMAn : std_logic := '1'; signal EXROMn : std_logic; signal GAMEn : std_logic; signal ROMHn : std_logic := '1'; signal ROMLn : std_logic := '1'; signal IO1n : std_logic := '1'; signal IO2n : std_logic := '1'; signal IRQn : std_logic := '1'; signal NMIn : std_logic := '1'; signal MEM_WEn : std_logic; signal MEM_OEn : std_logic; signal SDRAM_CSn : std_logic; signal SDRAM_RASn : std_logic; signal SDRAM_CASn : std_logic; signal SDRAM_WEn : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CLK : std_logic; signal SDRAM_DQM : std_logic; signal PWM_OUT : std_logic_vector(1 downto 0); signal IEC_ATN : std_logic := '1'; signal IEC_DATA : std_logic := '1'; signal IEC_CLOCK : std_logic := '1'; signal IEC_RESET : std_logic := '1'; signal IEC_SRQ_IN : std_logic := '1'; signal DISK_ACTn : std_logic; -- activity LED signal CART_LEDn : std_logic; signal SDACT_LEDn : std_logic; signal MOTOR_LEDn : std_logic; signal UART_TXD : std_logic; signal UART_RXD : std_logic := '1'; signal SD_SSn : std_logic; signal SD_CLK : std_logic; signal SD_MOSI : std_logic; signal SD_MISO : std_logic := '1'; signal SD_WP : std_logic := '1'; signal SD_CARDDETn : std_logic := '1'; signal BUTTON : std_logic_vector(2 downto 0) := "111"; signal SLOT_ADDR : std_logic_vector(15 downto 0); signal SLOT_DATA : std_logic_vector(7 downto 0); signal RWn : std_logic := '1'; signal CAS_MOTOR : std_logic := '1'; signal CAS_SENSE : std_logic := '0'; signal CAS_READ : std_logic := '0'; signal CAS_WRITE : std_logic := '0'; signal ETH_CLK : std_logic; signal ETH_RST : std_logic; signal ETH_CSn : std_logic; signal ETH_CS : std_logic; signal FLASH_CSn : std_logic; signal SRAM_CSn : std_logic; signal ONE_WIRE : std_logic := 'H'; signal sys_clock : std_logic := '0'; signal sys_reset : std_logic := '0'; signal rx_char : std_logic_vector(7 downto 0); signal rx_char_d : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal tx_char : std_logic_vector(7 downto 0) := X"00"; signal tx_done : std_logic; signal do_tx : std_logic := '0'; shared variable dram : h_mem_object; shared variable ram : h_mem_object; shared variable sram : h_mem_object; -- shared variable bram : h_mem_object; begin mut: entity work.ultimate_1541_250e generic map ( g_simulation => true ) port map ( CLOCK => sys_clock, PHI2 => PHI2, DOTCLK => DOTCLK, RSTn => RSTn, BUFFER_ENn => BUFFER_ENn, SLOT_ADDR => SLOT_ADDR, SLOT_DATA => SLOT_DATA, RWn => RWn, BA => BA, DMAn => DMAn, EXROMn => EXROMn, GAMEn => GAMEn, ROMHn => ROMHn, ROMLn => ROMLn, IO1n => IO1n, IO2n => IO2n, IRQn => IRQn, NMIn => NMIn, LB_ADDR => LB_ADDR, LB_DATA => LB_DATA, FLASH_CSn => FLASH_CSn, SRAM_CSn => SRAM_CSn, MEM_WEn => MEM_WEn, MEM_OEn => MEM_OEn, SDRAM_CSn => SDRAM_CSn, SDRAM_RASn => SDRAM_RASn, SDRAM_CASn => SDRAM_CASn, SDRAM_WEn => SDRAM_WEn, SDRAM_CKE => SDRAM_CKE, SDRAM_CLK => SDRAM_CLK, SDRAM_DQM => SDRAM_DQM, -- PWM outputs (for audio) PWM_OUT => PWM_OUT, -- IEC bus IEC_ATN => IEC_ATN, IEC_DATA => IEC_DATA, IEC_CLOCK => IEC_CLOCK, IEC_RESET => IEC_RESET, IEC_SRQ_IN => IEC_SRQ_IN, DISK_ACTn => DISK_ACTn, -- activity LED CART_LEDn => CART_LEDn, SDACT_LEDn => SDACT_LEDn, MOTOR_LEDn => MOTOR_LEDn, -- Debug UART UART_TXD => UART_TXD, UART_RXD => UART_RXD, -- USB USB_IOP => open, USB_ION => open, USB_SEP => '1', USB_SEN => '0', USB_DET => open, -- SD Card Interface SD_SSn => SD_SSn, SD_CLK => SD_CLK, SD_MOSI => SD_MOSI, SD_MISO => SD_MISO, SD_WP => '0', SD_CARDDETn => SD_CARDDETn, -- Cassette Interface CAS_MOTOR => CAS_MOTOR, CAS_SENSE => CAS_SENSE, CAS_READ => CAS_READ, CAS_WRITE => CAS_WRITE, -- Ethernet Interface ETH_CLK => ETH_CLK, ETH_IRQ => '0', ETH_CSn => ETH_CSn, ETH_CS => ETH_CS, ETH_RST => ETH_RST, ONE_WIRE => ONE_WIRE, -- Buttons BUTTON => BUTTON ); sys_clock <= not sys_clock after 10 ns; -- 50 MHz sys_reset <= '1', '0' after 100 ns; PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz RSTn <= '0', '1' after 6 us; process begin bind_mem_model("intram", ram); bind_mem_model("dram", dram); bind_mem_model("sram", sram); load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000"); load_memory("../../software/ultimate/result/ultimate_V1.bin", sram, X"00030000"); wait; end process; SLOT_DATA <= (others => 'H'); ROMHn <= '1'; ROMLn <= not PHI2 after 50 ns; IO1n <= '1'; IO2n <= '1'; process begin SLOT_ADDR <= X"7FF0"; RWn <= '1'; while true loop wait until PHI2 = '0'; --SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1); SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1); RWn <= '1'; wait until PHI2 = '0'; RWn <= '0'; end loop; end process; process begin BA <= '1'; for i in 0 to 100 loop wait until PHI2='0'; end loop; BA <= '0'; for i in 0 to 10 loop wait until PHI2='0'; end loop; end process; sram_bfm: entity work.sram_model_8 generic map("sram", 19, 10 ns) port map (LB_ADDR(18 downto 0), LB_DATA, SRAM_CSn, MEM_OEn, MEM_WEn); flash_bfm: entity work.sram_model_8 generic map("flash", 21, 70 ns) port map (LB_ADDR(20 downto 0), LB_DATA, FLASH_CSn, MEM_OEn, '1'); dram_bfm: entity work.dram_model_8 generic map( g_given_name => "dram", g_cas_latency => 2, g_burst_len_r => 1, g_burst_len_w => 1, g_column_bits => 10, g_row_bits => 13, g_bank_bits => 2 ) port map ( CLK => SDRAM_CLK, CKE => SDRAM_CKE, A => LB_ADDR(12 downto 0), BA => LB_ADDR(14 downto 13), CSn => SDRAM_CSn, RASn => SDRAM_RASn, CASn => SDRAM_CASn, WEn => SDRAM_WEn, DQM => SDRAM_DQM, DQ => LB_DATA); -- assert not (ADDRESS(18 downto 16)="011" and ADDRESS(15 downto 0)=X"86A0" and SRAM_CSn='0' and MEM_WEn='0') -- report "writing to jump address." -- severity failure; -- sram: entity work.sram_model_8 -- generic map("sram", 19, 10 ns) -- port map (LB_ADDR(18 downto 0), LB_DATA, SRAM_CSn, MEM_OEn, MEM_WEn); -- -- flash: entity work.sram_model_8 -- generic map("flash", 21, 70 ns) -- port map (LB_ADDR(20 downto 0), LB_DATA, FLASH_CSn, MEM_OEn, '1'); -- process(ETH_CS, ETH_CSn, LB_ADDR) -- begin -- if ETH_CS='1' and ETH_CSn='0' then -- LB_DATA <= not LB_ADDR(7 downto 0) after 135 ns; -- else -- LB_DATA <= (others => 'Z') after 50 ns; -- end if; -- end process; i_rx: entity work.rx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, rxd => UART_TXD, rxchar => rx_char, rx_ack => rx_ack ); i_tx: entity work.tx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, dotx => do_tx, txchar => tx_char, done => tx_done, txd => UART_RXD ); process(sys_clock) begin if rising_edge(sys_clock) then if rx_ack='1' then rx_char_d <= rx_char; end if; end if; end process; process procedure send_char(i: std_logic_vector(7 downto 0)) is begin if tx_done /= '1' then wait until tx_done = '1'; end if; wait until sys_clock='1'; tx_char <= i; do_tx <= '1'; wait until tx_done = '0'; wait until sys_clock='1'; do_tx <= '0'; end procedure; procedure send_string(i : string) is variable b : std_logic_vector(7 downto 0); begin for n in i'range loop b := std_logic_vector(to_unsigned(character'pos(i(n)), 8)); send_char(b); end loop; send_char(X"0d"); send_char(X"0a"); end procedure; begin wait for 2 ms; --send_string("wd 4005000 12345678"); send_string("run"); -- send_string("m 100000"); -- send_string("w 400000F 4"); wait; end process; -- check timing data process(PHI2) begin if falling_edge(PHI2) then assert SLOT_DATA'last_event >= 189 ns report "Timing error on C64 bus." severity error; end if; end process; end tb;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/ip/srl_fifo/vhdl_source/srl_fifo.vhd	3	3787	------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2004, Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Small Synchronous Fifo Using SRL16 ------------------------------------------------------------------------------- -- File : srl_fifo.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This implementation makes use of the SRL16 properties, -- implementing a 16-deep synchronous fifo in only one LUT per -- bit. It is a fall-through fifo. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity srl_fifo is generic (Width : integer := 32; Depth : integer := 15; -- 15 is the maximum Threshold : integer := 13); port ( clock : in std_logic; reset : in std_logic; GetElement : in std_logic; PutElement : in std_logic; FlushFifo : in std_logic; DataIn : in std_logic_vector(Width-1 downto 0); DataOut : out std_logic_vector(Width-1 downto 0); SpaceInFifo : out std_logic; AlmostFull : out std_logic; DataInFifo : out std_logic); end SRL_fifo; architecture Gideon of srl_fifo is signal NumElements : std_logic_vector(3 downto 0); signal FilteredGet : std_logic; signal FilteredPut : std_logic; signal DataInFifo_i : std_logic; signal SpaceInFifo_i : std_logic; constant Depth_std : std_logic_vector(3 downto 0) := conv_std_logic_vector(Depth-1, 4); begin FilteredGet <= DataInFifo_i and GetElement; FilteredPut <= SpaceInFifo_i and PutElement; DataInFifo <= DataInFifo_i; SpaceInFifo <= SpaceInFifo_i; process(clock) variable NewCnt : std_logic_vector(3 downto 0);--integer range 0 to Depth; begin if rising_edge(clock) then if FlushFifo='1' then NewCnt := "1111"; --0; elsif (FilteredGet='1') and (FilteredPut='0') then NewCnt := NumElements - 1; elsif (FilteredGet='0') and (FilteredPut='1') then NewCnt := NumElements + 1; else NewCnt := NumElements; end if; NumElements <= NewCnt; if (NewCnt > Threshold) and (NewCnt /= "1111") then AlmostFull <= '1'; else AlmostFull <= '0'; end if; if (NewCnt = "1111") then DataInFifo_i <= '0'; else DataInFifo_i <= '1'; end if; if (NewCnt /= Depth_std) then SpaceInFifo_i <= '1'; else SpaceInFifo_i <= '0'; end if; if Reset='1' then NumElements <= "1111"; SpaceInFifo_i <= '1'; DataInFifo_i <= '0'; AlmostFull <= '0'; end if; end if; end process; SRLs : for srl2 in 0 to Width-1 generate i_SRL : SRL16E port map ( CLK => clock, CE => FilteredPut, D => DataIn(srl2), A3 => NumElements(3), A2 => NumElements(2), A1 => NumElements(1), A0 => NumElements(0), Q => DataOut(srl2) ); end generate; end Gideon;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/zpu/vhdl_source/zpu_8bit_loadb.vhd	5	33125	------------------------------------------------------------------------------ ---- ---- ---- ZPU 8-bit version ---- ---- ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Description: ---- ---- ZPU is a 32 bits small stack cpu. This is a modified version of ---- ---- the zpu_small implementation. This one has only one 8-bit external ---- ---- memory port, which is used for I/O, instruction fetch and data ---- ---- accesses. It is intended to interface with existing 8-bit systems, ---- ---- while maintaining the large addressing range and 32-bit programming ---- ---- model. The 32-bit stack remains "internal" in the ZPU. ---- ---- ---- ---- This version is about the same size as zpu_small from zealot, ---- ---- but performs 25% better at the same clock speed, given that the ---- ---- external memory bus can operate with 0 wait states. The performance ---- ---- increase is due to the fact that most instructions only require 3 ---- ---- clock cycles instead of 4. ---- ---- ---- ---- Author: ---- ---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ---- ---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ---- ---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- ---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- ---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ---- ---- ---- ---- Distributed under the BSD license ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Design unit: zpu_8bit_loadb(Behave) (Entity and architecture) ---- ---- File name: zpu_8bit_loadb.vhdl ---- ---- Note: None ---- ---- Limitations: None known ---- ---- Errors: None known ---- ---- Library: work ---- ---- Dependencies: ieee.std_logic_1164 ---- ---- ieee.numeric_std ---- ---- work.zpupkg ---- ---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ---- ---- Language: VHDL ---- ---- Wishbone: No ---- ---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ---- ---- Simulation tools: Modelsim ---- ---- Text editor: UltraEdit 11.00a+ ---- ---- ---- ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.zpupkg.all; --use work.tl_string_util_pkg.all; entity zpu_8bit_loadb is generic( g_addr_size : integer := 16; -- Total address space width (incl. I/O) g_stack_size : integer := 12; -- Memory (stack+data) width g_prog_size : integer := 14; -- Program size g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0' port( clk_i : in std_logic; -- System Clock reset_i : in std_logic; -- Synchronous Reset interrupt_i : in std_logic; -- Interrupt break_o : out std_logic; -- Breakpoint opcode executed -- synthesis translate_off dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) -- synthesis translate_on -- BRAM (stack ONLY) a_en_o : out std_logic; a_we_o : out std_logic; -- BRAM A port Write Enable a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port a_i : in unsigned(31 downto 0); -- Data from BRAM A port b_en_o : out std_logic; b_we_o : out std_logic; -- BRAM B port Write Enable b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port b_i : in unsigned(31 downto 0); -- Data from BRAM B port -- memory port for text, bss, data c_req_o : out std_logic; -- request output c_inst_o : out std_logic; -- indicates request is for opcode (program data) c_we_o : out std_logic; -- write c_size_o : out std_logic_vector(1 downto 0); -- indicates size of transfer 00=byte, 11=dword c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0'); c_rack_i : in std_logic; -- request acknowledge c_dack_i : in std_logic; -- data acknowledge (read only) c_data_i : in std_logic_vector(c_opcode_width-1 downto 0); c_data_o : out std_logic_vector(c_opcode_width-1 downto 0) ); end entity zpu_8bit_loadb; architecture Behave of zpu_8bit_loadb is constant c_max_addr_bit : integer:=g_addr_size-1; -- Stack Pointer initial value: BRAM size-8 constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2*g_stack_size)-8, g_addr_size); constant c_sp_start : unsigned(g_stack_size-1 downto 2):= c_sp_start_1(g_stack_size-1 downto 2); -- Program counter signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0'); -- Stack pointer signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start; signal idim_r : std_logic:='0'; -- BRAM (stack) -- a_r is a register for the top of the stack [SP] -- Note: as this is a stack CPU this is a very important register. signal a_we_r : std_logic:='0'; signal a_en_r : std_logic:='0'; signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal a_r : unsigned(31 downto 0):=(others => '0'); -- b_r is a register for the next value in the stack [SP+1] signal b_we_r : std_logic:='0'; signal b_en_r : std_logic:='0'; signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal b_r : unsigned(31 downto 0):=(others => '0'); signal c_we_r : std_logic := '0'; signal c_req_r : std_logic := '0'; signal c_mux_r : std_logic := '0'; signal c_mux_d : std_logic := '0'; signal byte_req_cnt : unsigned(1 downto 0) := "00"; signal byte_ack_cnt : unsigned(1 downto 0) := "00"; signal posted_wr_a : std_logic := '0'; -- State machine. type state_t is (st_fetch, st_execute, st_add, st_or, st_compare, st_loadb2, st_and, st_store, st_read_mem, st_write_mem, st_add_sp, st_decode, st_resync); signal state : state_t:=st_fetch; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "one-hot"; -- Decoded Opcode type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp, dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_pop_int, dec_add, dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store, dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb, dec_neqbranch, dec_compare); signal d_opcode_r : decode_t; signal d_opcode : decode_t; signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered -- IRQ flag signal in_irq_r : std_logic:='0'; -- I/O space address signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0'); -- helper signals for compare instructions signal compare_dec : std_logic_vector(2 downto 0); signal compare_oper : std_logic_vector(2 downto 0); signal compare_bool : boolean; signal compare_res : unsigned(31 downto 0); begin a_en_o <= a_en_r; b_en_o <= b_en_r; c_req_o <= '1' when state = st_fetch else c_req_r; -- Dual ported memory interface a_we_o <= a_we_r; a_addr_o <= a_addr_r(g_stack_size-1 downto 2); a_o <= a_r; b_we_o <= b_we_r; b_addr_o <= b_addr_r(g_stack_size-1 downto 2); b_o <= b_r; opcode <= unsigned(c_data_i); c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0' else addr_r; c_we_o <= c_we_r; c_inst_o <= not c_mux_r; ------------------------- -- Instruction Decoder -- ------------------------- -- Note: We use a separate memory port to fetch opcodes. decode_control: process(opcode) begin compare_dec <= "000"; -- synthesis translate_off if opcode(0)='Z' then d_opcode <= dec_nop; else -- synthesis translate_on if (opcode(7 downto 7)=OPCODE_IM) then d_opcode <= dec_im; elsif (opcode(7 downto 5)=OPCODE_STORESP) then d_opcode <= dec_store_sp; elsif (opcode(7 downto 5)=OPCODE_LOADSP) then d_opcode <= dec_load_sp; elsif (opcode(7 downto 5)=OPCODE_EMULATE) then case opcode(5 downto 0) is when OPCODE_LOADB => d_opcode <= dec_loadb; when OPCODE_STOREB => d_opcode <= dec_storeb; when OPCODE_NEQBRANCH => d_opcode <= dec_neqbranch; when OPCODE_EQ => d_opcode <= dec_compare; compare_dec <= "001"; when OPCODE_LESSTHAN => -- 00 d_opcode <= dec_compare; compare_dec <= "100"; when OPCODE_LESSTHANOREQUAL => -- 01 d_opcode <= dec_compare; compare_dec <= "101"; when OPCODE_ULESSTHAN => -- 10 d_opcode <= dec_compare; compare_dec <= "110"; when OPCODE_ULESSTHANOREQUAL => -- 11 d_opcode <= dec_compare; compare_dec <= "111"; when others => d_opcode <= dec_emulate; end case; elsif (opcode(7 downto 4)=OPCODE_ADDSP) then d_opcode <= dec_add_sp; else -- OPCODE_SHORT case opcode(3 downto 0) is when OPCODE_BREAK => d_opcode <= dec_break; when OPCODE_PUSHSP => d_opcode <= dec_push_sp; when OPCODE_POPPC => d_opcode <= dec_pop_pc; when OPCODE_ADD => d_opcode <= dec_add; when OPCODE_OR => d_opcode <= dec_or; when OPCODE_AND => d_opcode <= dec_and; when OPCODE_LOAD => d_opcode <= dec_load; when OPCODE_NOT => d_opcode <= dec_not; when OPCODE_FLIP => d_opcode <= dec_flip; when OPCODE_STORE => d_opcode <= dec_store; when OPCODE_POPSP => d_opcode <= dec_pop_sp; when OPCODE_POPINT => d_opcode <= dec_pop_int; when others => -- OPCODE_NOP and others d_opcode <= dec_nop; end case; end if; -- synthesis translate_off end if; -- synthesis translate_on end process decode_control; opcode_control: process (clk_i) variable sp_offset : unsigned(4 downto 0); procedure emulate is begin sp_r <= sp_r-1; a_we_r <= '1'; a_en_r <= '1'; a_addr_r <= sp_r-1; a_r <= (others => '0'); -- could be changed to don't care a_r(pc_r'range) <= pc_r+1; -- Jump to NUM32 -- The emulate address is: -- 98 7654 3210 -- 0000 00aa aaa0 0000 pc_r <= (others => '0'); pc_r(9 downto 5) <= opcode_r(4 downto 0); end procedure; procedure execute_def is begin state <= st_fetch; -- At this point: -- a_i contains top of stack, b_i contains next-to-top of stack pc_r <= pc_r+1; -- increment by default -- synthesis translate_off -- Debug info (Trace) dbg_o.b_inst <= '1'; dbg_o.pc <= (others => '0'); dbg_o.pc(g_prog_size-1 downto 0) <= pc_r; dbg_o.opcode <= opcode_r; dbg_o.sp <= (others => '0'); dbg_o.sp(g_stack_size-1 downto 2) <= sp_r; dbg_o.stk_a <= a_i; dbg_o.stk_b <= b_i; -- synthesis translate_on -- During the next cycle we'll be reading the next opcode sp_offset(4):=not opcode_r(4); sp_offset(3 downto 0):=opcode_r(3 downto 0); idim_r <= '0'; end procedure; begin if rising_edge(clk_i) then break_o <= '0'; -- synthesis translate_off dbg_o.b_inst <= '0'; -- synthesis translate_on posted_wr_a <= '0'; c_we_r <= '0'; c_mux_d <= c_mux_r; d_opcode_r <= d_opcode; opcode_r <= opcode; a_we_r <= '0'; b_we_r <= '0'; a_en_r <= '0'; b_en_r <= '0'; a_r <= (others => g_dont_care); -- output register b_r <= (others => g_dont_care); a_addr_r <= (others => g_dont_care); b_addr_r <= (others => g_dont_care); addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2); case state is when st_fetch => -- During this cycle -- we'll fetch the opcode @ pc and thus it will -- be available for st_execute in the next cycle -- At this point a_i contains the value that is from the top of the stack -- or that was fetched from the stack with an offset (loadsp) a_r <= a_i; if c_rack_i='1' then -- our request for instr has been seen -- by default, we need the two values of the stack, so we'll fetch them as well a_we_r <= posted_wr_a; a_addr_r <= sp_r; a_en_r <= '1'; b_addr_r <= sp_r+1; b_en_r <= '1'; state <= st_decode; else posted_wr_a <= posted_wr_a; -- hold end if; when st_decode => compare_oper <= compare_dec; if c_dack_i='1' then if interrupt_i='1' and in_irq_r='0' and idim_r='0' then -- We got an interrupt, execute interrupt instead of next instruction in_irq_r <= '1'; d_opcode_r <= dec_interrupt; -- override end if; state <= st_execute; end if; when st_execute => execute_def; -------------------- -- Execution Unit -- -------------------- case d_opcode_r is when dec_interrupt => -- Not a real instruction, but an interrupt -- Push(PC); PC=32 sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_we_r <= '1'; a_en_r <= '1'; a_r <= (others => g_dont_care); a_r(pc_r'range) <= pc_r; -- Jump to ISR pc_r <= to_unsigned(32, pc_r'length); -- interrupt address --report "ZPU jumped to interrupt!" severity note; when dec_im => idim_r <= '1'; a_we_r <= '1'; a_en_r <= '1'; if idim_r='0' then -- First IM -- Push the 7 bits (extending the sign) sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32)); else -- Next IMs, shift the word and put the new value in the lower -- bits a_addr_r <= sp_r; a_r(31 downto 7) <= a_i(24 downto 0); a_r(6 downto 0) <= opcode_r(6 downto 0); end if; when dec_store_sp => -- [SP+Offset]=Pop() b_we_r <= '1'; b_en_r <= '1'; b_addr_r <= sp_r+sp_offset; b_r <= a_i; sp_r <= sp_r+1; state <= st_fetch; -- was resync when dec_load_sp => -- Push([SP+Offset]) sp_r <= sp_r-1; a_addr_r <= sp_r+sp_offset; a_en_r <= '1'; posted_wr_a <= '1'; state <= st_resync; -- extra delay to fetch from A when dec_emulate => -- Push(PC+1), PC=Opcode[4:0]*32 emulate; when dec_add_sp => -- Push(Pop()+[SP+Offset]) b_addr_r <= sp_r+sp_offset; b_en_r <= '1'; state <= st_add_sp; when dec_break => --report "Break instruction encountered" severity failure; break_o <= '1'; when dec_push_sp => -- Push(SP) sp_r <= sp_r-1; a_we_r <= '1'; a_addr_r <= sp_r-1; a_en_r <= '1'; a_r <= (others => '0'); a_r(sp_r'range) <= sp_r; a_r(31) <= '1'; -- Mark this address as a stack address when dec_pop_pc => -- Pop(PC) pc_r <= a_i(pc_r'range); sp_r <= sp_r+1; state <= st_fetch; -- was resync when dec_pop_int => -- Pop(PC) in_irq_r <= '0'; -- no longer in an interrupt pc_r <= a_i(pc_r'range); sp_r <= sp_r+1; state <= st_fetch; -- was resync when dec_compare => -- Push(Compare(Pop()+Pop()) sp_r <= sp_r+1; state <= st_compare; when dec_add => -- Push(Pop()+Pop()) sp_r <= sp_r+1; state <= st_add; when dec_or => -- Push(Pop() or Pop()) sp_r <= sp_r+1; state <= st_or; when dec_and => -- Push(Pop() and Pop()) sp_r <= sp_r+1; state <= st_and; when dec_not => -- Push(not(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= not a_i; when dec_flip => -- Push(flip(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; for i in 0 to 31 loop a_r(i) <= a_i(31-i); end loop; when dec_loadb => addr_r <= a_i(g_addr_size-1 downto 0); if a_i(31)='1' then -- stack a_addr_r <= a_i(a_addr_r'range); a_en_r <= '1'; state <= st_loadb2; else a_r <= (others => '0'); c_req_r <= '1'; c_mux_r <= '1'; byte_req_cnt <= "00"; -- 1 byte byte_ack_cnt <= "00"; c_size_o <= "00"; state <= st_read_mem; end if; when dec_load => -- Push([Pop()]) addr_r(1 downto 0) <= a_i(1 downto 0);-- xor "11"; if a_i(31)='1' then -- stack a_addr_r <= a_i(a_addr_r'range); a_en_r <= '1'; posted_wr_a <= '1'; state <= st_resync; else -- report "Load: " & hstr(a_i); c_req_r <= '1'; -- output memory request c_mux_r <= '1'; -- output correct address byte_req_cnt <= "11"; -- 4 bytes byte_ack_cnt <= "11"; c_size_o <= "11"; state <= st_read_mem; end if; when dec_store => sp_r <= sp_r+1; addr_r(1 downto 0) <= a_i(1 downto 0); if a_i(31) = '1' then state <= st_store; else -- a=Pop(), b=Pop(), [a]=b state <= st_write_mem; byte_req_cnt <= "11"; -- 4 bytes c_size_o <= "11"; end if; when dec_storeb => if a_i(31) = '1' then emulate; else -- a=Pop(), b=Pop(), [a]=b sp_r <= sp_r+1; addr_r(1 downto 0) <= a_i(1 downto 0); c_size_o <= "00"; byte_req_cnt <= "00"; -- 1 byte state <= st_write_mem; end if; when dec_pop_sp => -- SP=Pop() sp_r <= a_i(g_stack_size-1 downto 2); state <= st_fetch; -- was resync when dec_neqbranch => -- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a -- Branches are almost always taken as they form loops sp_r <= sp_r + 2; -- Need to fetch stack again. state <= st_resync; if b_i/=0 then pc_r <= pc_r + a_i(pc_r'range); end if; when others => -- includes 'nop' null; end case; when st_loadb2 => -- select the correct stack byte if a_en_r='0' then -- wait one cycle until BRAM data is available a_r <= (others => '0'); case addr_r(1 downto 0) is when "11" => a_r( 7 downto 0) <= a_i( 7 downto 0); when "10" => a_r( 7 downto 0) <= a_i(15 downto 8); when "01" => a_r( 7 downto 0) <= a_i(23 downto 16); when "00" => a_r( 7 downto 0) <= a_i(31 downto 24); when others => null; end case; -- report "LoadB: " & hstr(a_i) & ", addr: " & hstr(addr_r(1 downto 0)); -- a_r <= a_i; -- dummy a_addr_r <= sp_r; a_en_r <= '1'; a_we_r <= '1'; state <= st_fetch; end if; when st_store => sp_r <= sp_r+1; -- for a store we need to pop 2! a_we_r <= '1'; a_en_r <= '1'; a_addr_r <= a_i(g_stack_size-1 downto 2); a_r <= b_i; state <= st_fetch; -- was resync -- when st_storeb => -- sp_r <= sp_r+1; -- for a store we need to pop 2! -- a_we_r <= '1'; -- a_en_r <= '1'; -- a_addr_r <= a_i(g_stack_size-1 downto 2); -- a_r <= b_i(7 downto 0) & b_i(7 downto 0) & b_i(7 downto 0) & b_i(7 downto 0); -- state <= st_fetch; -- was resync when st_read_mem => -- BIG ENDIAN a_r <= a_r; -- stay put, as we are filling it byte by byte! if c_dack_i = '1' then byte_ack_cnt <= byte_ack_cnt - 1; case byte_ack_cnt is when "00" => -- report "Returning " & hstr(a_r(31 downto 8)) & hstr(c_data_i) & -- " while reading from " & hstr(addr_r); a_r(7 downto 0) <= unsigned(c_data_i); a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; state <= st_fetch; when "01" => a_r(15 downto 8) <= unsigned(c_data_i); when "10" => a_r(23 downto 16) <= unsigned(c_data_i); when others => -- 11 a_r(31 downto 24) <= unsigned(c_data_i); end case; end if; if c_rack_i='1' then addr_r(1 downto 0) <= addr_r(1 downto 0) + 1; byte_req_cnt <= byte_req_cnt - 1; if byte_req_cnt = "00" then c_req_r <= '0'; c_mux_r <= '0'; end if; end if; when st_write_mem => c_req_r <= '1'; c_mux_r <= '1'; c_we_r <= '1'; -- Note: Output data is muxed outside of this process if c_rack_i='1' then addr_r(1 downto 0) <= addr_r(1 downto 0) + 1; byte_req_cnt <= byte_req_cnt - 1; if byte_req_cnt = "00" then sp_r <= sp_r+1; -- add another to sp. c_mux_r <= '0'; c_req_r <= '0'; c_we_r <= '0'; state <= st_fetch; -- was resync end if; end if; when st_add_sp => state <= st_add; when st_compare => a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= compare_res; state <= st_fetch; when st_add => a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= a_i+b_i; state <= st_fetch; when st_or => a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= a_i or b_i; state <= st_fetch; when st_and => a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= a_i and b_i; state <= st_fetch; when st_resync => a_addr_r <= sp_r; state <= st_fetch; posted_wr_a <= posted_wr_a; -- keep when others => null; end case; if reset_i='1' then state <= st_fetch; sp_r <= c_sp_start; pc_r <= (others => '0'); idim_r <= '0'; in_irq_r <= '0'; c_mux_r <= '0'; c_size_o <= "11"; end if; end if; -- rising_edge(clk_i) end process opcode_control; p_outmux: process(byte_req_cnt, b_i) begin case byte_req_cnt is when "00" => c_data_o <= std_logic_vector(b_i(7 downto 0)); when "01" => c_data_o <= std_logic_vector(b_i(15 downto 8)); when "10" => c_data_o <= std_logic_vector(b_i(23 downto 16)); when others => -- 11 c_data_o <= std_logic_vector(b_i(31 downto 24)); end case; end process; i_compare: entity work.zpu_compare port map ( a => a_i, b => b_i, oper => compare_oper, y => compare_bool ); compare_res <= X"00000001" when compare_bool else X"00000000"; end architecture Behave; -- Entity: zpu_8bit_loadb	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/usb/vhdl_source/ulpi_bus.vhd	3	7397	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ulpi_bus is port ( clock : in std_logic; reset : in std_logic; ULPI_DATA : inout std_logic_vector(7 downto 0); ULPI_DIR : in std_logic; ULPI_NXT : in std_logic; ULPI_STP : out std_logic; -- status status : out std_logic_vector(7 downto 0); -- register interface reg_read : in std_logic; reg_write : in std_logic; reg_address : in std_logic_vector(5 downto 0); reg_wdata : in std_logic_vector(7 downto 0); reg_ack : out std_logic; -- stream interface tx_data : in std_logic_vector(7 downto 0); tx_last : in std_logic; tx_valid : in std_logic; tx_start : in std_logic; tx_next : out std_logic; rx_data : out std_logic_vector(7 downto 0); rx_register : out std_logic; rx_last : out std_logic; rx_valid : out std_logic; rx_store : out std_logic ); attribute keep_hierarchy : string; attribute keep_hierarchy of ulpi_bus : entity is "yes"; end ulpi_bus; architecture gideon of ulpi_bus is signal ulpi_data_out : std_logic_vector(7 downto 0); signal ulpi_data_in : std_logic_vector(7 downto 0); signal ulpi_dir_d1 : std_logic; signal ulpi_dir_d2 : std_logic; signal ulpi_dir_d3 : std_logic; signal ulpi_nxt_d1 : std_logic; signal ulpi_nxt_d2 : std_logic; signal ulpi_nxt_d3 : std_logic; signal reg_cmd_d2 : std_logic; signal reg_cmd_d3 : std_logic; signal reg_cmd_d4 : std_logic; signal reg_cmd_d5 : std_logic; signal rx_reg_i : std_logic; signal tx_reg_i : std_logic; signal rx_status_i : std_logic; signal ulpi_stop : std_logic := '1'; signal ulpi_last : std_logic; type t_state is ( idle, reading, writing, writing_data, transmit ); signal state : t_state; attribute iob : string; attribute iob of ulpi_data_in : signal is "true"; attribute iob of ulpi_dir_d1 : signal is "true"; attribute iob of ulpi_nxt_d1 : signal is "true"; attribute iob of ulpi_data_out : signal is "true"; attribute iob of ULPI_STP : signal is "true"; begin -- Marking incoming data based on next/dir pattern rx_data <= ulpi_data_in; rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1; rx_valid <= ulpi_dir_d1 and ulpi_dir_d2; rx_last <= not ulpi_dir_d1 and ulpi_dir_d2; rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i; rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and (not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and reg_cmd_d5; rx_register <= rx_reg_i; reg_ack <= rx_reg_i or tx_reg_i; p_sample: process(clock, reset) begin if rising_edge(clock) then ulpi_data_in <= ULPI_DATA; reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6); reg_cmd_d3 <= reg_cmd_d2; reg_cmd_d4 <= reg_cmd_d3; reg_cmd_d5 <= reg_cmd_d4; ulpi_dir_d1 <= ULPI_DIR; ulpi_dir_d2 <= ulpi_dir_d1; ulpi_dir_d3 <= ulpi_dir_d2; ulpi_nxt_d1 <= ULPI_NXT; ulpi_nxt_d2 <= ulpi_nxt_d1; ulpi_nxt_d3 <= ulpi_nxt_d2; if rx_status_i='1' then status <= ulpi_data_in; end if; if reset='1' then status <= (others => '0'); end if; end if; end process; p_tx_state: process(clock, reset) begin if rising_edge(clock) then ulpi_stop <= '0'; tx_reg_i <= '0'; case state is when idle => ulpi_data_out <= X"00"; if reg_read='1' and rx_reg_i='0' then ulpi_data_out <= "11" & reg_address; state <= reading; elsif reg_write='1' and tx_reg_i='0' then ulpi_data_out <= "10" & reg_address; state <= writing; elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then ulpi_data_out <= tx_data; ulpi_last <= tx_last; state <= transmit; end if; when reading => if rx_reg_i='1' then ulpi_data_out <= X"00"; state <= idle; end if; if ulpi_dir_d1='1' then state <= idle; -- terminate current tx ulpi_data_out <= X"00"; end if; when writing => if ULPI_NXT='1' then ulpi_data_out <= reg_wdata; state <= writing_data; end if; if ulpi_dir_d1='1' then state <= idle; -- terminate current tx ulpi_data_out <= X"00"; end if; when writing_data => if ULPI_NXT='1' and ULPI_DIR='0' then tx_reg_i <= '1'; ulpi_stop <= '1'; state <= idle; end if; if ulpi_dir_d1='1' then state <= idle; -- terminate current tx ulpi_data_out <= X"00"; end if; when transmit => if ULPI_NXT = '1' then if ulpi_last='1' or tx_valid = '0' then ulpi_data_out <= X"00"; ulpi_stop <= '1'; state <= idle; else ulpi_data_out <= tx_data; ulpi_last <= tx_last; end if; end if; when others => null; end case; if reset='1' then state <= idle; ulpi_stop <= '0'; ulpi_last <= '0'; end if; end if; end process; p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write) begin case state is when idle => tx_next <= not ULPI_DIR and tx_valid and tx_start; if reg_read='1' and rx_reg_i='0' then tx_next <= '0'; end if; if reg_write='1' and tx_reg_i='0' then tx_next <= '0'; end if; when transmit => tx_next <= ULPI_NXT and tx_valid and not ulpi_last; when others => tx_next <= '0'; end case; end process; ULPI_STP <= ulpi_stop; ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z'); end gideon;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/mem_ctrl/vhdl_sim/ext_mem_test_32_tb.vhd	5	7761	------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM ------------------------------------------------------------------------------- -- Description: This module implements a simple, single burst memory controller. -- User interface is 32 bit (burst of 2), externally 8x 8 bit. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.vital_timing.all; library work; use work.mem_bus_pkg.all; entity ext_mem_test_32_tb is end ext_mem_test_32_tb; architecture tb of ext_mem_test_32_tb is signal clock : std_logic := '1'; signal clk_2x : std_logic := '1'; signal reset : std_logic := '0'; signal inhibit : std_logic := '0'; signal is_idle : std_logic := '0'; signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init; signal resp_16 : t_mem_burst_16_resp; signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init; signal resp_32 : t_mem_burst_32_resp; signal okay : std_logic; signal SDRAM_CLK : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CSn : std_logic := '1'; signal SDRAM_RASn : std_logic := '1'; signal SDRAM_CASn : std_logic := '1'; signal SDRAM_WEn : std_logic := '1'; signal SDRAM_DQM : std_logic := '0'; signal SDRAM_A : std_logic_vector(12 downto 0); signal SDRAM_BA : std_logic_vector(1 downto 0); signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z'); signal logic_CLK : std_logic; signal logic_CKE : std_logic; signal logic_CSn : std_logic := '1'; signal logic_RASn : std_logic := '1'; signal logic_CASn : std_logic := '1'; signal logic_WEn : std_logic := '1'; signal logic_DQM : std_logic := '0'; signal logic_A : std_logic_vector(12 downto 0); signal logic_BA : std_logic_vector(1 downto 0); signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H'); signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H'); constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns ); begin clock <= not clock after 10.2 ns; clk_2x <= not clk_2x after 5.1 ns; reset <= '1', '0' after 100 ns; i_checker: entity work.ext_mem_test_32 port map ( clock => clock, reset => reset, req => req_32, resp => resp_32, okay => okay ); i_convert: entity work.mem_16to32 port map ( clock => clock, reset => reset, req_16 => req_16, resp_16 => resp_16, req_32 => req_32, resp_32 => resp_32 ); i_mut: entity work.ext_mem_ctrl_v6 generic map ( q_tcko_data => 5 ns, g_simulation => true ) port map ( clock => clock, clk_2x => clk_2x, reset => reset, inhibit => inhibit, is_idle => is_idle, req => req_16, resp => resp_16, SDRAM_CLK => logic_CLK, SDRAM_CKE => logic_CKE, SDRAM_CSn => logic_CSn, SDRAM_RASn => logic_RASn, SDRAM_CASn => logic_CASn, SDRAM_WEn => logic_WEn, SDRAM_DQM => logic_DQM, SDRAM_BA => logic_BA, SDRAM_A => logic_A, SDRAM_DQ => MEM_D ); i_sdram : entity work.mt48lc16m16a2 generic map( tipd_BA0 => c_wire_delay, tipd_BA1 => c_wire_delay, tipd_DQMH => c_wire_delay, tipd_DQML => c_wire_delay, tipd_DQ0 => c_wire_delay, tipd_DQ1 => c_wire_delay, tipd_DQ2 => c_wire_delay, tipd_DQ3 => c_wire_delay, tipd_DQ4 => c_wire_delay, tipd_DQ5 => c_wire_delay, tipd_DQ6 => c_wire_delay, tipd_DQ7 => c_wire_delay, tipd_DQ8 => c_wire_delay, tipd_DQ9 => c_wire_delay, tipd_DQ10 => c_wire_delay, tipd_DQ11 => c_wire_delay, tipd_DQ12 => c_wire_delay, tipd_DQ13 => c_wire_delay, tipd_DQ14 => c_wire_delay, tipd_DQ15 => c_wire_delay, tipd_CLK => c_wire_delay, tipd_CKE => c_wire_delay, tipd_A0 => c_wire_delay, tipd_A1 => c_wire_delay, tipd_A2 => c_wire_delay, tipd_A3 => c_wire_delay, tipd_A4 => c_wire_delay, tipd_A5 => c_wire_delay, tipd_A6 => c_wire_delay, tipd_A7 => c_wire_delay, tipd_A8 => c_wire_delay, tipd_A9 => c_wire_delay, tipd_A10 => c_wire_delay, tipd_A11 => c_wire_delay, tipd_A12 => c_wire_delay, tipd_WENeg => c_wire_delay, tipd_RASNeg => c_wire_delay, tipd_CSNeg => c_wire_delay, tipd_CASNeg => c_wire_delay, -- tpd delays tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ), tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ), -- -- tpw values: pulse widths -- tpw_CLK_posedge : VitalDelayType := UnitDelay; -- tpw_CLK_negedge : VitalDelayType := UnitDelay; -- -- tsetup values: setup times -- tsetup_DQ0_CLK : VitalDelayType := UnitDelay; -- -- thold values: hold times -- thold_DQ0_CLK : VitalDelayType := UnitDelay; -- -- tperiod_min: minimum clock period = 1/max freq -- tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- mem_file_name => "none", tpowerup => 100 ns ) port map( BA0 => logic_BA(0), BA1 => logic_BA(1), DQMH => dummy_dqm(1), DQML => logic_DQM, DQ0 => MEM_D(0), DQ1 => MEM_D(1), DQ2 => MEM_D(2), DQ3 => MEM_D(3), DQ4 => MEM_D(4), DQ5 => MEM_D(5), DQ6 => MEM_D(6), DQ7 => MEM_D(7), DQ8 => dummy_data(8), DQ9 => dummy_data(9), DQ10 => dummy_data(10), DQ11 => dummy_data(11), DQ12 => dummy_data(12), DQ13 => dummy_data(13), DQ14 => dummy_data(14), DQ15 => dummy_data(15), CLK => logic_CLK, CKE => logic_CKE, A0 => logic_A(0), A1 => logic_A(1), A2 => logic_A(2), A3 => logic_A(3), A4 => logic_A(4), A5 => logic_A(5), A6 => logic_A(6), A7 => logic_A(7), A8 => logic_A(8), A9 => logic_A(9), A10 => logic_A(10), A11 => logic_A(11), A12 => logic_A(12), WENeg => logic_WEn, RASNeg => logic_RASn, CSNeg => logic_CSn, CASNeg => logic_CASn ); end;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/fpga_top/video_fpga/vhdl_source/s3e_clockgen.vhd	5	4287	library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity s3e_clockgen is port ( clk_50 : in std_logic; reset_in : in std_logic; dcm_lock : out std_logic; sys_clock : out std_logic; -- 50 MHz sys_reset : out std_logic; sys_shifted : out std_logic; pix_clock : out std_logic; -- * 7/25 (14 MHz) pix_clock_en: out std_logic; pix_reset : out std_logic ); end s3e_clockgen; architecture Gideon of s3e_clockgen is signal clk_in_buf : std_logic; signal sys_clk_buf : std_logic; signal reset_dcm : std_logic; signal reset_cnt : integer range 0 to 63 := 0; signal dcm1_locked : std_logic := '1'; signal sys_clk_i : std_logic := '0'; signal sysrst_cnt : integer range 0 to 63; signal sys_reset_i : std_logic := '1'; signal sys_reset_p : std_logic := '1'; signal pix_clock_pre : std_logic; signal pix_clock_ii : std_logic; signal pix_clock_i : std_logic; signal pixrst_cnt : integer range 0 to 63; signal pix_reset_i : std_logic := '1'; signal pix_reset_p : std_logic := '1'; signal pixdiv : integer range 0 to 7; signal reset_c : std_logic; signal reset_out : std_logic := '1'; attribute register_duplication : string; attribute register_duplication of sys_reset_i : signal is "no"; signal clk_0_pre : std_logic; signal clk_270_pre : std_logic; begin dcm_lock <= dcm1_locked; bufg_in : BUFG port map (I => clk_50, O => clk_in_buf); process(clk_in_buf) begin if rising_edge(clk_in_buf) then if reset_cnt = 63 then reset_dcm <= '0'; else reset_cnt <= reset_cnt + 1; reset_dcm <= '1'; end if; end if; if reset_in='1' then reset_dcm <= '1'; reset_cnt <= 0; end if; end process; dcm_shft: DCM generic map ( CLKIN_PERIOD => 20.0, -- CLKOUT_PHASE_SHIFT => "FIXED", CLK_FEEDBACK => "1X", -- PHASE_SHIFT => -20, CLKDV_DIVIDE => 2.5, CLKFX_MULTIPLY => 5, CLKFX_DIVIDE => 2, STARTUP_WAIT => true ) port map ( CLKIN => clk_in_buf, CLKFB => sys_clk_buf, CLK0 => clk_0_pre, CLK270 => clk_270_pre, CLKFX => pix_clock_pre, LOCKED => dcm1_locked, RST => reset_dcm ); bufg_pix: BUFG port map (I => pix_clock_pre, O => pix_clock_ii); bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf); bufg_shft: BUFG port map (I => clk_270_pre, O => sys_shifted); sys_clk_i <= sys_clk_buf; sys_clock <= sys_clk_buf; pix_clock <= pix_clock_ii; pix_clock_i <= pix_clock_ii; process(sys_clk_i, dcm1_locked) begin if rising_edge(sys_clk_i) then if sysrst_cnt = 63 then sys_reset_i <= '0'; else sysrst_cnt <= sysrst_cnt + 1; end if; sys_reset_p <= sys_reset_i; end if; if dcm1_locked='0' then sysrst_cnt <= 0; sys_reset_i <= '1'; sys_reset_p <= '1'; end if; end process; process(pix_clock_i, dcm1_locked) begin if rising_edge(pix_clock_i) then if pixdiv = 0 then pixdiv <= 4; pix_clock_en <= '1'; else pixdiv <= pixdiv - 1; pix_clock_en <= '0'; end if; if pixrst_cnt = 63 then pix_reset_i <= '0'; else pixrst_cnt <= pixrst_cnt + 1; end if; pix_reset_p <= pix_reset_i; end if; if dcm1_locked='0' then pixrst_cnt <= 0; pix_reset_i <= '1'; pix_reset_p <= '1'; end if; end process; sys_reset <= sys_reset_p; pix_reset <= pix_reset_p; end Gideon;	gpl-3.0
meaepeppe/FIR_ISA	VHDL/FIR_constants.vhd	1	609	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.math_real.all; PACKAGE FIR_constants IS CONSTANT Nb : INTEGER := 9; CONSTANT Ord: INTEGER := 8; CONSTANT UO: INTEGER := 1; CONSTANT Nbmult: INTEGER := 10; CONSTANT Nbadder: INTEGER:= Nb; --NUM_BITS_MULT + integer(floor(log2(real(FIR_ORDER+1)))); CONSTANT pipe_d: INTEGER := 0; CONSTANT IO_buffers: BOOLEAN := TRUE; CONSTANT CELLS_PIPE_STAGES: INTEGER := Ord +UO -1; TYPE IO_array IS ARRAY(UO-1 DOWNTO 0) OF STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); END FIR_constants; PACKAGE BODY FIR_constants IS END PACKAGE BODY FIR_constants;	gpl-3.0
Project-Bonfire/EHA	RTL/Chip_Designs/IMMORTAL_Chip_2017/ZedBoard_FPGA/toppest_module.vhd	3	2951	--Copyright (C) 2016 Siavoosh Payandeh Azad ------------------------------------------------------------ -- This file is automatically generated! -- Here are the parameters: -- network size x: 2 -- network size y: 2 -- Data width: 32 -- Parity: False ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE ieee.numeric_std.ALL; use work.component_pack.all; entity toppest_module is generic (DATA_WIDTH: integer := 32; -- DATA_WIDTH_LV: integer := 11; memory_type : string := -- "TRI_PORT_X" -- "DUAL_PORT_" -- "ALTERA_LPM" "XILINX_16X" ); port ( reset: in std_logic; clk: in std_logic; -- IJTAG network for fault injection and checker status monitoring TCK : in std_logic; RST : in std_logic; SEL : in std_logic; SI : in std_logic; SE : in std_logic; UE : in std_logic; CE : in std_logic; SO : out std_logic; toF : out std_logic; toC : out std_logic; -- GPIO for Node 0 GPIO_out: out std_logic_vector(15 downto 0); GPIO_in: in std_logic_vector(14 downto 0); -- GPIO_in: in std_logic_vector(21 downto 15); --not enough inputs -- UART for all Plasmas uart_write_0 : out std_logic; uart_read_0 : in std_logic; uart_write_1 : out std_logic; uart_read_1 : in std_logic; uart_write_2 : out std_logic; uart_read_2 : in std_logic; uart_write_3 : out std_logic; uart_read_3 : in std_logic ); end toppest_module; architecture behavior of toppest_module is signal clk1_noc, clk2_ijtag : std_logic; begin noc2x2_inst: entity work.network_2x2_with_PE generic map ( DATA_WIDTH => DATA_WIDTH, DATA_WIDTH_LV => 0, --UNUSED memory_type => memory_type ) port map ( reset => (not reset), clk => clk1_noc, TCK => clk2_ijtag, RST => RST, SEL => SEL, SI => SI, SE => SE, UE => UE, CE => CE, SO => SO, toF => toF, toC => toC, GPIO_out => GPIO_out, GPIO_in => "0000000" & GPIO_in, --switch(0) == GPIO_in(0) ... uart_write_0 => uart_write_0, uart_read_0 => uart_read_0, uart_write_1 => uart_write_1, uart_read_1 => uart_read_1, uart_write_2 => uart_write_2, uart_read_2 => uart_read_2, uart_write_3 => uart_write_3, uart_read_3 => uart_read_3 ); clk_gen: entity work.clk_wiz_0 port map ( --in: clk_in1 => clk, --out: clk1_noc => clk1_noc, clk2_ijtag => clk2_ijtag); end;	gpl-3.0
Project-Bonfire/EHA	RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/Rxy_Reconf/RTL/Rxy_Reconf_pseudo.vhd	3	1147	--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity Rxy_Reconf_pseudo is port ( Rxy_reconf: in std_logic_vector(7 downto 0); ReConf_FF_out: in std_logic; Rxy: in std_logic_vector(7 downto 0); Reconfig : in std_logic; flit_type: in std_logic_vector(2 downto 0); grants: in std_logic; empty: in std_logic; Rxy_in: out std_logic_vector(7 downto 0); ReConf_FF_in: out std_logic ); end Rxy_Reconf_pseudo; architecture behavior of Rxy_Reconf_pseudo is begin process(Rxy_reconf, ReConf_FF_out, Rxy, Reconfig, flit_type, grants, empty) begin if ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' then Rxy_in <= Rxy_reconf; ReConf_FF_in <= '0'; else Rxy_in <= Rxy; if Reconfig = '1' then ReConf_FF_in <= '1'; else ReConf_FF_in <= ReConf_FF_out; end if; end if; end process; end;	gpl-3.0
Project-Bonfire/EHA	RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/LBDR_packet_drop_with_checkers/LBDR_packet_drop_with_checkers.vhd	3	28312	--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_packet_drop is generic ( cur_addr_rst: integer := 8; Rxy_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); faulty: in std_logic; packet_drop_order: out std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic; -- Checker outputs -- Routing part checkers err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order, -- Cx_Reconf checkers err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added -- Rxy_Reconf checkers err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end LBDR_packet_drop; architecture behavior of LBDR_packet_drop is signal Cx, Cx_in: std_logic_vector(3 downto 0); signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0); signal reconfig_cx, reconfig_cx_in: std_logic; signal ReConf_FF_in, ReConf_FF_out: std_logic; signal Rxy, Rxy_in: std_logic_vector(7 downto 0); signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0); signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal N1, E1, W1, S1 :std_logic :='0'; signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic; signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic; signal grants: std_logic; signal packet_drop, packet_drop_in: std_logic; -- Signal(s) required for checker(s) signal packet_drop_order_sig: std_logic; component LBDR_packet_drop_routing_part_pseudo_checkers is generic ( cur_addr_rst: integer := 8; Rxy_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); faulty: in std_logic; Cx: in std_logic_vector(3 downto 0); Rxy: in std_logic_vector(7 downto 0); packet_drop: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; grants: in std_logic; packet_drop_order: in std_logic; packet_drop_in: in std_logic; -- Checker outputs err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic ); end component; component Cx_Reconf_pseudo_checkers is port ( reconfig_cx: in std_logic; -- * flit_type: in std_logic_vector(2 downto 0); -- * empty: in std_logic; -- * grants: in std_logic; -- * Cx_in: in std_logic_vector(3 downto 0); -- * Temp_Cx: in std_logic_vector(3 downto 0); -- * reconfig_cx_in: in std_logic; -- * Cx: in std_logic_vector(3 downto 0); -- * Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added Reconfig_command : in std_logic; -- newly added Faulty_C_N: in std_logic; -- * Faulty_C_E: in std_logic; -- * Faulty_C_W: in std_logic; -- * Faulty_C_S: in std_logic; -- * Temp_Cx_in: in std_logic_vector(3 downto 0); -- * -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added ); end component; component Rxy_Reconf_pseudo_checkers is port ( ReConf_FF_out: in std_logic; Rxy: in std_logic_vector(7 downto 0); Rxy_tmp: in std_logic_vector(7 downto 0); Reconfig_command : in std_logic; flit_type: in std_logic_vector(2 downto 0); grants: in std_logic; empty: in std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Rxy_in: in std_logic_vector(7 downto 0); Rxy_tmp_in: in std_logic_vector(7 downto 0); ReConf_FF_in: in std_logic; err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end component; begin packet_drop_order <= packet_drop_order_sig; -- LBDR packet drop routing part checkers instantiation LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers generic map (cur_addr_rst => cur_addr_rst, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) port map ( empty => empty, flit_type => flit_type, Req_N_FF => Req_N_FF, Req_E_FF => Req_E_FF, Req_W_FF => Req_W_FF, Req_S_FF => Req_S_FF, Req_L_FF => Req_L_FF, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, dst_addr => dst_addr, faulty => faulty, Cx => Cx, Rxy => Rxy, packet_drop => packet_drop, N1_out => N1, E1_out => E1, W1_out => W1, S1_out => S1, Req_N_in => Req_N_in, Req_E_in => Req_E_in, Req_W_in => Req_W_in, Req_S_in => Req_S_in, Req_L_in => Req_L_in, grants => grants, packet_drop_order => packet_drop_order_sig, packet_drop_in => packet_drop_in, -- Checker outputs err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => err_grants_onehot, err_grants_mismatch => err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => err_packet_drop_order ); -- LBDR packet drop Cx Reconfiguration module checkers instantiation Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map ( reconfig_cx => reconfig_cx, flit_type => flit_type, empty => empty, grants => grants, Cx_in => Cx_in, Temp_Cx => Temp_Cx, reconfig_cx_in => reconfig_cx_in, Cx => Cx, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command => Reconfig_command, Faulty_C_N => Faulty_C_N, Faulty_C_E => Faulty_C_E, Faulty_C_W => Faulty_C_W, Faulty_C_S => Faulty_C_S, Temp_Cx_in => Temp_Cx_in, -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal ); -- LBDR packet drop Rxy Reconfiguration checkers instantiation Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers port map ( ReConf_FF_out => ReConf_FF_out, Rxy => Rxy, Rxy_tmp => Rxy_tmp, Reconfig_command => Reconfig_command, flit_type => flit_type, grants => grants, empty => empty, Rxy_reconf_PE => Rxy_reconf_PE, Rxy_in => Rxy_in, Rxy_tmp_in => Rxy_tmp_in, ReConf_FF_in => ReConf_FF_in, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); grants <= grant_N or grant_E or grant_W or grant_S or grant_L; cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0'; E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0'; W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0'; S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0'; process(clk, reset) begin if reset = '0' then Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length)); Rxy_tmp <= (others => '0'); Req_N_FF <= '0'; Req_E_FF <= '0'; Req_W_FF <= '0'; Req_S_FF <= '0'; Req_L_FF <= '0'; Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length)); Temp_Cx <= (others => '0'); ReConf_FF_out <= '0'; reconfig_cx <= '0'; packet_drop <= '0'; elsif clk'event and clk = '1' then Rxy <= Rxy_in; Rxy_tmp <= Rxy_tmp_in; Req_N_FF <= Req_N_in; Req_E_FF <= Req_E_in; Req_W_FF <= Req_W_in; Req_S_FF <= Req_S_in; Req_L_FF <= Req_L_in; ReConf_FF_out <= ReConf_FF_in; Cx <= Cx_in; reconfig_cx <= reconfig_cx_in; Temp_Cx <= Temp_Cx_in; packet_drop <= packet_drop_in; end if; end process; -- The combionational part process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty) begin if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then Rxy_tmp_in <= Rxy_tmp; Rxy_in <= Rxy_tmp; ReConf_FF_in <= '0'; else Rxy_in <= Rxy; if Reconfig_command = '1'then Rxy_tmp_in <= Rxy_reconf_PE; ReConf_FF_in <= '1'; else Rxy_tmp_in <= Rxy_tmp; ReConf_FF_in <= ReConf_FF_out; end if; end if; end process; process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin Temp_Cx_in <= Temp_Cx; if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then Cx_in <= Temp_Cx; reconfig_cx_in <= '0'; else Cx_in <= Cx; if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx; elsif Reconfig_command = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= Cx_reconf_PE; else reconfig_cx_in <= reconfig_cx; end if; end if; end process; Req_N <= Req_N_FF; Req_E <= Req_E_FF; Req_W <= Req_W_FF; Req_S <= Req_S_FF; Req_L <= Req_L_FF; process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop, faulty) begin packet_drop_in <= packet_drop; if flit_type = "001" and empty = '0' then Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0); Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1); Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2); Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3); if dst_addr = cur_addr then Req_L_in <= '1'; else Req_L_in <= '0'; end if; if faulty = '1' or (((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) = '0') and ((((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) = '0') and ((((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) = '0') and ((((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3)) = '0') and (dst_addr /= cur_addr)) then packet_drop_in <= '1'; Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; end if; elsif flit_type = "100" and empty = '0' and grants = '1' then Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; else Req_N_in <= Req_N_FF; Req_E_in <= Req_E_FF; Req_W_in <= Req_W_FF; Req_S_in <= Req_S_FF; Req_L_in <= Req_L_FF; end if; if flit_type = "100" and empty = '0' then if packet_drop = '1' then packet_drop_in <= '0'; end if; end if; end process; packet_drop_order_sig <= packet_drop; END;	gpl-3.0
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hanw/Open-Source-FPGA-Bitcoin-Miner	projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_dc_fwft_ext_as.vhd	9	12637	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RvP9zZHkeFP18wLlGgDfVe/DTwIyMP7dhvzgCxp5m3YYL/LPCO9ICc+LBKqhQGhkjW48xpBAGwp3 rBBSE8qK6w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Qh1YkIKhLAJw+T0XBKcVE5CFy7U9clrK+8m4T/x0yjOoagdJeeO9PlbMa8zDeYYoZZutG5tu4t0N sS2pvvQBM2LCvmWTcVG3LWECd1SoSHNd1Q6UbLR4rRzrlUIDN4/JUR9PWghJqqumcUUJxnx5knEi K7afdfP3GWpa+Mc54+8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HhfJKJ7YjkLmM42nTlzlQdDAF0pHVZnxLAjs72tXPKfyr7K5syerWW1IxhILiZNM2A0cNOUuK1B8 3pAH/L4JIt1TVyRIV84DJ8CQly1B9HRzFyS98BKzUfjErddgSfzRoWts821YG5qRykFYzVy0JSNW Ragz33rrmmL7qwMoZDWEs40RddcGX9de4kYYJLuItLwkKCeuM+I1G4CDXKEueQ5u6LQ93N2lQnas nPqBrP8n3BEnbThXBdK1yg3hcWqeBMMV3uoyqi+DrjDYmFIVQeHVKMb7fDMmbeiNu+e1+hNugM7Q zuV0EDd3VBu5V4gC82AsbfxPzRb2dPjR2bGkJA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block r+ZA+Oj7YdWnX06D5ZqZqXmUolmi4IW3cJCjO5tbt4FUt2NRQKFRaPVa/OzCRO98jZcUAZnOrsQs Rep+1VM+AH7vO0AlpTwL2YQWhQIRDtPP4l7hvmAW2QqsKSPWDbymkELktbLs6z2QWa6KZT127iXh ieyHXY4cnV7w42J65Do= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tEVWrDxJT9dKo2YC8zO/ut+oDpg3zkEfgzRECtcSkT6P2lC2McwywkyNOqCk/pmUPQ4bCYcOEOvI jUK+HW4ZZSod7UJE4eE4llpWX07n8fHKwMRVLxvYuhUZ9T0douxC3Lt0fXzC85NJTyJkGimu9KjD 6StBQXytAUuaDDuiaVXVLzHavnShPhHlIbufuZ5VdmuStq9zhYgYirOxIgWll7ywfvt6pWGt6w8p vRlZPnsBCK53+Du8/VX674tC+XGMKo3ahf5CvdS1v1bXUIITFznP1EPny1sPqbe8Z3AmcS4i9zBH 4q/viijyABREqAn303FRoDoAgPOHPMNMgH0nSQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7616) `protect data_block 2jcCW+L/DvZCppgVQq4J4wutN6bK0k6sf58j6Lv8ThwnWKdPBHykU8TGeWX/oWZAwjvz3s87ex1k bw4N3UjDvtfIJZd3xIN1FYC/uWK14Wpia0QJcWqRZp1JtQZsa4gRlgj9wa8mgg/zRb5m72JiU94x SSWVYvuYNxDqJVEWaqcczadPYste5BXE/2QpAyKn/7IzlZCuPa6dIxOCZwq6xAkjZsci4VLJGbmQ oAG3dFsy3DMeFso3O6D9TqLo2YB84+Qjvrfvl8dY/hA6Q30pIvfG7n2NjRkSwX/AEGGdT9QqcfXS VXXZ6EZP1kB95H3HfU8txXxsOK6SqmLOX5F+ZpfXbUpk2XIg0aTDmFTCh1oZpPh7v/HzkFCkRbua HRIhUA2WbVMAQdMtZskmOhC9bwrAZygUHitK5aF+AVwh+dj+eMHDsaNX0UdJ5YE/Vi+dABiLQTLZ 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Project-Bonfire/EHA	RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/counter_threshold.vhd	6	3894	--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand -- This design is based on the proposed method, discussed in the following publication: -- "A Fault Prediction Module for a Fault Tolerant NoC Operation" -- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C. library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity counter_threshold_classifier is generic ( counter_depth: integer := 8; healthy_counter_threshold: integer := 4; faulty_counter_threshold: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; faulty_packet, Healthy_packet: in std_logic; Healthy, Intermittent, Faulty: out std_logic ); end counter_threshold_classifier; architecture behavior of counter_threshold_classifier is signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0); signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0); signal NET: std_logic; --no error threshold signal DET: std_logic; --detected error threshold signal reset_counters: std_logic; TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state); SIGNAL state, next_state : STATE_TYPE := Healthy_state; begin process(clk, reset)begin if reset = '0' then faulty_counter_out <= (others => '0'); healthy_counter_out <= (others => '0'); state <= Reset_state; elsif clk'event and clk = '1' then faulty_counter_out <= faulty_counter_in; healthy_counter_out <= healthy_counter_in; state <= next_state; end if; end process; process(faulty_packet, reset_counters, faulty_counter_out)begin if reset_counters = '1' then faulty_counter_in <= (others => '0'); elsif faulty_packet = '1' then faulty_counter_in <= faulty_counter_out + 1; else faulty_counter_in <= faulty_counter_out; end if; end process; process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin if reset_counters = '1' then healthy_counter_in <= (others => '0'); elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then healthy_counter_in <= healthy_counter_out + 1; else healthy_counter_in <= healthy_counter_out; end if; end process; process(healthy_counter_out, faulty_counter_out) begin reset_counters <= '0'; DET <= '0'; NET <= '0'; if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then NET <= '1'; reset_counters <= '1'; end if; if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then DET <= '1'; reset_counters <= '1'; end if; end process; process (NET, DET, state)begin Healthy <= '0'; Intermittent <= '0'; Faulty <= '0'; case state is when Healthy_state => if NET = '1' then next_state <= Healthy_state; elsif DET = '1' then next_state <= Intermittent_state; Intermittent <= '1'; else next_state <= Healthy_state; end if; when Intermittent_state => if NET = '1' then next_state <= Healthy_state; Healthy <= '1'; elsif DET = '1' then next_state <= Faulty_state; Faulty <= '1'; else next_state <= Intermittent_state; end if; when Faulty_state => next_state <= Faulty_state; when Reset_state => next_state <= Healthy_state; Healthy <= '1'; end case; end process; END;	gpl-3.0
Project-Bonfire/EHA	RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/counter_threshold.vhd	6	3894	--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand -- This design is based on the proposed method, discussed in the following publication: -- "A Fault Prediction Module for a Fault Tolerant NoC Operation" -- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C. library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity counter_threshold_classifier is generic ( counter_depth: integer := 8; healthy_counter_threshold: integer := 4; faulty_counter_threshold: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; faulty_packet, Healthy_packet: in std_logic; Healthy, Intermittent, Faulty: out std_logic ); end counter_threshold_classifier; architecture behavior of counter_threshold_classifier is signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0); signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0); signal NET: std_logic; --no error threshold signal DET: std_logic; --detected error threshold signal reset_counters: std_logic; TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state); SIGNAL state, next_state : STATE_TYPE := Healthy_state; begin process(clk, reset)begin if reset = '0' then faulty_counter_out <= (others => '0'); healthy_counter_out <= (others => '0'); state <= Reset_state; elsif clk'event and clk = '1' then faulty_counter_out <= faulty_counter_in; healthy_counter_out <= healthy_counter_in; state <= next_state; end if; end process; process(faulty_packet, reset_counters, faulty_counter_out)begin if reset_counters = '1' then faulty_counter_in <= (others => '0'); elsif faulty_packet = '1' then faulty_counter_in <= faulty_counter_out + 1; else faulty_counter_in <= faulty_counter_out; end if; end process; process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin if reset_counters = '1' then healthy_counter_in <= (others => '0'); elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then healthy_counter_in <= healthy_counter_out + 1; else healthy_counter_in <= healthy_counter_out; end if; end process; process(healthy_counter_out, faulty_counter_out) begin reset_counters <= '0'; DET <= '0'; NET <= '0'; if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then NET <= '1'; reset_counters <= '1'; end if; if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then DET <= '1'; reset_counters <= '1'; end if; end process; process (NET, DET, state)begin Healthy <= '0'; Intermittent <= '0'; Faulty <= '0'; case state is when Healthy_state => if NET = '1' then next_state <= Healthy_state; elsif DET = '1' then next_state <= Intermittent_state; Intermittent <= '1'; else next_state <= Healthy_state; end if; when Intermittent_state => if NET = '1' then next_state <= Healthy_state; Healthy <= '1'; elsif DET = '1' then next_state <= Faulty_state; Faulty <= '1'; else next_state <= Intermittent_state; end if; when Faulty_state => next_state <= Faulty_state; when Reset_state => next_state <= Healthy_state; Healthy <= '1'; end case; end process; END;	gpl-3.0
Project-Bonfire/EHA	RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/plasma.vhd	3	15291	--------------------------------------------------------------------- -- TITLE: Plasma (CPU core with memory) -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 6/4/02 -- FILENAME: plasma.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- This entity combines the CPU core with memory and a UART. -- -- Memory Map: -- 0x00000000 - 0x0000ffff Internal RAM (8KB) -- 0x10000000 - 0x100fffff External RAM (1MB) -- Access all Misc registers with 32-bit accesses -- 0x20000000 Uart Write (will pause CPU if busy) -- 0x20000000 Uart Read -- 0x20000010 IRQ Mask -- 0x20000020 IRQ Status -- 0x20000030 GPIO0 Out Set bits -- 0x20000040 GPIO0 Out Clear bits -- 0x20000050 GPIOA In -- 0x20000060 Counter -- 0x20000070 Ethernet transmit count -- IRQ bits: -- 7 GPIO31 -- 6 ^GPIO31 -- 5 EthernetSendDone -- 4 EthernetReceive -- 3 Counter(18) -- 2 ^Counter(18) -- 1 ^UartWriteBusy -- 0 UartDataAvailable -- modified by: Siavoosh Payandeh Azad -- Change logs: -- * An NI has been instantiated! -- * some changes has been applied to the ports of the CPU to facilitate the new NI! --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity plasma is generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM"; log_file : string := "UNUSED"; ethernet : std_logic := '0'; use_cache : std_logic := '0'; current_address : integer := 0; stim_file: string :="code.txt"); port(clk : in std_logic; reset : in std_logic; uart_write : out std_logic; uart_read : in std_logic; address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); mem_pause_in : in std_logic; no_ddr_start : out std_logic; no_ddr_stop : out std_logic; gpio0_out : out std_logic_vector(31 downto 0); gpioA_in : in std_logic_vector(31 downto 0); credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0); link_faults: in std_logic_vector(4 downto 0); turn_faults: in std_logic_vector(19 downto 0); Rxy_reconf_PE: out std_logic_vector(7 downto 0); Cx_reconf_PE: out std_logic_vector(3 downto 0); Reconfig_command : out std_logic ); end; --entity plasma architecture logic of plasma is signal address_next : std_logic_vector(31 downto 2); signal byte_we_next : std_logic_vector(3 downto 0); signal cpu_address : std_logic_vector(31 downto 0); signal cpu_byte_we : std_logic_vector(3 downto 0); signal cpu_data_w : std_logic_vector(31 downto 0); signal cpu_data_r : std_logic_vector(31 downto 0); signal cpu_pause : std_logic; signal data_read_uart : std_logic_vector(7 downto 0); signal write_enable : std_logic; signal eth_pause_in : std_logic; signal eth_pause : std_logic; signal mem_busy : std_logic; signal enable_misc : std_logic; signal enable_uart : std_logic; signal enable_uart_read : std_logic; signal enable_uart_write : std_logic; signal enable_eth : std_logic; signal gpio0_reg : std_logic_vector(31 downto 0); signal uart_write_busy : std_logic; signal uart_data_avail : std_logic; signal irq_mask_reg : std_logic_vector(7 downto 0); signal irq_status : std_logic_vector(7 downto 0); signal irq : std_logic; signal irq_eth_rec : std_logic; signal irq_eth_send : std_logic; signal counter_reg : std_logic_vector(31 downto 0); signal ram_enable : std_logic; signal ram_byte_we : std_logic_vector(3 downto 0); signal ram_address, ram_address_late : std_logic_vector(31 downto 2); signal ram_data_w : std_logic_vector(31 downto 0); signal ram_data_r, ram_data_r_ni : std_logic_vector(31 downto 0); signal NI_irq_out : std_logic; --signal NI_read_flag : std_logic; --signal NI_write_flag : std_logic; signal cache_access : std_logic; signal cache_checking : std_logic; signal cache_miss : std_logic; signal cache_hit : std_logic; constant reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; constant reserved_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; constant reserved_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"; begin --architecture write_enable <= '1' when cpu_byte_we /= "0000" else '0'; mem_busy <= eth_pause or mem_pause_in; cache_hit <= cache_checking and not cache_miss; cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy cache_miss or --Cache wait (cpu_address(28) and not cache_hit and mem_busy); --DDR or flash irq_status <= gpioA_in(31) & not gpioA_in(31) & irq_eth_send & irq_eth_rec & counter_reg(18) & not counter_reg(18) & not uart_write_busy & uart_data_avail; irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29); gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0); enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0'; enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0'; enable_uart_read <= enable_uart and not write_enable; enable_uart_write <= enable_uart and write_enable; enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0'; cpu_address(1 downto 0) <= "00"; u1_cpu: mlite_cpu generic map (memory_type => memory_type) PORT MAP ( clk => clk, reset_in => reset, intr_in => irq, --NI_read_flag => NI_read_flag, --NI_write_flag => NI_write_flag, address_next => address_next, --before rising_edge(clk) byte_we_next => byte_we_next, address => cpu_address(31 downto 2), --after rising_edge(clk) byte_we => cpu_byte_we, data_w => cpu_data_w, data_r => cpu_data_r, mem_pause => cpu_pause); opt_cache: if use_cache = '0' generate cache_access <= '0'; cache_checking <= '0'; cache_miss <= '0'; end generate; opt_cache2: if use_cache = '1' generate --Control 4KB unified cache that uses the upper 4KB of the 8KB --internal RAM. Only lowest 2MB of DDR is cached. u_cache: cache generic map (memory_type => memory_type) PORT MAP ( clk => clk, reset => reset, address_next => address_next, byte_we_next => byte_we_next, cpu_address => cpu_address(31 downto 2), mem_busy => mem_busy, cache_access => cache_access, --access 4KB cache cache_checking => cache_checking, --checking if cache hit cache_miss => cache_miss); --cache miss end generate; --opt_cache2 no_ddr_start <= not eth_pause and cache_checking; no_ddr_stop <= not eth_pause and cache_miss; eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking); misc_proc: process(clk, reset, cpu_address, enable_misc, ram_data_r, ram_address_late, ram_data_r_ni, data_read, data_read_uart, cpu_pause, irq_mask_reg, irq_status, gpio0_reg, write_enable, cache_checking, gpioA_in, counter_reg, cpu_data_w) begin case cpu_address(30 downto 28) is when "000" => --internal RAM if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address) or (ram_address_late = reserved_counter_address)) then cpu_data_r <= ram_data_r_ni; else cpu_data_r <= ram_data_r; end if; when "001" => --external RAM if cache_checking = '1' then --cpu_data_r <= ram_data_r; --cache if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address) or (ram_address_late = reserved_counter_address)) then cpu_data_r <= ram_data_r_ni; else cpu_data_r <= ram_data_r; --cache end if; else cpu_data_r <= data_read; --DDR end if; when "010" => --misc case cpu_address(6 downto 4) is when "000" => --uart cpu_data_r <= ZERO(31 downto 8) & data_read_uart; when "001" => --irq_mask cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg; when "010" => --irq_status cpu_data_r <= ZERO(31 downto 8) & irq_status; when "011" => --gpio0 cpu_data_r <= gpio0_reg; when "101" => --gpioA cpu_data_r <= gpioA_in; when "110" => --counter cpu_data_r <= counter_reg; when others => cpu_data_r <= gpioA_in; end case; when "011" => --flash cpu_data_r <= data_read; when others => cpu_data_r <= ZERO; end case; if reset = '1' then irq_mask_reg <= ZERO(7 downto 0); gpio0_reg <= ZERO; counter_reg <= ZERO; elsif rising_edge(clk) then counter_reg <= bv_inc(counter_reg); if cpu_pause = '0' then if enable_misc = '1' and write_enable = '1' then if cpu_address(6 downto 4) = "001" then irq_mask_reg <= cpu_data_w(7 downto 0); elsif cpu_address(6 downto 4) = "011" then gpio0_reg <= gpio0_reg or cpu_data_w; elsif cpu_address(6 downto 4) = "100" then gpio0_reg <= gpio0_reg and not cpu_data_w; elsif cpu_address(6 downto 4) = "110" then counter_reg <= cpu_data_w; end if; end if; end if; end if; end process; process(ram_address, reset, clk)begin if reset = '1' then ram_address_late <= (others => '0'); elsif clk'event and clk = '1' then ram_address_late <= ram_address; end if; end process; ram_proc: process(cache_access, cache_miss, address_next, cpu_address, byte_we_next, cpu_data_w, data_read) begin if cache_access = '1' then --Check if cache hit or write through ram_enable <= '1'; ram_byte_we <= byte_we_next; ram_address(31 downto 2) <= ZERO(31 downto 16) & "0001" & address_next(11 downto 2); ram_data_w <= cpu_data_w; elsif cache_miss = '1' then --Update cache after cache miss ram_enable <= '1'; ram_byte_we <= "1111"; ram_address(31 downto 2) <= ZERO(31 downto 16) & "0001" & cpu_address(11 downto 2); ram_data_w <= data_read; else --Normal non-cache access if address_next(30 downto 28) = "000" then ram_enable <= '1'; else ram_enable <= '0'; end if; ram_byte_we <= byte_we_next; ram_address(31 downto 2) <= address_next(31 downto 2); ram_data_w <= cpu_data_w; end if; end process; u2_ram: ram generic map (memory_type => memory_type, stim_file => stim_file) port map ( clk => clk, reset => reset, enable => ram_enable, write_byte_enable => ram_byte_we, address => ram_address, data_write => ram_data_w, data_read => ram_data_r); u3_uart: uart generic map (log_file => log_file) port map( clk => clk, reset => reset, enable_read => enable_uart_read, enable_write => enable_uart_write, data_in => cpu_data_w(7 downto 0), data_out => data_read_uart, uart_read => uart_read, uart_write => uart_write, busy_write => uart_write_busy, data_avail => uart_data_avail); dma_gen: if ethernet = '0' generate address <= cpu_address(31 downto 2); byte_we <= cpu_byte_we; data_write <= cpu_data_w; eth_pause <= '0'; gpio0_out(28 downto 24) <= ZERO(28 downto 24); irq_eth_rec <= '0'; irq_eth_send <= '0'; end generate; dma_gen2: if ethernet = '1' generate u4_eth: eth_dma port map( clk => clk, reset => reset, enable_eth => gpio0_reg(24), select_eth => enable_eth, rec_isr => irq_eth_rec, send_isr => irq_eth_send, address => address, --to DDR byte_we => byte_we, data_write => data_write, data_read => data_read, pause_in => eth_pause_in, mem_address => cpu_address(31 downto 2), --from CPU mem_byte_we => cpu_byte_we, data_w => cpu_data_w, pause_out => eth_pause, E_RX_CLK => gpioA_in(20), E_RX_DV => gpioA_in(19), E_RXD => gpioA_in(18 downto 15), E_TX_CLK => gpioA_in(14), E_TX_EN => gpio0_out(28), E_TXD => gpio0_out(27 downto 24)); end generate; u4_ni: NI generic map(current_address => current_address, SHMU_address => 0) port map ( clk => clk, reset => reset, enable => ram_enable, write_byte_enable => ram_byte_we, address => ram_address, data_write => ram_data_w, data_read => ram_data_r_ni, --NI_read_flag => NI_read_flag, --NI_write_flag => NI_write_flag, irq_out => NI_irq_out, credit_in => credit_in, valid_out => valid_out, TX => TX, credit_out => credit_out, valid_in => valid_in, RX => RX, link_faults => link_faults, turn_faults => turn_faults, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command => Reconfig_command ); end; --architecture logic	gpl-3.0
hanw/Open-Source-FPGA-Bitcoin-Miner	projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_min_area_pkg.vhd	9	20310	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block jxN/oW/orWDYrGNDeYaaKEfCi7IXDST1H7kY+pfwSjXvFzUhtXa/ESY+6frcDMqbRJ1eo2luDAox cWJLXqxRWQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NZD6/M1Wq3T+MPBYrb0rDgrvmzcSpEqPprXNMZQAf3T4mm+X9Ef8JfmMdGwzW1fDI+bcoBs4Eah8 gD+UMQccGE7pIxC7a91GCCgw9vpTrIr9SQUnzhQbD3owkpRPynslE1YF/XZYoUoa082bN+xXE15P ImVuzsmrTkxRD/JJG08= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block vR/Q0JJeUd2kEPcvu4ju+/rFqkQ5fDmgFNNLxZ7X3nN/tkuY7Qs6+/1hEXTND8ziK2UidBS0UY0u H/z78ddslzJCv7kqzg6xCL+Ygdi1ZwSW9rZi+tfEBCIQLbBaVUYQL3FPlZRt/lh1RY6FErJi0snk IMq1yDglEuWt6Q34KgYIH1I6irx+e46R5ExKwUZlwibQKHUE4l0yuDl6RPhw4WYB+orJR+9vXdNK JnmkBOPpqrYA5d07YnxMml8T8hb/3mw7EXkXzy1VgpnnHy0CaFADnvgw/R9vCTh61MyaY50Lj3zI a8a7L4EIViXk12cPU5S4++9tEs0jyrzcP/z17A== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 39tQL0Za6jjNqIvtD/N2Isj/AbmvTpiEDvV2yV4gNTIgtn2ywUxRwdi82J+iXGb2X8Qi2vaTas6h D8PZWOKolKHMKDbtENScUbSroO4cF0i9EZtr0XCoLbcP8JkqsZF+7wTDQEC0qgMIM8KW/Cfgi5Nl aVDejqr875l9nR7hxTU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block gyWJmjn2Bg9mr2KRiiHGcjoq9/I7waI8FM6NTjpDznS4xmeV5mm57x6YBsM++FudbEa5y5HoVdR1 mdsxpnmAaYOrnHnc2gmUuppkGYAcS4ymSin/RhDyIj5rIMJRrfo1y7OOyrqG5FkS/hBWK207BVUe S2sC0QS+rzoO/BWfkL5Ju7eXSombyki8nRgfm5IYzeSMnv5GGoVJ0n2F53dEjthndfYjDCEYb0Fk 1t2Qo1VfcXCNjmmO71sgtFvKwBILSdQfo4pBmquD+Zj0ATxi6+2aiL42NKumj9b19HUMnQ0aAu7x bCDJa+nqjQa4ICaWct8YlWg/r4iEVfmWag6Bmw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13296) `protect data_block luUNIy6VnP8LtVYZ2zO4PMaAvD03kpaa/EMPecgSm0yA4UBUQGD+vOKLxmlXiRXKiXa+E6J1Txph 43UQ0Z07U/JtG8yRDF21fZfaAN0oTAQniMwi4P5dPIGJsrWMVDa3mRlC7gC0VDBdQpUqGRkqxt/U 434YWU+GiIbUnVByfYM8AelDOVDnPecjcvBo+YoGeSbYzu1GgKiyAJhzIRj6C4cXnI7D8lGeYVtc 25OQj+oD5T4yw0XYJAfsZgR/4lcHuLONwQnEmAeTtdmxbvDQ41RCu9zDBD5zRuAN2QTf4Y/f9fnD kmCFuyL2AAbpWwNMtyrieDYAw0prXXI/iqpVKGWtgFCSzRVx+9BrEHhNyslhVxIzpogsg3G8dV48 iZoFL/fPJVjqHw/LZNmaXuIGPfN0Lu+RG8i/SnZp8111LTaCZTSuoFAqruypwHWEO2pfVtV+Wwc8 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hanw/Open-Source-FPGA-Bitcoin-Miner	projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/updn_cntr.vhd	9	10023	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MJu6CgyUu9Rx7DcIJ1WYxtXlEf9M4WTCKxGxEQurf0wS9A8H1bgDo0mC890fMV9dGN8tlX9O0g8S Qo5Og3Qumg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ExWc9QkINx2fRYuZ4iSBIH4TVBU1flfUsD9t3OrI2kQ7DlcI+fe5CuJcHvn+4Eus+9Wj67q3dDNV 9dTH4+uTaBy8FMiinsFEBZgTCvLxjbkS7iDmyXPI6KoCg/drEbxmfK4PV9mTNoUm3QKU9Y1th135 zhhgH++Bd5h0Yysnh1U= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 08n8ceY25YWVAFoupqatlCl2rQz9SVENaon0KM72325O4WrZvgMUUROAdmvJAokRNgBam69d5hNf xK5eJgBApza+ZtJFfqI0CAMrdGpYjgWPbArqOYKTurrSxBx8saXjrSL2QFgUZA4cNsCQ0uDVJVqq ONMD/XJ9DxfoLnqhDfJJyu3ZcyW9RhDLzRkQlmNgXTdXGOBg+S4hLOdDuw4duyjwO8Zl35W152xw TySG49Ck4Om1VmF1ShBCjba3IUSK7zs0pB0pu4Y92K4ZcyRcFTZH2Nzwoo2IT67U645QWZrx4RGs 6uw00dS+OG4oSyyos+jKqstWrXK2CofN0Ko4aw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block j56kiWofr2kH1KQ9xxDRg1jv14wUx9T6gxwuCzRqJTgwMbZuCIhkYwpvUbNXEhD4SeMtH1aHaw8I HU4/UsUhBGYYINu90+vVVssqtZqYezl0Nl/L02zbNiom/Dcfb1SE2BsMaX/Y0HPVjgmrrOx/fGMe C7AQOpjLh5c81sn4jZU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block NJ5es1ZDqQ8NebX7NTnnmCSOJyin4Et3d+KOKh4tAtxiLfoNquxSeHAiNj0Mn2TMlCjLWp3/qGex H5xI9z0f4NPkHvs1NHfEtN/GeliNl7P+BvtaqAGawR14m0bHMQsiASq3wM6WugIs+T47dSQMVvzB PVI6FwE4b6vk9QtADFwXOrsVdXANiM690qPkx78Y5rX9ny+T0xTzkjqTSubBOQo3ncYLtd7f2o/N tjzBXZ9EvIm7bWwxaobF/n78sQ4/ZZBrdpNkgYIOha1BEVmsDbTnNsr7vVz0grGedBz10Fagv/G1 QARm/sMZyl/SJB2IhoBmSqL7CEQwh7gAdf8m7g== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5680) `protect data_block qZEl5eIT9NHWEZg7a7CsgYvd+eNj/jmFWkXx9V/kL39W3LQ9JT3ElU3FPR7V0E/A0OTVLkJO/1oI WMAmUdXHewTih+z0cwDSPwInrsmVe4GaVZlk6h2llkKC272touXNfFaB977TWsGkFPA9NqzLAuQd zrAKDzRWA0V3G2cvXCMkjvqBGL7ABo3OvvBOs6WaONSMDw7FowL3uA7fK+Ume2dkq1oTrj0cJm3+ 5SRUze8/iydDfzO0uSWWIihfo2FIAgufY1ovtHLnOHXyoChuyfAcqITec0GcQJPrDCsziXrBscQI s9xmfsx1YeKS7bWejvN+MX2Hr8Zx9oCZtKtD506fOlp1pgMqQ8irjagQsNWmgAcR+nsOrXaYNqNM iOeI0WRGXKkyQuTB2mHThm099Jg/lrsI2LxCkUAkRMF8AgKJuvU8DvqBUdqyS+7MYqeuHbHyXqfm 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hanw/Open-Source-FPGA-Bitcoin-Miner	projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/fifo16_patch_top.vhd	9	11515	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block cPZ7+eHDLjmNfVUj8WvKqXLAnPtyLm0s9aYSxSzHsqbVkwztD0TQZP6rapbcQM3whT4sRRe0Nv72 4hG04ccfPg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pDGgn+8ERDtvyySodmphmnLIurqM6Ql+NZFaA+4rCgAMlfgC9XqIc5lR1N3M2RxHZcDKAzfijmgq wUVBrbuleWBsgTB0E9cQb1vaYOPRfnUmsBAEMlSBrOybJO2x97XdjtnNdx21f5BsMSmSL99k84uC D3w/Q2EtG2sVqfsQ0Uw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ux0E7ic7ddrM05MHFP6SN01PL8t1fArCWREGsYjS2ONcF2IPi6qGxKv2j6Bz1/ksI2IdqxEwhMND Xwur5QkftdAoX842VLyoS+RhDtjOuzxClBPUN6Vp5PhuRj5IeqN65zqr7zc9VOA1EmoOY/R8fBEz Yo5b5k2v7CH1jlqgBhYliwBu+iM8gR/saVfjlxNHAqq9lCHEmlTh+cLc7U9e4drEHfwIEzJax4pV 3UJYu2YsQBbZsIHHMUvLM6+80Ox+YDCN03PRmISy/UeZ5/ptqjgXOo4VTQz/KgxyxlOsplJzflag /DihISoV8c87bVCFlaELwfvYcWhO1XAm5g9qhw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block EYV2fiDAQh47256HEG+lsKBNLjtKVHQOJbaPpVgeYOluFA28J//O8rDaD+o6fukMY9UOhT21+W74 eqHFBt7pa0zrz16/ZAQqs46TsLmKJqugsbZtphRz1JMU5+zfR/c9k4K1/CLB357EkoC+1fU3gPxX pYsfqy24jhagQ349Nkg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block bLJwmBFChIRX3l4b6zFqLjuzCEYMRmsSJsdKazWL8VLHQck3Qbxi50EZ4DPvqyxFcGnmBE7UdkS7 4whktutIv5Nf1TltNTuRrHFt9yCzZZ6BdoFh+UCXBHV7BgHaQemox6pN6HmtyrHs/jrWfynM8H6t pU9SNjG6QssLUAwOZXNFRv/EjDI33IJZniMh9ZUY+WTbOHlRmddCkAQ/EToYAcRPx9uv3iXiInys pN4Rxd27ZVxvkywvgA5u8skaQRlT206DpSLUGlrIRAaS08vPKOsqgNQdxiJRL4d3ATCXWh3AnfD/ hm0Ex7zx8yOCRtwA7vyU88q8ARmDTL+GPaSknQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6784) `protect data_block PEdyL/6maIPEePxPLZVmqWWjenOPjeFM0R0RyvI7Avm7KfW53geXamljlX/E066mv+Vp43jjGrbP 6MK5bjJ5Tog8BU5NYsSoIhhS3IaQpNBaNKkRqkHD9cFHua0Z9DJ+tQ+RUCUed7RBfO638ZkoYAIx 6mj4CJ2AOYBs8LX5tkj4kzo5OzeefCdaeeXb4BDaAb35QCyFf1VYbLz6qCw0Y38Jz6H8ixF2iHir N3zEuoFOUATKeJRoMdlyElzw4yBC6DB2QuFwZ2iT4tWVstEGGfCpWJYZ93LtsqI2ljfAHolVcavQ OQj0eA0aTHwuoWGs7MxnFDdLwUaXHVm7E2kq9M+H2eM1BzRCcxJQhP3DE588qJO8fvKeVC+mlSZq Y2xN9U1iWa2WscgSu/W/YGNG1rXN4IxYGEr9fkTOO9ZCYsQLE7ZSQBACak09TOlmZZGccR0e7C+9 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Project-Bonfire/EHA	RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/New_SHMU_on_Node/LBDR_packet_drop_checkers/LBDR_packet_drop_with_checkers.vhd	6	27011	--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_packet_drop is generic ( cur_addr_rst: integer := 5; Rxy_rst: integer := 60; Cx_rst: integer := 15; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); packet_drop_order: out std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic; -- Checker outputs -- Routing part checkers err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order, -- Cx_Reconf checkers err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added -- Rxy_Reconf checkers err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end LBDR_packet_drop; architecture behavior of LBDR_packet_drop is signal Cx, Cx_in: std_logic_vector(3 downto 0); signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0); signal reconfig_cx, reconfig_cx_in: std_logic; signal ReConf_FF_in, ReConf_FF_out: std_logic; signal Rxy, Rxy_in: std_logic_vector(7 downto 0); signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0); signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal N1, E1, W1, S1 :std_logic :='0'; signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic; signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic; signal grants: std_logic; signal packet_drop, packet_drop_in: std_logic; -- Signal(s) required for checker(s) signal packet_drop_order_sig: std_logic; component LBDR_packet_drop_routing_part_pseudo_checkers is generic ( cur_addr_rst: integer := 5; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); Cx: in std_logic_vector(3 downto 0); Rxy: in std_logic_vector(7 downto 0); packet_drop: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; grants: in std_logic; packet_drop_order: in std_logic; packet_drop_in: in std_logic; -- Checker outputs err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic ); end component; component Cx_Reconf_pseudo_checkers is port ( reconfig_cx: in std_logic; -- * flit_type: in std_logic_vector(2 downto 0); -- * empty: in std_logic; -- * grants: in std_logic; -- * Cx_in: in std_logic_vector(3 downto 0); -- * Temp_Cx: in std_logic_vector(3 downto 0); -- * reconfig_cx_in: in std_logic; -- * Cx: in std_logic_vector(3 downto 0); -- * Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added Reconfig_command : in std_logic; -- newly added Faulty_C_N: in std_logic; -- * Faulty_C_E: in std_logic; -- * Faulty_C_W: in std_logic; -- * Faulty_C_S: in std_logic; -- * Temp_Cx_in: in std_logic_vector(3 downto 0); -- * -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added ); end component; component Rxy_Reconf_pseudo_checkers is port ( ReConf_FF_out: in std_logic; Rxy: in std_logic_vector(7 downto 0); Rxy_tmp: in std_logic_vector(7 downto 0); Reconfig_command : in std_logic; flit_type: in std_logic_vector(2 downto 0); grants: in std_logic; empty: in std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Rxy_in: in std_logic_vector(7 downto 0); Rxy_tmp_in: in std_logic_vector(7 downto 0); ReConf_FF_in: in std_logic; err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end component; begin packet_drop_order <= packet_drop_order_sig; -- LBDR packet drop routing part checkers instantiation LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size) port map ( empty => empty, flit_type => flit_type, Req_N_FF => Req_N_FF, Req_E_FF => Req_E_FF, Req_W_FF => Req_W_FF, Req_S_FF => Req_S_FF, Req_L_FF => Req_L_FF, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, dst_addr => dst_addr, Cx => Cx, Rxy => Rxy, packet_drop => packet_drop, N1_out => N1, E1_out => E1, W1_out => W1, S1_out => S1, Req_N_in => Req_N_in, Req_E_in => Req_E_in, Req_W_in => Req_W_in, Req_S_in => Req_S_in, Req_L_in => Req_L_in, grants => grants, packet_drop_order => packet_drop_order_sig, packet_drop_in => packet_drop_in, -- Checker outputs err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => err_grants_onehot, err_grants_mismatch => err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in => err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal => err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => err_packet_drop_order ); -- LBDR packet drop Cx Reconfiguration module checkers instantiation Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map ( reconfig_cx => reconfig_cx, flit_type => flit_type, empty => empty, grants => grants, Cx_in => Cx_in, Temp_Cx => Temp_Cx, reconfig_cx_in => reconfig_cx_in, Cx => Cx, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command => Reconfig_command, Faulty_C_N => Faulty_C_N, Faulty_C_E => Faulty_C_E, Faulty_C_W => Faulty_C_W, Faulty_C_S => Faulty_C_S, Temp_Cx_in => Temp_Cx_in, -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal ); -- LBDR packet drop Rxy Reconfiguration checkers instantiation Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers port map ( ReConf_FF_out => ReConf_FF_out, Rxy => Rxy, Rxy_tmp => Rxy_tmp, Reconfig_command => Reconfig_command, flit_type => flit_type, grants => grants, empty => empty, Rxy_reconf_PE => Rxy_reconf_PE, Rxy_in => Rxy_in, Rxy_tmp_in => Rxy_tmp_in, ReConf_FF_in => ReConf_FF_in, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); grants <= grant_N or grant_E or grant_W or grant_S or grant_L; cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0'; E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0'; W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0'; S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0'; process(clk, reset) begin if reset = '0' then Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length)); Rxy_tmp <= (others => '0'); Req_N_FF <= '0'; Req_E_FF <= '0'; Req_W_FF <= '0'; Req_S_FF <= '0'; Req_L_FF <= '0'; Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length)); Temp_Cx <= (others => '0'); ReConf_FF_out <= '0'; reconfig_cx <= '0'; packet_drop <= '0'; elsif clk'event and clk = '1' then Rxy <= Rxy_in; Rxy_tmp <= Rxy_tmp_in; Req_N_FF <= Req_N_in; Req_E_FF <= Req_E_in; Req_W_FF <= Req_W_in; Req_S_FF <= Req_S_in; Req_L_FF <= Req_L_in; ReConf_FF_out <= ReConf_FF_in; Cx <= Cx_in; reconfig_cx <= reconfig_cx_in; Temp_Cx <= Temp_Cx_in; packet_drop <= packet_drop_in; end if; end process; -- The combionational part process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty)begin Rxy_tmp_in <= Rxy_tmp; if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then Rxy_in <= Rxy_tmp; ReConf_FF_in <= '0'; else Rxy_in <= Rxy; if Reconfig_command = '1'then Rxy_tmp_in <= Rxy_reconf_PE; ReConf_FF_in <= '1'; else Rxy_tmp_in <= Rxy_tmp; ReConf_FF_in <= ReConf_FF_out; end if; end if; end process; process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin Temp_Cx_in <= Temp_Cx; if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then Cx_in <= Temp_Cx; reconfig_cx_in <= '0'; else Cx_in <= Cx; if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx; elsif Reconfig_command = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= Cx_reconf_PE; else reconfig_cx_in <= reconfig_cx; end if; end if; end process; Req_N <= Req_N_FF; Req_E <= Req_E_FF; Req_W <= Req_W_FF; Req_S <= Req_S_FF; Req_L <= Req_L_FF; process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop, dst_addr, cur_addr) begin packet_drop_in <= packet_drop; if flit_type = "001" and empty = '0' then Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0); Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1); Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2); Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3); if dst_addr = cur_addr then Req_L_in <= '1'; else Req_L_in <= Req_L_FF; -- Added to remove latch possibility. Correct ?? end if; if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or (((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or (((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or (((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and dst_addr /= cur_addr then packet_drop_in <= '1'; end if; elsif flit_type = "100" and empty = '0' and grants = '1' then Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; else Req_N_in <= Req_N_FF; Req_E_in <= Req_E_FF; Req_W_in <= Req_W_FF; Req_S_in <= Req_S_FF; Req_L_in <= Req_L_FF; end if; if flit_type = "100" and empty = '0' then if packet_drop = '1' then packet_drop_in <= '0'; end if; end if; end process; packet_drop_order_sig <= packet_drop; END;	gpl-3.0
Project-Bonfire/EHA	RTL/Router/credit_based/RTL/FIFO_one_hot_credit_based_packet_drop.vhd	3	16426	--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FIFO_credit_based is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; credit_out: out std_logic; empty_out: out std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end FIFO_credit_based; architecture behavior of FIFO_credit_based is signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0); signal full, empty: std_logic; signal read_en, write_en: std_logic; signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0); constant fake_tail : std_logic_vector := "10000000000000000000000000000001"; alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3); signal faulty_packet_in, faulty_packet_out: std_logic; signal xor_all, fault_out: std_logic; type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop); signal state_out, state_in : state_type; signal fake_credit, credit_in, write_fake_flit: std_logic; signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0); begin -------------------------------------------------------------------------------------------- -- block diagram of the FIFO! -------------------------------------------------------------------------------------------- -- circular buffer structure -- <--- WriteP -- --------------------------------- -- \| 3 \| 2 \| 1 \| 0 \| -- --------------------------------- -- <--- readP -------------------------------------------------------------------------------------------- -- Packet drop state machine -- +---+ No +---+ No -- \| \| Flit \| \| Flit -- \| v \| v -- healthy +--------+ +--------+ -- +---header-->\| \| \| \|-------------------+ -- \| +->\| Header \|---Healthy body-->\| Body \|------------+ \| -- \| \| +--------+ +--------+ \| \| -- \| \| \| ^ \| Healthy \| ^ Healthy \| -- \| \| \| \| \| body \| \| Tail \| -- \| \| \| \| \| +---+ \| \| -- \| \| \| \| \| v \| -- +--------+ \| \| \| \| +--------+ \| -- No +-->\| \| \| \| \| +-----------------Healthy Tail------>\| \| \| -- Flit\| \| IDLE \| \| \| \| \| Tail \|--)--+ -- +---\| \| \| \| +-----------Healthy Header--------------\| \| \| \| -- +--------+ \| \| +--------+ \| \| -- ^ \| ^ \| Faulty No Faulty \| \| -- \| \| \| \| Flit Flit Flit \| \| -- \| \| \| \| +------------+ +---+ +---+ \| \| -- \| \| \| + --Healthy------+ \| \| \| \| \| \| \| -- \| \| \| header \| v \| v \| v \| \| -- \| \| \| +------------------+ \| \| -- \| \| +----Healthy Tail-----\| Packet \| \| \| -- \| +-------Faulty Flit----->\| Drop \|<-----------------------+ \| -- \| +------------------+ \| -- +-------------------------------------------------No Flit------------------+ -- ------------------------------------------------------------------------------------------------ process (clk, reset)begin if reset = '0' then read_pointer <= "0001"; write_pointer <= "0001"; FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0'); fake_credit_counter <= (others=>'0'); faulty_packet_out <= '0'; credit_out <= '0'; state_out <= Idle; elsif clk'event and clk = '1' then write_pointer <= write_pointer_in; read_pointer <= read_pointer_in; state_out <= state_in; faulty_packet_out <= faulty_packet_in; credit_out <= credit_in; fake_credit_counter <= fake_credit_counter_in; if write_en = '1' then --write into the memory FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in; end if; end if; end process; -- anything below here is pure combinational -- combinatorial part process(fake_credit, read_en, fake_credit_counter) begin fake_credit_counter_in <= fake_credit_counter; credit_in <= '0'; if fake_credit = '1' and read_en = '1' then fake_credit_counter_in <= fake_credit_counter + 1 ; end if; if (read_en ='1' or fake_credit = '1') then credit_in <= '1'; end if; if read_en = '0' and fake_credit = '0' and fake_credit_counter > 0 then fake_credit_counter_in <= fake_credit_counter - 1 ; credit_in <= '1'; end if; end process; process(valid_in, RX) begin if valid_in = '1' then xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1)); else xor_all <= '0'; end if; end process; process(valid_in, RX, xor_all)begin fault_out <= '0'; if valid_in = '1' and xor_all /= RX(0) then fault_out <= '1'; end if; end process; process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin -- this is the default value of the memory! case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; --some defaults fake_credit <= '0'; state_in <= state_out; faulty_packet_in <= faulty_packet_out; write_fake_flit <= '0'; case(state_out) is when Idle => if fault_out = '0' then if valid_in = '1' then state_in <= Header_flit; else state_in <= state_out; end if; else fake_credit <= '1'; FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; when Header_flit => if valid_in = '1' then if fault_out = '0' then if flit_type = "010" then state_in <= Body_flit; elsif flit_type ="100" then state_in <= Tail_flit; else -- we should not be here! state_in <= state_out; end if; else write_fake_flit <= '1'; case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; else state_in <= state_out; end if; when Body_flit => if valid_in = '1' then if fault_out = '0' then if flit_type = "010" then state_in <= state_out; elsif flit_type = "100" then state_in <= Tail_flit; else -- we should not be here! state_in <= state_out; end if; else write_fake_flit <= '1'; case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; else state_in <= state_out; end if; when Tail_flit => if valid_in = '1' then if fault_out = '0' then if flit_type = "001" then state_in <= Header_flit; else state_in <= state_out; end if; else fake_credit <= '1'; FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; else state_in <= Idle; end if; when Packet_drop => if faulty_packet_out = '1' then if valid_in = '1' and flit_type = "001" and fault_out = '0' then faulty_packet_in <= '0'; state_in <= Header_flit; write_fake_flit <= '1'; case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; faulty_packet_in <= '0'; state_in <= Idle; fake_credit <= '1'; else if valid_in = '1' then fake_credit <= '1'; end if; FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; state_in <= state_out; end if; else -- we should not be here! state_in <= state_out; end if; when others => state_in <= state_out; end case; end process; process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin case( read_pointer ) is when "0001" => Data_out <= FIFO_MEM_1; when "0010" => Data_out <= FIFO_MEM_2; when "0100" => Data_out <= FIFO_MEM_3; when "1000" => Data_out <= FIFO_MEM_4; when others => Data_out <= FIFO_MEM_1; end case ; end process; read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty; empty_out <= empty; process(write_en, write_pointer)begin if write_en = '1' then write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3); else write_pointer_in <= write_pointer; end if; end process; process(read_en, empty, read_pointer)begin if (read_en = '1' and empty = '0') then read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3); else read_pointer_in <= read_pointer; end if; end process; process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then write_en <= '1'; else write_en <= '0'; end if; end process; process(write_pointer, read_pointer) begin if read_pointer = write_pointer then empty <= '1'; else empty <= '0'; end if; -- if write_pointer = read_pointer>>1 then if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then full <= '1'; else full <= '0'; end if; end process; end;	gpl-3.0
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hanw/Open-Source-FPGA-Bitcoin-Miner	projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_output_block.vhd	9	17048	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ZDbLXMCW/rFA4qQp7M4XtRAVOMy7+62OqdKd3dOe4Jvb/C2JADukHaa3oslAf5TtlaTLr3ozEohl VKGhLio1ig== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Y/syMaBfRSQ9MD98NKAleGixPcntMfRl9i4DpBCi/l65gO8EpoXWOhQZbbZ/maNd7yin7yuO19Yn GGuE9YDWOl8XBpG3phkcKzJdSu0mKYd+0AQJj9q1lFv6qrGMoUttsl/IpN2yMUpz5fUapnIBd6rb mRz2FHrHicaebKc88GU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block FF+Cl3PgjNR7xzwHRMbIHqn9oRbNDNLj8DIaO1Hlm+2QX1CI/VCFdTgjthL/wOzU50VEXfI4vdA+ 5GN341oMmZ0O5YACNPw0jsmb5K/Axml5iblkv1aO205Ys1mBMBZkaFGlBcZsIV0uEzUDpOvPfeVc ABQXYw6KbTA1+NUfxZFROZrc/rjF2mQh4nDUCfFYZPrriJZjjyEjlSX+cy4KzCuZbbpJBCFd6XxQ koLohsN3xKemISIPZsKR/aiic3+A4CLGXARU2+NNZ8Y9zw6ZjLQLvFiy4Fb1QeehEhg6MMEY/h+t IjJP8sZ2k68e+ilMbQE8db8f77x7eXxc0dya2Q== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WftP1jT77k0S0KW6WZKPHR28tgdkvbiMqDTC2VCWXKRGglkNUJl3J5a6mxg7KN6NyWhnYj6a5QQx 8Hz0va2ePEpBUyQNGP6NCbGXeaRe8pCPsXgRKTVJmrMqDjyhAZagmIXcKOaLXzSspWEBEQiSDaSF bOXSgmj7JNe+zDKqwGQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block RqlUBtgum9dv43EmKmtzWIjfHZGaDUNQ3TN8Yu3IeXyJKi5cWCoW72Oqm8t5IbLFWHnY2SKPDquO q9pnAH1xYve2UU/ki12sb1zBNCPYJNGoVMVoYZ+WBiTxkJRS6r3QcID+4PLSLBrCx6FOaNYxyz+N HNXn1tfTA8+dazSGeer4nW4ht7uWxXKe8ZcSvezFDU3/Z+p+x33qF8Pn4hTSjcYP4oZL0Zy9vG3Q RhJw+4Hx1YmXbpfrBWVqQOuYui18fd1gpad/b4yH9e+H5xWbSO//cFWXzEE/cO+APY0/xbSvI9qd ejSJhSc7iuIlnvzmNk5U33IYSygGzh0yfq6Rzw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10880) `protect data_block RnRPKi9jEml7Lu5FUKT7enOKOvnc34gbCzO7zvUDeHtG+GUynXRcFA+rsSsRPbZpqCjxxTzp5Qun 6WLhdv9L8FEaS9Q1jhKlkGFB55l3+p4qQKTbx5MVd+YUJ7Zu/kMglcFpSUa+KoqO0Z5hy73i0hJN 4NWbm8nVqK+W+TFXMYBWUUv8aiJpbk5rUX8c6NP6epVkFpLlR9+peyLunYEUenGU2yYjoi+w4gtO OAZyJQPBi9ZX8ALBo4pje3GMW8fT+0WHbsQkbKnYPch58C5QTU8YIT2U0NIcMcjLTsDD+GLUXDQU aP3GFY0KrHDO38Ke6b0TZ8R6ZgY4JLkL71PDr2vR6Od+oeWjcrlbRoZ31NGIPlUw/vRIHffn0MhN n6Oe1LnKgVQEoM0cMX2+Y8CNaQziX0WvHey9nc+tDwS6a8IM+cdehwfaq+v9e1w4nHGXFHvMrv7J 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Project-Bonfire/EHA	RTL/Router/credit_based/RTL/New_SHMU_on_Node/shifter.vhd	16	3063	--------------------------------------------------------------------- -- TITLE: Shifter Unit -- AUTHOR: Steve Rhoads ([email protected]) -- Matthias Gruenewald -- DATE CREATED: 2/2/01 -- FILENAME: shifter.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the 32-bit shifter unit. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity shifter is generic(shifter_type : string := "DEFAULT"); port(value : in std_logic_vector(31 downto 0); shift_amount : in std_logic_vector(4 downto 0); shift_func : in shift_function_type; c_shift : out std_logic_vector(31 downto 0)); end; --entity shifter architecture logic of shifter is -- type shift_function_type is ( -- shift_nothing, shift_left_unsigned, -- shift_right_signed, shift_right_unsigned); signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0); signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0); signal fills : std_logic_vector(31 downto 16); begin fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED and value(31) = '1' else "0000000000000000"; shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value; shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L; shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L; shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L; shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L; shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value; shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R; shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R; shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R; shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R; GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or shift_func = SHIFT_RIGHT_SIGNED else ZERO; end generate; AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z'); c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z'); c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z'); end generate; end; --architecture logic	gpl-3.0
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Project-Bonfire/EHA	RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/Arbiter_in_one_hot_with_checkers_with_FI.vhd	3	13338	--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use work.component_pack.all; -- Is this like the old arbiter in the router with handshaking FC ?? entity Arbiter_in is port ( reset: in std_logic; clk: in std_logic; Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot) -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E, err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L, err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W, err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N, err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S, err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E, err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L, err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W, err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N, err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S, err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N, err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic ); end Arbiter_in; architecture behavior of Arbiter_in is component shift_register_serial_in is generic ( REG_WIDTH: integer := 32 ); port ( TCK, reset : in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0) ); end component; ---------------------------------------- -- Signals related to fault injection -- ---------------------------------------- -- Total: 7 bits signal FI_add_sta: std_logic_vector (6 downto 0); -- 5 bits for fault injection location address (ceil of log2(17) = 5) -- 2 bits for type of fault (SA0 or SA1) signal non_faulty_signals: std_logic_vector (16 downto 0); -- 17 bits for internal- and output-related signals (non-faulty) signal faulty_signals: std_logic_vector(16 downto 0); -- 17 bits for internal- and output-related signals (with single stuck-at fault injected in one of them) ---------------------------------------- ---------------------------------------- --TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local); --SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0); --SIGNAL state, state_in : STATE_TYPE := IDLE; SIGNAL state, state_in : STD_LOGIC_VECTOR (5 downto 0) := IDLE; SIGNAL X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic; -- needed for connecting output ports -- of Arbiter_in to checker inputs -- Signal(s) used for creating the chain of injected fault locations -- Total: 17 bits ??!! -- Arbiter_in internal-related signals signal state_faulty, state_in_faulty: std_logic_vector(5 downto 0); -- Arbiter_in output-related signals signal X_N_sig_faulty, X_E_sig_faulty, X_W_sig_faulty, X_S_sig_faulty, X_L_sig_faulty: std_logic; begin ------------------------------------- ---- Related to fault injection ----- ------------------------------------- -- Total: 17 bits -- for X_N, ... , X_L output signals, not sure whether to include them or the signals with _sig suffix in their names ??!! non_faulty_signals <= state & state_in & X_N_sig & X_E_sig & X_W_sig & X_S_sig & X_L_sig; -- Fault injector module instantiation FI: fault_injector generic map(DATA_WIDTH => 17, ADDRESS_WIDTH => 5) port map (data_in=> non_faulty_signals , address => FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals ); -- Extracting faulty values for internal- and output-related signals -- Total: 17 bits state_faulty <= faulty_signals (16 downto 11); state_in_faulty <= faulty_signals (10 downto 5); X_N_sig_faulty <= faulty_signals (4); X_E_sig_faulty <= faulty_signals (3); X_W_sig_faulty <= faulty_signals (2); X_S_sig_faulty <= faulty_signals (1); X_L_sig_faulty <= faulty_signals (0); -- Total: 7 bits SR: shift_register_serial_in generic map(REG_WIDTH => 7) port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta ); ------------------------------------- ------------------------------------- -- Becuase of checkers we did this X_N <= X_N_sig; X_E <= X_E_sig; X_W <= X_W_sig; X_S <= X_S_sig; X_L <= X_L_sig; -- Arbiter_in Checkers module instantiation ARBITER_IN_CHECKERS: Arbiter_in_one_hot_checkers port map ( req_X_N => req_X_N, -- _sig not needed, because it is an input port req_X_E => req_X_E, -- _sig not needed, because it is an input port req_X_W => req_X_W, -- _sig not needed, because it is an input port req_X_S => req_X_S, -- _sig not needed, because it is an input port req_X_L => req_X_L, -- _sig not needed, because it is an input port state => state_faulty, -- _sig not needed, because it is an input port state_in => state_in_faulty, -- _sig not needed, because it is an internal signal X_N => X_N_sig_faulty, X_E => X_E_sig_faulty, X_W => X_W_sig_faulty, X_S => X_S_sig_faulty, X_L => X_L_sig_faulty, -- Checker outputs err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal, err_IDLE_Req_N => err_IDLE_Req_N, err_IDLE_grant_N => err_IDLE_grant_N, err_North_Req_N => err_North_Req_N, err_North_grant_N => err_North_grant_N, err_East_Req_E => err_East_Req_E, err_East_grant_E => err_East_grant_E, err_West_Req_W => err_West_Req_W, err_West_grant_W => err_West_grant_W, err_South_Req_S => err_South_Req_S, err_South_grant_S => err_South_grant_S, err_Local_Req_L => err_Local_Req_L, err_Local_grant_L => err_Local_grant_L, err_IDLE_Req_E => err_IDLE_Req_E, err_IDLE_grant_E => err_IDLE_grant_E, err_North_Req_E => err_North_Req_E, err_North_grant_E => err_North_grant_E, err_East_Req_W => err_East_Req_W, err_East_grant_W => err_East_grant_W, err_West_Req_S => err_West_Req_S, err_West_grant_S => err_West_grant_S, err_South_Req_L => err_South_Req_L, err_South_grant_L => err_South_grant_L, err_Local_Req_N => err_Local_Req_N, err_Local_grant_N => err_Local_grant_N, err_IDLE_Req_W => err_IDLE_Req_W, err_IDLE_grant_W => err_IDLE_grant_W, err_North_Req_W => err_North_Req_W, err_North_grant_W => err_North_grant_W, err_East_Req_S => err_East_Req_S, err_East_grant_S => err_East_grant_S, err_West_Req_L => err_West_Req_L, err_West_grant_L => err_West_grant_L, err_South_Req_N => err_South_Req_N, err_South_grant_N => err_South_grant_N, err_Local_Req_E => err_Local_Req_E, err_Local_grant_E => err_Local_grant_E, err_IDLE_Req_S => err_IDLE_Req_S, err_IDLE_grant_S => err_IDLE_grant_S, err_North_Req_S => err_North_Req_S, err_North_grant_S => err_North_grant_S, err_East_Req_L => err_East_Req_L, err_East_grant_L => err_East_grant_L, err_West_Req_N => err_West_Req_N, err_West_grant_N => err_West_grant_N, err_South_Req_E => err_South_Req_E, err_South_grant_E => err_South_grant_E, err_Local_Req_W => err_Local_Req_W, err_Local_grant_W => err_Local_grant_W, err_IDLE_Req_L => err_IDLE_Req_L, err_IDLE_grant_L => err_IDLE_grant_L, err_North_Req_L => err_North_Req_L, err_North_grant_L => err_North_grant_L, err_East_Req_N => err_East_Req_N, err_East_grant_N => err_East_grant_N, err_West_Req_E => err_West_Req_E, err_West_grant_E => err_West_grant_E, err_South_Req_W => err_South_Req_W, err_South_grant_W => err_South_grant_W, err_Local_Req_S => err_Local_Req_S, err_Local_grant_S => err_Local_grant_S, err_state_in_onehot => err_state_in_onehot, err_no_request_grants => err_no_request_grants, err_request_no_grants => err_request_no_grants, err_no_Req_N_grant_N => err_no_Req_N_grant_N, err_no_Req_E_grant_E => err_no_Req_E_grant_E, err_no_Req_W_grant_W => err_no_Req_W_grant_W, err_no_Req_S_grant_S => err_no_Req_S_grant_S, err_no_Req_L_grant_L => err_no_Req_L_grant_L ); -- Sequential part process (clk, reset)begin if reset = '0' then state <= IDLE; elsif clk'event and clk ='1'then state <= state_in; end if; end process; -- anything below here is pure combinational -- Main Logic of Arbiter_in process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L) begin X_N_sig <= '0'; X_E_sig <= '0'; X_W_sig <= '0'; X_S_sig <= '0'; X_L_sig <= '0'; case state is when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S) -- Here it seems N has the higest priority, is it fine ? if req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; else state_in <= state; end if; when North => if req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; else state_in <= state; end if; when East => if req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; else state_in <= state; end if; when West => if req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; else state_in <= state; end if; when South => if req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; else state_in <= state; end if; when others => if req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; else state_in <= state; end if; end case; end process; end;	gpl-3.0
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hanw/Open-Source-FPGA-Bitcoin-Miner	projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_top.vhd	9	40066	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block N69BdjVBL3zr447/IslHpcQt6uxnKlEGffBeT6O/HPhIhs63hO+yBTBpbZe83b9oQQkb3iO1iekX AN7IS+Oj8A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Q2gSgSjShBThnpN7ocpVeIiupKozmKwVJ1Ka9owDuAS9y4GGTKN6eXAv6ND3rH3bK2m5rmiGc2dQ GqvMSafR3R5aQyLhHV0vE9ItdvwRv/PiR6RGhNqN3zMe7lJ+6AH2FuJN2tV2YbHEWsMpvrS/ozM1 eW8vym4p2Nmkhc0/Q74= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rgf/hTKzUgzPmpRNjQkGUhm/PJt/6MCtp6g+tuGzA135di4HysJDD1buAgwquHID3E9k4d3QtgNV jT7ynZQIoMsXOeKCy7IbT7749cprpDjO1OSVrXQIUUcP3F+gMYUpeL/mjQnfdCEN743AXdvxRnDc gVeJsjU9N64MxSJjbMUJmaddW7RRGip+wgYF1dVschvt86zUuMsTTbRlWaGT8/PVkqEVuyGg73ia FsMYBM8Oi9K0SgUyaUoQqHE7F5kjUaDy36Xg4c9dGuC4pkwoUfWUCMZPrgk/nygkA36gY8gDvz6U 20GmRwirRv5LPFdEu9omr/mfCV1tJE3cL2wf2Q== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block whJ+Mq4deBZDhR4gHJnHCL7JxuEJqNFrWBV6Ksnrye5rfDk+zUSuuj6k9MLoJRMZ9NpZeM9BbEn/ lx4N2zpT3HX4I7gsrzePK4hxagplucoM920UdfcilS8ZUjm0BM3SKRCGqgigpDbBNz1MyRAauRR2 TGMcoxB5Ne7BWv0iUBs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ZsJUyEeEG26LW0tiqAAVmbPXGV42PcJw5qTIOROOgw6cXXLb+KKUvI0qo0WOH27D2IG2UjbZ7zpK 8frckgj+Ei6f1HtE74Q6zFaEuZsJ5XO7FGsTfepBz2OcwZ2tArvysAeDtRyFjKM04fsTIg4zCndt 4Vdzk9lAcb45wumS3BULfbRVGBM9rMHjGQgaLzK9mgTtjibUERm67lPM3rx4Sli2JlzzgXGzw4cK 3Pr3iYBz4/HwqPFPp/u4PgTZaWGmrGjaG+cGYqnmk1B2xC16prjJLhkisxGz7rsLaUay+Y9Qtah2 0cQFnUESovN+P8/1qwaKLu4FVsSMVNnVAlt63g== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 27920) `protect data_block oUSJIenzMgR4/U5g+t0OV9b2YzRljk+3vTKsVmP/tjyeDBM/ad42F+YNEodlggZdHX4Uv/M2JDnX F2Bh7bgipZFJXIBYgIbFzF+CYRIfBn195Mur30OM3bc9K2TZSqS23UiRqfv1EprYZe5PFr99TMIu K3wlq3slmtPtuNGDxh8MIdZXbXSWWC6Qo6DIF9Y+jzxVZda0AhojaG3I0FHVGMyhk3bMbzvvMF+p V9A8JHk5PIvvMCmMJ7BjSRz3Xp7qLx9dM7lFM4W4WlHlKAH9mPMFlrjcbjo4j0iQ6WaA1k9i4O6g uL5tY6I/9Mr3RJuHCOvXOfdLT3aw2OdlbZ7aIqq+i16S7m1mvfWseFPy1exlEdhbh0QPzc+xsbic A19eio1NUsGNUGcqfGiQRGpScFomvtfYsV+riUorPxwf9+xBaw/Fvyxuqb4Qm1qkJAl9g3xCbtZO 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Project-Bonfire/EHA	RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_xilinx.vhd	3	181451	--------------------------------------------------------------------- -- TITLE: Random Access Memory for Xilinx -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 11/06/05 -- FILENAME: ram_xilinx.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements Plasma internal RAM as RAMB for Spartan 3x -- -- Compile the MIPS C and assembly code into "test.axf". -- Run convert.exe to change "test.axf" to "code.txt" which -- will contain the hex values of the opcodes. -- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd", -- to create the "ram_image.vhd" file that will have the opcodes -- correctly placed inside the INIT_00 => strings. -- Then include ram_image.vhd in the simulation/synthesis. -- -- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache -- if the DDR cache is enabled. --------------------------------------------------------------------- -- UPDATED: 09/07/10 Olivier Rinaudo ([email protected]) -- new behaviour: 8KB expandable to 64KB of internal RAM -- -- MEMORY MAP -- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache) -- 2000..3FFF : 8KB 16KB block1 -- 4000..5FFF : 8KB 24KB block2 -- 6000..7FFF : 8KB 32KB block3 -- 8000..9FFF : 8KB 40KB block4 -- A000..BFFF : 8KB 48KB block5 -- C000..DFFF : 8KB 56KB block6 -- E000..FFFF : 8KB 64KB block7 --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.mlite_pack.all; library UNISIM; use UNISIM.vcomponents.all; entity ram is generic(memory_type : string := "DEFAULT"; --Number of 8KB blocks of internal RAM, up to 64KB (1 to 8) block_count : integer := 1); port(clk : in std_logic; enable : in std_logic; reset : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0)); end; --entity ram architecture logic of ram is --type type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0); --Which 8KB block alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13); --Address within a 8KB block (without lower two bits) alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2); --Block enable with 1 bit per memory block signal block_enable: std_logic_vector(7 downto 0); --Block Data Out signal block_do: mem32_vector(7 downto 0); --Remember which block was selected signal block_sel_buf: std_logic_vector(2 downto 0); begin block_enable<= "00000001" when (enable='1') and (block_sel="000") else "00000010" when (enable='1') and (block_sel="001") else "00000100" when (enable='1') and (block_sel="010") else "00001000" when (enable='1') and (block_sel="011") else "00010000" when (enable='1') and (block_sel="100") else "00100000" when (enable='1') and (block_sel="101") else "01000000" when (enable='1') and (block_sel="110") else "10000000" when (enable='1') and (block_sel="111") else "00000000"; proc_blocksel: process (clk, block_sel) is begin if rising_edge(clk) then block_sel_buf <= block_sel; end if; end process; proc_do: process (block_do, block_sel_buf) is begin data_read <= block_do(conv_integer(block_sel_buf)); end process; -- BLOCKS generation block0: if (block_count > 0) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block0 block1: if (block_count > 1) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block1 block2: if (block_count > 2) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block2 block3: if (block_count > 3) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block3 block4: if (block_count > 4) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block4 block5: if (block_count > 5) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block5 block6: if (block_count > 6) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block6 block7: if (block_count > 7) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block7 end; --architecture logic	gpl-3.0
hanw/Open-Source-FPGA-Bitcoin-Miner	projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_extdepth_low_latency.vhd	9	37992	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MZXEstTSOPKn8d5gf+3b10LFSw1L9kvafhezpuljrAF/7ghdUav62CewvwgRX4SemyQaR291yKZu bGSff5WMXg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block kLYSw7WMBCamT+m4atNFnoIZxka3g3JtON0cEggFoebXF71E9cyWqze2b5I3JNud2dq0mGJH86Cd tM81uqf2Xg9WhxjI6FuBts9Vex6Dv6Nj04kCYSbuxNDshz7+gd5ia/7qUkXzcA4guNI5WUF1UBV6 vDQhVHruydJ1Ww/FftE= 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line_length = 76, bytes = 256) `protect key_block QjKrVi7WlHib6bKGT0OGTYs84rdmdleh6oyJXreK+5fkpjerLYbeEOPTjafziaS2WrFtudblMdrM E/LNohWFMg6HI5Be26qj8xWEs0q0AC8WTaKp6gJqvbS6/F7+AKuVdcIPelTrXKZOdyuOFLF64ju3 ybXKkvB/gCzTX5yFRChHQ+LRxfg2IkNNBF5JGaz+YyvIs2ar2kXSbUjGTl0tOC3QQ0oOO/oHlU7y bZvJ/NYdMJGcDDpZOufURSkyS0wkF3aAOdsXQRalncGVFQfbyohwEc4ZKnhd4xUEvAdlWzeSxdvO 1KZnNrgRbhhqLJkrU6oEQC+8G6eTCrAD3PT+hw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26384) `protect data_block T5hEEpYZDyI6IFna9r87axT1ja05gx9M51V3cKofAcPT3uPoqwWN9CdcaQ2czOfPxeq+BwxpiZmk 5ouxPXHBQi1Ey8mKyAPBofva6jhS6BEN7y8ZjdjeMWhcHepRGx5Z8s/XKWl+D6mtihVlJ7U0D+5S g/s6UKhwUHFsJTM45xxzVXqVWq9pOsioMGIlv7jk4HCnZjiPHFdhSbI+jbgKRnfbJHaiP8ega6VB A9DBqqZmM3rkg0V3MC0j6bJ4lyA/NCna8zJibq7G+p9HZ+7/nO/HvZNJp3h3L8u5JdSWbhOKwXiJ UjoiS5BhuPxd7kv859ById04Ss18OJp5Nd+Q/BOV0USYrelqdZ2XMZoMzhRTVJDdEhDPovAr2D7f zYYUEhvx/z5e1GqnTTL4bhD7xRYamBOyhCRFs35KwoemFk2UvrzJBqSWc4ceI5DQaozOXcDd/41u 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julioamerico/prj_crc_ip	src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/acb_96_bit/_primary.vhd	3	2560	library verilog; use verilog.vl_types.all; entity acb_96_bit is generic( ANALOG_QUAD_NUM : integer := 6; ACB_BYTES_NUM_PER_QUAD: integer := 12; WARNING_MSGS_ON : integer := 1 ); port( ACB_RST : in vl_logic; ACB_WEN : in vl_logic; ACB_ADDR : in vl_logic_vector(7 downto 0); ACB_WDATA : in vl_logic_vector(7 downto 0); ACB_RDATA : out vl_logic_vector(7 downto 0); AQO_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQO_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQO_AC_CONFIG : out vl_logic_vector(7 downto 0); AQO_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ0_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ1_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ1_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ1_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ1_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ1_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ2_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ2_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ2_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ2_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ2_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ3_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ3_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ3_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ3_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ3_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ4_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ4_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ4_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ4_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ4_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ5_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ5_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ5_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ5_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ5_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); DAC0_CONFIG : out vl_logic_vector(1 downto 0); DAC1_CONFIG : out vl_logic_vector(1 downto 0); DAC2_CONFIG : out vl_logic_vector(1 downto 0) ); end acb_96_bit;	gpl-3.0
hanw/Open-Source-FPGA-Bitcoin-Miner	projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_regs_fwd.vhd	9	9351	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block la25uVBWzC1l+JHhEL6c+Ts7V7z+YIo/kFZc/YoRuvF5aU3MaKWYyPlXeCJ89353nfhHkbdLXV4F nVVuxP9FyQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block nFg9pYQINwZA2M/ydTMPKxrCQrNDHt3RlR7cY6SpFxjoLHLbXhL1bAq6n1q9+Q2qjz6EazfBZ93K U0YpNGqnr+nqc2C5nb40zW2yQvfS4Rbw8mxQ73/lihHzruwr8kDVsMtt0iBxWrTieJOIk8/NeR2G +o/W4ndnrUAG/PfyIlA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block xuoFtB1eDGz1GlFErAZaPAS93bvbE5a9X5zV34MxLp8Ua9ky7RLKZwzWPuhW7tLpYh2ua4RSttmk dPsfayFAITrAU/dQAVWx4DUGO5t03cUgdN7ppPZLi5GX/MA95IxftPz2MIzhpH84Js1AO4luqQQc 5QxN9DH7mAIM0GVXwc0f48uoH19eD0/e7ciNMenZDiYHLFC4ACagzRoMnKlK4ZA6RSc1NIW6GfKa 8M1WYwzf0B7d/GeCgTpBG0FjkWha1+PPC3tNpTIzfUCoG9hESZTSV5bYv92St+WQ6sNnwG37tVqa iLDinljZPypL6xhmjimXUoCa+m62LGDkqdf4vQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P0dE5V9VUBP3x9gSL+lY/6kDeo+z3sDkMBilzcCbklSLv8Zh2uayd3oG98fq3BDs4Zyl2NIOR+4/ c3oQeFRXzhjxpRyK4NBrcY5gN80k3yvSH2WYV0Ha2x+39Jj8yQO/MunO8ZTCspwLwcHXnNHZNsHb SEAg+QS9ELaciwfw5D8= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block t3we8GV+pUi+tUpE/sSsfp+bLGtsUa2GACR/MBRAx8Rup76KD0FtZguzgORfNW3U/RRXivPYEwx2 YnVAkNK5JSRAyAcNUOh1nwJNd4vOCmRpVk4XeDn644n3Wza8R6vE4ZHxwvABYxMsztUi1tBqdTX+ 5G7mxdIbl8hLmHjOn9mWgfRtY1ZgsgeotbJfe2JmJP+lSUzhj6TeOhpeosvrxGHDW+OoVI8+21dZ rSaYKHGuWyyHJi/k2LWmFCszrm7zzz3izU7DalILlpEYm85eTWmehGHj/pJE4Boq4iEfeuZjagdl fMfJN7hju7whxsbPHrjRb1nqFZnUndHNTjLyvA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5184) `protect data_block 2hUzsBKKef+bDBf3jkL2Gx+BzRzHYqVbyIo6nIHQDrqRm8IOShRPRptfn0tIq7maZ/zVkOWEhE6E 8psQfcX0R7jREKV4cRPCaW830fPaMTZ+GcwNG5kEGhhMeBfPTgLv7n3kaVP9FTNssB5XQU/c0PpA X+WpwO6JEdtbJ/SoItPEa0A4P9wgUm+p3sqtElPvHnvqrZ+YwD34vuZPqSKwd61KFdg8YP4QIbdu c6UopFZO9ZMMmr8joqNg1CpRj50T9N35h0KcEl67sdfGAB3MMuOHE6IY2milOyGMpNT44RPO64R6 fcVPeQVezCysH1FkvAohWrr8qcVuV7UYDmkMy7cGkjkFhOMWMysfVsWuEmRfNqIhx9Rc9LoVs3pW 58EhruXWoW2y3rOgVmDVP11+D0MnTN8Bh6GLstrZWYlMx/YrlLA3pohNGUPW4bCfl1i001y7WyrK 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Project-Bonfire/EHA	RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/uart.vhd	6	7018	--------------------------------------------------------------------- -- TITLE: UART -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 5/29/02 -- FILENAME: uart.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the UART. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; use ieee.std_logic_textio.all; use ieee.std_logic_unsigned.all; use std.textio.all; use work.mlite_pack.all; entity uart is generic(log_file : string := "UNUSED"); port(clk : in std_logic; reset : in std_logic; enable_read : in std_logic; enable_write : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); uart_read : in std_logic; uart_write : out std_logic; busy_write : out std_logic; data_avail : out std_logic); end; --entity uart architecture logic of uart is signal delay_write_reg : std_logic_vector(9 downto 0); signal bits_write_reg : std_logic_vector(3 downto 0); signal data_write_reg : std_logic_vector(8 downto 0); signal delay_read_reg : std_logic_vector(9 downto 0); signal bits_read_reg : std_logic_vector(3 downto 0); signal data_read_reg : std_logic_vector(7 downto 0); signal data_save_reg : std_logic_vector(17 downto 0); signal busy_write_sig : std_logic; signal read_value_reg : std_logic_vector(6 downto 0); signal uart_read2 : std_logic; begin uart_proc: process(clk, reset, enable_read, enable_write, data_in, data_write_reg, bits_write_reg, delay_write_reg, data_read_reg, bits_read_reg, delay_read_reg, data_save_reg, read_value_reg, uart_read2, busy_write_sig, uart_read) constant COUNT_VALUE : std_logic_vector(9 downto 0) := -- "0100011110"; --33MHz/2/57600Hz = 0x11e -- "1101100100"; --50MHz/57600Hz = 0x364 "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2 -- "0011011001"; --12.5MHz/57600Hz = 0xd9 -- "0000000100"; --for debug (shorten read_value_reg) begin uart_read2 <= read_value_reg(read_value_reg'length - 1); if reset = '1' then data_write_reg <= ZERO(8 downto 1) & '1'; bits_write_reg <= "0000"; delay_write_reg <= ZERO(9 downto 0); read_value_reg <= ONES(read_value_reg'length-1 downto 0); data_read_reg <= ZERO(7 downto 0); bits_read_reg <= "0000"; delay_read_reg <= ZERO(9 downto 0); data_save_reg <= ZERO(17 downto 0); elsif rising_edge(clk) then --Write UART if bits_write_reg = "0000" then --nothing left to write? if enable_write = '1' then delay_write_reg <= ZERO(9 downto 0); --delay before next bit bits_write_reg <= "1010"; --number of bits to write data_write_reg <= data_in & '0'; --remember data & start bit end if; else if delay_write_reg /= COUNT_VALUE then delay_write_reg <= delay_write_reg + 1; --delay before next bit else delay_write_reg <= ZERO(9 downto 0); --reset delay bits_write_reg <= bits_write_reg - 1; --bits left to write data_write_reg <= '1' & data_write_reg(8 downto 1); end if; end if; --Average uart_read signal if uart_read = '1' then if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then read_value_reg <= read_value_reg + 1; end if; else if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then read_value_reg <= read_value_reg - 1; end if; end if; --Read UART if delay_read_reg = ZERO(9 downto 0) then --done delay for read? if bits_read_reg = "0000" then --nothing left to read? if uart_read2 = '0' then --wait for start bit delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period bits_read_reg <= "1001"; --bits left to read end if; else delay_read_reg <= COUNT_VALUE; --initialize delay bits_read_reg <= bits_read_reg - 1; --bits left to read data_read_reg <= uart_read2 & data_read_reg(7 downto 1); end if; else delay_read_reg <= delay_read_reg - 1; --delay end if; --Control character buffer if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then if data_save_reg(8) = '0' or (enable_read = '1' and data_save_reg(17) = '0') then --Empty buffer data_save_reg(8 downto 0) <= '1' & data_read_reg; else --Second character in buffer data_save_reg(17 downto 9) <= '1' & data_read_reg; if enable_read = '1' then data_save_reg(8 downto 0) <= data_save_reg(17 downto 9); end if; end if; elsif enable_read = '1' then data_save_reg(17) <= '0'; --data_available data_save_reg(8 downto 0) <= data_save_reg(17 downto 9); end if; end if; --rising_edge(clk) uart_write <= data_write_reg(0); if bits_write_reg /= "0000" -- Comment out the following line for full UART simulation (much slower) and log_file = "UNUSED" then busy_write_sig <= '1'; else busy_write_sig <= '0'; end if; busy_write <= busy_write_sig; data_avail <= data_save_reg(8); data_out <= data_save_reg(7 downto 0); end process; --uart_proc -- synthesis_off uart_logger: if log_file /= "UNUSED" generate uart_proc: process(clk, enable_write, data_in) file store_file : text open write_mode is log_file; variable hex_file_line : line; variable c : character; variable index : natural; variable line_length : natural := 0; begin if rising_edge(clk) and busy_write_sig = '0' then if enable_write = '1' then index := conv_integer(data_in(6 downto 0)); if index /= 10 then c := character'val(index); write(hex_file_line, c); line_length := line_length + 1; end if; if index = 10 or line_length >= 72 then --The following line may have to be commented out for synthesis writeline(store_file, hex_file_line); line_length := 0; end if; end if; --uart_sel end if; --rising_edge(clk) end process; --uart_proc end generate; --uart_logger -- synthesis_on end; --architecture logic	gpl-3.0
freecores/usb_fpga_1_11	examples/usb-fpga-1.15y/ucecho/fpga/ucecho.vhd	6	737	library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out std_logic_vector(7 downto 0); CS : in std_logic; CLK : in std_logic -- SCL : in std_logic; -- SDA : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z'); dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; end if; end process dpUCECHO; end RTL;	gpl-3.0
mistryalok/Zedboard	learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_PaintMask_32_0_1080_1920_s.vhd	2	24811	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter_PaintMask_32_0_1080_1920_s is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_0_V_empty_n : IN STD_LOGIC; p_src_data_stream_0_V_read : OUT STD_LOGIC; p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_1_V_empty_n : IN STD_LOGIC; p_src_data_stream_1_V_read : OUT STD_LOGIC; p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_2_V_empty_n : IN STD_LOGIC; p_src_data_stream_2_V_read : OUT STD_LOGIC; p_mask_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_mask_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_mask_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_mask_data_stream_V_empty_n : IN STD_LOGIC; p_mask_data_stream_V_read : OUT STD_LOGIC; p_dst_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_dst_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_0_V_full_n : IN STD_LOGIC; p_dst_data_stream_0_V_write : OUT STD_LOGIC; p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_1_V_full_n : IN STD_LOGIC; p_dst_data_stream_1_V_write : OUT STD_LOGIC; p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_2_V_full_n : IN STD_LOGIC; p_dst_data_stream_2_V_write : OUT STD_LOGIC ); end; architecture behav of image_filter_PaintMask_32_0_1080_1920_s is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010"; constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100"; constant ap_ST_st6_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000"; constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111"; signal ap_done_reg : STD_LOGIC := '0'; signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_23 : BOOLEAN; signal p_4_reg_194 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_bdd_71 : BOOLEAN; signal exitcond4_fu_210_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_83 : BOOLEAN; signal i_V_fu_215_p2 : STD_LOGIC_VECTOR (10 downto 0); signal i_V_reg_280 : STD_LOGIC_VECTOR (10 downto 0); signal exitcond_fu_225_p2 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond_reg_285 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC; signal ap_sig_bdd_94 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_sig_bdd_111 : BOOLEAN; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppstg_exitcond_reg_285_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_bdd_125 : BOOLEAN; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal j_V_fu_230_p2 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_39_fu_242_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_39_reg_294 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_40_fu_250_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_40_reg_299 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_41_fu_258_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_41_reg_304 : STD_LOGIC_VECTOR (7 downto 0); signal p_s_reg_183 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_cseq_ST_st6_fsm_3 : STD_LOGIC; signal ap_sig_bdd_158 : BOOLEAN; signal p_cast_fu_206_p1 : STD_LOGIC_VECTOR (11 downto 0); signal p_4_cast_fu_221_p1 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_37_fu_236_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0); begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_done_reg assign process. -- ap_done_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_done_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_continue)) then ap_done_reg <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond4_fu_210_p2 = ap_const_lv1_0)))) then ap_done_reg <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (exitcond_fu_225_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; end if; end if; end if; end process; -- p_4_reg_194 assign process. -- p_4_reg_194_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (exitcond_fu_225_p2 = ap_const_lv1_0))) then p_4_reg_194 <= j_V_fu_230_p2; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0))) then p_4_reg_194 <= ap_const_lv11_0; end if; end if; end process; -- p_s_reg_183 assign process. -- p_s_reg_183_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_71))) then p_s_reg_183 <= ap_const_lv11_0; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_3)) then p_s_reg_183 <= i_V_reg_280; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then ap_reg_ppstg_exitcond_reg_285_pp0_it1 <= exitcond_reg_285; exitcond_reg_285 <= exitcond_fu_225_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then i_V_reg_280 <= i_V_fu_215_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then tmp_39_reg_294 <= tmp_39_fu_242_p3; tmp_40_reg_299 <= tmp_40_fu_250_p3; tmp_41_reg_304 <= tmp_41_fu_258_p3; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_71, exitcond4_fu_210_p2, exitcond_fu_225_p2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not(ap_sig_bdd_71)) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if (not((exitcond4_fu_210_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_pp0_stg0_fsm_2 => if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then ap_NS_fsm <= ap_ST_st6_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_st6_fsm_3 => ap_NS_fsm <= ap_ST_st2_fsm_1; when others => ap_NS_fsm <= "XXXX"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_done_reg, exitcond4_fu_210_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond4_fu_210_p2 = ap_const_lv1_0))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(exitcond4_fu_210_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond4_fu_210_p2 = ap_const_lv1_0)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_111 assign process. -- ap_sig_bdd_111_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_mask_data_stream_V_empty_n, exitcond_reg_285) begin ap_sig_bdd_111 <= (((p_src_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_reg_285 = ap_const_lv1_0)) or ((exitcond_reg_285 = ap_const_lv1_0) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_reg_285 = ap_const_lv1_0) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_reg_285 = ap_const_lv1_0) and (p_mask_data_stream_V_empty_n = ap_const_logic_0))); end process; -- ap_sig_bdd_125 assign process. -- ap_sig_bdd_125_assign_proc : process(p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_reg_ppstg_exitcond_reg_285_pp0_it1) begin ap_sig_bdd_125 <= (((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1)) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0))); end process; -- ap_sig_bdd_158 assign process. -- ap_sig_bdd_158_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_158 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_23 assign process. -- ap_sig_bdd_23_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_71 assign process. -- ap_sig_bdd_71_assign_proc : process(ap_start, ap_done_reg) begin ap_sig_bdd_71 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1)); end process; -- ap_sig_bdd_83 assign process. -- ap_sig_bdd_83_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_83 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_bdd_94 assign process. -- ap_sig_bdd_94_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_94 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. -- ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_94) begin if (ap_sig_bdd_94) then ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23) begin if (ap_sig_bdd_23) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_83) begin if (ap_sig_bdd_83) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st6_fsm_3 assign process. -- ap_sig_cseq_ST_st6_fsm_3_assign_proc : process(ap_sig_bdd_158) begin if (ap_sig_bdd_158) then ap_sig_cseq_ST_st6_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_st6_fsm_3 <= ap_const_logic_0; end if; end process; exitcond4_fu_210_p2 <= "1" when (p_cast_fu_206_p1 = p_dst_rows_V_read) else "0"; exitcond_fu_225_p2 <= "1" when (p_4_cast_fu_221_p1 = p_dst_cols_V_read) else "0"; i_V_fu_215_p2 <= std_logic_vector(unsigned(p_s_reg_183) + unsigned(ap_const_lv11_1)); j_V_fu_230_p2 <= std_logic_vector(unsigned(p_4_reg_194) + unsigned(ap_const_lv11_1)); p_4_cast_fu_221_p1 <= std_logic_vector(resize(unsigned(p_4_reg_194),12)); p_cast_fu_206_p1 <= std_logic_vector(resize(unsigned(p_s_reg_183),12)); p_dst_data_stream_0_V_din <= tmp_39_reg_294; -- p_dst_data_stream_0_V_write assign process. -- p_dst_data_stream_0_V_write_assign_proc : process(ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_reg_285_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_dst_data_stream_0_V_write <= ap_const_logic_1; else p_dst_data_stream_0_V_write <= ap_const_logic_0; end if; end process; p_dst_data_stream_1_V_din <= tmp_40_reg_299; -- p_dst_data_stream_1_V_write assign process. -- p_dst_data_stream_1_V_write_assign_proc : process(ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_reg_285_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_dst_data_stream_1_V_write <= ap_const_logic_1; else p_dst_data_stream_1_V_write <= ap_const_logic_0; end if; end process; p_dst_data_stream_2_V_din <= tmp_41_reg_304; -- p_dst_data_stream_2_V_write assign process. -- p_dst_data_stream_2_V_write_assign_proc : process(ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_reg_285_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_dst_data_stream_2_V_write <= ap_const_logic_1; else p_dst_data_stream_2_V_write <= ap_const_logic_0; end if; end process; -- p_mask_data_stream_V_read assign process. -- p_mask_data_stream_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_mask_data_stream_V_read <= ap_const_logic_1; else p_mask_data_stream_V_read <= ap_const_logic_0; end if; end process; -- p_src_data_stream_0_V_read assign process. -- p_src_data_stream_0_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_src_data_stream_0_V_read <= ap_const_logic_1; else p_src_data_stream_0_V_read <= ap_const_logic_0; end if; end process; -- p_src_data_stream_1_V_read assign process. -- p_src_data_stream_1_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_src_data_stream_1_V_read <= ap_const_logic_1; else p_src_data_stream_1_V_read <= ap_const_logic_0; end if; end process; -- p_src_data_stream_2_V_read assign process. -- p_src_data_stream_2_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_src_data_stream_2_V_read <= ap_const_logic_1; else p_src_data_stream_2_V_read <= ap_const_logic_0; end if; end process; tmp_37_fu_236_p2 <= "1" when (p_mask_data_stream_V_dout = ap_const_lv8_0) else "0"; tmp_39_fu_242_p3 <= p_src_data_stream_0_V_dout when (tmp_37_fu_236_p2(0) = '1') else ap_const_lv8_FF; tmp_40_fu_250_p3 <= p_src_data_stream_1_V_dout when (tmp_37_fu_236_p2(0) = '1') else ap_const_lv8_0; tmp_41_fu_258_p3 <= p_src_data_stream_2_V_dout when (tmp_37_fu_236_p2(0) = '1') else ap_const_lv8_0; end behav;	gpl-3.0
mistryalok/Zedboard	learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/lib_fifo_v1_0/ca55fafe/hdl/src/vhdl/sync_fifo_fg.vhd	7	69796	-- sync_fifo_fg.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: sync_fifo_fg.vhd -- -- Description: -- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new -- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on -- the fly" call of FIFO Generator during design implementation. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- sync_fifo_fg.vhd -- \| -- \|-- fifo_generator_v4_3 -- \| -- \|-- fifo_generator_v9_3 -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- Revision: $Revision: 1.5.2.68 $ -- Date: $1/16/2008$ -- -- History: -- DET 1/16/2008 Initial Version -- -- DET 7/30/2008 for EDK 11.1 -- ~~~~~~ -- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3 -- ^^^^^^ -- -- MSH and DET 3/2/2009 For Lava SP2 -- ~~~~~~ -- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6 -- devices. -- - IfGen used so that legacy FPGA families still use Fifo Generator -- version 4.3. -- ^^^^^^ -- -- DET 4/9/2009 EDK 11.2 -- ~~~~~~ -- - Replaced FIFO Generator version 5.1 with 5.2. -- ^^^^^^ -- -- -- DET 2/9/2010 for EDK 12.1 -- ~~~~~~ -- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3. -- ^^^^^^ -- -- DET 3/10/2010 For EDK 12.x -- ~~~~~~ -- -- Per CR553307 -- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1. -- ^^^^^^ -- -- DET 6/18/2010 EDK_MS2 -- ~~~~~~ -- -- Per IR565916 -- - Added derivative part type checks for S6 or V6. -- ^^^^^^ -- -- DET 8/30/2010 EDK_MS4 -- ~~~~~~ -- -- Per CR573867 -- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2. -- - Added all of the AXI parameters and ports. They are not used -- in this application. -- - Updated method for derivative part support using new family -- aliasing function in family_support.vhd. -- - Incorporated an implementation to deal with unsupported FPGA -- parts passed in on the C_FAMILY parameter. -- ^^^^^^ -- -- DET 10/4/2010 EDK 13.1 -- ~~~~~~ -- - Updated the FIFO Generator version from V7.2 to 7.3. -- ^^^^^^ -- -- DET 12/8/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR586109 -- - Updated the FIFO Generator version from V7.3 to 8.1. -- ^^^^^^ -- -- DET 3/2/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR595473 -- - Update to use fifo_generator_v8_2 -- ^^^^^^ -- -- -- RBODDU 08/18/2011 EDK 13.3 -- ~~~~~~ -- - Update to use fifo_generator_v8_3 -- ^^^^^^ -- -- RBODDU 06/07/2012 EDK 14.2 -- ~~~~~~ -- - Update to use fifo_generator_v9_1 -- ^^^^^^ -- RBODDU 06/11/2012 EDK 14.4 -- ~~~~~~ -- - Update to use fifo_generator_v9_2 -- ^^^^^^ -- RBODDU 07/12/2012 EDK 14.5 -- ~~~~~~ -- - Update to use fifo_generator_v9_3 -- ^^^^^^ -- RBODDU 07/12/2012 EDK 14.5 -- ~~~~~~ -- - Update to use fifo_generator_v12_0 -- - Added sleep, wr_rst_busy, and rd_rst_busy signals -- - Changed FULL_FLAGS_RST_VAL to '1' -- ^^^^^^ -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library fifo_generator_v12_0; use fifo_generator_v12_0.all; ------------------------------------------------------------------------------- entity sync_fifo_fg is generic ( C_FAMILY : String := "virtex5"; -- new for FIFO Gen C_DCOUNT_WIDTH : integer := 4 ; C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo C_HAS_DCOUNT : integer := 1 ; C_HAS_RD_ACK : integer := 0 ; C_HAS_RD_ERR : integer := 0 ; C_HAS_WR_ACK : integer := 0 ; C_HAS_WR_ERR : integer := 0 ; C_HAS_ALMOST_FULL : integer := 0 ; C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM C_PORTS_DIFFER : integer := 0 ; C_RD_ACK_LOW : integer := 0 ; C_USE_EMBEDDED_REG : integer := 0 ; C_READ_DATA_WIDTH : integer := 16; C_READ_DEPTH : integer := 16; C_RD_ERR_LOW : integer := 0 ; C_WR_ACK_LOW : integer := 0 ; C_WR_ERR_LOW : integer := 0 ; C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through C_WRITE_DATA_WIDTH : integer := 16; C_WRITE_DEPTH : integer := 16; C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8 ); port ( Clk : in std_logic; Sinit : in std_logic; Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0); Wr_en : in std_logic; Rd_en : in std_logic; Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0); Almost_full : out std_logic; Full : out std_logic; Empty : out std_logic; Rd_ack : out std_logic; Wr_ack : out std_logic; Rd_err : out std_logic; Wr_err : out std_logic; Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0) ); end entity sync_fifo_fg; architecture implementation of sync_fifo_fg is -- Function delarations function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; end function log2; ------------------------------------------------------------------- -- Function -- -- Function Name: GetMaxDepth -- -- Function Description: -- Returns the largest value of either Write depth or Read depth -- requested by input parameters. -- ------------------------------------------------------------------- function GetMaxDepth (rd_depth : integer; wr_depth : integer) return integer is Variable max_value : integer := 0; begin If (rd_depth < wr_depth) Then max_value := wr_depth; else max_value := rd_depth; End if; return(max_value); end function GetMaxDepth; ------------------------------------------------------------------- -- Function -- -- Function Name: GetMemType -- -- Function Description: -- Generates the required integer value for the FG instance assignment -- of the C_MEMORY_TYPE parameter. Derived from -- the input memory type parameter C_MEMORY_TYPE. -- -- FIFO Generator values -- 0 = Any -- 1 = BRAM -- 2 = Distributed Memory -- 3 = Shift Registers -- ------------------------------------------------------------------- function GetMemType (inputmemtype : integer) return integer is Variable memtype : Integer := 0; begin If (inputmemtype = 0) Then -- distributed Memory memtype := 2; else memtype := 1; -- BRAM End if; return(memtype); end function GetMemType; -- Constant Declarations ---------------------------------------------- -- changing this to C_FAMILY Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd -- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily")); -- lib_fifo supports all families Constant FAMILY_IS_SUPPORTED : boolean := true; --Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and -- FAMILY_IS_SUPPORTED; --Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and -- FAMILY_IS_SUPPORTED; -- Calculate associated FIFO characteristics Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH); Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1; Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1; -- Get the integer value for a Block memory type fifo generator call Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE); -- Set the required integer value for the FG instance assignment -- of the C_IMPLEMENTATION_TYPE parameter. Derived from -- the input memory type parameter C_MEMORY_TYPE. -- -- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO) -- 1 = Common Clock Shift Register (Synchronous FIFO) -- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO) -- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls -- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls -- Constant FG_IMP_TYPE : integer := 0; -- The programable thresholds are not used so this is housekeeping. Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3; Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4; -- Constant zeros for programmable threshold inputs signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- Signals signal sig_full : std_logic; signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0); signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0); --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal ALMOST_EMPTY : std_logic; signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0); signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0); signal PROG_FULL : std_logic; signal PROG_EMPTY : std_logic; signal SBITERR : std_logic; signal DBITERR : std_logic; signal WR_RST_BUSY : std_logic; signal RD_RST_BUSY : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BID : std_logic_vector(3 DOWNTO 0); signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_BUSER : std_logic_vector(0 downto 0); signal S_AXI_BVALID : std_logic; -- AXI Full/Lite Master Write Channel (Read side) signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0); signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWUSER : std_logic_vector(0 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_WID : std_logic_vector(3 DOWNTO 0); signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0); signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0); signal M_AXI_WLAST : std_logic; signal M_AXI_WUSER : std_logic_vector(0 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_BREADY : std_logic; -- AXI Full/Lite Slave Read Channel (Write side) signal S_AXI_ARREADY : std_logic; signal S_AXI_RID : std_logic_vector(3 DOWNTO 0); signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0); signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_RLAST : std_logic; signal S_AXI_RUSER : std_logic_vector(0 downto 0); signal S_AXI_RVALID : std_logic; -- AXI Full/Lite Master Read Channel (Read side) signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0); signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARUSER : std_logic_vector(0 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_RREADY : std_logic; -- AXI Streaming Slave Signals (Write side) signal S_AXIS_TREADY : std_logic; -- AXI Streaming Master Signals (Read side) signal M_AXIS_TVALID : std_logic; signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0); signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TLAST : std_logic; signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0); signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_SBITERR : std_logic; signal AXI_AW_DBITERR : std_logic; signal AXI_AW_OVERFLOW : std_logic; signal AXI_AW_UNDERFLOW : std_logic; signal AXI_AW_PROG_FULL : STD_LOGIC; signal AXI_AW_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Data Channel Signals signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_SBITERR : std_logic; signal AXI_W_DBITERR : std_logic; signal AXI_W_OVERFLOW : std_logic; signal AXI_W_UNDERFLOW : std_logic; signal AXI_W_PROG_FULL : STD_LOGIC; signal AXI_W_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Response Channel Signals signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_SBITERR : std_logic; signal AXI_B_DBITERR : std_logic; signal AXI_B_OVERFLOW : std_logic; signal AXI_B_UNDERFLOW : std_logic; signal AXI_B_PROG_FULL : STD_LOGIC; signal AXI_B_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Address Channel Signals signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_SBITERR : std_logic; signal AXI_AR_DBITERR : std_logic; signal AXI_AR_OVERFLOW : std_logic; signal AXI_AR_UNDERFLOW : std_logic; signal AXI_AR_PROG_FULL : STD_LOGIC; signal AXI_AR_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Data Channel Signals signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_SBITERR : std_logic; signal AXI_R_DBITERR : std_logic; signal AXI_R_OVERFLOW : std_logic; signal AXI_R_UNDERFLOW : std_logic; signal AXI_R_PROG_FULL : STD_LOGIC; signal AXI_R_PROG_EMPTY : STD_LOGIC; -- AXI Streaming FIFO Related Signals signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_SBITERR : std_logic; signal AXIS_DBITERR : std_logic; signal AXIS_OVERFLOW : std_logic; signal AXIS_UNDERFLOW : std_logic; signal AXIS_PROG_FULL : STD_LOGIC; signal AXIS_PROG_EMPTY : STD_LOGIC; begin --(architecture implementation) ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_FAMILY -- -- If Generate Description: -- This IfGen is implemented if an unsupported FPGA family -- is passed in on the C_FAMILY parameter, -- ------------------------------------------------------------ -- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate -- begin -- synthesis translate_off ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_ASSERTION -- -- Process Description: -- Generate a simulation error assertion for an unsupported -- FPGA family string passed in on the C_FAMILY parameter. -- ------------------------------------------------------------- -- DO_ASSERTION : process -- begin -- Wait until second rising clock edge to issue assertion -- Wait until Clk = '1'; -- wait until Clk = '0'; -- Wait until Clk = '1'; -- Report an error in simulation environment -- assert FALSE report "******** UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!" -- severity ERROR; -- Wait;-- halt this process -- end process DO_ASSERTION; -- synthesis translate_on -- Tie outputs to logic low or logic high as required -- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Almost_full <= '0' ; -- : out std_logic; -- Full <= '0' ; -- : out std_logic; -- Empty <= '1' ; -- : out std_logic; -- Rd_ack <= '0' ; -- : out std_logic; -- Wr_ack <= '0' ; -- : out std_logic; -- Rd_err <= '1' ; -- : out std_logic; -- Wr_err <= '1' ; -- : out std_logic -- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0); -- end generate GEN_NO_FAMILY; ------------------------------------------------------------ -- If Generate -- -- Label: V6_S6_AND_LATER -- -- If Generate Description: -- This IfGen implements the fifo using fifo_generator_v9_3 -- when the designated FPGA Family is Spartan-6, Virtex-6 or -- later. -- ------------------------------------------------------------ FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate begin UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu") generate begin Full <= sig_full or WR_RST_BUSY; end generate UltraScale_device; Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu") generate begin Full <= sig_full; end generate Series7_device; -- Create legacy data count by concatonating the Full flag to the -- MS Bit position of the FIFO data count -- This is per the Fifo Generator Migration Guide sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt; Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto FGEN_CNT_WIDTH-C_DCOUNT_WIDTH); ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen FIFO Generator Call module for -- BRAM implementations of a legacy Sync FIFO -- ------------------------------------------------------------------------------- I_SYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0 generic map( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ??? C_DEFAULT_VALUE => "BlankString", -- what to do here ??? C_DIN_WIDTH => C_WRITE_DATA_WIDTH, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => C_READ_DATA_WIDTH, C_ENABLE_RLOCS => 0, -- not supported C_FAMILY => FAMILY_TO_USE, C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 1, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => C_HAS_DCOUNT, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => C_HAS_WR_ERR, C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO C_HAS_RD_RST => 0, -- not used for sync FIFO C_HAS_RST => 0, -- not used for sync FIFO C_HAS_SRST => 1, C_HAS_UNDERFLOW => C_HAS_RD_ERR, C_HAS_VALID => C_HAS_RD_ACK, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO C_HAS_WR_RST => 0, -- not used for sync FIFO C_IMPLEMENTATION_TYPE => FG_IMP_TYPE, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => FG_MEM_TYPE, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => C_WR_ERR_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, C_RD_DEPTH => MAX_DEPTH, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH, C_UNDERFLOW_LOW => C_RD_ERR_LOW, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129 C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => C_RD_ACK_LOW, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, C_WR_DEPTH => MAX_DEPTH, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_AXI_LEN_WIDTH => 8, -- : integer := 8; C_AXI_LOCK_WIDTH => 2, -- : integer := 2; C_HAS_AXI_ID => 0, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) port map( backup => '0', backup_marker => '0', clk => Clk, rst => '0', srst => Sinit, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => Din, wr_en => Wr_en, rd_en => Rd_en, prog_empty_thresh => PROG_RDTHRESH_ZEROS, prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, prog_full_thresh => PROG_WRTHRESH_ZEROS, prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, int_clk => '0', injectdbiterr => '0', -- new FG 5.1/5.2 injectsbiterr => '0', -- new FG 5.1/5.2 sleep => '0', dout => Dout, full => sig_full, almost_full => Almost_full, wr_ack => Wr_ack, overflow => Wr_err, empty => Empty, almost_empty => ALMOST_EMPTY, valid => Rd_ack, underflow => Rd_err, data_count => sig_prim_fg_datacnt, rd_data_count => RD_DATA_COUNT, wr_data_count => WR_DATA_COUNT, prog_full => PROG_FULL, prog_empty => PROG_EMPTY, sbiterr => SBITERR, dbiterr => DBITERR, wr_rst_busy => WR_RST_BUSY, rd_rst_busy => RD_RST_BUSY, -- AXI Global Signal m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); end generate FAMILY_SUPPORTED; end implementation;	gpl-3.0
davidhorrocks/1541UltimateII	fpga/io/uart_lite/vhdl_source/uart_peripheral.vhd	5	4651	library ieee; use ieee.std_logic_1164.all; entity uart_peripheral is generic ( tx_fifo : boolean := true; divisor : natural := 417 ); port ( clock : in std_logic; reset : in std_logic; bus_select : in std_logic; bus_write : in std_logic; bus_addr : in std_logic_vector(1 downto 0); bus_wdata : in std_logic_vector(7 downto 0); bus_rdata : out std_logic_vector(7 downto 0); uart_irq : out std_logic; txd : out std_logic; rxd : in std_logic ); end uart_peripheral; architecture gideon of uart_peripheral is signal dotx : std_logic; signal done : std_logic; signal rxchar : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal rxfifo_get : std_logic; signal rxfifo_dout : std_logic_vector(7 downto 0); signal rxfifo_full : std_logic; signal rxfifo_dav : std_logic; signal overflow : std_logic; signal flags : std_logic_vector(7 downto 0); signal imask : std_logic_vector(7 downto 6); signal txfifo_get : std_logic; signal txfifo_put : std_logic; signal txfifo_dout : std_logic_vector(7 downto 0); signal txfifo_full : std_logic := '1'; signal txfifo_dav : std_logic; signal dotx_d : std_logic; signal txchar : std_logic_vector(7 downto 0); begin my_tx: entity work.tx generic map (divisor) port map ( clk => clock, reset => reset, dotx => dotx, txchar => txchar, txd => txd, done => done ); my_rx: entity work.rx generic map (divisor) port map ( clk => clock, reset => reset, rxd => rxd, rxchar => rxchar, rx_ack => rx_ack ); my_rxfifo: entity work.srl_fifo generic map ( Width => 8, Threshold => 12 ) port map ( clock => clock, reset => reset, GetElement => rxfifo_get, PutElement => rx_ack, FlushFifo => '0', DataIn => rxchar, DataOut => rxfifo_dout, SpaceInFifo => open, AlmostFull => rxfifo_full, DataInFifo => rxfifo_dav ); gentx: if tx_fifo generate my_txfifo: entity work.srl_fifo generic map ( Width => 8, Threshold => 12 ) port map ( clock => clock, reset => reset, GetElement => txfifo_get, PutElement => txfifo_put, FlushFifo => '0', DataIn => bus_wdata, DataOut => txfifo_dout, SpaceInFifo => open, AlmostFull => txfifo_full, DataInFifo => txfifo_dav ); end generate; process(bus_select, bus_write, bus_addr, txfifo_dav, bus_wdata, txfifo_dout, done) begin if not tx_fifo then txfifo_put <= '0'; txchar <= bus_wdata; if bus_select='1' and bus_write='1' and bus_addr="00" then dotx <= '1'; else dotx <= '0'; end if; else -- there is a fifo dotx <= txfifo_dav and done; txchar <= txfifo_dout; if bus_select='1' and bus_write='1' and bus_addr="00" then txfifo_put <= '1'; else txfifo_put <= '0'; end if; end if; end process; process(clock) begin if rising_edge(clock) then rxfifo_get <= '0'; dotx_d <= dotx; txfifo_get <= dotx_d; if rxfifo_full='1' and rx_ack='1' then overflow <= '1'; end if; if bus_select='1' and bus_write='1' then case bus_addr is when "00" => -- dout null; -- covered by combi statement when "01" => -- din rxfifo_get <= '1'; when "10" => -- clear flags overflow <= overflow and not bus_wdata(0); when "11" => -- interrupt control imask <= bus_wdata(7 downto 6); when others => null; end case; end if; if reset='1' then overflow <= '0'; imask <= (others => '0'); end if; end if; end process; flags(0) <= overflow; flags(1) <= '0'; flags(2) <= '0'; flags(3) <= '0'; flags(4) <= txfifo_full; flags(5) <= rxfifo_full; flags(6) <= done; flags(7) <= rxfifo_dav; with bus_addr select bus_rdata <= rxfifo_dout when "00", flags when "10", imask & "000000" when "11", X"00" when others; uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0'; end gideon;	gpl-3.0
davidhorrocks/1541UltimateII	target/simulation/packages/vhdl_bfm/wave_pkg.vhd	5	5471	------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Wave package ------------------------------------------------------------------------------- -- File : wave_pkg.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This package provides ways to write (and maybe in future read) -- .wav files. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tl_flat_memory_model_pkg.all; use work.tl_file_io_pkg.all; package wave_pkg is type t_wave_channel is record number_of_samples : integer; memory : h_mem_object; end record; type t_wave_channel_array is array(natural range <>) of t_wave_channel; procedure open_channel(chan : out t_wave_channel); procedure push_sample(chan : inout t_wave_channel; sample : integer); procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array); end package; package body wave_pkg is procedure open_channel(chan : out t_wave_channel) is variable ch : t_wave_channel; begin register_mem_model("path", "channel", ch.memory); ch.number_of_samples := 0; chan := ch; end procedure; procedure push_sample(chan : inout t_wave_channel; sample : integer) is variable s : integer; begin s := sample; if s > 32767 then s := 32767; end if; if s < -32768 then s := -32768; end if; write_memory_int(chan.memory, chan.number_of_samples, s); chan.number_of_samples := chan.number_of_samples + 1; end procedure; procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is variable bytes : integer := (x'length + 7) / 8; variable xa : std_logic_vector(7+bytes8 downto 0); begin xa := (others => '0'); xa(x'length-1 downto 0) := x; for i in 0 to bytes-1 loop write_byte(f, xa(i8+7 downto i8), r); end loop; end procedure; procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is variable x_slv : std_logic_vector(31 downto 0); begin x_slv := std_logic_vector(to_signed(x, 32)); write_vector_le(x_slv, f, r); end procedure; procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is variable x_slv : std_logic_vector(15 downto 0); begin x_slv := std_logic_vector(to_signed(x, 16)); write_vector_le(x_slv, f, r); end procedure; procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is file myfile : t_binary_file; variable myrec : t_binary_file_rec; variable stat : file_open_status; variable file_size : integer; variable data_size : integer; variable max_length : integer; begin -- open file file_open(stat, myfile, name, write_mode); assert (stat = open_ok) report "Could not open file " & name & " for writing." severity failure; init_record(myrec); max_length := 0; for i in channels'range loop if channels(i).number_of_samples > max_length then max_length := channels(i).number_of_samples; end if; end loop; data_size := (max_length channels'length * 2); file_size := 12 + 16 + 8 + data_size; -- header write_vector_le(X"46464952", myfile, myrec); -- "RIFF" write_int_le (file_size-8, myfile, myrec); write_vector_le(X"45564157", myfile, myrec); -- "WAVE" -- chunk header write_vector_le(X"20746D66", myfile, myrec); -- "fmt " write_int_le (16, myfile, myrec); write_short_le (1, myfile, myrec); -- compression code = uncompressed write_short_le (channels'length, myfile, myrec); write_int_le (rate, myfile, myrec); -- sample rate write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps write_short_le (channels'length * 2, myfile, myrec); -- alignment write_short_le (16, myfile, myrec); -- bits per sample write_vector_le(X"61746164", myfile, myrec); -- "data" write_int_le (data_size, myfile, myrec); -- now write out all data! for i in 0 to max_length-1 loop for j in channels'range loop write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec); end loop; end loop; purge(myfile, myrec); file_close(myfile); end procedure; end;	gpl-3.0
freecores/light8080	vhdl/light8080.vhdl	1	52124	--############################################################################## -- light8080 : Intel 8080 binary compatible core --############################################################################## -- v1.1 (20 sep 2008) Microcode bug in INR fixed. -- v1.0 (05 nov 2007) First release. Jose A. Ruiz. -- -- This file and all the light8080 project files are freeware (See COPYING.TXT) --############################################################################## -- (See timing diagrams at bottom of file. More comprehensive explainations can -- be found in the design notes) --############################################################################## library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --############################################################################## -- vma : enable a memory or io r/w access. -- io : access in progress is io (and not memory) -- rd : read memory or io -- wr : write memory or io -- data_out : data output -- addr_out : memory and io address -- data_in : data input -- halt : halt status (1 when in halt state) -- inte : interrupt status (1 when enabled) -- intr : interrupt request -- inta : interrupt acknowledge -- reset : synchronous reset -- clk : clock -- -- (see timing diagrams at bottom of file) --############################################################################## entity light8080 is Port ( addr_out : out std_logic_vector(15 downto 0); inta : out std_logic; inte : out std_logic; halt : out std_logic; intr : in std_logic; vma : out std_logic; io : out std_logic; rd : out std_logic; wr : out std_logic; fetch : out std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); clk : in std_logic; reset : in std_logic ); end light8080; --############################################################################## -- All memory and io accesses are synchronous (rising clock edge). Signal vma -- works as the master memory and io synchronous enable. More specifically: -- -- * All memory/io control signals (io,rd,wr) are valid only when vma is -- high. They never activate when vms is inactive. -- * Signals data_out and address are only valid when vma='1'. The high -- address byte is 0x00 for all io accesses. -- * Signal data_in should be valid by the end of the cycle after vma='1', -- data is clocked in by the rising clock edge. -- -- All signals are assumed to be synchronous to the master clock. Prevention of -- metastability, if necessary, is up to you. -- -- Signal reset needs to be active for just 1 clock cycle (it is sampled on a -- positive clock edge and is subject to setup and hold times). -- Once reset is deasserted, the first fetch at address 0x0000 will happen 4 -- cycles later. -- -- Signal intr is sampled on all positive clock edges. If asserted when inte is -- high, interrupts will be disabled, inta will be asserted high and a fetch -- cycle will occur. The fetched instruction will be executed normally, except -- PC will not be valid in any subsequent fetch cycles of the same instruction, -- and will not be incremented (In practice, the same as the original 8080). -- inta will remain high for the duration of the fetched instruction (in the -- original 8080 it was high only for the opcode fetch cycle). -- PC will not be autoincremented while inta is high, but it can be explicitly -- modified (e.g. RTS, CALL, etc.). Again, the same as the original. -- Interrupts will be disabled upon assertion of inta, and remain disabled -- until explicitly enabled by the program (as in the original). -- -- The above means that any instruction can be supplied in an inta cycle, -- either single byte or multibyte. See the design notes. --############################################################################## architecture microcoded of light8080 is -- addr_low: low byte of address signal addr_low : std_logic_vector(7 downto 0); -- IR: instruction register. some bits left unused. signal IR : std_logic_vector(7 downto 0); -- s_field: IR field, sss source reg code signal s_field : std_logic_vector(2 downto 0); -- d_field: IR field, ddd destination reg code signal d_field : std_logic_vector(2 downto 0); -- p_field: IR field, pp 16-bit reg pair code signal p_field : std_logic_vector(1 downto 0); -- rbh: 1 when p_field=11, used in reg bank addressing for 'special' regs signal rbh : std_logic; -- 1 when P=11 (special case) -- alu_op: uinst field, ALU operation code signal alu_op : std_logic_vector(3 downto 0); -- DI: data input to ALU block from data_in, unregistered signal DI : std_logic_vector(7 downto 0); -- uc_addr: microcode (ucode) address signal uc_addr : std_logic_vector(7 downto 0); -- next_uc_addr: computed next microcode address (uaddr++/jump/ret/fetch) signal next_uc_addr : std_logic_vector(8 downto 0); -- uc_jmp_addr: uinst field, absolute ucode jump address signal uc_jmp_addr : std_logic_vector(7 downto 0); -- uc_ret_address: ucode return address saved in previous jump signal uc_ret_addr : std_logic_vector(7 downto 0); -- addr_plus_1: uaddr + 1 signal addr_plus_1 : std_logic_vector(7 downto 0); -- do_reset: reset, delayed 1 cycle -- used to reset the microcode sequencer signal do_reset : std_logic; -- uc_flags1: uinst field, encoded flag of group 1 (see ucode file) signal uc_flags1 : std_logic_vector(2 downto 0); -- uc_flags2: uinst field, encoded flag of group 2 (see ucode file) signal uc_flags2 : std_logic_vector(2 downto 0); -- uc_addr_sel: selection of next uc_addr, composition of 4 flags signal uc_addr_sel : std_logic_vector(3 downto 0); -- NOTE: see microcode file for information on flags signal uc_jsr : std_logic; -- uinst field, decoded 'jsr' flag signal uc_tjsr : std_logic; -- uinst field, decoded 'tjsr' flag signal uc_decode : std_logic; -- uinst field, decoded 'decode' flag signal uc_end : std_logic; -- uinst field, decoded 'end' flag signal condition_reg :std_logic; -- registered tjst condition -- condition: tjsr condition (computed ccc condition from '80 instructions) signal condition : std_logic; -- condition_sel: IR field, ccc condition code signal condition_sel :std_logic_vector(2 downto 0); signal uc_do_jmp : std_logic; -- uinst jump (jsr/tjsr) flag, pipelined signal uc_do_ret : std_logic; -- ret flag, pipelined signal uc_halt_flag : std_logic; -- uinst field, decoded 'halt' flag signal uc_halt : std_logic; -- halt command signal halt_reg : std_logic; -- halt status reg, output as 'halt' signal signal uc_ei : std_logic; -- uinst field, decoded 'ei' flag signal uc_di : std_logic; -- uinst field, decoded 'ei' flag signal inte_reg : std_logic; -- inte status reg, output as 'inte' signal signal int_pending : std_logic; -- intr requested, inta not active yet signal inta_reg : std_logic; -- inta status reg, output as 'inta' signal clr_t1 : std_logic; -- uinst field, explicitly erase T1 signal do_clr_t1 : std_logic; -- clr_t1 pipelined signal clr_t2 : std_logic; -- uinst field, explicitly erase T2 signal do_clr_t2 : std_logic; -- clr_t2 pipelined signal ucode : std_logic_vector(31 downto 0); -- microcode word signal ucode_field2 : std_logic_vector(24 downto 0); -- pipelined microcode -- microcode ROM : see design notes and microcode source file type t_rom is array (0 to 511) of std_logic_vector(31 downto 0); signal rom : t_rom := ( "00000000000000000000000000000000", -- 000 "00000000000001001000000001000100", -- 001 "00000000000001000000000001000100", -- 002 "10111101101001001000000001001101", -- 003 "10110110101001000000000001001101", -- 004 "00100000000000000000000000000000", -- 005 "00000000000000000000000000000000", -- 006 "11100100000000000000000000000000", -- 007 "00000000101010000000000000000000", -- 008 "00000100000100000000000001010111", -- 009 "00001000000000000000110000011001", -- 00a "00000100000100000000000001010111", -- 00b "00000000101010000000000010010111", -- 00c "00001000000000000000110000011100", -- 00d "00001000000000000000110000011111", -- 00e "00000100000100000000000001010111", -- 00f "00001000000000000000110000011111", -- 010 "00001000000000000000110000011100", -- 011 "00001000000000000000110000011111", -- 012 "00000000000110001000000001010111", -- 013 "00001000000000000000110000011111", -- 014 "00000100000110000000000001010111", -- 015 "00001000000000000000110000101110", -- 016 "00001000000000000000110000100010", -- 017 "00000100000000111000000001010111", -- 018 "00001000000000000000110000101110", -- 019 "00000000101000111000000010010111", -- 01a "00001000000000000000110000100101", -- 01b "00001000000000000000110000101110", -- 01c "10111101101001100000000001001101", -- 01d "10110110101001101000000001001101", -- 01e "00000000100000101000000001010111", -- 01f "00001000000000000000110000100010", -- 020 "00000100000000100000000001010111", -- 021 "00001000000000000000110000101110", -- 022 "00000000101000101000000010010111", -- 023 "10111101101001100000000001001101", -- 024 "10111010101001101000000001001101", -- 025 "00000000101000100000000010010111", -- 026 "00001000000000000000110000100101", -- 027 "00001000000000000000110000101000", -- 028 "00000100000000111000000001010111", -- 029 "00000000101000111000000010010111", -- 02a "00001000000000000000110000101011", -- 02b "00000000101000010000000000000000", -- 02c "00000000000001010000000001010111", -- 02d "00000000101000011000000000000000", -- 02e "00000000000001011000000001010111", -- 02f "00000000101000100000000000000000", -- 030 "00000000000000010000000001010111", -- 031 "00000000101000101000000000000000", -- 032 "00000000000000011000000001010111", -- 033 "00000000101001010000000000000000", -- 034 "00000000000000100000000001010111", -- 035 "00000000101001011000000000000000", -- 036 "00000100000000101000000001010111", -- 037 "00001000000000000000110000011111", -- 038 "00000100011000111000001101001100", -- 039 "00001000000000000000110000011111", -- 03a "00000100011000111000001101001101", -- 03b "00001000000000000000110000011111", -- 03c "00000100011000111000001101001110", -- 03d "00001000000000000000110000011111", -- 03e "00000100011000111000001101001111", -- 03f "00001000000000000000110000011111", -- 040 "00000100011000111000001101000100", -- 041 "00001000000000000000110000011111", -- 042 "00000100011000111000001101000101", -- 043 "00001000000000000000110000011111", -- 044 "00000100011000111000001101000110", -- 045 "00001000000000000000110000011111", -- 046 "00000100011000111000001110001110", -- 047 "00000000101010000000000000000000", -- 048 "00000100011000111000001101001100", -- 049 "00000000101010000000000000000000", -- 04a "00000100011000111000001101001101", -- 04b "00000000101010000000000000000000", -- 04c "00000100011000111000001101001110", -- 04d "00000000101010000000000000000000", -- 04e "00000100011000111000001101001111", -- 04f "00000000101010000000000000000000", -- 050 "00000100011000111000001101000100", -- 051 "00000000101010000000000000000000", -- 052 "00000100011000111000001101000101", -- 053 "00000000101010000000000000000000", -- 054 "00000100011000111000001101000110", -- 055 "00000000101010000000000000000000", -- 056 "00000100011000111000001110001110", -- 057 "00001000000000000000110000011001", -- 058 "00000100011000111000001101001100", -- 059 "00001000000000000000110000011001", -- 05a "00000100011000111000001101001101", -- 05b "00001000000000000000110000011001", -- 05c "00000100011000111000001101001110", -- 05d "00001000000000000000110000011001", -- 05e "00000100011000111000001101001111", -- 05f "00001000000000000000110000011001", -- 060 "00000100011000111000001101000100", -- 061 "00001000000000000000110000011001", -- 062 "00000100011000111000001101000101", -- 063 "00001000000000000000110000011001", -- 064 "00000100011000111000001101000110", -- 065 "00001000000000000000110000011001", -- 066 "00000100011000111000001110001110", -- 067 "10111100101100000000001001001101", -- 068 "00000100000000000000000000000000", -- 069 "00001000000000000000110000011001", -- 06a "10111100000000000000001010001101", -- 06b "00001000000000000000110000011100", -- 06c "10111100011100000000001001001111", -- 06d "00000100000000000000000000000000", -- 06e "00001000000000000000110000011001", -- 06f "11000000000000000000000000000000", -- 070 "10111100011001010000001010001111", -- 071 "00001000000000000000110000011100", -- 072 "10111100101110001000000001001101", -- 073 "10100100101110000000000001001101", -- 074 "10111100011110001000000001001111", -- 075 "10100100011110000000000001001111", -- 076 "00000000011110001000000000000000", -- 077 "00000000101000101000000101001100", -- 078 "00000000011110000000000000000000", -- 079 "00000100101000100000000101001101", -- 07a "00000000101000111000000010101000", -- 07b "00000100101000111000001101101000", -- 07c "00000100101000111000000101000000", -- 07d "00000100101000111000000101000001", -- 07e "00000100101000111000000101000010", -- 07f "00000100101000111000000101000011", -- 080 "00000100101000111000000001000111", -- 081 "00000100000000000000000100101100", -- 082 "00000100000000000000000100101101", -- 083 "00001000000000000000110000101110", -- 084 "00000000101001100000000000000000", -- 085 "00000000000001001000000001010111", -- 086 "00000000101001101000000000000000", -- 087 "00000100000001000000000001010111", -- 088 "00000100000000000000000000000000", -- 089 "00001000000000000000110000101110", -- 08a "00010000000000000000100000000101", -- 08b "00001000000000000000110000101110", -- 08c "11000000101001000000000010010111", -- 08d "00001000000000000000110000110100", -- 08e "11000000101001001000000010010111", -- 08f "00001000000000000000110000110100", -- 090 "00000000101001100000000000000000", -- 091 "00000000000001001000000001010111", -- 092 "00000000101001101000000000000000", -- 093 "00000100000001000000000001010111", -- 094 "00001000000000000000110000101110", -- 095 "00010000000000000000100000001101", -- 096 "00001000000000000000110000111001", -- 097 "00000000000001001000000001010111", -- 098 "00001000000000000000110000111001", -- 099 "00000100000001000000000001010111", -- 09a "00010000000000000000100000010111", -- 09b "11000000101001000000000010010111", -- 09c "00001000000000000000110000110100", -- 09d "11000000101001001000000010010111", -- 09e "00001000000000000000110000110100", -- 09f "11000000000001001000000001011111", -- 0a0 "00000100000001000000000001000100", -- 0a1 "00000000101000101000000000000000", -- 0a2 "00000000000001001000000001010111", -- 0a3 "00000000101000100000000000000000", -- 0a4 "00000100000001000000000001010111", -- 0a5 "11000000101110000000000010010111", -- 0a6 "00001000000000000000110000110100", -- 0a7 "11000000101110001000000010010111", -- 0a8 "00001000000000000000110000110100", -- 0a9 "00000100000000000000000000000000", -- 0aa "11000000101000111000000010010111", -- 0ab "00001000000000000000110000110100", -- 0ac "11000000000000000000000010110000", -- 0ad "00001000000000000000110000110100", -- 0ae "00000100000000000000000000000000", -- 0af "00001000000000000000110000111001", -- 0b0 "00000000000110001000000001010111", -- 0b1 "00001000000000000000110000111001", -- 0b2 "00000100000110000000000001010111", -- 0b3 "00001000000000000000110000111001", -- 0b4 "00000000000000110000001101010111", -- 0b5 "00001000000000000000110000111001", -- 0b6 "00000100000000111000000001010111", -- 0b7 "00001000000000000000110000111001", -- 0b8 "00000000000001100000000001010111", -- 0b9 "00001000000000000000110000111001", -- 0ba "00000000000001101000000001010111", -- 0bb "11000000101000100000000010010111", -- 0bc "00001000000000000000110000110100", -- 0bd "11000000101000101000000010010111", -- 0be "00001000000000000000110000110100", -- 0bf "00000000101001100000000000000000", -- 0c0 "00000000000000101000000001010111", -- 0c1 "00000000101001101000000000000000", -- 0c2 "00000100000000100000000001010111", -- 0c3 "00000000101000101000000000000000", -- 0c4 "00000000000001111000000001010111", -- 0c5 "00000000101000100000000000000000", -- 0c6 "00000100000001110000000001010111", -- 0c7 "01100100000000000000000000000000", -- 0c8 "01000100000000000000000000000000", -- 0c9 "00000000000001101000000001010111", -- 0ca "00001000000000000000110000011111", -- 0cb "00000000000001100000000001010111", -- 0cc "00000000000000000000000000000000", -- 0cd "00000001101001100000000000000000", -- 0ce "10010110101001101000000000000000", -- 0cf "00000100100000111000000001010111", -- 0d0 "00000000000001101000000001010111", -- 0d1 "00001000000000000000110000011111", -- 0d2 "00000000000001100000000001010111", -- 0d3 "00000000101000111000000010010111", -- 0d4 "00000001101001100000000000000000", -- 0d5 "10011010101001101000000000000000", -- 0d6 "00000100000000000000000000000000", -- 0d7 "11100100000000000000000000000000", -- 0d8 "00000001101000101000000000000000", -- 0d9 "00010110101000100000000000000000", -- 0da "00001100100001010000000001010111", -- 0db "00000001101000101000000000000000", -- 0dc "00011010101000100000000000000000", -- 0dd "00000100000000000000000000000000", -- 0de "10111101101001001000000001001101", -- 0df "10110110101001000000000001001101", -- 0e0 "00001100100000000000000010010111", -- 0e1 "00000001101001100000000000000000", -- 0e2 "00010110101001101000000000000000", -- 0e3 "00001100100000000000000000000000", -- 0e4 "00000001101001100000000000000000", -- 0e5 "00011010101001101000000000000000", -- 0e6 "00000100000000000000000000000000", -- 0e7 "00000001101110001000000000000000", -- 0e8 "00010110101110000000000000000000", -- 0e9 "00001100100000000000000000000000", -- 0ea "00000001101110001000000000000000", -- 0eb "00011010101110000000000000000000", -- 0ec "00000100000000000000000000000000", -- 0ed "10111101101001001000000001001101", -- 0ee "10110110101001000000000001001101", -- 0ef "00000000100001100000000001010111", -- 0f0 "10111101101001001000000001001101", -- 0f1 "10110110101001000000000001001101", -- 0f2 "00001100100001101000000001010111", -- 0f3 "10111100011001111000000001001111", -- 0f4 "10100000011001110000000001001111", -- 0f5 "00000001101001111000000000000000", -- 0f6 "00011010101001110000000000000000", -- 0f7 "00001100000000000000000000000000", -- 0f8 "10111101101001111000000001001101", -- 0f9 "10110110101001110000000001001101", -- 0fa "00001100100000000000000000000000", -- 0fb "00000100000000000000000000000000", -- 0fc "00000100000000000000000000000000", -- 0fd "00000100000000000000000000000000", -- 0fe "00000100000000000000000000000000", -- 0ff "00001000000000000000100000001001", -- 100 "00001000000000000000000000010010", -- 101 "00001000000000000000000000101010", -- 102 "00001000000000000000010000110011", -- 103 "00001000000000000000010000101000", -- 104 "00001000000000000000010000101101", -- 105 "00001000000000000000000000001110", -- 106 "00001000000000000000010000111101", -- 107 "00001000000000000000000000000000", -- 108 "00001000000000000000010000110111", -- 109 "00001000000000000000000000101000", -- 10a "00001000000000000000010000110101", -- 10b "00001000000000000000010000101000", -- 10c "00001000000000000000010000101101", -- 10d "00001000000000000000000000001110", -- 10e "00001000000000000000010000111110", -- 10f "00001000000000000000000000000000", -- 110 "00001000000000000000000000010010", -- 111 "00001000000000000000000000101010", -- 112 "00001000000000000000010000110011", -- 113 "00001000000000000000010000101000", -- 114 "00001000000000000000010000101101", -- 115 "00001000000000000000000000001110", -- 116 "00001000000000000000010000111111", -- 117 "00001000000000000000000000000000", -- 118 "00001000000000000000010000110111", -- 119 "00001000000000000000000000101000", -- 11a "00001000000000000000010000110101", -- 11b "00001000000000000000010000101000", -- 11c "00001000000000000000010000101101", -- 11d "00001000000000000000000000001110", -- 11e "00001000000000000000100000000000", -- 11f "00001000000000000000000000000000", -- 120 "00001000000000000000000000010010", -- 121 "00001000000000000000000000100010", -- 122 "00001000000000000000010000110011", -- 123 "00001000000000000000010000101000", -- 124 "00001000000000000000010000101101", -- 125 "00001000000000000000000000001110", -- 126 "00001000000000000000010000111011", -- 127 "00001000000000000000000000000000", -- 128 "00001000000000000000010000110111", -- 129 "00001000000000000000000000011100", -- 12a "00001000000000000000010000110101", -- 12b "00001000000000000000010000101000", -- 12c "00001000000000000000010000101101", -- 12d "00001000000000000000000000001110", -- 12e "00001000000000000000100000000001", -- 12f "00001000000000000000000000000000", -- 130 "00001000000000000000000000010010", -- 131 "00001000000000000000000000011001", -- 132 "00001000000000000000010000110011", -- 133 "00001000000000000000010000101010", -- 134 "00001000000000000000010000101111", -- 135 "00001000000000000000000000010000", -- 136 "00001000000000000000100000000011", -- 137 "00001000000000000000000000000000", -- 138 "00001000000000000000010000110111", -- 139 "00001000000000000000000000010110", -- 13a "00001000000000000000010000110101", -- 13b "00001000000000000000010000101000", -- 13c "00001000000000000000010000101101", -- 13d "00001000000000000000000000001110", -- 13e "00001000000000000000100000000010", -- 13f "00001000000000000000000000001000", -- 140 "00001000000000000000000000001000", -- 141 "00001000000000000000000000001000", -- 142 "00001000000000000000000000001000", -- 143 "00001000000000000000000000001000", -- 144 "00001000000000000000000000001000", -- 145 "00001000000000000000000000001010", -- 146 "00001000000000000000000000001000", -- 147 "00001000000000000000000000001000", -- 148 "00001000000000000000000000001000", -- 149 "00001000000000000000000000001000", -- 14a "00001000000000000000000000001000", -- 14b "00001000000000000000000000001000", -- 14c "00001000000000000000000000001000", -- 14d "00001000000000000000000000001010", -- 14e "00001000000000000000000000001000", -- 14f "00001000000000000000000000001000", -- 150 "00001000000000000000000000001000", -- 151 "00001000000000000000000000001000", -- 152 "00001000000000000000000000001000", -- 153 "00001000000000000000000000001000", -- 154 "00001000000000000000000000001000", -- 155 "00001000000000000000000000001010", -- 156 "00001000000000000000000000001000", -- 157 "00001000000000000000000000001000", -- 158 "00001000000000000000000000001000", -- 159 "00001000000000000000000000001000", -- 15a "00001000000000000000000000001000", -- 15b "00001000000000000000000000001000", -- 15c "00001000000000000000000000001000", -- 15d "00001000000000000000000000001010", -- 15e "00001000000000000000000000001000", -- 15f "00001000000000000000000000001000", -- 160 "00001000000000000000000000001000", -- 161 "00001000000000000000000000001000", -- 162 "00001000000000000000000000001000", -- 163 "00001000000000000000000000001000", -- 164 "00001000000000000000000000001000", -- 165 "00001000000000000000000000001010", -- 166 "00001000000000000000000000001000", -- 167 "00001000000000000000000000001000", -- 168 "00001000000000000000000000001000", -- 169 "00001000000000000000000000001000", -- 16a "00001000000000000000000000001000", -- 16b "00001000000000000000000000001000", -- 16c "00001000000000000000000000001000", -- 16d "00001000000000000000000000001010", -- 16e "00001000000000000000000000001000", -- 16f "00001000000000000000000000001100", -- 170 "00001000000000000000000000001100", -- 171 "00001000000000000000000000001100", -- 172 "00001000000000000000000000001100", -- 173 "00001000000000000000000000001100", -- 174 "00001000000000000000000000001100", -- 175 "00001000000000000000110000011000", -- 176 "00001000000000000000000000001100", -- 177 "00001000000000000000000000001000", -- 178 "00001000000000000000000000001000", -- 179 "00001000000000000000000000001000", -- 17a "00001000000000000000000000001000", -- 17b "00001000000000000000000000001000", -- 17c "00001000000000000000000000001000", -- 17d "00001000000000000000000000001010", -- 17e "00001000000000000000000000001000", -- 17f "00001000000000000000010000001000", -- 180 "00001000000000000000010000001000", -- 181 "00001000000000000000010000001000", -- 182 "00001000000000000000010000001000", -- 183 "00001000000000000000010000001000", -- 184 "00001000000000000000010000001000", -- 185 "00001000000000000000010000011000", -- 186 "00001000000000000000010000001000", -- 187 "00001000000000000000010000001010", -- 188 "00001000000000000000010000001010", -- 189 "00001000000000000000010000001010", -- 18a "00001000000000000000010000001010", -- 18b "00001000000000000000010000001010", -- 18c "00001000000000000000010000001010", -- 18d "00001000000000000000010000011010", -- 18e "00001000000000000000010000001010", -- 18f "00001000000000000000010000001100", -- 190 "00001000000000000000010000001100", -- 191 "00001000000000000000010000001100", -- 192 "00001000000000000000010000001100", -- 193 "00001000000000000000010000001100", -- 194 "00001000000000000000010000001100", -- 195 "00001000000000000000010000011100", -- 196 "00001000000000000000010000001100", -- 197 "00001000000000000000010000001110", -- 198 "00001000000000000000010000001110", -- 199 "00001000000000000000010000001110", -- 19a "00001000000000000000010000001110", -- 19b "00001000000000000000010000001110", -- 19c "00001000000000000000010000001110", -- 19d "00001000000000000000010000011110", -- 19e "00001000000000000000010000001110", -- 19f "00001000000000000000010000010000", -- 1a0 "00001000000000000000010000010000", -- 1a1 "00001000000000000000010000010000", -- 1a2 "00001000000000000000010000010000", -- 1a3 "00001000000000000000010000010000", -- 1a4 "00001000000000000000010000010000", -- 1a5 "00001000000000000000010000100000", -- 1a6 "00001000000000000000010000010000", -- 1a7 "00001000000000000000010000010010", -- 1a8 "00001000000000000000010000010010", -- 1a9 "00001000000000000000010000010010", -- 1aa "00001000000000000000010000010010", -- 1ab "00001000000000000000010000010010", -- 1ac "00001000000000000000010000010010", -- 1ad "00001000000000000000010000100010", -- 1ae "00001000000000000000010000010010", -- 1af "00001000000000000000010000010100", -- 1b0 "00001000000000000000010000010100", -- 1b1 "00001000000000000000010000010100", -- 1b2 "00001000000000000000010000010100", -- 1b3 "00001000000000000000010000010100", -- 1b4 "00001000000000000000010000010100", -- 1b5 "00001000000000000000010000100100", -- 1b6 "00001000000000000000010000010100", -- 1b7 "00001000000000000000010000010110", -- 1b8 "00001000000000000000010000010110", -- 1b9 "00001000000000000000010000010110", -- 1ba "00001000000000000000010000010110", -- 1bb "00001000000000000000010000010110", -- 1bc "00001000000000000000010000010110", -- 1bd "00001000000000000000010000100110", -- 1be "00001000000000000000010000010110", -- 1bf "00001000000000000000100000011011", -- 1c0 "00001000000000000000100000110000", -- 1c1 "00001000000000000000100000001010", -- 1c2 "00001000000000000000100000000100", -- 1c3 "00001000000000000000100000010101", -- 1c4 "00001000000000000000100000100110", -- 1c5 "00001000000000000000000000111000", -- 1c6 "00001000000000000000100000011100", -- 1c7 "00001000000000000000100000011011", -- 1c8 "00001000000000000000100000010111", -- 1c9 "00001000000000000000100000001010", -- 1ca "00001000000000000000000000000000", -- 1cb "00001000000000000000100000010101", -- 1cc "00001000000000000000100000001100", -- 1cd "00001000000000000000000000111010", -- 1ce "00001000000000000000100000011100", -- 1cf "00001000000000000000100000011011", -- 1d0 "00001000000000000000100000110000", -- 1d1 "00001000000000000000100000001010", -- 1d2 "00001000000000000000110000010001", -- 1d3 "00001000000000000000100000010101", -- 1d4 "00001000000000000000100000100110", -- 1d5 "00001000000000000000000000111100", -- 1d6 "00001000000000000000100000011100", -- 1d7 "00001000000000000000100000011011", -- 1d8 "00001000000000000000000000000000", -- 1d9 "00001000000000000000100000001010", -- 1da "00001000000000000000110000001010", -- 1db "00001000000000000000100000010101", -- 1dc "00001000000000000000000000000000", -- 1dd "00001000000000000000000000111110", -- 1de "00001000000000000000100000011100", -- 1df "00001000000000000000100000011011", -- 1e0 "00001000000000000000100000110000", -- 1e1 "00001000000000000000100000001010", -- 1e2 "00001000000000000000100000111000", -- 1e3 "00001000000000000000100000010101", -- 1e4 "00001000000000000000100000100110", -- 1e5 "00001000000000000000010000000000", -- 1e6 "00001000000000000000100000011100", -- 1e7 "00001000000000000000100000011011", -- 1e8 "00001000000000000000100000100010", -- 1e9 "00001000000000000000100000001010", -- 1ea "00001000000000000000000000101100", -- 1eb "00001000000000000000100000010101", -- 1ec "00001000000000000000000000000000", -- 1ed "00001000000000000000010000000010", -- 1ee "00001000000000000000100000011100", -- 1ef "00001000000000000000100000011011", -- 1f0 "00001000000000000000100000110100", -- 1f1 "00001000000000000000100000001010", -- 1f2 "00001000000000000000110000001001", -- 1f3 "00001000000000000000100000010101", -- 1f4 "00001000000000000000100000101011", -- 1f5 "00001000000000000000010000000100", -- 1f6 "00001000000000000000100000011100", -- 1f7 "00001000000000000000100000011011", -- 1f8 "00001000000000000000110000000100", -- 1f9 "00001000000000000000100000001010", -- 1fa "00001000000000000000110000001000", -- 1fb "00001000000000000000100000010101", -- 1fc "00001000000000000000000000000000", -- 1fd "00001000000000000000010000000110", -- 1fe "00001000000000000000100000011100" -- 1ff ); -- end of microcode ROM signal load_al : std_logic; -- uinst field, load AL reg from rbank signal load_addr : std_logic; -- uinst field, enable external addr reg load signal load_t1 : std_logic; -- uinst field, load reg T1 signal load_t2 : std_logic; -- uinst field, load reg T2 signal mux_in : std_logic; -- uinst field, T1/T2 input data selection signal load_do : std_logic; -- uinst field, pipelined, load DO reg -- rb_addr_sel: uinst field, rbank address selection: (sss,ddd,pp,ra_field) signal rb_addr_sel : std_logic_vector(1 downto 0); -- ra_field: uinst field, explicit reg bank address signal ra_field : std_logic_vector(3 downto 0); signal rbank_data : std_logic_vector(7 downto 0); -- rbank output signal alu_output : std_logic_vector(7 downto 0); -- ALU output -- data_output: datapath output: ALU output vs. F reg signal data_output : std_logic_vector(7 downto 0); signal T1 : std_logic_vector(7 downto 0); -- T1 reg (ALU operand) signal T2 : std_logic_vector(7 downto 0); -- T2 reg (ALU operand) -- alu_input: data loaded into T1, T2: rbank data vs. DI signal alu_input : std_logic_vector(7 downto 0); signal we_rb : std_logic; -- uinst field, commands a write to the rbank signal inhibit_pc_increment : std_logic; -- avoid PC changes (during INTA) signal rbank_rd_addr: std_logic_vector(3 downto 0); -- rbank rd addr signal rbank_wr_addr: std_logic_vector(3 downto 0); -- rbank wr addr signal DO : std_logic_vector(7 downto 0); -- data output reg -- Register bank as an array of 16 bytes (asynch. LUT ram) type t_reg_bank is array(0 to 15) of std_logic_vector(7 downto 0); -- Register bank : BC, DE, HL, AF, [PC, XY, ZW, SP] signal rbank : t_reg_bank; signal flag_reg : std_logic_vector(7 downto 0); -- F register -- flag_pattern: uinst field, F update pattern: which flags are updated signal flag_pattern : std_logic_vector(1 downto 0); signal flag_s : std_logic; -- new computed S flag signal flag_z : std_logic; -- new computed Z flag signal flag_p : std_logic; -- new computed P flag signal flag_cy : std_logic; -- new computed C flag signal flag_cy_1 : std_logic; -- C flag computed from arith/logic operation signal flag_cy_2 : std_logic; -- C flag computed from CPC circuit signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.) signal do_cy_op_d : std_logic; -- do_cy_op, pipelined signal do_cpc : std_logic; -- ALU operation is CPC signal do_cpc_d : std_logic; -- do_cpc, pipelined signal do_daa : std_logic; -- ALU operation is DAA signal flag_ac : std_logic; -- new computed half carry flag -- flag_aux_cy: new computed half carry flag (used in 16-bit ops) signal flag_aux_cy : std_logic; signal load_psw : std_logic; -- load F register -- aux carry computation and control signals signal use_aux : std_logic; -- decoded from flags in 1st phase signal use_aux_cy : std_logic; -- 2nd phase signal signal reg_aux_cy : std_logic; signal aux_cy_in : std_logic; signal set_aux_cy : std_logic; signal set_aux : std_logic; -- ALU control signals -- together they select ALU operation signal alu_fn : std_logic_vector(1 downto 0); signal use_logic : std_logic; -- logic/arith mux control signal mux_fn : std_logic_vector(1 downto 0); signal use_psw : std_logic; -- ALU/F mux control -- ALU arithmetic operands and result signal arith_op1 : std_logic_vector(8 downto 0); signal arith_op2 : std_logic_vector(8 downto 0); signal arith_op2_sgn: std_logic_vector(8 downto 0); signal arith_res : std_logic_vector(8 downto 0); signal arith_res8 : std_logic_vector(7 downto 0); -- ALU DAA intermediate signals (DAA has fully dedicated logic) signal daa_res : std_logic_vector(8 downto 0); signal daa_res8 : std_logic_vector(7 downto 0); signal daa_res9 : std_logic_vector(8 downto 0); signal daa_test1 : std_logic; signal daa_test1a : std_logic; signal daa_test2 : std_logic; signal daa_test2a : std_logic; signal arith_daa_res :std_logic_vector(7 downto 0); signal cy_daa : std_logic; -- ALU CY flag intermediate signals signal cy_in_sgn : std_logic; signal cy_in : std_logic; signal cy_in_gated : std_logic; signal cy_adder : std_logic; signal cy_arith : std_logic; signal cy_shifter : std_logic; -- ALU intermediate results signal logic_res : std_logic_vector(7 downto 0); signal shift_res : std_logic_vector(7 downto 0); signal alu_mux1 : std_logic_vector(7 downto 0); begin DI <= data_in; process(clk) -- IR register, load when uc_decode flag activates begin if clk'event and clk='1' then if uc_decode = '1' then IR <= DI; end if; end if; end process; s_field <= IR(2 downto 0); -- IR field extraction : sss reg code d_field <= IR(5 downto 3); -- ddd reg code p_field <= IR(5 downto 4); -- pp 16-bit reg pair code --############################################################################## -- Microcode sequencer process(clk) -- do_reset is reset delayed 1 cycle begin if clk'event and clk='1' then do_reset <= reset; end if; end process; uc_flags1 <= ucode(31 downto 29); uc_flags2 <= ucode(28 downto 26); -- microcode address control flags are gated by do_reset (reset has priority) uc_do_ret <= '1' when uc_flags2 = "011" and do_reset = '0' else '0'; uc_jsr <= '1' when uc_flags2 = "010" and do_reset = '0' else '0'; uc_tjsr <= '1' when uc_flags2 = "100" and do_reset = '0' else '0'; uc_decode <= '1' when uc_flags1 = "001" and do_reset = '0' else '0'; uc_end <= '1' when (uc_flags2 = "001" or (uc_tjsr='1' and condition_reg='0')) and do_reset = '0' else '0'; -- other microinstruction flags are decoded uc_halt_flag <= '1' when uc_flags1 = "111" else '0'; uc_halt <= '1' when uc_halt_flag='1' and inta_reg='0' else '0'; uc_ei <= '1' when uc_flags1 = "011" else '0'; uc_di <= '1' when uc_flags1 = "010" or inta_reg='1' else '0'; -- clr_t1/2 clears T1/T2 when explicitly commanded; T2 and T1 clear implicitly -- at the end of each instruction (by uc_decode) clr_t2 <= '1' when uc_flags2 = "001" else '0'; clr_t1 <= '1' when uc_flags1 = "110" else '0'; use_aux <= '1' when uc_flags1 = "101" else '0'; set_aux <= '1' when uc_flags2 = "111" else '0'; load_al <= ucode(24); load_addr <= ucode(25); do_cy_op_d <= '1' when ucode(5 downto 2)="1011" else '0'; -- decode CY ALU op do_cpc_d <= ucode(0); -- decode CPC ALU op -- uinst jump command, either unconditional or on a given condition uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg); vma <= load_addr; -- addr is valid, either for memmory or io -- assume the only uinst that does memory access in the range 0..f is 'fetch' fetch <= '1' when uc_addr(7 downto 4)=X"0" and load_addr='1' else '0'; -- external bus interface control signals io <= '1' when uc_flags1="100" else '0'; -- IO access (vs. memory) rd <= '1' when uc_flags2="101" else '0'; -- RD access wr <= '1' when uc_flags2="110" else '0'; -- WR access uc_jmp_addr <= ucode(11 downto 10) & ucode(5 downto 0); uc_addr_sel <= uc_do_ret & uc_do_jmp & uc_decode & uc_end; addr_plus_1 <= uc_addr + 1; -- TODO simplify this!! -- NOTE: when end='1' we jump either to the FETCH ucode ot to the HALT ucode -- depending on the value of the halt signal. -- We use the unregistered uc_halt instead of halt_reg because otherwise #end -- should be on the cycle following #halt, wasting a cycle. -- This means that the flag #halt has to be used with #end or will be ignored. with uc_addr_sel select next_uc_addr <= '0'&uc_ret_addr when "1000", -- ret '0'&uc_jmp_addr when "0100", -- jsr/tjsr '0'&addr_plus_1 when "0000", -- uaddr++ "000000"&uc_halt&"11" when "0001", -- end: go to fetch/halt uaddr '1'&DI when others; -- decode fetched address -- Note how we used DI (containing instruction opcode) as a microcode address -- read microcode rom process (clk) begin if clk'event and clk='1' then ucode <= rom(conv_integer(next_uc_addr)); end if; end process; -- microcode address register process (clk) begin if clk'event and clk='1' then if reset = '1' then uc_addr <= X"00"; else uc_addr <= next_uc_addr(7 downto 0); end if; end if; end process; -- ucode address 1-level 'return stack' process (clk) begin if clk'event and clk='1' then if reset = '1' then uc_ret_addr <= X"00"; elsif uc_do_jmp='1' then uc_ret_addr <= addr_plus_1; end if; end if; end process; alu_op <= ucode(3 downto 0); -- pipeline uinst field2 for 1-cycle delayed execution. -- note the same rbank addr field is used in cycles 1 and 2; this enforces -- some constraints on uinst programming but simplifies the system. process(clk) begin if clk'event and clk='1' then ucode_field2 <= do_cy_op_d & do_cpc_d & clr_t2 & clr_t1 & set_aux & use_aux & rbank_rd_addr & ucode(14 downto 4) & alu_op; end if; end process; --#### HALT logic process(clk) begin if clk'event and clk='1' then if reset = '1' or int_pending = '1' then --inta_reg halt_reg <= '0'; else if uc_halt = '1' then halt_reg <= '1'; end if; end if; end if; end process; halt <= halt_reg; --#### INTE logic -- inte_reg = '1' means interrupts ENABLED process(clk) begin if clk'event and clk='1' then if reset = '1' then inte_reg <= '0'; else if uc_di='1' or uc_ei='1' then inte_reg <= uc_ei; end if; end if; end if; end process; inte <= inte_reg; -- interrupts are ignored when inte='0' process(clk) begin if clk'event and clk='1' then if reset = '1' then int_pending <= '0'; else if intr = '1' and inte_reg = '1' and int_pending = '0' then int_pending <= '1'; else if inte_reg = '1' and uc_end='1' then int_pending <= '0'; end if; end if; end if; end if; end process; --#### INTA logic -- INTA goes high from END to END, that is for the entire time the instruction -- takes to fetch and execute; in the original 8080 it was asserted only for -- the M1 cycle. -- All instructions can be used in an inta cycle, including XTHL which was -- forbidden in the original 8080. -- It's up to you figuring out which cycle is which in multibyte instructions. process(clk) begin if clk'event and clk='1' then if reset = '1' then inta_reg <= '0'; else if int_pending = '1' and uc_end='1' then -- enter INTA state inta_reg <= '1'; else -- exit INTA state -- NOTE: don't reset inta when exiting halt state (uc_halt_flag='1'). -- If we omit this condition, when intr happens on halt state, inta -- will only last for 1 cycle, because in halt state uc_end is -- always asserted. if uc_end = '1' and uc_halt_flag='0' then inta_reg <= '0'; end if; end if; end if; end if; end process; inta <= inta_reg; --############################################################################## -- Datapath -- extract pipelined microcode fields ra_field <= ucode(18 downto 15); load_t1 <= ucode(23); load_t2 <= ucode(22); mux_in <= ucode(21); rb_addr_sel <= ucode(20 downto 19); load_do <= ucode_field2(7); set_aux_cy <= ucode_field2(20); do_clr_t1 <= ucode_field2(21); do_clr_t2 <= ucode_field2(22); -- T1 register process (clk) begin if clk'event and clk='1' then if reset = '1' or uc_decode = '1' or do_clr_t1='1' then T1 <= X"00"; else if load_t1 = '1' then T1 <= alu_input; end if; end if; end if; end process; -- T2 register process (clk) begin if clk'event and clk='1' then if reset = '1' or uc_decode = '1' or do_clr_t2='1' then T2 <= X"00"; else if load_t2 = '1' then T2 <= alu_input; end if; end if; end if; end process; -- T1/T2 input data mux alu_input <= rbank_data when mux_in = '1' else DI; -- register bank address mux logic rbh <= '1' when p_field = "11" else '0'; with rb_addr_sel select rbank_rd_addr <= ra_field when "00", "0"&s_field when "01", "0"&d_field when "10", rbh&p_field&ra_field(0) when others; -- RBank writes are inhibited in INTA state, but only for PC increments. inhibit_pc_increment <= '1' when inta_reg='1' and use_aux_cy='1' and rbank_wr_addr(3 downto 1) = "100" else '0'; we_rb <= ucode_field2(6) and not inhibit_pc_increment; -- Register bank logic -- NOTE: read is asynchronous, while write is synchronous; but note also -- that write phase for a given uinst happens the cycle after the read phase. -- This way we give the ALU time to do its job. rbank_wr_addr <= ucode_field2(18 downto 15); process(clk) begin if clk'event and clk='1' then if we_rb = '1' then rbank(conv_integer(rbank_wr_addr)) <= alu_output; end if; end if; end process; rbank_data <= rbank(conv_integer(rbank_rd_addr)); -- should we read F register or ALU output? use_psw <= '1' when ucode_field2(5 downto 4)="11" else '0'; data_output <= flag_reg when use_psw = '1' else alu_output; process (clk) begin if clk'event and clk='1' then if load_do = '1' then DO <= data_output; end if; end if; end process; --############################################################################## -- ALU alu_fn <= ucode_field2(1 downto 0); use_logic <= ucode_field2(2); mux_fn <= ucode_field2(4 downto 3); --#### make sure this is "00" in the microcode when no F updates should happen! flag_pattern <= ucode_field2(9 downto 8); use_aux_cy <= ucode_field2(19); do_cpc <= ucode_field2(23); do_cy_op <= ucode_field2(24); do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0'; aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1'; -- carry input selection: normal or aux (for 16 bit increments)? cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in; -- carry is not used (0) in add/sub operations cy_in_gated <= cy_in and alu_fn(0); --##### Adder/substractor -- zero extend adder operands to 9 bits to ease CY output synthesis -- use zero extension because we're only interested in cy from 7 to 8 arith_op1 <= '0' & T2; arith_op2 <= '0' & T1; -- The adder/substractor is done in 2 stages to help XSL synth it properly -- Other codings result in 1 adder + a substractor + 1 mux -- do 2nd op 2's complement if substracting... arith_op2_sgn <= arith_op2 when alu_fn(1) = '0' else not arith_op2; -- ...and complement cy input too cy_in_sgn <= cy_in_gated when alu_fn(1) = '0' else not cy_in_gated; -- once 2nd operand has been negated (or not) add operands normally arith_res <= arith_op1 + arith_op2_sgn + cy_in_sgn; -- take only 8 bits; 9th bit of adder is cy output arith_res8 <= arith_res(7 downto 0); cy_adder <= arith_res(8); --##### DAA dedicated logic -- Note a DAA takes 2 cycles to complete! --daa_test1a='1' when daa_res9(7 downto 4) > 0x06 daa_test1a <= arith_op2(3) and (arith_op2(2) or arith_op2(1) or arith_op2(0)); daa_test1 <= '1' when flag_reg(4)='1' or daa_test1a='1' else '0'; process(clk) begin if clk'event and clk='1' then if reset='1' then daa_res9 <= "000000000"; else if daa_test1='1' then daa_res9 <= arith_op2 + "000000110"; else daa_res9 <= arith_op2; end if; end if; end if; end process; --daa_test2a='1' when daa_res9(7 downto 4) > 0x06 FIXME unused? daa_test2a <= daa_res9(7) and (daa_res9(6) or daa_res9(5) or daa_res9(4)); daa_test2 <= '1' when flag_reg(0)='1' or daa_test1a='1' else '0'; daa_res <= '0'&daa_res9(7 downto 0) + "01100000" when daa_test2='1' else daa_res9; cy_daa <= daa_res(8); -- DAA vs. adder mux arith_daa_res <= daa_res(7 downto 0) when do_daa='1' else arith_res8; -- DAA vs. adder CY mux cy_arith <= cy_daa when do_daa='1' else cy_adder; --##### Logic operations block logic_res <= T1 and T2 when alu_fn = "00" else T1 xor T2 when alu_fn = "01" else T1 or T2 when alu_fn = "10" else not T1; --##### Shifter shifter: for i in 1 to 6 generate begin shift_res(i) <= T1(i-1) when alu_fn(0) = '0' else T1(i+1); end generate; shift_res(0) <= T1(7) when alu_fn = "00" else -- rot left cy_in when alu_fn = "10" else -- rot left through carry T1(1); -- rot right shift_res(7) <= T1(0) when alu_fn = "01" else -- rot right cy_in when alu_fn = "11" else -- rot right through carry T1(6); -- rot left cy_shifter <= T1(7) when alu_fn(0) = '0' else -- left T1(0); -- right alu_mux1 <= logic_res when use_logic = '1' else shift_res; with mux_fn select alu_output <= alu_mux1 when "00", arith_daa_res when "01", not alu_mux1 when "10", "00"&d_field&"000" when others; -- RST --###### flag computation flag_s <= alu_output(7); flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0)); flag_z <= '1' when alu_output=X"00" else '0'; flag_ac <= (arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4)); flag_cy_1 <= cy_arith when use_logic = '1' else cy_shifter; flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2; flag_aux_cy <= cy_adder; -- auxiliary carry reg process(clk) begin if clk'event and clk='1' then if reset='1' or uc_decode = '1' then reg_aux_cy <= '1'; -- inits to 0 every instruction else reg_aux_cy <= flag_aux_cy; end if; end if; end process; -- load PSW from ALU (i.e. POP AF) or from flag signals load_psw <= '1' when we_rb='1' and rbank_wr_addr="0110" else '0'; -- The F register has been split in two separate groupt that always update -- together (C and all others). -- F register, flags S,Z,AC,P process(clk) begin if clk'event and clk='1' then if reset='1' then flag_reg(7) <= '0'; flag_reg(6) <= '0'; flag_reg(4) <= '0'; flag_reg(2) <= '0'; elsif flag_pattern(1) = '1' then if load_psw = '1' then flag_reg(7) <= alu_output(7); flag_reg(6) <= alu_output(6); flag_reg(4) <= alu_output(4); flag_reg(2) <= alu_output(2); else flag_reg(7) <= flag_s; flag_reg(6) <= flag_z; flag_reg(4) <= flag_ac; flag_reg(2) <= flag_p; end if; end if; end if; end procesS; -- F register, flag C process(clk) begin if clk'event and clk='1' then if reset = '1' then flag_reg(0) <= '0'; elsif flag_pattern(0) = '1' then if load_psw = '1' then flag_reg(0) <= alu_output(0); else flag_reg(0) <= flag_cy; end if; end if; end if; end procesS; flag_reg(5) <= '0'; -- constant flag flag_reg(3) <= '0'; -- constant flag flag_reg(1) <= '1'; -- constant flag --##### Condition computation condition_sel <= d_field(2 downto 0); with condition_sel select condition <= not flag_reg(6) when "000", -- NZ flag_reg(6) when "001", -- Z not flag_reg(0) when "010", -- NC flag_reg(0) when "011", -- C not flag_reg(2) when "100", -- PO flag_reg(2) when "101", -- PE not flag_reg(7) when "110", -- P flag_reg(7) when others;-- M -- condition is registered to shorten the delay path; the extra 1-cycle -- delay is not relevant because conditions are tested in the next instruction -- at the earliest, and there's at least the fetch uinsts intervening. process(clk) begin if clk'event and clk='1' then if reset = '1' then condition_reg <= '0'; else condition_reg <= condition; end if; end if; end process; -- low byte address register process(clk) begin if clk'event and clk='1' then if reset = '1' then addr_low <= X"00"; elsif load_al = '1' then addr_low <= rbank_data; end if; end if; end process; -- note external address registers (high byte) are loaded directly from rbank addr_out <= rbank_data & addr_low; data_out <= DO; end microcoded; -------------------------------------------------------------------------------- -- Timing diagram 1: RD and WR cycles -------------------------------------------------------------------------------- -- 1 2 3 4 5 6 7 8 -- __ __ __ __ __ __ __ __ -- clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__ -- -- addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx -- -- data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx -- -- data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx -- _____ _____ -- vma_o ______________/ \___________/ \___________ -- _____ -- rd_o ______________/ \_____________________________ -- _____ -- wr_o ________________________________/ \___________ -- -- (functional diagram, actual time delays not shown) -------------------------------------------------------------------------------- -- This diagram shows a read cycle and a write cycle back to back. -- In clock edges (4) and (7), the address is loaded into the external -- synchronous RAM address register. -- In clock edge (5), read data is loaded into the CPU. -- In clock edge (7), write data is loaded into the external synchronous RAM. -- In actual operation, the CPU does about 1 rd/wr cycle for each 5 clock -- cycles, which is a waste of RAM bandwidth. --	gpl-3.0
dhmeves/ece-485	ece-485-project-2/sign_extend.vhd	1	3179	library IEEE; use ieee.std_logic_1164.all; entity sign_extend is port( instr15_0 : in std_logic_vector(15 downto 0); clk, rst, pre, ce : in std_logic; output : out std_logic_vector(31 downto 0) ); end sign_extend; architecture behav of sign_extend is signal output_buf, output_buf0 : std_logic; begin DFF1 : entity work.d_flip_flop(behav) port map(clk, instr15_0(0), rst, pre, ce, output(0)); DFF2 : entity work.d_flip_flop(behav) port map(clk, instr15_0(1), rst, pre, ce, output(1)); DFF3 : entity work.d_flip_flop(behav) port map(clk, instr15_0(2), rst, pre, ce, output(2)); DFF4 : entity work.d_flip_flop(behav) port map(clk, instr15_0(3), rst, pre, ce, output(3)); DFF5 : entity work.d_flip_flop(behav) port map(clk, instr15_0(4), rst, pre, ce, output(4)); DFF6 : entity work.d_flip_flop(behav) port map(clk, instr15_0(5), rst, pre, ce, output(5)); DFF7 : entity work.d_flip_flop(behav) port map(clk, instr15_0(6), rst, pre, ce, output(6)); DFF8 : entity work.d_flip_flop(behav) port map(clk, instr15_0(7), rst, pre, ce, output(7)); DFF9 : entity work.d_flip_flop(behav) port map(clk, instr15_0(8), rst, pre, ce, output(8)); DFF10 : entity work.d_flip_flop(behav) port map(clk, instr15_0(9), rst, pre, ce, output(9)); DFF11 : entity work.d_flip_flop(behav) port map(clk, instr15_0(10), rst, pre, ce, output(10)); DFF12 : entity work.d_flip_flop(behav) port map(clk, instr15_0(11), rst, pre, ce, output(11)); DFF13 : entity work.d_flip_flop(behav) port map(clk, instr15_0(12), rst, pre, ce, output(12)); DFF14 : entity work.d_flip_flop(behav) port map(clk, instr15_0(13), rst, pre, ce, output(13)); DFF15 : entity work.d_flip_flop(behav) port map(clk, instr15_0(14), rst, pre, ce, output(14)); DFF16 : entity work.d_flip_flop(behav) port map(clk, instr15_0(15), rst, pre, ce, output(15)); output_buf0 <= instr15_0(15) when rst = '0' else '0' when rst = '1'; output_buf <= output_buf0 when pre = '0' else '1' when pre = '1'; output(16) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(17) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(18) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(19) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(20) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(21) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(22) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(23) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(24) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(25) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(26) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(27) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(28) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(29) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(30) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(31) <= '0' when output_buf = '0' else '1' when output_buf = '1'; end behav;	gpl-3.0
freecores/gpib_controller	vhdl/test/gpib_DT_Test.vhd	1	13686	-------------------------------------------------------------------------------- --This file is part of fpga_gpib_controller. -- -- Fpga_gpib_controller is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Fpga_gpib_controller is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------------------------------- -- Author: Andrzej Paluch -- -- Create Date: 23:21:05 10/21/2011 -- Design Name: -- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd -- Project Name: usbToHpib -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: gpibInterface -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; use work.gpibComponents.all; use work.helperComponents.all; ENTITY gpib_DT_Test IS END gpib_DT_Test; ARCHITECTURE behavior OF gpib_DT_Test IS -- Component Declaration for the Unit Under Test (UUT) component gpibCableEmulator is port ( -- interface signals DIO_1 : in std_logic_vector (7 downto 0); output_valid_1 : in std_logic; DIO_2 : in std_logic_vector (7 downto 0); output_valid_2 : in std_logic; DIO : out std_logic_vector (7 downto 0); -- attention ATN_1 : in std_logic; ATN_2 : in std_logic; ATN : out std_logic; -- data valid DAV_1 : in std_logic; DAV_2 : in std_logic; DAV : out std_logic; -- not ready for data NRFD_1 : in std_logic; NRFD_2 : in std_logic; NRFD : out std_logic; -- no data accepted NDAC_1 : in std_logic; NDAC_2 : in std_logic; NDAC : out std_logic; -- end or identify EOI_1 : in std_logic; EOI_2 : in std_logic; EOI : out std_logic; -- service request SRQ_1 : in std_logic; SRQ_2 : in std_logic; SRQ : out std_logic; -- interface clear IFC_1 : in std_logic; IFC_2 : in std_logic; IFC : out std_logic; -- remote enable REN_1 : in std_logic; REN_2 : in std_logic; REN : out std_logic ); end component; -- inputs common signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal T1 : std_logic_vector(7 downto 0) := "00000100"; -- inputs 1 signal data_1 : std_logic_vector(7 downto 0) := (others => '0'); signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0'); signal rdy_1 : std_logic := '0'; signal nba_1 : std_logic := '0'; signal ltn_1 : std_logic := '0'; signal lun_1 : std_logic := '0'; signal lon_1 : std_logic := '0'; signal ton_1 : std_logic := '0'; signal endOf_1 : std_logic := '0'; signal gts_1 : std_logic := '0'; signal rpp_1 : std_logic := '0'; signal tcs_1 : std_logic := '0'; signal tca_1 : std_logic := '0'; signal sic_1 : std_logic := '0'; signal rsc_1 : std_logic := '0'; signal sre_1 : std_logic := '0'; signal rtl_1 : std_logic := '0'; signal rsv_1 : std_logic := '0'; signal ist_1 : std_logic := '0'; signal lpe_1 : std_logic := '0'; -- inputs 2 signal data_2 : std_logic_vector(7 downto 0) := (others => '0'); signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0'); signal rdy_2 : std_logic := '0'; signal nba_2 : std_logic := '0'; signal ltn_2 : std_logic := '0'; signal lun_2 : std_logic := '0'; signal lon_2 : std_logic := '0'; signal ton_2 : std_logic := '0'; signal endOf_2 : std_logic := '0'; signal gts_2 : std_logic := '0'; signal rpp_2 : std_logic := '0'; signal tcs_2 : std_logic := '0'; signal tca_2 : std_logic := '0'; signal sic_2 : std_logic := '0'; signal rsc_2 : std_logic := '0'; signal sre_2 : std_logic := '0'; signal rtl_2 : std_logic := '0'; signal rsv_2 : std_logic := '0'; signal ist_2 : std_logic := '0'; signal lpe_2 : std_logic := '0'; -- outputs 1 signal dvd_1 : std_logic; signal wnc_1 : std_logic; signal tac_1 : std_logic; signal cwrc_1 : std_logic; signal cwrd_1 : std_logic; signal clr_1 : std_logic; signal trg_1 : std_logic; signal atl_1 : std_logic; signal att_1 : std_logic; signal mla_1 : std_logic; signal lsb_1 : std_logic; signal spa_1 : std_logic; signal ppr_1 : std_logic; signal sreq_1 : std_logic; signal isLocal_1 : std_logic; signal currentSecAddr_1 : std_logic_vector (4 downto 0); -- outputs 2 signal dvd_2 : std_logic; signal wnc_2 : std_logic; signal tac_2 : std_logic; signal cwrc_2 : std_logic; signal cwrd_2 : std_logic; signal clr_2 : std_logic; signal trg_2 : std_logic; signal atl_2 : std_logic; signal att_2 : std_logic; signal mla_2 : std_logic; signal lsb_2 : std_logic; signal spa_2 : std_logic; signal ppr_2 : std_logic; signal sreq_2 : std_logic; signal isLocal_2 : std_logic; signal currentSecAddr_2 : std_logic_vector (4 downto 0); -- common signal DO : std_logic_vector (7 downto 0); signal DI_1 : std_logic_vector (7 downto 0); signal output_valid_1 : std_logic; signal DI_2 : std_logic_vector (7 downto 0); signal output_valid_2 : std_logic; signal ATN_1, ATN_2, ATN : std_logic; signal DAV_1, DAV_2, DAV : std_logic; signal NRFD_1, NRFD_2, NRFD : std_logic; signal NDAC_1, NDAC_2, NDAC : std_logic; signal EOI_1, EOI_2, EOI : std_logic; signal SRQ_1, SRQ_2, SRQ : std_logic; signal IFC_1, IFC_2, IFC : std_logic; signal REN_1, REN_2, REN : std_logic; -- gpib reader signal buf_interrupt : std_logic; signal data_available : std_logic; signal last_byte_addr : std_logic_vector (3 downto 0); signal end_of_stream : std_logic; signal byte_addr : std_logic_vector (3 downto 0); signal data_out : std_logic_vector (7 downto 0); signal reset_buffer : std_logic := '0'; signal dataSecAddr : std_logic_vector (4 downto 0); -- gpib writer signal w_last_byte_addr : std_logic_vector (3 downto 0) := (others => '0'); signal w_end_of_stream : std_logic := '0'; signal w_data_available : std_logic := '0'; signal w_buf_interrupt : std_logic; signal w_data_in : std_logic_vector (7 downto 0); signal w_byte_addr : std_logic_vector (3 downto 0); signal w_reset_buffer : std_logic := '0'; type WR_BUF_TYPE is array (0 to 15) of std_logic_vector (7 downto 0); signal w_write_buffer : WR_BUF_TYPE; -- Clock period definitions constant clk_period : time := 2ps; BEGIN -- Instantiate the Unit Under Test (UUT) gpib1: gpibInterface PORT MAP ( clk => clk, reset => reset, isLE => '0', isTE => '0', lpeUsed => '0', fixedPpLine => "000", eosUsed => '0', eosMark => "00000000", myListAddr => "00001", myTalkAddr => "00001", secAddrMask => (others => '0'), data => data_1, status_byte => status_byte_1, T1 => T1, rdy => rdy_1, nba => nba_1, ltn => ltn_1, lun => lun_1, lon => lon_1, ton => ton_1, endOf => endOf_1, gts => gts_1, rpp => rpp_1, tcs => tcs_1, tca => tca_1, sic => sic_1, rsc => rsc_1, sre => sre_1, rtl => rtl_1, rsv => rsv_1, ist => ist_1, lpe => lpe_1, dvd => dvd_1, wnc => wnc_1, tac => tac_1, cwrc => cwrc_1, cwrd => cwrd_1, clr => clr_1, trg => trg_1, atl => atl_1, att => att_1, mla => mla_1, lsb => lsb_1, spa => spa_1, ppr => ppr_1, sreq => sreq_1, isLocal => isLocal_1, currentSecAddr => currentSecAddr_1, DI => DO, DO => DI_1, output_valid => output_valid_1, ATN_in => ATN, ATN_out => ATN_1, DAV_in => DAV, DAV_out => DAV_1, NRFD_in => NRFD, NRFD_out => NRFD_1, NDAC_in => NDAC, NDAC_out => NDAC_1, EOI_in => EOI, EOI_out => EOI_1, SRQ_in => SRQ, SRQ_out => SRQ_1, IFC_in => IFC, IFC_out => IFC_1, REN_in => REN, REN_out => REN_1 ); -- Instantiate the Unit Under Test (UUT) gpib2: gpibInterface PORT MAP ( clk => clk, reset => reset, isLE => '0', isTE => '0', lpeUsed => '0', fixedPpLine => "000", eosUsed => '0', eosMark => "00000000", myListAddr => "00010", myTalkAddr => "00010", secAddrMask => (others => '0'), data => data_2, status_byte => status_byte_2, T1 => T1, rdy => rdy_2, nba => nba_2, ltn => ltn_2, lun => lun_2, lon => lon_2, ton => ton_2, endOf => endOf_2, gts => gts_2, rpp => rpp_2, tcs => tcs_2, tca => tca_2, sic => sic_2, rsc => rsc_2, sre => sre_2, rtl => rtl_2, rsv => rsv_2, ist => ist_2, lpe => lpe_2, dvd => dvd_2, wnc => wnc_2, tac => tac_2, cwrc => cwrc_2, cwrd => cwrd_2, clr => clr_2, trg => trg_2, atl => atl_2, att => att_2, mla => mla_2, lsb => lsb_2, spa => spa_2, ppr => ppr_2, sreq => sreq_2, isLocal => isLocal_2, currentSecAddr => currentSecAddr_2, DI => DO, DO => DI_2, output_valid => output_valid_2, ATN_in => ATN, ATN_out => ATN_2, DAV_in => DAV, DAV_out => DAV_2, NRFD_in => NRFD, NRFD_out => NRFD_2, NDAC_in => NDAC, NDAC_out => NDAC_2, EOI_in => EOI, EOI_out => EOI_2, SRQ_in => SRQ, SRQ_out => SRQ_2, IFC_in => IFC, IFC_out => IFC_2, REN_in => REN, REN_out => REN_2 ); ce: gpibCableEmulator port map ( -- interface signals DIO_1 => DI_1, output_valid_1 => output_valid_1, DIO_2 => DI_2, output_valid_2 => output_valid_2, DIO => DO, -- attention ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN, DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV, NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD, NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC, EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI, SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ, IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC, REN_1 => REN_1, REN_2 => REN_2, REN => REN ); gr: gpibReader generic map (ADDR_WIDTH => 4) port map ( clk => clk, reset => reset, ------------------------------------------------------------------------ ------ GPIB interface -------------------------------------------------- ------------------------------------------------------------------------ data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2, ------------------------------------------------------------------------ ------ external interface ---------------------------------------------- ------------------------------------------------------------------------ isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr, buf_interrupt => buf_interrupt, data_available => data_available, last_byte_addr => last_byte_addr, end_of_stream => end_of_stream, byte_addr => byte_addr, data_out => data_out, reset_buffer => reset_buffer ); w_data_in <= w_write_buffer(conv_integer(w_byte_addr)); gw: gpibWriter generic map (ADDR_WIDTH => 4) port map ( clk => clk, reset => reset, ------------------------------------------------------------------------ ------ GPIB interface -------------------------------------------------- ------------------------------------------------------------------------ data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1, endOf => endOf_1, att => att_1, cwrc => cwrc_1, ------------------------------------------------------------------------ ------ external interface ---------------------------------------------- ------------------------------------------------------------------------ isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'), last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream, data_available => w_data_available, buf_interrupt => w_buf_interrupt, data_in => w_data_in, byte_addr => w_byte_addr, reset_buffer => w_reset_buffer ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 10 clock periods. reset <= '1'; wait for clk_period10; reset <= '0'; wait for clk_period10; -- requests system control rsc_1 <= '1'; -- interface clear sic_1 <= '1'; wait until IFC_1 = '1'; sic_1 <= '0'; wait until IFC_1 = '0'; assert trg_1 = '0'; assert trg_2 = '0'; -- send GET (device clear) w_write_buffer(0) <= "00001000"; w_last_byte_addr <= "0000"; w_data_available <= '1'; wait until w_buf_interrupt='1'; assert trg_1 = '0'; assert trg_2 = '0'; w_reset_buffer <= '1'; wait for clk_period2; w_reset_buffer <= '0'; -- gpib2 to listen w_write_buffer(0) <= "00100010"; w_last_byte_addr <= "0000"; w_data_available <= '1'; wait until w_buf_interrupt='1'; assert trg_1 = '0'; assert trg_2 = '0'; w_reset_buffer <= '1'; wait for clk_period2; w_reset_buffer <= '0'; -- send GET w_write_buffer(0) <= "00001000"; w_last_byte_addr <= "0000"; w_data_available <= '1'; wait until w_buf_interrupt='1'; assert trg_1 = '0'; assert trg_2 = '1'; report "$$$ END OF TEST - DT (device trigger) $$$"; wait; end process; END;	gpl-3.0
freecores/gpib_controller	vhdl/src/gpib_helper/MemoryBlock_by_logic.vhd	1	2416	-------------------------------------------------------------------------------- --This file is part of fpga_gpib_controller. -- -- Fpga_gpib_controller is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Fpga_gpib_controller is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------------------------------- -- Entity: MemoryBlock -- Date:2011-11-14 -- Author: Andrzej Paluch -- -- Description ${cursor} -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library UNISIM; use UNISIM.vcomponents.all; use work.utilPkg.all; use work.helperComponents.all; entity MemoryBlock is port ( reset : in std_logic; clk : in std_logic; ------------------------------------------------- p1_addr : in std_logic_vector(10 downto 0); p1_data_in : in std_logic_vector(7 downto 0); p1_strobe : in std_logic; p1_data_out : out std_logic_vector(7 downto 0); ------------------------------------------------- p2_addr : in std_logic_vector(10 downto 0); p2_data_in : in std_logic_vector(7 downto 0); p2_strobe : in std_logic; p2_data_out : out std_logic_vector(7 downto 0) ); end MemoryBlock; architecture arch of MemoryBlock is type mem is array(0 to 31) of std_logic_vector(7 downto 0); signal memory : mem; signal addrP1, addrP2 : integer range 0 to 31; begin addrP1 <= conv_integer(UNSIGNED(p1_addr)); addrP2 <= conv_integer(UNSIGNED(p2_addr)); process(reset, clk) begin if reset = '1' then elsif rising_edge(clk) then p1_data_out <= memory(addrP1); p2_data_out <= memory(addrP2); if p1_strobe = '1' then memory(addrP1) <= p1_data_in; end if; if p2_strobe = '1' then memory(addrP2) <= p2_data_in; end if; end if; end process; end arch;	gpl-3.0
freecores/gpib_controller	vhdl/src/gpib/if_func_PP.vhd	1	4923	-------------------------------------------------------------------------------- --This file is part of fpga_gpib_controller. -- -- Fpga_gpib_controller is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Fpga_gpib_controller is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>. ---------------------------------------------------------------------------------- -- Author: Andrzej Paluch -- -- Create Date: 01:04:57 10/03/2011 -- Design Name: -- Module Name: if_func_PP - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.utilPkg.all; entity if_func_PP is port( -- device inputs clk : in std_logic; -- clock -- settings lpeUsed : std_logic; fixedPpLine : in std_logic_vector (2 downto 0); -- local commands pon : in std_logic; -- power on lpe : in std_logic; -- local poll enable ist : in std_logic; -- individual status -- state inputs ACDS : in std_logic; -- accept data state LADS : in std_logic; -- listener address state (L or LE) -- data input dio_data : in std_logic_vector(3 downto 0); -- byte from data lines -- remote command inputs IDY : in std_logic; -- identify PPE : in std_logic; -- parallel poll enable PPD : in std_logic; -- parallel poll disable PPC : in std_logic; -- parallel poll configure PPU : in std_logic; -- parallel poll unconfigure PCG : in std_logic; -- primary command group -- remote command outputs PPR : out std_logic; -- paralel poll response -- PPR command data ppBitValue : out std_logic; -- bit value ppLineNumber : out std_logic_vector (2 downto 0); -- reported states PPAS : out std_logic -- parallel poll active state ); end if_func_PP; architecture Behavioral of if_func_PP is -- states type PP_STATE_1 is ( -- parallel poll idle state ST_PPIS, -- parallel poll standby state ST_PPSS, -- parallel poll active state ST_PPAS ); -- states type PP_STATE_2 is ( -- parallel poll unaddressed to configure state ST_PUCS, -- parallel poll addressed to configure state ST_PACS ); -- current state signal current_state_1 : PP_STATE_1; signal current_state_2 : PP_STATE_2; -- predicates signal pred1, pred2, pred3, pred4, pred5 : boolean; -- memorized PP metadata signal S : std_logic; signal lineAddr : std_logic_vector (2 downto 0); begin -- state machine process - PP_STATE_1 process(pon, clk) begin if pon = '1' then current_state_1 <= ST_PPIS; elsif rising_edge(clk) then case current_state_1 is ------------------ when ST_PPIS => if pred1 then S <= dio_data(3); lineAddr <= dio_data(2 downto 0); current_state_1 <= ST_PPSS; end if; ------------------ when ST_PPSS => if pred3 then current_state_1 <= ST_PPAS; elsif pred2 then current_state_1 <= ST_PPIS; end if; ------------------ when ST_PPAS => if not pred3 then current_state_1 <= ST_PPSS; end if; ------------------ when others => current_state_1 <= ST_PPIS; end case; end if; end process; -- state machine process - PP_STATE_2 process(pon, clk) begin if pon = '1' then current_state_2 <= ST_PUCS; elsif rising_edge(clk) then case current_state_2 is ------------------ when ST_PUCS => if pred4 then current_state_2 <= ST_PACS; end if; ------------------ when ST_PACS => if pred5 then current_state_2 <= ST_PUCS; end if; ------------------ when others => current_state_2 <= ST_PUCS; end case; end if; end process; ppBitValue <= (not S xor ist) when lpeUsed='0' else ist; ppLineNumber <= lineAddr when lpeUsed='0' else fixedPpLine; PPR <= to_stdl(current_state_1 = ST_PPAS); PPAS <= to_stdl(current_state_1 = ST_PPAS); -- predicates with lpeUsed select pred1 <= is_1(lpe) when '1', PPE='1' and current_state_2=ST_PACS and ACDS='1' when others; with lpeUsed select pred2 <= is_1(not lpe) when '1', ((PPD='1' and current_state_2=ST_PACS) or PPU='1') and ACDS='1' when others; pred3 <= IDY='1'; pred4 <= PPC='1' and LADS='1' and ACDS='1'; pred5 <= PCG='1' and PPC='0' and ACDS='1'; end Behavioral;	gpl-3.0
MonsieurOenologue/Paprotto	subNbits.vhd	1	983	--Libraries imports library ieee; use ieee.std_logic_1164.all; --Entity declaration ENTITY subNbits IS GENERIC( N : IN NATURAL := 16 ); PORT( A, B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); Cin : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); Cout : OUT STD_LOGIC ); END; --Architecture behavior ARCHITECTURE behavior OF subNbits IS COMPONENT minNbits IS GENERIC( N : IN NATURAL := 16 ); PORT( A : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ); END COMPONENT; COMPONENT faG IS GENERIC( N : IN NATURAL := 16 ); PORT( A, B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); Cin : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); Cout : OUT STD_LOGIC ); END COMPONENT; SIGNAL tempB : STD_LOGIC_VECTOR(N-1 DOWNTO 0); SIGNAL tempCo : STD_LOGIC_VECTOR(N-1 DOWNTO 0); BEGIN min : minNbits GENERIC MAP (N) PORT MAP (B, tempB); add : faG GENERIC MAP (N) PORT MAP (A, tempB, Cin, S, Cout); END;	gpl-3.0
MonsieurOenologue/Paprotto	topLevel.vhd	1	817	--Libraries imports library ieee; use ieee.std_logic_1164.all; --Entity declaration ENTITY topLevel IS PORT( BT : IN STD_LOGIC_VECTOR(2 DOWNTO 0); SW : IN STD_LOGIC_VECTOR(15 DOWNTO 0); LEDG : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END; --Architecture behavior ARCHITECTURE behavior OF topLevel IS COMPONENT Paprotto IS GENERIC( N : IN NATURAL := 16 ); PORT( clk : IN STD_LOGIC; reset : IN std_logic; run : IN std_logic; code : IN std_logic_vector(15 DOWNTO 0); done : OUT std_logic; overflow : OUT std_logic ); END COMPONENT; SIGNAL databus : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN databus <= (OTHERS => '0'); LEDG(0) <= BT(0); CPU : Paprotto GENERIC MAP (16) PORT MAP(BT(2), BT(1), BT(0), SW, databus(1), LEDG(1)); END;	gpl-3.0
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iamllama/EE2020	ee2020.ip_user_files/ipstatic/hdl/lib_pkg_v1_0_rfs.vhd	6	16353	-- Processor Common Library Package ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: lib_pkg.vhd -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- need conversion function to convert reals/integers to std logic vectors use ieee.std_logic_arith.conv_std_logic_vector; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package lib_pkg is ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- type CHAR_TO_INT_TYPE is array (character) of integer; -- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer; -- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63); ------------------------------------------------------------------------------- -- Function and Procedure Declarations ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer; function min2 (num1, num2 : integer) return integer; function Addr_Bits(x,y : std_logic_vector) return integer; function clog2(x : positive) return natural; function pad_power2 ( in_num : integer ) return integer; function pad_4 ( in_num : integer ) return integer; function log2(x : natural) return integer; function pwr(x: integer; y: integer) return integer; function String_To_Int(S : string) return integer; function itoa (int : integer) return string; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- the RESET_ACTIVE constant should denote the logic level of an active reset constant RESET_ACTIVE : std_logic := '1'; -- table containing strings representing hex characters for conversion to -- integers constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE := ('0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4, '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, 'A'\|'a' => 10, 'B'\|'b' => 11, 'C'\|'c' => 12, 'D'\|'d' => 13, 'E'\|'e' => 14, 'F'\|'f' => 15, others => -1); end lib_pkg; package body lib_pkg is ------------------------------------------------------------------------------- -- Function Definitions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Function max2 -- -- This function returns the greater of two numbers. ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer is begin if num1 >= num2 then return num1; else return num2; end if; end function max2; ------------------------------------------------------------------------------- -- Function min2 -- -- This function returns the lesser of two numbers. ------------------------------------------------------------------------------- function min2 (num1, num2 : integer) return integer is begin if num1 <= num2 then return num1; else return num2; end if; end function min2; ------------------------------------------------------------------------------- -- Function Addr_bits -- -- function to convert an address range (base address and an upper address) -- into the number of upper address bits needed for decoding a device -- select signal. will handle slices and big or little endian ------------------------------------------------------------------------------- function Addr_Bits(x,y : std_logic_vector) return integer is variable addr_xor : std_logic_vector(x'range); variable count : integer := 0; begin assert x'length = y'length and (x'ascending xnor y'ascending) report "Addr_Bits: arguments are not the same type" severity ERROR; addr_xor := x xor y; for i in x'range loop if addr_xor(i) = '1' then return count; end if; count := count + 1; end loop; return x'length; end Addr_Bits; -------------------------------------------------------------------------------- -- Function clog2 - returns the integer ceiling of the base 2 logarithm of x, -- i.e., the least integer greater than or equal to log2(x). -------------------------------------------------------------------------------- function clog2(x : positive) return natural is variable r : natural := 0; variable rp : natural := 1; -- rp tracks the value 2r begin while rp < x loop -- Termination condition T: x <= 2r -- Loop invariant L: 2(r-1) < x r := r + 1; if rp > integer'high - rp then exit; end if; -- If doubling rp overflows -- the integer range, the doubled value would exceed x, so safe to exit. rp := rp + rp; end loop; -- L and T <-> 2(r-1) < x <= 2r <-> (r-1) < log2(x) <= r return r; -- end clog2; ------------------------------------------------------------------------------- -- Function pad_power2 -- -- This function returns the next power of 2 from the input number. If the -- input number is a power of 2, this function returns the input number. -- -- This function is used to round up the number of masters to the next power -- of 2 if the number of masters is not already a power of 2. -- -- Input argument 0, which is not a power of two, is accepted and returns 0. -- Input arguments less than 0 are not allowed. ------------------------------------------------------------------------------- -- function pad_power2 (in_num : integer ) return integer is begin if in_num = 0 then return 0; else return 2(clog2(in_num)); end if; end pad_power2; ------------------------------------------------------------------------------- -- Function pad_4 -- -- This function returns the next multiple of 4 from the input number. If the -- input number is a multiple of 4, this function returns the input number. -- ------------------------------------------------------------------------------- -- function pad_4 (in_num : integer ) return integer is variable out_num : integer; begin out_num := (((in_num-1)/4) + 1)4; return out_num; end pad_4; ------------------------------------------------------------------------------- -- Function log2 -- returns number of bits needed to encode x choices -- x = 0 returns 0 -- x = 1 returns 0 -- x = 2 returns 1 -- x = 4 returns 2, etc. ------------------------------------------------------------------------------- -- function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; end function log2; ------------------------------------------------------------------------------- -- Function pwr -- xy -- negative numbers not allowed for y ------------------------------------------------------------------------------- function pwr(x: integer; y: integer) return integer is variable z : integer := 1; begin if y = 0 then return 1; else for i in 1 to y loop z := z x; end loop; return z; end if; end function pwr; ------------------------------------------------------------------------------- -- Function itoa -- -- The itoa function converts an integer to a text string. -- This function is required since `image doesn't work in Synplicity -- Valid input range is -9999 to 9999 ------------------------------------------------------------------------------- -- function itoa (int : integer) return string is type table is array (0 to 9) of string (1 to 1); constant LUT : table := ("0", "1", "2", "3", "4", "5", "6", "7", "8", "9"); variable str1 : string(1 to 1); variable str2 : string(1 to 2); variable str3 : string(1 to 3); variable str4 : string(1 to 4); variable str5 : string(1 to 5); variable abs_int : natural; variable thousands_place : natural; variable hundreds_place : natural; variable tens_place : natural; variable ones_place : natural; variable sign : integer; begin abs_int := abs(int); if abs_int > int then sign := -1; else sign := 1; end if; thousands_place := abs_int/1000; hundreds_place := (abs_int-thousands_place1000)/100; tens_place := (abs_int-thousands_place1000-hundreds_place100)/10; ones_place := (abs_int-thousands_place1000-hundreds_place100-tens_place10); if sign>0 then if thousands_place>0 then str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif hundreds_place>0 then str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str3; elsif tens_place>0 then str2 := LUT(tens_place) & LUT(ones_place); return str2; else str1 := LUT(ones_place); return str1; end if; else if thousands_place>0 then str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str5; elsif hundreds_place>0 then str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif tens_place>0 then str3 := "-" & LUT(tens_place) & LUT(ones_place); return str3; else str2 := "-" & LUT(ones_place); return str2; end if; end if; end itoa; ----------------------------------------------------------------------------- -- Function String_To_Int -- -- Converts a string of hex character to an integer -- accept negative numbers ----------------------------------------------------------------------------- function String_To_Int(S : String) return Integer is variable Result : integer := 0; variable Temp : integer := S'Left; variable Negative : integer := 1; begin for I in S'Left to S'Right loop if (S(I) = '-') then Temp := 0; Negative := -1; else Temp := STRHEX_TO_INT_TABLE(S(I)); if (Temp = -1) then assert false report "Wrong value in String_To_Int conversion " & S(I) severity error; end if; end if; Result := Result * 16 + Temp; end loop; return (Negative * Result); end String_To_Int; end package body lib_pkg;	gpl-3.0
kjellhar/ArtixPi	spi_test/src/hdl/spi_slave_old.vhd	1	5579	---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 06/16/2016 04:17:04 AM -- Design Name: -- Module Name: spi_slave - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity spi_slave is Generic ( N : positive := 8; CPOL : std_logic := '0'; CPHA : std_logic := '0' ); Port ( clk : in STD_LOGIC; -- External SPI signals spi_ss_n : in STD_LOGIC; spi_clk : in STD_LOGIC; spi_mosi : in STD_LOGIC; spi_miso : out STD_LOGIC; -- Internal data signals di : out STD_LOGIC_VECTOR (N-1 downto 0); -- Data received from SPI do : in STD_LOGIC_VECTOR (N-1 downto 0); -- Data to be transmitted over SPI di_valid : out std_logic; -- High for one clock cycle to indicate a new word is present do_wren : in std_logic; -- Write a data word to the transmit register do_wrack : out std_logic); -- High for one clock cycle when the transmission starts. -- The next data word can be written as soon as this signal goes low. end spi_slave; architecture Behavioral of spi_slave is -- constants to control FlipFlop synthesis constant CAPTURE_EDGE : std_logic := (CPOL xnor CPHA); constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); type spi_state_t is ( IDLE, INIT_TRANSACTION, SHIFTING_DATA, WORD_COMPLETE ); signal spi_state : spi_state_t := IDLE; signal spi_state_next : spi_state_t; signal spi_clk_buf : std_logic := CPOL; signal spi_capture_edge : std_logic; signal spi_change_edge : std_logic; signal di_buf : std_logic; signal di_reg : std_logic_vector(N-1 downto 0); signal do_reg : std_logic_vector(N-1 downto 0); signal do_i : std_logic_vector(N-1 downto 0); signal bit_counter : integer range 0 to N-1 := 0; begin -- state register process begin wait until rising_edge (clk); if spi_ss_n='1' then spi_state <= IDLE; else spi_state <= spi_state_next; end if; end process; -- Next state logic process ( spi_state, spi_ss_n, bit_counter) begin spi_state_next <= spi_state; case (spi_state) is when IDLE => if spi_ss_n='0' then spi_state_next <= INIT_TRANSACTION; end if; when INIT_TRANSACTION => spi_state_next <= SHIFTING_DATA; when SHIFTING_DATA => if bit_counter=N-1 then spi_state_next <= WORD_COMPLETE; end if; when WORD_COMPLETE => if bit_counter = 0 then spi_state_next <= INIT_TRANSACTION; end if; when others => spi_state_next <= IDLE; end case; end process; -- SPI clock edge detector process begin wait until rising_edge(clk); spi_clk_buf <= spi_clk; if (spi_clk_buf= not spi_clk) and spi_clk=CAPTURE_EDGE then spi_capture_edge <= '1'; else spi_capture_edge <= '0'; end if; if (spi_clk_buf= not spi_clk) and spi_clk=CHANGE_EDGE then spi_change_edge <= '1'; else spi_change_edge <= '0'; end if; end process; -- Input shift register process begin wait until rising_edge(clk); di_buf <= spi_mosi; if spi_capture_edge='1' then di_reg <= di_reg(N-2 downto 0) & di_buf; bit_counter <= bit_counter + 1; end if; end process; -- output received data word process begin wait until rising_edge(clk); di_valid <= '0'; if spi_state=WORD_COMPLETE and bit_counter=0 then di <= di_reg; di_valid <= '1'; end if; end process; -- get data word for tx process begin wait until rising_edge(clk); if do_wren='1' then do_i <= do; end if; end process; -- output shift register process begin wait until rising_edge(clk); do_wrack <= '0'; if spi_state = IDLE then do_reg <= X"00"; elsif spi_state = INIT_TRANSACTION then do_reg <= do_i; do_wrack <= '1'; elsif spi_change_edge='1' and bit_counter /= 0 then do_reg <= do_reg(N-2 downto 0) & '0'; end if; end process; spi_miso <= do_reg(7); end Behavioral;	gpl-3.0
aylons/concordic	hdl/modules/cordic_vectoring/cordic_vectoring_wb.vhd	1	9110	------------------------------------------------------------------------------- -- Title : Wishbonized vectoring CORDIC -- Project : ------------------------------------------------------------------------------- -- File : cordic_vectoring_wb.vhd -- Author : aylons <aylons@LNLS190> -- Company : -- Created : 2014-09-03 -- Last update: 2014-11-19 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Wishbonized version of the CORDIC in vectoring mode. This -- module is transparent for both TGD and ADR, but to reduce area use, it may -- me set to only accept a maximum number of simultaneous data points being -- calculated. It may also accept parallel or serial I/Q data. ------------------------------------------------------------------------------- -- Copyright (c) 2014 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2014-09-03 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.genram_pkg.all; use work.wb_stream_pkg.all; ------------------------------------------------------------------------------- -- Input data structure: -- I = (g_width2)-1 downto g_width -- Q = g_width-1 downto 0; -- Output data structure: -- mag = (g_width2)-1 downto g_width -- phase = g_width-1 downto 0 entity cordic_vectoring_wb is generic ( g_stages : natural := 32; g_width : natural := 32; g_simultaneous : natural := 4; g_parallel : boolean := true; g_tgd_width : natural := 4; g_adr_width : natural := 3; g_input_buffer : natural := 4; g_output_buffer : natural := 2 ); port ( clk_i : in std_logic; rst_i : in std_logic; ce_i : in std_logic; snk_i : in t_wbs_sink_in; snk_o : out t_wbs_sink_out; src_i : in t_wbs_source_in; src_o : out t_wbs_source_out ); end entity cordic_vectoring_wb; ------------------------------------------------------------------------------- architecture str of cordic_vectoring_wb is signal data_sink, data_source : std_logic_vector(g_width2-1 downto 0) := (others => '0'); signal metadata_sink, metadata_source : std_logic_vector(g_tgd_width + g_adr_width - 1 downto 0); signal I : std_logic_vector(g_width-1 downto 0) := (others => '0'); signal Q : std_logic_vector(g_width-1 downto 0) := (others => '0'); signal mag : std_logic_vector(g_width-1 downto 0) := (others => '0'); signal phase : std_logic_vector(g_width-1 downto 0) := (others => '0'); signal tgd_sink : std_logic_vector(g_tgd_width-1 downto 0) := (others => '0'); signal adr_sink : std_logic_vector(g_adr_width-1 downto 0) := (others => '0'); signal valid_sink : std_logic := '0'; signal tgd_source : std_logic_vector(g_tgd_width-1 downto 0) := (others => '0'); signal adr_source : std_logic_vector(g_adr_width-1 downto 0) := (others => '0'); signal valid_source : std_logic := '0'; signal source_req : std_logic; signal ack_sink : std_logic; signal ack_source : std_logic; signal full_meta : std_logic; signal rst_n : std_logic; ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- component cordic_vectoring_slv is generic ( g_stages : natural; g_width : natural); port ( x_i : in std_logic_vector(g_width-1 downto 0) := (others => '0'); y_i : in std_logic_vector(g_width-1 downto 0) := (others => '0'); clk_i : in std_logic; ce_i : in std_logic; valid_i : in std_logic; rst_i : in std_logic; mag_o : out std_logic_vector(g_width-1 downto 0) := (others => '0'); phase_o : out std_logic_vector(g_width-1 downto 0) := (others => '0'); valid_o : out std_logic); end component cordic_vectoring_slv; component decoupled_fifo is generic ( g_fifo_width : natural; g_fifo_depth : natural); port ( rst_n_i : in std_logic; clk_i : in std_logic; d_i : in std_logic_vector(g_fifo_width-1 downto 0); we_i : in std_logic; rd_i : in std_logic; full_o : out std_logic; d_o : out std_logic_vector(g_fifo_width-1 downto 0); valid_o : out std_logic); end component decoupled_fifo; component generic_shiftreg_fifo is generic ( g_data_width : integer; g_size : integer); port ( rst_n_i : in std_logic := '1'; clk_i : in std_logic; d_i : in std_logic_vector(g_data_width-1 downto 0); we_i : in std_logic; q_o : out std_logic_vector(g_data_width-1 downto 0); rd_i : in std_logic; full_o : out std_logic; almost_full_o : out std_logic; q_valid_o : out std_logic); end component generic_shiftreg_fifo; component xwb_stream_sink is generic ( g_data_width : natural; g_addr_width : natural; g_tgd_width : natural; g_buffer_depth : natural); port ( clk_i : in std_logic; rst_n_i : in std_logic; snk_i : in t_wbs_sink_in; snk_o : out t_wbs_sink_out; addr_o : out std_logic_vector(g_adr_width-1 downto 0); data_o : out std_logic_vector(g_data_width-1 downto 0); tgd_o : out std_logic_vector(g_tgd_width-1 downto 0); error_o : out std_logic; dvalid_o : out std_logic; dreq_i : in std_logic); end component xwb_stream_sink; component xwb_stream_source is generic ( g_data_width : natural; g_addr_width : natural; g_tgd_width : natural; g_buffer_depth : natural); port ( clk_i : in std_logic; rst_n_i : in std_logic; src_i : in t_wbs_source_in; src_o : out t_wbs_source_out; addr_i : in std_logic_vector(g_adr_width-1 downto 0); data_i : in std_logic_vector(g_data_width-1 downto 0); tgd_i : in std_logic_vector(g_tgd_width-1 downto 0); dvalid_i : in std_logic; error_i : in std_logic; dreq_o : out std_logic); end component xwb_stream_source; begin -- architecture str rst_n <= not(rst_i); cmp_wb_sink : xwb_stream_sink generic map ( g_data_width => g_width2, g_addr_width => g_adr_width, g_tgd_width => g_tgd_width, g_buffer_depth => g_input_buffer) port map ( clk_i => clk_i, rst_n_i => rst_n, snk_i => snk_i, snk_o => snk_o, addr_o => adr_sink, data_o => data_sink, tgd_o => tgd_sink, error_o => open, -- no error treatment dvalid_o => valid_sink, dreq_i => ack_sink); I <= data_sink(g_width2-1 downto g_width); Q <= data_sink(g_width-1 downto 0); cmp_cordic : cordic_vectoring_slv generic map ( g_stages => g_stages, g_width => g_width) port map ( x_i => I, y_i => Q, clk_i => clk_i, ce_i => ce_i, valid_i => ack_sink, rst_i => rst_i, mag_o => mag, phase_o => phase, valid_o => valid_source); data_source(g_width2-1 downto g_width) <= mag; data_source(g_width-1 downto 0) <= phase; -- Metadata metadata_sink <= tgd_sink & adr_sink; ack_sink <= not(full_meta) and ce_i and valid_sink; ack_source <= source_req and ce_i and valid_source; -- Stop accepting new data if full cmp_metadata : decoupled_fifo generic map( g_fifo_width => g_adr_width + g_tgd_width, g_fifo_depth => g_simultaneous) port map ( rst_n_i => rst_n, clk_i => clk_i, d_i => metadata_sink, we_i => ack_sink, rd_i => ack_source, d_o => metadata_source, full_o => full_meta); tgd_source <= metadata_source(g_tgd_width + g_adr_width - 1 downto g_adr_width); adr_source <= metadata_source(g_adr_width - 1 downto 0); cmp_wb_source : xwb_stream_source generic map ( g_data_width => g_width*2, g_addr_width => g_adr_width, g_tgd_width => g_tgd_width, g_buffer_depth => g_output_buffer) port map ( clk_i => clk_i, rst_n_i => rst_n, src_i => src_i, src_o => src_o, addr_i => adr_source, data_i => data_source, tgd_i => tgd_source, dvalid_i => ack_source, error_i => '0', --error is only forwarded through TGD dreq_o => source_req); end architecture str; -------------------------------------------------------------------------------	gpl-3.0
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thequbit/af_paper	code/xilinx/pixel_difference_2d.vhd	1	1935	library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity pixel_difference_2d is Port ( i_clk : in STD_LOGIC; i_reset : in STD_LOGIC; i_R : in STD_LOGIC_VECTOR (7 downto 0); i_G : in STD_LOGIC_VECTOR (7 downto 0); i_B : in STD_LOGIC_VECTOR (7 downto 0); i_framevalid : in STD_LOGIC; i_linevalid : in STD_LOGIC; o_focusvalue : out STD_LOGIC_VECTOR(31 downto 0); o_dv : out STD_LOGIC ); end pixel_difference_2d; architecture Behavioral of pixel_difference_2d is COMPONENT color_space_converter PORT( i_clk : IN std_logic; i_reset : IN std_logic; i_R : IN std_logic_vector(7 downto 0); i_G : IN std_logic_vector(7 downto 0); i_B : IN std_logic_vector(7 downto 0); i_framevalid : IN std_logic; i_linevalid : IN std_logic; o_Y : OUT std_logic_vector(7 downto 0); o_framevalid : OUT std_logic; o_linevalid : OUT std_logic ); END COMPONENT; COMPONENT focus_calculation_pixel_difference_2d PORT( i_clk : IN std_logic; i_reset : IN std_logic; i_framevalid : IN std_logic; i_linevalid : IN std_logic; i_Y : IN std_logic_vector(7 downto 0); o_focusvalue : OUT std_logic_vector(31 downto 0); o_dv : OUT std_logic ); END COMPONENT; signal s_framevalid : STD_LOGIC; signal s_linevalid : STD_LOGIC; signal s_Y : STD_LOGIC_VECTOR(7 downto 0); begin Inst_color_space_converter: color_space_converter PORT MAP( i_clk => i_clk, i_reset => i_reset, i_R => i_R, i_G => i_G, i_B => i_B, i_framevalid => i_framevalid, i_linevalid => i_linevalid, o_Y => s_Y, o_framevalid => s_framevalid, o_linevalid => s_linevalid ); Inst_focus_calculation: focus_calculation_pixel_difference_2d PORT MAP( i_clk => i_clk, i_reset => i_reset, i_framevalid => s_framevalid, i_linevalid => s_linevalid, i_Y => s_Y, o_focusvalue => o_focusvalue, o_dv => o_dv ); end Behavioral;	gpl-3.0
iamllama/EE2020	ee2020.ip_user_files/ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd	1	94635	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block US61vRgaZan+kknoy1SnPxYNjkAw9TnKUufX6w+IcDeMGtqyYNromlIoLLZTg7jQub7nmjw8eWCP cY1aOfugKQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Cx+xG/jU1l+emWfaLPy7CXAXh1exaDmq8ZyJFnbt9CiAkRn3KSw//ly11TqIhymDcuIoqbSi8MB5 XrNKColQ8j763aa+JmESdVAhEDb3vw6vtSFZhbGzZ+gjqujywOuXpV4RLNfzGSHZi3T16jM00CVJ fZxkJaQO9Fnkhwc8+vQ= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4Jy/G3k875kthkA+QXWVjNJCNwrRuzDRSO4U5SzIrTbbuz2aX5Xp4gdKyvxdy5P5c+15hwjfMoNZ +VVbrsGViLFoYppHRzxDEhRr/Z6F8XPkdTBoLInA9yJ+mYNZhQr64k9PR9eRkJxYBGK6W09bLins fU3gdCNnvLaQsEgQWOU= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block O3ONP1KwZNdtuP9sQrFAGFl1CQVtyHjI34FdzXCxkhnhpnVMoCFa2bat3r3ak9golPUlczWtN0jo cytKpPs0SaxChx/s4TD/Jpte3nH6+gHdXFv3YP0NOc/iKUmQgAiXM9q5guBlRZNedAOgC7ZNjWT1 Rt1+NX52E+ATBH5d0S0rLA2lEWoebGEU6em7iO3RRFv58wLYKtkZbSWacxpZbMIxSbJPxJ8NPzuV YmvdoxSZWBO1C+KYAg7Al2wiIft4HX6SoDn5Y9uVpfcwwCdiRWkxQ2abVNmyyU9hBi3N9Rr5InLH wYwMquteT+a7hr7aUPPAeIaQewrj7Qz4gd1ZUA== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Vl+IzaoqzSXKOjWO99voPmAJ45URn945lCsMwx/p8gv5xg1P5LlGlBmC2PIT77XLV5lUoSbGKLW+ DN5UQduw74Bifv4122q5Y/f+GO2pdYJFdG28hMNvIqwsSLCy29sNSlzvjzRtU4AkfH9fo04VL9cu TqDIdChGPUawshMyIVdh9p2YqGesdAQjd653Jn4sZlLtoVZQfhRUVSAtojoyY55j0D17145KIhRH NP6jtdJbH2pgd6LKRZWb/ZPFOUVoz1tuHmF0Nx6nDc1Xoc2PwceLECqX2mTdvSLNHV2nRxZ5etGR a1GAuoTGmhBqyEg87HaNCj8xMPLE/Cc0a+89pg== `protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block olBNwKJ0hFE6IA6yPORaakXGltQcqHq2WBYFtXgtfLg0YTDpPojC6VULF+1C3s6WRubbW32qeBw9 uUPCsZO4PocNSP4MtrQbjysq1Xq4uUDFpe7+ooS5esPqi0vW/Vgynis/a4biFFMuVi5FIHk3mPEU F5y/g0XXxQHs/SNu5DKimQ1EB32qve0/dFJrINlJJaIfuMujCcJi8hRkxxJD26CsriXUdlM5IjvR vrNasTLHyuFkEVMzphJMxL+WOc5tRkoS6HCDjF+BttPFv+x1yz1a/J6b7jevZd8J6/tZBtxHxgzl gNnRYdEykPRCETc3Lbq7yGRgAn2jI1VgtdXTgw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920) `protect 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suoto/hdlcc	.ci/test_support/test_project/basic_library/two_entities_one_file.vhd	1	96	entity entity_a is end entity; entity entity_a is end entity; entity entity_b is end entity;	gpl-3.0
hiyuh/nvc	test/regress/issue59.vhd	5	752	package p is pure function f( i : boolean ) return integer; end package p; package body p is pure function f( i : boolean ) return integer is begin if (i = false) then return 0; else return 1; end if; end function f; end package body p; ------------------------------------------------------------------------------- use work.p.all; package q is constant d : integer := f(true) + 1; end package q; package body q is end package body q; ------------------------------------------------------------------------------- use work.q.all; entity issue59 is begin assert (d = 2); end entity issue59; architecture a of issue59 is begin end architecture a;	gpl-3.0
hiyuh/nvc	test/regress/issue204.vhd	5	228	entity issue204 is end entity; architecture a of issue204 is type enum_t is (a, b); begin main : process begin assert enum_t'leftof(b) = a; assert enum_t'rightof(a) = b; wait; end process; end architecture;	gpl-3.0
hiyuh/nvc	test/sem/issue221.vhd	5	723	package fred4 is type fred4_t is protected impure function is_empty return boolean; impure function hi_there return string; end protected fred4_t; end package fred4; package body fred4 is type fred4_t is protected body ---------------------------------------- impure function is_empty return boolean is begin return TRUE; end function is_empty; ---------------------------------------- impure function hi_there return string is begin if is_empty then return "perfect"; else return "we have a problem"; end if; end function hi_there; ---------------------------------------- end protected body fred4_t; end package body fred4;	gpl-3.0
dobairoland/ZyEHW	hw/hdl/axi_evol.vhd	1	14526	-- Copyright (C) 2014 Roland Dobai -- -- This file is part of ZyEHW. -- -- ZyEHW is free software: you can redistribute it and/or modify it under the -- terms of the GNU General Public License as published by the Free Software -- Foundation, either version 3 of the License, or (at your option) any later -- version. -- -- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY -- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS -- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more -- details. -- -- You should have received a copy of the GNU General Public License along -- with ZyEHW. If not, see <http://www.gnu.org/licenses/>. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.zyehw_pkg.all; entity axi_evol is port ( s_axi_aclk: in std_logic; s_axi_aresetn: in std_logic; s_axi_arvalid: in std_logic; s_axi_awvalid: in std_logic; s_axi_bready: in std_logic; s_axi_rready: in std_logic; s_axi_wvalid: in std_logic; s_axi_arprot: in std_logic_vector(2 downto 0); s_axi_awprot: in std_logic_vector(2 downto 0); s_axi_araddr: in std_logic_vector(31 downto 0); s_axi_awaddr: in std_logic_vector(31 downto 0); s_axi_wdata: in std_logic_vector(31 downto 0); s_axi_wstrb: in std_logic_vector(3 downto 0); s_axi_arready: out std_logic; s_axi_awready: out std_logic; s_axi_bvalid: out std_logic; s_axi_rvalid: out std_logic; s_axi_wready: out std_logic; s_axi_bresp: out std_logic_vector(1 downto 0); s_axi_rresp: out std_logic_vector(1 downto 0); s_axi_rdata: out std_logic_vector(31 downto 0); end_flag: in std_logic; start_rst: in std_logic; fitness: in fitness_arr_t; fifo_rderr: in std_logic; fifo_wrerr: in std_logic; frame_count: in frame_count_t; start_flag: out std_logic; chromosome: out mux_chromosome_arr_t ); end axi_evol; architecture beh_axi_evol of axi_evol is constant addr_width: integer:= 32; constant data_width: integer:= 32; constant numregisters: integer:= 1 -- control/status + population -- fitness + population ( -- chromosome 2( -- a and b inputs columnsrows -- PEs input_sel_width/data_width ) + 1 -- out multiplexers ); constant w32bytes: integer:= data_width/8; constant word_bits: integer:= integer(ceil(log2(real(w32bytes)))); constant reg_bits: integer:= integer(ceil(log2(real(numregisters)))); signal writeaddr, readaddr: std_logic_vector(reg_bits-1 downto 0); signal awready: std_logic; signal wready: std_logic; signal bvalid: std_logic; signal arready: std_logic; signal rdata: std_logic_vector(addr_width-1 downto 0); signal rvalid: std_logic; subtype reg_t is std_logic_vector(data_width-1 downto 0); type regs_t is array (0 to numregisters-1) of reg_t; signal databus: std_logic_vector(data_width-1 downto 0); signal regs: regs_t; signal reg_rden: std_logic; signal reg_wren: std_logic; begin -- Only the start_flag and the chromosome are real registers here. -- The end_flag, fifo_rderr, fifo_wrerr are read together with start_flag -- and are read-only. The fitness is also read-only. -- Addressing -- mux bits: -- (31..28) (27..24) (23..20) (19..16) (15..12) (11..8) (7..4) (3..0) -- -- regs(0) - (3) fifo_wrerr, (2) fifo_rderr, (1) end_flag, (0) start_flag -- Individual 0: -- regs( 1) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs( 2) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs( 3) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs( 4) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs( 5) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs( 6) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs( 7) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs( 8) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs( 9) - (3..2) filter_switch, (1..0) out_select -- Individual 1: -- regs(10) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(11) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(12) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(13) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(14) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(15) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(16) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(17) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(18) - (3..2) filter_switch, (1..0) out_select -- Individual 2: -- regs(19) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(20) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(21) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(22) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(23) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(24) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(25) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(26) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(27) - (3..2) filter_switch, (1..0) out_select -- Individual 3: -- regs(28) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(29) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(30) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(31) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(32) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(33) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(34) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(35) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(36) - (3..2) filter_switch, (1..0) out_select -- Individual 4: -- regs(37) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(38) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(39) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(40) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(41) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(42) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(43) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(44) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(45) - (3..2) filter_switch, (1..0) out_select -- Individual 5: -- regs(46) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(47) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(48) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(49) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(50) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(51) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(52) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(53) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(54) - (3..2) filter_switch, (1..0) out_select -- regs(55) - fitness of individual 0 -- regs(56) - fitness of individual 1 -- regs(57) - fitness of individual 2 -- regs(58) - fitness of individual 3 -- regs(59) - fitness of individual 4 -- regs(60) - fitness of individual 5 start_flag <= regs(0)(0); regs(0)(1) <= end_flag; regs(0)(2) <= fifo_rderr; regs(0)(3) <= fifo_wrerr; regs(0)(reg_t'high downto 4) <= frame_count; chrom_intconn: for i in 0 to population-1 generate chrom_col: for j in 0 to columns-1 generate chrom_row: for k in 0 to rows-1 generate chromosome(i).a_mux(k, j) <= regs(i(columns+1)+j+1)( input_sel_width(2k+1)-1 downto input_sel_width2k); chromosome(i).b_mux(k, j) <= regs(i(columns+1)+j+1)( input_sel_width2(k+1)-1 downto input_sel_width(2k+1)); end generate; end generate; chromosome(i).out_select <= regs((i+1)(columns+1))( output_sel_width-1 downto 0output_sel_width); chromosome(i).filter_switch <= regs((i+1)(columns+1))( 2output_sel_width-1 downto 1output_sel_width); end generate; fitness_intconn: for i in numregisters-population to numregisters-1 generate regs(i)(fitness_t'range) <= fitness(i-(numregisters-population)); regs(i)(reg_t'high downto fitness_t'high+1) <= (others => '0'); end generate; s_axi_awready <= awready; s_axi_wready <= wready; s_axi_bvalid <= bvalid; s_axi_arready <= arready; s_axi_rdata <= rdata; s_axi_rvalid <= rvalid; reg_wren <= wready and s_axi_wvalid and awready and s_axi_awvalid; reg_rden <= arready and s_axi_arvalid and (not rvalid); process (s_axi_aclk) begin if rising_edge(s_axi_aclk) then if s_axi_aresetn = '0' then awready <= '0'; writeaddr <= (others => '0'); wready <= '0'; bvalid <= '0'; arready <= '0'; readaddr <= (others => '1'); rvalid <= '0'; rdata <= (others => '0'); else if (awready = '0' and s_axi_awvalid = '1' and s_axi_wvalid = '1') then awready <= '1'; else awready <= '0'; end if; if (awready = '0' and s_axi_awvalid = '1' and s_axi_wvalid = '1') then writeaddr <= s_axi_awaddr(reg_bits+word_bits-1 downto word_bits); end if; if (wready = '0' and s_axi_wvalid = '1' and s_axi_awvalid = '1') then wready <= '1'; else wready <= '0'; end if; if (awready = '1' and s_axi_awvalid = '1' and wready = '1' and s_axi_wvalid = '1' and bvalid = '0') then bvalid <= '1'; elsif (s_axi_bready = '1' and bvalid = '1') then bvalid <= '0'; end if; if (arready = '0' and s_axi_arvalid = '1') then arready <= '1'; readaddr <= s_axi_araddr(reg_bits+word_bits-1 downto word_bits); else arready <= '0'; end if; if (arready = '1' and s_axi_arvalid = '1' and rvalid = '0') then rvalid <= '1'; elsif (rvalid = '1' and s_axi_rready = '1') then rvalid <= '0'; end if; if (reg_rden = '1') then rdata <= databus; end if; end if; end if; end process; registers: for i in regs'range generate -- in the control register only the start bit is writable (and is -- resetable by the signal from the cgp core) control_wr: if i = 0 generate process (s_axi_aclk, start_rst) is begin if start_rst = '1' then regs(0)(0) <= '0'; else if rising_edge(s_axi_aclk) then if (reg_wren = '1' and writeaddr = std_logic_vector(to_unsigned(0, reg_bits))) then if s_axi_wstrb(0) = '1' then regs(0)(0) <= s_axi_wdata(0); end if; end if; end if; end if; end process; end generate; -- the chromosome registers are resetable and writable regular -- registers chromosome_wr: if ((i > 0) and (i < (numregisters-population))) generate write_process: process (s_axi_aclk) is begin if rising_edge(s_axi_aclk) then if s_axi_aresetn = '0' then regs(i) <= (others => '0'); else if (reg_wren = '1' and writeaddr = std_logic_vector(to_unsigned(i, reg_bits))) then for j in 0 to w32bytes-1 loop if s_axi_wstrb(j) = '1' then regs(i)((j+1)8-1 downto j8) <= s_axi_wdata((j+1)8-1 downto j*8); end if; end loop; end if; end if; end if; end process; end generate; -- the fitness registers are read-only end generate; databusgen: for i in regs'range generate process (regs, readaddr, s_axi_aresetn) begin if s_axi_aresetn = '0' then databus <= (others => '1'); else if readaddr = std_logic_vector(to_unsigned(i, reg_bits)) then databus <= regs(i); else databus <= (others => 'Z'); end if; end if; end process; end generate; end beh_axi_evol;	gpl-3.0
hiyuh/nvc	test/regress/func11.vhd	5	403	entity func11 is end entity; architecture test of func11 is function foo(x : integer) return integer is begin return x + 1; end function; function foo(x : integer) return real is begin return real(x) + 1.0; end function; begin process is begin assert foo(1) = 2; assert foo(1) = 2.0; wait; end process; end architecture;	gpl-3.0
hiyuh/nvc	test/parse/extended.vhd	4	264	-- Test extended identifiers architecture foo of bar is signal \foo bar\ : integer; signal \a\\b\ : integer; signal \Thing!!! \ : integer; signal \name\ : integer; signal name : integer; begin \foo.bar.baz\ <= \hello\; end architecture;	gpl-3.0
hiyuh/nvc	test/regress/func14.vhd	5	772	entity func14 is end entity; architecture test of func14 is begin one: process is function func(x : integer) return integer is begin return x * 2; end function; variable y : integer; begin y := 2; wait for 1 ns; assert func(y) = 4; y := 4; wait for 1 ns; assert func(y) = 8; wait; end process; two: process is function func(x : integer) return integer is begin return x / 2; end function; variable y : integer; begin y := 2; wait for 1 ns; assert func(y) = 1; y := 4; wait for 1 ns; assert func(y) = 2; wait; end process; end architecture;	gpl-3.0
hiyuh/nvc	test/regress/attr9.vhd	3	454	entity attr9 is end entity; architecture test of attr9 is begin process is type my_small_int is range 1 to 10; begin assert integer'value("1") = 1; assert natural'value(" 12_3") = 123; assert my_small_int'value("5 ") = 5; assert boolean'value("true") = true; assert boolean'value("FALSE") = false; assert character'value("'x' ") = 'x'; wait; end process; end architecture;	gpl-3.0
hiyuh/nvc	test/regress/bitvec.vhd	3	679	entity bitvec is end entity; architecture test of bitvec is function get_bitvec(x, y : integer) return bit_vector is variable r : bit_vector(x to y) := "00"; begin return r; end function; begin process is variable b : bit_vector(3 downto 0); begin b := "1101"; assert not b = "0010"; assert (b and "1010") = "1000"; assert (b or "0110") = "1111"; assert (b xor "0111") = "1010"; assert (b xnor "0111") = "0101"; assert (b nand "1010") = "0111"; assert (b nor "0110") = "0000"; assert get_bitvec(1, 2) = "00"; wait; end process; end architecture;	gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado_HLS/image_contrast_adj/solution1/impl/vhdl/doHistStretch_fdiv_32ns_32ns_32_16.vhd

5

3100

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity doHistStretch_fdiv_32ns_32ns_32_16 is generic ( ID : integer := 2; NUM_STAGE : integer := 16; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of doHistStretch_fdiv_32ns_32ns_32_16 is --------------------- Component --------------------- component doHistStretch_ap_fdiv_14_no_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- doHistStretch_ap_fdiv_14_no_dsp_32_u : component doHistStretch_ap_fdiv_14_no_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;

gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/utt.fr/dohiststretch_v1_0/hdl/vhdl/doHistStretch_fdiv_32ns_32ns_32_16.vhd

5

3100

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2016.1 -- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity doHistStretch_fdiv_32ns_32ns_32_16 is generic ( ID : integer := 2; NUM_STAGE : integer := 16; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of doHistStretch_fdiv_32ns_32ns_32_16 is --------------------- Component --------------------- component doHistStretch_ap_fdiv_14_no_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- doHistStretch_ap_fdiv_14_no_dsp_32_u : component doHistStretch_ap_fdiv_14_no_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;

gpl-3.0

Darkin47/Zynq-TX-UTT

Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_pcc.vhd

3

103944

------------------------------------------------------------------------------- -- axi_datamover_pcc.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_pcc.vhd -- -- Description: -- This file implements the DataMover Predictive Command Calculator (PCC). -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_strb_gen2; ------------------------------------------------------------------------------- entity axi_datamover_pcc is generic ( C_IS_MM2S : Integer range 0 to 1 := 0; -- This parameter tells the PCC module if it is a MM2S -- instance or a S2MM instance. -- 0 = S2MM Instance -- 1 = MM2S Instance C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE Aligment output ports C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the LS address bus used for -- Muxing/Demuxing data to/from a wider AXI4 data bus C_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Sets the width of the AXi Address Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Stream Data width that -- is being supported by the PCC C_MAX_BURST_LEN : Integer range 2 to 256 := 16; -- Indicates the max allowed burst length to use for -- AXI4 transfer calculations C_CMD_WIDTH : Integer := 68; -- Sets the width of the input command port C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the input command C_BTT_USED : Integer range 8 to 23 := 16; -- Sets the width of the used portion of the BTT field -- of the input command C_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates if the Indeterminate BTT mode is enabled C_NATIVE_XFER_WIDTH : Integer range 8 to 1024 := 32; -- Indicates the Native transfer width to use for all -- transfer calculations. This will either be the DataMover -- input Stream width or the AXI4 MMap data width depending -- on DataMover parameterization. C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 -- Indicates the width of the starting address offset -- bus passed to Store and Forward functions ); port ( -- Clock and Reset input ---------------------------------------- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------------- -- Master Command FIFO/Register Interface -------------------------------------------- -- cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- -- The next command value available from the Command FIFO/Register -- -- cache2mstr_command : in std_logic_vector(7 downto 0); -- -- The next command value available from the Command FIFO/Register -- cmd2mstr_cmd_valid : in std_logic; -- -- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry -- -- mst2cmd_cmd_ready : out std_logic; -- -- Handshake bit indicating the Command Calculator is ready to accept -- -- another command -- -------------------------------------------------------------------------------------- -- Address Channel Controller Interface ----------------------------------- -- mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); -- -- The next command address to put on the AXI MMap ADDR -- -- mstr2addr_len : out std_logic_vector(7 downto 0); -- -- The next command length to put on the AXI MMap LEN -- -- mstr2addr_size : out std_logic_vector(2 downto 0); -- -- The next command size to put on the AXI MMap SIZE -- -- mstr2addr_burst : out std_logic_vector(1 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- -- mstr2addr_cache : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_user : out std_logic_vector(3 downto 0); -- -- The next command burst type to put on the AXI MMap BURST -- mstr2addr_cmd_cmplt : out std_logic; -- -- The indication to the Address Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2addr_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calcualtion error -- -- mstr2addr_cmd_valid : out std_logic; -- -- The next command valid indication to the Address Channel -- -- Controller for the AXI MMap -- -- addr2mstr_cmd_ready : In std_logic; -- -- Indication from the Address Channel Controller that the -- -- command is being accepted -- --------------------------------------------------------------------------- -- Data Channel Controller Interface ------------------------------------------------ -- mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap data -- -- width). -- -- mstr2data_len : out std_logic_vector(7 downto 0); -- -- The LEN value output to the Address Channel -- -- mstr2data_strt_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The starting strobe value to use for the data transfer -- -- mstr2data_last_strb : out std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0); -- -- The endiing (LAST) strobe value to use for the data transfer -- -- mstr2data_drr : out std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2data_eof : out std_logic; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2data_sequential : Out std_logic; -- -- The next sequential tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2data_calc_error : out std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2data_cmd_cmplt : out std_logic; -- -- The indication to the Data Channel that the current -- -- sub-command output is the last one compiled from the -- -- parent command pulled from the Command FIFO -- -- mstr2data_cmd_valid : out std_logic; -- -- The next command valid indication to the Data Channel -- -- Controller for the AXI MMap -- -- data2mstr_cmd_ready : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- command is being accepted on the AXI Address -- -- Channel -- -- mstr2data_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the MM2S DRE -- -- mstr2data_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the MM2S DRE -- ------------------------------------------------------------------------------------- -- Output flag indicating that a calculation error has occured ---------------------- -- calc_error : Out std_logic; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- ------------------------------------------------------------------------------------- -- Special DRE Controller Interface -------------------------------------------- -- dre2mstr_cmd_ready : In std_logic ; -- -- Indication from the S2MM DRE Controller that it can -- -- accept another command. -- -- mstr2dre_cmd_valid : out std_logic ; -- -- The next command valid indication to the S2MM DRE -- -- Controller. -- -- mstr2dre_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The source (S2MM Stream) alignment for the S2MM DRE -- -- mstr2dre_dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- -- The destinstion (S2MM MMap) alignment for the S2MM DRE -- -- mstr2dre_btt : out std_logic_vector(C_BTT_USED-1 downto 0) ; -- -- The BTT value output to the S2MM DRE. This is needed for -- -- Scatter operations. -- -- mstr2dre_drr : out std_logic ; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : out std_logic ; -- -- The endiing tranfer of a sequence of parent transfer commands -- -- mstr2dre_cmd_cmplt : Out std_logic ; -- -- The last child tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2dre_calc_error : out std_logic ; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- ------------------------------------------------------------------------------------- -- Store and Forward Support Start Offset --------------------------------------------- -- mstr2dre_strt_offset : out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0) -- -- Relays the starting address offset for a transfer to the Store and Forward -- -- functions incorporating upsizer/downsizer logic -- --------------------------------------------------------------------------------------- ); end entity axi_datamover_pcc; architecture implementation of axi_datamover_pcc is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declarations ------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_dbeat_residue_width -- -- Function Description: -- Calculates the number of Least significant bits of the BTT field -- that are unused for the LEN calculation -- ------------------------------------------------------------------- function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream begin case bytes_per_beat is when 1 => temp_dbeat_residue_width := 0; when 2 => temp_dbeat_residue_width := 1; when 4 => temp_dbeat_residue_width := 2; when 8 => temp_dbeat_residue_width := 3; when 16 => temp_dbeat_residue_width := 4; when 32 => temp_dbeat_residue_width := 5; when 64 => temp_dbeat_residue_width := 6; when others => -- 128-byte transfers temp_dbeat_residue_width := 7; end case; Return (temp_dbeat_residue_width); end function funct_get_dbeat_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_burstcnt_offset -- -- Function Description: -- Calculates the bit offset from the residue bits needed to detirmine -- the load value for the burst counter. -- ------------------------------------------------------------------- function funct_get_burst_residue_width (max_burst_len : integer) return integer is Variable temp_burst_residue_width : Integer := 0; begin case max_burst_len is when 256 => temp_burst_residue_width := 8; when 128 => temp_burst_residue_width := 7; when 64 => temp_burst_residue_width := 6; when 32 => temp_burst_residue_width := 5; when 16 => temp_burst_residue_width := 4; when 8 => temp_burst_residue_width := 3; when 4 => temp_burst_residue_width := 2; when others => -- assume 2 dbeats temp_burst_residue_width := 1; end case; Return (temp_burst_residue_width); end function funct_get_burst_residue_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_axi_size -- -- Function Description: -- Calculates the AXI SIZE Qualifier based on the data width. -- ------------------------------------------------------------------- function func_get_axi_size (native_dwidth : integer) return std_logic_vector is Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000"; Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001"; Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010"; Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011"; Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100"; Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101"; Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110"; Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111"; Variable temp_size : std_logic_vector(2 downto 0) := (others => '0'); begin case native_dwidth is when 8 => temp_size := AXI_SIZE_1BYTE; when 16 => temp_size := AXI_SIZE_2BYTE; when 32 => temp_size := AXI_SIZE_4BYTE; when 64 => temp_size := AXI_SIZE_8BYTE; when 128 => temp_size := AXI_SIZE_16BYTE; when 256 => temp_size := AXI_SIZE_32BYTE; when 512 => temp_size := AXI_SIZE_64BYTE; when others => -- 1024 bit dwidth temp_size := AXI_SIZE_128BYTE; end case; Return (temp_size); end function func_get_axi_size; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_ls_index -- -- Function Description: -- Calculates the Ls index of the Store and Forward -- starting offset bus based on the User Stream Width. -- ------------------------------------------------------------------- function funct_get_sf_offset_ls_index (stream_width : integer) return integer is Variable lvar_temp_ls_index : Integer := 0; begin case stream_width is when 8 => lvar_temp_ls_index := 0; when 16 => lvar_temp_ls_index := 1; when 32 => lvar_temp_ls_index := 2; when 64 => lvar_temp_ls_index := 3; when 128 => lvar_temp_ls_index := 4; when 256 => lvar_temp_ls_index := 5; when 512 => lvar_temp_ls_index := 6; when others => -- 1024 lvar_temp_ls_index := 7; end case; Return (lvar_temp_ls_index); end function funct_get_sf_offset_ls_index; -- Constant Declarations ---------------------------------------- Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address) Constant CMD_BTT_WIDTH : integer := C_BTT_USED; Constant CMD_BTT_LS_INDEX : integer := 0; Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1; Constant CMD_TYPE_INDEX : integer := 23; Constant CMD_DRR_INDEX : integer := BASE_CMD_WIDTH-1; Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2; Constant CMD_DSA_WIDTH : integer := 6; Constant CMD_DSA_LS_INDEX : integer := CMD_TYPE_INDEX+1; Constant CMD_DSA_MS_INDEX : integer := (CMD_DSA_LS_INDEX+CMD_DSA_WIDTH)-1; Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH; Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1; Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH; Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH; Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1; ---------------------------------------------------------------------------------------- -- Command calculation constants Constant SIZE_TO_USE : std_logic_vector(2 downto 0) := func_get_axi_size(C_NATIVE_XFER_WIDTH); Constant BYTES_PER_DBEAT : integer := C_NATIVE_XFER_WIDTH/8; Constant DBEATS_PER_BURST : integer := C_MAX_BURST_LEN; Constant BYTES_PER_MAX_BURST : integer := DBEATS_PER_BURST*BYTES_PER_DBEAT; Constant LEN_WIDTH : integer := 8; -- 8 bits fixed Constant MAX_LEN_VALUE : integer := DBEATS_PER_BURST-1; Constant XFER_LEN_ZERO : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_WIDTH : integer := funct_get_dbeat_residue_width(BYTES_PER_DBEAT); Constant BURST_RESIDUE_WIDTH : integer := funct_get_burst_residue_width(C_MAX_BURST_LEN); Constant BURST_RESIDUE_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH; Constant BTT_RESIDUE_WIDTH : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); Constant BTT_RESIDUE_1 : unsigned := TO_UNSIGNED( 1, BTT_RESIDUE_WIDTH); Constant BTT_RESIDUE_0 : unsigned := TO_UNSIGNED( 0, BTT_RESIDUE_WIDTH); Constant BURST_CNT_LS_INDEX : integer := DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH; Constant BURST_CNTR_WIDTH : integer := CMD_BTT_WIDTH - (DBEAT_RESIDUE_WIDTH+BURST_RESIDUE_WIDTH); Constant BRST_CNT_1 : unsigned := TO_UNSIGNED( 1, BURST_CNTR_WIDTH); Constant BRST_CNT_0 : unsigned := TO_UNSIGNED( 0, BURST_CNTR_WIDTH); Constant BRST_RESIDUE_0 : std_logic_vector(BURST_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant DBEAT_RESIDUE_0 : std_logic_vector(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_CNTR_WIDTH : integer := 16; -- Addres Counter slice Constant ADDR_MS_SLICE_WIDTH : integer := C_ADDR_WIDTH-ADDR_CNTR_WIDTH; Constant ADDR_CNTR_MAX_VALUE : unsigned := TO_UNSIGNED((2**ADDR_CNTR_WIDTH)-1, ADDR_CNTR_WIDTH); Constant ADDR_CNTR_ONE : unsigned := TO_UNSIGNED(1, ADDR_CNTR_WIDTH); Constant MBAA_ADDR_SLICE_WIDTH : integer := BTT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_SLICE_WIDTH : integer := DBEAT_RESIDUE_WIDTH; Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); Constant STRBGEN_ADDR_SLICE_1 : unsigned := TO_UNSIGNED( 1, STRBGEN_ADDR_SLICE_WIDTH); Constant SF_OFFSET_LS_INDEX : integer := funct_get_sf_offset_ls_index(C_STREAM_DWIDTH); Constant SF_OFFSET_MS_INDEX : integer := (SF_OFFSET_LS_INDEX + C_STRT_SF_OFFSET_WIDTH)-1; -- Type Declarations -------------------------------------------- type PCC_SM_STATE_TYPE is ( INIT, WAIT_FOR_CMD, CALC_1, CALC_2, CALC_3, WAIT_ON_XFER_PUSH, CHK_IF_DONE, ERROR_TRAP ); -- Signal Declarations -------------------------------------------- Signal sig_pcc_sm_state : PCC_SM_STATE_TYPE := INIT; Signal sig_pcc_sm_state_ns : PCC_SM_STATE_TYPE := INIT; signal sig_sm_halt_ns : std_logic := '0'; signal sig_sm_halt_reg : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns : std_logic := '0'; signal sig_sm_ld_xfer_reg_ns_tmp : std_logic := '0'; signal sig_sm_pop_input_reg_ns : std_logic := '0'; signal sig_sm_pop_input_reg : std_logic := '0'; signal sig_sm_ld_calc1_reg_ns : std_logic := '0'; signal sig_sm_ld_calc1_reg : std_logic := '0'; signal sig_sm_ld_calc2_reg_ns : std_logic := '0'; signal sig_sm_ld_calc2_reg : std_logic := '0'; signal sig_sm_ld_calc3_reg_ns : std_logic := '0'; signal sig_sm_ld_calc3_reg : std_logic := '0'; signal sig_parent_done : std_logic := '0'; signal sig_ld_xfer_reg : std_logic := '0'; signal sig_ld_xfer_reg_tmp : std_logic := '0'; signal sig_btt_raw : std_logic := '0'; signal sig_btt_is_zero : std_logic := '0'; signal sig_btt_is_zero_reg : std_logic := '0'; -- unused signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); -- unused signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0'); -- unused signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0'); -- unused signal sig_next_strt_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); -- unused signal sig_next_end_strb : std_logic_vector((C_NATIVE_XFER_WIDTH/8)-1 downto 0) := (others => '0'); ---------------------------------------------------------------------------------------- -- Burst Buster signals signal sig_burst_cnt_slice_im0 : unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_last_xfer_valid_im1 : std_logic := '0'; signal sig_brst_cnt_eq_zero_im0 : std_logic := '0'; signal sig_brst_cnt_eq_zero_ireg1 : std_logic := '0'; signal sig_brst_cnt_eq_one_im0 : std_logic := '0'; signal sig_brst_cnt_eq_one_ireg1 : std_logic := '0'; signal sig_brst_residue_eq_zero : std_logic := '0'; signal sig_brst_residue_eq_zero_reg : std_logic := '0'; signal sig_no_btt_residue_im0 : std_logic := '0'; signal sig_no_btt_residue_ireg1 : std_logic := '0'; signal sig_btt_residue_slice_im0 : Unsigned(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); -- Input command register signal sig_push_input_reg : std_logic := '0'; signal sig_pop_input_reg : std_logic := '0'; signal sig_input_burst_type_reg : std_logic := '0'; signal sig_input_cache_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_user_type_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_input_btt_residue_minus1_reg : std_logic_vector(BTT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_input_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_input_drr_reg : std_logic := '0'; signal sig_input_eof_reg : std_logic := '0'; signal sig_input_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_input_reg_empty : std_logic := '0'; signal sig_input_reg_full : std_logic := '0'; -- Output qualifier Register -- signal sig_ld_output : std_logic := '0'; signal sig_push_xfer_reg : std_logic := '0'; signal sig_pop_xfer_reg : std_logic := '0'; signal sig_xfer_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_type_reg : std_logic := '0'; signal sig_xfer_cache_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_user_reg : std_logic_vector (3 downto 0) := "0000"; signal sig_xfer_len_reg : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dsa_reg : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_drr_reg : std_logic := '0'; signal sig_xfer_eof_reg : std_logic := '0'; signal sig_xfer_strt_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_reg : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_is_seq_reg : std_logic := '0'; signal sig_xfer_cmd_cmplt_reg : std_logic := '0'; signal sig_xfer_calc_err_reg : std_logic := '0'; signal sig_xfer_reg_empty : std_logic := '0'; signal sig_xfer_reg_full : std_logic := '0'; -- Address Counter signal sig_ld_addr_cntr : std_logic := '0'; signal sig_incr_addr_cntr : std_logic := '0'; signal sig_addr_cntr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_byte_change_minus1_im2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); -- misc signal sig_xfer_len_im2 : std_logic_vector(LEN_WIDTH-1 downto 0); signal sig_xfer_strt_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_im2 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb2use_im3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_address_im0 : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_cmd_addr_slice : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_type_slice : std_logic := '0'; signal sig_cmd_cache_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_user_slice : std_logic_vector (3 downto 0) := "0000"; signal sig_cmd_tag_slice : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_dsa_slice : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_drr_slice : std_logic := '0'; signal sig_cmd_eof_slice : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_calc_error_pushed : std_logic := '0'; -- PCC2 stuff signal sig_finish_addr_offset_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_im2 : std_logic := '0'; signal sig_first_xfer_im0 : std_logic := '0'; signal sig_bytes_to_mbaa_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_bytes_to_mbaa_ireg1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover : std_logic := '0'; signal sig_predict_addr_lsh_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im1 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_kh : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_lsh_im0_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_cntr_im0_msh : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_addr_im0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_im1 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_ld_btt_cntr : std_logic := '0'; signal sig_decr_btt_cntr : std_logic := '0'; signal sig_btt_cntr_im0 : unsigned(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2data_valid : std_logic := '0'; signal sig_clr_cmd2data_valid : std_logic := '0'; signal sig_cmd2addr_valid : std_logic := '0'; signal sig_clr_cmd2addr_valid : std_logic := '0'; signal sig_btt_lt_b2mbaa_im0 : std_logic := '0'; signal sig_btt_lt_b2mbaa_ireg1 : std_logic := '0'; signal sig_btt_eq_b2mbaa_im0 : std_logic := '0'; signal sig_btt_eq_b2mbaa_ireg1 : std_logic := '0'; signal sig_addr_incr_ge_bpdb_im1 : std_logic := '0'; -- Unaligned start address support signal sig_adjusted_addr_incr_im1 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_adjusted_addr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_start_addr_offset_slice_im0 : Unsigned(DBEAT_RESIDUE_WIDTH-1 downto 0) := (others => '0'); signal sig_mbaa_addr_cntr_slice_im0 : Unsigned(MBAA_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_aligned_im0 : std_logic := '0'; signal sig_addr_aligned_ireg1 : std_logic := '0'; -- S2MM DRE Support signal sig_cmd2dre_valid : std_logic := '0'; signal sig_clr_cmd2dre_valid : std_logic := '0'; signal sig_input_xfer_btt_im0 : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_dre_eof_reg : std_logic := '0'; -- Long Timing path breakup intermediate registers signal sig_strbgen_addr_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_strbgen_bytes_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); signal sig_finish_addr_offset_ireg2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_addr_offset_im2 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); signal sig_xfer_strt_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_end_strb_ireg3 : std_logic_vector(BYTES_PER_DBEAT-1 downto 0) := (others => '0'); signal sig_xfer_len_eq_0_ireg3 : std_logic := '0'; signal sig_addr_cntr_incr_ireg2 : Unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im3_slv : std_logic_vector(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_im2 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_predict_addr_lsh_ireg3 : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsh_rollover_im3 : std_logic := '0'; signal sig_mmap_reset_reg : std_logic := '0'; ---------------------------------------------------------- begin --(architecture implementation) -- Assign calculation error output calc_error <= sig_calc_error_reg; -- Assign the ready output to the Command FIFO mst2cmd_cmd_ready <= not(sig_sm_halt_reg) and sig_input_reg_empty and not(sig_calc_error_pushed); -- Assign the Address Channel Controller Qualifiers mstr2addr_tag <= sig_xfer_tag_reg ; mstr2addr_addr <= sig_xfer_addr_reg; mstr2addr_len <= sig_xfer_len_reg ; mstr2addr_size <= sig_xfer_size ; mstr2addr_burst <= '0' & sig_xfer_type_reg; -- only fixed or increment supported mstr2addr_cache <= sig_xfer_cache_reg; -- only fixed or increment supported mstr2addr_user <= sig_xfer_user_reg; -- only fixed or increment supported mstr2addr_cmd_valid <= sig_cmd2addr_valid; mstr2addr_calc_error <= sig_xfer_calc_err_reg; mstr2addr_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Assign the Data Channel Controller Qualifiers mstr2data_tag <= sig_xfer_tag_reg ; mstr2data_saddr_lsb <= sig_xfer_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0); mstr2data_len <= sig_xfer_len_reg ; mstr2data_strt_strb <= sig_xfer_strt_strb_reg; mstr2data_last_strb <= sig_xfer_end_strb_reg ; mstr2data_drr <= sig_xfer_drr_reg ; mstr2data_eof <= sig_xfer_eof_reg ; mstr2data_sequential <= sig_xfer_is_seq_reg ; mstr2data_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; mstr2data_cmd_valid <= sig_cmd2data_valid ; mstr2data_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by MM2S DRE mstr2data_calc_error <= sig_xfer_calc_err_reg ; -- Assign the DRE Controller Qualifiers mstr2dre_cmd_valid <= sig_cmd2dre_valid ; -- Used by DRE mstr2dre_tag <= sig_xfer_tag_reg ; -- Used by DRE mstr2dre_btt <= sig_xfer_btt_reg ; -- Used by DRE mstr2dre_drr <= sig_xfer_drr_reg ; -- Used by DRE mstr2dre_eof <= sig_xfer_dre_eof_reg ; -- Used by DRE mstr2dre_cmd_cmplt <= sig_xfer_cmd_cmplt_reg; -- Used by DRE mstr2dre_calc_error <= sig_xfer_calc_err_reg ; -- Used by DRE ------------------------------------------------------------ -- If Generate -- -- Label: DO_MM2S_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the MM2S use case. -- ------------------------------------------------------------ DO_MM2S_CASE : if (C_IS_MM2S = 1) generate begin mstr2dre_dre_src_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE end generate DO_MM2S_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: DO_S2MM_CASE -- -- If Generate Description: -- Assigns the auxillary DRE Control Source and Destination -- ports for the S2MM use case. -- ------------------------------------------------------------ DO_S2MM_CASE : if (C_IS_MM2S = 0) generate begin mstr2dre_dre_src_align <= sig_xfer_dsa_reg(C_DRE_ALIGN_WIDTH-1 downto 0) ; -- Used by DRE mstr2dre_dre_dest_align <= sig_xfer_addr_reg(C_DRE_ALIGN_WIDTH-1 downto 0); -- Used by DRE end generate DO_S2MM_CASE; -- Store and Forward Support Start Offset (used by Packer/Unpacker logic) mstr2dre_strt_offset <= sig_xfer_addr_reg(SF_OFFSET_MS_INDEX downto SF_OFFSET_LS_INDEX); -- Start internal logic. -- sig_cmd_type_slice <= '1'; -- always incrementing (per Interface_X guidelines) sig_cmd_user_slice <= cache2mstr_command(7 downto 4); sig_cmd_cache_slice <= cache2mstr_command(3 downto 0); sig_cmd_type_slice <= cmd2mstr_command(CMD_TYPE_INDEX); sig_cmd_addr_slice <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX); sig_cmd_tag_slice <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX); sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX); sig_cmd_dsa_slice <= cmd2mstr_command(CMD_DSA_MS_INDEX downto CMD_DSA_LS_INDEX); sig_cmd_drr_slice <= cmd2mstr_command(CMD_DRR_INDEX); sig_cmd_eof_slice <= cmd2mstr_command(CMD_EOF_INDEX); -- Check for a zero length BTT (error condition) sig_btt_is_zero <= '1' when (sig_cmd_btt_slice = BTT_ZEROS) Else '0'; sig_xfer_size <= SIZE_TO_USE; ----------------------------------------------------------------- -- Reset fanout control ----------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RESET_REG -- -- Process Description: -- Registers the input reset to reduce fanout. This module -- has a high number of register bits to reset. -- ------------------------------------------------------------- IMP_RESET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_reset_reg <= mmap_reset; end if; end process IMP_RESET_REG; ----------------------------------------------------------------- -- Input xfer register design sig_push_input_reg <= not(sig_sm_halt_reg) and cmd2mstr_cmd_valid and sig_input_reg_empty and not(sig_calc_error_reg); sig_pop_input_reg <= sig_sm_pop_input_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_INPUT_QUAL -- -- Process Description: -- Implements the input command qualifier holding register -- ------------------------------------------------------------- REG_INPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_input_reg = '1' or sig_calc_error_pushed = '1') then sig_input_cache_type_reg <= (others => '0'); sig_input_user_type_reg <= (others => '0'); sig_input_burst_type_reg <= '0'; sig_input_tag_reg <= (others => '0'); sig_input_dsa_reg <= (others => '0'); sig_input_drr_reg <= '0'; sig_input_eof_reg <= '0'; sig_input_reg_empty <= '1'; sig_input_reg_full <= '0'; elsif (sig_push_input_reg = '1') then sig_input_cache_type_reg <= sig_cmd_cache_slice; sig_input_user_type_reg <= sig_cmd_user_slice; sig_input_burst_type_reg <= sig_cmd_type_slice; sig_input_tag_reg <= sig_cmd_tag_slice; sig_input_dsa_reg <= sig_cmd_dsa_slice; sig_input_drr_reg <= sig_cmd_drr_slice; sig_input_eof_reg <= sig_cmd_eof_slice; sig_input_reg_empty <= '0'; sig_input_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_INPUT_QUAL; ---------------------------------------------------------------------- -- Calculation Error Logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_FLOP -- -- Process Description: -- Implements the flop for the Calc Error flag, Once set, -- the flag cannot be cleared until a reset is issued. -- ------------------------------------------------------------- IMP_CALC_ERROR_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_reg <= '0'; elsif (sig_push_input_reg = '1' and sig_calc_error_reg = '0') then sig_calc_error_reg <= sig_btt_is_zero; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CALC_ERROR_PUSHED -- -- Process Description: -- Implements the flop for generating a flag indicating the -- calculation error flag has been pushed to the addr and data -- controllers. -- ------------------------------------------------------------- IMP_CALC_ERROR_PUSHED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_calc_error_pushed <= '0'; elsif (sig_push_xfer_reg = '1' and sig_calc_error_pushed = '0') then sig_calc_error_pushed <= sig_calc_error_reg; else Null; -- hold the current state end if; end if; end process IMP_CALC_ERROR_PUSHED; --------------------------------------------------------------------- -- Strobe Generator Logic sig_xfer_strt_strb2use_im3 <= sig_xfer_strt_strb_ireg3 When (sig_first_xfer_im0 = '1') Else (others => '1'); sig_xfer_end_strb2use_im3 <= sig_xfer_strt_strb2use_im3 When (sig_xfer_len_eq_0_ireg3 = '1' and sig_first_xfer_im0 = '1') else sig_xfer_end_strb_ireg3 When (sig_last_xfer_valid_im1 = '1') Else (others => '1'); ---------------------------------------------------------- -- Intermediate registers for STBGEN Fmax path ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_REGS -- -- Process Description: -- Intermediate registers for Strobegen inputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_strbgen_addr_ireg2 <= (others => '0'); sig_strbgen_bytes_ireg2 <= (others => '0'); sig_finish_addr_offset_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_strbgen_addr_ireg2 <= sig_strbgen_addr_im0 ; sig_strbgen_bytes_ireg2 <= sig_strbgen_bytes_im1 ; sig_finish_addr_offset_ireg2 <= sig_finish_addr_offset_im1; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_REGS; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_STBGEN_OUT_REGS -- -- Process Description: -- Intermediate registers for Strobegen outputs to break -- long timing paths. -- ------------------------------------------------------------- IMP_IM_STBGEN_OUT_REGS : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_xfer_strt_strb_ireg3 <= (others => '0'); sig_xfer_end_strb_ireg3 <= (others => '0'); sig_xfer_len_eq_0_ireg3 <= '0'; elsif (sig_sm_ld_calc3_reg = '1') then sig_xfer_strt_strb_ireg3 <= sig_xfer_strt_strb_im2; sig_xfer_end_strb_ireg3 <= sig_xfer_end_strb_im2 ; sig_xfer_len_eq_0_ireg3 <= sig_xfer_len_eq_0_im2 ; else null; -- hold state end if; end if; end process IMP_IM_STBGEN_OUT_REGS; ------------------------------------------------------------ -- Instance: I_STRT_STRB_GEN -- -- Description: -- Strobe generator instance. Generates strobe bits for -- a designated starting byte lane and the number of bytes -- to be transfered (for that data beat). -- ------------------------------------------------------------ I_STRT_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 0 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1 ) port map ( start_addr_offset => sig_strbgen_addr_ireg2 , end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0 num_valid_bytes => sig_strbgen_bytes_ireg2 , strb_out => sig_xfer_strt_strb_im2 ); -- The ending address offset is 1 less than the calculated -- starting address for the next sequential transfer. sig_last_addr_offset_im2 <= STD_LOGIC_VECTOR(UNSIGNED(sig_finish_addr_offset_ireg2) - STRBGEN_ADDR_SLICE_1); ------------------------------------------------------------ -- Instance: I_END_STRB_GEN -- -- Description: -- End Strobe generator instance. Generates asserted strobe -- bits from byte offset 0 to the ending byte offset. -- ------------------------------------------------------------ I_END_STRB_GEN : entity axi_datamover_v5_1_10.axi_datamover_strb_gen2 generic map ( C_OP_MODE => 1 , -- 0 = Offset/Length mode C_STRB_WIDTH => BYTES_PER_DBEAT , C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ) port map ( start_addr_offset => STRBGEN_ADDR_0 , end_addr_offset => sig_last_addr_offset_im2 , num_valid_bytes => STRBGEN_ADDR_0 , -- not used in op mode 1 strb_out => sig_xfer_end_strb_im2 ); ----------------------------------------------------------------- -- Output xfer register design sig_push_xfer_reg <= (sig_ld_xfer_reg and sig_xfer_reg_empty); -- Data taking xfer after Addr and DRE sig_pop_xfer_reg <= (sig_clr_cmd2data_valid and not(sig_cmd2addr_valid) and not(sig_cmd2dre_valid)) or -- Addr taking xfer after Data and DRE (sig_clr_cmd2addr_valid and not(sig_cmd2data_valid) and not(sig_cmd2dre_valid)) or -- DRE taking xfer after Data and ADDR (sig_clr_cmd2dre_valid and not(sig_cmd2data_valid) and not(sig_cmd2addr_valid)) or -- data and Addr taking xfer after DRE (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and not(sig_cmd2dre_valid)) or -- Addr and DRE taking xfer after Data (sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid and not(sig_cmd2data_valid)) or -- Data and DRE taking xfer after Addr (sig_clr_cmd2data_valid and sig_clr_cmd2dre_valid and not(sig_cmd2addr_valid)) or -- Addr, Data, and DRE all taking xfer (sig_clr_cmd2data_valid and sig_clr_cmd2addr_valid and sig_clr_cmd2dre_valid); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_OUTPUT_QUAL -- -- Process Description: -- Implements the output xfer qualifier holding register -- ------------------------------------------------------------- REG_OUTPUT_QUAL : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or (sig_pop_xfer_reg = '1' and sig_push_xfer_reg = '0')) then -- sig_xfer_cache_reg <= (others => '0'); -- sig_xfer_user_reg <= (others => '0'); -- sig_xfer_addr_reg <= (others => '0'); -- sig_xfer_type_reg <= '0'; -- sig_xfer_len_reg <= (others => '0'); -- sig_xfer_tag_reg <= (others => '0'); -- sig_xfer_dsa_reg <= (others => '0'); -- sig_xfer_drr_reg <= '0'; -- sig_xfer_eof_reg <= '0'; -- sig_xfer_strt_strb_reg <= (others => '0'); -- sig_xfer_end_strb_reg <= (others => '0'); -- sig_xfer_is_seq_reg <= '0'; -- sig_xfer_cmd_cmplt_reg <= '0'; -- sig_xfer_calc_err_reg <= '0'; -- sig_xfer_btt_reg <= (others => '0'); -- sig_xfer_dre_eof_reg <= '0'; sig_xfer_reg_empty <= '1'; sig_xfer_reg_full <= '0'; elsif (sig_push_xfer_reg = '1') then -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else -- sig_xfer_addr_reg <= sig_xfer_address_im0 ; -- end if; -- sig_xfer_type_reg <= sig_input_burst_type_reg ; -- sig_xfer_cache_reg <= sig_input_cache_type_reg ; -- sig_xfer_user_reg <= sig_input_user_type_reg ; -- sig_xfer_len_reg <= sig_xfer_len_im2 ; -- sig_xfer_tag_reg <= sig_input_tag_reg ; -- sig_xfer_dsa_reg <= sig_input_dsa_reg ; -- sig_xfer_drr_reg <= sig_input_drr_reg and -- sig_first_xfer_im0 ; -- sig_xfer_eof_reg <= sig_input_eof_reg and -- sig_last_xfer_valid_im1 ; -- sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; -- sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; -- sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; -- sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or -- sig_calc_error_reg ; -- sig_xfer_calc_err_reg <= sig_calc_error_reg ; -- sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; -- sig_xfer_dre_eof_reg <= sig_input_eof_reg ; sig_xfer_reg_empty <= '0'; sig_xfer_reg_full <= '1'; else null; -- Hold current State end if; end if; end process REG_OUTPUT_QUAL; -- if (sig_input_burst_type_reg = '0') then -- sig_xfer_addr_reg <= sig_addr_cntr_lsh_kh; -- else sig_xfer_addr_reg <= sig_xfer_address_im0 when (sig_input_burst_type_reg = '1') else sig_addr_cntr_lsh_kh ; -- end if; sig_xfer_type_reg <= sig_input_burst_type_reg ; sig_xfer_cache_reg <= sig_input_cache_type_reg ; sig_xfer_user_reg <= sig_input_user_type_reg ; sig_xfer_len_reg <= sig_xfer_len_im2 ; sig_xfer_tag_reg <= sig_input_tag_reg ; sig_xfer_dsa_reg <= sig_input_dsa_reg ; sig_xfer_drr_reg <= sig_input_drr_reg and sig_first_xfer_im0 ; sig_xfer_eof_reg <= sig_input_eof_reg and sig_last_xfer_valid_im1 ; sig_xfer_strt_strb_reg <= sig_xfer_strt_strb2use_im3 ; sig_xfer_end_strb_reg <= sig_xfer_end_strb2use_im3 ; sig_xfer_is_seq_reg <= not(sig_last_xfer_valid_im1) ; sig_xfer_cmd_cmplt_reg <= sig_last_xfer_valid_im1 or sig_calc_error_reg ; sig_xfer_calc_err_reg <= sig_calc_error_reg ; sig_xfer_btt_reg <= sig_input_xfer_btt_im0 ; sig_xfer_dre_eof_reg <= sig_input_eof_reg ; -------------------------------------------------------------- -- BTT Counter Logic sig_ld_btt_cntr <= sig_ld_addr_cntr; -- sig_decr_btt_cntr <= sig_incr_addr_cntr; -- above signal is using the incr_addr_cntr signal and hence cannot be -- used if burst type is Fixed sig_decr_btt_cntr <= sig_incr_addr_cntr; --sig_push_xfer_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_CNTR -- -- Process Description: -- Bytes to transfer counter implementation. -- ------------------------------------------------------------- IMP_BTT_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_btt_cntr_im0 <= (others => '0'); elsif (sig_ld_btt_cntr = '1') then sig_btt_cntr_im0 <= UNSIGNED(sig_cmd_btt_slice); Elsif (sig_decr_btt_cntr = '1') Then sig_btt_cntr_im0 <= sig_btt_cntr_im0-RESIZE(sig_addr_cntr_incr_ireg2, CMD_BTT_WIDTH); else null; -- hold current state end if; end if; end process IMP_BTT_CNTR; -- Convert to logic vector for the S2MM DRE use -- The DRE will only use this value prior to the first -- decrement of the BTT Counter. Using this saves a separate -- BTT register. sig_input_xfer_btt_im0 <= STD_LOGIC_VECTOR(sig_btt_cntr_im0); -- Rip the Burst Count slice from BTT counter value sig_burst_cnt_slice_im0 <= sig_btt_cntr_im0(CMD_BTT_WIDTH-1 downto BURST_CNT_LS_INDEX); sig_brst_cnt_eq_zero_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_0) Else '0'; sig_brst_cnt_eq_one_im0 <= '1' When (sig_burst_cnt_slice_im0 = BRST_CNT_1) Else '0'; -- Rip the BTT residue field from the BTT counter value sig_btt_residue_slice_im0 <= sig_btt_cntr_im0(BTT_RESIDUE_WIDTH-1 downto 0); -- Check for transfer length residue of zero prior to subtracting 1 sig_no_btt_residue_im0 <= '1' when (sig_btt_residue_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Unaligned address compensation -- Add the number of starting address offset byte positions to the -- final byte change value needed to calculate the AXI LEN field sig_start_addr_offset_slice_im0 <= sig_addr_cntr_lsh_im0(DBEAT_RESIDUE_WIDTH-1 downto 0); sig_adjusted_addr_incr_im1 <= sig_addr_cntr_incr_im1 + RESIZE(sig_start_addr_offset_slice_im0, ADDR_CNTR_WIDTH); -- adjust the address increment down by 1 byte to compensate -- for the LEN requirement of being N-1 data beats sig_byte_change_minus1_im2 <= sig_adjusted_addr_incr_ireg2-ADDR_CNTR_ONE; -- Rip the new transfer length value sig_xfer_len_im2 <= STD_LOGIC_VECTOR( RESIZE( sig_byte_change_minus1_im2(BTT_RESIDUE_WIDTH-1 downto DBEAT_RESIDUE_WIDTH), LEN_WIDTH) ); -- Check to see if the new xfer length is zero (1 data beat) sig_xfer_len_eq_0_im2 <= '1' when (sig_xfer_len_im2 = XFER_LEN_ZERO) Else '0'; -- Check for Last transfer condition --sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_im0 and sig_last_xfer_valid_im1 <= (sig_brst_cnt_eq_one_ireg1 and --sig_no_btt_residue_im0 and sig_no_btt_residue_ireg1 and -- sig_addr_aligned_im0) or -- always the last databeat case sig_addr_aligned_ireg1) or -- always the last databeat case -- ((sig_btt_lt_b2mbaa_im0 or sig_btt_eq_b2mbaa_im0) and -- less than a full burst remaining ((sig_btt_lt_b2mbaa_ireg1 or sig_btt_eq_b2mbaa_ireg1) and -- less than a full burst remaining -- (sig_brst_cnt_eq_zero_im0 and not(sig_no_btt_residue_im0))); (sig_brst_cnt_eq_zero_ireg1 and not(sig_no_btt_residue_ireg1))); ---------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------- -- -- General Address Counter Logic (applies to any address width of 32 or greater -- The address counter is divided into 2 16-bit segements for 32-bit address support. As the -- address gets wider, up to 2 more segements will be added via IfGens to provide for 64-bit -- addressing. -- ---------------------------------------------------------------------------------------------------- -- Rip the LS bits of the LS Address Counter for the StrobeGen -- starting address offset sig_strbgen_addr_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); -- Check if the calcualted address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat sig_addr_incr_ge_bpdb_im1 <= '1' When (sig_addr_cntr_incr_im1 >= TO_UNSIGNED(BYTES_PER_DBEAT, ADDR_CNTR_WIDTH)) Else '0'; -- If the calculated address increment (in bytes) is greater than the -- number of bytes that can be transfered per data beat, then clip the -- strobegen byte value to the number of bytes per data beat, else use the -- increment value. sig_strbgen_bytes_im1 <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1)) when (sig_addr_incr_ge_bpdb_im1 = '1') else STD_LOGIC_VECTOR(sig_addr_cntr_incr_im1(STRBGEN_ADDR_SLICE_WIDTH downto 0)); -------------------------------------------------------------------------- -- Address Counter logic sig_ld_addr_cntr <= sig_push_input_reg; -- don't increment address cntr if type is '0' (non-incrementing) sig_incr_addr_cntr <= sig_pop_xfer_reg;-- and -- sig_input_burst_type_reg; sig_mbaa_addr_cntr_slice_im0 <= sig_addr_cntr_lsh_im0(MBAA_ADDR_SLICE_WIDTH-1 downto 0); sig_bytes_to_mbaa_im0 <= TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH) - RESIZE(sig_mbaa_addr_cntr_slice_im0,ADDR_CNTR_WIDTH); sig_addr_aligned_im0 <= '1' when (sig_mbaa_addr_cntr_slice_im0 = BTT_RESIDUE_0) Else '0'; -- Check to see if the jump to the Max Burst Aligned Address (mbaa) is less -- than or equal to the remaining bytes to transfer. If it is, then at least -- two tranfers have to be scheduled. sig_btt_lt_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) < sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; sig_btt_eq_b2mbaa_im0 <= '1' when ((RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) = sig_bytes_to_mbaa_im0) and (sig_brst_cnt_eq_zero_im0 = '1')) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_REG1 -- -- Process Description: -- Intermediate register stage 1 for Address Counter -- derivative calculations. -- ------------------------------------------------------------- IMP_IM_REG1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_bytes_to_mbaa_ireg1 <= (others => '0'); sig_addr_aligned_ireg1 <= '0' ; sig_btt_lt_b2mbaa_ireg1 <= '0' ; sig_btt_eq_b2mbaa_ireg1 <= '0' ; sig_brst_cnt_eq_zero_ireg1 <= '0' ; sig_brst_cnt_eq_one_ireg1 <= '0' ; sig_no_btt_residue_ireg1 <= '0' ; elsif (sig_sm_ld_calc1_reg = '1') then sig_bytes_to_mbaa_ireg1 <= sig_bytes_to_mbaa_im0 ; sig_addr_aligned_ireg1 <= sig_addr_aligned_im0 ; sig_btt_lt_b2mbaa_ireg1 <= sig_btt_lt_b2mbaa_im0 ; sig_btt_eq_b2mbaa_ireg1 <= sig_btt_eq_b2mbaa_im0 ; sig_brst_cnt_eq_zero_ireg1 <= sig_brst_cnt_eq_zero_im0; sig_brst_cnt_eq_one_ireg1 <= sig_brst_cnt_eq_one_im0 ; sig_no_btt_residue_ireg1 <= sig_no_btt_residue_im0 ; else null; -- hold state end if; end if; end process IMP_IM_REG1; -- Select the address counter increment value to use sig_addr_cntr_incr_im1 <= RESIZE(sig_btt_residue_slice_im0, ADDR_CNTR_WIDTH) --When (sig_btt_lt_b2mbaa_im0 = '1') When (sig_btt_lt_b2mbaa_ireg1 = '1') --else sig_bytes_to_mbaa_im0 else sig_bytes_to_mbaa_ireg1 when (sig_first_xfer_im0 = '1') else TO_UNSIGNED(BYTES_PER_MAX_BURST, ADDR_CNTR_WIDTH); -- calculate the next starting address after the current -- xfer completes sig_predict_addr_lsh_im1 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_im1; -- Predict next transfer's address offset for the Strobe Generator sig_finish_addr_offset_im1 <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_im1(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0)); sig_addr_cntr_lsh_im0_slv <= STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- Determine if an address count lsh rollover is going to occur when -- jumping to the next starting address by comparing the MS bit of the -- current address lsh to the MS bit of the predicted address lsh . -- A transition of a '1' to a '0' is a rollover. sig_addr_lsh_rollover_im3 <= '1' when ( (sig_addr_cntr_lsh_im0_slv(ADDR_CNTR_WIDTH-1) = '1') and (sig_predict_addr_lsh_im3_slv(ADDR_CNTR_WIDTH-1) = '0') ) Else '0'; ---------------------------------------------------------- -- Intermediate registers for reducing the Address Counter -- Increment timing path ---------------------------------------------------------- -- calculate the next starting address after the current -- xfer completes using intermediate register values sig_predict_addr_lsh_im2 <= sig_addr_cntr_lsh_im0 + sig_addr_cntr_incr_ireg2; sig_predict_addr_lsh_im3_slv <= STD_LOGIC_VECTOR(sig_predict_addr_lsh_ireg3); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_ADDRINC_REG -- -- Process Description: -- Intermediate registers for address counter increment to -- break long timing paths. -- ------------------------------------------------------------- IMP_IM_ADDRINC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_addr_cntr_incr_ireg2 <= sig_addr_cntr_incr_im1; else null; -- hold state end if; end if; end process IMP_IM_ADDRINC_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_IM_PREDICT_ADDR_REG -- -- Process Description: -- Intermediate register for predicted address to break up -- long timing paths. -- ------------------------------------------------------------- IMP_IM_PREDICT_ADDR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_predict_addr_lsh_ireg3 <= (others => '0'); elsif (sig_sm_ld_calc3_reg = '1') then sig_predict_addr_lsh_ireg3 <= sig_predict_addr_lsh_im2; else null; -- hold state end if; end if; end process IMP_IM_PREDICT_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_ADDR_STUFF -- -- Process Description: -- Implements a general register for address counter related -- things. -- ------------------------------------------------------------- REG_ADDR_STUFF : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_adjusted_addr_incr_ireg2 <= (others => '0'); elsif (sig_sm_ld_calc2_reg = '1') then sig_adjusted_addr_incr_ireg2 <= sig_adjusted_addr_incr_im1; else null; -- hold state end if; end if; end process REG_ADDR_STUFF; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_LSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_LSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_lsh_im0 <= (others => '0'); sig_addr_cntr_lsh_kh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_lsh_im0 <= UNSIGNED(sig_cmd_addr_slice(ADDR_CNTR_WIDTH-1 downto 0)); sig_addr_cntr_lsh_kh <= sig_cmd_addr_slice; Elsif (sig_incr_addr_cntr = '1') then -- and sig_input_burst_type_reg = '1') Then sig_addr_cntr_lsh_im0 <= sig_predict_addr_lsh_ireg3; else null; -- hold current state end if; end if; end process IMP_LSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSH_ADDR_CNTR -- -- Process Description: -- Least Significant Half Address counter implementation. -- ------------------------------------------------------------- IMP_MSH_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_addr_cntr_im0_msh <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then sig_addr_cntr_im0_msh <= UNSIGNED(sig_cmd_addr_slice((2*ADDR_CNTR_WIDTH)-1 downto ADDR_CNTR_WIDTH)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1') then sig_addr_cntr_im0_msh <= sig_addr_cntr_im0_msh+ADDR_CNTR_ONE; else null; -- hold current state end if; end if; end process IMP_MSH_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FIRST_XFER_FLOP -- -- Process Description: -- Implements the register flop for the first transfer flag. -- ------------------------------------------------------------- IMP_FIRST_XFER_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_incr_addr_cntr = '1') then sig_first_xfer_im0 <= '0'; elsif (sig_ld_addr_cntr = '1') then sig_first_xfer_im0 <= '1'; else null; -- hold current state end if; end if; end process IMP_FIRST_XFER_FLOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_32 -- -- If Generate Description: -- Implements the Address segment merge logic for the 32-bit -- address width case. The address counter segments are split -- into two 16-bit sections to improve Fmax convergence. -- -- ------------------------------------------------------------ GEN_ADDR_32 : if (C_ADDR_WIDTH = 32) generate begin -- Populate the transfer address value by concatonating the -- address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); end generate GEN_ADDR_32; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_32_LE_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 32 bits and less than -- or equal to 48 bits. In this case, an additional counter segment -- is implemented (segment 3) that is variable width of 1 -- to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_32_LE_48 : if (C_ADDR_WIDTH > 32 and C_ADDR_WIDTH <= 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := C_ADDR_WIDTH-32; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant SEG3_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; begin -- Populate the transfer address value by concatonating the -- 3 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Adress Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter MSH (Segment 2) is at max value and will rollover -- at the next increment interval for the counter. Registering -- this signal and using it for the Seg 3 increment logic only -- works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 counter to go to -- max and the next increment operation that can bump segment 3. -- ------------------------------------------------------------- IMP_SEG2_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; end if; end if; end process IMP_SEG2_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and --sig_input_burst_type_reg = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; end generate GEN_ADDR_GT_32_LE_48; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADDR_GT_48 -- -- If Generate Description: -- Implements the additional Address Counter logic for the case -- when the address width is greater than 48 bits and less than -- or equal to 64. In this case, an additional 2 counter segments -- are implemented (segment 3 and 4). Segment 3 is a fixed 16-bits -- and segment 4 is variable width of 1 to 16 bits. -- ------------------------------------------------------------ GEN_ADDR_GT_48 : if (C_ADDR_WIDTH > 48) generate -- Local constants Constant ACNTR_SEG3_WIDTH : integer := ADDR_CNTR_WIDTH; Constant ACNTR_SEG3_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG3_WIDTH); Constant ACNTR_SEG3_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_MSH_MAX : unsigned(ADDR_CNTR_WIDTH-1 downto 0) := (others => '1'); Constant ACNTR_SEG4_WIDTH : integer := C_ADDR_WIDTH-48; Constant ACNTR_SEG4_ONE : unsigned := TO_UNSIGNED(1, ACNTR_SEG4_WIDTH); Constant SEG3_ADDR_RIP_MS_INDEX : integer := 47; Constant SEG3_ADDR_RIP_LS_INDEX : integer := 32; Constant SEG4_ADDR_RIP_MS_INDEX : integer := C_ADDR_WIDTH-1; Constant SEG4_ADDR_RIP_LS_INDEX : integer := 48; -- Local Signals signal lsig_seg3_addr_cntr : unsigned(ACNTR_SEG3_WIDTH-1 downto 0) := (others => '0'); signal lsig_acntr_msh_eq_max : std_logic := '0'; signal lsig_acntr_msh_eq_max_reg : std_logic := '0'; signal lsig_acntr_seg3_eq_max : std_logic := '0'; signal lsig_acntr_seg3_eq_max_reg : std_logic := '0'; signal lsig_seg4_addr_cntr : unsigned(ACNTR_SEG4_WIDTH-1 downto 0) := (others => '0'); begin -- Populate the transfer address value by concatonating the -- 4 address counter segments sig_xfer_address_im0 <= STD_LOGIC_VECTOR(lsig_seg4_addr_cntr ) & STD_LOGIC_VECTOR(lsig_seg3_addr_cntr ) & STD_LOGIC_VECTOR(sig_addr_cntr_im0_msh) & STD_LOGIC_VECTOR(sig_addr_cntr_lsh_im0); -- See if the MSH (Segment 2) of the Address Counter is at a max value lsig_acntr_msh_eq_max <= '1' when (sig_addr_cntr_im0_msh = ACNTR_MSH_MAX) Else '0'; -- See if the Segment 3 of the Address Counter is at a max value lsig_acntr_seg3_eq_max <= '1' when (lsig_seg3_addr_cntr = ACNTR_SEG3_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG2_3_EQ_MAX_REG -- -- Process Description: -- Implements a register for the flag indicating the address -- counter segments 2 and 3 are at max value and will rollover -- at the next increment interval for the counter. Registering -- these signals and using themt for the Seg 3/4 increment logic -- only works because there is always at least a 1 clock time gap -- between the increment causing the segment 2 or 3 counter to go -- to max and the next increment operation. -- ------------------------------------------------------------- IMP_SEG2_3_EQ_MAX_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_acntr_msh_eq_max_reg <= '0'; lsig_acntr_seg3_eq_max_reg <= '0'; else lsig_acntr_msh_eq_max_reg <= lsig_acntr_msh_eq_max; lsig_acntr_seg3_eq_max_reg <= lsig_acntr_seg3_eq_max; end if; end if; end process IMP_SEG2_3_EQ_MAX_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG3_ADDR_CNTR -- -- Process Description: -- Segment 3 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG3_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg3_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg3_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG3_ADDR_RIP_MS_INDEX downto SEG3_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1') then lsig_seg3_addr_cntr <= lsig_seg3_addr_cntr+ACNTR_SEG3_ONE; else null; -- hold current state end if; end if; end process IMP_SEG3_ADDR_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SEG4_ADDR_CNTR -- -- Process Description: -- Segment 4 of the Address counter implementation. -- ------------------------------------------------------------- IMP_SEG4_ADDR_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then lsig_seg4_addr_cntr <= (others => '0'); elsif (sig_ld_addr_cntr = '1') then lsig_seg4_addr_cntr <= UNSIGNED(sig_cmd_addr_slice(SEG4_ADDR_RIP_MS_INDEX downto SEG4_ADDR_RIP_LS_INDEX)); Elsif (sig_incr_addr_cntr = '1' and sig_addr_lsh_rollover_im3 = '1' and lsig_acntr_msh_eq_max_reg = '1' and lsig_acntr_seg3_eq_max_reg = '1') then lsig_seg4_addr_cntr <= lsig_seg4_addr_cntr+ACNTR_SEG4_ONE; else null; -- hold current state end if; end if; end process IMP_SEG4_ADDR_CNTR; end generate GEN_ADDR_GT_48; -- Addr and data Cntlr FIFO interface handshake logic ------------------------------ sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready; sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready; sig_clr_cmd2dre_valid <= sig_cmd2dre_valid and dre2mstr_cmd_ready; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DATA_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Data Controller Module. -- ------------------------------------------------------------- CMD2DATA_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2data_valid = '1') then sig_cmd2data_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2data_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DATA_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2ADDR_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the Address Controller Module. -- ------------------------------------------------------------- CMD2ADDR_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2addr_valid = '1') then sig_cmd2addr_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1') then sig_cmd2addr_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2ADDR_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMD2DRE_VALID_FLOP -- -- Process Description: -- Implements the set/reset flop for the Command Valid control -- to the DRE Module (S2MM DRE Only). -- -- Note that the S2MM DRE only needs to be loaded with a command -- for each parent command, not every child command. -- ------------------------------------------------------------- CMD2DRE_VALID_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_clr_cmd2dre_valid = '1') then sig_cmd2dre_valid <= '0'; elsif (sig_sm_ld_xfer_reg_ns = '1' and sig_first_xfer_im0 = '1') then sig_cmd2dre_valid <= '1'; else null; -- hold current state end if; end if; end process CMD2DRE_VALID_FLOP; ------------------------------------------------------------------------- -- PCC State machine Logic ------------------------------------------------------------- -- Combinational Process -- -- Label: PCC_SM_COMBINATIONAL -- -- Process Description: -- PCC State Machine combinational implementation -- ------------------------------------------------------------- PCC_SM_COMBINATIONAL : process (sig_pcc_sm_state , sig_parent_done , sig_push_input_reg , sig_pop_xfer_reg , sig_calc_error_pushed) begin -- SM Defaults sig_pcc_sm_state_ns <= INIT; sig_sm_halt_ns <= '0'; sig_sm_ld_xfer_reg_ns <= '0'; sig_sm_pop_input_reg_ns <= '0'; sig_sm_ld_calc1_reg_ns <= '0'; sig_sm_ld_calc2_reg_ns <= '0'; sig_sm_ld_calc3_reg_ns <= '0'; case sig_pcc_sm_state is -------------------------------------------- when INIT => sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_halt_ns <= '1'; -------------------------------------------- when WAIT_FOR_CMD => If (sig_push_input_reg = '1') Then sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; else sig_pcc_sm_state_ns <= WAIT_FOR_CMD; End if; -------------------------------------------- when CALC_1 => sig_pcc_sm_state_ns <= CALC_2; sig_sm_ld_calc2_reg_ns <= '1'; -------------------------------------------- when CALC_2 => sig_pcc_sm_state_ns <= CALC_3; sig_sm_ld_calc3_reg_ns <= '1'; -------------------------------------------- when CALC_3 => sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; sig_sm_ld_xfer_reg_ns <= '1'; -------------------------------------------- when WAIT_ON_XFER_PUSH => if (sig_pop_xfer_reg = '1') then sig_pcc_sm_state_ns <= CHK_IF_DONE; else -- wait until output register is loaded sig_pcc_sm_state_ns <= WAIT_ON_XFER_PUSH; end if; -------------------------------------------- when CHK_IF_DONE => If (sig_calc_error_pushed = '1') then -- Internal error, go to trap sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; elsif (sig_parent_done = '1') Then -- done with parent command sig_pcc_sm_state_ns <= WAIT_FOR_CMD; sig_sm_pop_input_reg_ns <= '1'; else -- Still breaking up parent command sig_pcc_sm_state_ns <= CALC_1; sig_sm_ld_calc1_reg_ns <= '1'; end if; -------------------------------------------- when ERROR_TRAP => sig_pcc_sm_state_ns <= ERROR_TRAP; sig_sm_halt_ns <= '1'; -------------------------------------------- when others => sig_pcc_sm_state_ns <= INIT; end case; end process PCC_SM_COMBINATIONAL; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PCC_SM_REGISTERED -- -- Process Description: -- PCC State Machine registered implementation -- ------------------------------------------------------------- PCC_SM_REGISTERED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1') then sig_pcc_sm_state <= INIT; sig_sm_halt_reg <= '1' ; sig_sm_pop_input_reg <= '0' ; sig_sm_ld_calc1_reg <= '0' ; sig_sm_ld_calc2_reg <= '0' ; sig_sm_ld_calc3_reg <= '0' ; else sig_pcc_sm_state <= sig_pcc_sm_state_ns ; sig_sm_halt_reg <= sig_sm_halt_ns ; sig_sm_pop_input_reg <= sig_sm_pop_input_reg_ns; sig_sm_ld_calc1_reg <= sig_sm_ld_calc1_reg_ns ; sig_sm_ld_calc2_reg <= sig_sm_ld_calc2_reg_ns ; sig_sm_ld_calc3_reg <= sig_sm_ld_calc3_reg_ns ; end if; end if; end process PCC_SM_REGISTERED; ------------------------------------------------------------------ -- Transfer Register Load Enable logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: LD_XFER_REG_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- LD_XFER_REG_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_xfer_reg = '1') then sig_ld_xfer_reg <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP; LD_XFER_REG_FLOP1 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_pop_xfer_reg = '1') then sig_ld_xfer_reg_tmp <= '0'; Elsif (sig_sm_ld_xfer_reg_ns = '1') Then sig_ld_xfer_reg_tmp <= '1'; else null; -- hold current state end if; end if; end process LD_XFER_REG_FLOP1; ------------------------------------------------------------------ -- Parent Done flag logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: PARENT_DONE_FLOP -- -- Process Description: -- Sample and Hold FLOP for signaling a load of the output -- xfer register. -- ------------------------------------------------------------- PARENT_DONE_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_mmap_reset_reg = '1' or sig_push_input_reg = '1') then sig_parent_done <= '0'; Elsif (sig_ld_xfer_reg_tmp = '1') Then sig_parent_done <= sig_last_xfer_valid_im1; else null; -- hold current state end if; end if; end process PARENT_DONE_FLOP; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/syn/vhdl/FIFO_image_filter_img_1_data_stream_1_V.vhd

4

4629

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_1_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_1_data_stream_1_V_shiftReg; architecture rtl of FIFO_image_filter_img_1_data_stream_1_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_1_data_stream_1_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_1_data_stream_1_V is component FIFO_image_filter_img_1_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_1_data_stream_1_V_shiftReg : FIFO_image_filter_img_1_data_stream_1_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_src0_data_stream_0_V.vhd

2

4621

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_src0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_src0_data_stream_0_V_shiftReg; architecture rtl of FIFO_image_filter_src0_data_stream_0_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_src0_data_stream_0_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_src0_data_stream_0_V is component FIFO_image_filter_src0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_src0_data_stream_0_V_shiftReg : FIFO_image_filter_src0_data_stream_0_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/FIFO_image_filter_src0_data_stream_0_V.vhd

2

4621

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_src0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_src0_data_stream_0_V_shiftReg; architecture rtl of FIFO_image_filter_src0_data_stream_0_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_src0_data_stream_0_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_src0_data_stream_0_V is component FIFO_image_filter_src0_data_stream_0_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_src0_data_stream_0_V_shiftReg : FIFO_image_filter_src0_data_stream_0_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/lite_ecc_reg.vhd

7

68156

------------------------------------------------------------------------------- -- lite_ecc_reg.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: lite_ecc_reg.vhd -- -- Description: This module contains the register components for the -- ECC status & control data when enabled. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl.vhd (v1_03_a) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/17/2011 v1.03a -- ~~~~~~ -- Add ECC support for 128-bit BRAM data width. -- Clean-up XST warnings. Add C_BRAM_ADDR_ADJUST_FACTOR parameter and -- modify BRAM address registers. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.axi_lite_if; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity lite_ecc_reg is generic ( C_S_AXI_PROTOCOL : string := "AXI4"; -- Used in this module to differentiate timing for error capture C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_SINGLE_PORT_BRAM : INTEGER := 1; -- Enable single port usage of BRAM C_BRAM_ADDR_ADJUST_FACTOR : integer := 2; -- Adjust factor to BRAM address width based on data width (in bits) -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC_WIDTH : integer := 8; -- Width of ECC data vector C_FAULT_INJECT : integer := 0; -- Enable fault injection registers C_ECC_ONOFF_RESET_VALUE : integer := 1; -- By default, ECC checking is on (can disable ECC @ reset by setting this to 0) -- Hard coded parameters at top level. -- Note: Kept in design for future enhancement. C_ENABLE_AXI_CTRL_REG_IF : integer := 0; -- By default the ECC AXI-Lite register interface is enabled C_CE_FAILING_REGISTERS : integer := 0; -- Enable CE (correctable error) failing registers C_UE_FAILING_REGISTERS : integer := 0; -- Enable UE (uncorrectable error) failing registers C_ECC_STATUS_REGISTERS : integer := 0; -- Enable ECC status registers C_ECC_ONOFF_REGISTER : integer := 0; -- Enable ECC on/off control register C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Clock and Reset S_AXI_AClk : in std_logic; S_AXI_AResetn : in std_logic; -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_AClk : in std_logic; -- S_AXI_CTRL_AResetn : in std_logic; Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- *** AXI-Lite ECC Register Interface Signals *** -- All synchronized to S_AXI_CTRL_AClk -- AXI-Lite Write Address Channel Signals (AW) AXI_CTRL_AWVALID : in std_logic; AXI_CTRL_AWREADY : out std_logic; AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_WVALID : in std_logic; AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); AXI_CTRL_BVALID : out std_logic; AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); AXI_CTRL_ARVALID : in std_logic; AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); AXI_CTRL_RVALID : out std_logic; AXI_CTRL_RREADY : in std_logic; -- *** Memory Controller Interface Signals *** -- All synchronized to S_AXI_AClk Enable_ECC : out std_logic; -- Indicates if and when ECC is enabled FaultInjectClr : in std_logic; -- Clear for Fault Inject Registers CE_Failing_We : in std_logic; -- WE for CE Failing Registers -- UE_Failing_We : in std_logic; -- WE for CE Failing Registers CE_CounterReg_Inc : in std_logic; -- Increment CE Counter Register Sl_CE : in std_logic; -- Correctable Error Flag Sl_UE : in std_logic; -- Uncorrectable Error Flag BRAM_Addr_A : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_B : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR); -- v1.03a BRAM_Addr_En : in std_logic; Active_Wr : in std_logic; -- BRAM_RdData_A : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- BRAM_RdData_B : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); -- Outputs FaultInjectData : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1); FaultInjectECC : out std_logic_vector (0 to C_ECC_WIDTH-1) ); end entity lite_ecc_reg; ------------------------------------------------------------------------------- architecture implementation of lite_ecc_reg is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- constant C_RESET_ACTIVE : std_logic := '0'; constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Start LMB BRAM v3.00a HDL constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1; constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1; constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1; constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1; constant C_HAS_ECC_ONOFF : boolean := C_ECC_ONOFF_REGISTER = 1; constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0; -- Register accesses -- Register addresses use word address, i.e 2 LSB don't care -- Don't decode MSB, i.e. mirrorring of registers in address space of module constant C_REGADDR_WIDTH : integer := 8; constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x0 = 00 0000 00 constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x4 = 00 0000 01 constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x8 = 00 0000 10 constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0xC = 00 0000 11 constant C_CE_FailingData_31_0 : std_logic_vector := "01000000"; -- 0x100 = 01 0000 00 constant C_CE_FailingData_63_31 : std_logic_vector := "01000001"; -- 0x104 = 01 0000 01 constant C_CE_FailingData_95_64 : std_logic_vector := "01000010"; -- 0x108 = 01 0000 10 constant C_CE_FailingData_127_96 : std_logic_vector := "01000011"; -- 0x10C = 01 0000 11 constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 = 01 1000 00 constant C_CE_FailingAddress_31_0 : std_logic_vector := "01110000"; -- 0x1C0 = 01 1100 00 constant C_CE_FailingAddress_63_32 : std_logic_vector := "01110001"; -- 0x1C4 = 01 1100 01 constant C_UE_FailingData_31_0 : std_logic_vector := "10000000"; -- 0x200 = 10 0000 00 constant C_UE_FailingData_63_31 : std_logic_vector := "10000001"; -- 0x204 = 10 0000 01 constant C_UE_FailingData_95_64 : std_logic_vector := "10000010"; -- 0x208 = 10 0000 10 constant C_UE_FailingData_127_96 : std_logic_vector := "10000011"; -- 0x20C = 10 0000 11 constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 = 10 1000 00 constant C_UE_FailingAddress_31_0 : std_logic_vector := "10110000"; -- 0x2C0 = 10 1100 00 constant C_UE_FailingAddress_63_32 : std_logic_vector := "10110000"; -- 0x2C4 = 10 1100 00 constant C_FaultInjectData_31_0 : std_logic_vector := "11000000"; -- 0x300 = 11 0000 00 constant C_FaultInjectData_63_32 : std_logic_vector := "11000001"; -- 0x304 = 11 0000 01 constant C_FaultInjectData_95_64 : std_logic_vector := "11000010"; -- 0x308 = 11 0000 10 constant C_FaultInjectData_127_96 : std_logic_vector := "11000011"; -- 0x30C = 11 0000 11 constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 = 11 1000 00 -- ECC Status register bit positions constant C_ECC_STATUS_CE : natural := 30; constant C_ECC_STATUS_UE : natural := 31; constant C_ECC_STATUS_WIDTH : natural := 2; constant C_ECC_ENABLE_IRQ_CE : natural := 30; constant C_ECC_ENABLE_IRQ_UE : natural := 31; constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2; constant C_ECC_ON_OFF_WIDTH : natural := 1; -- End LMB BRAM v3.00a HDL constant MSB_ZERO : std_logic_vector (31 downto C_S_AXI_ADDR_WIDTH) := (others => '0'); ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- signal S_AXI_AReset : std_logic; -- Start LMB BRAM v3.00a HDL -- Read and write data to internal registers constant C_DWIDTH : integer := 32; signal RegWrData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegWrData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegWrData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegRdData_i : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d1 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); --signal RegRdData_d2 : std_logic_vector(0 to C_DWIDTH-1) := (others => '0'); signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegAddr_i : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d1 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); --signal RegAddr_d2 : std_logic_vector(0 to C_REGADDR_WIDTH-1) := (others => '0'); signal RegWr : std_logic; signal RegWr_i : std_logic; --signal RegWr_d1 : std_logic; --signal RegWr_d2 : std_logic; -- Fault Inject Register signal FaultInjectData_WE_0 : std_logic := '0'; signal FaultInjectData_WE_1 : std_logic := '0'; signal FaultInjectData_WE_2 : std_logic := '0'; signal FaultInjectData_WE_3 : std_logic := '0'; signal FaultInjectECC_WE : std_logic := '0'; --signal FaultInjectClr : std_logic := '0'; -- Correctable Error First Failing Register signal CE_FailingAddress : std_logic_vector(0 to 31) := (others => '0'); signal CE_Failing_We_i : std_logic := '0'; -- signal CE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31); -- Uncorrectable Error First Failing Register -- signal UE_FailingAddress : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) := (others => '0'); -- signal UE_Failing_We_i : std_logic := '0'; -- signal UE_FailingData : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); -- signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31) := (others => '0'); -- ECC Status and Control register signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_StatusReg_WE : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31) := (others => '0'); signal ECC_EnableIRQReg_WE : std_logic := '0'; -- ECC On/Off Control register signal ECC_OnOffReg : std_logic_vector(32-C_ECC_ON_OFF_WIDTH to 31) := (others => '0'); signal ECC_OnOffReg_WE : std_logic := '0'; -- Correctable Error Counter signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31) := (others => '0'); signal CE_CounterReg_WE : std_logic := '0'; signal CE_CounterReg_Inc_i : std_logic := '0'; -- End LMB BRAM v3.00a HDL signal BRAM_Addr_A_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_A_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal FailingAddr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal axi_lite_wstrb_int : std_logic_vector (C_S_AXI_CTRL_DATA_WIDTH/8-1 downto 0) := (others => '0'); signal Enable_ECC_i : std_logic := '0'; signal ECC_UE_i : std_logic := '0'; signal FaultInjectData_i : std_logic_vector (0 to C_S_AXI_DATA_WIDTH-1) := (others => '0'); signal FaultInjectECC_i : std_logic_vector (0 to C_ECC_WIDTH-1) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin FaultInjectData <= FaultInjectData_i; FaultInjectECC <= FaultInjectECC_i; -- Reserve for future support. -- S_AXI_CTRL_AReset <= not (S_AXI_CTRL_AResetn); S_AXI_AReset <= not (S_AXI_AResetn); --------------------------------------------------------------------------- -- Instance: I_LITE_ECC_REG -- -- Description: -- This module is for the AXI-Lite ECC registers. -- -- Responsible for all AXI-Lite communication to the -- ECC register bank. Provides user interface signals -- to rest of AXI BRAM controller IP core for ECC functionality -- and control. -- -- Manages AXI-Lite write address (AW) and read address (AR), -- write data (W), write response (B), and read data (R) channels. -- -- Synchronized to AXI-Lite clock and reset. -- All RegWr, RegWrData, RegAddr, RegRdData must be synchronized to -- the AXI clock. -- --------------------------------------------------------------------------- I_AXI_LITE_IF : entity work.axi_lite_if generic map( C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH, C_REGADDR_WIDTH => C_REGADDR_WIDTH, C_DWIDTH => C_DWIDTH ) port map ( -- Reserve for future support. -- LMB_Clk => S_AXI_CTRL_AClk, -- LMB_Rst => S_AXI_CTRL_AReset, LMB_Clk => S_AXI_AClk, LMB_Rst => S_AXI_AReset, S_AXI_AWADDR => AXI_CTRL_AWADDR, S_AXI_AWVALID => AXI_CTRL_AWVALID, S_AXI_AWREADY => AXI_CTRL_AWREADY, S_AXI_WDATA => AXI_CTRL_WDATA, S_AXI_WSTRB => axi_lite_wstrb_int, S_AXI_WVALID => AXI_CTRL_WVALID, S_AXI_WREADY => AXI_CTRL_WREADY, S_AXI_BRESP => AXI_CTRL_BRESP, S_AXI_BVALID => AXI_CTRL_BVALID, S_AXI_BREADY => AXI_CTRL_BREADY, S_AXI_ARADDR => AXI_CTRL_ARADDR, S_AXI_ARVALID => AXI_CTRL_ARVALID, S_AXI_ARREADY => AXI_CTRL_ARREADY, S_AXI_RDATA => AXI_CTRL_RDATA, S_AXI_RRESP => AXI_CTRL_RRESP, S_AXI_RVALID => AXI_CTRL_RVALID, S_AXI_RREADY => AXI_CTRL_RREADY, RegWr => RegWr_i, RegWrData => RegWrData_i, RegAddr => RegAddr_i, RegRdData => RegRdData_i ); -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- -- Save HDL -- If it is decided to go back and use seperate clock inputs -- One for AXI4 and one for AXI4-Lite on this core. -- For now, temporarily comment out and replace the *_i signal -- assignments. RegWr <= RegWr_i; RegWrData <= RegWrData_i; RegAddr <= RegAddr_i; RegRdData_i <= RegRdData; -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- -- -- All registers must be synchronized to the correct clock. -- -- RegWr must be synchronized to the S_AXI_Clk -- -- RegWrData must be synchronized to the S_AXI_Clk -- -- RegAddr must be synchronized to the S_AXI_Clk -- -- RegRdData must be synchronized to the S_AXI_CTRL_Clk -- -- -- --------------------------------------------------------------------------- -- -- SYNC_AXI_CLK: process (S_AXI_AClk) -- begin -- if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then -- RegWr_d1 <= RegWr_i; -- RegWr_d2 <= RegWr_d1; -- RegWrData_d1 <= RegWrData_i; -- RegWrData_d2 <= RegWrData_d1; -- RegAddr_d1 <= RegAddr_i; -- RegAddr_d2 <= RegAddr_d1; -- end if; -- end process SYNC_AXI_CLK; -- -- RegWr <= RegWr_d2; -- RegWrData <= RegWrData_d2; -- RegAddr <= RegAddr_d2; -- -- -- SYNC_AXI_LITE_CLK: process (S_AXI_CTRL_AClk) -- begin -- if (S_AXI_CTRL_AClk'event and S_AXI_CTRL_AClk = '1' ) then -- RegRdData_d1 <= RegRdData; -- RegRdData_d2 <= RegRdData_d1; -- end if; -- end process SYNC_AXI_LITE_CLK; -- -- RegRdData_i <= RegRdData_d2; -- --------------------------------------------------------------------------- axi_lite_wstrb_int <= (others => '1'); --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_SNG -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If single port, only register Port A address. -- -- With CE flag being registered, must account for one more -- pipeline stage in stored BRAM addresss that correlates to -- failing ECC. --------------------------------------------------------------------------- GEN_ADDR_REG_SNG: if (C_SINGLE_PORT_BRAM = 1) generate -- 3rd pipeline stage on Port A (used for reads in single port mode) ONLY signal BRAM_Addr_A_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_A_d2 <= BRAM_Addr_A_d1; BRAM_Addr_A_d3 <= BRAM_Addr_A_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_A_d2 <= BRAM_Addr_A_d2; BRAM_Addr_A_d3 <= BRAM_Addr_A_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin FailingAddr_Ld (i) <= BRAM_Addr_A_d1(i); -- Only a single address active at a time. end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline). -- During read operaitons, use 3-deep address pipeline to store address values. FailingAddr_Ld (i) <= BRAM_Addr_A_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_SNG; --------------------------------------------------------------------------- -- Generate: GEN_ADDR_REG_DUAL -- Purpose: Generate two deep wrap-around address pipeline to store -- read address presented to BRAM. Used to update ECC -- register value when ECC correctable or uncorrectable error -- is detected. -- -- If dual port BRAM, register Port A & Port B address. -- -- Account for CE flag register delay, add 3rd BRAM address -- pipeline stage. -- --------------------------------------------------------------------------- GEN_ADDR_REG_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate -- Port B pipeline stages only used in a dual port mode configuration. signal BRAM_Addr_B_d1 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d2 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a signal BRAM_Addr_B_d3 : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0'); -- v1.03a begin BRAM_ADDR_REG: process (S_AXI_AClk) begin if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then if (BRAM_Addr_En = '1') then BRAM_Addr_A_d1 <= BRAM_Addr_A; BRAM_Addr_B_d1 <= BRAM_Addr_B; BRAM_Addr_B_d2 <= BRAM_Addr_B_d1; BRAM_Addr_B_d3 <= BRAM_Addr_B_d2; else BRAM_Addr_A_d1 <= BRAM_Addr_A_d1; BRAM_Addr_B_d1 <= BRAM_Addr_B_d1; BRAM_Addr_B_d2 <= BRAM_Addr_B_d2; BRAM_Addr_B_d3 <= BRAM_Addr_B_d3; end if; end if; end process BRAM_ADDR_REG; --------------------------------------------------------------------------- -- Generate: GEN_L_ADDR -- Purpose: Lower order BRAM address bits fixed @ zero depending -- on BRAM data width size. --------------------------------------------------------------------------- GEN_L_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate begin FailingAddr_Ld (i) <= '0'; end generate GEN_L_ADDR; --------------------------------------------------------------------------- -- Generate: GEN_ADDR -- Purpose: Assign valid BRAM address bits based on BRAM data width size. --------------------------------------------------------------------------- GEN_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate begin GEN_FA_LITE: if IF_IS_AXI4LITE generate begin -- Only one active operation at a time. -- Use one deep address pipeline. Determine if Port A or B based on active read or write. FailingAddr_Ld (i) <= BRAM_Addr_B_d1 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_LITE; GEN_FA_AXI: if IF_IS_AXI4 generate begin -- During the RMW portion, only one active address (use _d1 pipeline) (and from Port A). -- During read operations, use 3-deep address pipeline to store address values (and from Port B). FailingAddr_Ld (i) <= BRAM_Addr_B_d3 (i) when (Active_Wr = '0') else BRAM_Addr_A_d1 (i); end generate GEN_FA_AXI; end generate GEN_ADDR; end generate GEN_ADDR_REG_DUAL; --------------------------------------------------------------------------- -- Generate: FAULT_INJECT -- Purpose: Implement fault injection registers -- Remove check for (C_WRITE_ACCESS /= NO_WRITES) (from LMB) --------------------------------------------------------------------------- FAULT_INJECT : if C_HAS_FAULT_INJECT generate begin -- FaultInjectClr added to top level port list. -- Original LMB BRAM HDL -- FaultInjectClr <= '1' when ((sl_ready_i = '1') and (write_access = '1')) else '0'; --------------------------------------------------------------------------- -- Generate: GEN_32_FAULT -- Purpose: Create generates based on 32-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_32_FAULT : if C_S_AXI_DATA_WIDTH = 32 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 32-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (25:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_32_FAULT; --------------------------------------------------------------------------- -- Generate: GEN_64_FAULT -- Purpose: Create generates based on 64-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_64_FAULT : if C_S_AXI_DATA_WIDTH = 64 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 64-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then -- FaultInjectECC_i <= RegWrData(0 to C_DWIDTH-1); -- FaultInjectECC_i <= RegWrData(0 to C_ECC_WIDTH-1); -- (24:31) FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_64_FAULT; -- v1.03a --------------------------------------------------------------------------- -- Generate: GEN_128_FAULT -- Purpose: Create generates based on 128-bit C_S_AXI_DATA_WIDTH --------------------------------------------------------------------------- GEN_128_FAULT : if C_S_AXI_DATA_WIDTH = 128 generate begin FaultInjectData_WE_0 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_31_0) else '0'; FaultInjectData_WE_1 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_63_32) else '0'; FaultInjectData_WE_2 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_95_64) else '0'; FaultInjectData_WE_3 <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectData_127_96) else '0'; FaultInjectECC_WE <= '1' when (RegWr = '1' and RegAddr = C_FaultInjectECC) else '0'; -- Create fault vector for 128-bit data widths FaultInjectDataReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); elsif FaultInjectData_WE_0 = '1' then FaultInjectData_i (96 to 127) <= RegWrData; elsif FaultInjectData_WE_1 = '1' then FaultInjectData_i (64 to 95) <= RegWrData; elsif FaultInjectData_WE_2 = '1' then FaultInjectData_i (32 to 63) <= RegWrData; elsif FaultInjectData_WE_3 = '1' then FaultInjectData_i (0 to 31) <= RegWrData; elsif FaultInjectECC_WE = '1' then FaultInjectECC_i <= RegWrData(C_S_AXI_CTRL_DATA_WIDTH-C_ECC_WIDTH to C_S_AXI_CTRL_DATA_WIDTH-1); elsif FaultInjectClr = '1' then -- One shoot, clear after first LMB write FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end if; end if; end process FaultInjectDataReg; end generate GEN_128_FAULT; end generate FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: NO_FAULT_INJECT -- Purpose: Set default outputs when no fault inject capabilities. -- Remove check from C_WRITE_ACCESS (from LMB) --------------------------------------------------------------------------- NO_FAULT_INJECT : if not C_HAS_FAULT_INJECT generate begin FaultInjectData_i <= (others => '0'); FaultInjectECC_i <= (others => '0'); end generate NO_FAULT_INJECT; --------------------------------------------------------------------------- -- Generate: CE_FAILING_REGISTERS -- Purpose: Implement Correctable Error First Failing Register --------------------------------------------------------------------------- CE_FAILING_REGISTERS : if C_HAS_CE_FAILING_REGISTERS generate begin -- TBD (could come from axi_lite) -- CE_Failing_We <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') -- else '0'; CE_Failing_We_i <= '1' when (CE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0') else '0'; CE_FailingReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then CE_FailingAddress <= (others => '0'); -- Reserve for future support. -- CE_FailingData <= (others => '0'); elsif CE_Failing_We_i = '1' then --As the AXI Addr Width can now be lesser than 32, the address is getting shifted --Eg: If addr width is 16, and Failing address is 0000_fffc, the o/p on RDATA is comming as fffc_0000 CE_FailingAddress (0 to C_S_AXI_ADDR_WIDTH-1) <= FailingAddr_Ld (C_S_AXI_ADDR_WIDTH-1 downto 0); --CE_FailingAddress <= MSB_ZERO & FailingAddr_Ld ; -- Reserve for future support. -- CE_FailingData (0 to C_S_AXI_DATA_WIDTH-1) <= FailingRdData(0 to C_DWIDTH-1); end if; end if; end process CE_FailingReg; -- Note: Remove storage of CE_FFE & CE_FFD registers. -- Here for future support. -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_CE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_CE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- CE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- CE_FailingECC <= (others => '0'); -- elsif CE_Failing_We_i = '1' then -- CE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process CE_FailingECCReg; -- -- end generate GEN_CE_ECC_64; end generate CE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_CE_FAILING_REGISTERS -- Purpose: No Correctable Error Failing registers. --------------------------------------------------------------------------- NO_CE_FAILING_REGISTERS : if not C_HAS_CE_FAILING_REGISTERS generate begin CE_FailingAddress <= (others => '0'); -- CE_FailingData <= (others => '0'); -- CE_FailingECC <= (others => '0'); end generate NO_CE_FAILING_REGISTERS; -- Note: C_HAS_UE_FAILING_REGISTERS will always be set to 0 -- This generate clause will never be evaluated. -- Here for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: UE_FAILING_REGISTERS -- -- Purpose: Implement Unorrectable Error First Failing Register -- --------------------------------------------------------------------------- -- -- UE_FAILING_REGISTERS : if C_HAS_UE_FAILING_REGISTERS generate -- begin -- -- -- TBD (could come from axi_lite) -- -- UE_Failing_We <= '1' when (Sl_UE_i = '1' and Sl_Ready_i = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- -- else '0'; -- -- UE_Failing_We_i <= '1' when (UE_Failing_We = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0') -- else '0'; -- -- -- UE_FailingReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingAddress <= FailingAddr_Ld; -- UE_FailingData <= FailingRdData(0 to C_DWIDTH-1); -- end if; -- end if; -- end process UE_FailingReg; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_32 -- -- Purpose: Re-align ECC bits unique for 32-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_32: if C_S_AXI_DATA_WIDTH = 32 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- -- Data2Mem shifts ECC to lower data bits in remaining byte (when 32-bit data width) (33 to 39) -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH+1 to C_S_AXI_DATA_WIDTH+1+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_32; -- -- ----------------------------------------------------------------- -- -- Generate: GEN_UE_ECC_64 -- -- Purpose: Re-align ECC bits unique for 64-bit BRAM data width. -- ----------------------------------------------------------------- -- GEN_UE_ECC_64: if C_S_AXI_DATA_WIDTH = 64 generate -- begin -- -- UE_FailingECCReg : process(S_AXI_AClk) is -- begin -- if S_AXI_AClk'event and S_AXI_AClk = '1' then -- if S_AXI_AResetn = C_RESET_ACTIVE then -- UE_FailingECC <= (others => '0'); -- elsif UE_Failing_We = '1' then -- UE_FailingECC <= FailingRdData(C_S_AXI_DATA_WIDTH to C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1); -- end if; -- end if; -- end process UE_FailingECCReg; -- -- end generate GEN_UE_ECC_64; -- -- end generate UE_FAILING_REGISTERS; -- -- -- --------------------------------------------------------------------------- -- -- Generate: NO_UE_FAILING_REGISTERS -- -- Purpose: No Uncorrectable Error Failing registers. -- --------------------------------------------------------------------------- -- -- NO_UE_FAILING_REGISTERS : if not C_HAS_UE_FAILING_REGISTERS generate -- begin -- UE_FailingAddress <= (others => '0'); -- UE_FailingData <= (others => '0'); -- UE_FailingECC <= (others => '0'); -- end generate NO_UE_FAILING_REGISTERS; --------------------------------------------------------------------------- -- Generate: ECC_STATUS_REGISTERS -- Purpose: Enable ECC status and interrupt enable registers. --------------------------------------------------------------------------- ECC_STATUS_REGISTERS : if C_HAS_ECC_STATUS_REGISTERS generate begin ECC_StatusReg_WE (C_ECC_STATUS_CE) <= Sl_CE; ECC_StatusReg_WE (C_ECC_STATUS_UE) <= Sl_UE; StatusReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_StatusReg <= (others => '0'); elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then -- CE Interrupt status bit if RegWrData(C_ECC_STATUS_CE) = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1' end if; -- UE Interrupt status bit if RegWrData(C_ECC_STATUS_UE) = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1' end if; else if Sl_CE = '1' then ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs end if; if Sl_UE = '1' then ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs end if; end if; end if; end process StatusReg; ECC_EnableIRQReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_EnableIRQReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then ECC_EnableIRQReg <= (others => '0'); elsif ECC_EnableIRQReg_WE = '1' then -- CE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE); -- UE Interrupt enable bit ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE); end if; end if; end process EnableIRQReg; Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or (ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE)); --------------------------------------------------------------------------- -- Generate output flag for UE sticky bit -- Modify order to ensure that ECC_UE gets set when Sl_UE is asserted. REG_UE : process (S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE or (Enable_ECC_i = '0') then ECC_UE_i <= '0'; elsif Sl_UE = '1' then ECC_UE_i <= '1'; elsif (ECC_StatusReg (C_ECC_STATUS_UE) = '0') then ECC_UE_i <= '0'; else ECC_UE_i <= ECC_UE_i; end if; end if; end process REG_UE; ECC_UE <= ECC_UE_i; --------------------------------------------------------------------------- end generate ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: NO_ECC_STATUS_REGISTERS -- Purpose: No ECC status or interrupt registers enabled. --------------------------------------------------------------------------- NO_ECC_STATUS_REGISTERS : if not C_HAS_ECC_STATUS_REGISTERS generate begin ECC_EnableIRQReg <= (others => '0'); ECC_StatusReg <= (others => '0'); Interrupt <= '0'; ECC_UE <= '0'; end generate NO_ECC_STATUS_REGISTERS; --------------------------------------------------------------------------- -- Generate: GEN_ECC_ONOFF -- Purpose: Implement ECC on/off control register. --------------------------------------------------------------------------- GEN_ECC_ONOFF : if C_HAS_ECC_ONOFF generate begin ECC_OnOffReg_WE <= '1' when (RegWr = '1' and RegAddr = C_ECC_OnOffReg) else '0'; EnableIRQReg : process(S_AXI_AClk) is begin if S_AXI_AClk'event and S_AXI_AClk = '1' then if S_AXI_AResetn = C_RESET_ACTIVE then if (C_ECC_ONOFF_RESET_VALUE = 0) then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; else ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '1'; end if; -- ECC on by default at reset (but can be disabled) elsif ECC_OnOffReg_WE = '1' then ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= RegWrData(32-C_ECC_ON_OFF_WIDTH); end if; end if; end process EnableIRQReg; Enable_ECC_i <= ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH); Enable_ECC <= Enable_ECC_i; end generate GEN_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: GEN_NO_ECC_ONOFF -- Purpose: No ECC on/off control register. --------------------------------------------------------------------------- GEN_NO_ECC_ONOFF : if not C_HAS_ECC_ONOFF generate begin Enable_ECC <= '0'; -- ECC ON/OFF register is only enabled when C_ECC = 1. -- If C_ECC = 0, then no ECC on/off register (C_HAS_ECC_ONOFF = 0) then -- ECC should be disabled. ECC_OnOffReg(32-C_ECC_ON_OFF_WIDTH) <= '0'; end generate GEN_NO_ECC_ONOFF; --------------------------------------------------------------------------- -- Generate: CE_COUNTER -- Purpose: Enable Correctable Error Counter -- Fixed to size of C_CE_COUNTER_WIDTH = 8 bits. -- Parameterized here for future enhancements. --------------------------------------------------------------------------- CE_COUNTER : if C_HAS_CE_COUNTER generate -- One extra bit compare to CE_CounterReg to handle carry bit signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31); begin CE_CounterReg_WE <= '1' when (RegWr = '1' and RegAddr = C_CE_CounterReg) else '0'; -- TBD (could come from axi_lite) -- CE_CounterReg_Inc <= '1' when (Sl_CE_i = '1' and Sl_Ready_i = '1' and -- CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') -- else '0'; CE_CounterReg_Inc_i <= '1' when (CE_CounterReg_Inc = '1' and CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0') else '0'; CountReg : process(S_AXI_AClk) is begin if (S_AXI_AClk'event and S_AXI_AClk = '1') then if (S_AXI_AResetn = C_RESET_ACTIVE) then CE_CounterReg <= (others => '0'); elsif CE_CounterReg_WE = '1' then -- CE_CounterReg <= RegWrData(0 to C_DWIDTH-1); CE_CounterReg <= RegWrData(32-C_CE_COUNTER_WIDTH to 31); elsif CE_CounterReg_Inc_i = '1' then CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31); end if; end if; end process CountReg; CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1); end generate CE_COUNTER; -- Note: Hit this generate when C_ECC = 0. -- Reserve for future support. -- -- --------------------------------------------------------------------------- -- -- Generate: NO_CE_COUNTER -- -- Purpose: Default for no CE counter register. -- --------------------------------------------------------------------------- -- -- NO_CE_COUNTER : if not C_HAS_CE_COUNTER generate -- begin -- CE_CounterReg <= (others => '0'); -- end generate NO_CE_COUNTER; --------------------------------------------------------------------------- -- Generate: GEN_REG_32_DATA -- Purpose: Generate read register values & signal assignments based on -- 32-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_32_DATA: if C_S_AXI_DATA_WIDTH = 32 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress; when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- CE_FailingData (0 to 31); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= (others => '0'); -- CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- UE_FailingData (0 to 31); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= (others => '0'); -- UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_32_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_64_DATA -- Purpose: Generate read register values & signal assignments based on -- 64-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_64_DATA: if C_S_AXI_DATA_WIDTH = 64 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_64_DATA; --------------------------------------------------------------------------- -- Generate: GEN_REG_128_DATA -- Purpose: Generate read register values & signal assignments based on -- 128-bit BRAM data width. --------------------------------------------------------------------------- GEN_REG_128_DATA: if C_S_AXI_DATA_WIDTH = 128 generate begin SelRegRdData : process (RegAddr, ECC_StatusReg, ECC_EnableIRQReg, ECC_OnOffReg, CE_CounterReg, CE_FailingAddress, FaultInjectData_i, FaultInjectECC_i -- CE_FailingData, CE_FailingECC, -- UE_FailingAddress, UE_FailingData, UE_FailingECC ) begin RegRdData <= (others => '0'); case RegAddr is -- Replace 'range use here for vector (31:0) (AXI BRAM) and (0:31) (LMB BRAM) reassignment when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg; when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg; when C_ECC_OnOffReg => RegRdData(ECC_OnOffReg'range) <= ECC_OnOffReg; when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg; when C_CE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= CE_FailingAddress (0 to 31); when C_CE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- Temporary addition to readback fault inject register values when C_FaultInjectData_31_0 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (0 to 31); when C_FaultInjectData_63_32 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (32 to 63); when C_FaultInjectData_95_64 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (64 to 95); when C_FaultInjectData_127_96 => RegRdData(0 to C_DWIDTH-1) <= FaultInjectData_i (96 to 127); when C_FaultInjectECC => RegRdData(C_DWIDTH-C_ECC_WIDTH to C_DWIDTH-1) <= FaultInjectECC_i (0 to C_ECC_WIDTH-1); -- Note: For future enhancement. -- when C_CE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (96 to 127); -- when C_CE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (64 to 95); -- when C_CE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (32 to 63); -- when C_CE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= CE_FailingData (0 to 31); -- when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC; -- when C_UE_FailingAddress_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingAddress (0 to 31); -- when C_UE_FailingAddress_63_32 => RegRdData(0 to C_DWIDTH-1) <= (others => '0'); -- when C_UE_FailingData_31_0 => RegRdData(0 to C_DWIDTH-1) <= UE_FailingData (96 to 127); -- when C_UE_FailingData_63_31 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (64 to 95); -- when C_UE_FailingData_95_64 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (32 to 63); -- when C_UE_FailingData_127_96 => RegRdData(0 to C_DWIDTH-1 ) <= UE_FailingData (0 to 31); -- when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC; when others => RegRdData <= (others => '0'); end case; end process SelRegRdData; end generate GEN_REG_128_DATA; --------------------------------------------------------------------------- end architecture implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/image_filter.vhd

2

183530

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter is port ( INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0); INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0); INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0); INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0); rows : IN STD_LOGIC_VECTOR (31 downto 0); cols : IN STD_LOGIC_VECTOR (31 downto 0); ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; ap_start : IN STD_LOGIC; INPUT_STREAM_TVALID : IN STD_LOGIC; INPUT_STREAM_TREADY : OUT STD_LOGIC; OUTPUT_STREAM_TVALID : OUT STD_LOGIC; OUTPUT_STREAM_TREADY : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC ); end; architecture behav of image_filter is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "image_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.666670,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=6.112860,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=59,HLS_SYN_DSP=3,HLS_SYN_FF=7667,HLS_SYN_LUT=13162}"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_true : BOOLEAN := true; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_const_logic_1 : STD_LOGIC := '1'; signal ap_rst_n_inv : STD_LOGIC; signal image_filter_Block_proc_U0_ap_start : STD_LOGIC; signal image_filter_Block_proc_U0_ap_done : STD_LOGIC; signal image_filter_Block_proc_U0_ap_continue : STD_LOGIC; signal image_filter_Block_proc_U0_ap_idle : STD_LOGIC; signal image_filter_Block_proc_U0_ap_ready : STD_LOGIC; signal image_filter_Block_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0); signal image_filter_Block_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0); signal image_filter_Block_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_4 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_5 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_6 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_7 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_8 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_9 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_10 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_proc_U0_ap_return_11 : STD_LOGIC_VECTOR (11 downto 0); signal ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel : STD_LOGIC; signal p_dst_cols_V_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_dst_cols_V_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_dst_cols_V_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_full_n : STD_LOGIC; signal ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel : STD_LOGIC; signal p_src_cols_V_2_loc_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_src_cols_V_2_loc_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_cols_V_2_loc_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_full_n : STD_LOGIC; signal ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel : STD_LOGIC; signal p_src_rows_V_2_loc_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_src_rows_V_2_loc_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_rows_V_2_loc_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel : STD_LOGIC; signal p_src_cols_V_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_src_cols_V_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_cols_V_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V : STD_LOGIC; signal p_dst_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_p_dst_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_dst_cols_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel : STD_LOGIC; signal p_dst_rows_V_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_dst_rows_V_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_dst_rows_V_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V : STD_LOGIC; signal p_dst_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_p_dst_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_dst_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel : STD_LOGIC; signal p_src_rows_V_channel_full_n : STD_LOGIC; signal ap_reg_ready_p_src_rows_V_channel_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_rows_V_channel_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 : STD_LOGIC; signal p_src_rows_V_channel1_full_n : STD_LOGIC; signal ap_reg_ready_p_src_rows_V_channel1_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_rows_V_channel1_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 : STD_LOGIC; signal p_src_cols_V_channel1_full_n : STD_LOGIC; signal ap_reg_ready_p_src_cols_V_channel1_full_n : STD_LOGIC := '0'; signal ap_sig_ready_p_src_cols_V_channel1_full_n : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_start : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_done : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_continue : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_idle : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_ap_ready : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n : STD_LOGIC; signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_start : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_done : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_continue : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_idle : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_ready : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_read2 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_read16 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_read17 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_4 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_5 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_6 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1220_proc1_U0_ap_return_7 : STD_LOGIC_VECTOR (11 downto 0); signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V : STD_LOGIC; signal src0_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_src0_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_src0_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V : STD_LOGIC; signal src0_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_src0_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_src0_cols_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V : STD_LOGIC; signal src1_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_src1_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_src1_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V : STD_LOGIC; signal src1_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_src1_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_src1_cols_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V : STD_LOGIC; signal mask_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_mask_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_mask_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V : STD_LOGIC; signal mask_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_mask_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_mask_cols_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V : STD_LOGIC; signal dmask_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_dmask_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_dmask_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V : STD_LOGIC; signal dmask_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_dmask_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_dmask_cols_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_start : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_done : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_continue : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_idle : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_ready : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_p_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_p_read2 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_p_read6 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_p_read7 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_empty_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_read : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_write : STD_LOGIC; signal image_filter_Block_Mat_exit1222_proc1_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Block_Mat_exit1222_proc1_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0); signal ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V : STD_LOGIC; signal gray_rows_V_full_n : STD_LOGIC; signal ap_reg_ready_gray_rows_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_gray_rows_V_full_n : STD_LOGIC; signal ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V : STD_LOGIC; signal gray_cols_V_full_n : STD_LOGIC; signal ap_reg_ready_gray_cols_V_full_n : STD_LOGIC := '0'; signal ap_sig_ready_gray_cols_V_full_n : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_start : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_done : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_continue : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_idle : STD_LOGIC; signal image_filter_FAST_t_opr_U0_ap_ready : STD_LOGIC; signal image_filter_FAST_t_opr_U0_p_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_FAST_t_opr_U0_p_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_FAST_t_opr_U0_p_src_data_stream_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_FAST_t_opr_U0_p_src_data_stream_V_empty_n : STD_LOGIC; signal image_filter_FAST_t_opr_U0_p_src_data_stream_V_read : STD_LOGIC; signal image_filter_FAST_t_opr_U0_p_mask_data_stream_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_FAST_t_opr_U0_p_mask_data_stream_V_full_n : STD_LOGIC; signal image_filter_FAST_t_opr_U0_p_mask_data_stream_V_write : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_start : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_done : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_continue : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_idle : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_ap_ready : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_p_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Dilate_0_0_1080_1920_U0_p_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_empty_n : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_read : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_full_n : STD_LOGIC; signal image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_write : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_start : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_done : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_continue : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_idle : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_ap_ready : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_empty_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_read : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_empty_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_read : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_empty_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_read : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_empty_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_read : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_full_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_write : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_full_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_write : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_full_n : STD_LOGIC; signal image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_write : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_start : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_done : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_continue : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_idle : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_ap_ready : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0); signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY : STD_LOGIC; signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0); signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_hs_continue : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_U_ap_dummy_ce : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_2_loc_channel1_write : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_2_loc_channel1_empty_n : STD_LOGIC; signal p_src_cols_V_2_loc_channel1_read : STD_LOGIC; signal p_src_cols_V_2_loc_channel_U_ap_dummy_ce : STD_LOGIC; signal p_src_cols_V_2_loc_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_2_loc_channel_write : STD_LOGIC; signal p_src_cols_V_2_loc_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_2_loc_channel_empty_n : STD_LOGIC; signal p_src_cols_V_2_loc_channel_read : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_U_ap_dummy_ce : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_2_loc_channel1_write : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_2_loc_channel1_empty_n : STD_LOGIC; signal p_src_rows_V_2_loc_channel1_read : STD_LOGIC; signal p_src_rows_V_2_loc_channel_U_ap_dummy_ce : STD_LOGIC; signal p_src_rows_V_2_loc_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_2_loc_channel_write : STD_LOGIC; signal p_src_rows_V_2_loc_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_2_loc_channel_empty_n : STD_LOGIC; signal p_src_rows_V_2_loc_channel_read : STD_LOGIC; signal p_dst_cols_V_channel_U_ap_dummy_ce : STD_LOGIC; signal p_dst_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_cols_V_channel_write : STD_LOGIC; signal p_dst_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_cols_V_channel_empty_n : STD_LOGIC; signal p_dst_cols_V_channel_read : STD_LOGIC; signal p_dst_cols_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_cols_V_write : STD_LOGIC; signal p_dst_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_cols_V_empty_n : STD_LOGIC; signal p_dst_cols_V_read : STD_LOGIC; signal p_dst_rows_V_channel_U_ap_dummy_ce : STD_LOGIC; signal p_dst_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_rows_V_channel_write : STD_LOGIC; signal p_dst_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_rows_V_channel_empty_n : STD_LOGIC; signal p_dst_rows_V_channel_read : STD_LOGIC; signal p_dst_rows_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_rows_V_write : STD_LOGIC; signal p_dst_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_dst_rows_V_empty_n : STD_LOGIC; signal p_dst_rows_V_read : STD_LOGIC; signal p_src_cols_V_channel_U_ap_dummy_ce : STD_LOGIC; signal p_src_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_channel_write : STD_LOGIC; signal p_src_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_channel_empty_n : STD_LOGIC; signal p_src_cols_V_channel_read : STD_LOGIC; signal p_src_rows_V_channel_U_ap_dummy_ce : STD_LOGIC; signal p_src_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_channel_write : STD_LOGIC; signal p_src_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_channel_empty_n : STD_LOGIC; signal p_src_rows_V_channel_read : STD_LOGIC; signal p_src_rows_V_channel1_U_ap_dummy_ce : STD_LOGIC; signal p_src_rows_V_channel1_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_channel1_write : STD_LOGIC; signal p_src_rows_V_channel1_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_rows_V_channel1_empty_n : STD_LOGIC; signal p_src_rows_V_channel1_read : STD_LOGIC; signal p_src_cols_V_channel1_U_ap_dummy_ce : STD_LOGIC; signal p_src_cols_V_channel1_din : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_channel1_write : STD_LOGIC; signal p_src_cols_V_channel1_dout : STD_LOGIC_VECTOR (11 downto 0); signal p_src_cols_V_channel1_empty_n : STD_LOGIC; signal p_src_cols_V_channel1_read : STD_LOGIC; signal p_src_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal p_src_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_0_V_full_n : STD_LOGIC; signal p_src_data_stream_0_V_write : STD_LOGIC; signal p_src_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_0_V_empty_n : STD_LOGIC; signal p_src_data_stream_0_V_read : STD_LOGIC; signal p_src_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC; signal p_src_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_1_V_full_n : STD_LOGIC; signal p_src_data_stream_1_V_write : STD_LOGIC; signal p_src_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_1_V_empty_n : STD_LOGIC; signal p_src_data_stream_1_V_read : STD_LOGIC; signal p_src_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC; signal p_src_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_2_V_full_n : STD_LOGIC; signal p_src_data_stream_2_V_write : STD_LOGIC; signal p_src_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_src_data_stream_2_V_empty_n : STD_LOGIC; signal p_src_data_stream_2_V_read : STD_LOGIC; signal src0_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal src0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_0_V_full_n : STD_LOGIC; signal src0_data_stream_0_V_write : STD_LOGIC; signal src0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_0_V_empty_n : STD_LOGIC; signal src0_data_stream_0_V_read : STD_LOGIC; signal src0_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC; signal src0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_1_V_full_n : STD_LOGIC; signal src0_data_stream_1_V_write : STD_LOGIC; signal src0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_1_V_empty_n : STD_LOGIC; signal src0_data_stream_1_V_read : STD_LOGIC; signal src0_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC; signal src0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_2_V_full_n : STD_LOGIC; signal src0_data_stream_2_V_write : STD_LOGIC; signal src0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src0_data_stream_2_V_empty_n : STD_LOGIC; signal src0_data_stream_2_V_read : STD_LOGIC; signal src1_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal src1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_0_V_full_n : STD_LOGIC; signal src1_data_stream_0_V_write : STD_LOGIC; signal src1_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_0_V_empty_n : STD_LOGIC; signal src1_data_stream_0_V_read : STD_LOGIC; signal src1_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC; signal src1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_1_V_full_n : STD_LOGIC; signal src1_data_stream_1_V_write : STD_LOGIC; signal src1_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_1_V_empty_n : STD_LOGIC; signal src1_data_stream_1_V_read : STD_LOGIC; signal src1_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC; signal src1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_2_V_full_n : STD_LOGIC; signal src1_data_stream_2_V_write : STD_LOGIC; signal src1_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal src1_data_stream_2_V_empty_n : STD_LOGIC; signal src1_data_stream_2_V_read : STD_LOGIC; signal src0_rows_V_U_ap_dummy_ce : STD_LOGIC; signal src0_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal src0_rows_V_write : STD_LOGIC; signal src0_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal src0_rows_V_empty_n : STD_LOGIC; signal src0_rows_V_read : STD_LOGIC; signal src0_cols_V_U_ap_dummy_ce : STD_LOGIC; signal src0_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal src0_cols_V_write : STD_LOGIC; signal src0_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal src0_cols_V_empty_n : STD_LOGIC; signal src0_cols_V_read : STD_LOGIC; signal src1_rows_V_U_ap_dummy_ce : STD_LOGIC; signal src1_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal src1_rows_V_write : STD_LOGIC; signal src1_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal src1_rows_V_empty_n : STD_LOGIC; signal src1_rows_V_read : STD_LOGIC; signal src1_cols_V_U_ap_dummy_ce : STD_LOGIC; signal src1_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal src1_cols_V_write : STD_LOGIC; signal src1_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal src1_cols_V_empty_n : STD_LOGIC; signal src1_cols_V_read : STD_LOGIC; signal mask_rows_V_U_ap_dummy_ce : STD_LOGIC; signal mask_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal mask_rows_V_write : STD_LOGIC; signal mask_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal mask_rows_V_empty_n : STD_LOGIC; signal mask_rows_V_read : STD_LOGIC; signal mask_cols_V_U_ap_dummy_ce : STD_LOGIC; signal mask_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal mask_cols_V_write : STD_LOGIC; signal mask_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal mask_cols_V_empty_n : STD_LOGIC; signal mask_cols_V_read : STD_LOGIC; signal dmask_rows_V_U_ap_dummy_ce : STD_LOGIC; signal dmask_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal dmask_rows_V_write : STD_LOGIC; signal dmask_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal dmask_rows_V_empty_n : STD_LOGIC; signal dmask_rows_V_read : STD_LOGIC; signal dmask_cols_V_U_ap_dummy_ce : STD_LOGIC; signal dmask_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal dmask_cols_V_write : STD_LOGIC; signal dmask_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal dmask_cols_V_empty_n : STD_LOGIC; signal dmask_cols_V_read : STD_LOGIC; signal gray_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal gray_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal gray_data_stream_0_V_full_n : STD_LOGIC; signal gray_data_stream_0_V_write : STD_LOGIC; signal gray_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal gray_data_stream_0_V_empty_n : STD_LOGIC; signal gray_data_stream_0_V_read : STD_LOGIC; signal gray_rows_V_U_ap_dummy_ce : STD_LOGIC; signal gray_rows_V_din : STD_LOGIC_VECTOR (11 downto 0); signal gray_rows_V_write : STD_LOGIC; signal gray_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal gray_rows_V_empty_n : STD_LOGIC; signal gray_rows_V_read : STD_LOGIC; signal gray_cols_V_U_ap_dummy_ce : STD_LOGIC; signal gray_cols_V_din : STD_LOGIC_VECTOR (11 downto 0); signal gray_cols_V_write : STD_LOGIC; signal gray_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0); signal gray_cols_V_empty_n : STD_LOGIC; signal gray_cols_V_read : STD_LOGIC; signal mask_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal mask_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal mask_data_stream_0_V_full_n : STD_LOGIC; signal mask_data_stream_0_V_write : STD_LOGIC; signal mask_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal mask_data_stream_0_V_empty_n : STD_LOGIC; signal mask_data_stream_0_V_read : STD_LOGIC; signal dmask_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal dmask_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal dmask_data_stream_0_V_full_n : STD_LOGIC; signal dmask_data_stream_0_V_write : STD_LOGIC; signal dmask_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal dmask_data_stream_0_V_empty_n : STD_LOGIC; signal dmask_data_stream_0_V_read : STD_LOGIC; signal p_dst_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_0_V_full_n : STD_LOGIC; signal p_dst_data_stream_0_V_write : STD_LOGIC; signal p_dst_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_0_V_empty_n : STD_LOGIC; signal p_dst_data_stream_0_V_read : STD_LOGIC; signal p_dst_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_1_V_full_n : STD_LOGIC; signal p_dst_data_stream_1_V_write : STD_LOGIC; signal p_dst_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_1_V_empty_n : STD_LOGIC; signal p_dst_data_stream_1_V_read : STD_LOGIC; signal p_dst_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC; signal p_dst_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_2_V_full_n : STD_LOGIC; signal p_dst_data_stream_2_V_write : STD_LOGIC; signal p_dst_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0); signal p_dst_data_stream_2_V_empty_n : STD_LOGIC; signal p_dst_data_stream_2_V_read : STD_LOGIC; signal ap_reg_procdone_image_filter_Block_proc_U0 : STD_LOGIC := '0'; signal ap_sig_hs_done : STD_LOGIC; signal ap_reg_procdone_image_filter_AXIvideo2Mat_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_FAST_t_opr_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 : STD_LOGIC := '0'; signal ap_reg_procdone_image_filter_Mat2AXIvideo_U0 : STD_LOGIC := '0'; signal ap_CS : STD_LOGIC; signal ap_sig_top_allready : STD_LOGIC; component image_filter_Block_proc IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; rows : IN STD_LOGIC_VECTOR (31 downto 0); cols : IN STD_LOGIC_VECTOR (31 downto 0); ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_4 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_5 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_6 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_7 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_8 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_9 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_10 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_11 : OUT STD_LOGIC_VECTOR (11 downto 0) ); end component; component image_filter_AXIvideo2Mat IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0); INPUT_STREAM_TVALID : IN STD_LOGIC; INPUT_STREAM_TREADY : OUT STD_LOGIC; INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0); INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0); INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0); INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0); img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); img_data_stream_0_V_full_n : IN STD_LOGIC; img_data_stream_0_V_write : OUT STD_LOGIC; img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); img_data_stream_1_V_full_n : IN STD_LOGIC; img_data_stream_1_V_write : OUT STD_LOGIC; img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); img_data_stream_2_V_full_n : IN STD_LOGIC; img_data_stream_2_V_write : OUT STD_LOGIC ); end component; component image_filter_Block_Mat_exit1220_proc1 IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (11 downto 0); p_read2 : IN STD_LOGIC_VECTOR (11 downto 0); p_read16 : IN STD_LOGIC_VECTOR (11 downto 0); p_read17 : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_0_V_empty_n : IN STD_LOGIC; p_src_data_stream_0_V_read : OUT STD_LOGIC; p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_1_V_empty_n : IN STD_LOGIC; p_src_data_stream_1_V_read : OUT STD_LOGIC; p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_2_V_empty_n : IN STD_LOGIC; p_src_data_stream_2_V_read : OUT STD_LOGIC; src0_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_0_V_full_n : IN STD_LOGIC; src0_data_stream_0_V_write : OUT STD_LOGIC; src0_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_1_V_full_n : IN STD_LOGIC; src0_data_stream_1_V_write : OUT STD_LOGIC; src0_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_2_V_full_n : IN STD_LOGIC; src0_data_stream_2_V_write : OUT STD_LOGIC; src1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src1_data_stream_0_V_full_n : IN STD_LOGIC; src1_data_stream_0_V_write : OUT STD_LOGIC; src1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src1_data_stream_1_V_full_n : IN STD_LOGIC; src1_data_stream_1_V_write : OUT STD_LOGIC; src1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); src1_data_stream_2_V_full_n : IN STD_LOGIC; src1_data_stream_2_V_write : OUT STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_4 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_5 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_6 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_7 : OUT STD_LOGIC_VECTOR (11 downto 0) ); end component; component image_filter_Block_Mat_exit1222_proc1 IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_read : IN STD_LOGIC_VECTOR (11 downto 0); p_read2 : IN STD_LOGIC_VECTOR (11 downto 0); p_read6 : IN STD_LOGIC_VECTOR (11 downto 0); p_read7 : IN STD_LOGIC_VECTOR (11 downto 0); src0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_0_V_empty_n : IN STD_LOGIC; src0_data_stream_0_V_read : OUT STD_LOGIC; src0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_1_V_empty_n : IN STD_LOGIC; src0_data_stream_1_V_read : OUT STD_LOGIC; src0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); src0_data_stream_2_V_empty_n : IN STD_LOGIC; src0_data_stream_2_V_read : OUT STD_LOGIC; gray_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); gray_data_stream_0_V_full_n : IN STD_LOGIC; gray_data_stream_0_V_write : OUT STD_LOGIC; ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0); ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0) ); end component; component image_filter_FAST_t_opr IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_V_empty_n : IN STD_LOGIC; p_src_data_stream_V_read : OUT STD_LOGIC; p_mask_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_mask_data_stream_V_full_n : IN STD_LOGIC; p_mask_data_stream_V_write : OUT STD_LOGIC ); end component; component image_filter_Dilate_0_0_1080_1920_s IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_V_empty_n : IN STD_LOGIC; p_src_data_stream_V_read : OUT STD_LOGIC; p_dst_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_V_full_n : IN STD_LOGIC; p_dst_data_stream_V_write : OUT STD_LOGIC ); end component; component image_filter_PaintMask_32_0_1080_1920_s IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_0_V_empty_n : IN STD_LOGIC; p_src_data_stream_0_V_read : OUT STD_LOGIC; p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_1_V_empty_n : IN STD_LOGIC; p_src_data_stream_1_V_read : OUT STD_LOGIC; p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_2_V_empty_n : IN STD_LOGIC; p_src_data_stream_2_V_read : OUT STD_LOGIC; p_mask_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_mask_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_mask_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_mask_data_stream_V_empty_n : IN STD_LOGIC; p_mask_data_stream_V_read : OUT STD_LOGIC; p_dst_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_dst_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_0_V_full_n : IN STD_LOGIC; p_dst_data_stream_0_V_write : OUT STD_LOGIC; p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_1_V_full_n : IN STD_LOGIC; p_dst_data_stream_1_V_write : OUT STD_LOGIC; p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_2_V_full_n : IN STD_LOGIC; p_dst_data_stream_2_V_write : OUT STD_LOGIC ); end component; component image_filter_Mat2AXIvideo IS port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_0_V_empty_n : IN STD_LOGIC; img_data_stream_0_V_read : OUT STD_LOGIC; img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_1_V_empty_n : IN STD_LOGIC; img_data_stream_1_V_read : OUT STD_LOGIC; img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); img_data_stream_2_V_empty_n : IN STD_LOGIC; img_data_stream_2_V_read : OUT STD_LOGIC; OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0); OUTPUT_STREAM_TVALID : OUT STD_LOGIC; OUTPUT_STREAM_TREADY : IN STD_LOGIC; OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0); OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0); OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) ); end component; component FIFO_image_filter_p_src_cols_V_2_loc_channel1 IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_cols_V_2_loc_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_rows_V_2_loc_channel1 IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_rows_V_2_loc_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_cols_V_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_rows_V_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_cols_V_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_rows_V_channel IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_rows_V_channel1 IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_cols_V_channel1 IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_data_stream_1_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_src_data_stream_2_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_data_stream_1_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_data_stream_2_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_data_stream_1_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_data_stream_2_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src0_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_src1_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_mask_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_mask_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_dmask_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_dmask_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_gray_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_gray_rows_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_gray_cols_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (11 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (11 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_mask_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_dmask_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_data_stream_0_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_data_stream_1_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; component FIFO_image_filter_p_dst_data_stream_2_V IS port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_read_ce : IN STD_LOGIC; if_write_ce : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR (7 downto 0); if_full_n : OUT STD_LOGIC; if_write : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR (7 downto 0); if_empty_n : OUT STD_LOGIC; if_read : IN STD_LOGIC ); end component; begin image_filter_Block_proc_U0 : component image_filter_Block_proc port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Block_proc_U0_ap_start, ap_done => image_filter_Block_proc_U0_ap_done, ap_continue => image_filter_Block_proc_U0_ap_continue, ap_idle => image_filter_Block_proc_U0_ap_idle, ap_ready => image_filter_Block_proc_U0_ap_ready, rows => image_filter_Block_proc_U0_rows, cols => image_filter_Block_proc_U0_cols, ap_return_0 => image_filter_Block_proc_U0_ap_return_0, ap_return_1 => image_filter_Block_proc_U0_ap_return_1, ap_return_2 => image_filter_Block_proc_U0_ap_return_2, ap_return_3 => image_filter_Block_proc_U0_ap_return_3, ap_return_4 => image_filter_Block_proc_U0_ap_return_4, ap_return_5 => image_filter_Block_proc_U0_ap_return_5, ap_return_6 => image_filter_Block_proc_U0_ap_return_6, ap_return_7 => image_filter_Block_proc_U0_ap_return_7, ap_return_8 => image_filter_Block_proc_U0_ap_return_8, ap_return_9 => image_filter_Block_proc_U0_ap_return_9, ap_return_10 => image_filter_Block_proc_U0_ap_return_10, ap_return_11 => image_filter_Block_proc_U0_ap_return_11); image_filter_AXIvideo2Mat_U0 : component image_filter_AXIvideo2Mat port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_AXIvideo2Mat_U0_ap_start, ap_done => image_filter_AXIvideo2Mat_U0_ap_done, ap_continue => image_filter_AXIvideo2Mat_U0_ap_continue, ap_idle => image_filter_AXIvideo2Mat_U0_ap_idle, ap_ready => image_filter_AXIvideo2Mat_U0_ap_ready, INPUT_STREAM_TDATA => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA, INPUT_STREAM_TVALID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID, INPUT_STREAM_TREADY => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY, INPUT_STREAM_TKEEP => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP, INPUT_STREAM_TSTRB => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB, INPUT_STREAM_TUSER => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER, INPUT_STREAM_TLAST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST, INPUT_STREAM_TID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID, INPUT_STREAM_TDEST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST, img_rows_V_read => image_filter_AXIvideo2Mat_U0_img_rows_V_read, img_cols_V_read => image_filter_AXIvideo2Mat_U0_img_cols_V_read, img_data_stream_0_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din, img_data_stream_0_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n, img_data_stream_0_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write, img_data_stream_1_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din, img_data_stream_1_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n, img_data_stream_1_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write, img_data_stream_2_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din, img_data_stream_2_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n, img_data_stream_2_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write); image_filter_Block_Mat_exit1220_proc1_U0 : component image_filter_Block_Mat_exit1220_proc1 port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Block_Mat_exit1220_proc1_U0_ap_start, ap_done => image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_continue => image_filter_Block_Mat_exit1220_proc1_U0_ap_continue, ap_idle => image_filter_Block_Mat_exit1220_proc1_U0_ap_idle, ap_ready => image_filter_Block_Mat_exit1220_proc1_U0_ap_ready, p_read => image_filter_Block_Mat_exit1220_proc1_U0_p_read, p_read2 => image_filter_Block_Mat_exit1220_proc1_U0_p_read2, p_read16 => image_filter_Block_Mat_exit1220_proc1_U0_p_read16, p_read17 => image_filter_Block_Mat_exit1220_proc1_U0_p_read17, p_src_data_stream_0_V_dout => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_dout, p_src_data_stream_0_V_empty_n => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_empty_n, p_src_data_stream_0_V_read => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_read, p_src_data_stream_1_V_dout => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_dout, p_src_data_stream_1_V_empty_n => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_empty_n, p_src_data_stream_1_V_read => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_read, p_src_data_stream_2_V_dout => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_dout, p_src_data_stream_2_V_empty_n => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_empty_n, p_src_data_stream_2_V_read => image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_read, src0_data_stream_0_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_din, src0_data_stream_0_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_full_n, src0_data_stream_0_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_write, src0_data_stream_1_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_din, src0_data_stream_1_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_full_n, src0_data_stream_1_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_write, src0_data_stream_2_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_din, src0_data_stream_2_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_full_n, src0_data_stream_2_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_write, src1_data_stream_0_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_din, src1_data_stream_0_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_full_n, src1_data_stream_0_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_write, src1_data_stream_1_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_din, src1_data_stream_1_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_full_n, src1_data_stream_1_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_write, src1_data_stream_2_V_din => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_din, src1_data_stream_2_V_full_n => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_full_n, src1_data_stream_2_V_write => image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_write, ap_return_0 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_0, ap_return_1 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_1, ap_return_2 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_2, ap_return_3 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_3, ap_return_4 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_4, ap_return_5 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_5, ap_return_6 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_6, ap_return_7 => image_filter_Block_Mat_exit1220_proc1_U0_ap_return_7); image_filter_Block_Mat_exit1222_proc1_U0 : component image_filter_Block_Mat_exit1222_proc1 port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Block_Mat_exit1222_proc1_U0_ap_start, ap_done => image_filter_Block_Mat_exit1222_proc1_U0_ap_done, ap_continue => image_filter_Block_Mat_exit1222_proc1_U0_ap_continue, ap_idle => image_filter_Block_Mat_exit1222_proc1_U0_ap_idle, ap_ready => image_filter_Block_Mat_exit1222_proc1_U0_ap_ready, p_read => image_filter_Block_Mat_exit1222_proc1_U0_p_read, p_read2 => image_filter_Block_Mat_exit1222_proc1_U0_p_read2, p_read6 => image_filter_Block_Mat_exit1222_proc1_U0_p_read6, p_read7 => image_filter_Block_Mat_exit1222_proc1_U0_p_read7, src0_data_stream_0_V_dout => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_dout, src0_data_stream_0_V_empty_n => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_empty_n, src0_data_stream_0_V_read => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_read, src0_data_stream_1_V_dout => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_dout, src0_data_stream_1_V_empty_n => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_empty_n, src0_data_stream_1_V_read => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_read, src0_data_stream_2_V_dout => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_dout, src0_data_stream_2_V_empty_n => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_empty_n, src0_data_stream_2_V_read => image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_read, gray_data_stream_0_V_din => image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_din, gray_data_stream_0_V_full_n => image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_full_n, gray_data_stream_0_V_write => image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_write, ap_return_0 => image_filter_Block_Mat_exit1222_proc1_U0_ap_return_0, ap_return_1 => image_filter_Block_Mat_exit1222_proc1_U0_ap_return_1); image_filter_FAST_t_opr_U0 : component image_filter_FAST_t_opr port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_FAST_t_opr_U0_ap_start, ap_done => image_filter_FAST_t_opr_U0_ap_done, ap_continue => image_filter_FAST_t_opr_U0_ap_continue, ap_idle => image_filter_FAST_t_opr_U0_ap_idle, ap_ready => image_filter_FAST_t_opr_U0_ap_ready, p_src_rows_V_read => image_filter_FAST_t_opr_U0_p_src_rows_V_read, p_src_cols_V_read => image_filter_FAST_t_opr_U0_p_src_cols_V_read, p_src_data_stream_V_dout => image_filter_FAST_t_opr_U0_p_src_data_stream_V_dout, p_src_data_stream_V_empty_n => image_filter_FAST_t_opr_U0_p_src_data_stream_V_empty_n, p_src_data_stream_V_read => image_filter_FAST_t_opr_U0_p_src_data_stream_V_read, p_mask_data_stream_V_din => image_filter_FAST_t_opr_U0_p_mask_data_stream_V_din, p_mask_data_stream_V_full_n => image_filter_FAST_t_opr_U0_p_mask_data_stream_V_full_n, p_mask_data_stream_V_write => image_filter_FAST_t_opr_U0_p_mask_data_stream_V_write); image_filter_Dilate_0_0_1080_1920_U0 : component image_filter_Dilate_0_0_1080_1920_s port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Dilate_0_0_1080_1920_U0_ap_start, ap_done => image_filter_Dilate_0_0_1080_1920_U0_ap_done, ap_continue => image_filter_Dilate_0_0_1080_1920_U0_ap_continue, ap_idle => image_filter_Dilate_0_0_1080_1920_U0_ap_idle, ap_ready => image_filter_Dilate_0_0_1080_1920_U0_ap_ready, p_src_rows_V_read => image_filter_Dilate_0_0_1080_1920_U0_p_src_rows_V_read, p_src_cols_V_read => image_filter_Dilate_0_0_1080_1920_U0_p_src_cols_V_read, p_src_data_stream_V_dout => image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_dout, p_src_data_stream_V_empty_n => image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_empty_n, p_src_data_stream_V_read => image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_read, p_dst_data_stream_V_din => image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_din, p_dst_data_stream_V_full_n => image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_full_n, p_dst_data_stream_V_write => image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_write); image_filter_PaintMask_32_0_1080_1920_U0 : component image_filter_PaintMask_32_0_1080_1920_s port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_PaintMask_32_0_1080_1920_U0_ap_start, ap_done => image_filter_PaintMask_32_0_1080_1920_U0_ap_done, ap_continue => image_filter_PaintMask_32_0_1080_1920_U0_ap_continue, ap_idle => image_filter_PaintMask_32_0_1080_1920_U0_ap_idle, ap_ready => image_filter_PaintMask_32_0_1080_1920_U0_ap_ready, p_src_rows_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_rows_V_read, p_src_cols_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_cols_V_read, p_src_data_stream_0_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_dout, p_src_data_stream_0_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_empty_n, p_src_data_stream_0_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_read, p_src_data_stream_1_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_dout, p_src_data_stream_1_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_empty_n, p_src_data_stream_1_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_read, p_src_data_stream_2_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_dout, p_src_data_stream_2_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_empty_n, p_src_data_stream_2_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_read, p_mask_rows_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_rows_V_read, p_mask_cols_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_cols_V_read, p_mask_data_stream_V_dout => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_dout, p_mask_data_stream_V_empty_n => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_empty_n, p_mask_data_stream_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_read, p_dst_rows_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_rows_V_read, p_dst_cols_V_read => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_cols_V_read, p_dst_data_stream_0_V_din => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_din, p_dst_data_stream_0_V_full_n => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_full_n, p_dst_data_stream_0_V_write => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_write, p_dst_data_stream_1_V_din => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_din, p_dst_data_stream_1_V_full_n => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_full_n, p_dst_data_stream_1_V_write => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_write, p_dst_data_stream_2_V_din => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_din, p_dst_data_stream_2_V_full_n => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_full_n, p_dst_data_stream_2_V_write => image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_write); image_filter_Mat2AXIvideo_U0 : component image_filter_Mat2AXIvideo port map ( ap_clk => ap_clk, ap_rst => ap_rst_n_inv, ap_start => image_filter_Mat2AXIvideo_U0_ap_start, ap_done => image_filter_Mat2AXIvideo_U0_ap_done, ap_continue => image_filter_Mat2AXIvideo_U0_ap_continue, ap_idle => image_filter_Mat2AXIvideo_U0_ap_idle, ap_ready => image_filter_Mat2AXIvideo_U0_ap_ready, img_rows_V_read => image_filter_Mat2AXIvideo_U0_img_rows_V_read, img_cols_V_read => image_filter_Mat2AXIvideo_U0_img_cols_V_read, img_data_stream_0_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout, img_data_stream_0_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n, img_data_stream_0_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read, img_data_stream_1_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout, img_data_stream_1_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n, img_data_stream_1_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read, img_data_stream_2_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout, img_data_stream_2_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n, img_data_stream_2_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read, OUTPUT_STREAM_TDATA => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA, OUTPUT_STREAM_TVALID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID, OUTPUT_STREAM_TREADY => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY, OUTPUT_STREAM_TKEEP => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP, OUTPUT_STREAM_TSTRB => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB, OUTPUT_STREAM_TUSER => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER, OUTPUT_STREAM_TLAST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST, OUTPUT_STREAM_TID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID, OUTPUT_STREAM_TDEST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST); p_src_cols_V_2_loc_channel1_U : component FIFO_image_filter_p_src_cols_V_2_loc_channel1 port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_cols_V_2_loc_channel1_U_ap_dummy_ce, if_write_ce => p_src_cols_V_2_loc_channel1_U_ap_dummy_ce, if_din => p_src_cols_V_2_loc_channel1_din, if_full_n => p_src_cols_V_2_loc_channel1_full_n, if_write => p_src_cols_V_2_loc_channel1_write, if_dout => p_src_cols_V_2_loc_channel1_dout, if_empty_n => p_src_cols_V_2_loc_channel1_empty_n, if_read => p_src_cols_V_2_loc_channel1_read); p_src_cols_V_2_loc_channel_U : component FIFO_image_filter_p_src_cols_V_2_loc_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_cols_V_2_loc_channel_U_ap_dummy_ce, if_write_ce => p_src_cols_V_2_loc_channel_U_ap_dummy_ce, if_din => p_src_cols_V_2_loc_channel_din, if_full_n => p_src_cols_V_2_loc_channel_full_n, if_write => p_src_cols_V_2_loc_channel_write, if_dout => p_src_cols_V_2_loc_channel_dout, if_empty_n => p_src_cols_V_2_loc_channel_empty_n, if_read => p_src_cols_V_2_loc_channel_read); p_src_rows_V_2_loc_channel1_U : component FIFO_image_filter_p_src_rows_V_2_loc_channel1 port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_rows_V_2_loc_channel1_U_ap_dummy_ce, if_write_ce => p_src_rows_V_2_loc_channel1_U_ap_dummy_ce, if_din => p_src_rows_V_2_loc_channel1_din, if_full_n => p_src_rows_V_2_loc_channel1_full_n, if_write => p_src_rows_V_2_loc_channel1_write, if_dout => p_src_rows_V_2_loc_channel1_dout, if_empty_n => p_src_rows_V_2_loc_channel1_empty_n, if_read => p_src_rows_V_2_loc_channel1_read); p_src_rows_V_2_loc_channel_U : component FIFO_image_filter_p_src_rows_V_2_loc_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_rows_V_2_loc_channel_U_ap_dummy_ce, if_write_ce => p_src_rows_V_2_loc_channel_U_ap_dummy_ce, if_din => p_src_rows_V_2_loc_channel_din, if_full_n => p_src_rows_V_2_loc_channel_full_n, if_write => p_src_rows_V_2_loc_channel_write, if_dout => p_src_rows_V_2_loc_channel_dout, if_empty_n => p_src_rows_V_2_loc_channel_empty_n, if_read => p_src_rows_V_2_loc_channel_read); p_dst_cols_V_channel_U : component FIFO_image_filter_p_dst_cols_V_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_cols_V_channel_U_ap_dummy_ce, if_write_ce => p_dst_cols_V_channel_U_ap_dummy_ce, if_din => p_dst_cols_V_channel_din, if_full_n => p_dst_cols_V_channel_full_n, if_write => p_dst_cols_V_channel_write, if_dout => p_dst_cols_V_channel_dout, if_empty_n => p_dst_cols_V_channel_empty_n, if_read => p_dst_cols_V_channel_read); p_dst_cols_V_U : component FIFO_image_filter_p_dst_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_cols_V_U_ap_dummy_ce, if_write_ce => p_dst_cols_V_U_ap_dummy_ce, if_din => p_dst_cols_V_din, if_full_n => p_dst_cols_V_full_n, if_write => p_dst_cols_V_write, if_dout => p_dst_cols_V_dout, if_empty_n => p_dst_cols_V_empty_n, if_read => p_dst_cols_V_read); p_dst_rows_V_channel_U : component FIFO_image_filter_p_dst_rows_V_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_rows_V_channel_U_ap_dummy_ce, if_write_ce => p_dst_rows_V_channel_U_ap_dummy_ce, if_din => p_dst_rows_V_channel_din, if_full_n => p_dst_rows_V_channel_full_n, if_write => p_dst_rows_V_channel_write, if_dout => p_dst_rows_V_channel_dout, if_empty_n => p_dst_rows_V_channel_empty_n, if_read => p_dst_rows_V_channel_read); p_dst_rows_V_U : component FIFO_image_filter_p_dst_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_rows_V_U_ap_dummy_ce, if_write_ce => p_dst_rows_V_U_ap_dummy_ce, if_din => p_dst_rows_V_din, if_full_n => p_dst_rows_V_full_n, if_write => p_dst_rows_V_write, if_dout => p_dst_rows_V_dout, if_empty_n => p_dst_rows_V_empty_n, if_read => p_dst_rows_V_read); p_src_cols_V_channel_U : component FIFO_image_filter_p_src_cols_V_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_cols_V_channel_U_ap_dummy_ce, if_write_ce => p_src_cols_V_channel_U_ap_dummy_ce, if_din => p_src_cols_V_channel_din, if_full_n => p_src_cols_V_channel_full_n, if_write => p_src_cols_V_channel_write, if_dout => p_src_cols_V_channel_dout, if_empty_n => p_src_cols_V_channel_empty_n, if_read => p_src_cols_V_channel_read); p_src_rows_V_channel_U : component FIFO_image_filter_p_src_rows_V_channel port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_rows_V_channel_U_ap_dummy_ce, if_write_ce => p_src_rows_V_channel_U_ap_dummy_ce, if_din => p_src_rows_V_channel_din, if_full_n => p_src_rows_V_channel_full_n, if_write => p_src_rows_V_channel_write, if_dout => p_src_rows_V_channel_dout, if_empty_n => p_src_rows_V_channel_empty_n, if_read => p_src_rows_V_channel_read); p_src_rows_V_channel1_U : component FIFO_image_filter_p_src_rows_V_channel1 port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_rows_V_channel1_U_ap_dummy_ce, if_write_ce => p_src_rows_V_channel1_U_ap_dummy_ce, if_din => p_src_rows_V_channel1_din, if_full_n => p_src_rows_V_channel1_full_n, if_write => p_src_rows_V_channel1_write, if_dout => p_src_rows_V_channel1_dout, if_empty_n => p_src_rows_V_channel1_empty_n, if_read => p_src_rows_V_channel1_read); p_src_cols_V_channel1_U : component FIFO_image_filter_p_src_cols_V_channel1 port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_cols_V_channel1_U_ap_dummy_ce, if_write_ce => p_src_cols_V_channel1_U_ap_dummy_ce, if_din => p_src_cols_V_channel1_din, if_full_n => p_src_cols_V_channel1_full_n, if_write => p_src_cols_V_channel1_write, if_dout => p_src_cols_V_channel1_dout, if_empty_n => p_src_cols_V_channel1_empty_n, if_read => p_src_cols_V_channel1_read); p_src_data_stream_0_V_U : component FIFO_image_filter_p_src_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_data_stream_0_V_U_ap_dummy_ce, if_write_ce => p_src_data_stream_0_V_U_ap_dummy_ce, if_din => p_src_data_stream_0_V_din, if_full_n => p_src_data_stream_0_V_full_n, if_write => p_src_data_stream_0_V_write, if_dout => p_src_data_stream_0_V_dout, if_empty_n => p_src_data_stream_0_V_empty_n, if_read => p_src_data_stream_0_V_read); p_src_data_stream_1_V_U : component FIFO_image_filter_p_src_data_stream_1_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_data_stream_1_V_U_ap_dummy_ce, if_write_ce => p_src_data_stream_1_V_U_ap_dummy_ce, if_din => p_src_data_stream_1_V_din, if_full_n => p_src_data_stream_1_V_full_n, if_write => p_src_data_stream_1_V_write, if_dout => p_src_data_stream_1_V_dout, if_empty_n => p_src_data_stream_1_V_empty_n, if_read => p_src_data_stream_1_V_read); p_src_data_stream_2_V_U : component FIFO_image_filter_p_src_data_stream_2_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_src_data_stream_2_V_U_ap_dummy_ce, if_write_ce => p_src_data_stream_2_V_U_ap_dummy_ce, if_din => p_src_data_stream_2_V_din, if_full_n => p_src_data_stream_2_V_full_n, if_write => p_src_data_stream_2_V_write, if_dout => p_src_data_stream_2_V_dout, if_empty_n => p_src_data_stream_2_V_empty_n, if_read => p_src_data_stream_2_V_read); src0_data_stream_0_V_U : component FIFO_image_filter_src0_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_data_stream_0_V_U_ap_dummy_ce, if_write_ce => src0_data_stream_0_V_U_ap_dummy_ce, if_din => src0_data_stream_0_V_din, if_full_n => src0_data_stream_0_V_full_n, if_write => src0_data_stream_0_V_write, if_dout => src0_data_stream_0_V_dout, if_empty_n => src0_data_stream_0_V_empty_n, if_read => src0_data_stream_0_V_read); src0_data_stream_1_V_U : component FIFO_image_filter_src0_data_stream_1_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_data_stream_1_V_U_ap_dummy_ce, if_write_ce => src0_data_stream_1_V_U_ap_dummy_ce, if_din => src0_data_stream_1_V_din, if_full_n => src0_data_stream_1_V_full_n, if_write => src0_data_stream_1_V_write, if_dout => src0_data_stream_1_V_dout, if_empty_n => src0_data_stream_1_V_empty_n, if_read => src0_data_stream_1_V_read); src0_data_stream_2_V_U : component FIFO_image_filter_src0_data_stream_2_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_data_stream_2_V_U_ap_dummy_ce, if_write_ce => src0_data_stream_2_V_U_ap_dummy_ce, if_din => src0_data_stream_2_V_din, if_full_n => src0_data_stream_2_V_full_n, if_write => src0_data_stream_2_V_write, if_dout => src0_data_stream_2_V_dout, if_empty_n => src0_data_stream_2_V_empty_n, if_read => src0_data_stream_2_V_read); src1_data_stream_0_V_U : component FIFO_image_filter_src1_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_data_stream_0_V_U_ap_dummy_ce, if_write_ce => src1_data_stream_0_V_U_ap_dummy_ce, if_din => src1_data_stream_0_V_din, if_full_n => src1_data_stream_0_V_full_n, if_write => src1_data_stream_0_V_write, if_dout => src1_data_stream_0_V_dout, if_empty_n => src1_data_stream_0_V_empty_n, if_read => src1_data_stream_0_V_read); src1_data_stream_1_V_U : component FIFO_image_filter_src1_data_stream_1_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_data_stream_1_V_U_ap_dummy_ce, if_write_ce => src1_data_stream_1_V_U_ap_dummy_ce, if_din => src1_data_stream_1_V_din, if_full_n => src1_data_stream_1_V_full_n, if_write => src1_data_stream_1_V_write, if_dout => src1_data_stream_1_V_dout, if_empty_n => src1_data_stream_1_V_empty_n, if_read => src1_data_stream_1_V_read); src1_data_stream_2_V_U : component FIFO_image_filter_src1_data_stream_2_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_data_stream_2_V_U_ap_dummy_ce, if_write_ce => src1_data_stream_2_V_U_ap_dummy_ce, if_din => src1_data_stream_2_V_din, if_full_n => src1_data_stream_2_V_full_n, if_write => src1_data_stream_2_V_write, if_dout => src1_data_stream_2_V_dout, if_empty_n => src1_data_stream_2_V_empty_n, if_read => src1_data_stream_2_V_read); src0_rows_V_U : component FIFO_image_filter_src0_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_rows_V_U_ap_dummy_ce, if_write_ce => src0_rows_V_U_ap_dummy_ce, if_din => src0_rows_V_din, if_full_n => src0_rows_V_full_n, if_write => src0_rows_V_write, if_dout => src0_rows_V_dout, if_empty_n => src0_rows_V_empty_n, if_read => src0_rows_V_read); src0_cols_V_U : component FIFO_image_filter_src0_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src0_cols_V_U_ap_dummy_ce, if_write_ce => src0_cols_V_U_ap_dummy_ce, if_din => src0_cols_V_din, if_full_n => src0_cols_V_full_n, if_write => src0_cols_V_write, if_dout => src0_cols_V_dout, if_empty_n => src0_cols_V_empty_n, if_read => src0_cols_V_read); src1_rows_V_U : component FIFO_image_filter_src1_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_rows_V_U_ap_dummy_ce, if_write_ce => src1_rows_V_U_ap_dummy_ce, if_din => src1_rows_V_din, if_full_n => src1_rows_V_full_n, if_write => src1_rows_V_write, if_dout => src1_rows_V_dout, if_empty_n => src1_rows_V_empty_n, if_read => src1_rows_V_read); src1_cols_V_U : component FIFO_image_filter_src1_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => src1_cols_V_U_ap_dummy_ce, if_write_ce => src1_cols_V_U_ap_dummy_ce, if_din => src1_cols_V_din, if_full_n => src1_cols_V_full_n, if_write => src1_cols_V_write, if_dout => src1_cols_V_dout, if_empty_n => src1_cols_V_empty_n, if_read => src1_cols_V_read); mask_rows_V_U : component FIFO_image_filter_mask_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => mask_rows_V_U_ap_dummy_ce, if_write_ce => mask_rows_V_U_ap_dummy_ce, if_din => mask_rows_V_din, if_full_n => mask_rows_V_full_n, if_write => mask_rows_V_write, if_dout => mask_rows_V_dout, if_empty_n => mask_rows_V_empty_n, if_read => mask_rows_V_read); mask_cols_V_U : component FIFO_image_filter_mask_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => mask_cols_V_U_ap_dummy_ce, if_write_ce => mask_cols_V_U_ap_dummy_ce, if_din => mask_cols_V_din, if_full_n => mask_cols_V_full_n, if_write => mask_cols_V_write, if_dout => mask_cols_V_dout, if_empty_n => mask_cols_V_empty_n, if_read => mask_cols_V_read); dmask_rows_V_U : component FIFO_image_filter_dmask_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => dmask_rows_V_U_ap_dummy_ce, if_write_ce => dmask_rows_V_U_ap_dummy_ce, if_din => dmask_rows_V_din, if_full_n => dmask_rows_V_full_n, if_write => dmask_rows_V_write, if_dout => dmask_rows_V_dout, if_empty_n => dmask_rows_V_empty_n, if_read => dmask_rows_V_read); dmask_cols_V_U : component FIFO_image_filter_dmask_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => dmask_cols_V_U_ap_dummy_ce, if_write_ce => dmask_cols_V_U_ap_dummy_ce, if_din => dmask_cols_V_din, if_full_n => dmask_cols_V_full_n, if_write => dmask_cols_V_write, if_dout => dmask_cols_V_dout, if_empty_n => dmask_cols_V_empty_n, if_read => dmask_cols_V_read); gray_data_stream_0_V_U : component FIFO_image_filter_gray_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => gray_data_stream_0_V_U_ap_dummy_ce, if_write_ce => gray_data_stream_0_V_U_ap_dummy_ce, if_din => gray_data_stream_0_V_din, if_full_n => gray_data_stream_0_V_full_n, if_write => gray_data_stream_0_V_write, if_dout => gray_data_stream_0_V_dout, if_empty_n => gray_data_stream_0_V_empty_n, if_read => gray_data_stream_0_V_read); gray_rows_V_U : component FIFO_image_filter_gray_rows_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => gray_rows_V_U_ap_dummy_ce, if_write_ce => gray_rows_V_U_ap_dummy_ce, if_din => gray_rows_V_din, if_full_n => gray_rows_V_full_n, if_write => gray_rows_V_write, if_dout => gray_rows_V_dout, if_empty_n => gray_rows_V_empty_n, if_read => gray_rows_V_read); gray_cols_V_U : component FIFO_image_filter_gray_cols_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => gray_cols_V_U_ap_dummy_ce, if_write_ce => gray_cols_V_U_ap_dummy_ce, if_din => gray_cols_V_din, if_full_n => gray_cols_V_full_n, if_write => gray_cols_V_write, if_dout => gray_cols_V_dout, if_empty_n => gray_cols_V_empty_n, if_read => gray_cols_V_read); mask_data_stream_0_V_U : component FIFO_image_filter_mask_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => mask_data_stream_0_V_U_ap_dummy_ce, if_write_ce => mask_data_stream_0_V_U_ap_dummy_ce, if_din => mask_data_stream_0_V_din, if_full_n => mask_data_stream_0_V_full_n, if_write => mask_data_stream_0_V_write, if_dout => mask_data_stream_0_V_dout, if_empty_n => mask_data_stream_0_V_empty_n, if_read => mask_data_stream_0_V_read); dmask_data_stream_0_V_U : component FIFO_image_filter_dmask_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => dmask_data_stream_0_V_U_ap_dummy_ce, if_write_ce => dmask_data_stream_0_V_U_ap_dummy_ce, if_din => dmask_data_stream_0_V_din, if_full_n => dmask_data_stream_0_V_full_n, if_write => dmask_data_stream_0_V_write, if_dout => dmask_data_stream_0_V_dout, if_empty_n => dmask_data_stream_0_V_empty_n, if_read => dmask_data_stream_0_V_read); p_dst_data_stream_0_V_U : component FIFO_image_filter_p_dst_data_stream_0_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_data_stream_0_V_U_ap_dummy_ce, if_write_ce => p_dst_data_stream_0_V_U_ap_dummy_ce, if_din => p_dst_data_stream_0_V_din, if_full_n => p_dst_data_stream_0_V_full_n, if_write => p_dst_data_stream_0_V_write, if_dout => p_dst_data_stream_0_V_dout, if_empty_n => p_dst_data_stream_0_V_empty_n, if_read => p_dst_data_stream_0_V_read); p_dst_data_stream_1_V_U : component FIFO_image_filter_p_dst_data_stream_1_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_data_stream_1_V_U_ap_dummy_ce, if_write_ce => p_dst_data_stream_1_V_U_ap_dummy_ce, if_din => p_dst_data_stream_1_V_din, if_full_n => p_dst_data_stream_1_V_full_n, if_write => p_dst_data_stream_1_V_write, if_dout => p_dst_data_stream_1_V_dout, if_empty_n => p_dst_data_stream_1_V_empty_n, if_read => p_dst_data_stream_1_V_read); p_dst_data_stream_2_V_U : component FIFO_image_filter_p_dst_data_stream_2_V port map ( clk => ap_clk, reset => ap_rst_n_inv, if_read_ce => p_dst_data_stream_2_V_U_ap_dummy_ce, if_write_ce => p_dst_data_stream_2_V_U_ap_dummy_ce, if_din => p_dst_data_stream_2_V_din, if_full_n => p_dst_data_stream_2_V_full_n, if_write => p_dst_data_stream_2_V_write, if_dout => p_dst_data_stream_2_V_dout, if_empty_n => p_dst_data_stream_2_V_empty_n, if_read => p_dst_data_stream_2_V_read); -- ap_reg_procdone_image_filter_AXIvideo2Mat_U0 assign process. -- ap_reg_procdone_image_filter_AXIvideo2Mat_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_done)) then ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 assign process. -- ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done)) then ap_reg_procdone_image_filter_Block_Mat_exit1220_proc1_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 assign process. -- ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done)) then ap_reg_procdone_image_filter_Block_Mat_exit1222_proc1_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Block_proc_U0 assign process. -- ap_reg_procdone_image_filter_Block_proc_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0; elsif ((image_filter_Block_proc_U0_ap_done = ap_const_logic_1)) then ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 assign process. -- ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_Dilate_0_0_1080_1920_U0_ap_done)) then ap_reg_procdone_image_filter_Dilate_0_0_1080_1920_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_FAST_t_opr_U0 assign process. -- ap_reg_procdone_image_filter_FAST_t_opr_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_FAST_t_opr_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_FAST_t_opr_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_FAST_t_opr_U0_ap_done)) then ap_reg_procdone_image_filter_FAST_t_opr_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_Mat2AXIvideo_U0 assign process. -- ap_reg_procdone_image_filter_Mat2AXIvideo_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 assign process. -- ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_sig_hs_done)) then ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = image_filter_PaintMask_32_0_1080_1920_U0_ap_done)) then ap_reg_procdone_image_filter_PaintMask_32_0_1080_1920_U0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_dmask_cols_V_full_n assign process. -- ap_reg_ready_dmask_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_dmask_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_dmask_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = dmask_cols_V_full_n))) then ap_reg_ready_dmask_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_dmask_rows_V_full_n assign process. -- ap_reg_ready_dmask_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_dmask_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_dmask_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = dmask_rows_V_full_n))) then ap_reg_ready_dmask_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_gray_cols_V_full_n assign process. -- ap_reg_ready_gray_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_gray_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_continue))) then ap_reg_ready_gray_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = gray_cols_V_full_n))) then ap_reg_ready_gray_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_gray_rows_V_full_n assign process. -- ap_reg_ready_gray_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_gray_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_continue))) then ap_reg_ready_gray_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_done) and (ap_const_logic_1 = gray_rows_V_full_n))) then ap_reg_ready_gray_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_mask_cols_V_full_n assign process. -- ap_reg_ready_mask_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_mask_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_mask_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = mask_cols_V_full_n))) then ap_reg_ready_mask_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_mask_rows_V_full_n assign process. -- ap_reg_ready_mask_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_mask_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_mask_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = mask_rows_V_full_n))) then ap_reg_ready_mask_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_dst_cols_V_channel_full_n assign process. -- ap_reg_ready_p_dst_cols_V_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (p_dst_cols_V_channel_full_n = ap_const_logic_1))) then ap_reg_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_dst_cols_V_full_n assign process. -- ap_reg_ready_p_dst_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_dst_cols_V_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_dst_cols_V_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_dst_cols_V_full_n))) then ap_reg_ready_p_dst_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_dst_rows_V_channel_full_n assign process. -- ap_reg_ready_p_dst_rows_V_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_dst_rows_V_channel_full_n))) then ap_reg_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_dst_rows_V_full_n assign process. -- ap_reg_ready_p_dst_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_dst_rows_V_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_dst_rows_V_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_dst_rows_V_full_n))) then ap_reg_ready_p_dst_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n assign process. -- ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_2_loc_channel1_full_n))) then ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_cols_V_2_loc_channel_full_n assign process. -- ap_reg_ready_p_src_cols_V_2_loc_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_2_loc_channel_full_n))) then ap_reg_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_cols_V_channel1_full_n assign process. -- ap_reg_ready_p_src_cols_V_channel1_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_channel1_full_n))) then ap_reg_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_cols_V_channel_full_n assign process. -- ap_reg_ready_p_src_cols_V_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_cols_V_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_cols_V_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_cols_V_channel_full_n))) then ap_reg_ready_p_src_cols_V_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n assign process. -- ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_2_loc_channel1_full_n))) then ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_rows_V_2_loc_channel_full_n assign process. -- ap_reg_ready_p_src_rows_V_2_loc_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_2_loc_channel_full_n))) then ap_reg_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_rows_V_channel1_full_n assign process. -- ap_reg_ready_p_src_rows_V_channel1_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_channel1_full_n))) then ap_reg_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_p_src_rows_V_channel_full_n assign process. -- ap_reg_ready_p_src_rows_V_channel_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_p_src_rows_V_channel_full_n <= ap_const_logic_0; else if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then ap_reg_ready_p_src_rows_V_channel_full_n <= ap_const_logic_0; elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = p_src_rows_V_channel_full_n))) then ap_reg_ready_p_src_rows_V_channel_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_src0_cols_V_full_n assign process. -- ap_reg_ready_src0_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_src0_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_src0_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src0_cols_V_full_n))) then ap_reg_ready_src0_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_src0_rows_V_full_n assign process. -- ap_reg_ready_src0_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_src0_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_src0_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src0_rows_V_full_n))) then ap_reg_ready_src0_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_src1_cols_V_full_n assign process. -- ap_reg_ready_src1_cols_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_src1_cols_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_src1_cols_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src1_cols_V_full_n))) then ap_reg_ready_src1_cols_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ready_src1_rows_V_full_n assign process. -- ap_reg_ready_src1_rows_V_full_n_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_reg_ready_src1_rows_V_full_n <= ap_const_logic_0; else if (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_continue))) then ap_reg_ready_src1_rows_V_full_n <= ap_const_logic_0; elsif (((ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_done) and (ap_const_logic_1 = src1_rows_V_full_n))) then ap_reg_ready_src1_rows_V_full_n <= ap_const_logic_1; end if; end if; end if; end process; -- ap_CS assign process. -- ap_CS_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then ap_CS <= ap_const_logic_0; end if; end process; INPUT_STREAM_TREADY <= image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY; OUTPUT_STREAM_TDATA <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA; OUTPUT_STREAM_TDEST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST; OUTPUT_STREAM_TID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID; OUTPUT_STREAM_TKEEP <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP; OUTPUT_STREAM_TLAST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST; OUTPUT_STREAM_TSTRB <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB; OUTPUT_STREAM_TUSER <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER; OUTPUT_STREAM_TVALID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_dmask_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_dmask_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_dmask_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_dmask_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_mask_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_mask_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_mask_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_mask_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src0_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_src0_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src0_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_src0_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src1_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_src1_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V_assign_proc : process(image_filter_Block_Mat_exit1220_proc1_U0_ap_done, ap_reg_ready_src1_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_src1_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V <= image_filter_Block_Mat_exit1220_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V_assign_proc : process(image_filter_Block_Mat_exit1222_proc1_U0_ap_done, ap_reg_ready_gray_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_gray_cols_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V <= image_filter_Block_Mat_exit1222_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V assign process. -- ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V_assign_proc : process(image_filter_Block_Mat_exit1222_proc1_U0_ap_done, ap_reg_ready_gray_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_gray_rows_V_full_n)) then ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V <= image_filter_Block_Mat_exit1222_proc1_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_cols_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_dst_cols_V_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_cols_V_channel_full_n) begin if ((ap_reg_ready_p_dst_cols_V_channel_full_n = ap_const_logic_1)) then ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_rows_V_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_dst_rows_V_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_dst_rows_V_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_dst_rows_V_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_2_loc_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_2_loc_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1 <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_cols_V_channel1_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_cols_V_channel1_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1 <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_2_loc_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_2_loc_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1 <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_channel_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_channel_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel <= image_filter_Block_proc_U0_ap_done; end if; end process; -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 assign process. -- ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_p_src_rows_V_channel1_full_n) begin if ((ap_const_logic_1 = ap_reg_ready_p_src_rows_V_channel1_full_n)) then ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 <= ap_const_logic_0; else ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1 <= image_filter_Block_proc_U0_ap_done; end if; end process; ap_done <= ap_sig_hs_done; -- ap_idle assign process. -- ap_idle_assign_proc : process(image_filter_Block_proc_U0_ap_idle, image_filter_AXIvideo2Mat_U0_ap_idle, image_filter_Block_Mat_exit1220_proc1_U0_ap_idle, image_filter_Block_Mat_exit1222_proc1_U0_ap_idle, image_filter_FAST_t_opr_U0_ap_idle, image_filter_Dilate_0_0_1080_1920_U0_ap_idle, image_filter_PaintMask_32_0_1080_1920_U0_ap_idle, image_filter_Mat2AXIvideo_U0_ap_idle, p_src_cols_V_2_loc_channel1_empty_n, p_src_cols_V_2_loc_channel_empty_n, p_src_rows_V_2_loc_channel1_empty_n, p_src_rows_V_2_loc_channel_empty_n, p_dst_cols_V_channel_empty_n, p_dst_cols_V_empty_n, p_dst_rows_V_channel_empty_n, p_dst_rows_V_empty_n, p_src_cols_V_channel_empty_n, p_src_rows_V_channel_empty_n, p_src_rows_V_channel1_empty_n, p_src_cols_V_channel1_empty_n, src0_rows_V_empty_n, src0_cols_V_empty_n, src1_rows_V_empty_n, src1_cols_V_empty_n, mask_rows_V_empty_n, mask_cols_V_empty_n, dmask_rows_V_empty_n, dmask_cols_V_empty_n, gray_rows_V_empty_n, gray_cols_V_empty_n) begin if (((image_filter_Block_proc_U0_ap_idle = ap_const_logic_1) and (ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_idle) and (ap_const_logic_1 = image_filter_Block_Mat_exit1220_proc1_U0_ap_idle) and (ap_const_logic_1 = image_filter_Block_Mat_exit1222_proc1_U0_ap_idle) and (ap_const_logic_1 = image_filter_FAST_t_opr_U0_ap_idle) and (ap_const_logic_1 = image_filter_Dilate_0_0_1080_1920_U0_ap_idle) and (ap_const_logic_1 = image_filter_PaintMask_32_0_1080_1920_U0_ap_idle) and (ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_idle) and (ap_const_logic_0 = p_src_cols_V_2_loc_channel1_empty_n) and (ap_const_logic_0 = p_src_cols_V_2_loc_channel_empty_n) and (ap_const_logic_0 = p_src_rows_V_2_loc_channel1_empty_n) and (ap_const_logic_0 = p_src_rows_V_2_loc_channel_empty_n) and (ap_const_logic_0 = p_dst_cols_V_channel_empty_n) and (ap_const_logic_0 = p_dst_cols_V_empty_n) and (ap_const_logic_0 = p_dst_rows_V_channel_empty_n) and (ap_const_logic_0 = p_dst_rows_V_empty_n) and (ap_const_logic_0 = p_src_cols_V_channel_empty_n) and (ap_const_logic_0 = p_src_rows_V_channel_empty_n) and (ap_const_logic_0 = p_src_rows_V_channel1_empty_n) and (ap_const_logic_0 = p_src_cols_V_channel1_empty_n) and (ap_const_logic_0 = src0_rows_V_empty_n) and (ap_const_logic_0 = src0_cols_V_empty_n) and (ap_const_logic_0 = src1_rows_V_empty_n) and (ap_const_logic_0 = src1_cols_V_empty_n) and (ap_const_logic_0 = mask_rows_V_empty_n) and (ap_const_logic_0 = mask_cols_V_empty_n) and (ap_const_logic_0 = dmask_rows_V_empty_n) and (ap_const_logic_0 = dmask_cols_V_empty_n) and (ap_const_logic_0 = gray_rows_V_empty_n) and (ap_const_logic_0 = gray_cols_V_empty_n))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_ready <= ap_sig_top_allready; -- ap_rst_n_inv assign process. -- ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; ap_sig_hs_continue <= ap_const_logic_1; -- ap_sig_hs_done assign process. -- ap_sig_hs_done_assign_proc : process(image_filter_Mat2AXIvideo_U0_ap_done) begin if ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then ap_sig_hs_done <= ap_const_logic_1; else ap_sig_hs_done <= ap_const_logic_0; end if; end process; -- ap_sig_ready_dmask_cols_V_full_n assign process. -- ap_sig_ready_dmask_cols_V_full_n_assign_proc : process(dmask_cols_V_full_n, ap_reg_ready_dmask_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_dmask_cols_V_full_n)) then ap_sig_ready_dmask_cols_V_full_n <= dmask_cols_V_full_n; else ap_sig_ready_dmask_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_dmask_rows_V_full_n assign process. -- ap_sig_ready_dmask_rows_V_full_n_assign_proc : process(dmask_rows_V_full_n, ap_reg_ready_dmask_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_dmask_rows_V_full_n)) then ap_sig_ready_dmask_rows_V_full_n <= dmask_rows_V_full_n; else ap_sig_ready_dmask_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_gray_cols_V_full_n assign process. -- ap_sig_ready_gray_cols_V_full_n_assign_proc : process(gray_cols_V_full_n, ap_reg_ready_gray_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_gray_cols_V_full_n)) then ap_sig_ready_gray_cols_V_full_n <= gray_cols_V_full_n; else ap_sig_ready_gray_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_gray_rows_V_full_n assign process. -- ap_sig_ready_gray_rows_V_full_n_assign_proc : process(gray_rows_V_full_n, ap_reg_ready_gray_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_gray_rows_V_full_n)) then ap_sig_ready_gray_rows_V_full_n <= gray_rows_V_full_n; else ap_sig_ready_gray_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_mask_cols_V_full_n assign process. -- ap_sig_ready_mask_cols_V_full_n_assign_proc : process(mask_cols_V_full_n, ap_reg_ready_mask_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_mask_cols_V_full_n)) then ap_sig_ready_mask_cols_V_full_n <= mask_cols_V_full_n; else ap_sig_ready_mask_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_mask_rows_V_full_n assign process. -- ap_sig_ready_mask_rows_V_full_n_assign_proc : process(mask_rows_V_full_n, ap_reg_ready_mask_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_mask_rows_V_full_n)) then ap_sig_ready_mask_rows_V_full_n <= mask_rows_V_full_n; else ap_sig_ready_mask_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_dst_cols_V_channel_full_n assign process. -- ap_sig_ready_p_dst_cols_V_channel_full_n_assign_proc : process(p_dst_cols_V_channel_full_n, ap_reg_ready_p_dst_cols_V_channel_full_n) begin if ((ap_reg_ready_p_dst_cols_V_channel_full_n = ap_const_logic_0)) then ap_sig_ready_p_dst_cols_V_channel_full_n <= p_dst_cols_V_channel_full_n; else ap_sig_ready_p_dst_cols_V_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_dst_cols_V_full_n assign process. -- ap_sig_ready_p_dst_cols_V_full_n_assign_proc : process(p_dst_cols_V_full_n, ap_reg_ready_p_dst_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_dst_cols_V_full_n)) then ap_sig_ready_p_dst_cols_V_full_n <= p_dst_cols_V_full_n; else ap_sig_ready_p_dst_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_dst_rows_V_channel_full_n assign process. -- ap_sig_ready_p_dst_rows_V_channel_full_n_assign_proc : process(p_dst_rows_V_channel_full_n, ap_reg_ready_p_dst_rows_V_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_dst_rows_V_channel_full_n)) then ap_sig_ready_p_dst_rows_V_channel_full_n <= p_dst_rows_V_channel_full_n; else ap_sig_ready_p_dst_rows_V_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_dst_rows_V_full_n assign process. -- ap_sig_ready_p_dst_rows_V_full_n_assign_proc : process(p_dst_rows_V_full_n, ap_reg_ready_p_dst_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_dst_rows_V_full_n)) then ap_sig_ready_p_dst_rows_V_full_n <= p_dst_rows_V_full_n; else ap_sig_ready_p_dst_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n assign process. -- ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n_assign_proc : process(p_src_cols_V_2_loc_channel1_full_n, ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_2_loc_channel1_full_n)) then ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n <= p_src_cols_V_2_loc_channel1_full_n; else ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_cols_V_2_loc_channel_full_n assign process. -- ap_sig_ready_p_src_cols_V_2_loc_channel_full_n_assign_proc : process(p_src_cols_V_2_loc_channel_full_n, ap_reg_ready_p_src_cols_V_2_loc_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_2_loc_channel_full_n)) then ap_sig_ready_p_src_cols_V_2_loc_channel_full_n <= p_src_cols_V_2_loc_channel_full_n; else ap_sig_ready_p_src_cols_V_2_loc_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_cols_V_channel1_full_n assign process. -- ap_sig_ready_p_src_cols_V_channel1_full_n_assign_proc : process(p_src_cols_V_channel1_full_n, ap_reg_ready_p_src_cols_V_channel1_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_channel1_full_n)) then ap_sig_ready_p_src_cols_V_channel1_full_n <= p_src_cols_V_channel1_full_n; else ap_sig_ready_p_src_cols_V_channel1_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_cols_V_channel_full_n assign process. -- ap_sig_ready_p_src_cols_V_channel_full_n_assign_proc : process(p_src_cols_V_channel_full_n, ap_reg_ready_p_src_cols_V_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_cols_V_channel_full_n)) then ap_sig_ready_p_src_cols_V_channel_full_n <= p_src_cols_V_channel_full_n; else ap_sig_ready_p_src_cols_V_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n assign process. -- ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n_assign_proc : process(p_src_rows_V_2_loc_channel1_full_n, ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_2_loc_channel1_full_n)) then ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n <= p_src_rows_V_2_loc_channel1_full_n; else ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_rows_V_2_loc_channel_full_n assign process. -- ap_sig_ready_p_src_rows_V_2_loc_channel_full_n_assign_proc : process(p_src_rows_V_2_loc_channel_full_n, ap_reg_ready_p_src_rows_V_2_loc_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_2_loc_channel_full_n)) then ap_sig_ready_p_src_rows_V_2_loc_channel_full_n <= p_src_rows_V_2_loc_channel_full_n; else ap_sig_ready_p_src_rows_V_2_loc_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_rows_V_channel1_full_n assign process. -- ap_sig_ready_p_src_rows_V_channel1_full_n_assign_proc : process(p_src_rows_V_channel1_full_n, ap_reg_ready_p_src_rows_V_channel1_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_channel1_full_n)) then ap_sig_ready_p_src_rows_V_channel1_full_n <= p_src_rows_V_channel1_full_n; else ap_sig_ready_p_src_rows_V_channel1_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_p_src_rows_V_channel_full_n assign process. -- ap_sig_ready_p_src_rows_V_channel_full_n_assign_proc : process(p_src_rows_V_channel_full_n, ap_reg_ready_p_src_rows_V_channel_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_p_src_rows_V_channel_full_n)) then ap_sig_ready_p_src_rows_V_channel_full_n <= p_src_rows_V_channel_full_n; else ap_sig_ready_p_src_rows_V_channel_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_src0_cols_V_full_n assign process. -- ap_sig_ready_src0_cols_V_full_n_assign_proc : process(src0_cols_V_full_n, ap_reg_ready_src0_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_src0_cols_V_full_n)) then ap_sig_ready_src0_cols_V_full_n <= src0_cols_V_full_n; else ap_sig_ready_src0_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_src0_rows_V_full_n assign process. -- ap_sig_ready_src0_rows_V_full_n_assign_proc : process(src0_rows_V_full_n, ap_reg_ready_src0_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_src0_rows_V_full_n)) then ap_sig_ready_src0_rows_V_full_n <= src0_rows_V_full_n; else ap_sig_ready_src0_rows_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_src1_cols_V_full_n assign process. -- ap_sig_ready_src1_cols_V_full_n_assign_proc : process(src1_cols_V_full_n, ap_reg_ready_src1_cols_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_src1_cols_V_full_n)) then ap_sig_ready_src1_cols_V_full_n <= src1_cols_V_full_n; else ap_sig_ready_src1_cols_V_full_n <= ap_const_logic_1; end if; end process; -- ap_sig_ready_src1_rows_V_full_n assign process. -- ap_sig_ready_src1_rows_V_full_n_assign_proc : process(src1_rows_V_full_n, ap_reg_ready_src1_rows_V_full_n) begin if ((ap_const_logic_0 = ap_reg_ready_src1_rows_V_full_n)) then ap_sig_ready_src1_rows_V_full_n <= src1_rows_V_full_n; else ap_sig_ready_src1_rows_V_full_n <= ap_const_logic_1; end if; end process; ap_sig_top_allready <= image_filter_AXIvideo2Mat_U0_ap_ready; dmask_cols_V_U_ap_dummy_ce <= ap_const_logic_1; dmask_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_7; dmask_cols_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; dmask_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_cols_V; dmask_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; dmask_data_stream_0_V_din <= image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_din; dmask_data_stream_0_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_read; dmask_data_stream_0_V_write <= image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_write; dmask_rows_V_U_ap_dummy_ce <= ap_const_logic_1; dmask_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_6; dmask_rows_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; dmask_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_dmask_rows_V; gray_cols_V_U_ap_dummy_ce <= ap_const_logic_1; gray_cols_V_din <= image_filter_Block_Mat_exit1222_proc1_U0_ap_return_1; gray_cols_V_read <= image_filter_FAST_t_opr_U0_ap_ready; gray_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_cols_V; gray_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; gray_data_stream_0_V_din <= image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_din; gray_data_stream_0_V_read <= image_filter_FAST_t_opr_U0_p_src_data_stream_V_read; gray_data_stream_0_V_write <= image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_write; gray_rows_V_U_ap_dummy_ce <= ap_const_logic_1; gray_rows_V_din <= image_filter_Block_Mat_exit1222_proc1_U0_ap_return_0; gray_rows_V_read <= image_filter_FAST_t_opr_U0_ap_ready; gray_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1222_proc1_U0_gray_rows_V; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA <= INPUT_STREAM_TDATA; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST <= INPUT_STREAM_TDEST; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID <= INPUT_STREAM_TID; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP <= INPUT_STREAM_TKEEP; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST <= INPUT_STREAM_TLAST; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB <= INPUT_STREAM_TSTRB; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER <= INPUT_STREAM_TUSER; image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID <= INPUT_STREAM_TVALID; image_filter_AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1; image_filter_AXIvideo2Mat_U0_ap_start <= (ap_start and p_src_cols_V_channel_empty_n and p_src_rows_V_channel_empty_n); image_filter_AXIvideo2Mat_U0_img_cols_V_read <= p_src_cols_V_channel_dout; image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n <= p_src_data_stream_0_V_full_n; image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n <= p_src_data_stream_1_V_full_n; image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n <= p_src_data_stream_2_V_full_n; image_filter_AXIvideo2Mat_U0_img_rows_V_read <= p_src_rows_V_channel_dout; -- image_filter_Block_Mat_exit1220_proc1_U0_ap_continue assign process. -- image_filter_Block_Mat_exit1220_proc1_U0_ap_continue_assign_proc : process(ap_sig_ready_src0_rows_V_full_n, ap_sig_ready_src0_cols_V_full_n, ap_sig_ready_src1_rows_V_full_n, ap_sig_ready_src1_cols_V_full_n, ap_sig_ready_mask_rows_V_full_n, ap_sig_ready_mask_cols_V_full_n, ap_sig_ready_dmask_rows_V_full_n, ap_sig_ready_dmask_cols_V_full_n) begin if (((ap_const_logic_1 = ap_sig_ready_src0_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_src0_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_src1_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_src1_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_mask_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_mask_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_dmask_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_dmask_cols_V_full_n))) then image_filter_Block_Mat_exit1220_proc1_U0_ap_continue <= ap_const_logic_1; else image_filter_Block_Mat_exit1220_proc1_U0_ap_continue <= ap_const_logic_0; end if; end process; image_filter_Block_Mat_exit1220_proc1_U0_ap_start <= (p_src_cols_V_2_loc_channel_empty_n and p_src_rows_V_2_loc_channel_empty_n and p_src_rows_V_channel1_empty_n and p_src_cols_V_channel1_empty_n); image_filter_Block_Mat_exit1220_proc1_U0_p_read <= p_src_rows_V_2_loc_channel_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_read16 <= p_src_rows_V_channel1_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_read17 <= p_src_cols_V_channel1_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_read2 <= p_src_cols_V_2_loc_channel_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_dout <= p_src_data_stream_0_V_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_empty_n <= p_src_data_stream_0_V_empty_n; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_dout <= p_src_data_stream_1_V_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_empty_n <= p_src_data_stream_1_V_empty_n; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_dout <= p_src_data_stream_2_V_dout; image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_empty_n <= p_src_data_stream_2_V_empty_n; image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_full_n <= src0_data_stream_0_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_full_n <= src0_data_stream_1_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_full_n <= src0_data_stream_2_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_full_n <= src1_data_stream_0_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_full_n <= src1_data_stream_1_V_full_n; image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_full_n <= src1_data_stream_2_V_full_n; -- image_filter_Block_Mat_exit1222_proc1_U0_ap_continue assign process. -- image_filter_Block_Mat_exit1222_proc1_U0_ap_continue_assign_proc : process(ap_sig_ready_gray_rows_V_full_n, ap_sig_ready_gray_cols_V_full_n) begin if (((ap_const_logic_1 = ap_sig_ready_gray_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_gray_cols_V_full_n))) then image_filter_Block_Mat_exit1222_proc1_U0_ap_continue <= ap_const_logic_1; else image_filter_Block_Mat_exit1222_proc1_U0_ap_continue <= ap_const_logic_0; end if; end process; image_filter_Block_Mat_exit1222_proc1_U0_ap_start <= (p_src_cols_V_2_loc_channel1_empty_n and p_src_rows_V_2_loc_channel1_empty_n and src0_rows_V_empty_n and src0_cols_V_empty_n); image_filter_Block_Mat_exit1222_proc1_U0_gray_data_stream_0_V_full_n <= gray_data_stream_0_V_full_n; image_filter_Block_Mat_exit1222_proc1_U0_p_read <= p_src_rows_V_2_loc_channel1_dout; image_filter_Block_Mat_exit1222_proc1_U0_p_read2 <= p_src_cols_V_2_loc_channel1_dout; image_filter_Block_Mat_exit1222_proc1_U0_p_read6 <= src0_rows_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_p_read7 <= src0_cols_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_dout <= src0_data_stream_0_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_empty_n <= src0_data_stream_0_V_empty_n; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_dout <= src0_data_stream_1_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_empty_n <= src0_data_stream_1_V_empty_n; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_dout <= src0_data_stream_2_V_dout; image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_empty_n <= src0_data_stream_2_V_empty_n; -- image_filter_Block_proc_U0_ap_continue assign process. -- image_filter_Block_proc_U0_ap_continue_assign_proc : process(ap_sig_ready_p_dst_cols_V_channel_full_n, ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n, ap_sig_ready_p_src_cols_V_2_loc_channel_full_n, ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n, ap_sig_ready_p_src_rows_V_2_loc_channel_full_n, ap_sig_ready_p_src_cols_V_channel_full_n, ap_sig_ready_p_dst_cols_V_full_n, ap_sig_ready_p_dst_rows_V_channel_full_n, ap_sig_ready_p_dst_rows_V_full_n, ap_sig_ready_p_src_rows_V_channel_full_n, ap_sig_ready_p_src_rows_V_channel1_full_n, ap_sig_ready_p_src_cols_V_channel1_full_n) begin if (((ap_sig_ready_p_dst_cols_V_channel_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_2_loc_channel1_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_2_loc_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_2_loc_channel1_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_2_loc_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_dst_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_p_dst_rows_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_dst_rows_V_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_rows_V_channel1_full_n) and (ap_const_logic_1 = ap_sig_ready_p_src_cols_V_channel1_full_n))) then image_filter_Block_proc_U0_ap_continue <= ap_const_logic_1; else image_filter_Block_proc_U0_ap_continue <= ap_const_logic_0; end if; end process; image_filter_Block_proc_U0_ap_start <= ap_start; image_filter_Block_proc_U0_cols <= cols; image_filter_Block_proc_U0_rows <= rows; image_filter_Dilate_0_0_1080_1920_U0_ap_continue <= ap_const_logic_1; image_filter_Dilate_0_0_1080_1920_U0_ap_start <= (mask_rows_V_empty_n and mask_cols_V_empty_n); image_filter_Dilate_0_0_1080_1920_U0_p_dst_data_stream_V_full_n <= dmask_data_stream_0_V_full_n; image_filter_Dilate_0_0_1080_1920_U0_p_src_cols_V_read <= mask_cols_V_dout; image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_dout <= mask_data_stream_0_V_dout; image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_empty_n <= mask_data_stream_0_V_empty_n; image_filter_Dilate_0_0_1080_1920_U0_p_src_rows_V_read <= mask_rows_V_dout; image_filter_FAST_t_opr_U0_ap_continue <= ap_const_logic_1; image_filter_FAST_t_opr_U0_ap_start <= (gray_rows_V_empty_n and gray_cols_V_empty_n); image_filter_FAST_t_opr_U0_p_mask_data_stream_V_full_n <= mask_data_stream_0_V_full_n; image_filter_FAST_t_opr_U0_p_src_cols_V_read <= gray_cols_V_dout; image_filter_FAST_t_opr_U0_p_src_data_stream_V_dout <= gray_data_stream_0_V_dout; image_filter_FAST_t_opr_U0_p_src_data_stream_V_empty_n <= gray_data_stream_0_V_empty_n; image_filter_FAST_t_opr_U0_p_src_rows_V_read <= gray_rows_V_dout; image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY; image_filter_Mat2AXIvideo_U0_ap_continue <= ap_sig_hs_continue; image_filter_Mat2AXIvideo_U0_ap_start <= (p_dst_cols_V_channel_empty_n and p_dst_rows_V_channel_empty_n); image_filter_Mat2AXIvideo_U0_img_cols_V_read <= p_dst_cols_V_channel_dout; image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout <= p_dst_data_stream_0_V_dout; image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n <= p_dst_data_stream_0_V_empty_n; image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout <= p_dst_data_stream_1_V_dout; image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n <= p_dst_data_stream_1_V_empty_n; image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout <= p_dst_data_stream_2_V_dout; image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n <= p_dst_data_stream_2_V_empty_n; image_filter_Mat2AXIvideo_U0_img_rows_V_read <= p_dst_rows_V_channel_dout; image_filter_PaintMask_32_0_1080_1920_U0_ap_continue <= ap_const_logic_1; image_filter_PaintMask_32_0_1080_1920_U0_ap_start <= (p_dst_cols_V_empty_n and p_dst_rows_V_empty_n and src1_rows_V_empty_n and src1_cols_V_empty_n and dmask_rows_V_empty_n and dmask_cols_V_empty_n); image_filter_PaintMask_32_0_1080_1920_U0_p_dst_cols_V_read <= p_dst_cols_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_full_n <= p_dst_data_stream_0_V_full_n; image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_full_n <= p_dst_data_stream_1_V_full_n; image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_full_n <= p_dst_data_stream_2_V_full_n; image_filter_PaintMask_32_0_1080_1920_U0_p_dst_rows_V_read <= p_dst_rows_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_mask_cols_V_read <= dmask_cols_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_dout <= dmask_data_stream_0_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_mask_data_stream_V_empty_n <= dmask_data_stream_0_V_empty_n; image_filter_PaintMask_32_0_1080_1920_U0_p_mask_rows_V_read <= dmask_rows_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_cols_V_read <= src1_cols_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_dout <= src1_data_stream_0_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_empty_n <= src1_data_stream_0_V_empty_n; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_dout <= src1_data_stream_1_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_empty_n <= src1_data_stream_1_V_empty_n; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_dout <= src1_data_stream_2_V_dout; image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_empty_n <= src1_data_stream_2_V_empty_n; image_filter_PaintMask_32_0_1080_1920_U0_p_src_rows_V_read <= src1_rows_V_dout; mask_cols_V_U_ap_dummy_ce <= ap_const_logic_1; mask_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_5; mask_cols_V_read <= image_filter_Dilate_0_0_1080_1920_U0_ap_ready; mask_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_cols_V; mask_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; mask_data_stream_0_V_din <= image_filter_FAST_t_opr_U0_p_mask_data_stream_V_din; mask_data_stream_0_V_read <= image_filter_Dilate_0_0_1080_1920_U0_p_src_data_stream_V_read; mask_data_stream_0_V_write <= image_filter_FAST_t_opr_U0_p_mask_data_stream_V_write; mask_rows_V_U_ap_dummy_ce <= ap_const_logic_1; mask_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_4; mask_rows_V_read <= image_filter_Dilate_0_0_1080_1920_U0_ap_ready; mask_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_mask_rows_V; p_dst_cols_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1; p_dst_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_5; p_dst_cols_V_channel_read <= image_filter_Mat2AXIvideo_U0_ap_ready; p_dst_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V_channel; p_dst_cols_V_din <= image_filter_Block_proc_U0_ap_return_4; p_dst_cols_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; p_dst_cols_V_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_cols_V; p_dst_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_data_stream_0_V_din <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_din; p_dst_data_stream_0_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read; p_dst_data_stream_0_V_write <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_0_V_write; p_dst_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_data_stream_1_V_din <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_din; p_dst_data_stream_1_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read; p_dst_data_stream_1_V_write <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_1_V_write; p_dst_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_data_stream_2_V_din <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_din; p_dst_data_stream_2_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read; p_dst_data_stream_2_V_write <= image_filter_PaintMask_32_0_1080_1920_U0_p_dst_data_stream_2_V_write; p_dst_rows_V_U_ap_dummy_ce <= ap_const_logic_1; p_dst_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1; p_dst_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_3; p_dst_rows_V_channel_read <= image_filter_Mat2AXIvideo_U0_ap_ready; p_dst_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V_channel; p_dst_rows_V_din <= image_filter_Block_proc_U0_ap_return_2; p_dst_rows_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; p_dst_rows_V_write <= ap_chn_write_image_filter_Block_proc_U0_p_dst_rows_V; p_src_cols_V_2_loc_channel1_U_ap_dummy_ce <= ap_const_logic_1; p_src_cols_V_2_loc_channel1_din <= image_filter_Block_proc_U0_ap_return_9; p_src_cols_V_2_loc_channel1_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready; p_src_cols_V_2_loc_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel1; p_src_cols_V_2_loc_channel_U_ap_dummy_ce <= ap_const_logic_1; p_src_cols_V_2_loc_channel_din <= image_filter_Block_proc_U0_ap_return_8; p_src_cols_V_2_loc_channel_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready; p_src_cols_V_2_loc_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_2_loc_channel; p_src_cols_V_channel1_U_ap_dummy_ce <= ap_const_logic_1; p_src_cols_V_channel1_din <= image_filter_Block_proc_U0_ap_return_11; p_src_cols_V_channel1_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready; p_src_cols_V_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel1; p_src_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1; p_src_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_1; p_src_cols_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready; p_src_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_cols_V_channel; p_src_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; p_src_data_stream_0_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din; p_src_data_stream_0_V_read <= image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_0_V_read; p_src_data_stream_0_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write; p_src_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1; p_src_data_stream_1_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din; p_src_data_stream_1_V_read <= image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_1_V_read; p_src_data_stream_1_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write; p_src_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1; p_src_data_stream_2_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din; p_src_data_stream_2_V_read <= image_filter_Block_Mat_exit1220_proc1_U0_p_src_data_stream_2_V_read; p_src_data_stream_2_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write; p_src_rows_V_2_loc_channel1_U_ap_dummy_ce <= ap_const_logic_1; p_src_rows_V_2_loc_channel1_din <= image_filter_Block_proc_U0_ap_return_7; p_src_rows_V_2_loc_channel1_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready; p_src_rows_V_2_loc_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel1; p_src_rows_V_2_loc_channel_U_ap_dummy_ce <= ap_const_logic_1; p_src_rows_V_2_loc_channel_din <= image_filter_Block_proc_U0_ap_return_6; p_src_rows_V_2_loc_channel_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready; p_src_rows_V_2_loc_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_2_loc_channel; p_src_rows_V_channel1_U_ap_dummy_ce <= ap_const_logic_1; p_src_rows_V_channel1_din <= image_filter_Block_proc_U0_ap_return_10; p_src_rows_V_channel1_read <= image_filter_Block_Mat_exit1220_proc1_U0_ap_ready; p_src_rows_V_channel1_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel1; p_src_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1; p_src_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_0; p_src_rows_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready; p_src_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_p_src_rows_V_channel; src0_cols_V_U_ap_dummy_ce <= ap_const_logic_1; src0_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_1; src0_cols_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready; src0_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_cols_V; src0_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; src0_data_stream_0_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_din; src0_data_stream_0_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_0_V_read; src0_data_stream_0_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_0_V_write; src0_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1; src0_data_stream_1_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_din; src0_data_stream_1_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_1_V_read; src0_data_stream_1_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_1_V_write; src0_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1; src0_data_stream_2_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_din; src0_data_stream_2_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_src0_data_stream_2_V_read; src0_data_stream_2_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src0_data_stream_2_V_write; src0_rows_V_U_ap_dummy_ce <= ap_const_logic_1; src0_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_0; src0_rows_V_read <= image_filter_Block_Mat_exit1222_proc1_U0_ap_ready; src0_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src0_rows_V; src1_cols_V_U_ap_dummy_ce <= ap_const_logic_1; src1_cols_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_3; src1_cols_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; src1_cols_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_cols_V; src1_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1; src1_data_stream_0_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_din; src1_data_stream_0_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_0_V_read; src1_data_stream_0_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_0_V_write; src1_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1; src1_data_stream_1_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_din; src1_data_stream_1_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_1_V_read; src1_data_stream_1_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_1_V_write; src1_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1; src1_data_stream_2_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_din; src1_data_stream_2_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_p_src_data_stream_2_V_read; src1_data_stream_2_V_write <= image_filter_Block_Mat_exit1220_proc1_U0_src1_data_stream_2_V_write; src1_rows_V_U_ap_dummy_ce <= ap_const_logic_1; src1_rows_V_din <= image_filter_Block_Mat_exit1220_proc1_U0_ap_return_2; src1_rows_V_read <= image_filter_PaintMask_32_0_1080_1920_U0_ap_ready; src1_rows_V_write <= ap_chn_write_image_filter_Block_Mat_exit1220_proc1_U0_src1_rows_V; end behav;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd

3

24145

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_ftch_noqueue.vhd -- Description: This entity is the no queue version -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_ftch_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Stream Data Width C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; C_ASYNC : integer range 0 to 1 := 0; C_SG_WORDS_TO_FETCH : integer range 8 to 13 := 8; C_ENABLE_CDMA : integer range 0 to 1 := 0; C_ENABLE_CH1 : integer range 0 to 1 := 0; C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_primary_aclk : in std_logic ; m_axi_sg_aresetn : in std_logic ; -- p_reset_n : in std_logic ; -- -- Channel Control -- desc_flush : in std_logic ; -- ch1_cntrl_strm_stop : in std_logic ; ftch_active : in std_logic ; -- ftch_queue_empty : out std_logic ; -- ftch_queue_full : out std_logic ; -- sof_ftch_desc : in std_logic ; desc2_flush : in std_logic ; -- ftch2_active : in std_logic ; -- ftch2_queue_empty : out std_logic ; -- ftch2_queue_full : out std_logic ; -- -- writing_nxtdesc_in : in std_logic ; -- writing_curdesc_out : out std_logic ; -- writing2_curdesc_out : out std_logic ; -- -- DataMover Command -- ftch_cmnd_wr : in std_logic ; -- ftch_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- MM2S Stream In from DataMover -- m_axis_mm2s_tdata : in std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_mm2s_tlast : in std_logic ; -- m_axis_mm2s_tvalid : in std_logic ; -- m_axis_mm2s_tready : out std_logic ; -- m_axis2_mm2s_tready : out std_logic ; -- data_concat : in std_logic_vector -- (95 downto 0) ; -- data_concat_mcdma : in std_logic_vector -- (63 downto 0) ; -- next_bd : in std_logic_vector (31 downto 0); data_concat_tlast : in std_logic ; -- data_concat_valid : in std_logic ; -- -- -- Channel 1 AXI Fetch Stream Out -- m_axis_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis_ftch_tvalid : out std_logic ; -- m_axis_ftch_tready : in std_logic ; -- m_axis_ftch_tlast : out std_logic ; -- m_axis_ftch_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis_ftch_tvalid_new : out std_logic ; -- m_axis_ftch_desc_available : out std_logic ; m_axis2_ftch_tdata : out std_logic_vector -- (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; -- m_axis2_ftch_tvalid : out std_logic ; -- m_axis2_ftch_tready : in std_logic ; -- m_axis2_ftch_tlast : out std_logic ; -- m_axis2_ftch_tdata_new : out std_logic_vector -- (96+31*C_ENABLE_CDMA downto 0); -- m_axis2_ftch_tdata_mcdma_new : out std_logic_vector -- (63 downto 0); -- m_axis2_ftch_tdata_mcdma_nxt : out std_logic_vector -- (31 downto 0); -- m_axis2_ftch_tvalid_new : out std_logic ; -- m_axis2_ftch_desc_available : out std_logic ; m_axis_mm2s_cntrl_tdata : out std_logic_vector -- (31 downto 0); -- m_axis_mm2s_cntrl_tkeep : out std_logic_vector -- (3 downto 0); -- m_axis_mm2s_cntrl_tvalid : out std_logic ; -- m_axis_mm2s_cntrl_tready : in std_logic := '0'; -- m_axis_mm2s_cntrl_tlast : out std_logic -- ); end axi_sg_ftch_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_ftch_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel 1 internal signals signal curdesc_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal curdesc_tvalid : std_logic := '0'; signal ftch_tvalid : std_logic := '0'; signal ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ftch_tlast : std_logic := '0'; signal ftch_tready : std_logic := '0'; -- Misc Signals signal writing_curdesc : std_logic := '0'; signal writing_nxtdesc : std_logic := '0'; signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0'); signal writing_lsb : std_logic := '0'; signal writing_msb : std_logic := '0'; signal ftch_active_int : std_logic := '0'; signal ftch_tvalid_mult : std_logic := '0'; signal ftch_tdata_mult : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0'); signal ftch_tlast_mult : std_logic := '0'; signal counter : std_logic_vector (3 downto 0) := (others => '0'); signal wr_cntl : std_logic := '0'; signal ftch_tdata_new : std_logic_vector (96+31*C_ENABLE_CDMA downto 0); signal queue_wren, queue_rden : std_logic := '0'; signal queue_din : std_logic_vector (32 downto 0); signal queue_dout : std_logic_vector (32 downto 0); signal queue_empty, queue_full : std_logic := '0'; signal sof_ftch_desc_del, sof_ftch_desc_pulse : std_logic := '0'; signal sof_ftch_desc_del1 : std_logic := '0'; signal queue_sinit : std_logic := '0'; signal data_concat_mcdma_nxt : std_logic_vector (31 downto 0) := (others => '0'); signal current_bd : std_logic_vector (31 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin queue_sinit <= not m_axi_sg_aresetn; ftch_active_int <= ftch_active or ftch2_active; CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate begin ftch_tdata_new (95 downto 0) <= data_concat;-- when (ftch_active = '1') else (others =>'0'); ftch_tdata_new (127 downto 96) <= current_bd; end generate CDMA_FIELDS; DMA_FIELDS : if C_ENABLE_CDMA = 0 generate begin ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0'); ftch_tdata_new (96 downto 65) <= current_bd; end generate DMA_FIELDS; --------------------------------------------------------------------------- -- Write current descriptor to FIFO or out channel port --------------------------------------------------------------------------- NXT_BD_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate begin NEXT_BD_S2MM : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then data_concat_mcdma_nxt <= (others => '0'); elsif (ftch2_active = '1') then data_concat_mcdma_nxt <= next_bd; end if; end if; end process NEXT_BD_S2MM; end generate NXT_BD_MCDMA; WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then current_bd <= (others => '0'); -- -- -- Write LSB Address on command write elsif(ftch_cmnd_wr = '1' and ftch_active_int = '1')then current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST + DATAMOVER_CMD_ADDRLSB_BIT downto DATAMOVER_CMD_ADDRLSB_BIT); end if; end if; end process WRITE_CURDESC_PROCESS; GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate begin ftch_tvalid_mult <= m_axis_mm2s_tvalid; ftch_tdata_mult <= m_axis_mm2s_tdata; ftch_tlast_mult <= m_axis_mm2s_tlast; wr_cntl <= m_axis_mm2s_tvalid; m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= "0000"; m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; end generate GEN_MULT_CHANNEL; GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate begin ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid; ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata; ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast; CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 and C_ENABLE_CH1 = 1 generate begin SOF_DEL_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then sof_ftch_desc_del <= '0'; else sof_ftch_desc_del <= sof_ftch_desc; end if; end if; end process SOF_DEL_PROCESS; SOF_DEL1_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then sof_ftch_desc_del1 <= '0'; elsif (m_axis_mm2s_tvalid = '1') then sof_ftch_desc_del1 <= sof_ftch_desc; end if; end if; end process SOF_DEL1_PROCESS; sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1); queue_wren <= not queue_full and sof_ftch_desc and m_axis_mm2s_tvalid and ftch_active; queue_rden <= not queue_empty and m_axis_mm2s_cntrl_tready; queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast; queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata; I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1.axi_sg_cntrl_strm generic map( C_PRMRY_IS_ACLK_ASYNC => C_ASYNC , C_PRMY_CMDFIFO_DEPTH => 16, --FETCH_QUEUE_DEPTH , C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH , C_FAMILY => C_FAMILY ) port map( -- Secondary clock / reset m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , -- Primary clock / reset axi_prmry_aclk => m_axi_primary_aclk , p_reset_n => p_reset_n , -- MM2S Error mm2s_stop => ch1_cntrl_strm_stop , -- Control Stream input cntrlstrm_fifo_wren => queue_wren , cntrlstrm_fifo_full => queue_full , cntrlstrm_fifo_din => queue_din , -- Memory Map to Stream Control Stream Interface m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata , m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep , m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid , m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready , m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast ); end generate CONTROL_STREAM; NO_CONTROL_STREAM : if C_SG_WORDS_TO_FETCH /= 13 or C_ENABLE_CH1 = 0 generate begin m_axis_mm2s_cntrl_tdata <= (others => '0'); m_axis_mm2s_cntrl_tkeep <= "0000"; m_axis_mm2s_cntrl_tvalid <= '0'; m_axis_mm2s_cntrl_tlast <= '0'; end generate NO_CONTROL_STREAM; end generate GEN_NOMULT_CHANNEL; --------------------------------------------------------------------------- -- Map internal stream to external --------------------------------------------------------------------------- ftch_tready <= (m_axis_ftch_tready and ftch_active) or (m_axis2_ftch_tready and ftch2_active); m_axis_ftch_tdata_new <= ftch_tdata_new; m_axis_ftch_tdata_mcdma_new <= data_concat_mcdma; m_axis_ftch_tvalid_new <= data_concat_valid and ftch_active; m_axis_ftch_desc_available <= data_concat_tlast and ftch_active; REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH = 13 generate begin LATCH_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then m_axis2_ftch_tvalid_new <= '0'; m_axis2_ftch_desc_available <= '0'; else m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active; m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active; end if; end if; end process LATCH_PROCESS; LATCH2_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then m_axis2_ftch_tdata_new <= (others => '0'); elsif (data_concat_valid = '1' and ftch2_active = '1') then m_axis2_ftch_tdata_new <= ftch_tdata_new; end if; end if; end process LATCH2_PROCESS; end generate REG_FOR_STS_CNTRL; NO_REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH /= 13 generate begin m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active; m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active; m_axis2_ftch_tdata_new <= ftch_tdata_new; m_axis2_ftch_tdata_mcdma_new <= data_concat_mcdma; m_axis2_ftch_tdata_mcdma_nxt <= data_concat_mcdma_nxt; end generate NO_REG_FOR_STS_CNTRL; m_axis_mm2s_tready <= ftch_tready; m_axis2_mm2s_tready <= ftch_tready; --------------------------------------------------------------------------- -- generate psuedo empty flag for Idle generation --------------------------------------------------------------------------- Q_EMPTY_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then if(m_axi_sg_aresetn = '0' or desc_flush = '1')then ftch_queue_empty <= '1'; -- Else on valid and ready modify empty flag elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1' and ftch_active = '1')then -- On last mark as empty if(ftch_tlast = '1' )then ftch_queue_empty <= '1'; -- Otherwise mark as not empty else ftch_queue_empty <= '0'; end if; end if; end if; end process Q_EMPTY_PROCESS; Q2_EMPTY_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then if(m_axi_sg_aresetn = '0' or desc2_flush = '1')then ftch2_queue_empty <= '1'; -- Else on valid and ready modify empty flag elsif(ftch_tvalid = '1' and m_axis2_ftch_tready = '1' and ftch2_active = '1')then -- On last mark as empty if(ftch_tlast = '1' )then ftch2_queue_empty <= '1'; -- Otherwise mark as not empty else ftch2_queue_empty <= '0'; end if; end if; end if; end process Q2_EMPTY_PROCESS; -- do not need to indicate full to axi_sg_ftch_sm. Only -- needed for queue case to allow other channel to be serviced -- if it had queue room ftch_queue_full <= '0'; ftch2_queue_full <= '0'; -- If writing curdesc out then flag for proper mux selection writing_curdesc <= curdesc_tvalid; -- Map intnal signal to port writing_curdesc_out <= writing_curdesc and ftch_active; writing2_curdesc_out <= writing_curdesc and ftch2_active; -- Map port to internal signal writing_nxtdesc <= writing_nxtdesc_in; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/vhdl/image_filter_Dilate_0_0_1080_1920_s.vhd

2

92940

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter_Dilate_0_0_1080_1920_s is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_V_empty_n : IN STD_LOGIC; p_src_data_stream_V_read : OUT STD_LOGIC; p_dst_data_stream_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_V_full_n : IN STD_LOGIC; p_dst_data_stream_V_write : OUT STD_LOGIC ); end; architecture behav of image_filter_Dilate_0_0_1080_1920_s is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (4 downto 0) := "00001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (4 downto 0) := "00010"; constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (4 downto 0) := "00100"; constant ap_ST_pp0_stg0_fsm_3 : STD_LOGIC_VECTOR (4 downto 0) := "01000"; constant ap_ST_st12_fsm_4 : STD_LOGIC_VECTOR (4 downto 0) := "10000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv11_5 : STD_LOGIC_VECTOR (10 downto 0) := "00000000101"; constant ap_const_lv11_2 : STD_LOGIC_VECTOR (10 downto 0) := "00000000010"; constant ap_const_lv11_7FD : STD_LOGIC_VECTOR (10 downto 0) := "11111111101"; constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv11_7FF : STD_LOGIC_VECTOR (10 downto 0) := "11111111111"; constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; constant ap_const_lv11_4 : STD_LOGIC_VECTOR (10 downto 0) := "00000000100"; constant ap_const_lv12_FFC : STD_LOGIC_VECTOR (11 downto 0) := "111111111100"; constant ap_const_lv12_FFF : STD_LOGIC_VECTOR (11 downto 0) := "111111111111"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; constant ap_const_lv12_FFB : STD_LOGIC_VECTOR (11 downto 0) := "111111111011"; constant ap_const_lv12_FFA : STD_LOGIC_VECTOR (11 downto 0) := "111111111010"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000"; signal ap_done_reg : STD_LOGIC := '0'; signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_24 : BOOLEAN; signal p_025_0_i_i_reg_263 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_bdd_48 : BOOLEAN; signal heightloop_fu_324_p2 : STD_LOGIC_VECTOR (10 downto 0); signal heightloop_reg_1240 : STD_LOGIC_VECTOR (10 downto 0); signal widthloop_fu_330_p2 : STD_LOGIC_VECTOR (10 downto 0); signal widthloop_reg_1245 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_14_cast_fu_342_p1 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_14_cast_reg_1250 : STD_LOGIC_VECTOR (11 downto 0); signal p_neg226_i_i_cast_fu_350_p2 : STD_LOGIC_VECTOR (1 downto 0); signal p_neg226_i_i_cast_reg_1255 : STD_LOGIC_VECTOR (1 downto 0); signal ref_fu_356_p2 : STD_LOGIC_VECTOR (10 downto 0); signal ref_reg_1261 : STD_LOGIC_VECTOR (10 downto 0); signal ref_cast_fu_362_p1 : STD_LOGIC_VECTOR (11 downto 0); signal ref_cast_reg_1267 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_2_i_fu_366_p2 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_2_i_reg_1272 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_2_i1_fu_376_p2 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_2_i1_reg_1277 : STD_LOGIC_VECTOR (1 downto 0); signal i_V_fu_391_p2 : STD_LOGIC_VECTOR (10 downto 0); signal i_V_reg_1286 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_76 : BOOLEAN; signal tmp_17_fu_397_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_17_reg_1291 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_16_fu_386_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_23_reg_1296 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_fu_436_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_reg_1301 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_104_reg_1306 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_105_fu_457_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_105_reg_1310 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_108_fu_473_p3 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_108_reg_1316 : STD_LOGIC_VECTOR (1 downto 0); signal or_cond_i1_fu_506_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_i1_reg_1322 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_110_reg_1327 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_111_fu_520_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_111_reg_1332 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_112_fu_524_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_112_reg_1337 : STD_LOGIC_VECTOR (1 downto 0); signal or_cond_i2_fu_553_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_i2_reg_1344 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_114_reg_1349 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_115_fu_567_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_115_reg_1354 : STD_LOGIC_VECTOR (1 downto 0); signal sel_tmp8_fu_575_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp8_reg_1359 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC; signal ap_sig_bdd_116 : BOOLEAN; signal sel_tmp3_fu_579_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp3_reg_1364 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp4_fu_602_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp4_reg_1369 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp7_fu_607_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp7_reg_1374 : STD_LOGIC_VECTOR (0 downto 0); signal locy_2_t_fu_625_p2 : STD_LOGIC_VECTOR (1 downto 0); signal locy_2_t_reg_1379 : STD_LOGIC_VECTOR (1 downto 0); signal brmerge_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0); signal brmerge_reg_1383 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_fu_638_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_19_reg_1387 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_pp0_stg0_fsm_3 : STD_LOGIC; signal ap_sig_bdd_135 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond2_reg_1419 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_bdd_154 : BOOLEAN; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0'; signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0'; signal or_cond219_i_i_reg_1396 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_bdd_172 : BOOLEAN; signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0'; signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0); signal j_V_fu_643_p2 : STD_LOGIC_VECTOR (10 downto 0); signal or_cond219_i_i_fu_665_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_117_fu_676_p1 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_117_reg_1400 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_i_fu_698_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i_reg_1405 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_i_fu_703_p2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond_i_reg_1409 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_120_reg_1414 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal or_cond2_fu_723_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_29_fu_729_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_29_reg_1423 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal col_assign_fu_734_p2 : STD_LOGIC_VECTOR (1 downto 0); signal col_assign_reg_1427 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_col_assign_reg_1427_pp0_it1 : STD_LOGIC_VECTOR (1 downto 0); signal k_buf_0_val_0_addr_reg_1433 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_1_addr_reg_1439 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_2_addr_reg_1445 : STD_LOGIC_VECTOR (10 downto 0); signal col_assign_1_fu_762_p2 : STD_LOGIC_VECTOR (1 downto 0); signal col_assign_1_reg_1451 : STD_LOGIC_VECTOR (1 downto 0); signal ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 : STD_LOGIC_VECTOR (1 downto 0); signal k_buf_0_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_2_0_reg_1457 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_0_reg_1464 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_2_0_reg_1471 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_0_1_reg_1477 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_0_1_6_reg_1483 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_1_6_reg_1490 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_2_lo_reg_1496 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_0_2_reg_1501 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_1_fu_1033_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_128_1_reg_1506 : STD_LOGIC_VECTOR (0 downto 0); signal src_kernel_win_0_val_0_1_lo_reg_1511 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 : STD_LOGIC_VECTOR (7 downto 0); signal ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_1_lo_reg_1517 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_1_1_reg_1523 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_0_2_lo_reg_1529 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_1_2_reg_1534 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_2_fu_1080_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_128_2_reg_1539 : STD_LOGIC_VECTOR (0 downto 0); signal temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 : STD_LOGIC_VECTOR (7 downto 0); signal temp_0_i_i_i_057_i_i_1_2_1_reg_1544 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_0_address0 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_0_ce0 : STD_LOGIC; signal k_buf_0_val_0_address1 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_0_ce1 : STD_LOGIC; signal k_buf_0_val_0_we1 : STD_LOGIC; signal k_buf_0_val_0_d1 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_1_address0 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_1_ce0 : STD_LOGIC; signal k_buf_0_val_1_address1 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_1_ce1 : STD_LOGIC; signal k_buf_0_val_1_we1 : STD_LOGIC; signal k_buf_0_val_1_d1 : STD_LOGIC_VECTOR (7 downto 0); signal k_buf_0_val_2_address0 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_2_ce0 : STD_LOGIC; signal k_buf_0_val_2_address1 : STD_LOGIC_VECTOR (10 downto 0); signal k_buf_0_val_2_ce1 : STD_LOGIC; signal k_buf_0_val_2_we1 : STD_LOGIC; signal k_buf_0_val_2_d1 : STD_LOGIC_VECTOR (7 downto 0); signal p_012_0_i_i_reg_252 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_cseq_ST_st12_fsm_4 : STD_LOGIC; signal ap_sig_bdd_355 : BOOLEAN; signal tmp_69_fu_755_p1 : STD_LOGIC_VECTOR (63 downto 0); signal src_kernel_win_0_val_0_1_fu_106 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_0_0_fu_934_p3 : STD_LOGIC_VECTOR (7 downto 0); signal col_buf_0_val_0_0_9_fu_989_p3 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_0_2_fu_110 : STD_LOGIC_VECTOR (7 downto 0); signal col_buf_0_val_0_0_3_fu_114 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_2_1_fu_118 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_1_fu_122 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_0_fu_946_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_11_fu_1006_p3 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_1_2_fu_126 : STD_LOGIC_VECTOR (7 downto 0); signal col_buf_0_val_0_0_5_fu_130 : STD_LOGIC_VECTOR (7 downto 0); signal src_kernel_win_0_val_2_2_fu_134 : STD_LOGIC_VECTOR (7 downto 0); signal col_buf_0_val_0_0_6_fu_138 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_1_fu_142 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_8_fu_877_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_2_fu_146 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_6_fu_868_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_7_fu_150 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_4_fu_851_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_0_0_fu_166 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_0_1_fu_170 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_0_2_fu_174 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_fu_316_p1 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_100_fu_320_p1 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_14_fu_336_p2 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_101_fu_346_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_102_fu_372_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_15_cast_cast_fu_382_p1 : STD_LOGIC_VECTOR (11 downto 0); signal ImagLoc_y_fu_403_p2 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_103_fu_415_p4 : STD_LOGIC_VECTOR (10 downto 0); signal icmp_fu_425_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_25_fu_431_p2 : STD_LOGIC_VECTOR (0 downto 0); signal p_i_i_fu_450_p3 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_i5_fu_461_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_106_fu_466_p1 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_107_fu_470_p1 : STD_LOGIC_VECTOR (1 downto 0); signal y_1_fu_481_p2 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_109_fu_487_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i1_fu_501_p2 : STD_LOGIC_VECTOR (0 downto 0); signal rev_fu_495_p2 : STD_LOGIC_VECTOR (0 downto 0); signal y_1_1_fu_528_p2 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_113_fu_534_p3 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_i2_fu_548_p2 : STD_LOGIC_VECTOR (0 downto 0); signal rev1_fu_542_p2 : STD_LOGIC_VECTOR (0 downto 0); signal locy_fu_571_p2 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_s_fu_585_p3 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_80_fu_591_p3 : STD_LOGIC_VECTOR (1 downto 0); signal locy_1_t_fu_597_p2 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_81_fu_613_p3 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_82_fu_619_p3 : STD_LOGIC_VECTOR (1 downto 0); signal tmp_116_fu_649_p4 : STD_LOGIC_VECTOR (9 downto 0); signal icmp2_fu_659_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_18_cast_fu_634_p1 : STD_LOGIC_VECTOR (11 downto 0); signal ImagLoc_x_fu_670_p2 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_119_fu_684_p3 : STD_LOGIC_VECTOR (0 downto 0); signal rev2_fu_692_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_26_fu_717_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_118_fu_680_p1 : STD_LOGIC_VECTOR (1 downto 0); signal p_assign_fu_739_p3 : STD_LOGIC_VECTOR (10 downto 0); signal p_assign_1_i_fu_745_p3 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_121_fu_751_p1 : STD_LOGIC_VECTOR (1 downto 0); signal sel_tmp1_fu_833_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp5_fu_846_p2 : STD_LOGIC_VECTOR (0 downto 0); signal right_border_buf_0_val_1_2_3_fu_838_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_5_fu_860_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_0_1_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp9_fu_929_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp6_fu_941_p3 : STD_LOGIC_VECTOR (7 downto 0); signal sel_tmp_fu_971_p2 : STD_LOGIC_VECTOR (0 downto 0); signal sel_tmp2_fu_984_p2 : STD_LOGIC_VECTOR (0 downto 0); signal col_buf_0_val_0_0_2_fu_976_p3 : STD_LOGIC_VECTOR (7 downto 0); signal right_border_buf_0_val_1_2_fu_998_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_0_2_fu_1021_p2 : STD_LOGIC_VECTOR (0 downto 0); signal temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_1_1_fu_1055_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_128_1_2_fu_1070_p2 : STD_LOGIC_VECTOR (0 downto 0); signal temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_128_2_1_fu_1095_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_128_2_2_fu_1107_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0); component image_filter_FAST_t_opr_k_buf_val_0_V IS generic ( DataWidth : INTEGER; AddressRange : INTEGER; AddressWidth : INTEGER ); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR (10 downto 0); ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR (7 downto 0); address1 : IN STD_LOGIC_VECTOR (10 downto 0); ce1 : IN STD_LOGIC; we1 : IN STD_LOGIC; d1 : IN STD_LOGIC_VECTOR (7 downto 0) ); end component; begin k_buf_0_val_0_U : component image_filter_FAST_t_opr_k_buf_val_0_V generic map ( DataWidth => 8, AddressRange => 1920, AddressWidth => 11) port map ( clk => ap_clk, reset => ap_rst, address0 => k_buf_0_val_0_address0, ce0 => k_buf_0_val_0_ce0, q0 => k_buf_0_val_0_q0, address1 => k_buf_0_val_0_address1, ce1 => k_buf_0_val_0_ce1, we1 => k_buf_0_val_0_we1, d1 => k_buf_0_val_0_d1); k_buf_0_val_1_U : component image_filter_FAST_t_opr_k_buf_val_0_V generic map ( DataWidth => 8, AddressRange => 1920, AddressWidth => 11) port map ( clk => ap_clk, reset => ap_rst, address0 => k_buf_0_val_1_address0, ce0 => k_buf_0_val_1_ce0, q0 => k_buf_0_val_1_q0, address1 => k_buf_0_val_1_address1, ce1 => k_buf_0_val_1_ce1, we1 => k_buf_0_val_1_we1, d1 => k_buf_0_val_1_d1); k_buf_0_val_2_U : component image_filter_FAST_t_opr_k_buf_val_0_V generic map ( DataWidth => 8, AddressRange => 1920, AddressWidth => 11) port map ( clk => ap_clk, reset => ap_rst, address0 => k_buf_0_val_2_address0, ce0 => k_buf_0_val_2_ce0, q0 => k_buf_0_val_2_q0, address1 => k_buf_0_val_2_address1, ce1 => k_buf_0_val_2_ce1, we1 => k_buf_0_val_2_we1, d1 => k_buf_0_val_2_d1); -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_done_reg assign process. -- ap_done_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_done_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_continue)) then ap_done_reg <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then ap_done_reg <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_19_fu_638_p2))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it3 assign process. -- ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it3 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it4 assign process. -- ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then if (not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2))) then ap_reg_ppiten_pp0_it4 <= ap_const_logic_0; elsif ((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) then ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3; end if; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it5 assign process. -- ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it5 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it6 assign process. -- ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it6 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it7 assign process. -- ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; else if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then ap_reg_ppiten_pp0_it7 <= ap_const_logic_0; end if; end if; end if; end process; -- p_012_0_i_i_reg_252 assign process. -- p_012_0_i_i_reg_252_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_4)) then p_012_0_i_i_reg_252 <= i_V_reg_1286; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then p_012_0_i_i_reg_252 <= ap_const_lv11_0; end if; end if; end process; -- p_025_0_i_i_reg_263 assign process. -- p_025_0_i_i_reg_263_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then p_025_0_i_i_reg_263 <= j_V_fu_643_p2; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then p_025_0_i_i_reg_263 <= ap_const_lv11_0; end if; end if; end process; -- src_kernel_win_0_val_0_1_fu_106 assign process. -- src_kernel_win_0_val_0_1_fu_106_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then src_kernel_win_0_val_0_1_fu_106 <= right_border_buf_0_val_2_0_reg_1457; elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then src_kernel_win_0_val_0_1_fu_106 <= col_buf_0_val_0_0_9_fu_989_p3; elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then src_kernel_win_0_val_0_1_fu_106 <= src_kernel_win_0_val_0_0_fu_934_p3; end if; end if; end process; -- src_kernel_win_0_val_1_1_fu_122 assign process. -- src_kernel_win_0_val_1_1_fu_122_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2))) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2))))) then src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_0_reg_1464; elsif (((not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0)) or (not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it2) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it2) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0))))) then src_kernel_win_0_val_1_1_fu_122 <= right_border_buf_0_val_1_2_11_fu_1006_p3; elsif ((((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0)) or ((ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))))) then src_kernel_win_0_val_1_1_fu_122 <= src_kernel_win_0_val_1_0_fu_946_p3; end if; end if; end process; -- src_kernel_win_0_val_2_1_fu_118 assign process. -- src_kernel_win_0_val_2_1_fu_118_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and not((col_assign_1_reg_1451 = ap_const_lv2_1)) and not((col_assign_1_reg_1451 = ap_const_lv2_0)))) then src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_2_fu_174; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_0))) then src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_0_fu_166; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_i_reg_1405_pp0_it1) and (col_assign_1_reg_1451 = ap_const_lv2_1))) then src_kernel_win_0_val_2_1_fu_118 <= right_border_buf_0_val_0_1_fu_170; elsif (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and not((locy_2_t_reg_1379 = ap_const_lv2_1)) and not((locy_2_t_reg_1379 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and (ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_120_reg_1414_pp0_it1))))) then src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_2_q0; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_0))) then src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_0_q0; elsif ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_lv1_0 = brmerge_reg_1383) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = tmp_104_reg_1306) and (locy_2_t_reg_1379 = ap_const_lv2_1))) then src_kernel_win_0_val_2_1_fu_118 <= k_buf_0_val_1_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))) then ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 <= col_assign_1_reg_1451; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6 <= ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5; ap_reg_ppstg_or_cond2_reg_1419_pp0_it2 <= ap_reg_ppstg_or_cond2_reg_1419_pp0_it1; ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4 <= src_kernel_win_0_val_0_1_6_reg_1483; ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4; ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5 <= src_kernel_win_0_val_0_1_lo_reg_1511; ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it5; ap_reg_ppstg_tmp_120_reg_1414_pp0_it2 <= ap_reg_ppstg_tmp_120_reg_1414_pp0_it1; ap_reg_ppstg_tmp_19_reg_1387_pp0_it2 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it1; ap_reg_ppstg_tmp_19_reg_1387_pp0_it3 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it2; ap_reg_ppstg_tmp_19_reg_1387_pp0_it4 <= ap_reg_ppstg_tmp_19_reg_1387_pp0_it3; ap_reg_ppstg_tmp_i_reg_1405_pp0_it2 <= ap_reg_ppstg_tmp_i_reg_1405_pp0_it1; src_kernel_win_0_val_0_1_6_reg_1483 <= src_kernel_win_0_val_0_1_fu_106; src_kernel_win_0_val_1_1_6_reg_1490 <= src_kernel_win_0_val_1_1_fu_122; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then ap_reg_ppstg_col_assign_reg_1427_pp0_it1 <= col_assign_reg_1427; ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1 <= or_cond219_i_i_reg_1396; ap_reg_ppstg_or_cond2_reg_1419_pp0_it1 <= or_cond2_reg_1419; ap_reg_ppstg_tmp_120_reg_1414_pp0_it1 <= tmp_120_reg_1414; ap_reg_ppstg_tmp_19_reg_1387_pp0_it1 <= tmp_19_reg_1387; ap_reg_ppstg_tmp_29_reg_1423_pp0_it1 <= tmp_29_reg_1423; ap_reg_ppstg_tmp_i_reg_1405_pp0_it1 <= tmp_i_reg_1405; tmp_19_reg_1387 <= tmp_19_fu_638_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then brmerge_reg_1383 <= brmerge_fu_630_p2; locy_2_t_reg_1379 <= locy_2_t_fu_625_p2; sel_tmp3_reg_1364 <= sel_tmp3_fu_579_p2; sel_tmp4_reg_1369 <= sel_tmp4_fu_602_p2; sel_tmp7_reg_1374 <= sel_tmp7_fu_607_p2; sel_tmp8_reg_1359 <= sel_tmp8_fu_575_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)) and (ap_const_lv1_0 = or_cond2_reg_1419) and (ap_const_lv1_0 = tmp_120_reg_1414) and (ap_const_lv1_0 = tmp_i_reg_1405))) then col_assign_1_reg_1451 <= col_assign_1_fu_762_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)) and (ap_const_lv1_0 = tmp_29_fu_729_p2))) then col_assign_reg_1427 <= col_assign_fu_734_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then col_buf_0_val_0_0_3_fu_114 <= k_buf_0_val_0_q0; right_border_buf_0_val_0_2_fu_174 <= k_buf_0_val_2_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1))) then col_buf_0_val_0_0_5_fu_130 <= k_buf_0_val_0_q0; right_border_buf_0_val_0_1_fu_170 <= k_buf_0_val_2_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) then col_buf_0_val_0_0_6_fu_138 <= k_buf_0_val_0_q0; right_border_buf_0_val_0_0_fu_166 <= k_buf_0_val_2_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_48))) then heightloop_reg_1240 <= heightloop_fu_324_p2; p_neg226_i_i_cast_reg_1255 <= p_neg226_i_i_cast_fu_350_p2; ref_cast_reg_1267(0) <= ref_cast_fu_362_p1(0); ref_cast_reg_1267(1) <= ref_cast_fu_362_p1(1); ref_cast_reg_1267(2) <= ref_cast_fu_362_p1(2); ref_cast_reg_1267(3) <= ref_cast_fu_362_p1(3); ref_cast_reg_1267(4) <= ref_cast_fu_362_p1(4); ref_cast_reg_1267(5) <= ref_cast_fu_362_p1(5); ref_cast_reg_1267(6) <= ref_cast_fu_362_p1(6); ref_cast_reg_1267(7) <= ref_cast_fu_362_p1(7); ref_cast_reg_1267(8) <= ref_cast_fu_362_p1(8); ref_cast_reg_1267(9) <= ref_cast_fu_362_p1(9); ref_cast_reg_1267(10) <= ref_cast_fu_362_p1(10); ref_reg_1261 <= ref_fu_356_p2; tmp_14_cast_reg_1250(0) <= tmp_14_cast_fu_342_p1(0); tmp_14_cast_reg_1250(1) <= tmp_14_cast_fu_342_p1(1); tmp_14_cast_reg_1250(2) <= tmp_14_cast_fu_342_p1(2); tmp_14_cast_reg_1250(3) <= tmp_14_cast_fu_342_p1(3); tmp_14_cast_reg_1250(4) <= tmp_14_cast_fu_342_p1(4); tmp_14_cast_reg_1250(5) <= tmp_14_cast_fu_342_p1(5); tmp_14_cast_reg_1250(6) <= tmp_14_cast_fu_342_p1(6); tmp_14_cast_reg_1250(7) <= tmp_14_cast_fu_342_p1(7); tmp_14_cast_reg_1250(8) <= tmp_14_cast_fu_342_p1(8); tmp_14_cast_reg_1250(9) <= tmp_14_cast_fu_342_p1(9); tmp_14_cast_reg_1250(10) <= tmp_14_cast_fu_342_p1(10); tmp_2_i1_reg_1277 <= tmp_2_i1_fu_376_p2; tmp_2_i_reg_1272 <= tmp_2_i_fu_366_p2; widthloop_reg_1245 <= widthloop_fu_330_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then i_V_reg_1286 <= i_V_fu_391_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_reg_1387)))) then k_buf_0_val_0_addr_reg_1433 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_1_addr_reg_1439 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_2_addr_reg_1445 <= tmp_69_fu_755_p1(11 - 1 downto 0); end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then or_cond219_i_i_reg_1396 <= or_cond219_i_i_fu_665_p2; or_cond_i_reg_1409 <= or_cond_i_fu_703_p2; tmp_117_reg_1400 <= tmp_117_fu_676_p1; tmp_120_reg_1414 <= ImagLoc_x_fu_670_p2(11 downto 11); tmp_i_reg_1405 <= tmp_i_fu_698_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)))) then or_cond2_reg_1419 <= or_cond2_fu_723_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((tmp_16_fu_386_p2 = ap_const_lv1_0)))) then or_cond_i1_reg_1322 <= or_cond_i1_fu_506_p2; or_cond_i2_reg_1344 <= or_cond_i2_fu_553_p2; or_cond_reg_1301 <= or_cond_fu_436_p2; tmp_104_reg_1306 <= ImagLoc_y_fu_403_p2(11 downto 11); tmp_105_reg_1310 <= tmp_105_fu_457_p1; tmp_108_reg_1316 <= tmp_108_fu_473_p3; tmp_110_reg_1327 <= y_1_fu_481_p2(11 downto 11); tmp_111_reg_1332 <= tmp_111_fu_520_p1; tmp_112_reg_1337 <= tmp_112_fu_524_p1; tmp_114_reg_1349 <= y_1_1_fu_528_p2(11 downto 11); tmp_115_reg_1354 <= tmp_115_fu_567_p1; tmp_17_reg_1291 <= tmp_17_fu_397_p2; tmp_23_reg_1296 <= tmp_23_fu_409_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then right_border_buf_0_val_1_0_reg_1464 <= k_buf_0_val_1_q0; right_border_buf_0_val_2_0_reg_1457 <= k_buf_0_val_0_q0; src_kernel_win_0_val_2_0_reg_1471 <= k_buf_0_val_2_q0; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) and not((ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0))) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) and (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0)))) then right_border_buf_0_val_1_2_1_fu_142 <= right_border_buf_0_val_1_2_8_fu_877_p3; right_border_buf_0_val_1_2_2_fu_146 <= right_border_buf_0_val_1_2_6_fu_868_p3; right_border_buf_0_val_1_2_7_fu_150 <= right_border_buf_0_val_1_2_4_fu_851_p3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it3)))) then src_kernel_win_0_val_0_1_lo_reg_1511 <= src_kernel_win_0_val_0_1_fu_106; src_kernel_win_0_val_1_1_lo_reg_1517 <= src_kernel_win_0_val_1_1_fu_122; temp_0_i_i_i_057_i_i_1_1_1_reg_1523 <= temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it4)))) then src_kernel_win_0_val_0_2_fu_110 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it4; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it4)))) then src_kernel_win_0_val_0_2_lo_reg_1529 <= src_kernel_win_0_val_0_2_fu_110; temp_0_i_i_i_057_i_i_1_1_2_reg_1534 <= temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3; tmp_128_2_reg_1539 <= tmp_128_2_fu_1080_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)))) then src_kernel_win_0_val_1_2_fu_126 <= src_kernel_win_0_val_1_1_fu_122; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it2)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it2)))) then src_kernel_win_0_val_1_2_lo_reg_1496 <= src_kernel_win_0_val_1_2_fu_126; temp_0_i_i_i_057_i_i_1_0_2_reg_1501 <= temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3; tmp_128_1_reg_1506 <= tmp_128_1_fu_1033_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then src_kernel_win_0_val_2_2_fu_134 <= src_kernel_win_0_val_2_1_fu_118; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it1)))) then temp_0_i_i_i_057_i_i_1_0_1_reg_1477 <= temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it5)))) then temp_0_i_i_i_057_i_i_1_2_1_reg_1544 <= temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = tmp_19_fu_638_p2)) and not((ap_const_lv1_0 = or_cond2_fu_723_p2)))) then tmp_29_reg_1423 <= tmp_29_fu_729_p2; end if; end if; end process; tmp_14_cast_reg_1250(11) <= '0'; ref_cast_reg_1267(11) <= '0'; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_48, tmp_16_fu_386_p2, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not(ap_sig_bdd_48)) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if ((tmp_16_fu_386_p2 = ap_const_lv1_0)) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_st3_fsm_2; end if; when ap_ST_st3_fsm_2 => ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3; when ap_ST_pp0_stg0_fsm_3 => if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4)))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3; elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it6))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it3) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it4))))) then ap_NS_fsm <= ap_ST_st12_fsm_4; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_3; end if; when ap_ST_st12_fsm_4 => ap_NS_fsm <= ap_ST_st2_fsm_1; when others => ap_NS_fsm <= "XXXXX"; end case; end process; ImagLoc_x_fu_670_p2 <= std_logic_vector(unsigned(tmp_18_cast_fu_634_p1) + unsigned(ap_const_lv12_FFF)); ImagLoc_y_fu_403_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFC)); -- ap_done assign process. -- ap_done_assign_proc : process(ap_done_reg, ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2) begin if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0)))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_16_fu_386_p2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_16_fu_386_p2 = ap_const_lv1_0))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_116 assign process. -- ap_sig_bdd_116_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_116 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_bdd_135 assign process. -- ap_sig_bdd_135_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_135 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_154 assign process. -- ap_sig_bdd_154_assign_proc : process(p_src_data_stream_V_empty_n, brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1) begin ap_sig_bdd_154 <= ((p_src_data_stream_V_empty_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1))); end process; -- ap_sig_bdd_172 assign process. -- ap_sig_bdd_172_assign_proc : process(p_dst_data_stream_V_full_n, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6) begin ap_sig_bdd_172 <= ((p_dst_data_stream_V_full_n = ap_const_logic_0) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6))); end process; -- ap_sig_bdd_24 assign process. -- ap_sig_bdd_24_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_24 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_355 assign process. -- ap_sig_bdd_355_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_355 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); end process; -- ap_sig_bdd_48 assign process. -- ap_sig_bdd_48_assign_proc : process(ap_start, ap_done_reg) begin ap_sig_bdd_48 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1)); end process; -- ap_sig_bdd_76 assign process. -- ap_sig_bdd_76_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_76 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_cseq_ST_pp0_stg0_fsm_3 assign process. -- ap_sig_cseq_ST_pp0_stg0_fsm_3_assign_proc : process(ap_sig_bdd_135) begin if (ap_sig_bdd_135) then ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_3 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st12_fsm_4 assign process. -- ap_sig_cseq_ST_st12_fsm_4_assign_proc : process(ap_sig_bdd_355) begin if (ap_sig_bdd_355) then ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_1; else ap_sig_cseq_ST_st12_fsm_4 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_24) begin if (ap_sig_bdd_24) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_76) begin if (ap_sig_bdd_76) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st3_fsm_2 assign process. -- ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_116) begin if (ap_sig_bdd_116) then ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0; end if; end process; brmerge_fu_630_p2 <= (tmp_23_reg_1296 or or_cond_reg_1301); col_assign_1_fu_762_p2 <= std_logic_vector(unsigned(tmp_121_fu_751_p1) + unsigned(p_neg226_i_i_cast_reg_1255)); col_assign_fu_734_p2 <= std_logic_vector(unsigned(tmp_118_fu_680_p1) + unsigned(p_neg226_i_i_cast_reg_1255)); col_buf_0_val_0_0_2_fu_976_p3 <= col_buf_0_val_0_0_5_fu_130 when (sel_tmp_fu_971_p2(0) = '1') else col_buf_0_val_0_0_3_fu_114; col_buf_0_val_0_0_9_fu_989_p3 <= col_buf_0_val_0_0_6_fu_138 when (sel_tmp2_fu_984_p2(0) = '1') else col_buf_0_val_0_0_2_fu_976_p3; heightloop_fu_324_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_5)); i_V_fu_391_p2 <= std_logic_vector(unsigned(p_012_0_i_i_reg_252) + unsigned(ap_const_lv11_1)); icmp2_fu_659_p2 <= "0" when (tmp_116_fu_649_p4 = ap_const_lv10_0) else "1"; icmp_fu_425_p2 <= "1" when (signed(tmp_103_fu_415_p4) > signed(ap_const_lv11_0)) else "0"; j_V_fu_643_p2 <= std_logic_vector(unsigned(p_025_0_i_i_reg_263) + unsigned(ap_const_lv11_1)); k_buf_0_val_0_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_0_address1 <= k_buf_0_val_0_addr_reg_1433; -- k_buf_0_val_0_ce0 assign process. -- k_buf_0_val_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then k_buf_0_val_0_ce0 <= ap_const_logic_1; else k_buf_0_val_0_ce0 <= ap_const_logic_0; end if; end process; -- k_buf_0_val_0_ce1 assign process. -- k_buf_0_val_0_ce1_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then k_buf_0_val_0_ce1 <= ap_const_logic_1; else k_buf_0_val_0_ce1 <= ap_const_logic_0; end if; end process; k_buf_0_val_0_d1 <= p_src_data_stream_V_dout; -- k_buf_0_val_0_we1 assign process. -- k_buf_0_val_0_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7))))))) then k_buf_0_val_0_we1 <= ap_const_logic_1; else k_buf_0_val_0_we1 <= ap_const_logic_0; end if; end process; k_buf_0_val_1_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_1_address1 <= k_buf_0_val_1_addr_reg_1439; -- k_buf_0_val_1_ce0 assign process. -- k_buf_0_val_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then k_buf_0_val_1_ce0 <= ap_const_logic_1; else k_buf_0_val_1_ce0 <= ap_const_logic_0; end if; end process; -- k_buf_0_val_1_ce1 assign process. -- k_buf_0_val_1_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then k_buf_0_val_1_ce1 <= ap_const_logic_1; else k_buf_0_val_1_ce1 <= ap_const_logic_0; end if; end process; k_buf_0_val_1_d1 <= k_buf_0_val_0_q0; -- k_buf_0_val_1_we1 assign process. -- k_buf_0_val_1_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then k_buf_0_val_1_we1 <= ap_const_logic_1; else k_buf_0_val_1_we1 <= ap_const_logic_0; end if; end process; k_buf_0_val_2_address0 <= tmp_69_fu_755_p1(11 - 1 downto 0); k_buf_0_val_2_address1 <= k_buf_0_val_2_addr_reg_1445; -- k_buf_0_val_2_ce0 assign process. -- k_buf_0_val_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_3, ap_reg_ppiten_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_3) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then k_buf_0_val_2_ce0 <= ap_const_logic_1; else k_buf_0_val_2_ce0 <= ap_const_logic_0; end if; end process; -- k_buf_0_val_2_ce1 assign process. -- k_buf_0_val_2_ce1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then k_buf_0_val_2_ce1 <= ap_const_logic_1; else k_buf_0_val_2_ce1 <= ap_const_logic_0; end if; end process; k_buf_0_val_2_d1 <= k_buf_0_val_1_q0; -- k_buf_0_val_2_we1 assign process. -- k_buf_0_val_2_we1_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7, ap_reg_ppstg_tmp_29_reg_1423_pp0_it1) begin if (((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and (ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1)) or (not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))) and not((ap_const_lv1_0 = ap_reg_ppstg_tmp_29_reg_1423_pp0_it1))))) then k_buf_0_val_2_we1 <= ap_const_logic_1; else k_buf_0_val_2_we1 <= ap_const_logic_0; end if; end process; locy_1_t_fu_597_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_80_fu_591_p3)); locy_2_t_fu_625_p2 <= std_logic_vector(unsigned(tmp_112_reg_1337) - unsigned(tmp_82_fu_619_p3)); locy_fu_571_p2 <= std_logic_vector(unsigned(tmp_105_reg_1310) - unsigned(tmp_108_reg_1316)); or_cond219_i_i_fu_665_p2 <= (tmp_17_reg_1291 and icmp2_fu_659_p2); or_cond2_fu_723_p2 <= (tmp_26_fu_717_p2 and tmp_i_fu_698_p2); or_cond_fu_436_p2 <= (icmp_fu_425_p2 and tmp_25_fu_431_p2); or_cond_i1_fu_506_p2 <= (tmp_i1_fu_501_p2 and rev_fu_495_p2); or_cond_i2_fu_553_p2 <= (tmp_i2_fu_548_p2 and rev1_fu_542_p2); or_cond_i_fu_703_p2 <= (tmp_i_fu_698_p2 and rev2_fu_692_p2); p_assign_1_i_fu_745_p3 <= tmp_117_reg_1400 when (or_cond_i_reg_1409(0) = '1') else p_assign_fu_739_p3; p_assign_fu_739_p3 <= ap_const_lv11_0 when (tmp_120_reg_1414(0) = '1') else tmp_2_i_reg_1272; p_dst_data_stream_V_din <= ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6 when (tmp_128_2_2_fu_1107_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_2_1_reg_1544; -- p_dst_data_stream_V_write assign process. -- p_dst_data_stream_V_write_assign_proc : process(ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if ((not((ap_const_lv1_0 = ap_reg_ppstg_or_cond219_i_i_reg_1396_pp0_it6)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then p_dst_data_stream_V_write <= ap_const_logic_1; else p_dst_data_stream_V_write <= ap_const_logic_0; end if; end process; p_i_i_fu_450_p3 <= ap_const_lv11_2 when (tmp_25_fu_431_p2(0) = '1') else ref_reg_1261; p_neg226_i_i_cast_fu_350_p2 <= (tmp_101_fu_346_p1 xor ap_const_lv2_3); -- p_src_data_stream_V_read assign process. -- p_src_data_stream_V_read_assign_proc : process(brmerge_reg_1383, ap_reg_ppstg_tmp_19_reg_1387_pp0_it1, ap_reg_ppstg_or_cond2_reg_1419_pp0_it1, ap_sig_bdd_154, ap_reg_ppiten_pp0_it2, ap_sig_bdd_172, ap_reg_ppiten_pp0_it7) begin if ((not((ap_const_lv1_0 = ap_reg_ppstg_tmp_19_reg_1387_pp0_it1)) and not((ap_const_lv1_0 = brmerge_reg_1383)) and not((ap_const_lv1_0 = ap_reg_ppstg_or_cond2_reg_1419_pp0_it1)) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_154 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)) or (ap_sig_bdd_172 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it7)))))) then p_src_data_stream_V_read <= ap_const_logic_1; else p_src_data_stream_V_read <= ap_const_logic_0; end if; end process; ref_cast_fu_362_p1 <= std_logic_vector(resize(unsigned(ref_fu_356_p2),12)); ref_fu_356_p2 <= std_logic_vector(unsigned(tmp_fu_316_p1) + unsigned(ap_const_lv11_7FF)); rev1_fu_542_p2 <= (tmp_113_fu_534_p3 xor ap_const_lv1_1); rev2_fu_692_p2 <= (tmp_119_fu_684_p3 xor ap_const_lv1_1); rev_fu_495_p2 <= (tmp_109_fu_487_p3 xor ap_const_lv1_1); right_border_buf_0_val_1_2_11_fu_1006_p3 <= right_border_buf_0_val_1_2_1_fu_142 when (sel_tmp2_fu_984_p2(0) = '1') else right_border_buf_0_val_1_2_fu_998_p3; right_border_buf_0_val_1_2_3_fu_838_p3 <= right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp1_fu_833_p2(0) = '1') else k_buf_0_val_1_q0; right_border_buf_0_val_1_2_4_fu_851_p3 <= right_border_buf_0_val_1_2_7_fu_150 when (sel_tmp5_fu_846_p2(0) = '1') else right_border_buf_0_val_1_2_3_fu_838_p3; right_border_buf_0_val_1_2_5_fu_860_p3 <= k_buf_0_val_1_q0 when (sel_tmp1_fu_833_p2(0) = '1') else right_border_buf_0_val_1_2_2_fu_146; right_border_buf_0_val_1_2_6_fu_868_p3 <= right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp5_fu_846_p2(0) = '1') else right_border_buf_0_val_1_2_5_fu_860_p3; right_border_buf_0_val_1_2_8_fu_877_p3 <= k_buf_0_val_1_q0 when (sel_tmp5_fu_846_p2(0) = '1') else right_border_buf_0_val_1_2_1_fu_142; right_border_buf_0_val_1_2_fu_998_p3 <= right_border_buf_0_val_1_2_2_fu_146 when (sel_tmp_fu_971_p2(0) = '1') else right_border_buf_0_val_1_2_7_fu_150; sel_tmp1_fu_833_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_1) else "0"; sel_tmp2_fu_984_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_0) else "0"; sel_tmp3_fu_579_p2 <= "1" when (locy_fu_571_p2 = ap_const_lv2_1) else "0"; sel_tmp4_fu_602_p2 <= "1" when (tmp_112_reg_1337 = tmp_80_fu_591_p3) else "0"; sel_tmp5_fu_846_p2 <= "1" when (ap_reg_ppstg_col_assign_reg_1427_pp0_it1 = ap_const_lv2_0) else "0"; sel_tmp6_fu_941_p3 <= right_border_buf_0_val_2_0_reg_1457 when (sel_tmp4_reg_1369(0) = '1') else src_kernel_win_0_val_2_0_reg_1471; sel_tmp7_fu_607_p2 <= "1" when (locy_1_t_fu_597_p2 = ap_const_lv2_1) else "0"; sel_tmp8_fu_575_p2 <= "1" when (tmp_105_reg_1310 = tmp_108_reg_1316) else "0"; sel_tmp9_fu_929_p3 <= right_border_buf_0_val_2_0_reg_1457 when (sel_tmp8_reg_1359(0) = '1') else src_kernel_win_0_val_2_0_reg_1471; sel_tmp_fu_971_p2 <= "1" when (ap_reg_ppstg_col_assign_1_reg_1451_pp0_it2 = ap_const_lv2_1) else "0"; src_kernel_win_0_val_0_0_fu_934_p3 <= right_border_buf_0_val_1_0_reg_1464 when (sel_tmp3_reg_1364(0) = '1') else sel_tmp9_fu_929_p3; src_kernel_win_0_val_1_0_fu_946_p3 <= right_border_buf_0_val_1_0_reg_1464 when (sel_tmp7_reg_1374(0) = '1') else sel_tmp6_fu_941_p3; temp_0_i_i_i_057_i_i_1_0_1_fu_910_p3 <= src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_1_fu_904_p2(0) = '1') else src_kernel_win_0_val_2_2_fu_134; temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3 <= src_kernel_win_0_val_2_1_fu_118 when (tmp_128_0_2_fu_1021_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_0_1_reg_1477; temp_0_i_i_i_057_i_i_1_1_1_fu_1060_p3 <= src_kernel_win_0_val_1_1_6_reg_1490 when (tmp_128_1_1_fu_1055_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_1_fu_1050_p3; temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3 <= src_kernel_win_0_val_1_1_lo_reg_1517 when (tmp_128_1_2_fu_1070_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_1_1_reg_1523; temp_0_i_i_i_057_i_i_1_1_fu_1050_p3 <= src_kernel_win_0_val_1_2_lo_reg_1496 when (tmp_128_1_reg_1506(0) = '1') else temp_0_i_i_i_057_i_i_1_0_2_reg_1501; temp_0_i_i_i_057_i_i_1_2_1_fu_1100_p3 <= ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5 when (tmp_128_2_1_fu_1095_p2(0) = '1') else temp_0_i_i_i_057_i_i_1_2_fu_1090_p3; temp_0_i_i_i_057_i_i_1_2_fu_1090_p3 <= src_kernel_win_0_val_0_2_lo_reg_1529 when (tmp_128_2_reg_1539(0) = '1') else temp_0_i_i_i_057_i_i_1_1_2_reg_1534; tmp_100_fu_320_p1 <= p_src_cols_V_read(11 - 1 downto 0); tmp_101_fu_346_p1 <= p_src_cols_V_read(2 - 1 downto 0); tmp_102_fu_372_p1 <= p_src_rows_V_read(2 - 1 downto 0); tmp_103_fu_415_p4 <= ImagLoc_y_fu_403_p2(11 downto 1); tmp_105_fu_457_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0); tmp_106_fu_466_p1 <= ImagLoc_y_fu_403_p2(2 - 1 downto 0); tmp_107_fu_470_p1 <= ref_reg_1261(2 - 1 downto 0); tmp_108_fu_473_p3 <= tmp_106_fu_466_p1 when (tmp_i5_fu_461_p2(0) = '1') else tmp_107_fu_470_p1; tmp_109_fu_487_p3 <= y_1_fu_481_p2(11 downto 11); tmp_111_fu_520_p1 <= y_1_fu_481_p2(2 - 1 downto 0); tmp_112_fu_524_p1 <= p_i_i_fu_450_p3(2 - 1 downto 0); tmp_113_fu_534_p3 <= y_1_1_fu_528_p2(11 downto 11); tmp_115_fu_567_p1 <= y_1_1_fu_528_p2(2 - 1 downto 0); tmp_116_fu_649_p4 <= p_025_0_i_i_reg_263(10 downto 1); tmp_117_fu_676_p1 <= ImagLoc_x_fu_670_p2(11 - 1 downto 0); tmp_118_fu_680_p1 <= ImagLoc_x_fu_670_p2(2 - 1 downto 0); tmp_119_fu_684_p3 <= ImagLoc_x_fu_670_p2(11 downto 11); tmp_121_fu_751_p1 <= p_assign_1_i_fu_745_p3(2 - 1 downto 0); tmp_128_0_1_fu_904_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(src_kernel_win_0_val_2_2_fu_134)) else "0"; tmp_128_0_2_fu_1021_p2 <= "1" when (unsigned(src_kernel_win_0_val_2_1_fu_118) > unsigned(temp_0_i_i_i_057_i_i_1_0_1_reg_1477)) else "0"; tmp_128_1_1_fu_1055_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_6_reg_1490) > unsigned(temp_0_i_i_i_057_i_i_1_1_fu_1050_p3)) else "0"; tmp_128_1_2_fu_1070_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_1_lo_reg_1517) > unsigned(temp_0_i_i_i_057_i_i_1_1_1_reg_1523)) else "0"; tmp_128_1_fu_1033_p2 <= "1" when (unsigned(src_kernel_win_0_val_1_2_fu_126) > unsigned(temp_0_i_i_i_057_i_i_1_0_2_fu_1026_p3)) else "0"; tmp_128_2_1_fu_1095_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_6_reg_1483_pp0_it5) > unsigned(temp_0_i_i_i_057_i_i_1_2_fu_1090_p3)) else "0"; tmp_128_2_2_fu_1107_p2 <= "1" when (unsigned(ap_reg_ppstg_src_kernel_win_0_val_0_1_lo_reg_1511_pp0_it6) > unsigned(temp_0_i_i_i_057_i_i_1_2_1_reg_1544)) else "0"; tmp_128_2_fu_1080_p2 <= "1" when (unsigned(src_kernel_win_0_val_0_2_fu_110) > unsigned(temp_0_i_i_i_057_i_i_1_1_2_fu_1074_p3)) else "0"; tmp_14_cast_fu_342_p1 <= std_logic_vector(resize(unsigned(tmp_14_fu_336_p2),12)); tmp_14_fu_336_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FD)); tmp_15_cast_cast_fu_382_p1 <= std_logic_vector(resize(unsigned(p_012_0_i_i_reg_252),12)); tmp_16_fu_386_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) < unsigned(heightloop_reg_1240)) else "0"; tmp_17_fu_397_p2 <= "1" when (unsigned(p_012_0_i_i_reg_252) > unsigned(ap_const_lv11_4)) else "0"; tmp_18_cast_fu_634_p1 <= std_logic_vector(resize(unsigned(p_025_0_i_i_reg_263),12)); tmp_19_fu_638_p2 <= "1" when (unsigned(p_025_0_i_i_reg_263) < unsigned(widthloop_reg_1245)) else "0"; tmp_23_fu_409_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ap_const_lv12_FFF)) else "0"; tmp_25_fu_431_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(ref_cast_reg_1267)) else "0"; tmp_26_fu_717_p2 <= "0" when (p_025_0_i_i_reg_263 = ap_const_lv11_0) else "1"; tmp_29_fu_729_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(tmp_14_cast_reg_1250)) else "0"; tmp_2_i1_fu_376_p2 <= std_logic_vector(unsigned(tmp_102_fu_372_p1) + unsigned(ap_const_lv2_3)); tmp_2_i_fu_366_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_7FF)); tmp_69_fu_755_p1 <= std_logic_vector(resize(unsigned(p_assign_1_i_fu_745_p3),64)); tmp_80_fu_591_p3 <= tmp_111_reg_1332 when (or_cond_i1_reg_1322(0) = '1') else tmp_s_fu_585_p3; tmp_81_fu_613_p3 <= ap_const_lv2_0 when (tmp_114_reg_1349(0) = '1') else tmp_2_i1_reg_1277; tmp_82_fu_619_p3 <= tmp_115_reg_1354 when (or_cond_i2_reg_1344(0) = '1') else tmp_81_fu_613_p3; tmp_fu_316_p1 <= p_src_rows_V_read(11 - 1 downto 0); tmp_i1_fu_501_p2 <= "1" when (signed(y_1_fu_481_p2) < signed(p_src_rows_V_read)) else "0"; tmp_i2_fu_548_p2 <= "1" when (signed(y_1_1_fu_528_p2) < signed(p_src_rows_V_read)) else "0"; tmp_i5_fu_461_p2 <= "1" when (signed(ImagLoc_y_fu_403_p2) < signed(p_src_rows_V_read)) else "0"; tmp_i_fu_698_p2 <= "1" when (signed(ImagLoc_x_fu_670_p2) < signed(p_src_cols_V_read)) else "0"; tmp_s_fu_585_p3 <= ap_const_lv2_0 when (tmp_110_reg_1327(0) = '1') else tmp_2_i1_reg_1277; widthloop_fu_330_p2 <= std_logic_vector(unsigned(tmp_100_fu_320_p1) + unsigned(ap_const_lv11_2)); y_1_1_fu_528_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFA)); y_1_fu_481_p2 <= std_logic_vector(unsigned(tmp_15_cast_cast_fu_382_p1) + unsigned(ap_const_lv12_FFB)); end behav;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_dre.vhd

6

88906

------------------------------------------------------------------------------- -- axi_datamover_s2mm_dre.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_dre.vhd -- -- Description: -- This VHDL design implements a 64 bit wide (8 byte lane) function that -- realigns an arbitrarily aligned input data stream to an arbitrarily aligned -- output data stream. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n; use axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n; use axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_dre is Generic ( C_DWIDTH : Integer := 64; -- Sets the native data width of the DRE C_ALIGN_WIDTH : Integer := 3 -- Sets the width of the alignment control inputs -- Should be log2(C_DWIDTH) ); port ( -- Clock and Reset Input ---------------------------------------------- -- dre_clk : In std_logic; -- dre_rst : In std_logic; -- ---------------------------------------------------------------------- -- Alignment Control (Independent from Stream Input timing) ---------- -- dre_align_ready : Out std_logic; -- dre_align_valid : In std_logic; -- dre_use_autodest : In std_logic; -- dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); -- dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); -- ---------------------------------------------------------------------- -- Flush Control (Aligned to input Stream timing) -------------------- -- dre_flush : In std_logic; -- ---------------------------------------------------------------------- -- Stream Input Channel ---------------------------------------------- -- dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); -- dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); -- dre_in_tlast : In std_logic; -- dre_in_tvalid : In std_logic; -- dre_in_tready : Out std_logic; -- ---------------------------------------------------------------------- -- Stream Output Channel --------------------------------------------- -- dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); -- dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); -- dre_out_tlast : Out std_logic; -- dre_out_tvalid : Out std_logic; -- dre_out_tready : In std_logic -- ---------------------------------------------------------------------- ); end entity axi_datamover_s2mm_dre; architecture implementation of axi_datamover_s2mm_dre is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Functions ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_index -- -- Function Description: -- This function calculates the bus bit index corresponding -- to the MSB of the Slice lane index input and the Slice width. -- ------------------------------------------------------------------- function get_start_index (lane_index : integer; lane_width : integer) return integer is Variable bit_index_start : Integer := 0; begin bit_index_start := lane_index*lane_width; return(bit_index_start); end function get_start_index; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_index -- -- Function Description: -- This function calculates the bus bit index corresponding -- to the LSB of the Slice lane index input and the Slice width. -- ------------------------------------------------------------------- function get_end_index (lane_index : integer; lane_width : integer) return integer is Variable bit_index_end : Integer := 0; begin bit_index_end := (lane_index*lane_width) + (lane_width-1); return(bit_index_end); end function get_end_index; -- Constants Constant BYTE_WIDTH : integer := 8; -- bits Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH; Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1; Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1; Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0'); Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH; Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH; Constant NO_STRB_SET_VALUE : integer := 0; -- Types type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of std_logic_vector(SLICE_WIDTH-1 downto 0); -- Signals signal sig_input_data_reg : sig_byte_lane_type; signal sig_delay_data_reg : sig_byte_lane_type; signal sig_output_data_reg : sig_byte_lane_type; signal sig_pass_mux_bus : sig_byte_lane_type; signal sig_delay_mux_bus : sig_byte_lane_type; signal sig_final_mux_bus : sig_byte_lane_type; Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0'); Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0'); Signal sig_dre_flush_i : std_logic := '0'; Signal sig_pipeline_halt : std_logic := '0'; Signal sig_dre_tvalid_i : std_logic := '0'; Signal sig_input_accept : std_logic := '0'; Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0'); signal sig_final_mux_has_tlast : std_logic := '0'; signal sig_tlast_out : std_logic := '0'; Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0'); Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0'); Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0'); Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0'); Signal sig_auto_flush : std_logic := '0'; Signal sig_flush_db1 : std_logic := '0'; Signal sig_flush_db2 : std_logic := '0'; signal sig_flush_db1_complete : std_logic := '0'; signal sig_flush_db2_complete : std_logic := '0'; signal sig_output_xfer : std_logic := '0'; signal sig_advance_pipe_data : std_logic := '0'; Signal sig_flush_reg : std_logic := '0'; Signal sig_input_flush_stall : std_logic := '0'; Signal sig_cntl_accept : std_logic := '0'; Signal sig_dre_halted : std_logic := '0'; begin --(architecture implementation) -- Misc port assignments dre_align_ready <= sig_dre_halted or sig_flush_db2_complete ; dre_in_tready <= sig_input_accept ; dre_out_tstrb <= sig_dre_strb_out_i ; dre_out_tdata <= sig_dre_data_out_i ; dre_out_tvalid <= sig_dre_tvalid_i ; dre_out_tlast <= sig_tlast_out ; -- Internal logic sig_cntl_accept <= dre_align_valid and (sig_dre_halted or sig_flush_db2_complete); sig_pipeline_halt <= sig_dre_halted or (sig_dre_tvalid_i and not(dre_out_tready)); sig_output_xfer <= sig_dre_tvalid_i and dre_out_tready; sig_advance_pipe_data <= (dre_in_tvalid or sig_dre_flush_i) and not(sig_pipeline_halt); sig_dre_flush_i <= sig_auto_flush ; sig_input_accept <= dre_in_tvalid and not(sig_pipeline_halt) and not(sig_input_flush_stall); sig_flush_db1_complete <= sig_flush_db1 and not(sig_pipeline_halt); sig_flush_db2_complete <= sig_flush_db2 and not(sig_pipeline_halt); sig_auto_flush <= sig_flush_db1 or sig_flush_db2; sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation sig_last_written_strb <= sig_dre_strb_out_i; ------------------------------------------------------------------------------------ -- DRE Halted logic ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DRE_HALTED_FLOP -- -- Process Description: -- Implements a flop for the Halted state flag. All DRE -- operation is halted until a new alignment control is -- loaded. The DRE automatically goes into halted state -- at reset and at completion of a flush operation. -- ------------------------------------------------------------- IMP_DRE_HALTED_FLOP : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or (sig_flush_db2_complete = '1' and dre_align_valid = '0'))then sig_dre_halted <= '1'; -- default to halted state elsif (sig_cntl_accept = '1') then sig_dre_halted <= '0'; else null; -- hold current state end if; end if; end process IMP_DRE_HALTED_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_FLUSH_IN -- -- Process Description: -- Input Register for the flush command -- ------------------------------------------------------------- REG_FLUSH_IN : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or sig_flush_db2 = '1') then sig_flush_reg <= '0'; elsif (sig_input_accept = '1') then sig_flush_reg <= dre_flush; else null; -- hold current state end if; end if; end process REG_FLUSH_IN; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_FINAL_MUX_TLAST_OR -- -- Process Description: -- Look at all associated tlast bits in the Final Mux output -- and detirmine if any are set. -- -- ------------------------------------------------------------- DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus) Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0); begin lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX); for tlast_index in 1 to NUM_BYTE_LANES-1 loop lvar_finalmux_or(tlast_index) := lvar_finalmux_or(tlast_index-1) or sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX); end loop; sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1); end process DO_FINAL_MUX_TLAST_OR; ------------------------------------------------------------------------ ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: GEN_FLUSH_DB1 -- -- Process Description: -- Creates the first sequential flag indicating that the DRE needs to flush out -- current contents before allowing any new inputs. This is -- triggered by the receipt of the TLAST. -- ------------------------------------------------------------- GEN_FLUSH_DB1 : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then If (dre_rst = '1' or sig_flush_db2_complete = '1') Then sig_flush_db1 <= '0'; Elsif (sig_input_accept = '1') Then sig_flush_db1 <= dre_flush or dre_in_tlast; else null; -- hold state end if; -- else -- null; end if; end process GEN_FLUSH_DB1; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: GEN_FLUSH_DB2 -- -- Process Description: -- Creates a second sequential flag indicating that the DRE -- is flushing out current contents. This is -- triggered by the assertion of the first sequential flush -- flag. -- ------------------------------------------------------------- GEN_FLUSH_DB2 : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then If (dre_rst = '1' or sig_flush_db2_complete = '1') Then sig_flush_db2 <= '0'; elsif (sig_pipeline_halt = '0') then sig_flush_db2 <= sig_flush_db1; else null; -- hold state end if; -- else -- null; end if; end process GEN_FLUSH_DB2; ------------------------------------------------------------- -- Combinational Process -- -- Label: CALC_DEST_STRB_ALIGN -- -- Process Description: -- This process calculates the byte lane position of the -- left-most STRB that is unasserted on the DRE output STRB bus. -- The resulting value is used as the Destination Alignment -- Vector for the DRE. -- ------------------------------------------------------------- CALC_DEST_STRB_ALIGN : process (sig_last_written_strb) Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES; Variable lvar_strb_hole_detected : Boolean; Variable lvar_first_strb_assert_found : Boolean; Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES; Begin lvar_loop_count := NUM_BYTE_LANES; lvar_last_strb_hole_position := 0; lvar_strb_hole_detected := FALSE; lvar_first_strb_assert_found := FALSE; -- Search through the output STRB bus starting with the MSByte while (lvar_loop_count > 0) loop If (sig_last_written_strb(lvar_loop_count-1) = '0' and lvar_first_strb_assert_found = FALSE) Then lvar_strb_hole_detected := TRUE; lvar_last_strb_hole_position := lvar_loop_count-1; Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then lvar_first_strb_assert_found := true; else null; -- do nothing End if; lvar_loop_count := lvar_loop_count - 1; End loop; -- now assign the encoder output value to the bit position of the last Strobe encountered If (lvar_strb_hole_detected) Then sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH)); else sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH)); End if; end process CALC_DEST_STRB_ALIGN; ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ -- For Generate -- -- Label: FORMAT_OUTPUT_DATA_STRB -- -- For Generate Description: -- Connect the output Data and Strobe ports to the appropriate -- bits in the sig_output_data_reg. -- ------------------------------------------------------------ FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate begin sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto get_start_index(byte_lane_index, BYTE_WIDTH)) <= sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0); sig_dre_strb_out_i(byte_lane_index) <= sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2); end generate FORMAT_OUTPUT_DATA_STRB; ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ --------------------------------------------------------------------------------- -- Registers ------------------------------------------------------------ -- For Generate -- -- Label: GEN_INPUT_REG -- -- For Generate Description: -- -- Implements a programble number of input register slices. -- -- ------------------------------------------------------------ GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate begin ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_INPUTREG_SLICE -- -- Process Description: -- Implement a single register slice for the Input Register. -- ------------------------------------------------------------- DO_INPUTREG_SLICE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or sig_flush_db1_complete = '1' or -- clear on reset or if (dre_in_tvalid = '1' and sig_pipeline_halt = '0' and -- the pipe is being advanced and dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded sig_input_data_reg(slice_index) <= ZEROED_SLICE; elsif (dre_in_tstrb(slice_index) = '1' and sig_input_accept = '1') then sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) & dre_in_tstrb(slice_index) & dre_in_tdata((slice_index*8)+7 downto slice_index*8); else null; -- don't change state end if; end if; end process DO_INPUTREG_SLICE; end generate GEN_INPUT_REG; ------------------------------------------------------------ -- For Generate -- -- Label: GEN_DELAY_REG -- -- For Generate Description: -- -- Implements a programble number of output register slices -- -- ------------------------------------------------------------ GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate begin ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_DELAYREG_SLICE -- -- Process Description: -- Implement a single register slice -- ------------------------------------------------------------- DO_DELAYREG_SLICE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or -- clear on reset or if (sig_advance_pipe_data = '1' and -- the pipe is being advanced and sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded sig_delay_data_reg(slice_index) <= ZEROED_SLICE; elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and sig_advance_pipe_data = '1') then sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index); else null; -- don't change state end if; end if; end process DO_DELAYREG_SLICE; end generate GEN_DELAY_REG; ------------------------------------------------------------ -- For Generate -- -- Label: GEN_OUTPUT_REG -- -- For Generate Description: -- -- Implements a programble number of output register slices -- -- ------------------------------------------------------------ GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate begin ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_OUTREG_SLICE -- -- Process Description: -- Implement a single register slice -- ------------------------------------------------------------- DO_OUTREG_SLICE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1' or -- clear on reset or if (sig_output_xfer = '1' and -- the output is being transfered and sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded sig_output_data_reg(slice_index) <= ZEROED_SLICE; elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and sig_advance_pipe_data = '1') then sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index); else null; -- don't change state end if; end if; end process DO_OUTREG_SLICE; end generate GEN_OUTPUT_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: GEN_TVALID -- -- Process Description: -- This sync process generates the Write request for the -- destination interface. -- ------------------------------------------------------------- GEN_TVALID : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_dre_tvalid_i <= '0'; elsif (sig_advance_pipe_data = '1') then sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or sig_final_mux_has_tlast; -- the Last data beat of a packet Elsif (dre_out_tready = '1' and -- a completed write but no sig_dre_tvalid_i = '1') Then -- new input data so clear -- until more input data shows up sig_dre_tvalid_i <= '0'; else null; -- hold state end if; -- else -- null; end if; end process GEN_TVALID; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: GEN_TLAST_OUT -- -- Process Description: -- This sync process generates the TLAST output for the -- destination interface. -- ------------------------------------------------------------- GEN_TLAST_OUT : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_tlast_out <= '0'; elsif (sig_advance_pipe_data = '1') then sig_tlast_out <= sig_final_mux_has_tlast; Elsif (dre_out_tready = '1' and -- a completed transfer sig_dre_tvalid_i = '1') Then -- so clear tlast sig_tlast_out <= '0'; else null; -- hold state end if; -- else -- null; end if; end process GEN_TLAST_OUT; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MUXFARM_64 -- -- If Generate Description: -- Support Logic and Mux Farm for 64-bit data path case -- -- ------------------------------------------------------------ GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate Signal s_case_i_64 : Integer range 0 to 7 := 0; signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0'); Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0'); Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0'); Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0'); begin ------------------------------------------------------------- -- Combinational Process -- -- Label: FIND_MS_STRB_SET_8 -- -- Process Description: -- This process finds the most significant asserted strobe -- position. This position is used to enable the input flop -- for TLAST that is associated with that byte position. The -- TLAST can then flow through the DRE pipe with the last -- valid byte of data. -- ------------------------------------------------------------- FIND_MS_STRB_SET_8 : process (dre_in_tlast, dre_in_tstrb, sig_tlast_strobes) begin sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static if (dre_in_tlast = '0') then sig_tlast_enables <= "00000000"; elsif (sig_tlast_strobes(7) = '1') then sig_tlast_enables <= "10000000"; elsif (sig_tlast_strobes(6) = '1') then sig_tlast_enables <= "01000000"; elsif (sig_tlast_strobes(5) = '1') then sig_tlast_enables <= "00100000"; elsif (sig_tlast_strobes(4) = '1') then sig_tlast_enables <= "00010000"; elsif (sig_tlast_strobes(3) = '1') then sig_tlast_enables <= "00001000"; elsif (sig_tlast_strobes(2) = '1') then sig_tlast_enables <= "00000100"; elsif (sig_tlast_strobes(1) = '1') then sig_tlast_enables <= "00000010"; else sig_tlast_enables <= "00000001"; end if; end process FIND_MS_STRB_SET_8; --------------------------------------------------------------------------------- -- Shift Case logic -- The new auto-destination alignment is based on the last -- strobe alignment written into the output register. sig_next_auto_dest <= sig_current_dest_align; -- Select the destination alignment to use sig_dest_align_i <= sig_next_auto_dest When (dre_use_autodest = '1') Else dre_dest_align; -- Convert shift case to sld_logic_vector --sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3); sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3)); ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_SHIFT_CASE_64 -- -- Process Description: -- Implements the DRE Control State Calculator -- ------------------------------------------------------------- DO_SHIFT_CASE_64 : process (dre_src_align , sig_dest_align_i, sig_cntl_state_64) begin sig_cntl_state_64 <= dre_src_align & sig_dest_align_i; case sig_cntl_state_64 is when "000000" => s_case_i_64 <= 0; when "000001" => s_case_i_64 <= 7; when "000010" => s_case_i_64 <= 6; when "000011" => s_case_i_64 <= 5; when "000100" => s_case_i_64 <= 4; when "000101" => s_case_i_64 <= 3; when "000110" => s_case_i_64 <= 2; when "000111" => s_case_i_64 <= 1; when "001000" => s_case_i_64 <= 1; when "001001" => s_case_i_64 <= 0; when "001010" => s_case_i_64 <= 7; when "001011" => s_case_i_64 <= 6; when "001100" => s_case_i_64 <= 5; when "001101" => s_case_i_64 <= 4; when "001110" => s_case_i_64 <= 3; when "001111" => s_case_i_64 <= 2; when "010000" => s_case_i_64 <= 2; when "010001" => s_case_i_64 <= 1; when "010010" => s_case_i_64 <= 0; when "010011" => s_case_i_64 <= 7; when "010100" => s_case_i_64 <= 6; when "010101" => s_case_i_64 <= 5; when "010110" => s_case_i_64 <= 4; when "010111" => s_case_i_64 <= 3; when "011000" => s_case_i_64 <= 3; when "011001" => s_case_i_64 <= 2; when "011010" => s_case_i_64 <= 1; when "011011" => s_case_i_64 <= 0; when "011100" => s_case_i_64 <= 7; when "011101" => s_case_i_64 <= 6; when "011110" => s_case_i_64 <= 5; when "011111" => s_case_i_64 <= 4; when "100000" => s_case_i_64 <= 4; when "100001" => s_case_i_64 <= 3; when "100010" => s_case_i_64 <= 2; when "100011" => s_case_i_64 <= 1; when "100100" => s_case_i_64 <= 0; when "100101" => s_case_i_64 <= 7; when "100110" => s_case_i_64 <= 6; when "100111" => s_case_i_64 <= 5; when "101000" => s_case_i_64 <= 5; when "101001" => s_case_i_64 <= 4; when "101010" => s_case_i_64 <= 3; when "101011" => s_case_i_64 <= 2; when "101100" => s_case_i_64 <= 1; when "101101" => s_case_i_64 <= 0; when "101110" => s_case_i_64 <= 7; when "101111" => s_case_i_64 <= 6; when "110000" => s_case_i_64 <= 6; when "110001" => s_case_i_64 <= 5; when "110010" => s_case_i_64 <= 4; when "110011" => s_case_i_64 <= 3; when "110100" => s_case_i_64 <= 2; when "110101" => s_case_i_64 <= 1; when "110110" => s_case_i_64 <= 0; when "110111" => s_case_i_64 <= 7; when "111000" => s_case_i_64 <= 7; when "111001" => s_case_i_64 <= 6; when "111010" => s_case_i_64 <= 5; when "111011" => s_case_i_64 <= 4; when "111100" => s_case_i_64 <= 3; when "111101" => s_case_i_64 <= 2; when "111110" => s_case_i_64 <= 1; when "111111" => s_case_i_64 <= 0; when others => NULL; end case; end process DO_SHIFT_CASE_64; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SHIFT_CASE -- -- Process Description: -- This process registers the Shift Case output from the -- Shift Case Generator. This will be used to control the -- select inputs of the Shift Muxes for the duration of the -- data transfer session. If Pass Through is requested, then -- Shift Case 0 is forced regardless of source and destination -- alignment values. -- ------------------------------------------------------------- REG_SHIFT_CASE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_shift_case_reg <= (others => '0'); elsif (sig_cntl_accept = '1') then sig_shift_case_reg <= sig_shift_case_i; else null; -- hold state end if; -- else -- null; end if; end process REG_SHIFT_CASE; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start PASS Mux Farm Design------------------------------------------------- -- Pass Mux Byte 0 (wire) -- This is a wire so..... sig_pass_mux_bus(0) <= sig_input_data_reg(0); -- Pass Mux Byte 1 (2-1 x8 Mux) I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(0), I0 => sig_input_data_reg(1), I1 => sig_input_data_reg(0), Y => sig_pass_mux_bus(1) ); -- Pass Mux Byte 2 (4-1 x8 Mux) I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(2) , I1 => ZEROED_SLICE , I2 => sig_input_data_reg(0) , I3 => sig_input_data_reg(1) , Y => sig_pass_mux_bus(2) ); -- Pass Mux Byte 3 (4-1 x8 Mux) I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(3) , I1 => sig_input_data_reg(0) , I2 => sig_input_data_reg(1) , I3 => sig_input_data_reg(2) , Y => sig_pass_mux_bus(3) ); -- Pass Mux Byte 4 (8-1 x8 Mux) I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => sig_input_data_reg(4) , I1 => ZEROED_SLICE , I2 => ZEROED_SLICE , I3 => ZEROED_SLICE , I4 => sig_input_data_reg(0) , I5 => sig_input_data_reg(1) , I6 => sig_input_data_reg(2) , I7 => sig_input_data_reg(3) , Y => sig_pass_mux_bus(4) ); -- Pass Mux Byte 5 (8-1 x8 Mux) I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => sig_input_data_reg(5) , I1 => ZEROED_SLICE , I2 => ZEROED_SLICE , I3 => sig_input_data_reg(0) , I4 => sig_input_data_reg(1) , I5 => sig_input_data_reg(2) , I6 => sig_input_data_reg(3) , I7 => sig_input_data_reg(4) , Y => sig_pass_mux_bus(5) ); -- Pass Mux Byte 6 (8-1 x8 Mux) I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => sig_input_data_reg(6) , I1 => ZEROED_SLICE , I2 => sig_input_data_reg(0) , I3 => sig_input_data_reg(1) , I4 => sig_input_data_reg(2) , I5 => sig_input_data_reg(3) , I6 => sig_input_data_reg(4) , I7 => sig_input_data_reg(5) , Y => sig_pass_mux_bus(6) ); -- Pass Mux Byte 7 (8-1 x8 Mux) I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => sig_input_data_reg(7) , I1 => sig_input_data_reg(0) , I2 => sig_input_data_reg(1) , I3 => sig_input_data_reg(2) , I4 => sig_input_data_reg(3) , I5 => sig_input_data_reg(4) , I6 => sig_input_data_reg(5) , I7 => sig_input_data_reg(6) , Y => sig_pass_mux_bus(7) ); -- End PASS Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Delay Mux Farm Design------------------------------------------------- -- Delay Mux Byte 0 (8-1 x8 Mux) I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0) , I0 => ZEROED_SLICE , I1 => sig_input_data_reg(1) , I2 => sig_input_data_reg(2) , I3 => sig_input_data_reg(3) , I4 => sig_input_data_reg(4) , I5 => sig_input_data_reg(5) , I6 => sig_input_data_reg(6) , I7 => sig_input_data_reg(7) , Y => sig_delay_mux_bus(0) ); -- Delay Mux Byte 1 (8-1 x8 Mux) I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => ZEROED_SLICE , I1 => sig_input_data_reg(2) , I2 => sig_input_data_reg(3) , I3 => sig_input_data_reg(4) , I4 => sig_input_data_reg(5) , I5 => sig_input_data_reg(6) , I6 => sig_input_data_reg(7) , I7 => ZEROED_SLICE , Y => sig_delay_mux_bus(1) ); -- Delay Mux Byte 2 (8-1 x8 Mux) I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(2 downto 0), I0 => ZEROED_SLICE , I1 => sig_input_data_reg(3) , I2 => sig_input_data_reg(4) , I3 => sig_input_data_reg(5) , I4 => sig_input_data_reg(6) , I5 => sig_input_data_reg(7) , I6 => ZEROED_SLICE , I7 => ZEROED_SLICE , Y => sig_delay_mux_bus(2) ); -- Delay Mux Byte 3 (4-1 x8 Mux) I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(7) , I1 => sig_input_data_reg(4) , I2 => sig_input_data_reg(5) , I3 => sig_input_data_reg(6) , Y => sig_delay_mux_bus(3) ); -- Delay Mux Byte 4 (4-1 x8 Mux) I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => ZEROED_SLICE , I1 => sig_input_data_reg(5) , I2 => sig_input_data_reg(6) , I3 => sig_input_data_reg(7) , Y => sig_delay_mux_bus(4) ); -- Delay Mux Byte 5 (2-1 x8 Mux) I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH -- : Integer := 8 ) port map( Sel => sig_shift_case_reg(0), I0 => sig_input_data_reg(7), I1 => sig_input_data_reg(6), Y => sig_delay_mux_bus(5) ); -- Delay Mux Byte 6 (Wire) sig_delay_mux_bus(6) <= sig_input_data_reg(7); -- Delay Mux Byte 7 (Zeroed) sig_delay_mux_bus(7) <= ZEROED_SLICE; -- End Delay Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Final Mux Farm Design------------------------------------------------- -- Final Mux Byte 0 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B0_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 0 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(0) <= '0'; when "001" => sig_final_mux_sel(0) <= '1'; when "010" => sig_final_mux_sel(0) <= '1'; when "011" => sig_final_mux_sel(0) <= '1'; when "100" => sig_final_mux_sel(0) <= '1'; when "101" => sig_final_mux_sel(0) <= '1'; when "110" => sig_final_mux_sel(0) <= '1'; when "111" => sig_final_mux_sel(0) <= '1'; when others => sig_final_mux_sel(0) <= '0'; end case; end process MUX2_1_FINAL_B0_CNTL; I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(0) , I0 => sig_input_data_reg(0), I1 => sig_delay_data_reg(0), Y => sig_final_mux_bus(0) ); -- Final Mux Byte 1 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B1_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 1 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(1) <= '0'; when "001" => sig_final_mux_sel(1) <= '1'; when "010" => sig_final_mux_sel(1) <= '1'; when "011" => sig_final_mux_sel(1) <= '1'; when "100" => sig_final_mux_sel(1) <= '1'; when "101" => sig_final_mux_sel(1) <= '1'; when "110" => sig_final_mux_sel(1) <= '1'; when "111" => sig_final_mux_sel(1) <= '0'; when others => sig_final_mux_sel(1) <= '0'; end case; end process MUX2_1_FINAL_B1_CNTL; I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(1) , I0 => sig_pass_mux_bus(1) , I1 => sig_delay_data_reg(1), Y => sig_final_mux_bus(1) ); -- Final Mux Byte 2 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B2_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 2 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(2) <= '0'; when "001" => sig_final_mux_sel(2) <= '1'; when "010" => sig_final_mux_sel(2) <= '1'; when "011" => sig_final_mux_sel(2) <= '1'; when "100" => sig_final_mux_sel(2) <= '1'; when "101" => sig_final_mux_sel(2) <= '1'; when "110" => sig_final_mux_sel(2) <= '0'; when "111" => sig_final_mux_sel(2) <= '0'; when others => sig_final_mux_sel(2) <= '0'; end case; end process MUX2_1_FINAL_B2_CNTL; I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(2) , I0 => sig_pass_mux_bus(2) , I1 => sig_delay_data_reg(2), Y => sig_final_mux_bus(2) ); -- Final Mux Byte 3 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B3_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 3 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(3) <= '0'; when "001" => sig_final_mux_sel(3) <= '1'; when "010" => sig_final_mux_sel(3) <= '1'; when "011" => sig_final_mux_sel(3) <= '1'; when "100" => sig_final_mux_sel(3) <= '1'; when "101" => sig_final_mux_sel(3) <= '0'; when "110" => sig_final_mux_sel(3) <= '0'; when "111" => sig_final_mux_sel(3) <= '0'; when others => sig_final_mux_sel(3) <= '0'; end case; end process MUX2_1_FINAL_B3_CNTL; I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(3) , I0 => sig_pass_mux_bus(3) , I1 => sig_delay_data_reg(3), Y => sig_final_mux_bus(3) ); -- Final Mux Byte 4 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B4_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 4 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(4) <= '0'; when "001" => sig_final_mux_sel(4) <= '1'; when "010" => sig_final_mux_sel(4) <= '1'; when "011" => sig_final_mux_sel(4) <= '1'; when "100" => sig_final_mux_sel(4) <= '0'; when "101" => sig_final_mux_sel(4) <= '0'; when "110" => sig_final_mux_sel(4) <= '0'; when "111" => sig_final_mux_sel(4) <= '0'; when others => sig_final_mux_sel(4) <= '0'; end case; end process MUX2_1_FINAL_B4_CNTL; I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(4) , I0 => sig_pass_mux_bus(4) , I1 => sig_delay_data_reg(4), Y => sig_final_mux_bus(4) ); -- Final Mux Byte 5 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B5_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 5 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(5) <= '0'; when "001" => sig_final_mux_sel(5) <= '1'; when "010" => sig_final_mux_sel(5) <= '1'; when "011" => sig_final_mux_sel(5) <= '0'; when "100" => sig_final_mux_sel(5) <= '0'; when "101" => sig_final_mux_sel(5) <= '0'; when "110" => sig_final_mux_sel(5) <= '0'; when "111" => sig_final_mux_sel(5) <= '0'; when others => sig_final_mux_sel(5) <= '0'; end case; end process MUX2_1_FINAL_B5_CNTL; I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(5) , I0 => sig_pass_mux_bus(5) , I1 => sig_delay_data_reg(5), Y => sig_final_mux_bus(5) ); -- Final Mux Byte 6 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B6_CNTL -- -- Process Description: -- This process generates the Select Control for Byte 6 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "000" => sig_final_mux_sel(6) <= '0'; when "001" => sig_final_mux_sel(6) <= '1'; when "010" => sig_final_mux_sel(6) <= '0'; when "011" => sig_final_mux_sel(6) <= '0'; when "100" => sig_final_mux_sel(6) <= '0'; when "101" => sig_final_mux_sel(6) <= '0'; when "110" => sig_final_mux_sel(6) <= '0'; when "111" => sig_final_mux_sel(6) <= '0'; when others => sig_final_mux_sel(6) <= '0'; end case; end process MUX2_1_FINAL_B6_CNTL; I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(6) , I0 => sig_pass_mux_bus(6) , I1 => sig_delay_data_reg(6), Y => sig_final_mux_bus(6) ); -- Final Mux Byte 7 (wire) sig_final_mux_sel(7) <= '0'; sig_final_mux_bus(7) <= sig_pass_mux_bus(7); -- End Final Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- end generate GEN_MUXFARM_64; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MUXFARM_32 -- -- If Generate Description: -- Support Logic and Mux Farm for 32-bit data path case -- -- ------------------------------------------------------------ GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate Signal s_case_i_32 : Integer range 0 to 3 := 0; signal sig_cntl_state_32 : std_logic_vector(3 downto 0) := (others => '0'); Signal sig_shift_case_i : std_logic_vector(1 downto 0) := (others => '0'); Signal sig_shift_case_reg : std_logic_vector(1 downto 0) := (others => '0'); Signal sig_final_mux_sel : std_logic_vector(3 downto 0) := (others => '0'); begin ------------------------------------------------------------- -- Combinational Process -- -- Label: FIND_MS_STRB_SET_4 -- -- Process Description: -- This process finds the most significant asserted strobe -- position. This position is used to enable the input flop -- for TLAST that is associated with that byte position. The -- TLAST can then flow through the DRE pipe with the last -- valid byte of data. -- ------------------------------------------------------------- FIND_MS_STRB_SET_4 : process (dre_in_tlast, dre_in_tstrb, sig_tlast_strobes) begin sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static if (dre_in_tlast = '0') then sig_tlast_enables <= "0000"; elsif (sig_tlast_strobes(3) = '1') then sig_tlast_enables <= "1000"; elsif (sig_tlast_strobes(2) = '1') then sig_tlast_enables <= "0100"; elsif (sig_tlast_strobes(1) = '1') then sig_tlast_enables <= "0010"; else sig_tlast_enables <= "0001"; end if; end process FIND_MS_STRB_SET_4; --------------------------------------------------------------------------------- -- Shift Case logic -- The new auto-destination alignment is based on the last -- strobe alignment written into the output register. sig_next_auto_dest <= sig_current_dest_align; -- Select the destination alignment to use sig_dest_align_i <= sig_next_auto_dest When (dre_use_autodest = '1') Else dre_dest_align; -- Convert shift case to sld_logic_vector --sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2); sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2)); ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_SHIFT_CASE_32 -- -- Process Description: -- Implements the DRE Control State Calculator -- ------------------------------------------------------------- DO_SHIFT_CASE_32 : process (dre_src_align , sig_dest_align_i, sig_cntl_state_32) begin sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0); case sig_cntl_state_32 is when "0000" => s_case_i_32 <= 0; when "0001" => s_case_i_32 <= 3; when "0010" => s_case_i_32 <= 2; when "0011" => s_case_i_32 <= 1; when "0100" => s_case_i_32 <= 1; when "0101" => s_case_i_32 <= 0; when "0110" => s_case_i_32 <= 3; when "0111" => s_case_i_32 <= 2; when "1000" => s_case_i_32 <= 2; when "1001" => s_case_i_32 <= 1; when "1010" => s_case_i_32 <= 0; when "1011" => s_case_i_32 <= 3; when "1100" => s_case_i_32 <= 3; when "1101" => s_case_i_32 <= 2; when "1110" => s_case_i_32 <= 1; when "1111" => s_case_i_32 <= 0; when others => NULL; end case; end process DO_SHIFT_CASE_32; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SHIFT_CASE -- -- Process Description: -- This process registers the Shift Case output from the -- Shift Case Generator. This will be used to control the -- select inputs of the Shift Muxes for the duration of the -- data transfer session. If Pass Through is requested, then -- Shift Case 0 is forced regardless of source and destination -- alignment values. -- ------------------------------------------------------------- REG_SHIFT_CASE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_shift_case_reg <= (others => '0'); elsif (sig_cntl_accept = '1') then sig_shift_case_reg <= sig_shift_case_i; else null; -- hold state end if; -- else -- null; end if; end process REG_SHIFT_CASE; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start PASS Mux Farm Design------------------------------------------------- -- Pass Mux Byte 0 (wire) -- This is a wire so..... sig_pass_mux_bus(0) <= sig_input_data_reg(0); -- Pass Mux Byte 1 (2-1 x8 Mux) I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(0), I0 => sig_input_data_reg(1), I1 => sig_input_data_reg(0), Y => sig_pass_mux_bus(1) ); -- Pass Mux Byte 2 (4-1 x8 Mux) I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(2) , I1 => ZEROED_SLICE , I2 => sig_input_data_reg(0) , I3 => sig_input_data_reg(1) , Y => sig_pass_mux_bus(2) ); -- Pass Mux Byte 3 (4-1 x8 Mux) I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => sig_input_data_reg(3) , I1 => sig_input_data_reg(0) , I2 => sig_input_data_reg(1) , I3 => sig_input_data_reg(2) , Y => sig_pass_mux_bus(3) ); -- End PASS Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Delay Mux Farm Design------------------------------------------------- -- Delay Mux Byte 0 (4-1 x8 Mux) I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(1 downto 0), I0 => ZEROED_SLICE , I1 => sig_input_data_reg(1) , I2 => sig_input_data_reg(2) , I3 => sig_input_data_reg(3) , Y => sig_delay_mux_bus(0) ); -- Delay Mux Byte 1 (2-1 x8 Mux) I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg(0), I0 => sig_input_data_reg(3), I1 => sig_input_data_reg(2), Y => sig_delay_mux_bus(1) ); -- Delay Mux Byte 2 (Wire) sig_delay_mux_bus(2) <= sig_input_data_reg(3); -- Delay Mux Byte 3 (Zeroed) sig_delay_mux_bus(3) <= ZEROED_SLICE; -- End Delay Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Final Mux Farm Design------------------------------------------------- -- Final Mux Slice 0 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B0_CNTL -- -- Process Description: -- This process generates the Select Control for Slice 0 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "00" => sig_final_mux_sel(0) <= '0'; when "01" => sig_final_mux_sel(0) <= '1'; when "10" => sig_final_mux_sel(0) <= '1'; when "11" => sig_final_mux_sel(0) <= '1'; when others => sig_final_mux_sel(0) <= '0'; end case; end process MUX2_1_FINAL_B0_CNTL; I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(0) , I0 => sig_pass_mux_bus(0) , I1 => sig_delay_data_reg(0), Y => sig_final_mux_bus(0) ); -- Final Mux Slice 1 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B1_CNTL -- -- Process Description: -- This process generates the Select Control for slice 1 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "00" => sig_final_mux_sel(1) <= '0'; when "01" => sig_final_mux_sel(1) <= '1'; when "10" => sig_final_mux_sel(1) <= '1'; when "11" => sig_final_mux_sel(1) <= '0'; when others => sig_final_mux_sel(1) <= '0'; end case; end process MUX2_1_FINAL_B1_CNTL; I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(1) , I0 => sig_pass_mux_bus(1) , I1 => sig_delay_data_reg(1), Y => sig_final_mux_bus(1) ); -- Final Mux Slice 2 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B2_CNTL -- -- Process Description: -- This process generates the Select Control for Slice 2 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when "00" => sig_final_mux_sel(2) <= '0'; when "01" => sig_final_mux_sel(2) <= '1'; when "10" => sig_final_mux_sel(2) <= '0'; when "11" => sig_final_mux_sel(2) <= '0'; when others => sig_final_mux_sel(2) <= '0'; end case; end process MUX2_1_FINAL_B2_CNTL; I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(2) , I0 => sig_pass_mux_bus(2) , I1 => sig_delay_data_reg(2), Y => sig_final_mux_bus(2) ); -- Final Mux Slice 3 (wire) sig_final_mux_sel(3) <= '0'; sig_final_mux_bus(3) <= sig_pass_mux_bus(3); -- End Final Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- end generate GEN_MUXFARM_32; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MUXFARM_16 -- -- If Generate Description: -- Support Logic and Mux Farm for 16-bit data path case -- -- ------------------------------------------------------------ GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate Signal s_case_i_16 : Integer range 0 to 1 := 0; signal sig_cntl_state_16 : std_logic_vector(1 downto 0) := (others => '0'); Signal sig_shift_case_i : std_logic := '0'; Signal sig_shift_case_reg : std_logic := '0'; Signal sig_final_mux_sel : std_logic_vector(1 downto 0) := (others => '0'); begin ------------------------------------------------------------- -- Combinational Process -- -- Label: FIND_MS_STRB_SET_2 -- -- Process Description: -- This process finds the most significant asserted strobe -- position. This position is used to enable the input flop -- for TLAST that is associated with that byte position. The -- TLAST can then flow through the DRE pipe with the last -- valid byte of data. -- ------------------------------------------------------------- FIND_MS_STRB_SET_2 : process (dre_in_tlast, dre_in_tstrb, sig_tlast_strobes) begin sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static if (dre_in_tlast = '0') then sig_tlast_enables <= "00"; elsif (sig_tlast_strobes(1) = '1') then sig_tlast_enables <= "10"; else sig_tlast_enables <= "01"; end if; end process FIND_MS_STRB_SET_2; --------------------------------------------------------------------------------- -- Shift Case logic -- The new auto-destination alignment is based on the last -- strobe alignment written into the output register. sig_next_auto_dest <= sig_current_dest_align; -- Select the destination alignment to use sig_dest_align_i <= sig_next_auto_dest When (dre_use_autodest = '1') Else dre_dest_align; -- Convert shift case to std_logic sig_shift_case_i <= '1' When s_case_i_16 = 1 Else '0'; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_SHIFT_CASE_16 -- -- Process Description: -- Implements the DRE Control State Calculator -- ------------------------------------------------------------- DO_SHIFT_CASE_16 : process (dre_src_align , sig_dest_align_i, sig_cntl_state_16) begin sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0); case sig_cntl_state_16 is when "00" => s_case_i_16 <= 0; when "01" => s_case_i_16 <= 1; when "10" => s_case_i_16 <= 1; when "11" => s_case_i_16 <= 0; when others => NULL; end case; end process DO_SHIFT_CASE_16; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SHIFT_CASE -- -- Process Description: -- This process registers the Shift Case output from the -- Shift Case Generator. This will be used to control the -- select inputs of the Shift Muxes for the duration of the -- data transfer session. If Pass Through is requested, then -- Shift Case 0 is forced regardless of source and destination -- alignment values. -- ------------------------------------------------------------- REG_SHIFT_CASE : process (dre_clk) begin if (dre_clk'event and dre_clk = '1') then if (dre_rst = '1') then sig_shift_case_reg <= '0'; elsif (sig_cntl_accept = '1') then sig_shift_case_reg <= sig_shift_case_i; else null; -- hold state end if; -- else -- null; end if; end process REG_SHIFT_CASE; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start PASS Mux Farm Design------------------------------------------------- -- Pass Mux Byte 0 (wire) -- This is a wire so..... sig_pass_mux_bus(0) <= sig_input_data_reg(0); -- Pass Mux Byte 1 (2-1 x8 Mux) I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_shift_case_reg, I0 => sig_input_data_reg(1), I1 => sig_input_data_reg(0), Y => sig_pass_mux_bus(1) ); -- End PASS Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Delay Mux Farm Design------------------------------------------------- -- Delay Mux Slice 0 (Wire) sig_delay_mux_bus(0) <= sig_input_data_reg(1); -- Delay Mux Slice 1 (Zeroed) sig_delay_mux_bus(1) <= ZEROED_SLICE; -- End Delay Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Start Final Mux Farm Design------------------------------------------------- -- Final Mux Slice 0 (2-1 x8 Mux) ------------------------------------------------------------- -- Combinational Process -- -- Label: MUX2_1_FINAL_B0_CNTL -- -- Process Description: -- This process generates the Select Control for Slice 0 of -- the Final 2-1 Mux of the DRE. -- ------------------------------------------------------------- MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg) begin case sig_shift_case_reg is when '0' => sig_final_mux_sel(0) <= '0'; when others => sig_final_mux_sel(0) <= '1'; end case; end process MUX2_1_FINAL_B0_CNTL; I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n generic map( C_WIDTH => SLICE_WIDTH ) port map( Sel => sig_final_mux_sel(0) , I0 => sig_pass_mux_bus(0) , I1 => sig_delay_data_reg(0), Y => sig_final_mux_bus(0) ); -- Final Mux Slice 1 (wire) sig_final_mux_sel(1) <= '0'; sig_final_mux_bus(1) <= sig_pass_mux_bus(1); -- End Final Mux Farm Design--------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- end generate GEN_MUXFARM_16; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/Microsystem/axi_interface_part2/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/axi_bram_ctrl_top.vhd

6

43430

------------------------------------------------------------------------------- -- axi_bram_ctrl_top.vhd ------------------------------------------------------------------------------- -- -- -- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ------------------------------------------------------------------------------- -- Filename: axi_bram_ctrl_top.vhd -- -- Description: This file is the top level module for the AXI BRAM -- controller IP core. -- -- VHDL-Standard: VHDL'93 -- ------------------------------------------------------------------------------- -- Structure: -- axi_bram_ctrl_top.vhd (v4_0) -- | -- |-- full_axi.vhd -- | -- sng_port_arb.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- wr_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- | -- rd_chnl.vhd -- | -- wrap_brst.vhd -- | -- ua_narrow.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- checkbit_handler_64.vhd -- | -- (same helper components as checkbit_handler) -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- correct_one_bit_64.vhd -- | -- ecc_gen.vhd -- | -- |-- axi_lite.vhd -- | -- lite_ecc_reg.vhd -- | -- axi_lite_if.vhd -- | -- checkbit_handler.vhd -- | -- xor18.vhd -- | -- parity.vhd -- | -- correct_one_bit.vhd -- | -- ecc_gen.vhd -- -- -- ------------------------------------------------------------------------------- -- -- History: -- -- ^^^^^^ -- JLJ 2/1/2011 v1.03a -- ~~~~~~ -- Migrate to v1.03a. -- Plus minor code cleanup. -- ^^^^^^ -- JLJ 2/2/2011 v1.03a -- ~~~~~~ -- Remove library version # dependency. Replace with work library. -- ^^^^^^ -- JLJ 2/9/2011 v1.03a -- ~~~~~~ -- Update Create_Size_Default function to support 512 & 1024-bit BRAM. -- Replace usage of Create_Size_Default function. -- ^^^^^^ -- JLJ 2/15/2011 v1.03a -- ~~~~~~ -- Initial integration of Hsiao ECC algorithm. -- Add C_ECC_TYPE top level parameter on full_axi module. -- Update ECC signal sizes for 128-bit support. -- ^^^^^^ -- JLJ 2/16/2011 v1.03a -- ~~~~~~ -- Update WE size based on 128-bit ECC configuration. -- ^^^^^^ -- JLJ 2/22/2011 v1.03a -- ~~~~~~ -- Add C_ECC_TYPE top level parameter on axi_lite module. -- ^^^^^^ -- JLJ 2/23/2011 v1.03a -- ~~~~~~ -- Set C_ECC_TYPE = 1 for Hsiao DV regressions. -- ^^^^^^ -- JLJ 2/24/2011 v1.03a -- ~~~~~~ -- Move Find_ECC_Size function to package. -- ^^^^^^ -- JLJ 3/17/2011 v1.03a -- ~~~~~~ -- Add comments as noted in Spyglass runs. -- ^^^^^^ -- JLJ 5/6/2011 v1.03a -- ~~~~~~ -- Remove C_FAMILY from top level. -- Remove C_FAMILY in axi_lite sub module. -- ^^^^^^ -- JLJ 6/23/2011 v1.03a -- ~~~~~~ -- Migrate 9-bit ECC to 16-bit ECC for 128-bit BRAM data width. -- ^^^^^^ -- -- -- ------------------------------------------------------------------------------- -- Library declarations library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; library work; use work.axi_lite; use work.full_axi; use work.axi_bram_ctrl_funcs.all; ------------------------------------------------------------------------------ entity axi_bram_ctrl_top is generic ( -- AXI Parameters C_BRAM_ADDR_WIDTH : integer := 12; -- Width of AXI address bus (in bits) C_S_AXI_ADDR_WIDTH : integer := 32; -- Width of AXI address bus (in bits) C_S_AXI_DATA_WIDTH : integer := 32; -- Width of AXI data bus (in bits) C_S_AXI_ID_WIDTH : INTEGER := 4; -- AXI ID vector width C_S_AXI_PROTOCOL : string := "AXI4"; -- Set to AXI4LITE to optimize out burst transaction support C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1; -- Support for narrow burst operations C_SINGLE_PORT_BRAM : INTEGER := 0; -- Enable single port usage of BRAM -- C_FAMILY : string := "virtex6"; -- Specify the target architecture type -- AXI-Lite Register Parameters C_S_AXI_CTRL_ADDR_WIDTH : integer := 32; -- Width of AXI-Lite address bus (in bits) C_S_AXI_CTRL_DATA_WIDTH : integer := 32; -- Width of AXI-Lite data bus (in bits) -- ECC Parameters C_ECC : integer := 0; -- Enables or disables ECC functionality C_ECC_TYPE : integer := 1; C_FAULT_INJECT : integer := 0; -- Enable fault injection registers -- (default = disabled) C_ECC_ONOFF_RESET_VALUE : integer := 1 -- By default, ECC checking is on -- (can disable ECC @ reset by setting this to 0) -- Reserved parameters for future implementations. -- C_ENABLE_AXI_CTRL_REG_IF : integer := 1; -- By default the ECC AXI-Lite register interface is enabled -- C_CE_FAILING_REGISTERS : integer := 1; -- Enable CE (correctable error) failing registers -- C_UE_FAILING_REGISTERS : integer := 1; -- Enable UE (uncorrectable error) failing registers -- C_ECC_STATUS_REGISTERS : integer := 1; -- Enable ECC status registers -- C_ECC_ONOFF_REGISTER : integer := 1; -- Enable ECC on/off control register -- C_CE_COUNTER_WIDTH : integer := 0 -- Selects CE counter width/threshold to assert ECC_Interrupt ); port ( -- AXI Interface Signals -- AXI Clock and Reset S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; ECC_Interrupt : out std_logic := '0'; ECC_UE : out std_logic := '0'; -- AXI Write Address Channel Signals (AW) S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWLEN : in std_logic_vector(7 downto 0); S_AXI_AWSIZE : in std_logic_vector(2 downto 0); S_AXI_AWBURST : in std_logic_vector(1 downto 0); S_AXI_AWLOCK : in std_logic; S_AXI_AWCACHE : in std_logic_vector(3 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; -- AXI Write Data Channel Signals (W) S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0); S_AXI_WLAST : in std_logic; S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; -- AXI Write Data Response Channel Signals (B) S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; -- AXI Read Address Channel Signals (AR) S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARLEN : in std_logic_vector(7 downto 0); S_AXI_ARSIZE : in std_logic_vector(2 downto 0); S_AXI_ARBURST : in std_logic_vector(1 downto 0); S_AXI_ARLOCK : in std_logic; S_AXI_ARCACHE : in std_logic_vector(3 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; -- AXI Read Data Channel Signals (R) S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RLAST : out std_logic; S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- AXI-Lite ECC Register Interface Signals -- AXI-Lite Clock and Reset -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_ACLK : in std_logic; -- S_AXI_CTRL_ARESETN : in std_logic; -- AXI-Lite Write Address Channel Signals (AW) S_AXI_CTRL_AWVALID : in std_logic; S_AXI_CTRL_AWREADY : out std_logic; S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); -- AXI-Lite Write Data Channel Signals (W) S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_WVALID : in std_logic; S_AXI_CTRL_WREADY : out std_logic; -- AXI-Lite Write Data Response Channel Signals (B) S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_BVALID : out std_logic; S_AXI_CTRL_BREADY : in std_logic; -- AXI-Lite Read Address Channel Signals (AR) S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0); S_AXI_CTRL_ARVALID : in std_logic; S_AXI_CTRL_ARREADY : out std_logic; -- AXI-Lite Read Data Channel Signals (R) S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0); S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0); S_AXI_CTRL_RVALID : out std_logic; S_AXI_CTRL_RREADY : in std_logic; -- BRAM Interface Signals (Port A) BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_En_A : out std_logic; BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); -- BRAM Interface Signals (Port B) BRAM_Rst_B : out std_logic; BRAM_Clk_B : out std_logic; BRAM_En_B : out std_logic; BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0); BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) ); end entity axi_bram_ctrl_top; ------------------------------------------------------------------------------- architecture implementation of axi_bram_ctrl_top is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- All functions defined in axi_bram_ctrl_funcs package. ------------------------------------------------------------------------------- -- Constants ------------------------------------------------------------------------------- -- Model behavior of AXI Interconnect in simulation for wrapping of ID values. constant C_SIM_ONLY : std_logic := '1'; -- Reset active level (common through core) constant C_RESET_ACTIVE : std_logic := '0'; -- Create top level constant to assign fixed value to ARSIZE and AWSIZE -- when narrow bursting is parameterized out of the IP core instantiation. -- constant AXI_FIXED_SIZE_WO_NARROW : std_logic_vector (2 downto 0) := Create_Size_Default; -- v1.03a constant AXI_FIXED_SIZE_WO_NARROW : integer := log2 (C_S_AXI_DATA_WIDTH/8); -- Only instantiate logic based on C_S_AXI_PROTOCOL. constant IF_IS_AXI4 : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4")); constant IF_IS_AXI4LITE : boolean := (Equal_String (C_S_AXI_PROTOCOL, "AXI4LITE")); -- Determine external ECC width. -- Use function defined in axi_bram_ctrl_funcs package. constant C_ECC_WIDTH : integer := Find_ECC_Size (C_ECC, C_S_AXI_DATA_WIDTH); constant C_ECC_FULL_BIT_WIDTH : integer := Find_ECC_Full_Bit_Size (C_ECC, C_S_AXI_DATA_WIDTH); -- Set internal parameters for ECC register enabling when C_ECC = 1 constant C_ENABLE_AXI_CTRL_REG_IF_I : integer := C_ECC; constant C_CE_FAILING_REGISTERS_I : integer := C_ECC; constant C_UE_FAILING_REGISTERS_I : integer := 0; -- Remove all UE registers -- Catastrophic error indicated with ECC_UE & Interrupt flags. constant C_ECC_STATUS_REGISTERS_I : integer := C_ECC; constant C_ECC_ONOFF_REGISTER_I : integer := C_ECC; constant C_CE_COUNTER_WIDTH : integer := 8 * C_ECC; -- Counter only sized when C_ECC = 1. -- Selects CE counter width/threshold to assert ECC_Interrupt -- Hard coded at 8-bits to capture and count up to 256 correctable errors. --constant C_ECC_TYPE : integer := 1; -- v1.03a -- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- -- Internal BRAM Signals -- Port A signal bram_en_a_int : std_logic := '0'; signal bram_we_a_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0'); signal bram_addr_a_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_wrdata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); signal bram_rddata_a_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Port B signal bram_addr_b_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_en_b_int : std_logic := '0'; signal bram_we_b_int : std_logic_vector (((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto 0) := (others => '0'); signal bram_wrdata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); signal bram_rddata_b_int : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0'); signal axi_awsize_int : std_logic_vector(2 downto 0) := (others => '0'); signal axi_arsize_int : std_logic_vector(2 downto 0) := (others => '0'); signal S_AXI_ARREADY_int : std_logic := '0'; signal S_AXI_AWREADY_int : std_logic := '0'; signal S_AXI_RID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0'); signal S_AXI_BID_int : std_logic_vector (C_S_AXI_ID_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Architecture Body ------------------------------------------------------------------------------- begin -- *** BRAM Port A Output Signals *** BRAM_Rst_A <= not (S_AXI_ARESETN); BRAM_Clk_A <= S_AXI_ACLK; BRAM_En_A <= bram_en_a_int; BRAM_WE_A ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_a_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0); BRAM_Addr_A <= bram_addr_a_int; bram_rddata_a_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)); BRAM_WrData_A ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH-1 downto 0); -- Added for 13.3 -- Drive unused upper ECC bits to '0' -- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case. GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate begin BRAM_WrData_A ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0'); BRAM_WrData_A ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0); end generate GEN_128_ECC_WR; GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate begin BRAM_WrData_A ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_a_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_A ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_a_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_A ((C_ECC_WIDTH-1) downto 0); end generate GEN_ECC_WR; -- *** BRAM Port B Output Signals *** GEN_PORT_B: if (C_SINGLE_PORT_BRAM = 0) generate begin BRAM_Rst_B <= not (S_AXI_ARESETN); BRAM_WE_B ((((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH)/8) - 1) downto (C_ECC_FULL_BIT_WIDTH/8)) <= bram_we_b_int((C_S_AXI_DATA_WIDTH/8)-1 downto 0); BRAM_Addr_B <= bram_addr_b_int; BRAM_En_B <= bram_en_b_int; bram_rddata_b_int (C_S_AXI_DATA_WIDTH-1 downto 0) <= BRAM_RdData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)); BRAM_WrData_B ((C_S_AXI_DATA_WIDTH + C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_FULL_BIT_WIDTH)) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH-1 downto 0); -- 13.3 -- BRAM_WrData_B <= bram_wrdata_b_int; -- Added for 13.3 -- Drive unused upper ECC bits to '0' -- For bram_block compatibility, must drive unused upper bits to '0' for ECC 128-bit use case. GEN_128_ECC_WR: if (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1) generate begin BRAM_WrData_B ((C_ECC_FULL_BIT_WIDTH - 1) downto (C_ECC_WIDTH)) <= (others => '0'); BRAM_WrData_B ((C_ECC_WIDTH-1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0); end generate GEN_128_ECC_WR; GEN_ECC_WR: if ( not (C_S_AXI_DATA_WIDTH = 128) and (C_ECC = 1)) generate begin BRAM_WrData_B ((C_ECC_WIDTH - 1) downto 0) <= bram_wrdata_b_int(C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH); BRAM_WE_B ((C_ECC_FULL_BIT_WIDTH/8) - 1 downto 0) <= bram_we_b_int(((C_S_AXI_DATA_WIDTH+C_ECC_FULL_BIT_WIDTH)/8)-1 downto (C_S_AXI_DATA_WIDTH/8)); bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto C_S_AXI_DATA_WIDTH) <= BRAM_RdData_B ((C_ECC_WIDTH-1) downto 0); end generate GEN_ECC_WR; end generate GEN_PORT_B; GEN_NO_PORT_B: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_Rst_B <= '0'; BRAM_WE_B <= (others => '0'); BRAM_WrData_B <= (others => '0'); BRAM_Addr_B <= (others => '0'); BRAM_En_B <= '0'; end generate GEN_NO_PORT_B; --------------------------------------------------------------------------- -- -- Generate: GEN_BRAM_CLK_B -- Purpose: Only drive BRAM_Clk_B when dual port BRAM is enabled. -- --------------------------------------------------------------------------- GEN_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 0) generate begin BRAM_Clk_B <= S_AXI_ACLK; end generate GEN_BRAM_CLK_B; --------------------------------------------------------------------------- -- -- Generate: GEN_NO_BRAM_CLK_B -- Purpose: Drive default value for BRAM_Clk_B when single port -- BRAM is enabled and no clock is necessary on the inactive -- BRAM port. -- --------------------------------------------------------------------------- GEN_NO_BRAM_CLK_B: if (C_SINGLE_PORT_BRAM = 1) generate begin BRAM_Clk_B <= '0'; end generate GEN_NO_BRAM_CLK_B; --------------------------------------------------------------------------- -- Generate top level ARSIZE and AWSIZE signals for rd_chnl and wr_chnl -- respectively, based on design parameter setting of generic, -- C_S_AXI_SUPPORTS_NARROW_BURST. --------------------------------------------------------------------------- -- -- Generate: GEN_W_NARROW -- Purpose: Create internal AWSIZE and ARSIZE signal for write and -- read channel modules based on top level AXI signal inputs. -- --------------------------------------------------------------------------- GEN_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 1) and (IF_IS_AXI4) generate begin axi_awsize_int <= S_AXI_AWSIZE; axi_arsize_int <= S_AXI_ARSIZE; end generate GEN_W_NARROW; --------------------------------------------------------------------------- -- -- Generate: GEN_WO_NARROW -- Purpose: Create internal AWSIZE and ARSIZE signal for write and -- read channel modules based on hard coded -- value that indicates all AXI transfers will be equal in -- size to the AXI data bus. -- --------------------------------------------------------------------------- GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW_BURST = 0) or (IF_IS_AXI4LITE) generate begin -- axi_awsize_int <= AXI_FIXED_SIZE_WO_NARROW; -- When AXI-LITE (no narrow transfers supported) -- axi_arsize_int <= AXI_FIXED_SIZE_WO_NARROW; -- v1.03a axi_awsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3)); axi_arsize_int <= std_logic_vector (to_unsigned (AXI_FIXED_SIZE_WO_NARROW, 3)); end generate GEN_WO_NARROW; S_AXI_ARREADY <= S_AXI_ARREADY_int; S_AXI_AWREADY <= S_AXI_AWREADY_int; --------------------------------------------------------------------------- -- -- Generate: GEN_AXI_LITE -- Purpose: Create internal signals for lower level write and read -- channel modules to discard unused AXI signals when the -- AXI protocol is set up for AXI-LITE. -- --------------------------------------------------------------------------- GEN_AXI4LITE: if (IF_IS_AXI4LITE) generate begin -- For simulation purposes ONLY -- AXI Interconnect handles this in real system topologies. S_AXI_BID <= S_AXI_BID_int; S_AXI_RID <= S_AXI_RID_int; ----------------------------------------------------------------------- -- -- Generate: GEN_SIM_ONLY -- Purpose: Mimic behavior of AXI Interconnect in simulation. -- In real hardware system, AXI Interconnect stores and -- wraps value of ARID to RID and AWID to BID. -- ----------------------------------------------------------------------- GEN_SIM_ONLY: if (C_SIM_ONLY = '1') generate begin ------------------------------------------------------------------- -- Must register and wrap the AWID signal REG_BID: process (S_AXI_ACLK) begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if (S_AXI_ARESETN = C_RESET_ACTIVE) then S_AXI_BID_int <= (others => '0'); elsif (S_AXI_AWVALID = '1') and (S_AXI_AWREADY_int = '1') then S_AXI_BID_int <= S_AXI_AWID; else S_AXI_BID_int <= S_AXI_BID_int; end if; end if; end process REG_BID; ------------------------------------------------------------------- -- Must register and wrap the ARID signal REG_RID: process (S_AXI_ACLK) begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if (S_AXI_ARESETN = C_RESET_ACTIVE) then S_AXI_RID_int <= (others => '0'); elsif (S_AXI_ARVALID = '1') and (S_AXI_ARREADY_int = '1') then S_AXI_RID_int <= S_AXI_ARID; else S_AXI_RID_int <= S_AXI_RID_int; end if; end if; end process REG_RID; ------------------------------------------------------------------- end generate GEN_SIM_ONLY; --------------------------------------------------------------------------- -- -- Generate: GEN_HW -- Purpose: Drive default values of RID and BID. In real system -- these are left unconnected and AXI Interconnect is -- responsible for values. -- --------------------------------------------------------------------------- GEN_HW: if (C_SIM_ONLY = '0') generate begin S_AXI_BID_int <= (others => '0'); S_AXI_RID_int <= (others => '0'); end generate GEN_HW; --------------------------------------------------------------------------- -- Instance: I_AXI_LITE -- -- Description: -- This module is for the AXI-Lite -- instantiation of the BRAM controller interface. -- -- Responsible for shared address pipelining between the -- write address (AW) and read address (AR) channels. -- Controls (seperately) the data flows for the write data -- (W), write response (B), and read data (R) channels. -- -- Creates a shared port to BRAM (for all read and write -- transactions) or dual BRAM port utilization based on a -- generic parameter setting. -- -- Instantiates ECC register block if enabled and -- generates ECC logic, when enabled. -- -- --------------------------------------------------------------------------- I_AXI_LITE : entity work.axi_lite generic map ( C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , -- C_FAMILY => C_FAMILY , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC => C_ECC , C_ECC_TYPE => C_ECC_TYPE , -- v1.03a C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths) C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC C_FAULT_INJECT => C_FAULT_INJECT , C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , ECC_Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , AXI_AWADDR => S_AXI_AWADDR , AXI_AWVALID => S_AXI_AWVALID , AXI_AWREADY => S_AXI_AWREADY_int , AXI_WDATA => S_AXI_WDATA , AXI_WSTRB => S_AXI_WSTRB , AXI_WVALID => S_AXI_WVALID , AXI_WREADY => S_AXI_WREADY , AXI_BRESP => S_AXI_BRESP , AXI_BVALID => S_AXI_BVALID , AXI_BREADY => S_AXI_BREADY , AXI_ARADDR => S_AXI_ARADDR , AXI_ARVALID => S_AXI_ARVALID , AXI_ARREADY => S_AXI_ARREADY_int , AXI_RDATA => S_AXI_RDATA , AXI_RRESP => S_AXI_RRESP , AXI_RLAST => S_AXI_RLAST , AXI_RVALID => S_AXI_RVALID , AXI_RREADY => S_AXI_RREADY , -- Add AXI-Lite ECC Register Ports -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK , -- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN , AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , BRAM_En_A => bram_en_a_int , BRAM_WE_A => bram_we_a_int , BRAM_Addr_A => bram_addr_a_int , BRAM_WrData_A => bram_wrdata_a_int , BRAM_RdData_A => bram_rddata_a_int , BRAM_En_B => bram_en_b_int , BRAM_WE_B => bram_we_b_int , BRAM_Addr_B => bram_addr_b_int , BRAM_WrData_B => bram_wrdata_b_int , BRAM_RdData_B => bram_rddata_b_int ); end generate GEN_AXI4LITE; --------------------------------------------------------------------------- -- -- Generate: GEN_AXI -- Purpose: Only create internal signals for lower level write and read -- channel modules to assign AXI signals when the -- AXI protocol is set up for non AXI-LITE IF connections. -- For AXI4, all AXI signals are assigned to lower level modules. -- -- For AXI-Lite connections, generate statement above will -- create default values on these signals (assigned here). -- --------------------------------------------------------------------------- GEN_AXI4: if (IF_IS_AXI4) generate begin --------------------------------------------------------------------------- -- Instance: I_FULL_AXI -- -- Description: -- Full AXI BRAM controller logic. -- Instantiates wr_chnl and rd_chnl modules. -- If enabled, ECC register interface is included. -- --------------------------------------------------------------------------- I_FULL_AXI : entity work.full_axi generic map ( C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH , C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH , C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH , C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL , C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM , C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST , C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH , C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH , C_ECC => C_ECC , C_ECC_WIDTH => C_ECC_WIDTH , -- 8-bits for ECC (32 & 64-bit data widths) C_ECC_TYPE => C_ECC_TYPE , -- v1.03a C_FAULT_INJECT => C_FAULT_INJECT , C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE , C_ENABLE_AXI_CTRL_REG_IF => C_ENABLE_AXI_CTRL_REG_IF_I , -- Use internal constants determined by C_ECC C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS_I , C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS_I , C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS_I , C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER_I , C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH ) port map ( S_AXI_AClk => S_AXI_ACLK , S_AXI_AResetn => S_AXI_ARESETN , ECC_Interrupt => ECC_Interrupt , ECC_UE => ECC_UE , S_AXI_AWID => S_AXI_AWID , S_AXI_AWADDR => S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH-1 downto 0), S_AXI_AWLEN => S_AXI_AWLEN , S_AXI_AWSIZE => axi_awsize_int , S_AXI_AWBURST => S_AXI_AWBURST , S_AXI_AWLOCK => S_AXI_AWLOCK , S_AXI_AWCACHE => S_AXI_AWCACHE , S_AXI_AWPROT => S_AXI_AWPROT , S_AXI_AWVALID => S_AXI_AWVALID , S_AXI_AWREADY => S_AXI_AWREADY_int , S_AXI_WDATA => S_AXI_WDATA , S_AXI_WSTRB => S_AXI_WSTRB , S_AXI_WLAST => S_AXI_WLAST , S_AXI_WVALID => S_AXI_WVALID , S_AXI_WREADY => S_AXI_WREADY , S_AXI_BID => S_AXI_BID , S_AXI_BRESP => S_AXI_BRESP , S_AXI_BVALID => S_AXI_BVALID , S_AXI_BREADY => S_AXI_BREADY , S_AXI_ARID => S_AXI_ARID , S_AXI_ARADDR => S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH-1 downto 0), S_AXI_ARLEN => S_AXI_ARLEN , S_AXI_ARSIZE => axi_arsize_int , S_AXI_ARBURST => S_AXI_ARBURST , S_AXI_ARLOCK => S_AXI_ARLOCK , S_AXI_ARCACHE => S_AXI_ARCACHE , S_AXI_ARPROT => S_AXI_ARPROT , S_AXI_ARVALID => S_AXI_ARVALID , S_AXI_ARREADY => S_AXI_ARREADY_int , S_AXI_RID => S_AXI_RID , S_AXI_RDATA => S_AXI_RDATA , S_AXI_RRESP => S_AXI_RRESP , S_AXI_RLAST => S_AXI_RLAST , S_AXI_RVALID => S_AXI_RVALID , S_AXI_RREADY => S_AXI_RREADY , -- Add AXI-Lite ECC Register Ports -- Note: AXI-Lite Control IF and AXI IF share the same clock. -- S_AXI_CTRL_ACLK => S_AXI_CTRL_ACLK , -- S_AXI_CTRL_ARESETN => S_AXI_CTRL_ARESETN , S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID , S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY , S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR , S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA , S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID , S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY , S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP , S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID , S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY , S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR , S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID , S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY , S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA , S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP , S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID , S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY , BRAM_En_A => bram_en_a_int , BRAM_WE_A => bram_we_a_int , BRAM_WrData_A => bram_wrdata_a_int , BRAM_Addr_A => bram_addr_a_int , BRAM_RdData_A => bram_rddata_a_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) , BRAM_En_B => bram_en_b_int , BRAM_WE_B => bram_we_b_int , BRAM_Addr_B => bram_addr_b_int , BRAM_WrData_B => bram_wrdata_b_int , BRAM_RdData_B => bram_rddata_b_int (C_S_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) ); -- v1.02a -- Seperate instantiations for wr_chnl and rd_chnl moved to -- full_axi module. end generate GEN_AXI4; end architecture implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/demo/ipi_proj/srcs/ip/fmc_imageon_hdmi_in_v2_01_a/src/fmc_imageon_hdmi_in.vhd

7

9295

------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2011 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Aug 31, 2011 -- Design Name: FMC-IMAGEON -- Module Name: fmc_imageon_hdmi_in.vhd -- Project Name: FMC-IMAGEON -- Target Devices: Spartan-6, Virtex-6 -- Artix-7, Kintex-7, Virtex-7, Zynq -- Avnet Boards: FMC-IMAGEON -- -- Tool versions: ISE 14.3 -- -- Description: FMC-IMAGEON HDMI input interface. -- -- Dependencies: -- -- Revision: Aug 31, 2011: 1.01 Initial version -- Nov 11, 2011: 1.02 Add CCIR656 decode logic -- Remove VSYNC/HSYNC ports -- Feb 06, 2012: 1.03 Fix sync de-embed logic -- Change IOB attribute from "TRUE" to "FORCE" -- Oct 19, 2012: 2.01a Remove XSVI bus interface -- Remove xsvi_ prefixes to video_ -- Rename active_video to de -- Change IP_GROUP to FMC-IMAGEON -- ------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fmc_imageon_hdmi_in is Generic ( C_DATA_WIDTH : integer := 16; C_FAMILY : string := "virtex6" ); Port ( clk : in std_logic; -- IO Pins io_hdmii_spdif : in std_logic; io_hdmii_video : in std_logic_vector(15 downto 0); -- Audio Port audio_spdif : out std_logic; -- Video Ports -- video_vsync : out std_logic; -- video_hsync : out std_logic; video_vblank : out std_logic; video_hblank : out std_logic; video_de : out std_logic; video_data : out std_logic_vector((C_DATA_WIDTH-1) downto 0); -- Debug Port debug_o : out std_logic_vector(23 downto 0) ); end fmc_imageon_hdmi_in; architecture rtl of fmc_imageon_hdmi_in is -- -- IOB registers -- signal spdif_r : std_logic; signal video_r : std_logic_vector (15 downto 0); attribute IOB : string; attribute IOB of spdif_r: signal is "FORCE"; attribute IOB of video_r: signal is "FORCE"; -- -- Input Delay -- signal video_d1 : std_logic_vector(15 downto 0); signal video_d2 : std_logic_vector(15 downto 0); signal video_d3 : std_logic_vector(15 downto 0); signal video_d4 : std_logic_vector(15 downto 0); -- -- CCIR656 Decode Logic -- signal sc : std_logic; signal sav_va : std_logic; signal eav_va : std_logic; signal sav_vb : std_logic; signal eav_vb : std_logic; signal sav_va_d1 : std_logic; signal sav_va_d2 : std_logic; signal sav_va_d3 : std_logic; signal sav_va_d4 : std_logic; signal sav_vb_d1 : std_logic; signal sav_vb_d2 : std_logic; signal sav_vb_d3 : std_logic; signal sav_vb_d4 : std_logic; signal sync_code : std_logic; signal vblank : std_logic; signal hblank : std_logic; signal de : std_logic; begin -- -- IOB registers -- io_iregs_l : process (clk) begin if Rising_Edge(clk) then spdif_r <= io_hdmii_spdif; video_r <= io_hdmii_video; end if; end process; -- -- Input Delay -- input_delay_l : process (clk) begin if Rising_Edge(clk) then -- Delay DATA by 4 cycles to have a 4 cycle view of data video_d1 <= video_r; video_d2 <= video_d1; video_d3 <= video_d2; video_d4 <= video_d3; end if; end process; -- -- CCIR656 Decode Logic -- ccir656_decode_l : process ( video_r, video_d1, video_d2, video_d3, video_d4 ) begin -- Sync Code sc <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") ) then sc <= '1'; end if; -- Start of Active Video (active line) sav_va <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") and (video_r = X"8080") ) then sav_va <= '1'; end if; -- End of Active Video (active line) eav_va <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") and (video_r = X"9D9D") ) then eav_va <= '1'; end if; -- Start of Inactive Video (blank line) sav_vb <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d1 = X"0000") and (video_r = X"ABAB") ) then sav_vb <= '1'; end if; -- End of Inactive Video (blank line) eav_vb <= '0'; if ( (video_d3 = X"FFFF") and (video_d2 = X"0000") and (video_d2 = X"0000") and (video_r = X"B6B6") ) then eav_vb <= '1'; end if; end process; ccir656_syncgen_l : process (clk) begin if Rising_Edge(clk) then -- Delay SAV by 4 cycles sav_va_d1 <= sav_va; sav_va_d2 <= sav_va_d1; sav_va_d3 <= sav_va_d2; sav_va_d4 <= sav_va_d3; -- sav_vb_d1 <= sav_vb; sav_vb_d2 <= sav_vb_d1; sav_vb_d3 <= sav_vb_d2; sav_vb_d4 <= sav_vb_d3; -- Create generic Sync Code event indicator (for use with ChipScope) sync_code <= sc; -- Create DE strobe based on SAV/EAV events if ( sav_va_d4 = '1' ) then de <= '1'; end if; if ( eav_va = '1' or eav_vb = '1' ) then de <= '0'; end if; -- Create VBLANK strobes based on SAV events --if ( sav_vb = '1' ) then if ( sav_vb = '1' or eav_vb = '1' ) then vblank <= '1'; end if; if ( sav_va = '1' ) then vblank <= '0'; end if; -- Create HBLANK strobes based on SAV/EAV events if ( sav_va_d4 = '1' or sav_vb_d4 = '1' ) then hblank <= '0'; end if; if ( eav_va = '1' or eav_vb = '1' ) then hblank <= '1'; end if; end if; end process; -- -- Video Ports -- VIDEO_PORTS_16BIT_GEN : if (C_DATA_WIDTH = 16) generate video_ports_16bit_oregs_l : process (clk) begin if rising_edge( clk ) then -- video_vsync <= '0'; -- video_hsync <= '0'; video_vblank <= vblank; video_hblank <= hblank; video_de <= de; video_data <= video_d4; end if; end process; end generate VIDEO_PORTS_16BIT_GEN; -- -- Audio Port -- audio_spdif <= spdif_r; -- -- Debug Port -- Can be used to connect to ChipScope for debugging. -- Having a port makes these signals accessible for debug via EDK. -- debug_l : process (clk) begin if Rising_Edge(clk) then debug_o(15 downto 0) <= video_r; debug_o( 16) <= spdif_r; debug_o( 17) <= de; debug_o( 18) <= hblank; debug_o( 19) <= vblank; debug_o( 20) <= sav_va; debug_o( 21) <= sav_vb; debug_o( 22) <= eav_va or eav_vb; debug_o( 23) <= sync_code; end if; end process; end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_mm2s_omit_wrap.vhd

18

16390

------------------------------------------------------------------------------- -- axi_datamover_mm2s_omit_wrap.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_omit_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Omit Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_omit_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 0; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Lite MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 0; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input -------------------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ----------------------------------------------------------- -- MM2S Halt request input control------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ----------------------------------------------------------- -- Error discrete output ---------------------------------- mm2s_err : Out std_logic; -- -- Composite Error indication -- ----------------------------------------------------------- -- Optional MM2S Command and Status clock and Reset ----------- -- Only used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- --------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ---------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- ---------------------------------------------------------------- -- Address Posting contols ------------------------------------- mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- ---------------------------------------------------------------- -- MM2S AXI Address Channel I/O -------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- MM2S AXI MMap Read Data Channel I/O ------------------------------------------ mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- ---------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ----------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ----------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ---------------------------------------------------------------------- ); end entity axi_datamover_mm2s_omit_wrap; architecture implementation of axi_datamover_mm2s_omit_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; begin --(architecture implementation) mm2s_dbg_data <= X"BEEF0000" ; -- 32 bit Constant indicating OMIT type -- Just tie off output ports mm2s_halt_cmplt <= mm2s_halt ; mm2s_err <= '0' ; mm2s_cmd_wready <= '0' ; mm2s_sts_wvalid <= '0' ; mm2s_sts_wdata <= (others => '0'); mm2s_sts_wstrb <= (others => '0'); mm2s_sts_wlast <= '0' ; mm2s_arid <= (others => '0'); mm2s_araddr <= (others => '0'); mm2s_arlen <= (others => '0'); mm2s_arsize <= (others => '0'); mm2s_arburst <= (others => '0'); mm2s_arprot <= (others => '0'); mm2s_arcache <= (others => '0'); mm2s_aruser <= (others => '0'); mm2s_arvalid <= '0' ; mm2s_rready <= '0' ; mm2s_strm_wdata <= (others => '0'); mm2s_strm_wstrb <= (others => '0'); mm2s_strm_wlast <= '0' ; mm2s_strm_wvalid <= '0' ; mm2s_addr_req_posted <= '0' ; mm2s_rd_xfer_cmplt <= '0' ; -- Input ports are ignored end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/acme/ipi_proj/srcs/ip/vsrc_sel_v1_0/vhdl/video_src_sel.vhd

6

8306

-- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2010 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Library UNISIM; use UNISIM.vcomponents.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity vsrc_sel is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_CHANNELS : integer := 1 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ -- User logic ports video_clk_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_clk_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); de_1 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); de_2 : in std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_clk : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); hsync : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); vsync : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); de : out std_logic_vector(C_NUM_CHANNELS-1 downto 0); video_sel : in std_logic ); attribute MAX_FANOUT : string; attribute SIGIS : string; -- attribute SIGIS of Bus2IP_Clk : signal is "CLK"; -- attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity vsrc_sel; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of vsrc_sel is begin de <= de_1 when video_sel = '0' else de_2; hsync <= hsync_1 when video_sel = '0' else hsync_2; vsync <= vsync_1 when video_sel = '0' else vsync_2; VIDEO_SEL_GEN:for i in 0 to C_NUM_CHANNELS-1 generate begin BUFGMUX_INST : BUFGMUX generic map ( CLK_SEL_TYPE => "SYNC" -- Not supported. Must be "SYNC". ) port map ( O => video_clk(i), -- 1-bit output: Clock buffer output I0 => video_clk_1(i), -- 1-bit input: Clock buffer input (S=0) I1 => video_clk_2(i), -- 1-bit input: Clock buffer input (S=1) S => video_sel-- 1-bit input: Clock buffer select ); end generate VIDEO_SEL_GEN; end IMP;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd

5

92755

------------------------------------------------------------------------------- -- axi_datamover_s2mm_full_wrap.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_full_wrap.vhd -- -- Description: -- This file implements the DataMover S2MM FULL Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all ; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset ; use axi_datamover_v5_1.axi_datamover_cmd_status ; use axi_datamover_v5_1.axi_datamover_pcc ; use axi_datamover_v5_1.axi_datamover_ibttcc ; use axi_datamover_v5_1.axi_datamover_indet_btt ; use axi_datamover_v5_1.axi_datamover_s2mm_realign ; use axi_datamover_v5_1.axi_datamover_addr_cntl ; use axi_datamover_v5_1.axi_datamover_wrdata_cntl ; use axi_datamover_v5_1.axi_datamover_wr_status_cntl; Use axi_datamover_v5_1.axi_datamover_skid2mm_buf ; Use axi_datamover_v5_1.axi_datamover_skid_buf ; Use axi_datamover_v5_1.axi_datamover_wr_sf ; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_full_wrap is generic ( C_INCLUDE_S2MM : Integer range 0 to 2 := 1; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Lite S2MM functionality C_S2MM_AWID : Integer range 0 to 255 := 9; -- Specifies the constant value to output on -- the ARID output port C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_S2MM_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) General Purpose Store and Forward function -- 0 = Omit GP Store and Forward -- 1 = Include GP Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- S2MM Primary Clock and Reset inputs ---------------------------- s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- ------------------------------------------------------------------- -- S2MM Primary Reset input --------------------------------------- s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------- -- S2MM Halt request input control -------------------------------- s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------------- -- S2MM Error discrete output ------------------------------------- s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------------- -- Optional Command and Status Clock and Reset ------------------- -- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 -- -- s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ----------------------------------------------------- s2mm_cmd_wvalid : in std_logic; -- s2mm_cmd_wready : out std_logic; -- s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); -- -------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) -------------------------------------------------------- s2mm_sts_wvalid : out std_logic; -- s2mm_sts_wready : in std_logic; -- s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); -- s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); -- s2mm_sts_wlast : out std_logic; -- ---------------------------------------------------------------------------------------------------- -- Address posting controls --------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI Address Channel I/O -------------------------------------- s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel PROT output -- -- s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ----------- -- s2mm__awlock : out std_logic_vector(2 downto 0); -- -- s2mm__awcache : out std_logic_vector(4 downto 0); -- -- s2mm__awqos : out std_logic_vector(3 downto 0); -- -- s2mm__awregion : out std_logic_vector(3 downto 0); -- ----------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O --------------------------------------------- s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); -- s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); -- s2mm_wlast : Out std_logic; -- s2mm_wvalid : Out std_logic; -- s2mm_wready : In std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ----------------------------------------- s2mm_bresp : In std_logic_vector(1 downto 0); -- s2mm_bvalid : In std_logic; -- s2mm_bready : Out std_logic; -- -------------------------------------------------------------------------------------- -- S2MM AXI Master Stream Channel I/O ----------------------------------------------- s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); -- s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); -- s2mm_strm_wlast : In std_logic; -- s2mm_strm_wvalid : In std_logic; -- s2mm_strm_wready : Out std_logic; -- -------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ----------------------------------------------------------------- ); end entity axi_datamover_s2mm_full_wrap; architecture implementation of axi_datamover_s2mm_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_wdemux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Write Strobe demux select control. -- ------------------------------------------------------------------- function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_wdemux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin if (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_status_width -- -- Function Description: -- This function sets the width of the Status pipe depending on the -- Store and Forward inclusion or ommision. -- ------------------------------------------------------------------- function funct_set_status_width (store_forward_enabled : integer) return integer is Variable temp_status_bit_width : Integer := 8; begin If (store_forward_enabled = 1) Then temp_status_bit_width := 32; Else temp_status_bit_width := 8; End if; Return (temp_status_bit_width); end function funct_set_status_width; ------------------------------------------------------------------- -- Function -- -- Function Name: get_bits_needed -- -- Function Description: -- -- ------------------------------------------------------------------- function get_bits_needed (max_bytes : integer) return integer is Variable fvar_temp_bit_width : Integer := 1; begin if (max_bytes <= 1) then fvar_temp_bit_width := 1; elsif (max_bytes <= 3) then fvar_temp_bit_width := 2; elsif (max_bytes <= 7) then fvar_temp_bit_width := 3; elsif (max_bytes <= 15) then fvar_temp_bit_width := 4; elsif (max_bytes <= 31) then fvar_temp_bit_width := 5; elsif (max_bytes <= 63) then fvar_temp_bit_width := 6; elsif (max_bytes <= 127) then fvar_temp_bit_width := 7; elsif (max_bytes <= 255) then fvar_temp_bit_width := 8; elsif (max_bytes <= 511) then fvar_temp_bit_width := 9; elsif (max_bytes <= 1023) then fvar_temp_bit_width := 10; elsif (max_bytes <= 2047) then fvar_temp_bit_width := 11; elsif (max_bytes <= 4095) then fvar_temp_bit_width := 12; elsif (max_bytes <= 8191) then fvar_temp_bit_width := 13; else -- 8k - 16K fvar_temp_bit_width := 14; end if; Return (fvar_temp_bit_width); end function get_bits_needed; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_need_realigner -- -- Function Description: -- Determines if the Realigner module needs to be included. -- ------------------------------------------------------------------- function funct_need_realigner (indet_btt_enabled : integer; dre_included : integer; gp_sf_included : integer) return integer is Variable temp_val : Integer := 0; begin If ((indet_btt_enabled = 1) or (dre_included = 1) or (gp_sf_included = 1)) Then temp_val := 1; else temp_val := 0; End if; Return (temp_val); end function funct_need_realigner; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for S2MM -- modules downstream from the upsizing Store and Forward. If -- Store and forward is present, then the effective Stream width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Stream width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled > 0) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_bytes_per_dbeat -- -- Function Description: -- This function calculates the number of bytes transfered per -- databeat on the MMap AXI4 Write Data Channel by the S2MM. The -- value is based on input parameterization of included functions -- in the S2MM block. -- ------------------------------------------------------------------- function funct_get_bytes_per_dbeat (ibtt_enabled : integer ; gpsf_enabled : integer ; stream_dwidth : integer ; mmap_dwidth : integer ) return integer is Variable fvar_temp_bytes_per_xfer : Integer := 4; begin If (ibtt_enabled > 0 or gpsf_enabled > 0) Then -- transfers will be upsized to mmap data width fvar_temp_bytes_per_xfer := mmap_dwidth/8; Else -- transfers will be in stream data widths (may be narrow transfers on mmap) fvar_temp_bytes_per_xfer := stream_dwidth/8; End if; Return (fvar_temp_bytes_per_xfer); end function funct_get_bytes_per_dbeat; -- Constant Declarations ---------------------------------------- Constant SF_ENABLED : integer := C_INCLUDE_S2MM_GP_SF + C_S2MM_SUPPORT_INDET_BTT; Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_S2MM_MDATA_WIDTH, C_S2MM_SDATA_WIDTH, SF_ENABLED); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant IS_NOT_MM2S : integer range 0 to 1 := 0; Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID; Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH; Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH; Constant S2MM_MDATA_WIDTH : integer range 32 to 1024 := C_S2MM_MDATA_WIDTH; Constant S2MM_SDATA_WIDTH : integer range 8 to 1024 := C_S2MM_SDATA_WIDTH; Constant S2MM_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant S2MM_CMD_WIDTH : integer := (S2MM_TAG_WIDTH+S2MM_ADDR_WIDTH+32); Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := C_INCLUDE_S2MM_STSFIFO; Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH; Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC; Constant S2MM_BURST_SIZE : integer range 2 to 256 := C_S2MM_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH); Constant S2MM_BTT_USED : integer range 8 to 23 := C_S2MM_BTT_USED; Constant BITS_PER_BYTE : integer := 8; Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH; Constant S2MM_DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_S2MM_DRE, S2MM_SDATA_WIDTH); Constant DRE_SUPPORT_SCATTER : integer range 0 to 1 := 1; Constant ENABLE_INDET_BTT_SF : integer range 0 to 1 := C_S2MM_SUPPORT_INDET_BTT; Constant ENABLE_GP_SF : integer range 0 to 1 := C_INCLUDE_S2MM_GP_SF ; Constant BYTES_PER_MMAP_DBEAT : integer := funct_get_bytes_per_dbeat(ENABLE_INDET_BTT_SF , ENABLE_GP_SF , S2MM_SDATA_WIDTH , S2MM_MDATA_WIDTH); Constant MAX_BYTES_PER_BURST : integer := BYTES_PER_MMAP_DBEAT*S2MM_BURST_SIZE; Constant IBTT_XFER_BYTES_WIDTH : integer := get_bits_needed(MAX_BYTES_PER_BURST); Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2; -- 2 added for going -- full thresholding -- in WSC Constant WSC_STATUS_WIDTH : integer range 8 to 32 := funct_set_status_width(ENABLE_INDET_BTT_SF); Constant WSC_BYTES_RCVD_WIDTH : integer range 8 to 32 := S2MM_BTT_USED; Constant ADD_REALIGNER : integer := funct_need_realigner(ENABLE_INDET_BTT_SF , INCLUDE_S2MM_DRE , ENABLE_GP_SF); -- Calculates the minimum needed depth of the GP Store and Forward FIFO -- based on the S2MM pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) * S2MM_BURST_SIZE; -- Assigns the depth of the optional GP Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(S2MM_MDATA_WIDTH, S2MM_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_last : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2addr_data_rdy : std_logic := '0'; signal sig_data2all_tlast_error : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2wsc_calc_error : std_logic := '0'; signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0'); signal sig_data2wsc_cmd_empty : std_logic := '0'; signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(WSC_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2wsc_status_ready : std_logic := '0'; signal sig_wsc2stat_status_valid : std_logic := '0'; signal sig_wsc2mstr_halt_pipe : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wvalid : std_logic := '0'; signal sig_skid2data_wready : std_logic := '0'; signal sig_data2skid_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_data2skid_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_data2skid_wlast : std_logic := '0'; signal sig_skid2axi_wvalid : std_logic := '0'; signal sig_axi2skid_wready : std_logic := '0'; signal sig_skid2axi_wdata : std_logic_vector(S2MM_MDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_skid2axi_wstrb : std_logic_vector((S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_skid2axi_wlast : std_logic := '0'; signal sig_data2wsc_sof : std_logic := '0'; signal sig_data2wsc_eof : std_logic := '0'; signal sig_data2wsc_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_data2wsc_eop : std_logic := '0'; signal sig_data2wsc_bytes_rcvd : std_logic_vector(WSC_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2pcc_xfer_valid : std_logic := '0'; signal sig_pcc2sf_xfer_ready : std_logic := '0'; signal sig_sf2pcc_cmd_cmplt : std_logic := '0'; signal sig_sf2pcc_packet_eop : std_logic := '0'; signal sig_sf2pcc_xfer_bytes : std_logic_vector(IBTT_XFER_BYTES_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tvalid : std_logic := '0'; signal sig_wdc2ibtt_tready : std_logic := '0'; signal sig_ibtt2wdc_tdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ibtt2wdc_tlast : std_logic := '0'; signal sig_ibtt2wdc_eop : std_logic := '0'; signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(7 downto 0) := (others => '0'); signal sig_dre2ibtt_tvalid : std_logic := '0'; signal sig_ibtt2dre_tready : std_logic := '0'; signal sig_dre2ibtt_tdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2ibtt_tlast : std_logic := '0'; signal sig_dre2ibtt_eop : std_logic := '0'; signal sig_dre2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2dre_cmd_valid : std_logic := '0'; signal sig_mstr2dre_tag : std_logic_vector(S2MM_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_src_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_dre_dest_align : std_logic_vector(S2MM_DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_btt : std_logic_vector(S2MM_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2dre_drr : std_logic := '0'; signal sig_mstr2dre_eof : std_logic := '0'; signal sig_mstr2dre_cmd_cmplt : std_logic := '0'; signal sig_mstr2dre_calc_error : std_logic := '0'; signal sig_realign2wdc_eop_error : std_logic := '0'; signal sig_dre2all_halted : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_wsc2rst_stop_cmplt : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal skid2dre_wvalid : std_logic := '0'; signal dre2skid_wready : std_logic := '0'; signal skid2dre_wdata : std_logic_vector(S2MM_SDATA_WIDTH-1 downto 0) := (others => '0'); signal skid2dre_wstrb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal skid2dre_wlast : std_logic := '0'; signal sig_s2mm_allow_addr_req : std_logic := '0'; signal sig_ok_to_post_wr_addr : std_logic := '0'; signal sig_s2mm_addr_req_posted : std_logic := '0'; signal sig_s2mm_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_ibtt2wdc_error : std_logic := '0'; signal sig_sf_strt_addr_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2dre_sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal s2mm_awcache_int : std_logic_vector (3 downto 0); signal s2mm_awuser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug/Test Port Assignments s2mm_dbg_data <= sig_dbg_data_mux_out; -- Note that only the s2mm_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (s2mm_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"CAFE1111" ; -- 32 bit Constant indicating S2MM FULL type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2wsc_status_ready; sig_dbg_data_1(7) <= sig_wsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error --sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ADD_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen adds in the EOP status marker to the debug -- vector data when Indet BTT Store and Forward is enabled. -- ------------------------------------------------------------ GEN_ADD_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 1) generate begin sig_dbg_data_1(19) <= sig_wsc2stat_status(31) ; -- EOP Marker end generate GEN_ADD_DEBUG_EOP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DEBUG_EOP -- -- If Generate Description: -- -- This IfGen zeros the debug vector bit used for the EOP -- status marker when Indet BTT Store and Forward is not -- enabled. -- ------------------------------------------------------------ GEN_NO_DEBUG_EOP : if (ENABLE_INDET_BTT_SF = 0) generate begin sig_dbg_data_1(19) <= '0' ; -- EOP Marker end generate GEN_NO_DEBUG_EOP; ---- End of Debug/Test Support -------------------------------- -- Assign the Address posting control outputs s2mm_addr_req_posted <= sig_s2mm_addr_req_posted ; s2mm_wr_xfer_cmplt <= sig_s2mm_wr_xfer_cmplt ; s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len ; s2mm_wr_len <= sig_s2mm_wr_len ; -- Write Data Channel I/O s2mm_wvalid <= sig_skid2axi_wvalid; sig_axi2skid_wready <= s2mm_wready ; s2mm_wdata <= sig_skid2axi_wdata ; s2mm_wlast <= sig_skid2axi_wlast ; GEN_S2MM_TKEEP_ENABLE2 : if C_ENABLE_S2MM_TKEEP = 1 generate begin s2mm_wstrb <= sig_skid2axi_wstrb ; end generate GEN_S2MM_TKEEP_ENABLE2; GEN_S2MM_TKEEP_DISABLE2 : if C_ENABLE_S2MM_TKEEP = 0 generate begin s2mm_wstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE2; GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off s2mm_awcache <= s2mm_awcache_int; -- pre Interface-X guidelines for Masters s2mm_awuser <= s2mm_awuser_int; -- pre Interface-X guidelines for Masters sig_s2mm_cache_data <= s2mm_cmd_wdata(79 downto 72); -- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96); end generate GEN_CACHE2; -- Internal error output discrete s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ) port map ( primary_aclk => s2mm_aclk , primary_aresetn => s2mm_aresetn , secondary_awclk => s2mm_cmdsts_awclk , secondary_aresetn => s2mm_cmdsts_aresetn , halt_req => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => sig_wsc2rst_stop_cmplt , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO , C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , secondary_awclk => s2mm_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => s2mm_cmd_wvalid , cmd_wready => s2mm_cmd_wready , cmd_wdata => sig_s2mm_cmd_wdata , cache_data => sig_s2mm_cache_data , sts_wvalid => s2mm_sts_wvalid , sts_wready => s2mm_sts_wready , sts_wdata => s2mm_sts_wdata , sts_wstrb => s2mm_sts_wstrb , sts_wlast => s2mm_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_wsc2stat_status , stat2mstr_status_ready => sig_stat2wsc_status_ready , mst2stst_status_valid => sig_wsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_WR_STATUS_CNTLR -- -- Description: -- Write Status Controller Block -- ------------------------------------------------------------ I_WR_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_wr_status_cntl generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH , C_STS_WIDTH => WSC_STATUS_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2wsc_stop_request => sig_rst2all_stop_request , wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt , addr2wsc_addr_posted => sig_addr2data_addr_posted , s2mm_bresp => s2mm_bresp , s2mm_bvalid => s2mm_bvalid , s2mm_bready => s2mm_bready , calc2wsc_calc_error => sig_calc2dm_calc_err , addr2wsc_calc_error => sig_addr2wsc_calc_error , addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_error => sig_data2wsc_calc_err , data2wsc_last_error => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , data2wsc_valid => sig_data2wsc_valid , wsc2data_ready => sig_wsc2data_ready , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2stat_status => sig_wsc2stat_status , stat2wsc_status_ready => sig_stat2wsc_status_ready , wsc2stat_status_valid => sig_wsc2stat_status_valid , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_PCC -- -- If Generate Description: -- Include the normal Predictive Command Calculator function, -- Store and Forward is not an included feature. -- -- ------------------------------------------------------------ GEN_INCLUDE_PCC : if (ENABLE_INDET_BTT_SF = 0) generate begin ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_NOT_MM2S , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_SUPPORT_INDET_BTT => ENABLE_INDET_BTT_SF , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => open , mstr2data_dre_dest_align => open , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_PCC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_IBTTCC -- -- If Generate Description: -- Include the Indeterminate BTT Command Calculator function, -- Store and Forward is enabled in the S2MM. -- -- ------------------------------------------------------------ GEN_INCLUDE_IBTTCC : if (ENABLE_INDET_BTT_SF = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_MSTR_SFCC -- -- Description: -- Instantiates the Store and Forward Command Calculator -- Block. -- ------------------------------------------------------------ I_S2MM_MSTR_IBTTCC : entity axi_datamover_v5_1.axi_datamover_ibttcc generic map ( C_SF_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_CMD_WIDTH => S2MM_CMD_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_BTT_USED => S2MM_BTT_USED , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset ); end generate GEN_INCLUDE_IBTTCC; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate begin ------------------------------------------------------------ -- Instance: I_S2MM_STRM_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registerd Slave Stream inputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => s2mm_strm_wvalid , s_ready => s2mm_strm_wready , s_data => s2mm_strm_wdata , s_strb => s2mm_strm_wstrb , s_last => s2mm_strm_wlast , -- Master Side (Stream Data Output m_valid => skid2dre_wvalid , m_ready => dre2skid_wready , m_data => skid2dre_wdata , m_strb => skid2dre_wstrb , m_last => skid2dre_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate begin skid2dre_wvalid <= s2mm_strm_wvalid; s2mm_strm_wready <= dre2skid_wready; skid2dre_wdata <= s2mm_strm_wdata; skid2dre_wstrb <= s2mm_strm_wstrb; skid2dre_wlast <= s2mm_strm_wlast; end generate DISABLE_AXIS_SKID; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_REALIGNER -- -- If Generate Description: -- Omit the S2MM Realignment Engine -- -- ------------------------------------------------------------ GEN_NO_REALIGNER : if (ADD_REALIGNER = 0) generate begin -- Set to Always ready for DRE to PCC Command Interface sig_dre2mstr_cmd_ready <= LOGIC_HIGH; -- Without DRE and Scatter, the end of packet is the TLAST --sig_dre2ibtt_eop <= skid2dre_wlast ; sig_dre2ibtt_eop <= sig_dre2ibtt_tlast ; -- use skid buffered version -- Cant't detect undrrun/overrun here sig_realign2wdc_eop_error <= '0'; ENABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '1' generate begin ------------------------------------------------------------ -- Instance: I_NO_REALIGN_SKID_BUF -- -- Description: -- Instance for a Skid Buffer which provides for -- Fmax timing improvement between the Null Absorber and -- the Write Data controller when the Realigner is not -- present (no DRE and no Store and Forward case). -- ------------------------------------------------------------ I_NO_REALIGN_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => S2MM_SDATA_WIDTH ) port map ( -- System Ports aclk => s2mm_aclk , arst => sig_mmap_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => LOGIC_LOW , -- Slave Side (Null Absorber Input) s_valid => skid2dre_wvalid , s_ready => dre2skid_wready , s_data => skid2dre_wdata , s_strb => skid2dre_wstrb , s_last => skid2dre_wlast , -- Master Side (Stream Data Output to WData Cntlr) m_valid => sig_dre2ibtt_tvalid , m_ready => sig_ibtt2dre_tready , m_data => sig_dre2ibtt_tdata , m_strb => sig_dre2ibtt_tstrb , m_last => sig_dre2ibtt_tlast ); end generate ENABLE_NOREALIGNER_SKID; DISABLE_NOREALIGNER_SKID : if C_ENABLE_SKID_BUF(3) = '0' generate begin sig_dre2ibtt_tvalid <= skid2dre_wvalid; dre2skid_wready <= sig_ibtt2dre_tready; sig_dre2ibtt_tdata <= skid2dre_wdata; sig_dre2ibtt_tstrb <= skid2dre_wstrb; sig_dre2ibtt_tlast <= skid2dre_wlast; end generate DISABLE_NOREALIGNER_SKID; end generate GEN_NO_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_REALIGNER -- -- If Generate Description: -- Include the S2MM realigner Module. It hosts the S2MM DRE -- and the Scatter Block. -- -- Note that the General Purpose Store and Forward Module -- needs the Scatter function to detect input overrun and -- underrun events on the AXI Stream input. Thus the Realigner -- is included whenever the GP Store and Forward is enabled. -- ------------------------------------------------------------ GEN_INCLUDE_REALIGNER : if (ADD_REALIGNER = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_REALIGNER -- -- Description: -- Instance for the S2MM Data Realignment Module. -- ------------------------------------------------------------ I_S2MM_REALIGNER : entity axi_datamover_v5_1.axi_datamover_s2mm_realign generic map ( C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_INCLUDE_DRE => INCLUDE_S2MM_DRE , C_DRE_CNTL_FIFO_DEPTH => DRE_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => S2MM_DRE_ALIGN_WIDTH , C_SUPPORT_SCATTER => DRE_SUPPORT_SCATTER , C_BTT_USED => S2MM_BTT_USED , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , -- Write Data Controller or Store and Forward I/O ------- wdc2dre_wready => sig_ibtt2dre_tready , dre2wdc_wvalid => sig_dre2ibtt_tvalid , dre2wdc_wdata => sig_dre2ibtt_tdata , dre2wdc_wstrb => sig_dre2ibtt_tstrb , dre2wdc_wlast => sig_dre2ibtt_tlast , dre2wdc_eop => sig_dre2ibtt_eop , -- Starting offset output ------------------------------- dre2sf_strt_offset => sig_sf_strt_addr_offset , -- AXI Slave Stream In ----------------------------------- s2mm_strm_wready => dre2skid_wready , s2mm_strm_wvalid => skid2dre_wvalid , s2mm_strm_wdata => skid2dre_wdata , s2mm_strm_wstrb => skid2dre_wstrb , s2mm_strm_wlast => skid2dre_wlast , -- Command Calculator Interface -------------------------- dre2mstr_cmd_ready => sig_dre2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2dre_cmd_valid , mstr2dre_tag => sig_mstr2dre_tag , mstr2dre_dre_src_align => sig_mstr2dre_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2dre_dre_dest_align , mstr2dre_btt => sig_mstr2dre_btt , mstr2dre_drr => sig_mstr2dre_drr , mstr2dre_eof => sig_mstr2dre_eof , mstr2dre_cmd_cmplt => sig_mstr2dre_cmd_cmplt , mstr2dre_calc_error => sig_mstr2dre_calc_error , mstr2dre_strt_offset => sig_mstr2dre_sf_strt_offset , -- Premature TLAST assertion error flag dre2all_tlast_error => sig_realign2wdc_eop_error , -- DRE Halted Status dre2all_halted => sig_dre2all_halted ); end generate GEN_INCLUDE_REALIGNER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT_SF -- -- If Generate Description: -- Include the Indeterminate BTT Logic with specialized -- Store and Forward function, This also requires the -- Scatter Engine in the Realigner module. -- -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT_SF : if (ENABLE_INDET_BTT_SF = 1) generate begin -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; ------------------------------------------------------------ -- Instance: I_INDET_BTT -- -- Description: -- Instance for the Indeterminate BTT with Store and Forward -- module. -- ------------------------------------------------------------ I_INDET_BTT : entity axi_datamover_v5_1.axi_datamover_indet_btt generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_IBTT_XFER_BYTES_WIDTH => IBTT_XFER_BYTES_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_MAX_BURST_LEN => S2MM_BURST_SIZE , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_DRE => INCLUDE_S2MM_DRE , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , ibtt2wdc_stbs_asserted => sig_ibtt2wdc_stbs_asserted, ibtt2wdc_eop => sig_ibtt2wdc_eop , ibtt2wdc_tdata => sig_ibtt2wdc_tdata , ibtt2wdc_tstrb => sig_ibtt2wdc_tstrb , ibtt2wdc_tlast => sig_ibtt2wdc_tlast , ibtt2wdc_tvalid => sig_ibtt2wdc_tvalid , wdc2ibtt_tready => sig_wdc2ibtt_tready , dre2ibtt_tvalid => sig_dre2ibtt_tvalid , ibtt2dre_tready => sig_ibtt2dre_tready , dre2ibtt_tdata => sig_dre2ibtt_tdata , dre2ibtt_tstrb => sig_dre2ibtt_tstrb , dre2ibtt_tlast => sig_dre2ibtt_tlast , dre2ibtt_eop => sig_dre2ibtt_eop , dre2ibtt_strt_addr_offset => sig_sf_strt_addr_offset , sf2pcc_xfer_valid => sig_sf2pcc_xfer_valid , pcc2sf_xfer_ready => sig_pcc2sf_xfer_ready , sf2pcc_cmd_cmplt => sig_sf2pcc_cmd_cmplt , sf2pcc_packet_eop => sig_sf2pcc_packet_eop , sf2pcc_xfer_bytes => sig_sf2pcc_xfer_bytes ); end generate GEN_ENABLE_INDET_BTT_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_SF -- -- If Generate Description: -- Bypasses any store and Forward functions. -- -- ------------------------------------------------------------ GEN_NO_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 0) generate begin -- Use only external address posting enable sig_s2mm_allow_addr_req <= s2mm_allow_addr_req ; -- Housekeep unused signal in this case sig_ok_to_post_wr_addr <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; -- Just pass DRE signals through sig_ibtt2dre_tready <= sig_wdc2ibtt_tready ; sig_ibtt2wdc_tvalid <= sig_dre2ibtt_tvalid ; sig_ibtt2wdc_tdata <= sig_dre2ibtt_tdata ; sig_ibtt2wdc_tstrb <= sig_dre2ibtt_tstrb ; sig_ibtt2wdc_tlast <= sig_dre2ibtt_tlast ; sig_ibtt2wdc_eop <= sig_dre2ibtt_eop ; sig_ibtt2wdc_stbs_asserted <= (others => '0') ; -- Pass the Realigner EOP error through sig_ibtt2wdc_error <= sig_realign2wdc_eop_error; end generate GEN_NO_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_GP_SF -- -- If Generate Description: -- Include the General Purpose Store and Forward module. -- This If Generate can only be enabled when -- Indeterminate BTT mode is not enabled. The General Purpose -- Store and Forward is instantiated in place of the Indet -- BTT Store and Forward. -- ------------------------------------------------------------ GEN_INCLUDE_GP_SF : if (ENABLE_INDET_BTT_SF = 0 and ENABLE_GP_SF = 1) generate begin -- Merge the external address posting control with the -- SF address posting control. sig_s2mm_allow_addr_req <= s2mm_allow_addr_req and sig_ok_to_post_wr_addr ; -- Zero these out since Indet BTT is not enabled, they -- are only used by the WDC in that mode sig_ibtt2wdc_stbs_asserted <= (others => '0') ; sig_ibtt2wdc_eop <= '0' ; -- SFCC Interface Signals that are not used sig_pcc2sf_xfer_ready <= '0' ; sig_sf2pcc_xfer_valid <= '0' ; sig_sf2pcc_cmd_cmplt <= '0' ; sig_sf2pcc_packet_eop <= '0' ; sig_sf2pcc_xfer_bytes <= (others => '0') ; ------------------------------------------------------------ -- Instance: I_S2MM_GP_SF -- -- Description: -- Instance for the S2MM (Write) General Purpose Store and -- Forward Module. This module can only be enabled when -- Indeterminate BTT mode is not enabled. It is connected -- in place of the IBTT Module when GP SF is enabled. -- ------------------------------------------------------------ I_S2MM_GP_SF : entity axi_datamover_v5_1.axi_datamover_wr_sf generic map ( C_WR_ADDR_PIPE_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => S2MM_SDATA_WIDTH , C_STRT_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ----------------------------- aclk => s2mm_aclk , reset => sig_mmap_rst , -- Slave Stream Input -------------------------------- sf2sin_tready => sig_ibtt2dre_tready , sin2sf_tvalid => sig_dre2ibtt_tvalid , sin2sf_tdata => sig_dre2ibtt_tdata , sin2sf_tkeep => sig_dre2ibtt_tstrb , sin2sf_tlast => sig_dre2ibtt_tlast , sin2sf_error => sig_realign2wdc_eop_error , -- Starting Address Offset Input --------------------- sin2sf_strt_addr_offset => sig_sf_strt_addr_offset , -- DataMover Write Side Address Pipelining Control Interface -------- ok_to_post_wr_addr => sig_ok_to_post_wr_addr , wr_addr_posted => sig_s2mm_addr_req_posted , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , wr_ld_nxt_len => sig_s2mm_ld_nxt_len , wr_len => sig_s2mm_wr_len , -- Write Side Stream Out to DataMover S2MM ------------- sout2sf_tready => sig_wdc2ibtt_tready , sf2sout_tvalid => sig_ibtt2wdc_tvalid , sf2sout_tdata => sig_ibtt2wdc_tdata , sf2sout_tkeep => sig_ibtt2wdc_tstrb , sf2sout_tlast => sig_ibtt2wdc_tlast , sf2sout_error => sig_ibtt2wdc_error ); end generate GEN_INCLUDE_GP_SF; ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => S2MM_ADDR_WIDTH , C_ADDR_ID => S2MM_AWID_VALUE , C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => s2mm_awid , addr2axi_aaddr => s2mm_awaddr , addr2axi_alen => s2mm_awlen , addr2axi_asize => s2mm_awsize , addr2axi_aburst => s2mm_awburst , addr2axi_aprot => s2mm_awprot , addr2axi_avalid => s2mm_awvalid , addr2axi_acache => s2mm_awcache_int , addr2axi_auser => s2mm_awuser_int , axi2addr_aready => s2mm_awready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , -- mstr2addr_cache_info => sig_cache2mstr_command , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_s2mm_allow_addr_req , addr_req_posted => sig_s2mm_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2wsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_WR_DATA_CNTL -- -- Description: -- Write Data Controller Block -- ------------------------------------------------------------ I_WR_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_wrdata_cntl generic map ( C_REALIGNER_INCLUDED => ADD_REALIGNER , C_ENABLE_INDET_BTT => ENABLE_INDET_BTT_SF , C_SF_BYTES_RCVD_WIDTH => WSC_BYTES_RCVD_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => S2MM_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => s2mm_aclk , mmap_reset => sig_mmap_rst , rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len , s2mm_wr_len => sig_s2mm_wr_len , data2skid_saddr_lsb => sig_data2skid_addr_lsb , data2skid_wdata => sig_data2skid_wdata , data2skid_wstrb => sig_data2skid_wstrb , data2skid_wlast => sig_data2skid_wlast , data2skid_wvalid => sig_data2skid_wvalid , skid2data_wready => sig_skid2data_wready , s2mm_strm_wvalid => sig_ibtt2wdc_tvalid , s2mm_strm_wready => sig_wdc2ibtt_tready , s2mm_strm_wdata => sig_ibtt2wdc_tdata , s2mm_strm_wstrb => sig_ibtt2wdc_tstrb , s2mm_strm_wlast => sig_ibtt2wdc_tlast , s2mm_strm_eop => sig_ibtt2wdc_eop , s2mm_stbs_asserted => sig_ibtt2wdc_stbs_asserted, realign2wdc_eop_error => sig_ibtt2wdc_error , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_last , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => sig_data2addr_data_rdy , data2all_tlast_error => sig_data2all_tlast_error , data2all_dcntlr_halted => sig_data2all_dcntlr_halted, data2skid_halt => sig_data2skid_halt , data2wsc_tag => sig_data2wsc_tag , data2wsc_calc_err => sig_data2wsc_calc_err , data2wsc_last_err => sig_data2wsc_last_err , data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt , wsc2data_ready => sig_wsc2data_ready , data2wsc_valid => sig_data2wsc_valid , data2wsc_eop => sig_data2wsc_eop , data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd , wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe ); --ENABLE_AXIMMAP_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate --begin ------------------------------------------------------------ -- Instance: I_S2MM_MMAP_SKID_BUF -- -- Description: -- Instance for the S2MM Skid Buffer which provides for -- registered outputs and supports bi-dir throttling. -- -- This Module also provides Write Data Bus Mirroring and WSTRB -- Demuxing to match a narrow Stream to a wider MMap Write -- Channel. By doing this in the skid buffer, the resource -- utilization of the skid buffer can be minimized by only -- having to buffer/mux the Stream data width, not the MMap -- Data width. -- ------------------------------------------------------------ I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid2mm_buf generic map ( C_MDATA_WIDTH => S2MM_MDATA_WIDTH , C_SDATA_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH ) port map ( -- System Ports ACLK => s2mm_aclk , ARST => sig_stream_rst , -- Slave Side (Wr Data Controller Input Side ) S_ADDR_LSB => sig_data2skid_addr_lsb, S_VALID => sig_data2skid_wvalid , S_READY => sig_skid2data_wready , S_Data => sig_data2skid_wdata , S_STRB => sig_data2skid_wstrb , S_Last => sig_data2skid_wlast , -- Master Side (MMap Write Data Output Side) M_VALID => sig_skid2axi_wvalid , M_READY => sig_axi2skid_wready , M_Data => sig_skid2axi_wdata , M_STRB => sig_skid2axi_wstrb , M_Last => sig_skid2axi_wlast ); --end generate ENABLE_AXIMMAP_SKID; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/vhdl/FIFO_image_filter_img_0_data_stream_1_V.vhd

4

4629

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_img_0_data_stream_1_V_shiftReg; architecture rtl of FIFO_image_filter_img_0_data_stream_1_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_img_0_data_stream_1_V is generic ( MEM_STYLE : string := "auto"; DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_img_0_data_stream_1_V is component FIFO_image_filter_img_0_data_stream_1_V_shiftReg is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 1; DEPTH : integer := 2); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_img_0_data_stream_1_V_shiftReg : FIFO_image_filter_img_0_data_stream_1_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_q_mngr.vhd

3

39575

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_q_mngr.vhd -- Description: This entity is the descriptor update queue manager -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_q_mngr is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33; -- 1 IOC bit + 32 Update Status Bits C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0; -- Number of descriptors to fetch and queue for each channel. -- A value of zero excludes the fetch queues. C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8; -- Number of words to update C_INCLUDE_CH1 : integer range 0 to 1 := 1; -- Include or Exclude channel 1 scatter gather engine -- 0 = Exclude Channel 1 SG Engine -- 1 = Include Channel 1 SG Engine C_INCLUDE_CH2 : integer range 0 to 1 := 1; -- Include or Exclude channel 2 scatter gather engine -- 0 = Exclude Channel 2 SG Engine -- 1 = Include Channel 2 SG Engine C_AXIS_IS_ASYNC : integer range 0 to 1 := 0; -- Channel 1 is async to sg_aclk -- 0 = Synchronous to SG ACLK -- 1 = Asynchronous to SG ACLK C_FAMILY : string := "virtex7" -- Device family used for proper BRAM selection ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- --***********************************-- -- --** Channel 1 Control **-- -- --***********************************-- -- ch1_updt_curdesc_wren : out std_logic ; -- ch1_updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch1_updt_active : in std_logic ; -- ch1_updt_queue_empty : out std_logic ; -- ch1_updt_ioc : out std_logic ; -- ch1_updt_ioc_irq_set : in std_logic ; -- -- ch1_dma_interr : out std_logic ; -- ch1_dma_slverr : out std_logic ; -- ch1_dma_decerr : out std_logic ; -- ch1_dma_interr_set : in std_logic ; -- ch1_dma_slverr_set : in std_logic ; -- ch1_dma_decerr_set : in std_logic ; -- -- --***********************************-- -- --** Channel 2 Control **-- -- --***********************************-- -- ch2_updt_active : in std_logic ; -- -- ch2_updt_curdesc_wren : out std_logic ; -- -- ch2_updt_curdesc : out std_logic_vector -- -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- ch2_updt_queue_empty : out std_logic ; -- ch2_updt_ioc : out std_logic ; -- ch2_updt_ioc_irq_set : in std_logic ; -- -- ch2_dma_interr : out std_logic ; -- ch2_dma_slverr : out std_logic ; -- ch2_dma_decerr : out std_logic ; -- ch2_dma_interr_set : in std_logic ; -- ch2_dma_slverr_set : in std_logic ; -- ch2_dma_decerr_set : in std_logic ; -- -- --***********************************-- -- --** Channel 1 Update Interface In **-- -- --***********************************-- -- s_axis_ch1_updt_aclk : in std_logic ; -- -- Update Pointer Stream -- s_axis_ch1_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_ch1_updtptr_tvalid : in std_logic ; -- s_axis_ch1_updtptr_tready : out std_logic ; -- s_axis_ch1_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_ch1_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_ch1_updtsts_tvalid : in std_logic ; -- s_axis_ch1_updtsts_tready : out std_logic ; -- s_axis_ch1_updtsts_tlast : in std_logic ; -- -- --***********************************-- -- --** Channel 2 Update Interface In **-- -- --***********************************-- -- s_axis_ch2_updt_aclk : in std_logic ; -- -- Update Pointer Stream -- s_axis_ch2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); -- s_axis_ch2_updtptr_tvalid : in std_logic ; -- s_axis_ch2_updtptr_tready : out std_logic ; -- s_axis_ch2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_ch2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_ch2_updtsts_tvalid : in std_logic ; -- s_axis_ch2_updtsts_tready : out std_logic ; -- s_axis_ch2_updtsts_tlast : in std_logic ; -- -- --***************************************-- -- --** Update Interface to AXI DataMover **-- -- --***************************************-- -- -- S2MM Stream Out To DataMover -- s_axis_s2mm_tdata : out std_logic_vector -- (C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; -- s_axis_s2mm_tlast : out std_logic ; -- s_axis_s2mm_tvalid : out std_logic ; -- s_axis_s2mm_tready : in std_logic -- ); end axi_sg_updt_q_mngr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_q_mngr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal m_axis_ch1_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_ch1_updt_tlast : std_logic := '0'; signal m_axis_ch1_updt_tvalid : std_logic := '0'; signal m_axis_ch1_updt_tready : std_logic := '0'; signal m_axis_ch2_updt_tdata : std_logic_vector(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); signal m_axis_ch2_updt_tlast : std_logic := '0'; signal m_axis_ch2_updt_tvalid : std_logic := '0'; signal m_axis_ch2_updt_tready : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin --***************************************************************************** --** CHANNEL 1 ** --***************************************************************************** ------------------------------------------------------------------------------- -- If Channel 1 is enabled then instantiate descriptor update logic. ------------------------------------------------------------------------------- -- If Descriptor Update queueing enabled then instantiate Queue Logic GEN_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate begin ------------------------------------------------------------------------------- I_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE , C_SG_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE , C_SG2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE , C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC , C_INCLUDE_MM2S => C_INCLUDE_CH1 , C_INCLUDE_S2MM => C_INCLUDE_CH2 , C_FAMILY => C_FAMILY ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , s_axis_updt_aclk => s_axis_ch1_updt_aclk , --********************************-- --** Control and Status **-- --********************************-- updt_curdesc_wren => ch1_updt_curdesc_wren , updt_curdesc => ch1_updt_curdesc , updt_active => ch1_updt_active , updt_queue_empty => ch1_updt_queue_empty , updt_ioc => ch1_updt_ioc , updt_ioc_irq_set => ch1_updt_ioc_irq_set , dma_interr => ch1_dma_interr , dma_slverr => ch1_dma_slverr , dma_decerr => ch1_dma_decerr , dma_interr_set => ch1_dma_interr_set , dma_slverr_set => ch1_dma_slverr_set , dma_decerr_set => ch1_dma_decerr_set , -- updt2_curdesc_wren => ch2_updt_curdesc_wren , -- updt2_curdesc => ch2_updt_curdesc , updt2_active => ch2_updt_active , updt2_queue_empty => ch2_updt_queue_empty , updt2_ioc => ch2_updt_ioc , updt2_ioc_irq_set => ch2_updt_ioc_irq_set , dma2_interr => ch2_dma_interr , dma2_slverr => ch2_dma_slverr , dma2_decerr => ch2_dma_decerr , dma2_interr_set => ch2_dma_interr_set , dma2_slverr_set => ch2_dma_slverr_set , dma2_decerr_set => ch2_dma_decerr_set , --********************************-- --** Update Interfaces In **-- --********************************-- -- Update Pointer Stream s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata , s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid , s_axis_updtptr_tready => s_axis_ch1_updtptr_tready , s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast , -- Update Status Stream s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata , s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid , s_axis_updtsts_tready => s_axis_ch1_updtsts_tready , s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast , -- Update Pointer Stream s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata , s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready , s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- Update Status Stream s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata , s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready , s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast , --********************************-- --** Update Interfaces Out **-- --********************************-- -- S2MM Stream Out To DataMover m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata , m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast , m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid , m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready , -- m_axis2_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis2_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis2_updt_tready => m_axis_ch2_updt_tready ); end generate GEN_QUEUE; --***************************************************************************** --** CHANNEL 1 - NO DESCRIPTOR QUEUE ** --***************************************************************************** -- No update queue enabled, therefore map internal stream logic -- directly to channel port. GEN_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate begin I_NO_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue generic map( C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ) port map( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk => m_axi_sg_aclk , m_axi_sg_aresetn => m_axi_sg_aresetn , --********************************-- --** Control and Status **-- --********************************-- updt_curdesc_wren => ch1_updt_curdesc_wren , updt_curdesc => ch1_updt_curdesc , updt_active => ch1_updt_active , updt_queue_empty => ch1_updt_queue_empty , updt_ioc => ch1_updt_ioc , updt_ioc_irq_set => ch1_updt_ioc_irq_set , dma_interr => ch1_dma_interr , dma_slverr => ch1_dma_slverr , dma_decerr => ch1_dma_decerr , dma_interr_set => ch1_dma_interr_set , dma_slverr_set => ch1_dma_slverr_set , dma_decerr_set => ch1_dma_decerr_set , updt2_active => ch2_updt_active , updt2_queue_empty => ch2_updt_queue_empty , updt2_ioc => ch2_updt_ioc , updt2_ioc_irq_set => ch2_updt_ioc_irq_set , dma2_interr => ch2_dma_interr , dma2_slverr => ch2_dma_slverr , dma2_decerr => ch2_dma_decerr , dma2_interr_set => ch2_dma_interr_set , dma2_slverr_set => ch2_dma_slverr_set , dma2_decerr_set => ch2_dma_decerr_set , --********************************-- --** Update Interfaces In **-- --********************************-- -- Update Pointer Stream s_axis_updtptr_tdata => s_axis_ch1_updtptr_tdata , s_axis_updtptr_tvalid => s_axis_ch1_updtptr_tvalid , s_axis_updtptr_tready => s_axis_ch1_updtptr_tready , s_axis_updtptr_tlast => s_axis_ch1_updtptr_tlast , -- Update Status Stream s_axis_updtsts_tdata => s_axis_ch1_updtsts_tdata , s_axis_updtsts_tvalid => s_axis_ch1_updtsts_tvalid , s_axis_updtsts_tready => s_axis_ch1_updtsts_tready , s_axis_updtsts_tlast => s_axis_ch1_updtsts_tlast , -- Update Pointer Stream s_axis2_updtptr_tdata => s_axis_ch2_updtptr_tdata , s_axis2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , s_axis2_updtptr_tready => s_axis_ch2_updtptr_tready , s_axis2_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- Update Status Stream s_axis2_updtsts_tdata => s_axis_ch2_updtsts_tdata , s_axis2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , s_axis2_updtsts_tready => s_axis_ch2_updtsts_tready , s_axis2_updtsts_tlast => s_axis_ch2_updtsts_tlast , --********************************-- --** Update Interfaces Out **-- --********************************-- -- S2MM Stream Out To DataMover m_axis_updt_tdata => s_axis_s2mm_tdata, --m_axis_ch1_updt_tdata , m_axis_updt_tlast => s_axis_s2mm_tlast, --m_axis_ch1_updt_tlast , m_axis_updt_tvalid => s_axis_s2mm_tvalid, --m_axis_ch1_updt_tvalid , m_axis_updt_tready => s_axis_s2mm_tready --m_axis_ch1_updt_tready , -- m_axis_updt_tdata => m_axis_ch1_updt_tdata , -- m_axis_updt_tlast => m_axis_ch1_updt_tlast , -- m_axis_updt_tvalid => m_axis_ch1_updt_tvalid , -- m_axis_updt_tready => m_axis_ch1_updt_tready , -- S2MM Stream Out To DataMover -- m_axis2_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis2_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis2_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis2_updt_tready => m_axis_ch2_updt_tready ); end generate GEN_NO_QUEUE; -- Channel 1 NOT included therefore tie ch1 outputs off --GEN_NO_CH1_UPDATE_Q_IF : if C_INCLUDE_CH1 = 0 generate --begin -- ch1_updt_curdesc_wren <= '0'; -- ch1_updt_curdesc <= (others => '0'); -- ch1_updt_queue_empty <= '1'; -- ch1_updt_ioc <= '0'; -- ch1_dma_interr <= '0'; -- ch1_dma_slverr <= '0'; -- ch1_dma_decerr <= '0'; -- m_axis_ch1_updt_tdata <= (others => '0'); -- m_axis_ch1_updt_tlast <= '0'; -- m_axis_ch1_updt_tvalid <= '0'; -- s_axis_ch1_updtptr_tready <= '0'; -- s_axis_ch1_updtsts_tready <= '0'; --end generate GEN_NO_CH1_UPDATE_Q_IF; --***************************************************************************** --** CHANNEL 2 ** --***************************************************************************** ------------------------------------------------------------------------------- -- If Channel 2 is enabled then instantiate descriptor update logic. ------------------------------------------------------------------------------- --GEN_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 1 generate -- --begin -- -- --************************************************************************* -- --** CHANNEL 2 - DESCRIPTOR QUEUE ** -- --************************************************************************* -- -- If Descriptor Update queueing enabled then instantiate Queue Logic -- GEN_CH2_QUEUE : if C_SG_UPDT_DESC2QUEUE /= 0 generate -- begin -- --------------------------------------------------------------------------- -- I_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_queue -- generic map( -- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , -- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , -- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , -- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH , -- C_SG_UPDT_DESC2QUEUE => C_SG_UPDT_DESC2QUEUE , -- C_SG_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE , -- C_FAMILY => C_FAMILY -- ) -- port map( -- --------------------------------------------------------------- -- -- AXI Scatter Gather Interface -- --------------------------------------------------------------- -- m_axi_sg_aclk => m_axi_sg_aclk , -- m_axi_sg_aresetn => m_axi_sg_aresetn , -- s_axis_updt_aclk => s_axis_ch2_updt_aclk , -- -- --********************************-- -- --** Control and Status **-- -- --********************************-- -- updt_curdesc_wren => ch2_updt_curdesc_wren , -- updt_curdesc => ch2_updt_curdesc , -- updt_active => ch2_updt_active , -- updt_queue_empty => ch2_updt_queue_empty , -- updt_ioc => ch2_updt_ioc , -- updt_ioc_irq_set => ch2_updt_ioc_irq_set , -- -- dma_interr => ch2_dma_interr , -- dma_slverr => ch2_dma_slverr , -- dma_decerr => ch2_dma_decerr , -- dma_interr_set => ch2_dma_interr_set , -- dma_slverr_set => ch2_dma_slverr_set , -- dma_decerr_set => ch2_dma_decerr_set , -- -- --********************************-- -- --** Update Interfaces In **-- -- --********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata , -- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , -- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready , -- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- -- -- Update Status Stream -- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata , -- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , -- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready , -- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast , -- -- --********************************-- -- --** Update Interfaces Out **-- -- --********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis_updt_tready => m_axis_ch2_updt_tready -- ); -- -- end generate GEN_CH2_QUEUE; -- -- -- --***************************************************************************** -- --** CHANNEL 2 - NO DESCRIPTOR QUEUE ** -- --***************************************************************************** -- -- -- No update queue enabled, therefore map internal stream logic -- -- directly to channel port. -- GEN_CH2_NO_QUEUE : if C_SG_UPDT_DESC2QUEUE = 0 generate -- I_NO_CH2_UPDT_DESC_QUEUE : entity axi_sg_v4_1.axi_sg_updt_noqueue -- generic map( -- C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH , -- C_M_AXIS_UPDT_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH , -- C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH , -- C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH -- ) -- port map( -- --------------------------------------------------------------- -- -- AXI Scatter Gather Interface -- --------------------------------------------------------------- -- m_axi_sg_aclk => m_axi_sg_aclk , -- m_axi_sg_aresetn => m_axi_sg_aresetn , -- -- --********************************-- -- --** Control and Status **-- -- --********************************-- -- updt_curdesc_wren => ch2_updt_curdesc_wren , -- updt_curdesc => ch2_updt_curdesc , -- updt_active => ch2_updt_active , -- updt_queue_empty => ch2_updt_queue_empty , -- updt_ioc => ch2_updt_ioc , -- updt_ioc_irq_set => ch2_updt_ioc_irq_set , -- -- dma_interr => ch2_dma_interr , -- dma_slverr => ch2_dma_slverr , -- dma_decerr => ch2_dma_decerr , -- dma_interr_set => ch2_dma_interr_set , -- dma_slverr_set => ch2_dma_slverr_set , -- dma_decerr_set => ch2_dma_decerr_set , -- -- --********************************-- -- --** Update Interfaces In **-- -- --********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata => s_axis_ch2_updtptr_tdata , -- s_axis_updtptr_tvalid => s_axis_ch2_updtptr_tvalid , -- s_axis_updtptr_tready => s_axis_ch2_updtptr_tready , -- s_axis_updtptr_tlast => s_axis_ch2_updtptr_tlast , -- -- -- Update Status Stream -- s_axis_updtsts_tdata => s_axis_ch2_updtsts_tdata , -- s_axis_updtsts_tvalid => s_axis_ch2_updtsts_tvalid , -- s_axis_updtsts_tready => s_axis_ch2_updtsts_tready , -- s_axis_updtsts_tlast => s_axis_ch2_updtsts_tlast , -- -- --********************************-- -- --** Update Interfaces Out **-- -- --********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata => m_axis_ch2_updt_tdata , -- m_axis_updt_tlast => m_axis_ch2_updt_tlast , -- m_axis_updt_tvalid => m_axis_ch2_updt_tvalid , -- m_axis_updt_tready => m_axis_ch2_updt_tready -- ); -- -- end generate GEN_CH2_NO_QUEUE; -- --end generate GEN_CH2_UPDATE_Q_IF; -- ---- Channel 2 NOT included therefore tie ch2 outputs off --GEN_NO_CH2_UPDATE_Q_IF : if C_INCLUDE_CH2 = 0 generate --begin -- ch2_updt_curdesc_wren <= '0'; -- ch2_updt_curdesc <= (others => '0'); -- ch2_updt_queue_empty <= '1'; -- -- ch2_updt_ioc <= '0'; -- ch2_dma_interr <= '0'; -- ch2_dma_slverr <= '0'; -- ch2_dma_decerr <= '0'; -- -- m_axis_ch2_updt_tdata <= (others => '0'); -- m_axis_ch2_updt_tlast <= '0'; -- m_axis_ch2_updt_tvalid <= '0'; -- -- s_axis_ch2_updtptr_tready <= '0'; -- s_axis_ch2_updtsts_tready <= '0'; -- --end generate GEN_NO_CH2_UPDATE_Q_IF; ------------------------------------------------------------------------------- -- MUX For DataMover ------------------------------------------------------------------------------- --TO_DATAMVR_MUX : process(ch1_updt_active, -- ch2_updt_active, -- m_axis_ch1_updt_tdata, -- m_axis_ch1_updt_tlast, -- m_axis_ch1_updt_tvalid, -- m_axis_ch2_updt_tdata, -- m_axis_ch2_updt_tlast, -- m_axis_ch2_updt_tvalid) -- begin -- if(ch1_updt_active = '1')then -- s_axis_s2mm_tdata <= m_axis_ch1_updt_tdata; -- s_axis_s2mm_tlast <= m_axis_ch1_updt_tlast; -- s_axis_s2mm_tvalid <= m_axis_ch1_updt_tvalid; -- elsif(ch2_updt_active = '1')then -- s_axis_s2mm_tdata <= m_axis_ch2_updt_tdata; -- s_axis_s2mm_tlast <= m_axis_ch2_updt_tlast; -- s_axis_s2mm_tvalid <= m_axis_ch2_updt_tvalid; -- else -- s_axis_s2mm_tdata <= (others => '0'); -- s_axis_s2mm_tlast <= '0'; -- s_axis_s2mm_tvalid <= '0'; -- end if; -- end process TO_DATAMVR_MUX; -- --m_axis_ch1_updt_tready <= s_axis_s2mm_tready; --m_axis_ch2_updt_tready <= s_axis_s2mm_tready; -- end implementation;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/FIFO_image_filter_gray_rows_V.vhd

2

4556

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity FIFO_image_filter_gray_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end FIFO_image_filter_gray_rows_V_shiftReg; architecture rtl of FIFO_image_filter_gray_rows_V_shiftReg is --constant DEPTH_WIDTH: integer := 16; type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0); signal SRL_SIG : SRL_ARRAY; begin p_shift: process (clk) begin if (clk'event and clk = '1') then if (ce = '1') then SRL_SIG <= data & SRL_SIG(0 to DEPTH-2); end if; end if; end process; q <= SRL_SIG(conv_integer(a)); end rtl; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity FIFO_image_filter_gray_rows_V is generic ( MEM_STYLE : string := "shiftreg"; DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : IN STD_LOGIC; reset : IN STD_LOGIC; if_empty_n : OUT STD_LOGIC; if_read_ce : IN STD_LOGIC; if_read : IN STD_LOGIC; if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); if_full_n : OUT STD_LOGIC; if_write_ce : IN STD_LOGIC; if_write : IN STD_LOGIC; if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0)); end entity; architecture rtl of FIFO_image_filter_gray_rows_V is component FIFO_image_filter_gray_rows_V_shiftReg is generic ( DATA_WIDTH : integer := 12; ADDR_WIDTH : integer := 2; DEPTH : integer := 3); port ( clk : in std_logic; data : in std_logic_vector(DATA_WIDTH-1 downto 0); ce : in std_logic; a : in std_logic_vector(ADDR_WIDTH-1 downto 0); q : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component; signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0); signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); signal shiftReg_ce : STD_LOGIC; signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1'); signal internal_empty_n : STD_LOGIC := '0'; signal internal_full_n : STD_LOGIC := '1'; begin if_empty_n <= internal_empty_n; if_full_n <= internal_full_n; shiftReg_data <= if_din; if_dout <= shiftReg_q; process (clk) begin if clk'event and clk = '1' then if reset = '1' then mOutPtr <= (others => '1'); internal_empty_n <= '0'; internal_full_n <= '1'; else if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and ((if_write and if_write_ce) = '0' or internal_full_n = '0') then mOutPtr <= mOutPtr -1; if (mOutPtr = 0) then internal_empty_n <= '0'; end if; internal_full_n <= '1'; elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and ((if_write and if_write_ce) = '1' and internal_full_n = '1') then mOutPtr <= mOutPtr +1; internal_empty_n <= '1'; if (mOutPtr = DEPTH -2) then internal_full_n <= '0'; end if; end if; end if; end if; end process; shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0); shiftReg_ce <= (if_write and if_write_ce) and internal_full_n; U_FIFO_image_filter_gray_rows_V_shiftReg : FIFO_image_filter_gray_rows_V_shiftReg generic map ( DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH, DEPTH => DEPTH) port map ( clk => clk, data => shiftReg_data, ce => shiftReg_ce, a => shiftReg_addr, q => shiftReg_q); end rtl;

gpl-3.0

freecores/usb_fpga_1_11

examples/usb-fpga-1.11/1.11c/ucecho/fpga/ucecho.vhd

42

580

library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out unsigned(7 downto 0); CLK : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; pb <= pb_buf; end if; end process dpUCECHO; end RTL;

gpl-3.0

freecores/usb_fpga_1_11

examples/usb-fpga-1.2/ucecho/fpga/ucecho.vhd

42

580

library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out unsigned(7 downto 0); CLK : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; pb <= pb_buf; end if; end process dpUCECHO; end RTL;

gpl-3.0

freecores/usb_fpga_1_11

examples/usb-fpga-1.15/1.15a/ucecho/fpga/ucecho.vhd

42

580

library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out unsigned(7 downto 0); CLK : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; pb <= pb_buf; end if; end process dpUCECHO; end RTL;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_strb_gen2.vhd

18

101757

------------------------------------------------------------------------------- -- axi_datamover_strb_gen2.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_strb_gen2.vhd -- -- Description: -- Second generation AXI Strobe Generator module. This design leverages -- look up table approach vs real-time calculation. This design method is -- used to reduce logic levels and improve final Fmax timing. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_strb_gen2 is generic ( C_OP_MODE : Integer range 0 to 1 := 0; -- 0 = offset/length mode -- 1 = offset/offset mode, C_STRB_WIDTH : Integer := 8; -- number of addr bits needed C_OFFSET_WIDTH : Integer := 3; -- log2(C_STRB_WIDTH) C_NUM_BYTES_WIDTH : Integer := 4 -- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0) -- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1) ); port ( -- Starting offset input ----------------------------------------------------- -- start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); -- -- Specifies the starting address offset of the strobe value -- ------------------------------------------------------------------------------ -- used in both offset/offset and offset/length modes -- Endig Offset Input -------------------------------------------------------- -- end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); -- -- Specifies the ending address offset of the strobe value -- -- used in only offset/offset mode (C_OP_MODE = 1) -- ------------------------------------------------------------------------------ -- Number of valid Bytes input (from starting offset) ------------------------ -- num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); -- -- Specifies the number of valid bytes from starting offset -- -- used in only offset/length mode (C_OP_MODE = 0) -- ------------------------------------------------------------------------------ -- Generated Strobe output --------------------------------------------------- -- strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) -- ------------------------------------------------------------------------------ ); end entity axi_datamover_strb_gen2; architecture implementation of axi_datamover_strb_gen2 is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_2 -- -- Function Description: -- returns the 2-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_2 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "11"; when others => var_start_vector := "10"; end case; Return (var_start_vector); end function get_start_2; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_2 -- -- Function Description: -- Returns the 2-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_2 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "01"; when others => var_end_vector := "11"; end case; Return (var_end_vector); end function get_end_2; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_4 -- -- Function Description: -- returns the 4-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_4 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "1111"; when 1 => var_start_vector := "1110"; when 2 => var_start_vector := "1100"; when others => var_start_vector := "1000"; end case; Return (var_start_vector); end function get_start_4; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_4 -- -- Function Description: -- Returns the 4-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_4 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "0001"; when 1 => var_end_vector := "0011"; when 2 => var_end_vector := "0111"; when others => var_end_vector := "1111"; end case; Return (var_end_vector); end function get_end_4; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_8 -- -- Function Description: -- returns the 8-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_8 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "11111111"; when 1 => var_start_vector := "11111110"; when 2 => var_start_vector := "11111100"; when 3 => var_start_vector := "11111000"; when 4 => var_start_vector := "11110000"; when 5 => var_start_vector := "11100000"; when 6 => var_start_vector := "11000000"; when others => var_start_vector := "10000000"; end case; Return (var_start_vector); end function get_start_8; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_8 -- -- Function Description: -- Returns the 8-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_8 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "00000001"; when 1 => var_end_vector := "00000011"; when 2 => var_end_vector := "00000111"; when 3 => var_end_vector := "00001111"; when 4 => var_end_vector := "00011111"; when 5 => var_end_vector := "00111111"; when 6 => var_end_vector := "01111111"; when others => var_end_vector := "11111111"; end case; Return (var_end_vector); end function get_end_8; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_16 -- -- Function Description: -- returns the 16-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_16 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "1111111111111111"; when 1 => var_start_vector := "1111111111111110"; when 2 => var_start_vector := "1111111111111100"; when 3 => var_start_vector := "1111111111111000"; when 4 => var_start_vector := "1111111111110000"; when 5 => var_start_vector := "1111111111100000"; when 6 => var_start_vector := "1111111111000000"; when 7 => var_start_vector := "1111111110000000"; when 8 => var_start_vector := "1111111100000000"; when 9 => var_start_vector := "1111111000000000"; when 10 => var_start_vector := "1111110000000000"; when 11 => var_start_vector := "1111100000000000"; when 12 => var_start_vector := "1111000000000000"; when 13 => var_start_vector := "1110000000000000"; when 14 => var_start_vector := "1100000000000000"; when others => var_start_vector := "1000000000000000"; end case; Return (var_start_vector); end function get_start_16; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_16 -- -- Function Description: -- Returns the 16-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_16 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "0000000000000001"; when 1 => var_end_vector := "0000000000000011"; when 2 => var_end_vector := "0000000000000111"; when 3 => var_end_vector := "0000000000001111"; when 4 => var_end_vector := "0000000000011111"; when 5 => var_end_vector := "0000000000111111"; when 6 => var_end_vector := "0000000001111111"; when 7 => var_end_vector := "0000000011111111"; when 8 => var_end_vector := "0000000111111111"; when 9 => var_end_vector := "0000001111111111"; when 10 => var_end_vector := "0000011111111111"; when 11 => var_end_vector := "0000111111111111"; when 12 => var_end_vector := "0001111111111111"; when 13 => var_end_vector := "0011111111111111"; when 14 => var_end_vector := "0111111111111111"; when others => var_end_vector := "1111111111111111"; end case; Return (var_end_vector); end function get_end_16; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_32 -- -- Function Description: -- returns the 32-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_32 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "11111111111111111111111111111111"; when 1 => var_start_vector := "11111111111111111111111111111110"; when 2 => var_start_vector := "11111111111111111111111111111100"; when 3 => var_start_vector := "11111111111111111111111111111000"; when 4 => var_start_vector := "11111111111111111111111111110000"; when 5 => var_start_vector := "11111111111111111111111111100000"; when 6 => var_start_vector := "11111111111111111111111111000000"; when 7 => var_start_vector := "11111111111111111111111110000000"; when 8 => var_start_vector := "11111111111111111111111100000000"; when 9 => var_start_vector := "11111111111111111111111000000000"; when 10 => var_start_vector := "11111111111111111111110000000000"; when 11 => var_start_vector := "11111111111111111111100000000000"; when 12 => var_start_vector := "11111111111111111111000000000000"; when 13 => var_start_vector := "11111111111111111110000000000000"; when 14 => var_start_vector := "11111111111111111100000000000000"; when 15 => var_start_vector := "11111111111111111000000000000000"; when 16 => var_start_vector := "11111111111111110000000000000000"; when 17 => var_start_vector := "11111111111111100000000000000000"; when 18 => var_start_vector := "11111111111111000000000000000000"; when 19 => var_start_vector := "11111111111110000000000000000000"; when 20 => var_start_vector := "11111111111100000000000000000000"; when 21 => var_start_vector := "11111111111000000000000000000000"; when 22 => var_start_vector := "11111111110000000000000000000000"; when 23 => var_start_vector := "11111111100000000000000000000000"; when 24 => var_start_vector := "11111111000000000000000000000000"; when 25 => var_start_vector := "11111110000000000000000000000000"; when 26 => var_start_vector := "11111100000000000000000000000000"; when 27 => var_start_vector := "11111000000000000000000000000000"; when 28 => var_start_vector := "11110000000000000000000000000000"; when 29 => var_start_vector := "11100000000000000000000000000000"; when 30 => var_start_vector := "11000000000000000000000000000000"; when others => var_start_vector := "10000000000000000000000000000000"; end case; Return (var_start_vector); end function get_start_32; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_32 -- -- Function Description: -- Returns the 32-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_32 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "00000000000000000000000000000001"; when 1 => var_end_vector := "00000000000000000000000000000011"; when 2 => var_end_vector := "00000000000000000000000000000111"; when 3 => var_end_vector := "00000000000000000000000000001111"; when 4 => var_end_vector := "00000000000000000000000000011111"; when 5 => var_end_vector := "00000000000000000000000000111111"; when 6 => var_end_vector := "00000000000000000000000001111111"; when 7 => var_end_vector := "00000000000000000000000011111111"; when 8 => var_end_vector := "00000000000000000000000111111111"; when 9 => var_end_vector := "00000000000000000000001111111111"; when 10 => var_end_vector := "00000000000000000000011111111111"; when 11 => var_end_vector := "00000000000000000000111111111111"; when 12 => var_end_vector := "00000000000000000001111111111111"; when 13 => var_end_vector := "00000000000000000011111111111111"; when 14 => var_end_vector := "00000000000000000111111111111111"; when 15 => var_end_vector := "00000000000000001111111111111111"; when 16 => var_end_vector := "00000000000000011111111111111111"; when 17 => var_end_vector := "00000000000000111111111111111111"; when 18 => var_end_vector := "00000000000001111111111111111111"; when 19 => var_end_vector := "00000000000011111111111111111111"; when 20 => var_end_vector := "00000000000111111111111111111111"; when 21 => var_end_vector := "00000000001111111111111111111111"; when 22 => var_end_vector := "00000000011111111111111111111111"; when 23 => var_end_vector := "00000000111111111111111111111111"; when 24 => var_end_vector := "00000001111111111111111111111111"; when 25 => var_end_vector := "00000011111111111111111111111111"; when 26 => var_end_vector := "00000111111111111111111111111111"; when 27 => var_end_vector := "00001111111111111111111111111111"; when 28 => var_end_vector := "00011111111111111111111111111111"; when 29 => var_end_vector := "00111111111111111111111111111111"; when 30 => var_end_vector := "01111111111111111111111111111111"; when others => var_end_vector := "11111111111111111111111111111111"; end case; Return (var_end_vector); end function get_end_32; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_64 -- -- Function Description: -- returns the 64-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_64 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111"; when 1 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110"; when 2 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100"; when 3 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000"; when 4 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000"; when 5 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000"; when 6 => var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000"; when 7 => var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000"; when 8 => var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000"; when 9 => var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000"; when 10 => var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000"; when 11 => var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000"; when 12 => var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000"; when 13 => var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000"; when 14 => var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000"; when 15 => var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000"; when 16 => var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000"; when 17 => var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000"; when 18 => var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000"; when 19 => var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000"; when 20 => var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000"; when 21 => var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000"; when 22 => var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000"; when 23 => var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000"; when 24 => var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000"; when 25 => var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000"; when 26 => var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000"; when 27 => var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000"; when 28 => var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000"; when 29 => var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000"; when 30 => var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000"; when 31 => var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000"; when 32 => var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000"; when 33 => var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000"; when 34 => var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000"; when 35 => var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000"; when 36 => var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000"; when 37 => var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000"; when 38 => var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000"; when 39 => var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000"; when 40 => var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000"; when 41 => var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000"; when 42 => var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000"; when 43 => var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000"; when 44 => var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000"; when 45 => var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000"; when 46 => var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000"; when 47 => var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000"; when 48 => var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000"; when 49 => var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000"; when 50 => var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000"; when 51 => var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000"; when 52 => var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000"; when 53 => var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000"; when 54 => var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000"; when 55 => var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000"; when 56 => var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000"; when 57 => var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000"; when 58 => var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000"; when 59 => var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000"; when 60 => var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000"; when 61 => var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000"; when 62 => var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000"; when others => var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000"; end case; Return (var_start_vector); end function get_start_64; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_64 -- -- Function Description: -- Returns the 64-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_64 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001"; when 1 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011"; when 2 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111"; when 3 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111"; when 4 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111"; when 5 => var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111"; when 6 => var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111"; when 7 => var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111"; when 8 => var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111"; when 9 => var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111"; when 10 => var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111"; when 11 => var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111"; when 12 => var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111"; when 13 => var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111"; when 14 => var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111"; when 15 => var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111"; when 16 => var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111"; when 17 => var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111"; when 18 => var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111"; when 19 => var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111"; when 20 => var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111"; when 21 => var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111"; when 22 => var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111"; when 23 => var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111"; when 24 => var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111"; when 25 => var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111"; when 26 => var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111"; when 27 => var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111"; when 28 => var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111"; when 29 => var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111"; when 30 => var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111"; when 31 => var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111"; when 32 => var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111"; when 33 => var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111"; when 34 => var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111"; when 35 => var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111"; when 36 => var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111"; when 37 => var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111"; when 38 => var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111"; when 39 => var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111"; when 40 => var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111"; when 41 => var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111"; when 42 => var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111"; when 43 => var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111"; when 44 => var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111"; when 45 => var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111"; when 46 => var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111"; when 47 => var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111"; when 48 => var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111"; when 49 => var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111"; when 50 => var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111"; when 51 => var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111"; when 52 => var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111"; when 53 => var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111"; when 54 => var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111"; when 55 => var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111"; when 56 => var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111"; when 57 => var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111"; when 58 => var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111"; when 59 => var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111"; when 60 => var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111"; when 61 => var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111"; when 62 => var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111"; when others => var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111"; end case; Return (var_end_vector); end function get_end_64; ------------------------------------------------------------------- -- Function -- -- Function Name: get_start_128 -- -- Function Description: -- returns the 128-bit vector filled with '1's from the start -- offset to the end of of the vector -- ------------------------------------------------------------------- function get_start_128 (start_offset : natural) return std_logic_vector is Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0'); begin case start_offset is when 0 => var_start_vector(127 downto 0) := (others => '1'); when 1 => var_start_vector(127 downto 1) := (others => '1'); var_start_vector( 0 downto 0) := (others => '0'); when 2 => var_start_vector(127 downto 2) := (others => '1'); var_start_vector( 1 downto 0) := (others => '0'); when 3 => var_start_vector(127 downto 3) := (others => '1'); var_start_vector( 2 downto 0) := (others => '0'); when 4 => var_start_vector(127 downto 4) := (others => '1'); var_start_vector( 3 downto 0) := (others => '0'); when 5 => var_start_vector(127 downto 5) := (others => '1'); var_start_vector( 4 downto 0) := (others => '0'); when 6 => var_start_vector(127 downto 6) := (others => '1'); var_start_vector( 5 downto 0) := (others => '0'); when 7 => var_start_vector(127 downto 7) := (others => '1'); var_start_vector( 6 downto 0) := (others => '0'); when 8 => var_start_vector(127 downto 8) := (others => '1'); var_start_vector( 7 downto 0) := (others => '0'); when 9 => var_start_vector(127 downto 9) := (others => '1'); var_start_vector( 8 downto 0) := (others => '0'); when 10 => var_start_vector(127 downto 10) := (others => '1'); var_start_vector( 9 downto 0) := (others => '0'); when 11 => var_start_vector(127 downto 11) := (others => '1'); var_start_vector( 10 downto 0) := (others => '0'); when 12 => var_start_vector(127 downto 12) := (others => '1'); var_start_vector( 11 downto 0) := (others => '0'); when 13 => var_start_vector(127 downto 13) := (others => '1'); var_start_vector( 12 downto 0) := (others => '0'); when 14 => var_start_vector(127 downto 14) := (others => '1'); var_start_vector( 13 downto 0) := (others => '0'); when 15 => var_start_vector(127 downto 15) := (others => '1'); var_start_vector( 14 downto 0) := (others => '0'); when 16 => var_start_vector(127 downto 16) := (others => '1'); var_start_vector( 15 downto 0) := (others => '0'); when 17 => var_start_vector(127 downto 17) := (others => '1'); var_start_vector( 16 downto 0) := (others => '0'); when 18 => var_start_vector(127 downto 18) := (others => '1'); var_start_vector( 17 downto 0) := (others => '0'); when 19 => var_start_vector(127 downto 19) := (others => '1'); var_start_vector( 18 downto 0) := (others => '0'); when 20 => var_start_vector(127 downto 20) := (others => '1'); var_start_vector( 19 downto 0) := (others => '0'); when 21 => var_start_vector(127 downto 21) := (others => '1'); var_start_vector( 20 downto 0) := (others => '0'); when 22 => var_start_vector(127 downto 22) := (others => '1'); var_start_vector( 21 downto 0) := (others => '0'); when 23 => var_start_vector(127 downto 23) := (others => '1'); var_start_vector( 22 downto 0) := (others => '0'); when 24 => var_start_vector(127 downto 24) := (others => '1'); var_start_vector( 23 downto 0) := (others => '0'); when 25 => var_start_vector(127 downto 25) := (others => '1'); var_start_vector( 24 downto 0) := (others => '0'); when 26 => var_start_vector(127 downto 26) := (others => '1'); var_start_vector( 25 downto 0) := (others => '0'); when 27 => var_start_vector(127 downto 27) := (others => '1'); var_start_vector( 26 downto 0) := (others => '0'); when 28 => var_start_vector(127 downto 28) := (others => '1'); var_start_vector( 27 downto 0) := (others => '0'); when 29 => var_start_vector(127 downto 29) := (others => '1'); var_start_vector( 28 downto 0) := (others => '0'); when 30 => var_start_vector(127 downto 30) := (others => '1'); var_start_vector( 29 downto 0) := (others => '0'); when 31 => var_start_vector(127 downto 31) := (others => '1'); var_start_vector( 30 downto 0) := (others => '0'); when 32 => var_start_vector(127 downto 32) := (others => '1'); var_start_vector( 31 downto 0) := (others => '0'); when 33 => var_start_vector(127 downto 33) := (others => '1'); var_start_vector( 32 downto 0) := (others => '0'); when 34 => var_start_vector(127 downto 34) := (others => '1'); var_start_vector( 33 downto 0) := (others => '0'); when 35 => var_start_vector(127 downto 35) := (others => '1'); var_start_vector( 34 downto 0) := (others => '0'); when 36 => var_start_vector(127 downto 36) := (others => '1'); var_start_vector( 35 downto 0) := (others => '0'); when 37 => var_start_vector(127 downto 37) := (others => '1'); var_start_vector( 36 downto 0) := (others => '0'); when 38 => var_start_vector(127 downto 38) := (others => '1'); var_start_vector( 37 downto 0) := (others => '0'); when 39 => var_start_vector(127 downto 39) := (others => '1'); var_start_vector( 38 downto 0) := (others => '0'); when 40 => var_start_vector(127 downto 40) := (others => '1'); var_start_vector( 39 downto 0) := (others => '0'); when 41 => var_start_vector(127 downto 41) := (others => '1'); var_start_vector( 40 downto 0) := (others => '0'); when 42 => var_start_vector(127 downto 42) := (others => '1'); var_start_vector( 41 downto 0) := (others => '0'); when 43 => var_start_vector(127 downto 43) := (others => '1'); var_start_vector( 42 downto 0) := (others => '0'); when 44 => var_start_vector(127 downto 44) := (others => '1'); var_start_vector( 43 downto 0) := (others => '0'); when 45 => var_start_vector(127 downto 45) := (others => '1'); var_start_vector( 44 downto 0) := (others => '0'); when 46 => var_start_vector(127 downto 46) := (others => '1'); var_start_vector( 45 downto 0) := (others => '0'); when 47 => var_start_vector(127 downto 47) := (others => '1'); var_start_vector( 46 downto 0) := (others => '0'); when 48 => var_start_vector(127 downto 48) := (others => '1'); var_start_vector( 47 downto 0) := (others => '0'); when 49 => var_start_vector(127 downto 49) := (others => '1'); var_start_vector( 48 downto 0) := (others => '0'); when 50 => var_start_vector(127 downto 50) := (others => '1'); var_start_vector( 49 downto 0) := (others => '0'); when 51 => var_start_vector(127 downto 51) := (others => '1'); var_start_vector( 50 downto 0) := (others => '0'); when 52 => var_start_vector(127 downto 52) := (others => '1'); var_start_vector( 51 downto 0) := (others => '0'); when 53 => var_start_vector(127 downto 53) := (others => '1'); var_start_vector( 52 downto 0) := (others => '0'); when 54 => var_start_vector(127 downto 54) := (others => '1'); var_start_vector( 53 downto 0) := (others => '0'); when 55 => var_start_vector(127 downto 55) := (others => '1'); var_start_vector( 54 downto 0) := (others => '0'); when 56 => var_start_vector(127 downto 56) := (others => '1'); var_start_vector( 55 downto 0) := (others => '0'); when 57 => var_start_vector(127 downto 57) := (others => '1'); var_start_vector( 56 downto 0) := (others => '0'); when 58 => var_start_vector(127 downto 58) := (others => '1'); var_start_vector( 57 downto 0) := (others => '0'); when 59 => var_start_vector(127 downto 59) := (others => '1'); var_start_vector( 58 downto 0) := (others => '0'); when 60 => var_start_vector(127 downto 60) := (others => '1'); var_start_vector( 59 downto 0) := (others => '0'); when 61 => var_start_vector(127 downto 61) := (others => '1'); var_start_vector( 60 downto 0) := (others => '0'); when 62 => var_start_vector(127 downto 62) := (others => '1'); var_start_vector( 61 downto 0) := (others => '0'); when 63 => var_start_vector(127 downto 63) := (others => '1'); var_start_vector( 62 downto 0) := (others => '0'); when 64 => var_start_vector(127 downto 64) := (others => '1'); var_start_vector( 63 downto 0) := (others => '0'); when 65 => var_start_vector(127 downto 65) := (others => '1'); var_start_vector( 64 downto 0) := (others => '0'); when 66 => var_start_vector(127 downto 66) := (others => '1'); var_start_vector( 65 downto 0) := (others => '0'); when 67 => var_start_vector(127 downto 67) := (others => '1'); var_start_vector( 66 downto 0) := (others => '0'); when 68 => var_start_vector(127 downto 68) := (others => '1'); var_start_vector( 67 downto 0) := (others => '0'); when 69 => var_start_vector(127 downto 69) := (others => '1'); var_start_vector( 68 downto 0) := (others => '0'); when 70 => var_start_vector(127 downto 70) := (others => '1'); var_start_vector( 69 downto 0) := (others => '0'); when 71 => var_start_vector(127 downto 71) := (others => '1'); var_start_vector( 70 downto 0) := (others => '0'); when 72 => var_start_vector(127 downto 72) := (others => '1'); var_start_vector( 71 downto 0) := (others => '0'); when 73 => var_start_vector(127 downto 73) := (others => '1'); var_start_vector( 72 downto 0) := (others => '0'); when 74 => var_start_vector(127 downto 74) := (others => '1'); var_start_vector( 73 downto 0) := (others => '0'); when 75 => var_start_vector(127 downto 75) := (others => '1'); var_start_vector( 74 downto 0) := (others => '0'); when 76 => var_start_vector(127 downto 76) := (others => '1'); var_start_vector( 75 downto 0) := (others => '0'); when 77 => var_start_vector(127 downto 77) := (others => '1'); var_start_vector( 76 downto 0) := (others => '0'); when 78 => var_start_vector(127 downto 78) := (others => '1'); var_start_vector( 77 downto 0) := (others => '0'); when 79 => var_start_vector(127 downto 79) := (others => '1'); var_start_vector( 78 downto 0) := (others => '0'); when 80 => var_start_vector(127 downto 80) := (others => '1'); var_start_vector( 79 downto 0) := (others => '0'); when 81 => var_start_vector(127 downto 81) := (others => '1'); var_start_vector( 80 downto 0) := (others => '0'); when 82 => var_start_vector(127 downto 82) := (others => '1'); var_start_vector( 81 downto 0) := (others => '0'); when 83 => var_start_vector(127 downto 83) := (others => '1'); var_start_vector( 82 downto 0) := (others => '0'); when 84 => var_start_vector(127 downto 84) := (others => '1'); var_start_vector( 83 downto 0) := (others => '0'); when 85 => var_start_vector(127 downto 85) := (others => '1'); var_start_vector( 84 downto 0) := (others => '0'); when 86 => var_start_vector(127 downto 86) := (others => '1'); var_start_vector( 85 downto 0) := (others => '0'); when 87 => var_start_vector(127 downto 87) := (others => '1'); var_start_vector( 86 downto 0) := (others => '0'); when 88 => var_start_vector(127 downto 88) := (others => '1'); var_start_vector( 87 downto 0) := (others => '0'); when 89 => var_start_vector(127 downto 89) := (others => '1'); var_start_vector( 88 downto 0) := (others => '0'); when 90 => var_start_vector(127 downto 90) := (others => '1'); var_start_vector( 89 downto 0) := (others => '0'); when 91 => var_start_vector(127 downto 91) := (others => '1'); var_start_vector( 90 downto 0) := (others => '0'); when 92 => var_start_vector(127 downto 92) := (others => '1'); var_start_vector( 91 downto 0) := (others => '0'); when 93 => var_start_vector(127 downto 93) := (others => '1'); var_start_vector( 92 downto 0) := (others => '0'); when 94 => var_start_vector(127 downto 94) := (others => '1'); var_start_vector( 93 downto 0) := (others => '0'); when 95 => var_start_vector(127 downto 95) := (others => '1'); var_start_vector( 94 downto 0) := (others => '0'); when 96 => var_start_vector(127 downto 96) := (others => '1'); var_start_vector( 95 downto 0) := (others => '0'); when 97 => var_start_vector(127 downto 97) := (others => '1'); var_start_vector( 96 downto 0) := (others => '0'); when 98 => var_start_vector(127 downto 98) := (others => '1'); var_start_vector( 97 downto 0) := (others => '0'); when 99 => var_start_vector(127 downto 99) := (others => '1'); var_start_vector( 98 downto 0) := (others => '0'); when 100 => var_start_vector(127 downto 100) := (others => '1'); var_start_vector( 99 downto 0) := (others => '0'); when 101 => var_start_vector(127 downto 101) := (others => '1'); var_start_vector(100 downto 0) := (others => '0'); when 102 => var_start_vector(127 downto 102) := (others => '1'); var_start_vector(101 downto 0) := (others => '0'); when 103 => var_start_vector(127 downto 103) := (others => '1'); var_start_vector(102 downto 0) := (others => '0'); when 104 => var_start_vector(127 downto 104) := (others => '1'); var_start_vector(103 downto 0) := (others => '0'); when 105 => var_start_vector(127 downto 105) := (others => '1'); var_start_vector(104 downto 0) := (others => '0'); when 106 => var_start_vector(127 downto 106) := (others => '1'); var_start_vector(105 downto 0) := (others => '0'); when 107 => var_start_vector(127 downto 107) := (others => '1'); var_start_vector(106 downto 0) := (others => '0'); when 108 => var_start_vector(127 downto 108) := (others => '1'); var_start_vector(107 downto 0) := (others => '0'); when 109 => var_start_vector(127 downto 109) := (others => '1'); var_start_vector(108 downto 0) := (others => '0'); when 110 => var_start_vector(127 downto 110) := (others => '1'); var_start_vector(109 downto 0) := (others => '0'); when 111 => var_start_vector(127 downto 111) := (others => '1'); var_start_vector(110 downto 0) := (others => '0'); when 112 => var_start_vector(127 downto 112) := (others => '1'); var_start_vector(111 downto 0) := (others => '0'); when 113 => var_start_vector(127 downto 113) := (others => '1'); var_start_vector(112 downto 0) := (others => '0'); when 114 => var_start_vector(127 downto 114) := (others => '1'); var_start_vector(113 downto 0) := (others => '0'); when 115 => var_start_vector(127 downto 115) := (others => '1'); var_start_vector(114 downto 0) := (others => '0'); when 116 => var_start_vector(127 downto 116) := (others => '1'); var_start_vector(115 downto 0) := (others => '0'); when 117 => var_start_vector(127 downto 117) := (others => '1'); var_start_vector(116 downto 0) := (others => '0'); when 118 => var_start_vector(127 downto 118) := (others => '1'); var_start_vector(117 downto 0) := (others => '0'); when 119 => var_start_vector(127 downto 119) := (others => '1'); var_start_vector(118 downto 0) := (others => '0'); when 120 => var_start_vector(127 downto 120) := (others => '1'); var_start_vector(119 downto 0) := (others => '0'); when 121 => var_start_vector(127 downto 121) := (others => '1'); var_start_vector(120 downto 0) := (others => '0'); when 122 => var_start_vector(127 downto 122) := (others => '1'); var_start_vector(121 downto 0) := (others => '0'); when 123 => var_start_vector(127 downto 123) := (others => '1'); var_start_vector(122 downto 0) := (others => '0'); when 124 => var_start_vector(127 downto 124) := (others => '1'); var_start_vector(123 downto 0) := (others => '0'); when 125 => var_start_vector(127 downto 125) := (others => '1'); var_start_vector(124 downto 0) := (others => '0'); when 126 => var_start_vector(127 downto 126) := (others => '1'); var_start_vector(125 downto 0) := (others => '0'); when others => var_start_vector(127 downto 127) := (others => '1'); var_start_vector(126 downto 0) := (others => '0'); end case; Return (var_start_vector); end function get_start_128; ------------------------------------------------------------------- -- Function -- -- Function Name: get_end_128 -- -- Function Description: -- Returns the 128-bit vector filled with '1's from the lsbit -- of the vector to the end offset. -- ------------------------------------------------------------------- function get_end_128 (end_offset : natural) return std_logic_vector is Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0'); begin case end_offset is when 0 => var_end_vector(127 downto 1) := (others => '0'); var_end_vector( 0 downto 0) := (others => '1'); when 1 => var_end_vector(127 downto 2) := (others => '0'); var_end_vector( 1 downto 0) := (others => '1'); when 2 => var_end_vector(127 downto 3) := (others => '0'); var_end_vector( 2 downto 0) := (others => '1'); when 3 => var_end_vector(127 downto 4) := (others => '0'); var_end_vector( 3 downto 0) := (others => '1'); when 4 => var_end_vector(127 downto 5) := (others => '0'); var_end_vector( 4 downto 0) := (others => '1'); when 5 => var_end_vector(127 downto 6) := (others => '0'); var_end_vector( 5 downto 0) := (others => '1'); when 6 => var_end_vector(127 downto 7) := (others => '0'); var_end_vector( 6 downto 0) := (others => '1'); when 7 => var_end_vector(127 downto 8) := (others => '0'); var_end_vector( 7 downto 0) := (others => '1'); when 8 => var_end_vector(127 downto 9) := (others => '0'); var_end_vector( 8 downto 0) := (others => '1'); when 9 => var_end_vector(127 downto 10) := (others => '0'); var_end_vector( 9 downto 0) := (others => '1'); when 10 => var_end_vector(127 downto 11) := (others => '0'); var_end_vector( 10 downto 0) := (others => '1'); when 11 => var_end_vector(127 downto 12) := (others => '0'); var_end_vector( 11 downto 0) := (others => '1'); when 12 => var_end_vector(127 downto 13) := (others => '0'); var_end_vector( 12 downto 0) := (others => '1'); when 13 => var_end_vector(127 downto 14) := (others => '0'); var_end_vector( 13 downto 0) := (others => '1'); when 14 => var_end_vector(127 downto 15) := (others => '0'); var_end_vector( 14 downto 0) := (others => '1'); when 15 => var_end_vector(127 downto 16) := (others => '0'); var_end_vector( 15 downto 0) := (others => '1'); when 16 => var_end_vector(127 downto 17) := (others => '0'); var_end_vector( 16 downto 0) := (others => '1'); when 17 => var_end_vector(127 downto 18) := (others => '0'); var_end_vector( 17 downto 0) := (others => '1'); when 18 => var_end_vector(127 downto 19) := (others => '0'); var_end_vector( 18 downto 0) := (others => '1'); when 19 => var_end_vector(127 downto 20) := (others => '0'); var_end_vector( 19 downto 0) := (others => '1'); when 20 => var_end_vector(127 downto 21) := (others => '0'); var_end_vector( 20 downto 0) := (others => '1'); when 21 => var_end_vector(127 downto 22) := (others => '0'); var_end_vector( 21 downto 0) := (others => '1'); when 22 => var_end_vector(127 downto 23) := (others => '0'); var_end_vector( 22 downto 0) := (others => '1'); when 23 => var_end_vector(127 downto 24) := (others => '0'); var_end_vector( 23 downto 0) := (others => '1'); when 24 => var_end_vector(127 downto 25) := (others => '0'); var_end_vector( 24 downto 0) := (others => '1'); when 25 => var_end_vector(127 downto 26) := (others => '0'); var_end_vector( 25 downto 0) := (others => '1'); when 26 => var_end_vector(127 downto 27) := (others => '0'); var_end_vector( 26 downto 0) := (others => '1'); when 27 => var_end_vector(127 downto 28) := (others => '0'); var_end_vector( 27 downto 0) := (others => '1'); when 28 => var_end_vector(127 downto 29) := (others => '0'); var_end_vector( 28 downto 0) := (others => '1'); when 29 => var_end_vector(127 downto 30) := (others => '0'); var_end_vector( 29 downto 0) := (others => '1'); when 30 => var_end_vector(127 downto 31) := (others => '0'); var_end_vector( 30 downto 0) := (others => '1'); when 31 => var_end_vector(127 downto 32) := (others => '0'); var_end_vector( 31 downto 0) := (others => '1'); when 32 => var_end_vector(127 downto 33) := (others => '0'); var_end_vector( 32 downto 0) := (others => '1'); when 33 => var_end_vector(127 downto 34) := (others => '0'); var_end_vector( 33 downto 0) := (others => '1'); when 34 => var_end_vector(127 downto 35) := (others => '0'); var_end_vector( 34 downto 0) := (others => '1'); when 35 => var_end_vector(127 downto 36) := (others => '0'); var_end_vector( 35 downto 0) := (others => '1'); when 36 => var_end_vector(127 downto 37) := (others => '0'); var_end_vector( 36 downto 0) := (others => '1'); when 37 => var_end_vector(127 downto 38) := (others => '0'); var_end_vector( 37 downto 0) := (others => '1'); when 38 => var_end_vector(127 downto 39) := (others => '0'); var_end_vector( 38 downto 0) := (others => '1'); when 39 => var_end_vector(127 downto 40) := (others => '0'); var_end_vector( 39 downto 0) := (others => '1'); when 40 => var_end_vector(127 downto 41) := (others => '0'); var_end_vector( 40 downto 0) := (others => '1'); when 41 => var_end_vector(127 downto 42) := (others => '0'); var_end_vector( 41 downto 0) := (others => '1'); when 42 => var_end_vector(127 downto 43) := (others => '0'); var_end_vector( 42 downto 0) := (others => '1'); when 43 => var_end_vector(127 downto 44) := (others => '0'); var_end_vector( 43 downto 0) := (others => '1'); when 44 => var_end_vector(127 downto 45) := (others => '0'); var_end_vector( 44 downto 0) := (others => '1'); when 45 => var_end_vector(127 downto 46) := (others => '0'); var_end_vector( 45 downto 0) := (others => '1'); when 46 => var_end_vector(127 downto 47) := (others => '0'); var_end_vector( 46 downto 0) := (others => '1'); when 47 => var_end_vector(127 downto 48) := (others => '0'); var_end_vector( 47 downto 0) := (others => '1'); when 48 => var_end_vector(127 downto 49) := (others => '0'); var_end_vector( 48 downto 0) := (others => '1'); when 49 => var_end_vector(127 downto 50) := (others => '0'); var_end_vector( 49 downto 0) := (others => '1'); when 50 => var_end_vector(127 downto 51) := (others => '0'); var_end_vector( 50 downto 0) := (others => '1'); when 51 => var_end_vector(127 downto 52) := (others => '0'); var_end_vector( 51 downto 0) := (others => '1'); when 52 => var_end_vector(127 downto 53) := (others => '0'); var_end_vector( 52 downto 0) := (others => '1'); when 53 => var_end_vector(127 downto 54) := (others => '0'); var_end_vector( 53 downto 0) := (others => '1'); when 54 => var_end_vector(127 downto 55) := (others => '0'); var_end_vector( 54 downto 0) := (others => '1'); when 55 => var_end_vector(127 downto 56) := (others => '0'); var_end_vector( 55 downto 0) := (others => '1'); when 56 => var_end_vector(127 downto 57) := (others => '0'); var_end_vector( 56 downto 0) := (others => '1'); when 57 => var_end_vector(127 downto 58) := (others => '0'); var_end_vector( 57 downto 0) := (others => '1'); when 58 => var_end_vector(127 downto 59) := (others => '0'); var_end_vector( 58 downto 0) := (others => '1'); when 59 => var_end_vector(127 downto 60) := (others => '0'); var_end_vector( 59 downto 0) := (others => '1'); when 60 => var_end_vector(127 downto 61) := (others => '0'); var_end_vector( 60 downto 0) := (others => '1'); when 61 => var_end_vector(127 downto 62) := (others => '0'); var_end_vector( 61 downto 0) := (others => '1'); when 62 => var_end_vector(127 downto 63) := (others => '0'); var_end_vector( 62 downto 0) := (others => '1'); when 63 => var_end_vector(127 downto 64) := (others => '0'); var_end_vector( 63 downto 0) := (others => '1'); when 64 => var_end_vector(127 downto 65) := (others => '0'); var_end_vector( 64 downto 0) := (others => '1'); when 65 => var_end_vector(127 downto 66) := (others => '0'); var_end_vector( 65 downto 0) := (others => '1'); when 66 => var_end_vector(127 downto 67) := (others => '0'); var_end_vector( 66 downto 0) := (others => '1'); when 67 => var_end_vector(127 downto 68) := (others => '0'); var_end_vector( 67 downto 0) := (others => '1'); when 68 => var_end_vector(127 downto 69) := (others => '0'); var_end_vector( 68 downto 0) := (others => '1'); when 69 => var_end_vector(127 downto 70) := (others => '0'); var_end_vector( 69 downto 0) := (others => '1'); when 70 => var_end_vector(127 downto 71) := (others => '0'); var_end_vector( 70 downto 0) := (others => '1'); when 71 => var_end_vector(127 downto 72) := (others => '0'); var_end_vector( 71 downto 0) := (others => '1'); when 72 => var_end_vector(127 downto 73) := (others => '0'); var_end_vector( 72 downto 0) := (others => '1'); when 73 => var_end_vector(127 downto 74) := (others => '0'); var_end_vector( 73 downto 0) := (others => '1'); when 74 => var_end_vector(127 downto 75) := (others => '0'); var_end_vector( 74 downto 0) := (others => '1'); when 75 => var_end_vector(127 downto 76) := (others => '0'); var_end_vector( 75 downto 0) := (others => '1'); when 76 => var_end_vector(127 downto 77) := (others => '0'); var_end_vector( 76 downto 0) := (others => '1'); when 77 => var_end_vector(127 downto 78) := (others => '0'); var_end_vector( 77 downto 0) := (others => '1'); when 78 => var_end_vector(127 downto 79) := (others => '0'); var_end_vector( 78 downto 0) := (others => '1'); when 79 => var_end_vector(127 downto 80) := (others => '0'); var_end_vector( 79 downto 0) := (others => '1'); when 80 => var_end_vector(127 downto 81) := (others => '0'); var_end_vector( 80 downto 0) := (others => '1'); when 81 => var_end_vector(127 downto 82) := (others => '0'); var_end_vector( 81 downto 0) := (others => '1'); when 82 => var_end_vector(127 downto 83) := (others => '0'); var_end_vector( 82 downto 0) := (others => '1'); when 83 => var_end_vector(127 downto 84) := (others => '0'); var_end_vector( 83 downto 0) := (others => '1'); when 84 => var_end_vector(127 downto 85) := (others => '0'); var_end_vector( 84 downto 0) := (others => '1'); when 85 => var_end_vector(127 downto 86) := (others => '0'); var_end_vector( 85 downto 0) := (others => '1'); when 86 => var_end_vector(127 downto 87) := (others => '0'); var_end_vector( 86 downto 0) := (others => '1'); when 87 => var_end_vector(127 downto 88) := (others => '0'); var_end_vector( 87 downto 0) := (others => '1'); when 88 => var_end_vector(127 downto 89) := (others => '0'); var_end_vector( 88 downto 0) := (others => '1'); when 89 => var_end_vector(127 downto 90) := (others => '0'); var_end_vector( 89 downto 0) := (others => '1'); when 90 => var_end_vector(127 downto 91) := (others => '0'); var_end_vector( 90 downto 0) := (others => '1'); when 91 => var_end_vector(127 downto 92) := (others => '0'); var_end_vector( 91 downto 0) := (others => '1'); when 92 => var_end_vector(127 downto 93) := (others => '0'); var_end_vector( 92 downto 0) := (others => '1'); when 93 => var_end_vector(127 downto 94) := (others => '0'); var_end_vector( 93 downto 0) := (others => '1'); when 94 => var_end_vector(127 downto 95) := (others => '0'); var_end_vector( 94 downto 0) := (others => '1'); when 95 => var_end_vector(127 downto 96) := (others => '0'); var_end_vector( 95 downto 0) := (others => '1'); when 96 => var_end_vector(127 downto 97) := (others => '0'); var_end_vector( 96 downto 0) := (others => '1'); when 97 => var_end_vector(127 downto 98) := (others => '0'); var_end_vector( 97 downto 0) := (others => '1'); when 98 => var_end_vector(127 downto 99) := (others => '0'); var_end_vector( 98 downto 0) := (others => '1'); when 99 => var_end_vector(127 downto 100) := (others => '0'); var_end_vector( 99 downto 0) := (others => '1'); when 100 => var_end_vector(127 downto 101) := (others => '0'); var_end_vector(100 downto 0) := (others => '1'); when 101 => var_end_vector(127 downto 102) := (others => '0'); var_end_vector(101 downto 0) := (others => '1'); when 102 => var_end_vector(127 downto 103) := (others => '0'); var_end_vector(102 downto 0) := (others => '1'); when 103 => var_end_vector(127 downto 104) := (others => '0'); var_end_vector(103 downto 0) := (others => '1'); when 104 => var_end_vector(127 downto 105) := (others => '0'); var_end_vector(104 downto 0) := (others => '1'); when 105 => var_end_vector(127 downto 106) := (others => '0'); var_end_vector(105 downto 0) := (others => '1'); when 106 => var_end_vector(127 downto 107) := (others => '0'); var_end_vector(106 downto 0) := (others => '1'); when 107 => var_end_vector(127 downto 108) := (others => '0'); var_end_vector(107 downto 0) := (others => '1'); when 108 => var_end_vector(127 downto 109) := (others => '0'); var_end_vector(108 downto 0) := (others => '1'); when 109 => var_end_vector(127 downto 110) := (others => '0'); var_end_vector(109 downto 0) := (others => '1'); when 110 => var_end_vector(127 downto 111) := (others => '0'); var_end_vector(110 downto 0) := (others => '1'); when 111 => var_end_vector(127 downto 112) := (others => '0'); var_end_vector(111 downto 0) := (others => '1'); when 112 => var_end_vector(127 downto 113) := (others => '0'); var_end_vector(112 downto 0) := (others => '1'); when 113 => var_end_vector(127 downto 114) := (others => '0'); var_end_vector(113 downto 0) := (others => '1'); when 114 => var_end_vector(127 downto 115) := (others => '0'); var_end_vector(114 downto 0) := (others => '1'); when 115 => var_end_vector(127 downto 116) := (others => '0'); var_end_vector(115 downto 0) := (others => '1'); when 116 => var_end_vector(127 downto 117) := (others => '0'); var_end_vector(116 downto 0) := (others => '1'); when 117 => var_end_vector(127 downto 118) := (others => '0'); var_end_vector(117 downto 0) := (others => '1'); when 118 => var_end_vector(127 downto 119) := (others => '0'); var_end_vector(118 downto 0) := (others => '1'); when 119 => var_end_vector(127 downto 120) := (others => '0'); var_end_vector(119 downto 0) := (others => '1'); when 120 => var_end_vector(127 downto 121) := (others => '0'); var_end_vector(120 downto 0) := (others => '1'); when 121 => var_end_vector(127 downto 122) := (others => '0'); var_end_vector(121 downto 0) := (others => '1'); when 122 => var_end_vector(127 downto 123) := (others => '0'); var_end_vector(122 downto 0) := (others => '1'); when 123 => var_end_vector(127 downto 124) := (others => '0'); var_end_vector(123 downto 0) := (others => '1'); when 124 => var_end_vector(127 downto 125) := (others => '0'); var_end_vector(124 downto 0) := (others => '1'); when 125 => var_end_vector(127 downto 126) := (others => '0'); var_end_vector(125 downto 0) := (others => '1'); when 126 => var_end_vector(127 downto 127) := (others => '0'); var_end_vector(126 downto 0) := (others => '1'); when others => var_end_vector(127 downto 0) := (others => '1'); end case; Return (var_end_vector); end function get_end_128; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_clip_value -- -- Function Description: -- Returns a value that cannot exceed a clip value. -- ------------------------------------------------------------------- function funct_clip_value (input_value : natural; max_value : natural) return natural is Variable temp_value : Natural := 0; begin If (input_value <= max_value) Then temp_value := input_value; Else temp_value := max_value; End if; Return (temp_value); end function funct_clip_value; -- Constants Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom -- if op Mode = 1 -- Signals signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); begin --(architecture implementation) -- Assign the output strobe value strb_out <= sig_ouput_stbs ; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OFF_OFF_CASE -- -- If Generate Description: -- Calculates the internal start and end offsets for the -- case when start and end offsets are being provided. -- -- ------------------------------------------------------------ GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate begin sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH); sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH); end generate GEN_OFF_OFF_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OFF_LEN_CASE -- -- If Generate Description: -- Calculates the internal start and end offsets for the -- case when start offset and length are being provided. -- ------------------------------------------------------------ GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate -- Local Constants Declarations Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH; Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH); Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH); Constant MAX_VALUE : natural := C_STRB_WIDTH-1; -- local signals signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0'); signal lsig_end_addr_int : integer := 0; signal lsig_strt_addr_int : integer := 0; begin lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH); lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH); lsig_length_adjust_us <= L_ZERO When (lsig_num_valid_bytes_us = L_ZERO) Else L_ONE; lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us; lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us; lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us); lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us); sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH); sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ; end generate GEN_OFF_LEN_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_1BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 1-bit strobe width case. -- -- ------------------------------------------------------------ GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate begin sig_ouput_stbs <= (others => '1') ; end generate GEN_1BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_2BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 2-bit strobe width case. -- -- ------------------------------------------------------------ GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 1; Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_2(lsig_start_offset); lsig_end_vect <= get_end_2(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_2BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_4BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 4-bit strobe width case. -- -- ------------------------------------------------------------ GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 3; Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_4(lsig_start_offset); lsig_end_vect <= get_end_4(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_4BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_8BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 8-bit strobe width case. -- -- ------------------------------------------------------------ GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 7; Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_8(lsig_start_offset); lsig_end_vect <= get_end_8(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_8BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_16BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 16-bit strobe width case. -- -- ------------------------------------------------------------ GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 15; Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_16(lsig_start_offset); lsig_end_vect <= get_end_16(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_16BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_32BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 32-bit strobe width case. -- -- ------------------------------------------------------------ GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 31; Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_32(lsig_start_offset); lsig_end_vect <= get_end_32(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_32BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_64BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 64-bit strobe width case. -- -- ------------------------------------------------------------ GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 63; Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_64(lsig_start_offset); lsig_end_vect <= get_end_64(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_64BIT_CASE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_128BIT_CASE -- -- If Generate Description: -- Generates the strobes for the 64-bit strobe width case. -- -- ------------------------------------------------------------ GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate -- local signals Signal lsig_start_offset : Natural := 0; Signal lsig_end_offset : Natural := 127; Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0'); Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0'); Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0'); begin lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ; lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ; lsig_start_vect <= get_start_128(lsig_start_offset); lsig_end_vect <= get_end_128(lsig_end_offset) ; lsig_cmplt_vect <= lsig_start_vect and lsig_end_vect; sig_ouput_stbs <= lsig_cmplt_vect ; end generate GEN_128BIT_CASE; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/2a047f91/hdl/src/vhdl/axi_dma_mm2s_sm.vhd

2

28379

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_mm2s_sm.vhd -- Description: This entity contains the MM2S DMA Controller State Machine -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1; use axi_dma_v7_1.axi_dma_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.clog2; ------------------------------------------------------------------------------- entity axi_dma_mm2s_sm is generic ( C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for MM2S Read Port C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Width of Buffer Length, Transferred Bytes, and BTT fields C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1; -- Depth of DataMover command FIFO C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control and Status -- mm2s_run_stop : in std_logic ; -- mm2s_keyhole : in std_logic ; mm2s_ftch_idle : in std_logic ; -- mm2s_stop : in std_logic ; -- mm2s_cmnd_idle : out std_logic ; -- mm2s_sts_idle : out std_logic ; -- mm2s_desc_flush : out std_logic ; -- -- -- MM2S Descriptor Fetch Request (from mm2s_sm) -- desc_available : in std_logic ; -- desc_fetch_req : out std_logic ; -- desc_fetch_done : in std_logic ; -- desc_update_done : in std_logic ; -- updt_pending : in std_logic ; packet_in_progress : in std_logic ; -- -- -- DataMover Command -- mm2s_cmnd_wr : out std_logic ; -- mm2s_cmnd_data : out std_logic_vector -- ((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0); -- mm2s_cmnd_pending : in std_logic ; -- -- -- Descriptor Fields -- mm2s_cache_info : in std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- mm2s_desc_baddress : in std_logic_vector -- (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- mm2s_desc_blength : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- mm2s_desc_blength_v : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- mm2s_desc_blength_s : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) ; -- mm2s_desc_eof : in std_logic ; -- mm2s_desc_sof : in std_logic -- ); end axi_dma_mm2s_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_mm2s_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0'); -- DataMover Command Destination Stream Offset constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant MM2S_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH) := (others => '0'); -- Queued commands counter width constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1); -- Queued commands zero count constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- type SG_MM2S_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, -- EXECUTE_XFER, WAIT_STATUS ); signal mm2s_cs : SG_MM2S_STATE_TYPE; signal mm2s_ns : SG_MM2S_STATE_TYPE; -- State Machine Signals signal desc_fetch_req_cmb : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal mm2s_cmnd_wr_i : std_logic := '0'; attribute mark_debug of mm2s_cmnd_wr_i : signal is "true"; signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0'); signal count_incr : std_logic := '0'; signal count_decr : std_logic := '0'; signal mm2s_desc_flush_i : std_logic := '0'; signal queue_more : std_logic := '0'; signal burst_type : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin mm2s_cmnd_wr <= mm2s_cmnd_wr_i; mm2s_desc_flush <= mm2s_desc_flush_i; -- Flush any fetch descriptors if stopped due to errors or soft reset -- or if not in middle of packet and run/stop clears mm2s_desc_flush_i <= '1' when (mm2s_stop = '1') or (packet_in_progress = '0' and mm2s_run_stop = '0') else '0'; burst_type <= '1' and (not mm2s_keyhole); -- A 0 on mm2s_kyhole means increment type burst -- 1 means fixed burst ------------------------------------------------------------------------------- -- MM2S Transfer State Machine ------------------------------------------------------------------------------- MM2S_MACHINE : process(mm2s_cs, mm2s_run_stop, packet_in_progress, desc_available, updt_pending, -- desc_fetch_done, desc_update_done, mm2s_cmnd_pending, mm2s_stop, mm2s_desc_flush_i -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; write_cmnd_cmb <= '0'; mm2s_cmnd_idle <= '0'; mm2s_ns <= mm2s_cs; case mm2s_cs is ------------------------------------------------------------------- when IDLE => -- Running or Stopped but in middle of xfer and Descriptor -- data available, No errors logged, and Room to queue more -- commands, then fetch descriptor -- if (updt_pending = '1') then -- mm2s_ns <= IDLE; if( (mm2s_run_stop = '1' or packet_in_progress = '1') -- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then if (C_SG_INCLUDE_DESC_QUEUE = 0) then -- coverage off mm2s_ns <= WAIT_STATUS; write_cmnd_cmb <= '1'; -- coverage on else mm2s_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; end if; else mm2s_cmnd_idle <= '1'; write_cmnd_cmb <= '0'; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- error detected or run/stop cleared if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then mm2s_ns <= IDLE; -- descriptor fetch complete -- elsif(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; -- mm2s_ns <= EXECUTE_XFER; elsif(mm2s_cmnd_pending = '0')then desc_fetch_req_cmb <= '0'; if (updt_pending = '0') then if(C_SG_INCLUDE_DESC_QUEUE = 1)then mm2s_ns <= IDLE; -- coverage off write_cmnd_cmb <= '1'; -- coverage on else mm2s_ns <= WAIT_STATUS; end if; end if; else mm2s_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '0'; end if; ------------------------------------------------------------------- -- when EXECUTE_XFER => -- -- error detected -- if(mm2s_stop = '1')then -- mm2s_ns <= IDLE; -- -- Write another command if there is not one already pending -- elsif(mm2s_cmnd_pending = '0')then -- if (updt_pending = '0') then -- write_cmnd_cmb <= '1'; -- end if; -- if(C_SG_INCLUDE_DESC_QUEUE = 1)then -- mm2s_ns <= IDLE; -- else -- mm2s_ns <= WAIT_STATUS; -- end if; -- else -- mm2s_ns <= EXECUTE_XFER; -- end if; -- ------------------------------------------------------------------- -- coverage off when WAIT_STATUS => -- wait until desc update complete or error occurs if(desc_update_done = '1' or mm2s_stop = '1')then mm2s_ns <= IDLE; else mm2s_ns <= WAIT_STATUS; end if; -- coverage on ------------------------------------------------------------------- -- coverage off when others => mm2s_ns <= IDLE; -- coverage on end case; end process MM2S_MACHINE; ------------------------------------------------------------------------------- -- register state machine states ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_cs <= IDLE; else mm2s_cs <= mm2s_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- register state machine signals ------------------------------------------------------------------------------- --SM_SIG_REGISTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- desc_fetch_req <= '0' ; -- else -- if (C_SG_INCLUDE_DESC_QUEUE = 0) then -- desc_fetch_req <= '1'; --desc_fetch_req_cmb ; -- else -- desc_fetch_req <= desc_fetch_req_cmb ; -- end if; -- end if; -- end if; -- end process SM_SIG_REGISTER; desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else desc_fetch_req_cmb ; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to mm2s_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_cmnd_wr_i <= '0'; -- mm2s_cmnd_data <= (others => '0'); -- Fetch SM issued a command write -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in mm2s_sg_if. elsif(write_cmnd_cmb = '1')then mm2s_cmnd_wr_i <= '1'; -- mm2s_cmnd_data <= mm2s_cache_info -- & mm2s_desc_blength_v -- & mm2s_desc_blength_s -- & MM2S_CMD_RSVD -- -- Command Tag -- & '0' -- & '0' -- & mm2s_desc_eof -- Cat. EOF to CMD Tag -- & mm2s_desc_eof -- Cat. IOC to CMD Tag -- -- Command -- & mm2s_desc_baddress -- & mm2s_desc_sof -- & mm2s_desc_eof -- & MM2S_CMD_DSA -- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697 -- & PAD_VALUE -- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); else mm2s_cmnd_wr_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; mm2s_cmnd_data <= mm2s_cache_info & mm2s_desc_blength_v & mm2s_desc_blength_s & MM2S_CMD_RSVD -- Command Tag & '0' & '0' & mm2s_desc_eof -- Cat. EOF to CMD Tag & mm2s_desc_eof -- Cat. IOC to CMD Tag -- Command & mm2s_desc_baddress & mm2s_desc_sof & mm2s_desc_eof & MM2S_CMD_DSA & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697 & PAD_VALUE & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to mm2s_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then mm2s_cmnd_wr_i <= '0'; -- mm2s_cmnd_data <= (others => '0'); -- Fetch SM issued a command write -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in mm2s_sg_if. elsif(write_cmnd_cmb = '1')then mm2s_cmnd_wr_i <= '1'; -- mm2s_cmnd_data <= mm2s_cache_info -- & mm2s_desc_blength_v -- & mm2s_desc_blength_s -- & MM2S_CMD_RSVD -- -- Command Tag -- & '0' -- & '0' -- & mm2s_desc_eof -- Cat. EOF to CMD Tag -- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF) -- -- Command -- & mm2s_desc_baddress -- & mm2s_desc_sof -- & mm2s_desc_eof -- & MM2S_CMD_DSA -- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697 -- & mm2s_desc_blength; else mm2s_cmnd_wr_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; mm2s_cmnd_data <= mm2s_cache_info & mm2s_desc_blength_v & mm2s_desc_blength_s & MM2S_CMD_RSVD -- Command Tag & '0' & '0' & mm2s_desc_eof -- Cat. EOF to CMD Tag & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF) -- Command & mm2s_desc_baddress & mm2s_desc_sof & mm2s_desc_eof & MM2S_CMD_DSA & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697 & mm2s_desc_blength; end generate GEN_CMD_BTT_EQL_23; ------------------------------------------------------------------------------- -- Counter for keepting track of pending commands/status in primary datamover -- Use this to determine if primary datamover for mm2s is Idle. ------------------------------------------------------------------------------- -- increment with each command written count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0' else '0'; -- decrement with each status received count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1' else '0'; -- count number of queued commands to keep track of what datamover is still -- working on --CMD2STS_COUNTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then -- cmnds_queued <= (others => '0'); -- elsif(count_incr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1); -- elsif(count_decr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1); -- end if; -- end if; -- end process CMD2STS_COUNTER; QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then cmnds_queued_shift <= (others => '0'); elsif(count_incr = '1')then cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1'; elsif(count_decr = '1')then cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1); end if; end if; end process CMD2STS_COUNTER1; end generate QUEUE_COUNT; NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin -- coverage off CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then cmnds_queued_shift(0) <= '0'; elsif(count_incr = '1')then cmnds_queued_shift (0) <= '1'; elsif(count_decr = '1')then cmnds_queued_shift (0) <= '0'; end if; end if; end process CMD2STS_COUNTER1; end generate NOQUEUE_COUNT; -- coverage on -- Indicate status is idle when no cmnd/sts queued --mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000" -- else '0'; mm2s_sts_idle <= not cmnds_queued_shift (0); ------------------------------------------------------------------------------- -- Queue only the amount of commands that can be queued on descriptor update -- else lock up can occur. Note datamover command fifo depth is set to number -- of descriptors to queue. ------------------------------------------------------------------------------- --QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; -- else -- queue_more <= '0'; -- end if; -- end if; -- end process QUEUE_MORE_PROCESS; QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then queue_more <= '0'; -- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; else queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1)); end if; end if; end process QUEUE_MORE_PROCESS; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_rdmux.vhd

13

69082

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_rdmux.vhd -- -- Description: -- This file implements the DataMover Master Read Data Multiplexer. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_sg_rdmux is generic ( C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the select control bus C_MMAP_DWIDTH : Integer range 32 to 1024 := 32; -- Indicates the width of the AXI4 Data Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32 -- Indicates the width of the AXI Stream Data Channel ); port ( -- AXI MMap Data Channel Input ----------------------------------------------- -- mmap_read_data_in : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); -- -- AXI Read data input -- ------------------------------------------------------------------------------- -- AXI Master Stream --------------------------------------------------------- -- mux_data_out : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- --Mux data output -- ------------------------------------------------------------------------------- -- Command Calculator Interface ----------------------------------------------- -- mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap Data -- -- Width). -- ------------------------------------------------------------------------------- ); end entity axi_sg_rdmux; architecture implementation of axi_sg_rdmux is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Decalarations ------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_mux_sel_width -- -- Function Description: -- Calculates the number of needed bits for the Mux Select control -- based on the number of input channels to the mux. -- -- Note that the number of input mux channels are always a -- power of 2. -- ------------------------------------------------------------------- function func_mux_sel_width (num_channels : integer) return integer is Variable var_sel_width : integer := 0; begin case num_channels is when 2 => var_sel_width := 1; when 4 => var_sel_width := 2; when 8 => var_sel_width := 3; when 16 => var_sel_width := 4; when 32 => var_sel_width := 5; when 64 => var_sel_width := 6; when 128 => var_sel_width := 7; when others => var_sel_width := 0; end case; Return (var_sel_width); end function func_mux_sel_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_sel_ls_index -- -- Function Description: -- Calculates the LS index of the select field to rip from the -- input select bus. -- -- Note that the number of input mux channels are always a -- power of 2. -- ------------------------------------------------------------------- function func_sel_ls_index (channel_width : integer) return integer is Variable var_sel_ls_index : integer := 0; begin case channel_width is when 8 => var_sel_ls_index := 0; when 16 => var_sel_ls_index := 1; when 32 => var_sel_ls_index := 2; when 64 => var_sel_ls_index := 3; when 128 => var_sel_ls_index := 4; when 256 => var_sel_ls_index := 5; when 512 => var_sel_ls_index := 6; when others => -- 1024-bit channel case var_sel_ls_index := 7; end case; Return (var_sel_ls_index); end function func_sel_ls_index; -- Constant Decalarations ------------------------------------------------- Constant CHANNEL_DWIDTH : integer := C_STREAM_DWIDTH; Constant NUM_MUX_CHANNELS : integer := C_MMAP_DWIDTH/CHANNEL_DWIDTH; Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS); Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(CHANNEL_DWIDTH); -- Signal Declarations -------------------------------------------- signal sig_rdmux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin --(architecture implementation) -- Assign the Output data port mux_data_out <= sig_rdmux_dout; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_STRM_EQ_MMAP -- -- If Generate Description: -- This IfGen implements the case where the Stream Data Width is -- the same as the Memory Map read Data width. -- -- ------------------------------------------------------------ GEN_STRM_EQ_MMAP : if (NUM_MUX_CHANNELS = 1) generate begin sig_rdmux_dout <= mmap_read_data_in; end generate GEN_STRM_EQ_MMAP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_2XN -- -- If Generate Description: -- 2 channel input mux case -- -- ------------------------------------------------------------ GEN_2XN : if (NUM_MUX_CHANNELS = 2) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_2XN_NUX -- -- Process Description: -- Implement the 2XN Mux -- ------------------------------------------------------------- DO_2XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when others => -- 1 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1); end case; end process DO_2XN_NUX; end generate GEN_2XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_4XN -- -- If Generate Description: -- 4 channel input mux case -- -- ------------------------------------------------------------ GEN_4XN : if (NUM_MUX_CHANNELS = 4) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_4XN_NUX -- -- Process Description: -- Implement the 4XN Mux -- ------------------------------------------------------------- DO_4XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1); when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2); when others => -- 3 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3); end case; end process DO_4XN_NUX; end generate GEN_4XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_8XN -- -- If Generate Description: -- 8 channel input mux case -- -- ------------------------------------------------------------ GEN_8XN : if (NUM_MUX_CHANNELS = 8) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_8XN_NUX -- -- Process Description: -- Implement the 8XN Mux -- ------------------------------------------------------------- DO_8XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1); when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2); when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3); when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4); when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5); when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6); when others => -- 7 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7); end case; end process DO_8XN_NUX; end generate GEN_8XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_16XN -- -- If Generate Description: -- 16 channel input mux case -- -- ------------------------------------------------------------ GEN_16XN : if (NUM_MUX_CHANNELS = 16) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_16XN_NUX -- -- Process Description: -- Implement the 16XN Mux -- ------------------------------------------------------------- DO_16XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1); when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2); when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3); when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4); when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5); when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6); when 7 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7); when 8 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8); when 9 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9); when 10 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10); when 11 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11); when 12 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12); when 13 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13); when 14 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14); when others => -- 15 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15); end case; end process DO_16XN_NUX; end generate GEN_16XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_32XN -- -- If Generate Description: -- 32 channel input mux case -- -- ------------------------------------------------------------ GEN_32XN : if (NUM_MUX_CHANNELS = 32) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_32XN_NUX -- -- Process Description: -- Implement the 32XN Mux -- ------------------------------------------------------------- DO_32XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0); when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1); when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2); when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3); when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4); when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5); when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6); when 7 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7); when 8 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8); when 9 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9); when 10 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10); when 11 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11); when 12 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12); when 13 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13); when 14 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14); when 15 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15); when 16 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16); when 17 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17); when 18 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18); when 19 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19); when 20 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20); when 21 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21); when 22 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22); when 23 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23); when 24 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24); when 25 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25); when 26 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26); when 27 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27); when 28 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28); when 29 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29); when 30 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30); when others => -- 31 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31); end case; end process DO_32XN_NUX; end generate GEN_32XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_64XN -- -- If Generate Description: -- 64 channel input mux case -- -- ------------------------------------------------------------ GEN_64XN : if (NUM_MUX_CHANNELS = 64) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_64XN_NUX -- -- Process Description: -- Implement the 64XN Mux -- ------------------------------------------------------------- DO_64XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ; when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ; when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ; when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ; when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ; when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ; when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ; when 7 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ; when 8 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ; when 9 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ; when 10 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10); when 11 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11); when 12 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12); when 13 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13); when 14 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14); when 15 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15); when 16 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16); when 17 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17); when 18 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18); when 19 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19); when 20 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20); when 21 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21); when 22 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22); when 23 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23); when 24 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24); when 25 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25); when 26 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26); when 27 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27); when 28 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28); when 29 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29); when 30 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30); when 31 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31); when 32 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32); when 33 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33); when 34 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34); when 35 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35); when 36 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36); when 37 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37); when 38 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38); when 39 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39); when 40 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40); when 41 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41); when 42 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42); when 43 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43); when 44 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44); when 45 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45); when 46 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46); when 47 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47); when 48 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48); when 49 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49); when 50 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50); when 51 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51); when 52 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52); when 53 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53); when 54 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54); when 55 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55); when 56 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56); when 57 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57); when 58 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58); when 59 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59); when 60 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60); when 61 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61); when 62 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62); when others => -- 63 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63); end case; end process DO_64XN_NUX; end generate GEN_64XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_128XN -- -- If Generate Description: -- 128 channel input mux case -- -- ------------------------------------------------------------ GEN_128XN : if (NUM_MUX_CHANNELS = 128) generate -- local signals signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_mux_sel_int : integer := 0; signal sig_mux_sel_int_local : integer := 0; signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens sig_mux_sel_int_local <= sig_mux_sel_int; sig_rdmux_dout <= sig_mux_dout; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_128XN_NUX -- -- Process Description: -- Implement the 64XN Mux -- ------------------------------------------------------------- DO_128XN_NUX : process (sig_mux_sel_int_local, mmap_read_data_in) begin case sig_mux_sel_int_local is when 0 => sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ; when 1 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ; when 2 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ; when 3 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ; when 4 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ; when 5 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ; when 6 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ; when 7 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ; when 8 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ; when 9 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ; when 10 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10); when 11 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11); when 12 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12); when 13 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13); when 14 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14); when 15 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15); when 16 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16); when 17 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17); when 18 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18); when 19 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19); when 20 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20); when 21 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21); when 22 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22); when 23 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23); when 24 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24); when 25 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25); when 26 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26); when 27 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27); when 28 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28); when 29 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29); when 30 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30); when 31 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31); when 32 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32); when 33 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33); when 34 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34); when 35 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35); when 36 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36); when 37 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37); when 38 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38); when 39 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39); when 40 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40); when 41 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41); when 42 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42); when 43 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43); when 44 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44); when 45 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45); when 46 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46); when 47 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47); when 48 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48); when 49 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49); when 50 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50); when 51 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51); when 52 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52); when 53 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53); when 54 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54); when 55 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55); when 56 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56); when 57 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57); when 58 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58); when 59 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59); when 60 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60); when 61 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61); when 62 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62); when 63 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63); when 64 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*65)-1 downto CHANNEL_DWIDTH*64) ; when 65 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*66)-1 downto CHANNEL_DWIDTH*65) ; when 66 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*67)-1 downto CHANNEL_DWIDTH*66) ; when 67 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*68)-1 downto CHANNEL_DWIDTH*67) ; when 68 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*69)-1 downto CHANNEL_DWIDTH*68) ; when 69 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*70)-1 downto CHANNEL_DWIDTH*69) ; when 70 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*71)-1 downto CHANNEL_DWIDTH*70) ; when 71 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*72)-1 downto CHANNEL_DWIDTH*71) ; when 72 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*73)-1 downto CHANNEL_DWIDTH*72) ; when 73 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*74)-1 downto CHANNEL_DWIDTH*73) ; when 74 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*75)-1 downto CHANNEL_DWIDTH*74) ; when 75 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*76)-1 downto CHANNEL_DWIDTH*75) ; when 76 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*77)-1 downto CHANNEL_DWIDTH*76) ; when 77 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*78)-1 downto CHANNEL_DWIDTH*77) ; when 78 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*79)-1 downto CHANNEL_DWIDTH*78) ; when 79 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*80)-1 downto CHANNEL_DWIDTH*79) ; when 80 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*81)-1 downto CHANNEL_DWIDTH*80) ; when 81 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*82)-1 downto CHANNEL_DWIDTH*81) ; when 82 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*83)-1 downto CHANNEL_DWIDTH*82) ; when 83 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*84)-1 downto CHANNEL_DWIDTH*83) ; when 84 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*85)-1 downto CHANNEL_DWIDTH*84) ; when 85 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*86)-1 downto CHANNEL_DWIDTH*85) ; when 86 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*87)-1 downto CHANNEL_DWIDTH*86) ; when 87 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*88)-1 downto CHANNEL_DWIDTH*87) ; when 88 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*89)-1 downto CHANNEL_DWIDTH*88) ; when 89 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*90)-1 downto CHANNEL_DWIDTH*89) ; when 90 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*91)-1 downto CHANNEL_DWIDTH*90) ; when 91 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*92)-1 downto CHANNEL_DWIDTH*91) ; when 92 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*93)-1 downto CHANNEL_DWIDTH*92) ; when 93 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*94)-1 downto CHANNEL_DWIDTH*93) ; when 94 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*95)-1 downto CHANNEL_DWIDTH*94) ; when 95 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*96)-1 downto CHANNEL_DWIDTH*95) ; when 96 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*97 )-1 downto CHANNEL_DWIDTH*96 ) ; when 97 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*98 )-1 downto CHANNEL_DWIDTH*97 ) ; when 98 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*99 )-1 downto CHANNEL_DWIDTH*98 ) ; when 99 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*100)-1 downto CHANNEL_DWIDTH*99 ) ; when 100 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*101)-1 downto CHANNEL_DWIDTH*100) ; when 101 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*102)-1 downto CHANNEL_DWIDTH*101) ; when 102 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*103)-1 downto CHANNEL_DWIDTH*102) ; when 103 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*104)-1 downto CHANNEL_DWIDTH*103) ; when 104 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*105)-1 downto CHANNEL_DWIDTH*104) ; when 105 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*106)-1 downto CHANNEL_DWIDTH*105) ; when 106 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*107)-1 downto CHANNEL_DWIDTH*106) ; when 107 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*108)-1 downto CHANNEL_DWIDTH*107) ; when 108 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*109)-1 downto CHANNEL_DWIDTH*108) ; when 109 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*110)-1 downto CHANNEL_DWIDTH*109) ; when 110 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*111)-1 downto CHANNEL_DWIDTH*110) ; when 111 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*112)-1 downto CHANNEL_DWIDTH*111) ; when 112 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*113)-1 downto CHANNEL_DWIDTH*112) ; when 113 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*114)-1 downto CHANNEL_DWIDTH*113) ; when 114 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*115)-1 downto CHANNEL_DWIDTH*114) ; when 115 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*116)-1 downto CHANNEL_DWIDTH*115) ; when 116 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*117)-1 downto CHANNEL_DWIDTH*116) ; when 117 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*118)-1 downto CHANNEL_DWIDTH*117) ; when 118 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*119)-1 downto CHANNEL_DWIDTH*118) ; when 119 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*120)-1 downto CHANNEL_DWIDTH*119) ; when 120 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*121)-1 downto CHANNEL_DWIDTH*120) ; when 121 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*122)-1 downto CHANNEL_DWIDTH*121) ; when 122 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*123)-1 downto CHANNEL_DWIDTH*122) ; when 123 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*124)-1 downto CHANNEL_DWIDTH*123) ; when 124 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*125)-1 downto CHANNEL_DWIDTH*124) ; when 125 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*126)-1 downto CHANNEL_DWIDTH*125) ; when 126 => sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*127)-1 downto CHANNEL_DWIDTH*126) ; when others => -- 127 case sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*128)-1 downto CHANNEL_DWIDTH*127) ; end case; end process DO_128XN_NUX; end generate GEN_128XN; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_bram_ctrl_v4_0/b6365b74/hdl/vhdl/coregen_comp_defs.vhd

4

13824

------------------------------------------------------------------------------- -- coregen_comp_defs - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2008-2013 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: coregen_comp_defs.vhd -- Version: initial -- Description: -- Component declarations for all black box netlists generated by -- running COREGEN and AXI BRAM CTRL when XST elaborated the client core -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- coregen_comp_defs.vhd ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; PACKAGE coregen_comp_defs IS ------------------------------------------------------------------------------------- -- Start Block Memory Generator Component for blk_mem_gen_v8_2 -- Component declaration for blk_mem_gen_v8_2 pulled from the blk_mem_gen_v8_2.v -- Verilog file used to match paramter order for NCSIM compatibility ------------------------------------------------------------------------------------- component blk_mem_gen_v8_2 generic ( ---------------------------------------------------------------------------- -- Generic Declarations ---------------------------------------------------------------------------- --Device Family & Elaboration Directory Parameters: C_FAMILY : STRING := "virtex4"; C_XDEVICEFAMILY : STRING := "virtex4"; -- C_ELABORATION_DIR : STRING := ""; C_INTERFACE_TYPE : INTEGER := 0; C_AXI_TYPE : INTEGER := 1; C_AXI_SLAVE_TYPE : INTEGER := 0; C_HAS_AXI_ID : INTEGER := 0; C_AXI_ID_WIDTH : INTEGER := 4; --General Memory Parameters: C_MEM_TYPE : INTEGER := 2; C_BYTE_SIZE : INTEGER := 9; C_ALGORITHM : INTEGER := 0; C_PRIM_TYPE : INTEGER := 3; --Memory Initialization Parameters: C_LOAD_INIT_FILE : INTEGER := 0; C_INIT_FILE_NAME : STRING := ""; C_USE_DEFAULT_DATA : INTEGER := 0; C_DEFAULT_DATA : STRING := "111111111"; C_RST_TYPE : STRING := "SYNC"; --Port A Parameters: --Reset Parameters: C_HAS_RSTA : INTEGER := 0; C_RST_PRIORITY_A : STRING := "CE"; C_RSTRAM_A : INTEGER := 0; C_INITA_VAL : STRING := "0"; --Enable Parameters: C_HAS_ENA : INTEGER := 1; C_HAS_REGCEA : INTEGER := 0; --Byte Write Enable Parameters: C_USE_BYTE_WEA : INTEGER := 0; C_WEA_WIDTH : INTEGER := 1; --Write Mode: C_WRITE_MODE_A : STRING := "WRITE_FIRST"; --Data-Addr Width Parameters: C_WRITE_WIDTH_A : INTEGER := 4; C_READ_WIDTH_A : INTEGER := 4; C_WRITE_DEPTH_A : INTEGER := 4096; C_READ_DEPTH_A : INTEGER := 4096; C_ADDRA_WIDTH : INTEGER := 12; --Port B Parameters: --Reset Parameters: C_HAS_RSTB : INTEGER := 0; C_RST_PRIORITY_B : STRING := "CE"; C_RSTRAM_B : INTEGER := 0; C_INITB_VAL : STRING := "0"; --Enable Parameters: C_HAS_ENB : INTEGER := 1; C_HAS_REGCEB : INTEGER := 0; --Byte Write Enable Parameters: C_USE_BYTE_WEB : INTEGER := 0; C_WEB_WIDTH : INTEGER := 1; --Write Mode: C_WRITE_MODE_B : STRING := "WRITE_FIRST"; --Data-Addr Width Parameters: C_WRITE_WIDTH_B : INTEGER := 4; C_READ_WIDTH_B : INTEGER := 4; C_WRITE_DEPTH_B : INTEGER := 4096; C_READ_DEPTH_B : INTEGER := 4096; C_ADDRB_WIDTH : INTEGER := 12; --Output Registers/ Pipelining Parameters: C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0; C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0; C_MUX_PIPELINE_STAGES : INTEGER := 0; --Input/Output Registers for SoftECC : C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0; --ECC Parameters C_USE_ECC : INTEGER := 0; C_USE_SOFTECC : INTEGER := 0; C_HAS_INJECTERR : INTEGER := 0; --Simulation Model Parameters: C_SIM_COLLISION_CHECK : STRING := "NONE"; C_COMMON_CLK : INTEGER := 0; C_DISABLE_WARN_BHV_COLL : INTEGER := 0; C_DISABLE_WARN_BHV_RANGE : INTEGER := 0 ); PORT ( ---------------------------------------------------------------------------- -- Input and Output Declarations ---------------------------------------------------------------------------- -- Native BMG Input and Output Port Declarations --Port A: CLKA : IN STD_LOGIC := '0'; RSTA : IN STD_LOGIC := '0'; ENA : IN STD_LOGIC := '0'; REGCEA : IN STD_LOGIC := '0'; WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0); --Port B: CLKB : IN STD_LOGIC := '0'; RSTB : IN STD_LOGIC := '0'; ENB : IN STD_LOGIC := '0'; REGCEB : IN STD_LOGIC := '0'; WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0'); DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0); --ECC: INJECTSBITERR : IN STD_LOGIC := '0'; INJECTDBITERR : IN STD_LOGIC := '0'; SBITERR : OUT STD_LOGIC; DBITERR : OUT STD_LOGIC; RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0); -- AXI BMG Input and Output Port Declarations -- AXI Global Signals S_AClk : IN STD_LOGIC := '0'; S_ARESETN : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Write (write side) S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN STD_LOGIC := '0'; S_AXI_AWREADY : OUT STD_LOGIC; S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WLAST : IN STD_LOGIC := '0'; S_AXI_WVALID : IN STD_LOGIC := '0'; S_AXI_WREADY : OUT STD_LOGIC; S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_BVALID : OUT STD_LOGIC; S_AXI_BREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Slave Read (Write side) S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN STD_LOGIC := '0'; S_AXI_ARREADY : OUT STD_LOGIC; S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); S_AXI_RLAST : OUT STD_LOGIC; S_AXI_RVALID : OUT STD_LOGIC; S_AXI_RREADY : IN STD_LOGIC := '0'; -- AXI Full/Lite Sideband Signals S_AXI_INJECTSBITERR : IN STD_LOGIC := '0'; S_AXI_INJECTDBITERR : IN STD_LOGIC := '0'; S_AXI_SBITERR : OUT STD_LOGIC; S_AXI_DBITERR : OUT STD_LOGIC; S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ); END COMPONENT; --blk_mem_gen_v8_2 END coregen_comp_defs;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_reset.vhd

12

23104

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_reset.vhd -- -- Description: -- This file implements the DataMover Reset module. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_sg_reset is generic ( C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0 -- 0 = Use Synchronous Command/Statys User Interface -- 1 = Use Asynchronous Command/Statys User Interface ); port ( -- Primary Clock and Reset Inputs ----------------- -- primary_aclk : in std_logic; -- primary_aresetn : in std_logic; -- --------------------------------------------------- -- Async operation clock and reset from User ------ -- Used for Command/Status User interface -- -- synchronization when C_STSCMD_IS_ASYNC = 1 -- -- secondary_awclk : in std_logic; -- secondary_aresetn : in std_logic; -- --------------------------------------------------- -- Halt request input control ------------------------------- halt_req : in std_logic; -- -- Active high soft shutdown request (can be a pulse) -- -- -- Halt Complete status flag -- halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Soft Shutdown internal interface ------------------------------------------------ -- flush_stop_request : Out std_logic; -- -- Active high soft stop request to modules -- -- data_cntlr_stopped : in std_logic; -- -- Active high flag indicating the data controller is flushed and stopped -- -- addr_cntlr_stopped : in std_logic; -- -- Active high flag indicating the address controller is flushed and stopped -- -- aux1_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 1 module -- -- Tie high if unused -- -- aux2_stopped : in std_logic; -- -- Active high flag flush complete for auxillary 2 module -- -- Tie high if unused -- ------------------------------------------------------------------------------------ -- HW Reset outputs to reset groups ------------------------------------- -- cmd_stat_rst_user : Out std_logic; -- -- The reset to the Command/Status Module User interface side -- -- cmd_stat_rst_int : Out std_logic; -- -- The reset to the Command/Status Module internal interface side -- -- mmap_rst : Out std_logic; -- -- The reset to the Memory Map interface side -- -- stream_rst : Out std_logic -- -- The reset to the Stream interface side -- -------------------------------------------------------------------------- ); end entity axi_sg_reset; architecture implementation of axi_sg_reset is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Signals signal sig_cmd_stat_rst_user_n : std_logic := '0'; signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0'; signal sig_cmd_stat_rst_int_reg_n : std_logic := '0'; signal sig_mmap_rst_reg_n : std_logic := '0'; signal sig_stream_rst_reg_n : std_logic := '0'; signal sig_syncd_sec_rst : std_logic := '0'; -- soft shutdown support signal sig_internal_reset : std_logic := '0'; signal sig_s_h_halt_reg : std_logic := '0'; signal sig_halt_cmplt : std_logic := '0'; -- additional CDC synchronization signals signal sig_sec_neg_edge_plus_delay : std_logic := '0'; signal sig_secondary_aresetn_reg : std_logic := '0'; signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0'; signal sig_prim2sec_rst_reg2_n : std_logic := '0'; begin --(architecture implementation) -- Assign outputs cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n); cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; mmap_rst <= not(sig_mmap_rst_reg_n) or sig_syncd_sec_rst; stream_rst <= not(sig_stream_rst_reg_n) or sig_syncd_sec_rst; -- Internal logic Implmentation ------------------------------------------------------------ -- If Generate -- -- Label: GEN_SYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Synchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate begin sig_syncd_sec_rst <= '0'; sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from); end generate GEN_SYNC_CMDSTAT_RESET; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ASYNC_CMDSTAT_RESET -- -- If Generate Description: -- This IfGen assigns the reset for the -- Asynchronous Command/Status User interface case -- ------------------------------------------------------------ GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate signal sig_sec_reset_in_reg_n : std_logic := '0'; -- Secondary reset pulse stretcher signal sig_secondary_dly1 : std_logic := '0'; signal sig_secondary_dly2 : std_logic := '0'; signal sig_neg_edge_detect : std_logic := '0'; signal sig_sec2prim_reset : std_logic := '0'; signal sig_sec2prim_reset_reg : std_logic := '0'; signal sig_sec2prim_reset_reg2 : std_logic := '0'; signal sig_sec2prim_rst_syncro1 : std_logic := '0'; signal sig_sec2prim_rst_syncro2 : std_logic := '0'; begin -- Generate the reset in the primary clock domain. Use the longer -- of the pulse stretched reset or the actual reset. sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or sig_sec2prim_rst_syncro2; -- Check for falling edge of secondary_aresetn input sig_neg_edge_detect <= '1' when (sig_sec_reset_in_reg_n = '1' and secondary_aresetn = '0') else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSE_STRETCH_FLOPS -- -- Process Description: -- This process implements a 3 clock wide pulse whenever the -- secondary reset is asserted -- ------------------------------------------------------------- IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then If (sig_secondary_dly2 = '1') Then sig_secondary_dly1 <= '0' ; sig_secondary_dly2 <= '0' ; Elsif (sig_neg_edge_detect = '1') Then sig_secondary_dly1 <= '1'; else sig_secondary_dly2 <= sig_secondary_dly1 ; End if; end if; end process IMP_PUSE_STRETCH_FLOPS; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_NEG_EDGE -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- negative edge detection, -- ------------------------------------------------------------- SYNC_NEG_EDGE : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or sig_secondary_dly1 or sig_secondary_dly2; end if; end process SYNC_NEG_EDGE; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO -- -- Process Description: -- This process registers the secondary reset input to -- the primary clock domain. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_sec2prim_reset_reg <= sig_sec_neg_edge_plus_delay ; sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg; end if; end process SEC2PRIM_RST_SYNCRO; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_SEC_RST -- -- Process Description: -- First (source clock) stage synchronizer for CDC of -- secondary reset input, -- ------------------------------------------------------------- REG_SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_secondary_aresetn_reg <= secondary_aresetn; end if; end process REG_SEC_RST; -- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SEC2PRIM_RST_SYNCRO_2 -- -- Process Description: -- Second stage (destination) synchronizers for the secondary -- reset CDC to the primary clock. -- ------------------------------------------------------------- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then -- CDC sig_sec2prim_rst_syncro1 <= not(secondary_aresetn); sig_sec2prim_rst_syncro1 <= not(sig_secondary_aresetn_reg); sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1; end if; end process SEC2PRIM_RST_SYNCRO_2; -- Generate the Command and Status side reset sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and sig_prim2sec_rst_reg2_n; -- CDC sig_cmd_stat_rst_user_reg_n_cdc_from; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_RESET_ASYNC -- -- Process Description: -- This process registers the secondary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_RESET_ASYNC : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_sec_reset_in_reg_n <= secondary_aresetn; end if; end process REG_RESET_ASYNC; -- CDC add ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SYNC_PRIM2SEC_RST -- -- Process Description: -- Second (destination clock) stage synchronizers for CDC of -- primary reset input, -- ------------------------------------------------------------- SYNC_PRIM2SEC_RST : process (secondary_awclk) begin if (secondary_awclk'event and secondary_awclk = '1') then sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from; sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to; end if; end process SYNC_PRIM2SEC_RST; -- end generate GEN_ASYNC_CMDSTAT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_PRIM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status User interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_PRIM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn; end if; end process REG_CMDSTAT_PRIM_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_CMDSTAT_INT_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Command/Status internal interface reset. -- ------------------------------------------------------------- REG_CMDSTAT_INT_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_cmd_stat_rst_int_reg_n <= primary_aresetn; end if; end process REG_CMDSTAT_INT_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_MMAP_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Memory Map interface reset. -- ------------------------------------------------------------- REG_MMAP_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_mmap_rst_reg_n <= primary_aresetn; end if; end process REG_MMAP_RESET; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_STREAM_RESET -- -- Process Description: -- This process registers the primary reset input to -- generate the Stream interface reset. -- ------------------------------------------------------------- REG_STREAM_RESET : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then sig_stream_rst_reg_n <= primary_aresetn; end if; end process REG_STREAM_RESET; -- Soft Shutdown logic ------------------------------------------------------ sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or sig_syncd_sec_rst; flush_stop_request <= sig_s_h_halt_reg; halt_cmplt <= sig_halt_cmplt; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_HALT_REQ -- -- Process Description: -- Implements a sample and hold flop for the halt request -- input. Can only be cleared on a HW reset. -- ------------------------------------------------------------- REG_HALT_REQ : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_s_h_halt_reg <= '0'; elsif (halt_req = '1') then sig_s_h_halt_reg <= '1'; else null; -- hold current state end if; end if; end process REG_HALT_REQ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_CMPLT -- -- Process Description: -- Implements a the flop for the halt complete status -- output. Can only be cleared on a HW reset. -- ------------------------------------------------------------- IMP_HALT_CMPLT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_internal_reset = '1') then sig_halt_cmplt <= '0'; elsif (data_cntlr_stopped = '1' and addr_cntlr_stopped = '1' and aux1_stopped = '1' and aux2_stopped = '1') then sig_halt_cmplt <= '1'; else null; -- hold current state end if; end if; end process IMP_HALT_CMPLT; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_mssai_skid_buf.vhd

6

24680

------------------------------------------------------------------------------- -- axi_datamover_mssai_skid_buf.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mssai_skid_buf.vhd -- -- Description: -- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode that -- also incorporates the MS Strobe Asserted detection function needed by the -- module. This provides a register isolation of the MS asserted strobe index -- Scatter needed to improve Fmax. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; Use axi_datamover_v5_1.axi_datamover_ms_strb_set; ------------------------------------------------------------------------------- entity axi_datamover_mssai_skid_buf is generic ( C_WDATA_WIDTH : INTEGER range 8 to 1024 := 32 ; -- Width of the Stream Data bus (in bits) C_INDEX_WIDTH : Integer range 1 to 8 := 2 -- Sets the width of the MS asserted strobe index output value ); port ( -- Clock and Reset Ports ----------------------- aclk : In std_logic ; -- arst : In std_logic ; -- ------------------------------------------------ -- Shutdown control (assert for 1 clk pulse) --- skid_stop : In std_logic ; -- ------------------------------------------------ -- Slave Side (Stream Data Input) ------------------------------------ s_valid : In std_logic ; -- s_ready : Out std_logic ; -- s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- s_last : In std_logic ; -- ---------------------------------------------------------------------- -- Master Side (Stream Data Output ----------------------------------- m_valid : Out std_logic ; -- m_ready : In std_logic ; -- m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- m_last : Out std_logic ; -- -- m_mssa_index : Out std_logic_vector(C_INDEX_WIDTH-1 downto 0); -- m_strb_error : Out std_logic -- ---------------------------------------------------------------------- ); end entity axi_datamover_mssai_skid_buf; architecture implementation of axi_datamover_mssai_skid_buf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Constant declarations ------------------------- Constant STROBE_WIDTH : integer := C_WDATA_WIDTH/8; -- Signals declarations ------------------------- Signal sig_reset_reg : std_logic := '0'; signal sig_spcl_s_ready_set : std_logic := '0'; signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_reg : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_skid_reg : std_logic := '0'; signal sig_skid_reg_en : std_logic := '0'; signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_mux_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_skid_mux_out : std_logic := '0'; signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_reg_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_reg_out : std_logic := '0'; signal sig_data_reg_out_en : std_logic := '0'; signal sig_m_valid_out : std_logic := '0'; signal sig_m_valid_dup : std_logic := '0'; signal sig_m_valid_comb : std_logic := '0'; signal sig_s_ready_out : std_logic := '0'; signal sig_s_ready_comb : std_logic := '0'; signal sig_stop_request : std_logic := '0'; signal sig_stopped : std_logic := '0'; signal sig_sready_stop : std_logic := '0'; signal sig_sready_early_stop : std_logic := '0'; signal sig_sready_stop_set : std_logic := '0'; signal sig_sready_stop_reg : std_logic := '0'; signal sig_mvalid_stop_reg : std_logic := '0'; signal sig_mvalid_stop : std_logic := '0'; signal sig_mvalid_early_stop : std_logic := '0'; signal sig_mvalid_stop_set : std_logic := '0'; signal sig_slast_with_stop : std_logic := '0'; signal sig_sstrb_stop_mask : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_sstrb_with_stop : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_mssa_index_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_mssa_index_reg_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_error : std_logic := '0'; signal sig_strb_error_reg_out : std_logic := '0'; -- Fmax improvements signal sig_s_ready_dup : std_logic := '0'; signal sig_s_ready_dup2 : std_logic := '0'; signal sig_s_ready_dup3 : std_logic := '0'; signal sig_s_ready_dup4 : std_logic := '0'; signal sig_skid_mux_sel : std_logic := '0'; signal sig_skid_mux_sel2 : std_logic := '0'; signal sig_skid_mux_sel3 : std_logic := '0'; signal sig_skid_mux_sel4 : std_logic := '0'; -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup2 : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup3 : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup4 : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup2 : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup3 : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup4 : signal is "no"; begin --(architecture implementation) m_valid <= sig_m_valid_out; s_ready <= sig_s_ready_out; m_strb <= sig_strb_reg_out; m_last <= sig_last_reg_out; m_data <= sig_data_reg_out; m_mssa_index <= sig_mssa_index_reg_out; m_strb_error <= sig_strb_error_reg_out; -- Special shutdown logic version of Slast. -- A halt request forces a tlast through the skig buffer sig_slast_with_stop <= s_last or sig_stop_request; sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask; -- Assign the special s_ready FLOP set signal sig_spcl_s_ready_set <= sig_reset_reg; -- Generate the ouput register load enable control sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup); -- Generate the skid input register load enable control sig_skid_reg_en <= sig_s_ready_dup; -- Generate the skid mux select control sig_skid_mux_sel2 <= not(sig_s_ready_dup2); sig_skid_mux_sel3 <= not(sig_s_ready_dup3); sig_skid_mux_sel4 <= not(sig_s_ready_dup4); -- Skid Mux sig_data_skid_mux_out <= sig_data_skid_reg When (sig_skid_mux_sel2 = '1') Else s_data; sig_strb_skid_mux_out <= sig_strb_skid_reg When (sig_skid_mux_sel3 = '1') Else sig_sstrb_with_stop; sig_last_skid_mux_out <= sig_last_skid_reg When (sig_skid_mux_sel4 = '1') Else sig_slast_with_stop; -- m_valid combinational logic sig_m_valid_comb <= s_valid or (sig_m_valid_dup and (not(sig_s_ready_dup) or not(m_ready))); -- s_ready combinational logic sig_s_ready_comb <= m_ready or (sig_s_ready_dup and (not(sig_m_valid_dup) or not(s_valid))); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_THE_RST -- -- Process Description: -- Register input reset -- ------------------------------------------------------------- REG_THE_RST : process (aclk) begin if (aclk'event and aclk = '1') then sig_reset_reg <= arst; end if; end process REG_THE_RST; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_READY_FLOP -- -- Process Description: -- Registers s_ready handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- S_READY_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_sready_stop = '1' or sig_sready_early_stop = '1') then -- Special stop condition sig_s_ready_out <= '0'; sig_s_ready_dup <= '0'; sig_s_ready_dup2 <= '0'; sig_s_ready_dup3 <= '0'; sig_s_ready_dup4 <= '0'; Elsif (sig_spcl_s_ready_set = '1') Then sig_s_ready_out <= '1'; sig_s_ready_dup <= '1'; sig_s_ready_dup2 <= '1'; sig_s_ready_dup3 <= '1'; sig_s_ready_dup4 <= '1'; else sig_s_ready_out <= sig_s_ready_comb; sig_s_ready_dup <= sig_s_ready_comb; sig_s_ready_dup2 <= sig_s_ready_comb; sig_s_ready_dup3 <= sig_s_ready_comb; sig_s_ready_dup4 <= sig_s_ready_comb; end if; end if; end process S_READY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: M_VALID_FLOP -- -- Process Description: -- Registers m_valid handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- M_VALID_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA sig_mvalid_stop = '1' or sig_mvalid_stop_set = '1') then -- Special stop condition sig_m_valid_out <= '0'; sig_m_valid_dup <= '0'; else sig_m_valid_out <= sig_m_valid_comb; sig_m_valid_dup <= sig_m_valid_comb; end if; end if; end process M_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_DATA_REG -- -- Process Description: -- This process implements the skid register for the -- Skid Buffer Data signals. Note that reset has been removed -- to reduce route of resets for very wide data buses. -- ------------------------------------------------------------- SKID_DATA_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (sig_skid_reg_en = '1') then sig_data_skid_reg <= s_data; else null; -- hold current state end if; end if; end process SKID_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_CNTL_REG -- -- Process Description: -- This process implements the skid registers for the -- Skid Buffer control signals -- ------------------------------------------------------------- SKID_CNTL_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_strb_skid_reg <= (others => '0'); sig_last_skid_reg <= '0'; elsif (sig_skid_reg_en = '1') then sig_strb_skid_reg <= sig_sstrb_with_stop; sig_last_skid_reg <= sig_slast_with_stop; else null; -- hold current state end if; end if; end process SKID_CNTL_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_DATA_REG -- -- Process Description: -- This process implements the output register for the -- Skid Buffer Data signals. Note that reset has been removed -- to reduce route of resets for very wide data buses. -- ------------------------------------------------------------- OUTPUT_DATA_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (sig_data_reg_out_en = '1') then sig_data_reg_out <= sig_data_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_CNTL_REG -- -- Process Description: -- This process implements the output registers for the -- Skid Buffer Control signals. -- ------------------------------------------------------------- OUTPUT_CNTL_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_mvalid_stop_reg = '1') then sig_strb_reg_out <= (others => '0'); sig_last_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_strb_reg_out <= sig_strb_skid_mux_out; sig_last_reg_out <= sig_last_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_CNTL_REG; -------- Special Stop Logic -------------------------------------- sig_sready_stop <= sig_sready_stop_reg; sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately sig_sready_stop_set <= sig_sready_early_stop; sig_mvalid_stop <= sig_mvalid_stop_reg; sig_mvalid_early_stop <= sig_m_valid_dup and m_ready and skid_stop; sig_mvalid_stop_set <= sig_mvalid_early_stop or (sig_stop_request and not(sig_m_valid_dup)) or (sig_m_valid_dup and m_ready and sig_stop_request); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STOP_REQ_FLOP -- -- Process Description: -- This process implements the Stop request flop. It is a -- sample and hold register that can only be cleared by reset. -- ------------------------------------------------------------- IMP_STOP_REQ_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_stop_request <= '0'; sig_sstrb_stop_mask <= (others => '0'); elsif (skid_stop = '1') then sig_stop_request <= '1'; sig_sstrb_stop_mask <= (others => '1'); else null; -- hold current state end if; end if; end process IMP_STOP_REQ_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_SREADY_FLOP -- -- Process Description: -- This process implements the flag to clear the s_ready -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_SREADY_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_sready_stop_reg <= '0'; elsif (sig_sready_stop_set = '1') then sig_sready_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_SREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_MVALID_FLOP -- -- Process Description: -- This process implements the flag to clear the m_valid -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_MVALID_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_mvalid_stop_reg <= '0'; elsif (sig_mvalid_stop_set = '1') then sig_mvalid_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_MVALID_FLOP; ---------------------------------------------------------------------------- -- Logic for the detection of the most significant asserted strobe bit and -- the formulation of the index of that strobe bit. ---------------------------------------------------------------------------- ------------------------------------------------------------ -- Instance: I_MSSAI_DETECTION -- -- Description: -- This module detects the most significant asserted strobe -- and outputs the bit index of the strobe. -- ------------------------------------------------------------ I_MSSAI_DETECTION : entity axi_datamover_v5_1.axi_datamover_ms_strb_set generic map ( C_STRB_WIDTH => STROBE_WIDTH , C_INDEX_WIDTH => C_INDEX_WIDTH ) port map ( -- Input Stream Strobes strbs_in => sig_strb_skid_mux_out , -- Index of the most significant strobe asserted ms_strb_index => sig_mssa_index_out , -- Output flag for a detected error associated Strobe assertions strb_error => sig_strb_error ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSSAI_REG -- -- Process Description: -- This process implements the output register for the -- Skid Buffer's MSSAI value and the strobe error bit -- that is needed by the Scatter module. -- ------------------------------------------------------------- IMP_MSSAI_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_mvalid_stop_reg = '1') then sig_mssa_index_reg_out <= (others => '0'); sig_strb_error_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_mssa_index_reg_out <= sig_mssa_index_out; sig_strb_error_reg_out <= sig_strb_error; else null; -- hold current state end if; end if; end process IMP_MSSAI_REG; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_wrdata_cntl.vhd

5

91465

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_wrdata_cntl.vhd -- -- Description: -- This file implements the DataMover Master Write Data Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_fifo; ------------------------------------------------------------------------------- entity axi_sg_wrdata_cntl is generic ( C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0; -- Indicates the Data Realignment function is included (external -- to this module) C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Indicates the INDET BTT function is included (external -- to this module) C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1; -- Sets the width of the data2wsc_bytes_rcvd port used for -- relaying the actual number of bytes received when Idet BTT is -- enabled (C_ENABLE_INDET_BTT = 1) C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the LS bits of the transfer address that -- are being used to Demux write data to a wider AXI4 Write -- Data Bus C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4; -- Sets the depth of the internal command fifo used for the -- command queue C_MMAP_DWIDTH : Integer range 32 to 1024 := 32; -- Indicates the native data width of the Read Data port C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Stream output data port C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Indicates the width of the Tag field of the input command C_FAMILY : String := "virtex7" -- Indicates the device family of the target FPGA ); port ( -- Clock and Reset inputs ---------------------------------------------- -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------------------ -- Soft Shutdown internal interface ------------------------------------ -- rst2data_stop_request : in std_logic; -- -- Active high soft stop request to modules -- -- data2addr_stop_req : Out std_logic; -- -- Active high signal requesting the Address Controller -- -- to stop posting commands to the AXI Read Address Channel -- -- data2rst_stop_cmplt : Out std_logic; -- -- Active high indication that the Data Controller has completed -- -- any pending transfers committed by the Address Controller -- -- after a stop has been requested by the Reset module. -- ------------------------------------------------------------------------ -- Store and Forward support signals for external User logic ------------ -- wr_xfer_cmplt : Out std_logic; -- -- Active high indication that the Data Controller has completed -- -- a single write data transfer on the AXI4 Write Data Channel. -- -- This signal is escentially echos the assertion of wlast sent -- -- to the AXI4. -- -- s2mm_ld_nxt_len : out std_logic; -- -- Active high pulse indicating a new xfer length has been queued -- -- to the WDC Cmd FIFO -- -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- -- Bus indicating the AXI LEN value associated with the xfer command -- -- loaded into the WDC Command FIFO. -- ------------------------------------------------------------------------- -- AXI Write Data Channel Skid buffer I/O --------------------------------------- -- data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- Write DATA output to skid buffer -- -- data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- Write DATA output to skid buffer -- -- data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- Write DATA output to skid buffer -- -- data2skid_wlast : Out std_logic; -- -- Write LAST output to skid buffer -- -- data2skid_wvalid : Out std_logic; -- -- Write VALID output to skid buffer -- -- skid2data_wready : In std_logic; -- -- Write READY input from skid buffer -- ---------------------------------------------------------------------------------- -- AXI Slave Stream In ----------------------------------------------------------- -- s2mm_strm_wvalid : In std_logic; -- -- AXI Stream VALID input -- -- s2mm_strm_wready : Out Std_logic; -- -- AXI Stream READY Output -- -- s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- AXI Stream data input -- -- s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- AXI Stream STRB input -- -- s2mm_strm_wlast : In std_logic; -- -- AXI Stream LAST input -- ---------------------------------------------------------------------------------- -- Stream input sideband signal from Indeterminate BTT and/or DRE ---------------- -- s2mm_strm_eop : In std_logic; -- -- Stream End of Packet marker input. This is only used when Indeterminate -- -- BTT mode is enable. Otherwise it is ignored -- -- -- s2mm_stbs_asserted : in std_logic_vector(7 downto 0); -- -- Indicates the number of asserted WSTRB bits for the -- -- associated input stream data beat -- -- -- -- Realigner Underrun/overrun error flag used in non Indeterminate BTT -- -- Mode -- realign2wdc_eop_error : In std_logic ; -- -- Asserted active high and will only clear with reset. It is only used -- -- when Indeterminate BTT is not enabled and the Realigner Module is -- -- instantiated upstream from the WDC. The Realigner will detect overrun -- -- underrun conditions and will will relay these conditions via this signal. -- ---------------------------------------------------------------------------------- -- Command Calculator Interface -------------------------------------------------- -- mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); -- -- The next command start address LSbs to use for the write strb -- -- demux (only used if Stream data width is less than the MMap Dwidth). -- -- mstr2data_len : In std_logic_vector(7 downto 0); -- -- The LEN value output to the Address Channel -- -- mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- The starting strobe value to use for the first stream data beat -- -- mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- The endiing (LAST) strobe value to use for the last stream -- -- data beat -- -- mstr2data_drr : In std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2data_eof : In std_logic; -- -- The endiing tranfer of a sequence of transfers -- -- mstr2data_sequential : In std_logic; -- -- The next sequential tranfer of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2data_calc_error : In std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2data_cmd_cmplt : In std_logic; -- -- The final child tranfer of a parent command fetched from -- -- the Command FIFO (not necessarily an EOF command) -- -- mstr2data_cmd_valid : In std_logic; -- -- The next command valid indication to the Data Channel -- -- Controller for the AXI MMap -- -- data2mstr_cmd_ready : Out std_logic ; -- -- Indication from the Data Channel Controller that the -- -- command is being accepted on the AXI Address -- -- Channel -- ---------------------------------------------------------------------------------- -- Address Controller Interface -------------------------------------------------- -- addr2data_addr_posted : In std_logic ; -- -- Indication from the Address Channel Controller to the -- -- Data Controller that an address has been posted to the -- -- AXI Address Channel -- -- -- data2addr_data_rdy : out std_logic; -- -- Indication that the Data Channel is ready to send the first -- -- databeat of the next command on the write data channel. -- -- This is used for the "wait for data" feature which keeps the -- -- address controller from issuing a transfer request until the -- -- corresponding data valid is asserted on the stream input. The -- -- WDC will continue to assert the output until an assertion on -- -- the addr2data_addr_posted is received. -- --------------------------------------------------------------------------------- -- Premature TLAST assertion error flag ------------------------------------------ -- data2all_tlast_error : Out std_logic; -- -- When asserted, this indicates the data controller detected -- -- a premature TLAST assertion on the incoming data stream. -- --------------------------------------------------------------------------------- -- Data Controller Halted Status ------------------------------------------------- -- data2all_dcntlr_halted : Out std_logic; -- -- When asserted, this indicates the data controller has satisfied -- -- all pending transfers queued by the Address Controller and is halted. -- ---------------------------------------------------------------------------------- -- Input Stream Skid Buffer Halt control ----------------------------------------- -- data2skid_halt : Out std_logic; -- -- The data controller asserts this output for 1 primary clock period -- -- The pulse commands the MM2S Stream skid buffer to tun off outputs -- -- at the next tlast transmission. -- ---------------------------------------------------------------------------------- -- Write Status Controller Interface --------------------------------------------- -- data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The command tag -- -- data2wsc_calc_err : Out std_logic ; -- -- Indication that the current command out from the Cntl FIFO -- -- has a calculation error -- -- data2wsc_last_err : Out std_logic ; -- -- Indication that the current write transfer encountered a premature -- -- TLAST assertion on the incoming Stream Channel -- -- data2wsc_cmd_cmplt : Out std_logic ; -- -- Indication by the Data Channel Controller that the -- -- corresponding status is the last status for a command -- -- pulled from the command FIFO -- -- wsc2data_ready : in std_logic; -- -- Input from the Write Status Module indicating that the -- -- Status Reg/FIFO is ready to accept data -- -- data2wsc_valid : Out std_logic; -- -- Output to the Command/Status Module indicating that the -- -- Data Controller has valid tag and err indicators to write -- -- to the Status module -- -- data2wsc_eop : Out std_logic; -- -- Output to the Write Status Controller indicating that the -- -- associated command status also corresponds to a End of Packet -- -- marker for the input Stream. This is only used when Inderminate -- -- BTT is enabled in the S2MM. -- -- data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); -- -- Output to the Write Status Controller indicating the actual -- -- number of bytes received from the Stream input for the -- -- corresponding command status. This is only used when Inderminate -- -- BTT is enabled in the S2MM. -- -- wsc2mstr_halt_pipe : In std_logic -- -- Indication to Halt the Data and Address Command pipeline due -- -- to the Status FIFO going full or an internal error being logged -- ---------------------------------------------------------------------------------- ); end entity axi_sg_wrdata_cntl; architecture implementation of axi_sg_wrdata_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function declaration ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_dbeat_residue_width -- -- Function Description: -- Calculates the number of Least significant bits of the BTT field -- that are unused for the LEN calculation -- ------------------------------------------------------------------- -- coverage off function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream begin case bytes_per_beat is when 128 => -- 1024 bits -- Added per Per CR616409 temp_dbeat_residue_width := 7; -- Added per Per CR616409 when 64 => -- 512 bits -- Added per Per CR616409 temp_dbeat_residue_width := 6; -- Added per Per CR616409 when 32 => -- 256 bits temp_dbeat_residue_width := 5; when 16 => -- 128 bits temp_dbeat_residue_width := 4; when 8 => -- 64 bits temp_dbeat_residue_width := 3; when 4 => -- 32 bits temp_dbeat_residue_width := 2; when 2 => -- 16 bits temp_dbeat_residue_width := 1; when others => -- assume 1-byte transfers temp_dbeat_residue_width := 0; end case; Return (temp_dbeat_residue_width); end function funct_get_dbeat_residue_width; -- coverage on ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_cnt_width -- -- Function Description: -- Sets a count width based on a fifo depth. A depth of 4 or less -- is a special case which requires a minimum count width of 3 bits. -- ------------------------------------------------------------------- function funct_set_cnt_width (fifo_depth : integer) return integer is Variable temp_cnt_width : Integer := 4; begin if (fifo_depth <= 4) then temp_cnt_width := 3; -- coverage off elsif (fifo_depth <= 8) then temp_cnt_width := 4; elsif (fifo_depth <= 16) then temp_cnt_width := 5; elsif (fifo_depth <= 32) then temp_cnt_width := 6; else -- fifo depth <= 64 temp_cnt_width := 7; end if; -- coverage on Return (temp_cnt_width); end function funct_set_cnt_width; -- Constant Declarations -------------------------------------------- Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8; Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0'); Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH; Constant LEN_WIDTH : integer := 8; Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; Constant DRR_WIDTH : integer := 1; Constant EOF_WIDTH : integer := 1; Constant CALC_ERR_WIDTH : integer := 1; Constant CMD_CMPLT_WIDTH : integer := 1; Constant SEQUENTIAL_WIDTH : integer := 1; Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field SADDR_LSB_WIDTH + -- LS Address field width LEN_WIDTH + -- LEN field STRB_WIDTH + -- Starting Strobe field STRB_WIDTH + -- Ending Strobe field DRR_WIDTH + -- DRE Re-alignment Request Flag Field EOF_WIDTH + -- EOF flag field SEQUENTIAL_WIDTH + -- Sequential command flag CMD_CMPLT_WIDTH + -- Command Complete Flag CALC_ERR_WIDTH; -- Calc error flag Constant TAG_STRT_INDEX : integer := 0; Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH; Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH; Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH; Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH; Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH; Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH; Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH; Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH; Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH; Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8; Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH); Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH); Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '1'); -- Signal Declarations -------------------------------------------- signal sig_get_next_dqual : std_logic := '0'; signal sig_last_mmap_dbeat : std_logic := '0'; signal sig_last_mmap_dbeat_reg : std_logic := '0'; signal sig_mmap2data_ready : std_logic := '0'; signal sig_data2mmap_valid : std_logic := '0'; signal sig_data2mmap_last : std_logic := '0'; signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_ld_new_cmd : std_logic := '0'; signal sig_ld_new_cmd_reg : std_logic := '0'; signal sig_cmd_cmplt_reg : std_logic := '0'; signal sig_calc_error_reg : std_logic := '0'; signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_posted : std_logic := '0'; signal sig_dqual_rdy : std_logic := '0'; signal sig_good_mmap_dbeat : std_logic := '0'; signal sig_first_dbeat : std_logic := '0'; signal sig_last_dbeat : std_logic := '0'; signal sig_single_dbeat : std_logic := '0'; signal sig_new_len_eq_0 : std_logic := '0'; signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0'); Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0; signal sig_dbeat_cntr_eq_0 : std_logic := '0'; signal sig_dbeat_cntr_eq_1 : std_logic := '0'; signal sig_wsc_ready : std_logic := '0'; signal sig_push_to_wsc : std_logic := '0'; signal sig_push_to_wsc_cmplt : std_logic := '0'; signal sig_set_push2wsc : std_logic := '0'; signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2wsc_calc_err : std_logic := '0'; signal sig_data2wsc_last_err : std_logic := '0'; signal sig_data2wsc_cmd_cmplt : std_logic := '0'; signal sig_tlast_error : std_logic := '0'; signal sig_tlast_error_strbs : std_logic := '0'; signal sig_end_stbs_match_err : std_logic := '0'; signal sig_tlast_error_reg : std_logic := '0'; signal sig_cmd_is_eof : std_logic := '0'; signal sig_push_err2wsc : std_logic := '0'; signal sig_tlast_error_ovrrun : std_logic := '0'; signal sig_tlast_error_undrrun : std_logic := '0'; signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_next_eof_reg : std_logic := '0'; signal sig_next_sequential_reg : std_logic := '0'; signal sig_next_cmd_cmplt_reg : std_logic := '0'; signal sig_next_calc_error_reg : std_logic := '0'; signal sig_pop_dqual_reg : std_logic := '0'; signal sig_push_dqual_reg : std_logic := '0'; signal sig_dqual_reg_empty : std_logic := '0'; signal sig_dqual_reg_full : std_logic := '0'; signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_posted_cntr_eq_0 : std_logic := '0'; signal sig_addr_posted_cntr_max : std_logic := '0'; signal sig_decr_addr_posted_cntr : std_logic := '0'; signal sig_incr_addr_posted_cntr : std_logic := '0'; signal sig_addr_posted_cntr_eq_1 : std_logic := '0'; signal sig_apc_going2zero : std_logic := '0'; signal sig_aposted_cntr_ready : std_logic := '0'; signal sig_addr_chan_rdy : std_logic := '0'; Signal sig_no_posted_cmds : std_logic := '0'; signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_ls_addr_cntr : std_logic := '0'; signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0'); Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_next_drr : std_logic := '0'; signal sig_fifo_next_eof : std_logic := '0'; signal sig_fifo_next_cmd_cmplt : std_logic := '0'; signal sig_fifo_next_sequential : std_logic := '0'; signal sig_fifo_next_calc_error : std_logic := '0'; signal sig_cmd_fifo_empty : std_logic := '0'; signal sig_fifo_wr_cmd_valid : std_logic := '0'; signal sig_fifo_wr_cmd_ready : std_logic := '0'; signal sig_fifo_rd_cmd_valid : std_logic := '0'; signal sig_fifo_rd_cmd_ready : std_logic := '0'; signal sig_sequential_push : std_logic := '0'; signal sig_clr_dqual_reg : std_logic := '0'; signal sig_tlast_err_stop : std_logic := '0'; signal sig_halt_reg : std_logic := '0'; signal sig_halt_reg_dly1 : std_logic := '0'; signal sig_halt_reg_dly2 : std_logic := '0'; signal sig_halt_reg_dly3 : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_stop_wvalid : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_s2mm_strm_wready : std_logic := '0'; signal sig_s2mm_strm_wready_del : std_logic := '0'; signal sig_good_strm_dbeat : std_logic := '0'; signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0'); signal sig_wfd_simult_clr_set : std_logic := '0'; signal sig_wr_xfer_cmplt : std_logic := '0'; signal sig_s2mm_ld_nxt_len : std_logic := '0'; signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_spcl_push_err2wsc : std_logic := '0'; begin --(architecture implementation) -- Command calculator handshake data2mstr_cmd_ready <= sig_data2mstr_cmd_ready; -- Write Data Channel Skid Buffer Port assignments sig_mmap2data_ready <= skid2data_wready ; data2skid_wvalid <= sig_data2mmap_valid ; data2skid_wlast <= sig_data2mmap_last ; data2skid_wdata <= sig_data2mmap_data ; data2skid_saddr_lsb <= sig_addr_lsb_reg ; -- AXI MM2S Stream Channel Port assignments sig_data2mmap_data <= s2mm_strm_wdata ; -- Premature TLAST assertion indication data2all_tlast_error <= sig_tlast_error_reg ; -- Stream Input Ready Handshake s2mm_strm_wready <= sig_s2mm_strm_wready ; sig_good_strm_dbeat <= s2mm_strm_wvalid and sig_s2mm_strm_wready; -- sig_s2mm_strm_wready_del; sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and sig_dqual_rdy; -- Write Status Block interface signals data2wsc_valid <= sig_push_to_wsc and not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror sig_wsc_ready <= wsc2data_ready ; data2wsc_tag <= sig_data2wsc_tag ; data2wsc_calc_err <= sig_data2wsc_calc_err ; data2wsc_last_err <= sig_data2wsc_last_err ; data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ; -- Address Channel Controller synchro pulse input sig_addr_posted <= addr2data_addr_posted; -- Request to halt the Address Channel Controller data2addr_stop_req <= sig_halt_reg or sig_tlast_error_reg; -- Halted flag to the reset module data2rst_stop_cmplt <= sig_data2rst_stop_cmplt; -- Indicate the Write Data Controller is always ready data2addr_data_rdy <= '1'; -- Write Transfer Completed Status output wr_xfer_cmplt <= sig_wr_xfer_cmplt ; -- New LEN value is being loaded s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len; -- The new LEN value s2mm_wr_len <= sig_s2mm_wr_len; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_CMPLT_FLAG -- -- Process Description: -- Implements the status flag indicating that a write data -- transfer has completed. This is an echo of a wlast assertion -- and a qualified data beat on the AXI4 Write Data Channel. -- ------------------------------------------------------------- IMP_WR_CMPLT_FLAG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wr_xfer_cmplt <= '0'; sig_s2mm_strm_wready_del <= '0'; else sig_wr_xfer_cmplt <= sig_data2mmap_last and sig_good_strm_dbeat; sig_s2mm_strm_wready_del <= sig_s2mm_strm_wready; end if; end if; end process IMP_WR_CMPLT_FLAG; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Omits any Indeterminate BTT Support logic and includes -- any error detection needed in Non Indeterminate BTT mode. -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate begin sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb; -- Just housekeep the output port signals data2wsc_eop <= '0'; data2wsc_bytes_rcvd <= (others => '0'); -- WRSTRB logic ------------------------------ -- Generate the Write Strobes for the MMap Write Data Channel -- for the non Indeterminate BTT Case data2skid_wstrb <= (others => '1') when mmap_reset = '0' else (others => '0'); --sig_strt_strb_reg -- data2skid_wstrb <= sig_strt_strb_reg -- When (sig_first_dbeat = '1') -- Else sig_last_strb_reg -- When (sig_last_dbeat = '1') -- Else (others => '1'); -- Generate the Stream Ready for the Stream input side sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested (sig_mmap2data_ready and sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path sig_dqual_rdy and not(sig_calc_error_reg) and not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection -- MMap Write Data Channel Valid Handshaking sig_data2mmap_valid <= (s2mm_strm_wvalid or sig_tlast_error_reg or -- force valid if TLAST error sig_halt_reg ) and -- force valid if halt requested sig_addr_chan_rdy and -- xfers are commited on the address channel and sig_dqual_rdy and -- there are commands in the command fifo not(sig_calc_error_reg) and not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk -- or when the soft shutdown has completed ------------------------------------------------------------ -- If Generate -- -- Label: GEN_LOCAL_ERR_DETECT -- -- If Generate Description: -- Implements the local overrun and underrun detection when -- the S2MM Realigner is not included. -- -- ------------------------------------------------------------ GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate begin ------- Input Stream TLAST assertion error ------------------------------- sig_tlast_error_ovrrun <= sig_cmd_is_eof and sig_dbeat_cntr_eq_0 and sig_good_mmap_dbeat and not(s2mm_strm_wlast); sig_tlast_error_undrrun <= s2mm_strm_wlast and sig_good_mmap_dbeat and (not(sig_dbeat_cntr_eq_0) or not(sig_cmd_is_eof)); sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value (s2mm_strm_wlast = '1') and -- at TLAST assertion (sig_good_mmap_dbeat = '1')) -- Qualified databeat Else '0'; sig_tlast_error <= (sig_tlast_error_ovrrun or sig_tlast_error_undrrun or sig_end_stbs_match_err) and not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown -- Just housekeep this when local TLAST error detection is used sig_spcl_push_err2wsc <= '0'; end generate GEN_LOCAL_ERR_DETECT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_EXTERN_ERR_DETECT -- -- If Generate Description: -- Omits the local overrun and underrun detection and relies -- on the S2MM Realigner for the detection. -- ------------------------------------------------------------ GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate begin sig_tlast_error_undrrun <= '0'; -- not used here sig_tlast_error_ovrrun <= '0'; -- not used here sig_end_stbs_match_err <= '0'; -- not used here sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown -- Special case for pushing error status when timing is such that no -- addresses have been posted to AXI and a TLAST error has been detected -- by the Realigner module and propagated in from the Stream input side. sig_spcl_push_err2wsc <= sig_tlast_error_reg and not(sig_tlast_err_stop) and not(sig_addr_chan_rdy ); end generate GEN_EXTERN_ERR_DETECT; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERR_REG -- -- Process Description: -- Implements a sample and hold flop for the flag indicating -- that the input Stream TLAST assertion was not at the expected -- data beat relative to the commanded number of databeats -- from the associated command from the SCC or PCC. ------------------------------------------------------------- IMP_TLAST_ERR_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_tlast_error_reg <= '0'; -- coverage off elsif (sig_tlast_error = '1') then sig_tlast_error_reg <= '1'; -- coverage on else null; -- hold current state end if; end if; end process IMP_TLAST_ERR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERROR_STOP -- -- Process Description: -- Implements the flop to generate a stop flag once the TLAST -- error condition has been relayed to the Write Status -- Controller. This stop flag is used to prevent any more -- pushes to the Write Status Controller. -- ------------------------------------------------------------- IMP_TLAST_ERROR_STOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_tlast_err_stop <= '0'; -- coverage off elsif (sig_tlast_error_reg = '1' and sig_push_to_wsc_cmplt = '1') then sig_tlast_err_stop <= '1'; -- coverage on else null; -- Hold State end if; end if; end process IMP_TLAST_ERROR_STOP; end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INDET_BTT -- -- If Generate Description: -- Includes any Indeterminate BTT Support logic. Primarily -- this is a counter for the input stream bytes received. The -- received byte count is relayed to the Write Status Controller -- for each parent command completed. -- When a packet completion is indicated via the EOP marker -- assertion, the status to the Write Status Controller also -- indicates the EOP condition. -- Note that underrun and overrun detection/error flagging -- is disabled in Indeterminate BTT Mode. -- ------------------------------------------------------------ -- GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate -- -- -- local constants -- Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH; -- Constant NUM_ZEROS_WIDTH : integer := 8; -- Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8; -- Constant STRBGEN_ADDR_SLICE_WIDTH : integer := -- funct_get_dbeat_residue_width(BYTES_PER_DBEAT); -- -- Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); -- -- -- -- -- local signals -- signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0'); -- signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0'); -- signal lsig_ld_byte_cntr : std_logic := '0'; -- signal lsig_incr_byte_cntr : std_logic := '0'; -- signal lsig_clr_byte_cntr : std_logic := '0'; -- signal lsig_end_of_cmd_reg : std_logic := '0'; -- signal lsig_eop_s_h_reg : std_logic := '0'; -- signal lsig_eop_reg : std_logic := '0'; -- signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0'); -- signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0'); -- -- -- -- -- begin -- -- -- -- Assign the outputs to the Write Status Controller -- data2wsc_eop <= lsig_eop_reg and -- not(sig_next_calc_error_reg); -- -- data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr); -- -- -- -- -- WRSTRB logic ------------------------------ -- -- -- -- --sig_strbgen_bytes <= (others => '1'); -- set to the max value -- -- -- -- set the length to the max number of bytes per databeat -- sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1)); -- -- -- -- -- -- -- sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb), -- STRBGEN_ADDR_SLICE_WIDTH)) ; -- -- -- -- -- ------------------------------------------------------------ -- -- Instance: I_STRT_STRB_GEN -- -- -- -- Description: -- -- Strobe generator used to generate the starting databeat -- -- strobe value for soft shutdown case where the S2MM has to -- -- flush out all of the transfers that have been committed -- -- to the AXI Write address channel. Starting Strobes must -- -- match the committed address offest for each transfer. -- -- -- ------------------------------------------------------------ -- I_STRT_STRB_GEN : entity axi_sg_v4_1.axi_sg_strb_gen2 -- generic map ( -- -- C_OP_MODE => 0 , -- 0 = Offset/Length mode -- C_STRB_WIDTH => BYTES_PER_DBEAT , -- C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH , -- C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1 -- -- ) -- port map ( -- -- start_addr_offset => sig_strbgen_addr , -- end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0 -- num_valid_bytes => sig_strbgen_bytes , -- strb_out => sig_sfhalt_next_strt_strb -- -- ); -- -- -- -- -- -- -- -- -- Generate the WSTRB to use during soft shutdown -- sig_halt_strb <= sig_strt_strb_reg -- When (sig_first_dbeat = '1' or -- sig_single_dbeat = '1') -- Else (others => '1'); -- -- -- -- -- Generate the Write Strobes for the MMap Write Data Channel -- -- for the Indeterminate BTT case. Strobes come from the Stream -- -- input from the Indeterminate BTT module during normal operation. -- -- However, during soft shutdown, those strobes become unpredictable -- -- so generated strobes have to be used. -- data2skid_wstrb <= sig_halt_strb -- When (sig_halt_reg = '1') -- -- Else s2mm_strm_wstrb; -- -- -- -- -- Generate the Stream Ready for the Stream input side -- sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested -- (sig_mmap2data_ready and -- MMap is accepting the xfers -- sig_addr_chan_rdy and -- xfers are commited on the address channel and -- sig_dqual_rdy and -- there are commands in the command fifo -- not(sig_calc_error_reg) and -- No internal error -- not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk -- -- or when the soft shutdown has completed -- -- -- -- MMap Write Data Channel Valid Handshaking -- sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid -- sig_halt_reg ) and -- force valid if halt requested -- sig_addr_chan_rdy and -- xfers are commited on the address channel and -- sig_dqual_rdy and -- there are commands in the command fifo -- not(sig_calc_error_reg) and -- No internal error -- not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk -- -- or when the soft shutdown has completed -- -- -- -- -- TLAST Error housekeeping for Indeterminate BTT Mode -- -- There is no Underrun/overrun in Stroe and Forward mode -- -- sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT -- sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT -- sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT -- sig_tlast_error <= '0'; -- Not used with Indeterminate BTT -- sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT -- sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT -- -- -- -- -- -- ------------------------------------------------------------- -- -- Synchronous Process with Sync Reset -- -- -- -- Label: IMP_EOP_REG_FLOP -- -- -- -- Process Description: -- -- Register the End of Packet marker. -- -- -- ------------------------------------------------------------- -- IMP_EOP_REG_FLOP : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- if (mmap_reset = '1') then -- -- lsig_end_of_cmd_reg <= '0'; -- lsig_eop_reg <= '0'; -- -- -- Elsif (sig_good_strm_dbeat = '1') Then -- -- -- lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and -- s2mm_strm_wlast; -- -- lsig_eop_reg <= s2mm_strm_eop; -- -- else -- -- null; -- hold current state -- -- end if; -- end if; -- end process IMP_EOP_REG_FLOP; -- -- -- -- -- -- ----- Byte Counter Logic ----------------------------------------------- -- -- The Byte counter reflects the actual byte count received on the -- -- Stream input for each parent command loaded into the S2MM command -- -- FIFO. Thus it counts input bytes until the command complete qualifier -- -- is set and the TLAST input from the Stream input. -- -- -- lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start -- not(sig_good_strm_dbeat); -- immediately after the previous one finished. -- -- -- lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts -- sig_good_strm_dbeat; -- immediately after the previous one finished. -- -- lsig_incr_byte_cntr <= sig_good_strm_dbeat; -- -- -- lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted), -- BYTE_CNTR_WIDTH); -- -- ------------------------------------------------------------- -- -- Synchronous Process with Sync Reset -- -- -- -- Label: IMP_BYTE_CMTR -- -- -- -- Process Description: -- -- Keeps a running byte count per burst packet loaded into the -- -- xfer FIFO. It is based on the strobes set on the incoming -- -- Stream dbeat. -- -- -- ------------------------------------------------------------- -- IMP_BYTE_CMTR : process (primary_aclk) -- begin -- if (primary_aclk'event and primary_aclk = '1') then -- if (mmap_reset = '1' or -- lsig_clr_byte_cntr = '1') then -- -- lsig_byte_cntr <= (others => '0'); -- -- elsif (lsig_ld_byte_cntr = '1') then -- -- lsig_byte_cntr <= lsig_byte_cntr_incr_value; -- -- elsif (lsig_incr_byte_cntr = '1') then -- -- lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value; -- -- else -- null; -- hold current value -- end if; -- end if; -- end process IMP_BYTE_CMTR; -- -- -- -- -- -- end generate GEN_INDET_BTT; -- -- Internal logic ------------------------------ sig_good_mmap_dbeat <= sig_mmap2data_ready and sig_data2mmap_valid; sig_last_mmap_dbeat <= sig_good_mmap_dbeat and sig_data2mmap_last; sig_get_next_dqual <= sig_last_mmap_dbeat; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_LAST_DBEAT -- -- Process Description: -- This implements a FLOP that creates a pulse -- indicating the LAST signal for an outgoing write data channel -- has been sent. Note that it is possible to have back to -- back LAST databeats. -- ------------------------------------------------------------- REG_LAST_DBEAT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_last_mmap_dbeat_reg <= '0'; else sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat; end if; end if; end process REG_LAST_DBEAT; ----- Write Status Interface Stuff -------------------------- sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready; sig_set_push2wsc <= (sig_good_mmap_dbeat and sig_dbeat_cntr_eq_0) or sig_push_err2wsc or sig_spcl_push_err2wsc; -- Special case from CR616212 ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_INTERR_PUSH_FLOP -- -- Process Description: -- Generate a 1 clock wide pulse when a calc error has propagated -- from the Command Calculator. This pulse is used to force a -- push of the error status to the Write Status Controller -- without a AXI transfer completion. -- ------------------------------------------------------------- IMP_INTERR_PUSH_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_push_err2wsc = '1') then sig_push_err2wsc <= '0'; elsif (sig_ld_new_cmd_reg = '1' and sig_calc_error_reg = '1') then sig_push_err2wsc <= '1'; else null; -- hold state end if; end if; end process IMP_INTERR_PUSH_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSH2WSC_FLOP -- -- Process Description: -- Implements a Sample and hold register for the outbound status -- signals to the Write Status Controller (WSC). This register -- has to support back to back transfer completions. -- ------------------------------------------------------------- IMP_PUSH2WSC_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or (sig_push_to_wsc_cmplt = '1' and sig_set_push2wsc = '0')) then sig_push_to_wsc <= '0'; sig_data2wsc_tag <= (others => '0'); sig_data2wsc_calc_err <= '0'; sig_data2wsc_last_err <= '0'; sig_data2wsc_cmd_cmplt <= '0'; elsif (sig_set_push2wsc = '1' and sig_tlast_err_stop = '0') then sig_push_to_wsc <= '1'; sig_data2wsc_tag <= sig_tag_reg ; sig_data2wsc_calc_err <= sig_calc_error_reg ; sig_data2wsc_last_err <= sig_tlast_error_reg or sig_tlast_error ; sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or sig_tlast_error_reg or sig_tlast_error ; else null; -- hold current state end if; end if; end process IMP_PUSH2WSC_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_LD_NEW_CMD_REG -- -- Process Description: -- Registers the flag indicating a new command has been -- loaded. Needs to be a 1 clk wide pulse. -- ------------------------------------------------------------- IMP_LD_NEW_CMD_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_ld_new_cmd_reg = '1') then sig_ld_new_cmd_reg <= '0'; else sig_ld_new_cmd_reg <= sig_ld_new_cmd; end if; end if; end process IMP_LD_NEW_CMD_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_NXT_LEN_REG -- -- Process Description: -- Registers the load control and length value for a command -- passed to the WDC input command interface. The registered -- signals are used for the external Indeterminate BTT support -- ports. -- ------------------------------------------------------------- IMP_NXT_LEN_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_s2mm_ld_nxt_len <= '0'; sig_s2mm_wr_len <= (others => '0'); else sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and sig_data2mstr_cmd_ready; sig_s2mm_wr_len <= mstr2data_len; end if; end if; end process IMP_NXT_LEN_REG; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_DATA_CNTL_FIFO -- -- If Generate Description: -- Omits the input data control FIFO if the requested FIFO -- depth is 1. The Data Qualifier Register serves as a -- 1 deep FIFO by itself. -- ------------------------------------------------------------ GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate begin -- Command Calculator Handshake output sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ; -- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and -- pre 13.1 sig_aposted_cntr_ready and -- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling -- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is -- pre 13.1 -- no calculation error being propagated sig_fifo_wr_cmd_ready <= sig_push_dqual_reg; sig_fifo_next_tag <= mstr2data_tag ; sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ; sig_fifo_next_len <= mstr2data_len ; sig_fifo_next_strt_strb <= mstr2data_strt_strb ; sig_fifo_next_last_strb <= mstr2data_last_strb ; sig_fifo_next_drr <= mstr2data_drr ; sig_fifo_next_eof <= mstr2data_eof ; sig_fifo_next_sequential <= mstr2data_sequential ; sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ; sig_fifo_next_calc_error <= mstr2data_calc_error ; end generate GEN_NO_DATA_CNTL_FIFO; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_DATA_CNTL_FIFO -- -- If Generate Description: -- Includes the input data control FIFO if the requested -- FIFO depth is more than 1. -- ------------------------------------------------------------ GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate begin -- Command Calculator Handshake output sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ; -- pop the fifo when dqual reg is pushed sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- Format the input fifo data word sig_cmd_fifo_data_in <= mstr2data_calc_error & mstr2data_cmd_cmplt & mstr2data_sequential & mstr2data_eof & mstr2data_drr & mstr2data_last_strb & mstr2data_strt_strb & mstr2data_len & mstr2data_saddr_lsb & mstr2data_tag ; -- Rip the output fifo data word sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX); sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto SADDR_LSB_STRT_INDEX); sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto LEN_STRT_INDEX); sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto STRT_STRB_STRT_INDEX); sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto LAST_STRB_STRT_INDEX); sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX); sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX); sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX); sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX); sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX); ------------------------------------------------------------ -- Instance: I_DATA_CNTL_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO -- ------------------------------------------------------------ I_DATA_CNTL_FIFO : entity axi_sg_v4_1.axi_sg_fifo generic map ( C_DWIDTH => DCTL_FIFO_WIDTH , C_DEPTH => C_DATA_CNTL_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_fifo_wr_cmd_valid , fifo_wr_tready => sig_fifo_wr_cmd_ready , fifo_wr_tdata => sig_cmd_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_fifo_rd_cmd_valid , fifo_rd_tready => sig_fifo_rd_cmd_ready , fifo_rd_tdata => sig_cmd_fifo_data_out , fifo_rd_empty => sig_cmd_fifo_empty ); end generate GEN_DATA_CNTL_FIFO; -- Data Qualifier Register ------------------------------------ sig_ld_new_cmd <= sig_push_dqual_reg ; sig_dqual_rdy <= sig_dqual_reg_full ; sig_strt_strb_reg <= sig_next_strt_strb_reg ; sig_last_strb_reg <= sig_next_last_strb_reg ; sig_tag_reg <= sig_next_tag_reg ; sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ; sig_calc_error_reg <= sig_next_calc_error_reg ; sig_cmd_is_eof <= sig_next_eof_reg ; -- new for no bubbles between child requests sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified sig_last_dbeat and -- last data beat of transfer sig_next_sequential_reg;-- next queued command is sequential -- to the current command -- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or -- pre 13.1 sig_dqual_reg_empty) and -- pre 13.1 sig_fifo_rd_cmd_valid and -- pre 13.1 sig_aposted_cntr_ready and -- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not -- pre 13.1 -- stalling the command execution pipe sig_push_dqual_reg <= (sig_sequential_push or sig_dqual_reg_empty) and sig_fifo_rd_cmd_valid and sig_aposted_cntr_ready and not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not -- stalling the command execution pipe sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and sig_get_next_dqual and sig_dqual_reg_full ; -- new for no bubbles between child requests sig_clr_dqual_reg <= mmap_reset or (sig_pop_dqual_reg and not(sig_push_dqual_reg)); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DQUAL_REG -- -- Process Description: -- This process implements a register for the Data -- Control and qualifiers. It operates like a 1 deep Sync FIFO. -- ------------------------------------------------------------- IMP_DQUAL_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (sig_clr_dqual_reg = '1') then sig_next_tag_reg <= (others => '0'); sig_next_strt_strb_reg <= (others => '0'); sig_next_last_strb_reg <= (others => '0'); sig_next_eof_reg <= '0' ; sig_next_sequential_reg <= '0' ; sig_next_cmd_cmplt_reg <= '0' ; sig_next_calc_error_reg <= '0' ; sig_dqual_reg_empty <= '1' ; sig_dqual_reg_full <= '0' ; elsif (sig_push_dqual_reg = '1') then sig_next_tag_reg <= sig_fifo_next_tag ; sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ; sig_next_last_strb_reg <= sig_fifo_next_last_strb ; sig_next_eof_reg <= sig_fifo_next_eof ; sig_next_sequential_reg <= sig_fifo_next_sequential ; sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ; sig_next_calc_error_reg <= sig_fifo_next_calc_error ; sig_dqual_reg_empty <= '0'; sig_dqual_reg_full <= '1'; else null; -- don't change state end if; end if; end process IMP_DQUAL_REG; -- Address LS Cntr logic -------------------------- sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr); sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH); sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_ADDR_LSB_CNTR -- -- Process Description: -- Implements the LS Address Counter used for controlling -- the Write STRB DeMux during Burst transfers -- ------------------------------------------------------------- DO_ADDR_LSB_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or (sig_pop_dqual_reg = '1'and sig_push_dqual_reg = '0')) then -- Clear the Counter sig_ls_addr_cntr <= (others => '0'); elsif (sig_push_dqual_reg = '1') then -- Load the Counter sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb); elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd; else null; -- Hold Current value end if; end if; end process DO_ADDR_LSB_CNTR; -- Address Posted Counter Logic -------------------------------------- sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or sig_apc_going2zero) ; -- Gates data channel xfer handshake sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted sig_incr_addr_posted_cntr <= sig_addr_posted ; sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ; sig_addr_posted_cntr_eq_0 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ZERO) Else '0'; sig_addr_posted_cntr_max <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_MAX) Else '0'; sig_addr_posted_cntr_eq_1 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ONE) Else '0'; sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and sig_decr_addr_posted_cntr and not(sig_incr_addr_posted_cntr); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_POSTED_FIFO_CNTR -- -- Process Description: -- This process implements a counter for the tracking -- if an Address has been posted on the AXI address channel. -- The Data Controller must wait for an address to be posted -- before proceeding with the corresponding data transfer on -- the Data Channel. The counter is also used to track flushing -- operations where all transfers commited on the AXI Address -- Channel have to be completed before a halt can occur. ------------------------------------------------------------- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_addr_posted_cntr <= ADDR_POSTED_ZERO; elsif (sig_incr_addr_posted_cntr = '1' and sig_decr_addr_posted_cntr = '0' and sig_addr_posted_cntr_max = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ; elsif (sig_incr_addr_posted_cntr = '0' and sig_decr_addr_posted_cntr = '1' and sig_addr_posted_cntr_eq_0 = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ; else null; -- don't change state end if; end if; end process IMP_ADDR_POSTED_FIFO_CNTR; ------- First/Middle/Last Dbeat detimination ------------------- sig_new_len_eq_0 <= '1' When (sig_fifo_next_len = LEN_OF_ZERO) else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_FIRST_MID_LAST -- -- Process Description: -- Implements the detection of the First/Mid/Last databeat of -- a transfer. -- ------------------------------------------------------------- DO_FIRST_MID_LAST : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_first_dbeat <= '0'; sig_last_dbeat <= '0'; sig_single_dbeat <= '0'; elsif (sig_ld_new_cmd = '1') then sig_first_dbeat <= not(sig_new_len_eq_0); sig_last_dbeat <= sig_new_len_eq_0; sig_single_dbeat <= sig_new_len_eq_0; Elsif (sig_dbeat_cntr_eq_1 = '1' and sig_good_mmap_dbeat = '1') Then sig_first_dbeat <= '0'; sig_last_dbeat <= '1'; sig_single_dbeat <= '0'; Elsif (sig_dbeat_cntr_eq_0 = '0' and sig_dbeat_cntr_eq_1 = '0' and sig_good_mmap_dbeat = '1') Then sig_first_dbeat <= '0'; sig_last_dbeat <= '0'; sig_single_dbeat <= '0'; else null; -- hold current state end if; end if; end process DO_FIRST_MID_LAST; ------- Data Controller Halted Indication ------------------------------- data2all_dcntlr_halted <= sig_no_posted_cmds or sig_calc_error_reg; ------- Data Beat counter logic ------------------------------- sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr); sig_dbeat_cntr_eq_0 <= '1' when (sig_dbeat_cntr_int = 0) Else '0'; sig_dbeat_cntr_eq_1 <= '1' when (sig_dbeat_cntr_int = 1) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DO_DBEAT_CNTR -- -- Process Description: -- Implements the transfer data beat counter used to track -- progress of the transfer. -- ------------------------------------------------------------- DO_DBEAT_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_dbeat_cntr <= (others => '0'); elsif (sig_ld_new_cmd = '1') then sig_dbeat_cntr <= unsigned(sig_fifo_next_len); Elsif (sig_good_mmap_dbeat = '1' and sig_dbeat_cntr_eq_0 = '0') Then sig_dbeat_cntr <= sig_dbeat_cntr-1; else null; -- Hold current state end if; end if; end process DO_DBEAT_CNTR; ------- Soft Shutdown Logic ------------------------------- -- Formulate the soft shutdown complete flag sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown sig_no_posted_cmds and not(sig_calc_error_reg)) or (sig_halt_reg_dly3 and -- Shutdown after error trap sig_calc_error_reg); -- Generate a gate signal to deassert the WVALID output -- for 1 clock cycle after a WLAST is issued. This only -- occurs when in soft shutdown mode. sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and sig_halt_reg) or sig_data2rst_stop_cmplt; -- Assign the output port skid buf control for the -- input Stream skid buffer data2skid_halt <= sig_data2skid_halt; -- Create a 1 clock wide pulse to tell the input -- stream skid buffer to shut down. sig_data2skid_halt <= sig_halt_reg_dly2 and not(sig_halt_reg_dly3); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG -- -- Process Description: -- Implements the flop for capturing the Halt request from -- the Reset module. -- ------------------------------------------------------------- IMP_HALT_REQ_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg <= '0'; elsif (rst2data_stop_request = '1') then sig_halt_reg <= '1'; else null; -- Hold current State end if; end if; end process IMP_HALT_REQ_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG_DLY -- -- Process Description: -- Implements the flops for delaying the halt request by 3 -- clocks to allow the Address Controller to halt before the -- Data Contoller can safely indicate it has exhausted all -- transfers committed to the AXI Address Channel by the Address -- Controller. -- ------------------------------------------------------------- IMP_HALT_REQ_REG_DLY : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg_dly1 <= '0'; sig_halt_reg_dly2 <= '0'; sig_halt_reg_dly3 <= '0'; else sig_halt_reg_dly1 <= sig_halt_reg; sig_halt_reg_dly2 <= sig_halt_reg_dly1; sig_halt_reg_dly3 <= sig_halt_reg_dly2; end if; end if; end process IMP_HALT_REQ_REG_DLY; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_slice.vhd

19

4781

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; entity axi_datamover_slice is generic ( C_DATA_WIDTH : Integer range 1 to 200 := 64 ); port ( ACLK : in std_logic; ARESET : in std_logic; -- Slave side S_PAYLOAD_DATA : in std_logic_vector (C_DATA_WIDTH-1 downto 0); S_VALID : in std_logic; S_READY : out std_logic; -- Master side M_PAYLOAD_DATA : out std_logic_vector (C_DATA_WIDTH-1 downto 0); M_VALID : out std_logic; M_READY : in std_logic ); end entity axi_datamover_slice; architecture working of axi_datamover_slice is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of working : architecture is "yes"; signal storage_data : std_logic_vector (C_DATA_WIDTH-1 downto 0); signal s_ready_i : std_logic; signal m_valid_i : std_logic; signal areset_d : std_logic_vector (1 downto 0); begin -- assign local signal to its output signal S_READY <= s_ready_i; M_VALID <= m_valid_i; process (ACLK) begin if (ACLK'event and ACLK = '1') then areset_d(0) <= ARESET; areset_d(1) <= areset_d(0); end if; end process; -- Save payload data whenever we have a transaction on the slave side process (ACLK) begin if (ACLK'event and ACLK = '1') then if (S_VALID = '1' and s_ready_i = '1') then storage_data <= S_PAYLOAD_DATA; else storage_data <= storage_data; end if; end if; end process; M_PAYLOAD_DATA <= storage_data; -- M_Valid set to high when we have a completed transfer on slave side -- Is removed on a M_READY except if we have a new transfer on the slave side process (ACLK) begin if (ACLK'event and ACLK = '1') then if (areset_d (1) = '1') then m_valid_i <= '0'; elsif (S_VALID = '1') then m_valid_i <= '1'; elsif (M_READY = '1') then m_valid_i <= '0'; else m_valid_i <= m_valid_i; end if; end if; end process; -- Slave Ready is either when Master side drives M_Ready or we have space in our storage data s_ready_i <= (M_READY or (not m_valid_i)) and not (areset_d(1) or areset_d(0)); end working;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/0535f152/hdl/src/vhdl/axi_sg_updt_noqueue.vhd

3

30514

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_noqueue.vhd -- Description: This entity provides the descriptor update for the No Queue mode -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_sg_v4_1; use axi_sg_v4_1.axi_sg_pkg.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 -- 1 IOC bit + 32 Update Status Bits ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- updt2_active : in std_logic ; -- updt2_queue_empty : out std_logic ; -- updt2_ioc : out std_logic ; -- updt2_ioc_irq_set : in std_logic ; -- -- dma2_interr : out std_logic ; -- dma2_slverr : out std_logic ; -- dma2_decerr : out std_logic ; -- dma2_interr_set : in std_logic ; -- dma2_slverr_set : in std_logic ; -- dma2_decerr_set : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface In **-- -- --*********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- -- Update Pointer Stream -- s_axis2_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis2_updtptr_tvalid : in std_logic ; -- s_axis2_updtptr_tready : out std_logic ; -- s_axis2_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis2_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis2_updtsts_tvalid : in std_logic ; -- s_axis2_updtsts_tready : out std_logic ; -- s_axis2_updtsts_tlast : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface Out**-- -- --*********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Contstants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal writing_curdesc : std_logic := '0'; signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; signal writing_status : std_logic := '0'; signal curdesc_tready : std_logic := '0'; signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; signal writing_status_re_ch1 : std_logic := '0'; signal writing_status_re_ch2 : std_logic := '0'; signal updt_active_int : std_logic := '0'; signal s_axis_updtptr_tvalid_int : std_logic := '0'; signal s_axis_updtsts_tvalid_int : std_logic := '0'; signal s_axis_updtsts_tlast_int : std_logic := '0'; signal s_axis_updtptr_tdata_int : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0'); signal s_axis_qual : std_logic := '0'; signal s_axis2_qual : std_logic := '0'; signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); -- signal m_axis_updt_tlast_mm2s : std_logic ; -- signal m_axis_updt_tvalid_mm2s : std_logic ; signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); -- signal m_axis_updt_tlast_s2mm : std_logic ; -- signal m_axis_updt_tvalid_s2mm : std_logic ; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else m_axis_updt_tdata_s2mm; m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else m_axis_updt_tvalid_s2mm; m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else m_axis_updt_tlast_s2mm; updt_active_int <= updt_active or updt2_active; s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid; s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid; s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast; s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active; s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active; -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- the channel REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active or updt2_active; end if; end if; end process REG_ACTIVE; updt_active_re <= (updt_active or updt2_active) and not updt_active_d1; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active_int, s_axis_updtptr_tvalid_int, updt_active, updt2_active, s_axis_qual, s_axis2_qual, s_axis_updtptr_tvalid, s_axis2_updtptr_tvalid, s_axis_updtsts_tvalid_int, m_axis_updt_tready) begin write_curdesc_lsb <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; writing_curdesc <= '0'; curdesc_tready <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or (s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then writing_curdesc <= '1'; pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor when READ_CURDESC_LSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then write_curdesc_lsb <= '1'; -- pntr_ns <= READ_CURDESC_MSB; pntr_ns <= WRITE_STATUS; else -- coverage off pntr_ns <= READ_CURDESC_LSB; -- coverage on end if; -- coverage off --------------------------------------------------------------- -- Get upper current descriptor when READ_CURDESC_MSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. if(s_axis_updtptr_tvalid_int = '1')then write_curdesc_msb <= '1'; pntr_ns <= WRITE_STATUS; else pntr_ns <= READ_CURDESC_MSB; end if; -- coverage on --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => writing_status <= '1'; --s_axis_updtsts_tvalid_int; if((s_axis_qual = '1' and m_axis_updt_tready = '1') or (s_axis2_qual = '1' and m_axis_updt_tready = '1')) then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; -- coverage off when others => pntr_ns <= IDLE; -- coverage on end case; end process CURDESC_PNTR_STATE; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; -- Status stream signals m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status; m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status; s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active; -- Pointer stream signals s_axis_updtptr_tready <= curdesc_tready and updt_active; -- Indicate need for channel service for update state machine updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status); m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status; m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status; s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active; -- Pointer stream signals s_axis2_updtptr_tready <= curdesc_tready and updt2_active; -- Indicate need for channel service for update state machine updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status); --********************************************************************* --** POINTER CAPTURE LOGIC --********************************************************************* s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else s_axis2_updtptr_tdata; --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1')then updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1')then updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_lsb = '1')then -- elsif(write_curdesc_msb = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --********************************************************************* --** ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; writing_status_re_ch1 <= writing_status_re and updt_active; writing_status_re_ch2 <= writing_status_re and updt2_active; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re_ch1 = '1')then updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re_ch1 = '1')then dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG2_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then updt2_ioc <= '0'; elsif(writing_status_re_ch2 = '1')then updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG2_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then dma2_interr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE2_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then dma2_slverr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE2_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then dma2_decerr <= '0'; elsif(writing_status_re_ch2 = '1')then dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE2_DMADEC_ERROR; end implementation;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s05/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/axi_cdma_v4_1/25515467/hdl/src/vhdl/axi_cdma_sfifo_autord.vhd

1

19630

------------------------------------------------------------------------------- -- axi_cdma_sfifo_autord.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_cdma_sfifo_autord.vhd -- Version: initial -- Description: -- This file contains the logic to generate a CoreGen call to create a -- synchronous FIFO as part of the synthesis process of XST. This eliminates -- the need for multiple fixed netlists for various sizes and widths of FIFOs. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library lib_fifo_v1_0; use lib_fifo_v1_0.sync_fifo_fg; ------------------------------------------------------------------------------- entity axi_cdma_sfifo_autord is generic ( C_DWIDTH : integer := 32; C_DEPTH : integer := 128; C_DATA_CNT_WIDTH : integer := 8; C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0; C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0; C_USE_BLKMEM : Integer range 0 to 1 := 1; -- 1 = Use Block RAM -- 0 = USE SRL C_FAMILY : String := "virtex7" ); port ( -- Inputs SFIFO_Sinit : In std_logic; -- Reset SFIFO_Clk : In std_logic; -- Clock SFIFO_Wr_en : In std_logic; -- Write enable SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); -- Write Data input SFIFO_Rd_en : In std_logic; -- Read Enable SFIFO_Clr_Rd_Data_Valid : In std_logic; -- Clear the Read data valid -- Outputs SFIFO_DValid : Out std_logic; -- Read Data Valid indication SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); -- Read Data out SFIFO_Full : Out std_logic; -- FIFO Full flag SFIFO_Empty : Out std_logic; -- FIFO empty flag SFIFO_Almost_full : Out std_logic; -- FIFO almost Full flag SFIFO_Almost_empty : Out std_logic; -- FIFO almost empty flag SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); -- Read count SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); -- Read count minus 1 SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); -- Write count SFIFO_Rd_ack : Out std_logic -- Read acknowledge ); end entity axi_cdma_sfifo_autord; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of axi_cdma_sfifo_autord is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; -- Constant declarations -- none -- Signal declarations signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0'); signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0'); signal raw_data_count_int : natural := 0; signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0'); signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0'); Signal corrected_empty : std_logic := '0'; Signal corrected_almost_empty : std_logic := '0'; Signal sig_SFIFO_empty : std_logic := '0'; -- backend fifo read ack sample and hold Signal sig_rddata_valid : std_logic := '0'; Signal hold_ff_q : std_logic := '0'; Signal ored_ack_ff_reset : std_logic := '0'; Signal autoread : std_logic := '0'; Signal sig_sfifo_rdack : std_logic := '0'; Signal fifo_read_enable : std_logic := '0'; begin -- Bit ordering translations write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little -- endian. SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to -- Big endian. -- Other port usages and assignments SFIFO_Rd_ack <= sig_sfifo_rdack; SFIFO_Almost_empty <= corrected_almost_empty; SFIFO_Empty <= corrected_empty; SFIFO_Wr_count <= raw_data_cnt_lil_end; SFIFO_Rd_count <= raw_data_count_corr; SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1; SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator fifo_read_enable <= SFIFO_Rd_en; -- or autoread; ------------------------------------------------------------ -- Instance: I_SYNC_FIFOGEN_FIFO -- -- Description: -- Instance for the synchronous fifo from proc common. -- ------------------------------------------------------------ I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0.sync_fifo_fg generic map( C_FAMILY => C_FAMILY, -- requred for FIFO Gen C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH, C_ENABLE_RLOCS => 0, C_HAS_DCOUNT => 1, C_HAS_RD_ACK => 1, C_HAS_RD_ERR => 0, C_HAS_WR_ACK => 1, C_HAS_WR_ERR => 0, C_MEMORY_TYPE => C_USE_BLKMEM, C_PORTS_DIFFER => 0, C_RD_ACK_LOW => 0, C_READ_DATA_WIDTH => C_DWIDTH, C_READ_DEPTH => C_DEPTH, C_RD_ERR_LOW => 0, C_WR_ACK_LOW => 0, C_WR_ERR_LOW => 0, C_WRITE_DATA_WIDTH => C_DWIDTH, C_WRITE_DEPTH => C_DEPTH, C_PRELOAD_REGS => 1, -- 1 = first word fall through C_PRELOAD_LATENCY => 0, -- 0 = first word fall through C_USE_EMBEDDED_REG => 1 -- 0 ; ) port map( Clk => SFIFO_Clk, Sinit => SFIFO_Sinit, Din => write_data_lil_end, Wr_en => SFIFO_Wr_en, Rd_en => fifo_read_enable, Dout => read_data_lil_end, Almost_full => open, Full => SFIFO_Full, Empty => sig_SFIFO_empty, Rd_ack => sig_sfifo_rdack, Wr_ack => open, Rd_err => open, Wr_err => open, Data_count => raw_data_cnt_lil_end ); ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Read Ack assert & hold logic Needed because.... ------------------------------------------------------------------------------- -- 1) The CoreGen Sync FIFO has to be read once to get valid -- data to the read data port. -- 2) The Read ack from the fifo is only asserted for 1 clock. -- 3) A signal is needed that indicates valid data is at the read -- port of the FIFO and has not yet been used. This signal needs -- to be held until the next read operation occurs or a clear -- signal is received. ored_ack_ff_reset <= fifo_read_enable or SFIFO_Sinit or SFIFO_Clr_Rd_Data_Valid; sig_rddata_valid <= hold_ff_q or sig_sfifo_rdack; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ACK_HOLD_FLOP -- -- Process Description: -- Flop for registering the hold flag -- ------------------------------------------------------------- IMP_ACK_HOLD_FLOP : process (SFIFO_Clk) begin if (SFIFO_Clk'event and SFIFO_Clk = '1') then if (ored_ack_ff_reset = '1') then hold_ff_q <= '0'; else hold_ff_q <= sig_rddata_valid; end if; end if; end process IMP_ACK_HOLD_FLOP; -- generate auto-read enable. This keeps fresh data at the output -- of the FIFO whenever it is available. autoread <= '1' -- create a read strobe when the when (sig_rddata_valid = '0' and -- output data is NOT valid sig_SFIFO_empty = '0') -- and the FIFO is not empty Else '0'; raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end); ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_ALMOST_EMPTY -- -- If Generate Description: -- This IFGen corrects the FIFO Read Count output for the -- auto read function and includes the generation of the -- Almost_Empty flag. -- ------------------------------------------------------------ INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate -- local signals Signal raw_data_count_int_corr : integer := 0; Signal raw_data_count_int_corr_minus1 : integer := 0; begin ------------------------------------------------------------- -- Combinational Process -- -- Label: CORRECT_RD_CNT_IAE -- -- Process Description: -- This process corrects the FIFO Read Count output for the -- auto read function and includes the generation of the -- Almost_Empty flag. -- ------------------------------------------------------------- CORRECT_RD_CNT_IAE : process (sig_rddata_valid, sig_SFIFO_empty, raw_data_count_int) begin if (sig_rddata_valid = '0') then raw_data_count_int_corr <= 0; raw_data_count_int_corr_minus1 <= 0; corrected_empty <= '1'; corrected_almost_empty <= '0'; elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty raw_data_count_int_corr <= 1; raw_data_count_int_corr_minus1 <= 0; corrected_empty <= '0'; corrected_almost_empty <= '1'; Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty raw_data_count_int_corr <= 2; raw_data_count_int_corr_minus1 <= 1; corrected_empty <= '0'; corrected_almost_empty <= '0'; else -- rddata valid and modify rd count from FIFO raw_data_count_int_corr <= raw_data_count_int+1; raw_data_count_int_corr_minus1 <= raw_data_count_int; corrected_empty <= '0'; corrected_almost_empty <= '0'; end if; end process CORRECT_RD_CNT_IAE; raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr, C_DATA_CNT_WIDTH); raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1, C_DATA_CNT_WIDTH); end generate INCLUDE_ALMOST_EMPTY; ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_ALMOST_EMPTY -- -- If Generate Description: -- This process corrects the FIFO Read Count output for the -- auto read function and omits the generation of the -- Almost_Empty flag. -- ------------------------------------------------------------ OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate -- local signals Signal raw_data_count_int_corr : integer := 0; begin corrected_almost_empty <= '0'; -- always low ------------------------------------------------------------- -- Combinational Process -- -- Label: CORRECT_RD_CNT -- -- Process Description: -- This process corrects the FIFO Read Count output for the -- auto read function and omits the generation of the -- Almost_Empty flag. -- ------------------------------------------------------------- CORRECT_RD_CNT : process (sig_rddata_valid, sig_SFIFO_empty, raw_data_count_int) begin if (sig_rddata_valid = '0') then raw_data_count_int_corr <= 0; corrected_empty <= '1'; elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty raw_data_count_int_corr <= 1; corrected_empty <= '0'; Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty raw_data_count_int_corr <= 2; corrected_empty <= '0'; else -- rddata valid and modify rd count from FIFO raw_data_count_int_corr <= raw_data_count_int+1; corrected_empty <= '0'; end if; end process CORRECT_RD_CNT; raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr, C_DATA_CNT_WIDTH); end generate OMIT_ALMOST_EMPTY; ------------------------------------------------------------ -- If Generate -- -- Label: INCLUDE_ALMOST_FULL -- -- If Generate Description: -- This IfGen Includes the generation of the Amost_Full flag. -- -- ------------------------------------------------------------ INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate -- Local Constants Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1; begin SFIFO_Almost_full <= '1' When raw_data_count_int = ALMOST_FULL_VALUE Else '0'; end generate INCLUDE_ALMOST_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: OMIT_ALMOST_FULL -- -- If Generate Description: -- This IfGen Omits the generation of the Amost_Full flag. -- -- ------------------------------------------------------------ OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate begin SFIFO_Almost_full <= '0'; -- always low end generate OMIT_ALMOST_FULL; end imp;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/c2n_playback/vhdl_source/c2n_playback_io.vhd

3

7052

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; entity c2n_playback_io is port ( clock : in std_logic; reset : in std_logic; req : in t_io_req; resp : out t_io_resp; phi2_tick : in std_logic; c64_stopped : in std_logic; c2n_motor : in std_logic; c2n_sense : out std_logic; c2n_out_r : out std_logic; c2n_out_w : out std_logic ); end c2n_playback_io; architecture gideon of c2n_playback_io is signal enabled : std_logic; signal counter : unsigned(23 downto 0); signal error : std_logic; signal status : std_logic_vector(7 downto 0); signal fifo_dout : std_logic_vector(7 downto 0); signal fifo_read : std_logic; signal fifo_full : std_logic; signal fifo_empty : std_logic; signal fifo_almostfull : std_logic; signal fifo_flush : std_logic; signal fifo_write : std_logic; signal pulse : std_logic; signal toggle : std_logic; signal cnt2 : integer range 0 to 63; signal stream_en : std_logic; type t_state is (idle, multi1, multi2, multi3, count_down); signal state : t_state; signal state_enc : std_logic_vector(1 downto 0); signal mode : std_logic; signal sel : std_logic_vector(1 downto 0); signal c2n_out : std_logic; attribute register_duplication : string; attribute register_duplication of stream_en : signal is "no"; begin process(clock) begin if rising_edge(clock) then -- c2n pin out and sync if sel = "00" then c2n_sense <= enabled and not fifo_empty; else c2n_sense <= '0'; end if; stream_en <= enabled and c2n_motor; if fifo_empty='1' and enabled='1' then error <= '1'; end if; -- create a pulse of 50 ticks if cnt2 = 0 then pulse <= '0'; elsif phi2_tick='1' then cnt2 <= cnt2 - 1; end if; -- bus handling resp <= c_io_resp_init; if req.write='1' then resp.ack <= '1'; -- ack for fifo write as well. if req.address(11)='0' then enabled <= req.data(0); if req.data(1)='1' then error <= '0'; end if; fifo_flush <= req.data(2); mode <= req.data(3); sel <= req.data(7 downto 6); end if; elsif req.read='1' then resp.ack <= '1'; resp.data <= status; end if; case state is when idle => if enabled='1' and fifo_empty='0' then if fifo_dout=X"00" then if mode='1' then state <= multi1; else counter <= to_unsigned(256*8, counter'length); state <= count_down; end if; else counter <= unsigned("0000000000000" & fifo_dout & "000"); state <= count_down; end if; else toggle <= '0'; end if; when multi1 => if fifo_empty='0' then counter(7 downto 0) <= unsigned(fifo_dout); state <= multi2; elsif enabled = '0' then state <= idle; end if; when multi2 => if fifo_empty='0' then counter(15 downto 8) <= unsigned(fifo_dout); state <= multi3; elsif enabled = '0' then state <= idle; end if; when multi3 => if fifo_empty='0' then counter(23 downto 16) <= unsigned(fifo_dout); state <= count_down; elsif enabled = '0' then state <= idle; end if; when count_down => if phi2_tick='1' and stream_en='1' and c64_stopped='0' then if (counter = 1) or (counter = 0) then pulse <= '1'; toggle <= not toggle; cnt2 <= 49; state <= idle; else counter <= counter - 1; end if; elsif enabled = '0' then state <= idle; end if; when others => null; end case; if reset='1' then enabled <= '0'; counter <= (others => '0'); pulse <= '0'; error <= '0'; mode <= '0'; sel <= "00"; end if; end if; end process; fifo_write <= req.write and req.address(11); -- 0x800-0xFFF (2K) fifo_read <= '0' when state = count_down else (enabled and not fifo_empty); fifo: entity work.sync_fifo generic map ( g_depth => 2048, -- Actual depth. g_data_width => 8, g_threshold => 1536, g_storage => "block", g_fall_through => true ) port map ( clock => clock, reset => reset, rd_en => fifo_read, wr_en => fifo_write, din => req.data, dout => fifo_dout, flush => fifo_flush, full => fifo_full, almost_full => fifo_almostfull, empty => fifo_empty, count => open ); status(0) <= enabled; status(1) <= error; status(2) <= fifo_full; status(3) <= fifo_almostfull; status(4) <= state_enc(0); status(5) <= state_enc(1); status(6) <= stream_en; status(7) <= fifo_empty; c2n_out <= not pulse; with sel select c2n_out_r <= c2n_out when "00", pulse when "10", '1' when others; c2n_out_w <= pulse when sel="01" else '1'; with state select state_enc <= "00" when idle, "01" when multi1, "01" when multi2, "01" when multi3, "10" when count_down, "11" when others; end gideon;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/usb/vhdl_source/ulpi_host.vhd

3

27625

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.usb_pkg.all; entity ulpi_host is port ( clock : in std_logic; reset : in std_logic; -- Descriptor RAM interface descr_addr : out std_logic_vector(8 downto 0); descr_rdata : in std_logic_vector(31 downto 0); descr_wdata : out std_logic_vector(31 downto 0); descr_en : out std_logic; descr_we : out std_logic; -- Buffer RAM interface buf_addr : out std_logic_vector(10 downto 0); buf_rdata : in std_logic_vector(7 downto 0); buf_wdata : out std_logic_vector(7 downto 0); buf_en : out std_logic; buf_we : out std_logic; -- Transmit Path Interface tx_busy : in std_logic; tx_ack : in std_logic; -- Interface to send tokens and handshakes send_token : out std_logic; send_handsh : out std_logic; tx_pid : out std_logic_vector(3 downto 0); tx_token : out std_logic_vector(10 downto 0); -- Interface to send data packets send_data : out std_logic; no_data : out std_logic; user_data : out std_logic_vector(7 downto 0); user_last : out std_logic; user_valid : out std_logic; user_next : in std_logic; -- Interface to bus initialization unit reset_done : in std_logic; sof_enable : in std_logic; scan_enable : in std_logic := '1'; speed : in std_logic_vector(1 downto 0); abort : in std_logic; -- Receive Path Interface rx_pid : in std_logic_vector(3 downto 0); rx_token : in std_logic_vector(10 downto 0); valid_token : in std_logic; valid_handsh : in std_logic; valid_packet : in std_logic; data_valid : in std_logic; data_start : in std_logic; data_out : in std_logic_vector(7 downto 0); rx_error : in std_logic ); end ulpi_host; architecture functional of ulpi_host is signal frame_div : integer range 0 to 65535; signal frame_cnt : unsigned(13 downto 0) := (others => '0'); signal do_sof : std_logic; constant c_max_transaction : integer := 31; constant c_max_pipe : integer := 31; constant c_timeout_val : integer := 7167; constant c_transaction_offset : unsigned(8 downto 6) := "001"; signal transaction_pntr : integer range 0 to c_max_transaction; signal descr_addr_i : unsigned(8 downto 0); -- could be temporarily pipe addr type t_state is (startup, idle, wait4start, scan_transactions, get_pipe, handle_trans, setup_token, bulk_token, send_data_packet, get_status, wait_for_ack, receive_data, send_ack, update_pipe, update_trans, do_ping ); signal state : t_state; signal substate : integer range 0 to 7; signal trans_in : t_transaction; signal pipe_in : t_pipe; signal trans_cnt : unsigned(10 downto 0); signal trans_len : unsigned(10 downto 0); signal buf_addr_i : unsigned(10 downto 0); -- signal speed : std_logic_vector(1 downto 0) := "11"; signal no_data_i : boolean; signal abort_reg : std_logic; signal tx_put : std_logic; signal tx_last : std_logic; signal need_ping : std_logic; signal fifo_data_in : std_logic_vector(7 downto 0); signal tx_almost_full : std_logic; signal link_busy : std_logic; signal timeout : boolean; signal timeout_cnt : integer range 0 to c_timeout_val; signal first_transfer : boolean; signal terminate : std_logic; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "sequential"; -- attribute keep : string; -- attribute keep of timeout : signal is "true"; signal debug_count : integer range 0 to 1023 := 0; signal debug_error : std_logic := '0'; begin descr_addr <= std_logic_vector(descr_addr_i); buf_addr <= std_logic_vector(buf_addr_i); no_data <= '1' when no_data_i else '0'; buf_wdata <= data_out; -- should be rx_data buf_we <= '1' when (state = receive_data) and (data_valid = '1') else '0'; p_protocol: process(clock) procedure next_transaction is begin if terminate='1' then terminate <= '0'; state <= idle; elsif transaction_pntr = c_max_transaction then transaction_pntr <= 0; state <= idle; -- wait for next sof before rescan else transaction_pntr <= transaction_pntr + 1; substate <= 0; state <= scan_transactions; end if; end procedure; function min(a, b: unsigned) return unsigned is begin if a < b then return a; else return b; end if; end function; variable trans_temp : t_transaction; variable len : unsigned(trans_temp.transfer_length'range); begin if rising_edge(clock) then descr_en <= '0'; descr_we <= '0'; tx_put <= '0'; if abort='1' then abort_reg <= '1'; end if; -- default counter if substate /= 3 then substate <= substate + 1; end if; if timeout_cnt /= 0 then timeout_cnt <= timeout_cnt - 1; if timeout_cnt = 1 then timeout <= false;--true; end if; end if; case state is when startup => tx_pid <= c_pid_reserved; do_sof <= '0'; frame_div <= 7499; if reset_done='1' then state <= idle; if speed = "10" then need_ping <= '1'; end if; end if; when idle => abort_reg <= '0'; if do_sof='1' then do_sof <= '0'; tx_token <= std_logic_vector(frame_cnt(13 downto 3)); tx_pid <= c_pid_sof; if speed = "00" then send_handsh <= '1'; else send_token <= '1'; end if; if speed(1)='1' then frame_cnt <= frame_cnt + 1; else frame_cnt <= frame_cnt + 8; end if; state <= wait4start; end if; when wait4start => if tx_ack='1' then send_token <= '0'; send_handsh <= '0'; send_data <= '0'; -- redundant - will not come here substate <= 0; if scan_enable='1' then state <= scan_transactions; else state <= idle; end if; end if; when scan_transactions => case substate is when 0 => descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr, descr_addr_i'length-c_transaction_offset'length); descr_en <= '1'; when 2 => trans_temp := data_to_t_transaction(descr_rdata); trans_in <= trans_temp; substate <= 0; if trans_temp.state = busy then state <= get_pipe; else -- go for next, unless we are at the end of the list next_transaction; end if; when others => null; end case; when get_pipe => case substate is when 0 => descr_addr_i <= (others => '0'); descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer; descr_en <= '1'; when 2 => pipe_in <= data_to_t_pipe(descr_rdata); first_transfer <= true; state <= handle_trans; --- when others => null; end case; when handle_trans => -- both pipe and transaction records are now valid abort_reg <= '0'; substate <= 0; if do_sof='1' and link_busy='0' then state <= idle; elsif pipe_in.state /= initialized then -- can we use the pipe? trans_in.state <= error; state <= update_trans; else -- yes we can timeout <= false; timeout_cnt <= c_timeout_val; link_busy <= trans_in.link_to_next; case trans_in.transaction_type is when control => -- a control out sequence exists of a setup token -- and then a data0 packet, which should be followed by -- an ack from the device. The next phase of the transaction -- could be either in or out, and defines whether it is a -- control read or a control write. -- By choice, control transfers are implemented using -- two transactions, which are executed in guaranteed -- sequence. -- In this way, each stage has its own buffer. -- Note, the first pipe should be of type OUT, although it is not -- checked. tx_pid <= c_pid_setup; tx_token <= pipe_in.device_endpoint & pipe_in.device_address; send_token <= '1'; state <= setup_token; when bulk | interrupt => tx_token <= pipe_in.device_endpoint & pipe_in.device_address; state <= bulk_token; send_token <= '1'; timeout <= false; timeout_cnt <= c_timeout_val; if pipe_in.direction = dir_in then tx_pid <= c_pid_in; else -- if need_ping='1' then -- tx_pid <= c_pid_ping; -- state <= do_ping; -- else tx_pid <= c_pid_out; -- end if; end if; if pipe_in.control='1' and first_transfer then pipe_in.data_toggle <= '1'; -- start with data 1 end if; first_transfer <= false; when others => -- not yet supported trans_in.state <= error; state <= update_trans; end case; end if; when setup_token => if tx_ack='1' then send_token <= '0'; tx_pid <= c_pid_data0; -- send setup data immediately send_data <= '1'; buf_en <= '1'; substate <= 0; state <= send_data_packet; end if; -- prepare buffer buf_addr_i <= trans_in.buffer_address; trans_len <= trans_in.transfer_length; -- not cut up trans_cnt <= trans_in.transfer_length; -- not cut up no_data_i <= (trans_in.transfer_length = 0); when do_ping => if tx_ack='1' then send_token <= '0'; end if; -- wait for ack/nack or nyet. if rx_error='1' then trans_in.state <= error; state <= update_trans; elsif abort_reg='1' then pipe_in.state <= aborted; state <= update_pipe; abort_reg <= '0'; elsif valid_handsh='1' then -- maybe an ack? if rx_pid = c_pid_ack then tx_pid <= c_pid_out; send_token <= '1'; state <= bulk_token; elsif rx_pid = c_pid_stall then pipe_in.state <= stalled; trans_in.state <= error; state <= update_pipe; elsif (rx_pid = c_pid_nak) or (rx_pid = c_pid_nyet) then state <= handle_trans; end if; -- all other pids are just ignored elsif timeout then state <= handle_trans; end if; when bulk_token => if tx_ack='1' then send_token <= '0'; if pipe_in.direction = dir_out then if pipe_in.data_toggle = '0' then tx_pid <= c_pid_data0; else tx_pid <= c_pid_data1; end if; send_data <= '1'; buf_en <= '1'; substate <= 0; state <= send_data_packet; else -- input timeout <= false; timeout_cnt <= c_timeout_val; state <= receive_data; buf_en <= '1'; end if; end if; -- prepare buffer buf_addr_i <= trans_in.buffer_address; if pipe_in.direction = dir_out then len := min(trans_in.transfer_length, pipe_in.max_transfer); trans_len <= len; -- possibly cut up trans_cnt <= len; no_data_i <= (trans_in.transfer_length = 0); else trans_len <= (others => '0'); end if; when send_data_packet => case substate is when 0 => if tx_ack='1' then send_data <= '0'; if no_data_i then substate <= 2; end if; else substate <= 0; end if; when 1 => substate <= 1; -- stay! if tx_almost_full='0' then tx_put <= '1'; buf_addr_i <= buf_addr_i + 1; trans_cnt <= trans_cnt - 1; if trans_cnt = 1 then tx_last <= '1'; substate <= 2; buf_en <= '0'; else tx_last <= '0'; end if; end if; when 2 => if tx_busy='1' then substate <= 2; else state <= wait_for_ack; timeout <= false; timeout_cnt <= c_timeout_val; end if; when others => null; end case; when wait_for_ack => if rx_error='1' then trans_in.state <= error; state <= update_trans; elsif abort_reg='1' then pipe_in.state <= aborted; state <= update_pipe; abort_reg <= '0'; elsif valid_handsh='1' then -- maybe an ack? if (rx_pid = c_pid_ack) or (rx_pid = c_pid_nyet) then if rx_pid = c_pid_nyet then need_ping <= '1'; else need_ping <= '0'; end if; if trans_in.transfer_length = trans_len then trans_in.state <= done; if pipe_in.control='1' and trans_in.transaction_type = bulk then state <= get_status; substate <= 0; else state <= update_pipe; end if; else trans_in.state <= busy; state <= handle_trans; end if; trans_in.buffer_address <= buf_addr_i; -- store back trans_in.transfer_length <= trans_in.transfer_length - trans_len; pipe_in.data_toggle <= not pipe_in.data_toggle; elsif rx_pid = c_pid_stall then pipe_in.state <= stalled; trans_in.state <= error; state <= update_pipe; elsif rx_pid = c_pid_nak then terminate <= '0'; --link_busy; -- if control packet, then don't continue with next transaction! state <= update_trans; -- state <= handle_trans; -- just retry and retry, no matter what kind of packet it is, don't send SOF! end if; -- all other pids are just ignored -- elsif do_sof='1' then -- state <= idle; -- test elsif timeout then pipe_in.timeout <= '1'; trans_in.state <= error; state <= update_pipe; -- state <= handle_trans; -- try again end if; when get_status => case substate is when 0 => send_token <= '1'; tx_pid <= c_pid_in; when 1 => if tx_ack='1' then send_token <= '0'; timeout_cnt <= c_timeout_val; timeout <= false; else substate <= 1; -- wait end if; when 2 => if valid_packet='1' or valid_handsh='1' then state <= update_pipe; -- end transaction elsif rx_error='1' or timeout then trans_in.state <= error; state <= update_pipe; -- end transaction else substate <= 2; -- wait end if; when others => null; end case; when receive_data => if data_valid = '1' then timeout <= false; timeout_cnt <= 0; -- does not occur anymore buf_addr_i <= buf_addr_i + 1; trans_len <= trans_len + 1; end if; -------------------------------------------------------------------- if rx_error = '1' or debug_error='1' then -- go back to send the in token again buf_en <= '0'; state <= handle_trans; elsif abort_reg='1' then pipe_in.state <= aborted; state <= update_pipe; abort_reg <= '0'; elsif valid_packet='1' then buf_en <= '0'; trans_in.buffer_address <= buf_addr_i - 2; -- cut off CRC trans_in.transfer_length <= trans_in.transfer_length - (trans_len - 2); if ((trans_len - 2) >= trans_in.transfer_length) or ((trans_len - 2) < pipe_in.max_transfer) then trans_in.state <= done; else trans_in.state <= busy; end if; state <= send_ack; substate <= 0; elsif valid_handsh='1' then buf_en <= '0'; if rx_pid = c_pid_nak then if pipe_in.control='1' then state <= idle; -- retry on next sof, do not go to the next transaction else state <= update_trans; -- is not updated, but is the standard path to go to the next transact. end if; elsif rx_pid = c_pid_stall then trans_in.state <= error; pipe_in.state <= stalled; state <= update_pipe; end if; elsif timeout then -- device doesn't answer, could it have missed my in token? buf_en <= '0'; state <= handle_trans; end if; when send_ack => case substate is when 0 => send_handsh <= '1'; tx_pid <= c_pid_ack; when 1 => if tx_ack='0' then substate <= 1; -- stay here. else send_handsh <= '0'; state <= update_trans; -- if (pipe_in.control='0') and (trans_in.state = done) then -- state <= update_trans; -- elsif (pipe_in.control='1') and (trans_len = 2) then -- no data, thus status already received -- state <= update_trans; -- else -- null; -- -- substate <= 2; -- end if; end if; -- when 2 => -- send status back (no data packet) -- tx_pid <= c_pid_out; -- tx_token <= pipe_in.device_endpoint & pipe_in.device_address; -- send_token <= '1'; -- when 3 => -- wait until token was sent -- if tx_ack='0' then -- substate <= 3; -- else -- send_token <= '0'; -- no_data_i <= true; -- send_data <= '1'; -- tx_pid <= c_pid_data1; -- end if; -- when 4 => -- wait until no data packet was processed -- if tx_ack='0' then -- substate <= 4; -- else -- send_data <= '0'; -- state <= update_trans; -- end if; when others => null; end case; when update_pipe => descr_addr_i <= (others => '0'); descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer; descr_en <= '1'; descr_we <= '1'; descr_wdata <= t_pipe_to_data(pipe_in); state <= update_trans; when update_trans => descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr, descr_addr_i'length-c_transaction_offset'length); descr_wdata <= t_transaction_to_data(trans_in); descr_en <= '1'; descr_we <= '1'; next_transaction; when others => null; end case; --------------------------------------------------- -- DEBUG --------------------------------------------------- -- if state /= receive_data then -- debug_count <= 0; -- debug_error <= '0'; -- elsif debug_count = 1023 then -- debug_error <= '1'; -- else -- debug_count <= debug_count + 1; -- end if; --------------------------------------------------- if frame_div = 0 then do_sof <= sof_enable; if speed(1)='1' then frame_div <= 7499; -- microframes else frame_div <= 59999; -- 1 ms frames end if; else frame_div <= frame_div - 1; end if; if reset_done='0' then state <= startup; end if; if speed /= "10" then -- If not high speed, then we force no ping need_ping <= '0'; end if; if reset = '1' then abort_reg <= '0'; buf_en <= '0'; buf_addr_i <= (others => '0'); trans_len <= (others => '0'); trans_cnt <= (others => '0'); link_busy <= '0'; state <= startup; do_sof <= '0'; frame_div <= 7499; frame_cnt <= (others => '0'); send_token <= '0'; send_data <= '0'; send_handsh <= '0'; need_ping <= '0'; terminate <= '0'; end if; end if; end process; -- Decoupling of ulpi tx bus and our generation of data -- to meet timing of "next" signal -- fifo_data_in <= reset_data when (state = startup) else buf_rdata; fifo_data_in <= buf_rdata; i_srl_tx: entity work.srl_fifo generic map ( Width => 9, Depth => 15, Threshold => 10 ) port map ( clock => clock, reset => reset, GetElement => user_next, PutElement => tx_put, FlushFifo => '0', DataIn(7 downto 0) => fifo_data_in, DataIn(8) => tx_last, DataOut(7 downto 0) => user_data, DataOut(8) => user_last, SpaceInFifo => open, AlmostFull => tx_almost_full, DataInFifo => user_valid ); end functional;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/usb/vhdl_source/token_crc.vhd

3

1863

------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2004, Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : token_crc.vhd ------------------------------------------------------------------------------- -- File : token_crc.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This file is used to calculate the CRC over a USB token ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity token_crc is port ( clock : in std_logic; sync : in std_logic; token_in : in std_logic_vector(10 downto 0); crc : out std_logic_vector(4 downto 0) ); end token_crc; architecture Gideon of token_crc is -- signal crc_reg : std_logic_vector(4 downto 0) := (others => '0'); constant polynom : std_logic_vector(4 downto 0) := "00100"; -- CRC-5 = x5 + x2 + 1 begin process(clock) variable tmp : std_logic_vector(crc'range); variable d : std_logic; begin if rising_edge(clock) then tmp := (others => '1'); for i in token_in'reverse_range loop -- LSB first! d := token_in(i) xor tmp(tmp'high); tmp := tmp(tmp'high-1 downto 0) & d; --'0'; if d = '1' then tmp := tmp xor polynom; end if; end loop; for i in tmp'range loop -- reverse and invert crc(crc'high-i) <= not(tmp(i)); end loop; end if; end process; end Gideon;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/nano_cpu/vhdl_source/nano.vhd

3

6323

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.nano_cpu_pkg.all; use work.io_bus_pkg.all; library unisim; use unisim.vcomponents.all; entity nano is port ( clock : in std_logic; reset : in std_logic; -- i/o interface io_addr : out unsigned(7 downto 0); io_write : out std_logic; io_read : out std_logic; io_wdata : out std_logic_vector(15 downto 0); io_rdata : in std_logic_vector(15 downto 0); stall : in std_logic; -- system interface (to write code into the nano) sys_clock : in std_logic := '0'; sys_reset : in std_logic := '0'; sys_io_req : in t_io_req := c_io_req_init; sys_io_resp : out t_io_resp ); end entity; architecture structural of nano is signal sys_enable : std_logic; -- instruction/data ram signal ram_addr : std_logic_vector(9 downto 0); signal ram_en : std_logic; signal ram_we : std_logic; signal ram_wdata : std_logic_vector(15 downto 0); signal ram_rdata : std_logic_vector(15 downto 0); signal sys_io_req_bram : t_io_req; signal sys_io_resp_bram : t_io_resp; signal sys_io_req_regs : t_io_req; signal sys_io_resp_regs : t_io_resp; signal sys_core_reset : std_logic; signal usb_reset_tig : std_logic; signal usb_core_reset : std_logic; signal bram_reset : std_logic; signal bram_data : std_logic_vector(7 downto 0); begin i_split: entity work.io_bus_splitter generic map ( g_range_lo => 12, g_range_hi => 12, g_ports => 2 ) port map ( clock => sys_clock, req => sys_io_req, resp => sys_io_resp, reqs(0) => sys_io_req_bram, -- 4080000 reqs(1) => sys_io_req_regs, -- 4081000 resps(0) => sys_io_resp_bram, resps(1) => sys_io_resp_regs ); i_core: entity work.nano_cpu port map ( clock => clock, reset => usb_core_reset, -- instruction/data ram ram_addr => ram_addr, ram_en => ram_en, ram_we => ram_we, ram_wdata => ram_wdata, ram_rdata => ram_rdata, -- i/o interface io_addr => io_addr, io_write => io_write, io_read => io_read, io_wdata => io_wdata, io_rdata => io_rdata, stall => stall ); i_buf_ram: RAMB16_S9_S18 generic map ( INIT_00 => X"096CE011A0CA095CC00F29596893E8210968C00F295C6893E93FA0CA0963E947", INIT_01 => X"E9340964E05CE9340894E9340965E8DAC01E295A6832E821089AA0C40974A0CA", INIT_02 => X"D0356824B800A027D82A6827B800C822809559580895A02FD822682F8095E020", INIT_03 => X"E02AA011A0000959B8000957E033A020D83A6820A024B8000958E850D82E682F", INIT_04 => X"C856295D808E4958088EE05051590894A02FD856682FE02AA010A001088FA000", INIT_05 => X"0BF2C0840BF0E845B800E9340966A02DD85B682DE82AA010A000095BA0016860", INIT_06 => X"0BF4E082C079516BC074516AC06F51690BF0808F0BF183F50957A0700BF3A071", INIT_07 => X"D87E687483F5A0726833811FE8C4E082E934E8A0E8850BF4E082E934E89CE885", INIT_08 => X"00000000B800A050B800D8896874A040A073C08C8090E05C83F00957E934091F", INIT_09 => X"E0A6095AE8400962004B15E00050004000450046000000000000000000000008", INIT_0A => X"C0BE6822C8BEE82EE82AA012A00259580890A000E0A6195A295E0891E8400958", INIT_0B => X"49580892B8000958C8BE5163B8000959C8BA5160B800095AC8B651596830A022", INIT_0C => X"C8D85161E0D20957E83CC8CE515A0830C8D9E82EE840095FE0B8C0BC515A8092", INIT_0D => X"8094095AC0E1515E296F6832E0BEE0B6B8000959B800095AC8D65093095EE83C", INIT_0E => X"0894A02EA01E80950976A0C4097280940958E0E980940957C0E729596832B800", INIT_0F => X"B800A0C48900810049670894C8F1809559580895A02FD8F1682FD101682EC117", INIT_10 => X"A055C114809559580895C90959580975A0458095089BA018A045809409590000", INIT_11 => X"0000E0FAC917809559580895A02FD917682F8095095AA019E107C91159580975", INIT_12 => X"0BFDB800894683FE297149580BFE8146496D0BFEB800C926E920B8003BFE0BFF", INIT_13 => X"0957B80083FD297749580BFD91460945814649700BFD8145B8003BFC29774958", INIT_14 => X"0969A07183F30973A07083F2096E83F4096200000000B80083FF83FE83FD83FC", INIT_15 => X"000900080007000600050003000200010000B800A0720963809B809A095B83F0", INIT_16 => X"0038123403B000260023002200210FA00096001300120011000E000D000B000A", INIT_17 => X"00000000000000000000000000000000007F007802EE006156780050003F0330", INIT_3F => X"FF00000000000000000000000000000000000000000000000000000000000000" ) port map ( CLKB => clock, SSRB => reset, ENB => ram_en, WEB => ram_we, ADDRB => ram_addr, DIB => ram_wdata, DIPB => "00", DOB => ram_rdata, CLKA => sys_clock, SSRA => sys_reset, ENA => sys_enable, WEA => sys_io_req_bram.write, ADDRA => std_logic_vector(sys_io_req_bram.address(10 downto 0)), DIA => sys_io_req_bram.data, DIPA => "0", DOA => bram_data ); sys_enable <= sys_io_req_bram.write or sys_io_req_bram.read; bram_reset <= not sys_enable; sys_io_resp_bram.data <= bram_data when sys_io_resp_bram.ack = '1' else X"00"; process(sys_clock) begin if rising_edge(sys_clock) then sys_io_resp_bram.ack <= sys_enable; sys_io_resp_regs <= c_io_resp_init; sys_io_resp_regs.ack <= sys_io_req_regs.write or sys_io_req_regs.read; if sys_io_req_regs.write = '1' then -- any address sys_core_reset <= not sys_io_req_regs.data(0); end if; if sys_reset = '1' then sys_core_reset <= '1'; end if; end if; end process; process(clock) begin if rising_edge(clock) then usb_reset_tig <= sys_core_reset; usb_core_reset <= usb_reset_tig; end if; end process; end architecture;

gpl-3.0

davidhorrocks/1541UltimateII

target/simulation/vhdl_bfm/bram_model_8sp.vhd

5

2053

------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : BRAM model ------------------------------------------------------------------------------- -- File : bram_model_8sp.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This simple BRAM model uses the flat memory model package. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.tl_flat_memory_model_pkg.all; entity bram_model_8sp is generic ( g_given_name : string; g_depth : positive := 18 ); port ( CLK : in std_logic; SSR : in std_logic; EN : in std_logic; WE : in std_logic; ADDR : in std_logic_vector(g_depth-1 downto 0); DI : in std_logic_vector(7 downto 0); DO : out std_logic_vector(7 downto 0) ); end bram_model_8sp; architecture bfm of bram_model_8sp is shared variable this : h_mem_object; signal bound : boolean := false; begin bind: process begin register_mem_model(bram_model_8sp'path_name, g_given_name, this); bound <= true; wait; end process; process(CLK) variable vaddr : std_logic_vector(31 downto 0) := (others => '0'); begin if rising_edge(CLK) then vaddr(g_depth-1 downto 0) := ADDR; if EN='1' then if bound then DO <= read_memory_8(this, vaddr); if WE='1' then write_memory_8(this, vaddr, DI); end if; end if; end if; if SSR='1' then DO <= (others => '0'); end if; end if; end process; end bfm;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/usb2/vhdl_source/usb_io_bank.vhd

5

8681

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity usb_io_bank is port ( clock : in std_logic; reset : in std_logic; -- i/o interface io_addr : in unsigned(7 downto 0); io_write : in std_logic; io_read : in std_logic; io_wdata : in std_logic_vector(15 downto 0); io_rdata : out std_logic_vector(15 downto 0); stall : out std_logic; -- Memory controller and buffer mem_ready : in std_logic; transferred : in unsigned(10 downto 0); -- Register access reg_read : out std_logic := '0'; reg_write : out std_logic := '0'; reg_ack : in std_logic; reg_addr : out std_logic_vector(5 downto 0) := (others => '0'); reg_wdata : out std_logic_vector(7 downto 0) := X"00"; reg_rdata : in std_logic_vector(7 downto 0); status : in std_logic_vector(7 downto 0); -- I/O pins from RX rx_pid : in std_logic_vector(3 downto 0); rx_token : in std_logic_vector(10 downto 0); rx_valid_token : in std_logic; rx_valid_handsh : in std_logic; rx_valid_packet : in std_logic; rx_error : in std_logic; -- I/O pins to TX tx_pid : out std_logic_vector(3 downto 0); tx_token : out std_logic_vector(10 downto 0); tx_send_token : out std_logic; tx_send_handsh : out std_logic; tx_send_data : out std_logic; tx_length : out unsigned(10 downto 0); tx_no_data : out std_logic; tx_chirp_enable : out std_logic; tx_chirp_level : out std_logic; tx_chirp_end : out std_logic; tx_chirp_start : out std_logic; tx_ack : in std_logic ); end entity; architecture gideon of usb_io_bank is signal pulse_in : std_logic_vector(15 downto 0) := (others => '0'); signal pulse_out : std_logic_vector(15 downto 0) := (others => '0'); signal latched : std_logic_vector(15 downto 0) := (others => '0'); signal level_out : std_logic_vector(15 downto 0) := (others => '0'); signal frame_div : integer range 0 to 65535; signal frame_cnt : unsigned(13 downto 0) := (others => '0'); signal stall_i : std_logic := '0'; signal ulpi_access : std_logic; signal tx_chirp_start_i : std_logic; signal tx_chirp_end_i : std_logic; signal filter_cnt : unsigned(7 downto 0); signal filter_st1 : std_logic; signal reset_filter : std_logic; begin pulse_in(0) <= rx_error; pulse_in(1) <= rx_valid_token; pulse_in(2) <= rx_valid_handsh; pulse_in(3) <= rx_valid_packet; pulse_in(4) <= rx_valid_packet or rx_valid_handsh or rx_valid_token or rx_error; pulse_in(7) <= tx_ack; -- tx ack resets lower half of output pulses tx_no_data <= level_out(0); tx_send_token <= pulse_out(0); tx_send_handsh <= pulse_out(1); tx_send_data <= pulse_out(2); tx_chirp_level <= level_out(5); tx_chirp_start <= tx_chirp_start_i; tx_chirp_end <= tx_chirp_end_i; tx_chirp_start_i <= pulse_out(8); tx_chirp_end_i <= pulse_out(9); reset_filter <= pulse_out(14); pulse_in(14) <= filter_st1; pulse_in(13) <= '1' when (status(5 downto 4) = "10") else '0'; process(clock) variable adlo : unsigned(3 downto 0); variable adhi : unsigned(7 downto 4); begin if rising_edge(clock) then adlo := io_addr(3 downto 0); adhi := io_addr(7 downto 4); if tx_ack = '1' then pulse_out(7 downto 0) <= (others => '0'); end if; pulse_out(15 downto 8) <= X"00"; pulse_in(15) <= '0'; if frame_div = 0 then frame_div <= 7499; -- microframes pulse_in(15) <= '1'; frame_cnt <= frame_cnt + 1; else frame_div <= frame_div - 1; end if; if tx_chirp_start_i = '1' then tx_chirp_enable <= '1'; elsif tx_chirp_end_i = '1' then tx_chirp_enable <= '0'; end if; filter_st1 <= '0'; if reset_filter = '1' then filter_cnt <= (others => '0'); elsif status(1) = '0' then filter_cnt <= (others => '0'); else filter_cnt <= filter_cnt + 1; if filter_cnt = 255 and latched(14)='0' then filter_st1 <= '1'; end if; end if; if reg_ack='1' then reg_write <= '0'; reg_read <= '0'; stall_i <= '0'; end if; if io_write='1' then reg_addr <= std_logic_vector(io_addr(5 downto 0)); case adhi is when X"0" => case adlo(3 downto 0) is when X"0" => tx_pid <= io_wdata(tx_pid'range); when X"1" => tx_token <= io_wdata(tx_token'range); when X"2" => tx_length <= unsigned(io_wdata(tx_length'range)); when others => null; end case; when X"1" => pulse_out(to_integer(adlo)) <= '1'; when X"2" => latched(to_integer(adlo)) <= '0'; when X"4" => level_out(to_integer(adlo)) <= '0'; when X"5" => level_out(to_integer(adlo)) <= '1'; when X"C"|X"D"|X"E"|X"F" => reg_wdata <= io_wdata(7 downto 0); reg_write <= '1'; stall_i <= '1'; when others => null; end case; end if; if io_read = '1' then reg_addr <= std_logic_vector(io_addr(5 downto 0)); if io_addr(7 downto 6) = "10" then reg_read <= '1'; stall_i <= '1'; end if; end if; for i in latched'range loop if pulse_in(i)='1' then latched(i) <= '1'; end if; end loop; if reset='1' then tx_pid <= (others => '0'); tx_token <= (others => '0'); tx_length <= (others => '0'); latched <= (others => '0'); level_out <= (others => '0'); reg_read <= '0'; reg_write <= '0'; stall_i <= '0'; tx_chirp_enable <= '0'; end if; end if; end process; ulpi_access <= io_addr(7); stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned process(latched, level_out, rx_pid, rx_token, reg_rdata, io_addr) variable adlo : unsigned(3 downto 0); variable adhi : unsigned(7 downto 4); begin io_rdata <= (others => '0'); adlo := io_addr(3 downto 0); adhi := io_addr(7 downto 4); case adhi is when X"2" => io_rdata(15) <= latched(to_integer(adlo)); when X"3" => case adlo(3 downto 0) is when X"0" => io_rdata <= X"000" & rx_pid; when X"1" => io_rdata <= "00000" & rx_token; when X"2" => io_rdata <= X"00" & status; when X"3" => io_rdata <= "00000" & std_logic_vector(transferred); when others => null; end case; when X"6" => case adlo(3 downto 0) is when X"0" => io_rdata <= "00000" & std_logic_vector(frame_cnt(13 downto 3)); when others => null; end case; when X"7" => io_rdata(15) <= mem_ready; when X"8"|X"9"|X"A"|X"B" => io_rdata <= X"00" & reg_rdata; when others => null; end case; end process; end architecture;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/video/vhdl_source/char_generator_regs.vhd

4

4411

------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010, Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Character Generator Registers ------------------------------------------------------------------------------- -- File : char_generator_regs.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: Registers for the character generator ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; use work.char_generator_pkg.all; entity char_generator_regs is port ( clock : in std_logic; reset : in std_logic; io_req : in t_io_req; io_resp : out t_io_resp; keyb_row : in std_logic_vector(7 downto 0); keyb_col : inout std_logic_vector(7 downto 0); control : out t_chargen_control ); end entity; architecture gideon of char_generator_regs is signal control_i : t_chargen_control := c_chargen_control_init; begin process(clock) begin if rising_edge(clock) then io_resp <= c_io_resp_init; if io_req.write='1' then io_resp.ack <= '1'; case io_req.address(3 downto 0) is when c_chargen_line_clocks_hi => control_i.clocks_per_line(10 downto 8) <= unsigned(io_req.data(2 downto 0)); when c_chargen_line_clocks_lo => control_i.clocks_per_line(7 downto 0) <= unsigned(io_req.data); when c_chargen_char_width => control_i.char_width <= unsigned(io_req.data(2 downto 0)); when c_chargen_char_height => control_i.char_height <= unsigned(io_req.data(3 downto 0)); when c_chargen_chars_per_line => control_i.chars_per_line <= unsigned(io_req.data); when c_chargen_active_lines => control_i.active_lines <= unsigned(io_req.data(5 downto 0)); when c_chargen_x_on_hi => control_i.x_on(11 downto 8) <= unsigned(io_req.data(3 downto 0)); when c_chargen_x_on_lo => control_i.x_on(7 downto 0) <= unsigned(io_req.data); when c_chargen_y_on_hi => control_i.y_on(11 downto 8) <= unsigned(io_req.data(3 downto 0)); when c_chargen_y_on_lo => control_i.y_on(7 downto 0) <= unsigned(io_req.data); when c_chargen_pointer_hi => control_i.pointer(14 downto 8) <= unsigned(io_req.data(6 downto 0)); when c_chargen_pointer_lo => control_i.pointer(7 downto 0) <= unsigned(io_req.data); when c_chargen_perform_sync => control_i.perform_sync <= io_req.data(0); when c_chargen_transparency => control_i.transparent <= io_req.data(3 downto 0); control_i.overlay_on <= io_req.data(7); when c_chargen_keyb_col => keyb_col <= io_req.data; when others => null; end case; elsif io_req.read='1' then io_resp.ack <= '1'; case io_req.address(3 downto 0) is when c_chargen_keyb_row => io_resp.data <= keyb_row; when c_chargen_keyb_col => io_resp.data <= keyb_col; when others => null; end case; end if; if reset='1' then control_i <= c_chargen_control_init; keyb_col <= (others => '1'); end if; end if; end process; control <= control_i; end gideon;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v2_mk1.vhd

5

10827

library work; use work.tl_flat_memory_model_pkg.all; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity harness_v2_mk1 is end harness_v2_mk1; architecture tb of harness_v2_mk1 is constant c_uart_divisor : natural := 434; signal PHI2 : std_logic := '0'; signal RSTn : std_logic := '1'; signal DOTCLK : std_logic := '1'; signal BUFFER_ENn : std_logic := '1'; signal LB_ADDR : std_logic_vector(21 downto 0); signal LB_DATA : std_logic_vector(7 downto 0) := X"00"; signal BA : std_logic := '0'; signal DMAn : std_logic := '1'; signal EXROMn : std_logic; signal GAMEn : std_logic; signal ROMHn : std_logic := '1'; signal ROMLn : std_logic := '1'; signal IO1n : std_logic := '1'; signal IO2n : std_logic := '1'; signal IRQn : std_logic := '1'; signal NMIn : std_logic := '1'; signal MEM_WEn : std_logic; signal MEM_OEn : std_logic; signal SDRAM_CSn : std_logic; signal SDRAM_RASn : std_logic; signal SDRAM_CASn : std_logic; signal SDRAM_WEn : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CLK : std_logic; signal SDRAM_DQM : std_logic; signal PWM_OUT : std_logic_vector(1 downto 0); signal IEC_ATN : std_logic := '1'; signal IEC_DATA : std_logic := '1'; signal IEC_CLOCK : std_logic := '1'; signal IEC_RESET : std_logic := '1'; signal IEC_SRQ_IN : std_logic := '1'; signal DISK_ACTn : std_logic; -- activity LED signal CART_LEDn : std_logic; signal SDACT_LEDn : std_logic; signal MOTOR_LEDn : std_logic; signal UART_TXD : std_logic; signal UART_RXD : std_logic := '1'; signal SD_SSn : std_logic; signal SD_CLK : std_logic; signal SD_MOSI : std_logic; signal SD_MISO : std_logic := '1'; signal SD_WP : std_logic := '1'; signal SD_CARDDETn : std_logic := '1'; signal BUTTON : std_logic_vector(2 downto 0) := "111"; signal SLOT_ADDR : std_logic_vector(15 downto 0); signal SLOT_DATA : std_logic_vector(7 downto 0); signal RWn : std_logic := '1'; signal CAS_MOTOR : std_logic := '1'; signal CAS_SENSE : std_logic := '0'; signal CAS_READ : std_logic := '0'; signal CAS_WRITE : std_logic := '0'; signal ETH_CLK : std_logic; signal ETH_RST : std_logic; signal ETH_CSn : std_logic; signal ETH_CS : std_logic; signal FLASH_CSn : std_logic; signal SRAM_CSn : std_logic; signal ONE_WIRE : std_logic := 'H'; signal sys_clock : std_logic := '0'; signal sys_reset : std_logic := '0'; signal rx_char : std_logic_vector(7 downto 0); signal rx_char_d : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal tx_char : std_logic_vector(7 downto 0) := X"00"; signal tx_done : std_logic; signal do_tx : std_logic := '0'; shared variable dram : h_mem_object; shared variable ram : h_mem_object; shared variable sram : h_mem_object; -- shared variable bram : h_mem_object; begin mut: entity work.ultimate_1541_250e generic map ( g_simulation => true ) port map ( CLOCK => sys_clock, PHI2 => PHI2, DOTCLK => DOTCLK, RSTn => RSTn, BUFFER_ENn => BUFFER_ENn, SLOT_ADDR => SLOT_ADDR, SLOT_DATA => SLOT_DATA, RWn => RWn, BA => BA, DMAn => DMAn, EXROMn => EXROMn, GAMEn => GAMEn, ROMHn => ROMHn, ROMLn => ROMLn, IO1n => IO1n, IO2n => IO2n, IRQn => IRQn, NMIn => NMIn, LB_ADDR => LB_ADDR, LB_DATA => LB_DATA, FLASH_CSn => FLASH_CSn, SRAM_CSn => SRAM_CSn, MEM_WEn => MEM_WEn, MEM_OEn => MEM_OEn, SDRAM_CSn => SDRAM_CSn, SDRAM_RASn => SDRAM_RASn, SDRAM_CASn => SDRAM_CASn, SDRAM_WEn => SDRAM_WEn, SDRAM_CKE => SDRAM_CKE, SDRAM_CLK => SDRAM_CLK, SDRAM_DQM => SDRAM_DQM, -- PWM outputs (for audio) PWM_OUT => PWM_OUT, -- IEC bus IEC_ATN => IEC_ATN, IEC_DATA => IEC_DATA, IEC_CLOCK => IEC_CLOCK, IEC_RESET => IEC_RESET, IEC_SRQ_IN => IEC_SRQ_IN, DISK_ACTn => DISK_ACTn, -- activity LED CART_LEDn => CART_LEDn, SDACT_LEDn => SDACT_LEDn, MOTOR_LEDn => MOTOR_LEDn, -- Debug UART UART_TXD => UART_TXD, UART_RXD => UART_RXD, -- USB USB_IOP => open, USB_ION => open, USB_SEP => '1', USB_SEN => '0', USB_DET => open, -- SD Card Interface SD_SSn => SD_SSn, SD_CLK => SD_CLK, SD_MOSI => SD_MOSI, SD_MISO => SD_MISO, SD_WP => '0', SD_CARDDETn => SD_CARDDETn, -- Cassette Interface CAS_MOTOR => CAS_MOTOR, CAS_SENSE => CAS_SENSE, CAS_READ => CAS_READ, CAS_WRITE => CAS_WRITE, -- Ethernet Interface ETH_CLK => ETH_CLK, ETH_IRQ => '0', ETH_CSn => ETH_CSn, ETH_CS => ETH_CS, ETH_RST => ETH_RST, ONE_WIRE => ONE_WIRE, -- Buttons BUTTON => BUTTON ); sys_clock <= not sys_clock after 10 ns; -- 50 MHz sys_reset <= '1', '0' after 100 ns; PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz RSTn <= '0', '1' after 6 us; process begin bind_mem_model("intram", ram); bind_mem_model("dram", dram); bind_mem_model("sram", sram); load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000"); load_memory("../../software/ultimate/result/ultimate_V1.bin", sram, X"00030000"); wait; end process; SLOT_DATA <= (others => 'H'); ROMHn <= '1'; ROMLn <= not PHI2 after 50 ns; IO1n <= '1'; IO2n <= '1'; process begin SLOT_ADDR <= X"7FF0"; RWn <= '1'; while true loop wait until PHI2 = '0'; --SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1); SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1); RWn <= '1'; wait until PHI2 = '0'; RWn <= '0'; end loop; end process; process begin BA <= '1'; for i in 0 to 100 loop wait until PHI2='0'; end loop; BA <= '0'; for i in 0 to 10 loop wait until PHI2='0'; end loop; end process; sram_bfm: entity work.sram_model_8 generic map("sram", 19, 10 ns) port map (LB_ADDR(18 downto 0), LB_DATA, SRAM_CSn, MEM_OEn, MEM_WEn); flash_bfm: entity work.sram_model_8 generic map("flash", 21, 70 ns) port map (LB_ADDR(20 downto 0), LB_DATA, FLASH_CSn, MEM_OEn, '1'); dram_bfm: entity work.dram_model_8 generic map( g_given_name => "dram", g_cas_latency => 2, g_burst_len_r => 1, g_burst_len_w => 1, g_column_bits => 10, g_row_bits => 13, g_bank_bits => 2 ) port map ( CLK => SDRAM_CLK, CKE => SDRAM_CKE, A => LB_ADDR(12 downto 0), BA => LB_ADDR(14 downto 13), CSn => SDRAM_CSn, RASn => SDRAM_RASn, CASn => SDRAM_CASn, WEn => SDRAM_WEn, DQM => SDRAM_DQM, DQ => LB_DATA); -- assert not (ADDRESS(18 downto 16)="011" and ADDRESS(15 downto 0)=X"86A0" and SRAM_CSn='0' and MEM_WEn='0') -- report "writing to jump address." -- severity failure; -- sram: entity work.sram_model_8 -- generic map("sram", 19, 10 ns) -- port map (LB_ADDR(18 downto 0), LB_DATA, SRAM_CSn, MEM_OEn, MEM_WEn); -- -- flash: entity work.sram_model_8 -- generic map("flash", 21, 70 ns) -- port map (LB_ADDR(20 downto 0), LB_DATA, FLASH_CSn, MEM_OEn, '1'); -- process(ETH_CS, ETH_CSn, LB_ADDR) -- begin -- if ETH_CS='1' and ETH_CSn='0' then -- LB_DATA <= not LB_ADDR(7 downto 0) after 135 ns; -- else -- LB_DATA <= (others => 'Z') after 50 ns; -- end if; -- end process; i_rx: entity work.rx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, rxd => UART_TXD, rxchar => rx_char, rx_ack => rx_ack ); i_tx: entity work.tx generic map (c_uart_divisor) port map ( clk => sys_clock, reset => sys_reset, dotx => do_tx, txchar => tx_char, done => tx_done, txd => UART_RXD ); process(sys_clock) begin if rising_edge(sys_clock) then if rx_ack='1' then rx_char_d <= rx_char; end if; end if; end process; process procedure send_char(i: std_logic_vector(7 downto 0)) is begin if tx_done /= '1' then wait until tx_done = '1'; end if; wait until sys_clock='1'; tx_char <= i; do_tx <= '1'; wait until tx_done = '0'; wait until sys_clock='1'; do_tx <= '0'; end procedure; procedure send_string(i : string) is variable b : std_logic_vector(7 downto 0); begin for n in i'range loop b := std_logic_vector(to_unsigned(character'pos(i(n)), 8)); send_char(b); end loop; send_char(X"0d"); send_char(X"0a"); end procedure; begin wait for 2 ms; --send_string("wd 4005000 12345678"); send_string("run"); -- send_string("m 100000"); -- send_string("w 400000F 4"); wait; end process; -- check timing data process(PHI2) begin if falling_edge(PHI2) then assert SLOT_DATA'last_event >= 189 ns report "Timing error on C64 bus." severity error; end if; end process; end tb;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/ip/srl_fifo/vhdl_source/srl_fifo.vhd

3

3787

------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2004, Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Small Synchronous Fifo Using SRL16 ------------------------------------------------------------------------------- -- File : srl_fifo.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This implementation makes use of the SRL16 properties, -- implementing a 16-deep synchronous fifo in only one LUT per -- bit. It is a fall-through fifo. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity srl_fifo is generic (Width : integer := 32; Depth : integer := 15; -- 15 is the maximum Threshold : integer := 13); port ( clock : in std_logic; reset : in std_logic; GetElement : in std_logic; PutElement : in std_logic; FlushFifo : in std_logic; DataIn : in std_logic_vector(Width-1 downto 0); DataOut : out std_logic_vector(Width-1 downto 0); SpaceInFifo : out std_logic; AlmostFull : out std_logic; DataInFifo : out std_logic); end SRL_fifo; architecture Gideon of srl_fifo is signal NumElements : std_logic_vector(3 downto 0); signal FilteredGet : std_logic; signal FilteredPut : std_logic; signal DataInFifo_i : std_logic; signal SpaceInFifo_i : std_logic; constant Depth_std : std_logic_vector(3 downto 0) := conv_std_logic_vector(Depth-1, 4); begin FilteredGet <= DataInFifo_i and GetElement; FilteredPut <= SpaceInFifo_i and PutElement; DataInFifo <= DataInFifo_i; SpaceInFifo <= SpaceInFifo_i; process(clock) variable NewCnt : std_logic_vector(3 downto 0);--integer range 0 to Depth; begin if rising_edge(clock) then if FlushFifo='1' then NewCnt := "1111"; --0; elsif (FilteredGet='1') and (FilteredPut='0') then NewCnt := NumElements - 1; elsif (FilteredGet='0') and (FilteredPut='1') then NewCnt := NumElements + 1; else NewCnt := NumElements; end if; NumElements <= NewCnt; if (NewCnt > Threshold) and (NewCnt /= "1111") then AlmostFull <= '1'; else AlmostFull <= '0'; end if; if (NewCnt = "1111") then DataInFifo_i <= '0'; else DataInFifo_i <= '1'; end if; if (NewCnt /= Depth_std) then SpaceInFifo_i <= '1'; else SpaceInFifo_i <= '0'; end if; if Reset='1' then NumElements <= "1111"; SpaceInFifo_i <= '1'; DataInFifo_i <= '0'; AlmostFull <= '0'; end if; end if; end process; SRLs : for srl2 in 0 to Width-1 generate i_SRL : SRL16E port map ( CLK => clock, CE => FilteredPut, D => DataIn(srl2), A3 => NumElements(3), A2 => NumElements(2), A1 => NumElements(1), A0 => NumElements(0), Q => DataOut(srl2) ); end generate; end Gideon;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/zpu/vhdl_source/zpu_8bit_loadb.vhd

5

33125

------------------------------------------------------------------------------ ---- ---- ---- ZPU 8-bit version ---- ---- ---- ---- http://www.opencores.org/ ---- ---- ---- ---- Description: ---- ---- ZPU is a 32 bits small stack cpu. This is a modified version of ---- ---- the zpu_small implementation. This one has only one 8-bit external ---- ---- memory port, which is used for I/O, instruction fetch and data ---- ---- accesses. It is intended to interface with existing 8-bit systems, ---- ---- while maintaining the large addressing range and 32-bit programming ---- ---- model. The 32-bit stack remains "internal" in the ZPU. ---- ---- ---- ---- This version is about the same size as zpu_small from zealot, ---- ---- but performs 25% better at the same clock speed, given that the ---- ---- external memory bus can operate with 0 wait states. The performance ---- ---- increase is due to the fact that most instructions only require 3 ---- ---- clock cycles instead of 4. ---- ---- ---- ---- Author: ---- ---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ---- ---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ---- ---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ---- ---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ---- ---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ---- ---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ---- ---- ---- ---- Distributed under the BSD license ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Design unit: zpu_8bit_loadb(Behave) (Entity and architecture) ---- ---- File name: zpu_8bit_loadb.vhdl ---- ---- Note: None ---- ---- Limitations: None known ---- ---- Errors: None known ---- ---- Library: work ---- ---- Dependencies: ieee.std_logic_1164 ---- ---- ieee.numeric_std ---- ---- work.zpupkg ---- ---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ---- ---- Language: VHDL ---- ---- Wishbone: No ---- ---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ---- ---- Simulation tools: Modelsim ---- ---- Text editor: UltraEdit 11.00a+ ---- ---- ---- ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.zpupkg.all; --use work.tl_string_util_pkg.all; entity zpu_8bit_loadb is generic( g_addr_size : integer := 16; -- Total address space width (incl. I/O) g_stack_size : integer := 12; -- Memory (stack+data) width g_prog_size : integer := 14; -- Program size g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0' port( clk_i : in std_logic; -- System Clock reset_i : in std_logic; -- Synchronous Reset interrupt_i : in std_logic; -- Interrupt break_o : out std_logic; -- Breakpoint opcode executed -- synthesis translate_off dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log) -- synthesis translate_on -- BRAM (stack ONLY) a_en_o : out std_logic; a_we_o : out std_logic; -- BRAM A port Write Enable a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port a_i : in unsigned(31 downto 0); -- Data from BRAM A port b_en_o : out std_logic; b_we_o : out std_logic; -- BRAM B port Write Enable b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port b_i : in unsigned(31 downto 0); -- Data from BRAM B port -- memory port for text, bss, data c_req_o : out std_logic; -- request output c_inst_o : out std_logic; -- indicates request is for opcode (program data) c_we_o : out std_logic; -- write c_size_o : out std_logic_vector(1 downto 0); -- indicates size of transfer 00=byte, 11=dword c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0'); c_rack_i : in std_logic; -- request acknowledge c_dack_i : in std_logic; -- data acknowledge (read only) c_data_i : in std_logic_vector(c_opcode_width-1 downto 0); c_data_o : out std_logic_vector(c_opcode_width-1 downto 0) ); end entity zpu_8bit_loadb; architecture Behave of zpu_8bit_loadb is constant c_max_addr_bit : integer:=g_addr_size-1; -- Stack Pointer initial value: BRAM size-8 constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size); constant c_sp_start : unsigned(g_stack_size-1 downto 2):= c_sp_start_1(g_stack_size-1 downto 2); -- Program counter signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0'); -- Stack pointer signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start; signal idim_r : std_logic:='0'; -- BRAM (stack) -- a_r is a register for the top of the stack [SP] -- Note: as this is a stack CPU this is a very important register. signal a_we_r : std_logic:='0'; signal a_en_r : std_logic:='0'; signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal a_r : unsigned(31 downto 0):=(others => '0'); -- b_r is a register for the next value in the stack [SP+1] signal b_we_r : std_logic:='0'; signal b_en_r : std_logic:='0'; signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0'); signal b_r : unsigned(31 downto 0):=(others => '0'); signal c_we_r : std_logic := '0'; signal c_req_r : std_logic := '0'; signal c_mux_r : std_logic := '0'; signal c_mux_d : std_logic := '0'; signal byte_req_cnt : unsigned(1 downto 0) := "00"; signal byte_ack_cnt : unsigned(1 downto 0) := "00"; signal posted_wr_a : std_logic := '0'; -- State machine. type state_t is (st_fetch, st_execute, st_add, st_or, st_compare, st_loadb2, st_and, st_store, st_read_mem, st_write_mem, st_add_sp, st_decode, st_resync); signal state : state_t:=st_fetch; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "one-hot"; -- Decoded Opcode type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp, dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_pop_int, dec_add, dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store, dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb, dec_neqbranch, dec_compare); signal d_opcode_r : decode_t; signal d_opcode : decode_t; signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered -- IRQ flag signal in_irq_r : std_logic:='0'; -- I/O space address signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0'); -- helper signals for compare instructions signal compare_dec : std_logic_vector(2 downto 0); signal compare_oper : std_logic_vector(2 downto 0); signal compare_bool : boolean; signal compare_res : unsigned(31 downto 0); begin a_en_o <= a_en_r; b_en_o <= b_en_r; c_req_o <= '1' when state = st_fetch else c_req_r; -- Dual ported memory interface a_we_o <= a_we_r; a_addr_o <= a_addr_r(g_stack_size-1 downto 2); a_o <= a_r; b_we_o <= b_we_r; b_addr_o <= b_addr_r(g_stack_size-1 downto 2); b_o <= b_r; opcode <= unsigned(c_data_i); c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0' else addr_r; c_we_o <= c_we_r; c_inst_o <= not c_mux_r; ------------------------- -- Instruction Decoder -- ------------------------- -- Note: We use a separate memory port to fetch opcodes. decode_control: process(opcode) begin compare_dec <= "000"; -- synthesis translate_off if opcode(0)='Z' then d_opcode <= dec_nop; else -- synthesis translate_on if (opcode(7 downto 7)=OPCODE_IM) then d_opcode <= dec_im; elsif (opcode(7 downto 5)=OPCODE_STORESP) then d_opcode <= dec_store_sp; elsif (opcode(7 downto 5)=OPCODE_LOADSP) then d_opcode <= dec_load_sp; elsif (opcode(7 downto 5)=OPCODE_EMULATE) then case opcode(5 downto 0) is when OPCODE_LOADB => d_opcode <= dec_loadb; when OPCODE_STOREB => d_opcode <= dec_storeb; when OPCODE_NEQBRANCH => d_opcode <= dec_neqbranch; when OPCODE_EQ => d_opcode <= dec_compare; compare_dec <= "001"; when OPCODE_LESSTHAN => -- 00 d_opcode <= dec_compare; compare_dec <= "100"; when OPCODE_LESSTHANOREQUAL => -- 01 d_opcode <= dec_compare; compare_dec <= "101"; when OPCODE_ULESSTHAN => -- 10 d_opcode <= dec_compare; compare_dec <= "110"; when OPCODE_ULESSTHANOREQUAL => -- 11 d_opcode <= dec_compare; compare_dec <= "111"; when others => d_opcode <= dec_emulate; end case; elsif (opcode(7 downto 4)=OPCODE_ADDSP) then d_opcode <= dec_add_sp; else -- OPCODE_SHORT case opcode(3 downto 0) is when OPCODE_BREAK => d_opcode <= dec_break; when OPCODE_PUSHSP => d_opcode <= dec_push_sp; when OPCODE_POPPC => d_opcode <= dec_pop_pc; when OPCODE_ADD => d_opcode <= dec_add; when OPCODE_OR => d_opcode <= dec_or; when OPCODE_AND => d_opcode <= dec_and; when OPCODE_LOAD => d_opcode <= dec_load; when OPCODE_NOT => d_opcode <= dec_not; when OPCODE_FLIP => d_opcode <= dec_flip; when OPCODE_STORE => d_opcode <= dec_store; when OPCODE_POPSP => d_opcode <= dec_pop_sp; when OPCODE_POPINT => d_opcode <= dec_pop_int; when others => -- OPCODE_NOP and others d_opcode <= dec_nop; end case; end if; -- synthesis translate_off end if; -- synthesis translate_on end process decode_control; opcode_control: process (clk_i) variable sp_offset : unsigned(4 downto 0); procedure emulate is begin sp_r <= sp_r-1; a_we_r <= '1'; a_en_r <= '1'; a_addr_r <= sp_r-1; a_r <= (others => '0'); -- could be changed to don't care a_r(pc_r'range) <= pc_r+1; -- Jump to NUM*32 -- The emulate address is: -- 98 7654 3210 -- 0000 00aa aaa0 0000 pc_r <= (others => '0'); pc_r(9 downto 5) <= opcode_r(4 downto 0); end procedure; procedure execute_def is begin state <= st_fetch; -- At this point: -- a_i contains top of stack, b_i contains next-to-top of stack pc_r <= pc_r+1; -- increment by default -- synthesis translate_off -- Debug info (Trace) dbg_o.b_inst <= '1'; dbg_o.pc <= (others => '0'); dbg_o.pc(g_prog_size-1 downto 0) <= pc_r; dbg_o.opcode <= opcode_r; dbg_o.sp <= (others => '0'); dbg_o.sp(g_stack_size-1 downto 2) <= sp_r; dbg_o.stk_a <= a_i; dbg_o.stk_b <= b_i; -- synthesis translate_on -- During the next cycle we'll be reading the next opcode sp_offset(4):=not opcode_r(4); sp_offset(3 downto 0):=opcode_r(3 downto 0); idim_r <= '0'; end procedure; begin if rising_edge(clk_i) then break_o <= '0'; -- synthesis translate_off dbg_o.b_inst <= '0'; -- synthesis translate_on posted_wr_a <= '0'; c_we_r <= '0'; c_mux_d <= c_mux_r; d_opcode_r <= d_opcode; opcode_r <= opcode; a_we_r <= '0'; b_we_r <= '0'; a_en_r <= '0'; b_en_r <= '0'; a_r <= (others => g_dont_care); -- output register b_r <= (others => g_dont_care); a_addr_r <= (others => g_dont_care); b_addr_r <= (others => g_dont_care); addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2); case state is when st_fetch => -- During this cycle -- we'll fetch the opcode @ pc and thus it will -- be available for st_execute in the next cycle -- At this point a_i contains the value that is from the top of the stack -- or that was fetched from the stack with an offset (loadsp) a_r <= a_i; if c_rack_i='1' then -- our request for instr has been seen -- by default, we need the two values of the stack, so we'll fetch them as well a_we_r <= posted_wr_a; a_addr_r <= sp_r; a_en_r <= '1'; b_addr_r <= sp_r+1; b_en_r <= '1'; state <= st_decode; else posted_wr_a <= posted_wr_a; -- hold end if; when st_decode => compare_oper <= compare_dec; if c_dack_i='1' then if interrupt_i='1' and in_irq_r='0' and idim_r='0' then -- We got an interrupt, execute interrupt instead of next instruction in_irq_r <= '1'; d_opcode_r <= dec_interrupt; -- override end if; state <= st_execute; end if; when st_execute => execute_def; -------------------- -- Execution Unit -- -------------------- case d_opcode_r is when dec_interrupt => -- Not a real instruction, but an interrupt -- Push(PC); PC=32 sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_we_r <= '1'; a_en_r <= '1'; a_r <= (others => g_dont_care); a_r(pc_r'range) <= pc_r; -- Jump to ISR pc_r <= to_unsigned(32, pc_r'length); -- interrupt address --report "ZPU jumped to interrupt!" severity note; when dec_im => idim_r <= '1'; a_we_r <= '1'; a_en_r <= '1'; if idim_r='0' then -- First IM -- Push the 7 bits (extending the sign) sp_r <= sp_r-1; a_addr_r <= sp_r-1; a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32)); else -- Next IMs, shift the word and put the new value in the lower -- bits a_addr_r <= sp_r; a_r(31 downto 7) <= a_i(24 downto 0); a_r(6 downto 0) <= opcode_r(6 downto 0); end if; when dec_store_sp => -- [SP+Offset]=Pop() b_we_r <= '1'; b_en_r <= '1'; b_addr_r <= sp_r+sp_offset; b_r <= a_i; sp_r <= sp_r+1; state <= st_fetch; -- was resync when dec_load_sp => -- Push([SP+Offset]) sp_r <= sp_r-1; a_addr_r <= sp_r+sp_offset; a_en_r <= '1'; posted_wr_a <= '1'; state <= st_resync; -- extra delay to fetch from A when dec_emulate => -- Push(PC+1), PC=Opcode[4:0]*32 emulate; when dec_add_sp => -- Push(Pop()+[SP+Offset]) b_addr_r <= sp_r+sp_offset; b_en_r <= '1'; state <= st_add_sp; when dec_break => --report "Break instruction encountered" severity failure; break_o <= '1'; when dec_push_sp => -- Push(SP) sp_r <= sp_r-1; a_we_r <= '1'; a_addr_r <= sp_r-1; a_en_r <= '1'; a_r <= (others => '0'); a_r(sp_r'range) <= sp_r; a_r(31) <= '1'; -- Mark this address as a stack address when dec_pop_pc => -- Pop(PC) pc_r <= a_i(pc_r'range); sp_r <= sp_r+1; state <= st_fetch; -- was resync when dec_pop_int => -- Pop(PC) in_irq_r <= '0'; -- no longer in an interrupt pc_r <= a_i(pc_r'range); sp_r <= sp_r+1; state <= st_fetch; -- was resync when dec_compare => -- Push(Compare(Pop()+Pop()) sp_r <= sp_r+1; state <= st_compare; when dec_add => -- Push(Pop()+Pop()) sp_r <= sp_r+1; state <= st_add; when dec_or => -- Push(Pop() or Pop()) sp_r <= sp_r+1; state <= st_or; when dec_and => -- Push(Pop() and Pop()) sp_r <= sp_r+1; state <= st_and; when dec_not => -- Push(not(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= not a_i; when dec_flip => -- Push(flip(Pop())) a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; for i in 0 to 31 loop a_r(i) <= a_i(31-i); end loop; when dec_loadb => addr_r <= a_i(g_addr_size-1 downto 0); if a_i(31)='1' then -- stack a_addr_r <= a_i(a_addr_r'range); a_en_r <= '1'; state <= st_loadb2; else a_r <= (others => '0'); c_req_r <= '1'; c_mux_r <= '1'; byte_req_cnt <= "00"; -- 1 byte byte_ack_cnt <= "00"; c_size_o <= "00"; state <= st_read_mem; end if; when dec_load => -- Push([Pop()]) addr_r(1 downto 0) <= a_i(1 downto 0);-- xor "11"; if a_i(31)='1' then -- stack a_addr_r <= a_i(a_addr_r'range); a_en_r <= '1'; posted_wr_a <= '1'; state <= st_resync; else -- report "Load: " & hstr(a_i); c_req_r <= '1'; -- output memory request c_mux_r <= '1'; -- output correct address byte_req_cnt <= "11"; -- 4 bytes byte_ack_cnt <= "11"; c_size_o <= "11"; state <= st_read_mem; end if; when dec_store => sp_r <= sp_r+1; addr_r(1 downto 0) <= a_i(1 downto 0); if a_i(31) = '1' then state <= st_store; else -- a=Pop(), b=Pop(), [a]=b state <= st_write_mem; byte_req_cnt <= "11"; -- 4 bytes c_size_o <= "11"; end if; when dec_storeb => if a_i(31) = '1' then emulate; else -- a=Pop(), b=Pop(), [a]=b sp_r <= sp_r+1; addr_r(1 downto 0) <= a_i(1 downto 0); c_size_o <= "00"; byte_req_cnt <= "00"; -- 1 byte state <= st_write_mem; end if; when dec_pop_sp => -- SP=Pop() sp_r <= a_i(g_stack_size-1 downto 2); state <= st_fetch; -- was resync when dec_neqbranch => -- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a -- Branches are almost always taken as they form loops sp_r <= sp_r + 2; -- Need to fetch stack again. state <= st_resync; if b_i/=0 then pc_r <= pc_r + a_i(pc_r'range); end if; when others => -- includes 'nop' null; end case; when st_loadb2 => -- select the correct stack byte if a_en_r='0' then -- wait one cycle until BRAM data is available a_r <= (others => '0'); case addr_r(1 downto 0) is when "11" => a_r( 7 downto 0) <= a_i( 7 downto 0); when "10" => a_r( 7 downto 0) <= a_i(15 downto 8); when "01" => a_r( 7 downto 0) <= a_i(23 downto 16); when "00" => a_r( 7 downto 0) <= a_i(31 downto 24); when others => null; end case; -- report "LoadB: " & hstr(a_i) & ", addr: " & hstr(addr_r(1 downto 0)); -- a_r <= a_i; -- dummy a_addr_r <= sp_r; a_en_r <= '1'; a_we_r <= '1'; state <= st_fetch; end if; when st_store => sp_r <= sp_r+1; -- for a store we need to pop 2! a_we_r <= '1'; a_en_r <= '1'; a_addr_r <= a_i(g_stack_size-1 downto 2); a_r <= b_i; state <= st_fetch; -- was resync -- when st_storeb => -- sp_r <= sp_r+1; -- for a store we need to pop 2! -- a_we_r <= '1'; -- a_en_r <= '1'; -- a_addr_r <= a_i(g_stack_size-1 downto 2); -- a_r <= b_i(7 downto 0) & b_i(7 downto 0) & b_i(7 downto 0) & b_i(7 downto 0); -- state <= st_fetch; -- was resync when st_read_mem => -- BIG ENDIAN a_r <= a_r; -- stay put, as we are filling it byte by byte! if c_dack_i = '1' then byte_ack_cnt <= byte_ack_cnt - 1; case byte_ack_cnt is when "00" => -- report "Returning " & hstr(a_r(31 downto 8)) & hstr(c_data_i) & -- " while reading from " & hstr(addr_r); a_r(7 downto 0) <= unsigned(c_data_i); a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; state <= st_fetch; when "01" => a_r(15 downto 8) <= unsigned(c_data_i); when "10" => a_r(23 downto 16) <= unsigned(c_data_i); when others => -- 11 a_r(31 downto 24) <= unsigned(c_data_i); end case; end if; if c_rack_i='1' then addr_r(1 downto 0) <= addr_r(1 downto 0) + 1; byte_req_cnt <= byte_req_cnt - 1; if byte_req_cnt = "00" then c_req_r <= '0'; c_mux_r <= '0'; end if; end if; when st_write_mem => c_req_r <= '1'; c_mux_r <= '1'; c_we_r <= '1'; -- Note: Output data is muxed outside of this process if c_rack_i='1' then addr_r(1 downto 0) <= addr_r(1 downto 0) + 1; byte_req_cnt <= byte_req_cnt - 1; if byte_req_cnt = "00" then sp_r <= sp_r+1; -- add another to sp. c_mux_r <= '0'; c_req_r <= '0'; c_we_r <= '0'; state <= st_fetch; -- was resync end if; end if; when st_add_sp => state <= st_add; when st_compare => a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= compare_res; state <= st_fetch; when st_add => a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= a_i+b_i; state <= st_fetch; when st_or => a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= a_i or b_i; state <= st_fetch; when st_and => a_addr_r <= sp_r; a_we_r <= '1'; a_en_r <= '1'; a_r <= a_i and b_i; state <= st_fetch; when st_resync => a_addr_r <= sp_r; state <= st_fetch; posted_wr_a <= posted_wr_a; -- keep when others => null; end case; if reset_i='1' then state <= st_fetch; sp_r <= c_sp_start; pc_r <= (others => '0'); idim_r <= '0'; in_irq_r <= '0'; c_mux_r <= '0'; c_size_o <= "11"; end if; end if; -- rising_edge(clk_i) end process opcode_control; p_outmux: process(byte_req_cnt, b_i) begin case byte_req_cnt is when "00" => c_data_o <= std_logic_vector(b_i(7 downto 0)); when "01" => c_data_o <= std_logic_vector(b_i(15 downto 8)); when "10" => c_data_o <= std_logic_vector(b_i(23 downto 16)); when others => -- 11 c_data_o <= std_logic_vector(b_i(31 downto 24)); end case; end process; i_compare: entity work.zpu_compare port map ( a => a_i, b => b_i, oper => compare_oper, y => compare_bool ); compare_res <= X"00000001" when compare_bool else X"00000000"; end architecture Behave; -- Entity: zpu_8bit_loadb

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/usb/vhdl_source/ulpi_bus.vhd

3

7397

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ulpi_bus is port ( clock : in std_logic; reset : in std_logic; ULPI_DATA : inout std_logic_vector(7 downto 0); ULPI_DIR : in std_logic; ULPI_NXT : in std_logic; ULPI_STP : out std_logic; -- status status : out std_logic_vector(7 downto 0); -- register interface reg_read : in std_logic; reg_write : in std_logic; reg_address : in std_logic_vector(5 downto 0); reg_wdata : in std_logic_vector(7 downto 0); reg_ack : out std_logic; -- stream interface tx_data : in std_logic_vector(7 downto 0); tx_last : in std_logic; tx_valid : in std_logic; tx_start : in std_logic; tx_next : out std_logic; rx_data : out std_logic_vector(7 downto 0); rx_register : out std_logic; rx_last : out std_logic; rx_valid : out std_logic; rx_store : out std_logic ); attribute keep_hierarchy : string; attribute keep_hierarchy of ulpi_bus : entity is "yes"; end ulpi_bus; architecture gideon of ulpi_bus is signal ulpi_data_out : std_logic_vector(7 downto 0); signal ulpi_data_in : std_logic_vector(7 downto 0); signal ulpi_dir_d1 : std_logic; signal ulpi_dir_d2 : std_logic; signal ulpi_dir_d3 : std_logic; signal ulpi_nxt_d1 : std_logic; signal ulpi_nxt_d2 : std_logic; signal ulpi_nxt_d3 : std_logic; signal reg_cmd_d2 : std_logic; signal reg_cmd_d3 : std_logic; signal reg_cmd_d4 : std_logic; signal reg_cmd_d5 : std_logic; signal rx_reg_i : std_logic; signal tx_reg_i : std_logic; signal rx_status_i : std_logic; signal ulpi_stop : std_logic := '1'; signal ulpi_last : std_logic; type t_state is ( idle, reading, writing, writing_data, transmit ); signal state : t_state; attribute iob : string; attribute iob of ulpi_data_in : signal is "true"; attribute iob of ulpi_dir_d1 : signal is "true"; attribute iob of ulpi_nxt_d1 : signal is "true"; attribute iob of ulpi_data_out : signal is "true"; attribute iob of ULPI_STP : signal is "true"; begin -- Marking incoming data based on next/dir pattern rx_data <= ulpi_data_in; rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1; rx_valid <= ulpi_dir_d1 and ulpi_dir_d2; rx_last <= not ulpi_dir_d1 and ulpi_dir_d2; rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i; rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and (not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and reg_cmd_d5; rx_register <= rx_reg_i; reg_ack <= rx_reg_i or tx_reg_i; p_sample: process(clock, reset) begin if rising_edge(clock) then ulpi_data_in <= ULPI_DATA; reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6); reg_cmd_d3 <= reg_cmd_d2; reg_cmd_d4 <= reg_cmd_d3; reg_cmd_d5 <= reg_cmd_d4; ulpi_dir_d1 <= ULPI_DIR; ulpi_dir_d2 <= ulpi_dir_d1; ulpi_dir_d3 <= ulpi_dir_d2; ulpi_nxt_d1 <= ULPI_NXT; ulpi_nxt_d2 <= ulpi_nxt_d1; ulpi_nxt_d3 <= ulpi_nxt_d2; if rx_status_i='1' then status <= ulpi_data_in; end if; if reset='1' then status <= (others => '0'); end if; end if; end process; p_tx_state: process(clock, reset) begin if rising_edge(clock) then ulpi_stop <= '0'; tx_reg_i <= '0'; case state is when idle => ulpi_data_out <= X"00"; if reg_read='1' and rx_reg_i='0' then ulpi_data_out <= "11" & reg_address; state <= reading; elsif reg_write='1' and tx_reg_i='0' then ulpi_data_out <= "10" & reg_address; state <= writing; elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then ulpi_data_out <= tx_data; ulpi_last <= tx_last; state <= transmit; end if; when reading => if rx_reg_i='1' then ulpi_data_out <= X"00"; state <= idle; end if; if ulpi_dir_d1='1' then state <= idle; -- terminate current tx ulpi_data_out <= X"00"; end if; when writing => if ULPI_NXT='1' then ulpi_data_out <= reg_wdata; state <= writing_data; end if; if ulpi_dir_d1='1' then state <= idle; -- terminate current tx ulpi_data_out <= X"00"; end if; when writing_data => if ULPI_NXT='1' and ULPI_DIR='0' then tx_reg_i <= '1'; ulpi_stop <= '1'; state <= idle; end if; if ulpi_dir_d1='1' then state <= idle; -- terminate current tx ulpi_data_out <= X"00"; end if; when transmit => if ULPI_NXT = '1' then if ulpi_last='1' or tx_valid = '0' then ulpi_data_out <= X"00"; ulpi_stop <= '1'; state <= idle; else ulpi_data_out <= tx_data; ulpi_last <= tx_last; end if; end if; when others => null; end case; if reset='1' then state <= idle; ulpi_stop <= '0'; ulpi_last <= '0'; end if; end if; end process; p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write) begin case state is when idle => tx_next <= not ULPI_DIR and tx_valid and tx_start; if reg_read='1' and rx_reg_i='0' then tx_next <= '0'; end if; if reg_write='1' and tx_reg_i='0' then tx_next <= '0'; end if; when transmit => tx_next <= ULPI_NXT and tx_valid and not ulpi_last; when others => tx_next <= '0'; end case; end process; ULPI_STP <= ulpi_stop; ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z'); end gideon;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/mem_ctrl/vhdl_sim/ext_mem_test_32_tb.vhd

5

7761

------------------------------------------------------------------------------- -- Title : External Memory controller for SDRAM ------------------------------------------------------------------------------- -- Description: This module implements a simple, single burst memory controller. -- User interface is 32 bit (burst of 2), externally 8x 8 bit. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.vital_timing.all; library work; use work.mem_bus_pkg.all; entity ext_mem_test_32_tb is end ext_mem_test_32_tb; architecture tb of ext_mem_test_32_tb is signal clock : std_logic := '1'; signal clk_2x : std_logic := '1'; signal reset : std_logic := '0'; signal inhibit : std_logic := '0'; signal is_idle : std_logic := '0'; signal req_16 : t_mem_burst_16_req := c_mem_burst_16_req_init; signal resp_16 : t_mem_burst_16_resp; signal req_32 : t_mem_burst_32_req := c_mem_burst_32_req_init; signal resp_32 : t_mem_burst_32_resp; signal okay : std_logic; signal SDRAM_CLK : std_logic; signal SDRAM_CKE : std_logic; signal SDRAM_CSn : std_logic := '1'; signal SDRAM_RASn : std_logic := '1'; signal SDRAM_CASn : std_logic := '1'; signal SDRAM_WEn : std_logic := '1'; signal SDRAM_DQM : std_logic := '0'; signal SDRAM_A : std_logic_vector(12 downto 0); signal SDRAM_BA : std_logic_vector(1 downto 0); signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z'); signal logic_CLK : std_logic; signal logic_CKE : std_logic; signal logic_CSn : std_logic := '1'; signal logic_RASn : std_logic := '1'; signal logic_CASn : std_logic := '1'; signal logic_WEn : std_logic := '1'; signal logic_DQM : std_logic := '0'; signal logic_A : std_logic_vector(12 downto 0); signal logic_BA : std_logic_vector(1 downto 0); signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H'); signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H'); constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns ); begin clock <= not clock after 10.2 ns; clk_2x <= not clk_2x after 5.1 ns; reset <= '1', '0' after 100 ns; i_checker: entity work.ext_mem_test_32 port map ( clock => clock, reset => reset, req => req_32, resp => resp_32, okay => okay ); i_convert: entity work.mem_16to32 port map ( clock => clock, reset => reset, req_16 => req_16, resp_16 => resp_16, req_32 => req_32, resp_32 => resp_32 ); i_mut: entity work.ext_mem_ctrl_v6 generic map ( q_tcko_data => 5 ns, g_simulation => true ) port map ( clock => clock, clk_2x => clk_2x, reset => reset, inhibit => inhibit, is_idle => is_idle, req => req_16, resp => resp_16, SDRAM_CLK => logic_CLK, SDRAM_CKE => logic_CKE, SDRAM_CSn => logic_CSn, SDRAM_RASn => logic_RASn, SDRAM_CASn => logic_CASn, SDRAM_WEn => logic_WEn, SDRAM_DQM => logic_DQM, SDRAM_BA => logic_BA, SDRAM_A => logic_A, SDRAM_DQ => MEM_D ); i_sdram : entity work.mt48lc16m16a2 generic map( tipd_BA0 => c_wire_delay, tipd_BA1 => c_wire_delay, tipd_DQMH => c_wire_delay, tipd_DQML => c_wire_delay, tipd_DQ0 => c_wire_delay, tipd_DQ1 => c_wire_delay, tipd_DQ2 => c_wire_delay, tipd_DQ3 => c_wire_delay, tipd_DQ4 => c_wire_delay, tipd_DQ5 => c_wire_delay, tipd_DQ6 => c_wire_delay, tipd_DQ7 => c_wire_delay, tipd_DQ8 => c_wire_delay, tipd_DQ9 => c_wire_delay, tipd_DQ10 => c_wire_delay, tipd_DQ11 => c_wire_delay, tipd_DQ12 => c_wire_delay, tipd_DQ13 => c_wire_delay, tipd_DQ14 => c_wire_delay, tipd_DQ15 => c_wire_delay, tipd_CLK => c_wire_delay, tipd_CKE => c_wire_delay, tipd_A0 => c_wire_delay, tipd_A1 => c_wire_delay, tipd_A2 => c_wire_delay, tipd_A3 => c_wire_delay, tipd_A4 => c_wire_delay, tipd_A5 => c_wire_delay, tipd_A6 => c_wire_delay, tipd_A7 => c_wire_delay, tipd_A8 => c_wire_delay, tipd_A9 => c_wire_delay, tipd_A10 => c_wire_delay, tipd_A11 => c_wire_delay, tipd_A12 => c_wire_delay, tipd_WENeg => c_wire_delay, tipd_RASNeg => c_wire_delay, tipd_CSNeg => c_wire_delay, tipd_CASNeg => c_wire_delay, -- tpd delays tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ), tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ), -- -- tpw values: pulse widths -- tpw_CLK_posedge : VitalDelayType := UnitDelay; -- tpw_CLK_negedge : VitalDelayType := UnitDelay; -- -- tsetup values: setup times -- tsetup_DQ0_CLK : VitalDelayType := UnitDelay; -- -- thold values: hold times -- thold_DQ0_CLK : VitalDelayType := UnitDelay; -- -- tperiod_min: minimum clock period = 1/max freq -- tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- mem_file_name => "none", tpowerup => 100 ns ) port map( BA0 => logic_BA(0), BA1 => logic_BA(1), DQMH => dummy_dqm(1), DQML => logic_DQM, DQ0 => MEM_D(0), DQ1 => MEM_D(1), DQ2 => MEM_D(2), DQ3 => MEM_D(3), DQ4 => MEM_D(4), DQ5 => MEM_D(5), DQ6 => MEM_D(6), DQ7 => MEM_D(7), DQ8 => dummy_data(8), DQ9 => dummy_data(9), DQ10 => dummy_data(10), DQ11 => dummy_data(11), DQ12 => dummy_data(12), DQ13 => dummy_data(13), DQ14 => dummy_data(14), DQ15 => dummy_data(15), CLK => logic_CLK, CKE => logic_CKE, A0 => logic_A(0), A1 => logic_A(1), A2 => logic_A(2), A3 => logic_A(3), A4 => logic_A(4), A5 => logic_A(5), A6 => logic_A(6), A7 => logic_A(7), A8 => logic_A(8), A9 => logic_A(9), A10 => logic_A(10), A11 => logic_A(11), A12 => logic_A(12), WENeg => logic_WEn, RASNeg => logic_RASn, CSNeg => logic_CSn, CASNeg => logic_CASn ); end;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/fpga_top/video_fpga/vhdl_source/s3e_clockgen.vhd

5

4287

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity s3e_clockgen is port ( clk_50 : in std_logic; reset_in : in std_logic; dcm_lock : out std_logic; sys_clock : out std_logic; -- 50 MHz sys_reset : out std_logic; sys_shifted : out std_logic; pix_clock : out std_logic; -- * 7/25 (14 MHz) pix_clock_en: out std_logic; pix_reset : out std_logic ); end s3e_clockgen; architecture Gideon of s3e_clockgen is signal clk_in_buf : std_logic; signal sys_clk_buf : std_logic; signal reset_dcm : std_logic; signal reset_cnt : integer range 0 to 63 := 0; signal dcm1_locked : std_logic := '1'; signal sys_clk_i : std_logic := '0'; signal sysrst_cnt : integer range 0 to 63; signal sys_reset_i : std_logic := '1'; signal sys_reset_p : std_logic := '1'; signal pix_clock_pre : std_logic; signal pix_clock_ii : std_logic; signal pix_clock_i : std_logic; signal pixrst_cnt : integer range 0 to 63; signal pix_reset_i : std_logic := '1'; signal pix_reset_p : std_logic := '1'; signal pixdiv : integer range 0 to 7; signal reset_c : std_logic; signal reset_out : std_logic := '1'; attribute register_duplication : string; attribute register_duplication of sys_reset_i : signal is "no"; signal clk_0_pre : std_logic; signal clk_270_pre : std_logic; begin dcm_lock <= dcm1_locked; bufg_in : BUFG port map (I => clk_50, O => clk_in_buf); process(clk_in_buf) begin if rising_edge(clk_in_buf) then if reset_cnt = 63 then reset_dcm <= '0'; else reset_cnt <= reset_cnt + 1; reset_dcm <= '1'; end if; end if; if reset_in='1' then reset_dcm <= '1'; reset_cnt <= 0; end if; end process; dcm_shft: DCM generic map ( CLKIN_PERIOD => 20.0, -- CLKOUT_PHASE_SHIFT => "FIXED", CLK_FEEDBACK => "1X", -- PHASE_SHIFT => -20, CLKDV_DIVIDE => 2.5, CLKFX_MULTIPLY => 5, CLKFX_DIVIDE => 2, STARTUP_WAIT => true ) port map ( CLKIN => clk_in_buf, CLKFB => sys_clk_buf, CLK0 => clk_0_pre, CLK270 => clk_270_pre, CLKFX => pix_clock_pre, LOCKED => dcm1_locked, RST => reset_dcm ); bufg_pix: BUFG port map (I => pix_clock_pre, O => pix_clock_ii); bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf); bufg_shft: BUFG port map (I => clk_270_pre, O => sys_shifted); sys_clk_i <= sys_clk_buf; sys_clock <= sys_clk_buf; pix_clock <= pix_clock_ii; pix_clock_i <= pix_clock_ii; process(sys_clk_i, dcm1_locked) begin if rising_edge(sys_clk_i) then if sysrst_cnt = 63 then sys_reset_i <= '0'; else sysrst_cnt <= sysrst_cnt + 1; end if; sys_reset_p <= sys_reset_i; end if; if dcm1_locked='0' then sysrst_cnt <= 0; sys_reset_i <= '1'; sys_reset_p <= '1'; end if; end process; process(pix_clock_i, dcm1_locked) begin if rising_edge(pix_clock_i) then if pixdiv = 0 then pixdiv <= 4; pix_clock_en <= '1'; else pixdiv <= pixdiv - 1; pix_clock_en <= '0'; end if; if pixrst_cnt = 63 then pix_reset_i <= '0'; else pixrst_cnt <= pixrst_cnt + 1; end if; pix_reset_p <= pix_reset_i; end if; if dcm1_locked='0' then pixrst_cnt <= 0; pix_reset_i <= '1'; pix_reset_p <= '1'; end if; end process; sys_reset <= sys_reset_p; pix_reset <= pix_reset_p; end Gideon;

gpl-3.0

meaepeppe/FIR_ISA

VHDL/FIR_constants.vhd

1

609

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.math_real.all; PACKAGE FIR_constants IS CONSTANT Nb : INTEGER := 9; CONSTANT Ord: INTEGER := 8; CONSTANT UO: INTEGER := 1; CONSTANT Nbmult: INTEGER := 10; CONSTANT Nbadder: INTEGER:= Nb; --NUM_BITS_MULT + integer(floor(log2(real(FIR_ORDER+1)))); CONSTANT pipe_d: INTEGER := 0; CONSTANT IO_buffers: BOOLEAN := TRUE; CONSTANT CELLS_PIPE_STAGES: INTEGER := Ord +UO -1; TYPE IO_array IS ARRAY(UO-1 DOWNTO 0) OF STD_LOGIC_VECTOR(Nb-1 DOWNTO 0); END FIR_constants; PACKAGE BODY FIR_constants IS END PACKAGE BODY FIR_constants;

gpl-3.0

Project-Bonfire/EHA

RTL/Chip_Designs/IMMORTAL_Chip_2017/ZedBoard_FPGA/toppest_module.vhd

3

2951

--Copyright (C) 2016 Siavoosh Payandeh Azad ------------------------------------------------------------ -- This file is automatically generated! -- Here are the parameters: -- network size x: 2 -- network size y: 2 -- Data width: 32 -- Parity: False ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; USE ieee.numeric_std.ALL; use work.component_pack.all; entity toppest_module is generic (DATA_WIDTH: integer := 32; -- DATA_WIDTH_LV: integer := 11; memory_type : string := -- "TRI_PORT_X" -- "DUAL_PORT_" -- "ALTERA_LPM" "XILINX_16X" ); port ( reset: in std_logic; clk: in std_logic; -- IJTAG network for fault injection and checker status monitoring TCK : in std_logic; RST : in std_logic; SEL : in std_logic; SI : in std_logic; SE : in std_logic; UE : in std_logic; CE : in std_logic; SO : out std_logic; toF : out std_logic; toC : out std_logic; -- GPIO for Node 0 GPIO_out: out std_logic_vector(15 downto 0); GPIO_in: in std_logic_vector(14 downto 0); -- GPIO_in: in std_logic_vector(21 downto 15); --not enough inputs -- UART for all Plasmas uart_write_0 : out std_logic; uart_read_0 : in std_logic; uart_write_1 : out std_logic; uart_read_1 : in std_logic; uart_write_2 : out std_logic; uart_read_2 : in std_logic; uart_write_3 : out std_logic; uart_read_3 : in std_logic ); end toppest_module; architecture behavior of toppest_module is signal clk1_noc, clk2_ijtag : std_logic; begin noc2x2_inst: entity work.network_2x2_with_PE generic map ( DATA_WIDTH => DATA_WIDTH, DATA_WIDTH_LV => 0, --UNUSED memory_type => memory_type ) port map ( reset => (not reset), clk => clk1_noc, TCK => clk2_ijtag, RST => RST, SEL => SEL, SI => SI, SE => SE, UE => UE, CE => CE, SO => SO, toF => toF, toC => toC, GPIO_out => GPIO_out, GPIO_in => "0000000" & GPIO_in, --switch(0) == GPIO_in(0) ... uart_write_0 => uart_write_0, uart_read_0 => uart_read_0, uart_write_1 => uart_write_1, uart_read_1 => uart_read_1, uart_write_2 => uart_write_2, uart_read_2 => uart_read_2, uart_write_3 => uart_write_3, uart_read_3 => uart_read_3 ); clk_gen: entity work.clk_wiz_0 port map ( --in: clk_in1 => clk, --out: clk1_noc => clk1_noc, clk2_ijtag => clk2_ijtag); end;

gpl-3.0

Project-Bonfire/EHA

RTL/Router/credit_based/Checkers/Control_Part_Checkers/LBDR_packet_drop_checkers/Rxy_Reconf/RTL/Rxy_Reconf_pseudo.vhd

3

1147

--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity Rxy_Reconf_pseudo is port ( Rxy_reconf: in std_logic_vector(7 downto 0); ReConf_FF_out: in std_logic; Rxy: in std_logic_vector(7 downto 0); Reconfig : in std_logic; flit_type: in std_logic_vector(2 downto 0); grants: in std_logic; empty: in std_logic; Rxy_in: out std_logic_vector(7 downto 0); ReConf_FF_in: out std_logic ); end Rxy_Reconf_pseudo; architecture behavior of Rxy_Reconf_pseudo is begin process(Rxy_reconf, ReConf_FF_out, Rxy, Reconfig, flit_type, grants, empty) begin if ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' then Rxy_in <= Rxy_reconf; ReConf_FF_in <= '0'; else Rxy_in <= Rxy; if Reconfig = '1' then ReConf_FF_in <= '1'; else ReConf_FF_in <= ReConf_FF_out; end if; end if; end process; end;

gpl-3.0

Project-Bonfire/EHA

RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/LBDR_packet_drop_with_checkers/LBDR_packet_drop_with_checkers.vhd

3

28312

--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_packet_drop is generic ( cur_addr_rst: integer := 8; Rxy_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); faulty: in std_logic; packet_drop_order: out std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic; -- Checker outputs -- Routing part checkers err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order, -- Cx_Reconf checkers err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added -- Rxy_Reconf checkers err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end LBDR_packet_drop; architecture behavior of LBDR_packet_drop is signal Cx, Cx_in: std_logic_vector(3 downto 0); signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0); signal reconfig_cx, reconfig_cx_in: std_logic; signal ReConf_FF_in, ReConf_FF_out: std_logic; signal Rxy, Rxy_in: std_logic_vector(7 downto 0); signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0); signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal N1, E1, W1, S1 :std_logic :='0'; signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic; signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic; signal grants: std_logic; signal packet_drop, packet_drop_in: std_logic; -- Signal(s) required for checker(s) signal packet_drop_order_sig: std_logic; component LBDR_packet_drop_routing_part_pseudo_checkers is generic ( cur_addr_rst: integer := 8; Rxy_rst: integer := 8; Cx_rst: integer := 8; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); faulty: in std_logic; Cx: in std_logic_vector(3 downto 0); Rxy: in std_logic_vector(7 downto 0); packet_drop: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; grants: in std_logic; packet_drop_order: in std_logic; packet_drop_in: in std_logic; -- Checker outputs err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic ); end component; component Cx_Reconf_pseudo_checkers is port ( reconfig_cx: in std_logic; -- * flit_type: in std_logic_vector(2 downto 0); -- * empty: in std_logic; -- * grants: in std_logic; -- * Cx_in: in std_logic_vector(3 downto 0); -- * Temp_Cx: in std_logic_vector(3 downto 0); -- * reconfig_cx_in: in std_logic; -- * Cx: in std_logic_vector(3 downto 0); -- * Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added Reconfig_command : in std_logic; -- newly added Faulty_C_N: in std_logic; -- * Faulty_C_E: in std_logic; -- * Faulty_C_W: in std_logic; -- * Faulty_C_S: in std_logic; -- * Temp_Cx_in: in std_logic_vector(3 downto 0); -- * -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added ); end component; component Rxy_Reconf_pseudo_checkers is port ( ReConf_FF_out: in std_logic; Rxy: in std_logic_vector(7 downto 0); Rxy_tmp: in std_logic_vector(7 downto 0); Reconfig_command : in std_logic; flit_type: in std_logic_vector(2 downto 0); grants: in std_logic; empty: in std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Rxy_in: in std_logic_vector(7 downto 0); Rxy_tmp_in: in std_logic_vector(7 downto 0); ReConf_FF_in: in std_logic; err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end component; begin packet_drop_order <= packet_drop_order_sig; -- LBDR packet drop routing part checkers instantiation LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers generic map (cur_addr_rst => cur_addr_rst, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) port map ( empty => empty, flit_type => flit_type, Req_N_FF => Req_N_FF, Req_E_FF => Req_E_FF, Req_W_FF => Req_W_FF, Req_S_FF => Req_S_FF, Req_L_FF => Req_L_FF, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, dst_addr => dst_addr, faulty => faulty, Cx => Cx, Rxy => Rxy, packet_drop => packet_drop, N1_out => N1, E1_out => E1, W1_out => W1, S1_out => S1, Req_N_in => Req_N_in, Req_E_in => Req_E_in, Req_W_in => Req_W_in, Req_S_in => Req_S_in, Req_L_in => Req_L_in, grants => grants, packet_drop_order => packet_drop_order_sig, packet_drop_in => packet_drop_in, -- Checker outputs err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => err_grants_onehot, err_grants_mismatch => err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => err_packet_drop_order ); -- LBDR packet drop Cx Reconfiguration module checkers instantiation Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map ( reconfig_cx => reconfig_cx, flit_type => flit_type, empty => empty, grants => grants, Cx_in => Cx_in, Temp_Cx => Temp_Cx, reconfig_cx_in => reconfig_cx_in, Cx => Cx, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command => Reconfig_command, Faulty_C_N => Faulty_C_N, Faulty_C_E => Faulty_C_E, Faulty_C_W => Faulty_C_W, Faulty_C_S => Faulty_C_S, Temp_Cx_in => Temp_Cx_in, -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal ); -- LBDR packet drop Rxy Reconfiguration checkers instantiation Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers port map ( ReConf_FF_out => ReConf_FF_out, Rxy => Rxy, Rxy_tmp => Rxy_tmp, Reconfig_command => Reconfig_command, flit_type => flit_type, grants => grants, empty => empty, Rxy_reconf_PE => Rxy_reconf_PE, Rxy_in => Rxy_in, Rxy_tmp_in => Rxy_tmp_in, ReConf_FF_in => ReConf_FF_in, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); grants <= grant_N or grant_E or grant_W or grant_S or grant_L; cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0'; E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0'; W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0'; S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0'; process(clk, reset) begin if reset = '0' then Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length)); Rxy_tmp <= (others => '0'); Req_N_FF <= '0'; Req_E_FF <= '0'; Req_W_FF <= '0'; Req_S_FF <= '0'; Req_L_FF <= '0'; Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length)); Temp_Cx <= (others => '0'); ReConf_FF_out <= '0'; reconfig_cx <= '0'; packet_drop <= '0'; elsif clk'event and clk = '1' then Rxy <= Rxy_in; Rxy_tmp <= Rxy_tmp_in; Req_N_FF <= Req_N_in; Req_E_FF <= Req_E_in; Req_W_FF <= Req_W_in; Req_S_FF <= Req_S_in; Req_L_FF <= Req_L_in; ReConf_FF_out <= ReConf_FF_in; Cx <= Cx_in; reconfig_cx <= reconfig_cx_in; Temp_Cx <= Temp_Cx_in; packet_drop <= packet_drop_in; end if; end process; -- The combionational part process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty) begin if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then Rxy_tmp_in <= Rxy_tmp; Rxy_in <= Rxy_tmp; ReConf_FF_in <= '0'; else Rxy_in <= Rxy; if Reconfig_command = '1'then Rxy_tmp_in <= Rxy_reconf_PE; ReConf_FF_in <= '1'; else Rxy_tmp_in <= Rxy_tmp; ReConf_FF_in <= ReConf_FF_out; end if; end if; end process; process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin Temp_Cx_in <= Temp_Cx; if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then Cx_in <= Temp_Cx; reconfig_cx_in <= '0'; else Cx_in <= Cx; if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx; elsif Reconfig_command = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= Cx_reconf_PE; else reconfig_cx_in <= reconfig_cx; end if; end if; end process; Req_N <= Req_N_FF; Req_E <= Req_E_FF; Req_W <= Req_W_FF; Req_S <= Req_S_FF; Req_L <= Req_L_FF; process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop, faulty) begin packet_drop_in <= packet_drop; if flit_type = "001" and empty = '0' then Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0); Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1); Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2); Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3); if dst_addr = cur_addr then Req_L_in <= '1'; else Req_L_in <= '0'; end if; if faulty = '1' or (((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) = '0') and ((((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) = '0') and ((((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) = '0') and ((((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3)) = '0') and (dst_addr /= cur_addr)) then packet_drop_in <= '1'; Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; end if; elsif flit_type = "100" and empty = '0' and grants = '1' then Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; else Req_N_in <= Req_N_FF; Req_E_in <= Req_E_FF; Req_W_in <= Req_W_FF; Req_S_in <= Req_S_FF; Req_L_in <= Req_L_FF; end if; if flit_type = "100" and empty = '0' then if packet_drop = '1' then packet_drop_in <= '0'; end if; end if; end process; packet_drop_order_sig <= packet_drop; END;

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_dc_fwft_ext_as.vhd

9

12637

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gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/rd_dc_fwft_ext_as.vhd

9

12637

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block RvP9zZHkeFP18wLlGgDfVe/DTwIyMP7dhvzgCxp5m3YYL/LPCO9ICc+LBKqhQGhkjW48xpBAGwp3 rBBSE8qK6w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Qh1YkIKhLAJw+T0XBKcVE5CFy7U9clrK+8m4T/x0yjOoagdJeeO9PlbMa8zDeYYoZZutG5tu4t0N sS2pvvQBM2LCvmWTcVG3LWECd1SoSHNd1Q6UbLR4rRzrlUIDN4/JUR9PWghJqqumcUUJxnx5knEi K7afdfP3GWpa+Mc54+8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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gpl-3.0

Project-Bonfire/EHA

RTL/Chip_Designs/archive/IMMORTAL_Chip_2017/With_checkers/counter_threshold.vhd

6

3894

--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand -- This design is based on the proposed method, discussed in the following publication: -- "A Fault Prediction Module for a Fault Tolerant NoC Operation" -- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C. library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity counter_threshold_classifier is generic ( counter_depth: integer := 8; healthy_counter_threshold: integer := 4; faulty_counter_threshold: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; faulty_packet, Healthy_packet: in std_logic; Healthy, Intermittent, Faulty: out std_logic ); end counter_threshold_classifier; architecture behavior of counter_threshold_classifier is signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0); signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0); signal NET: std_logic; --no error threshold signal DET: std_logic; --detected error threshold signal reset_counters: std_logic; TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state); SIGNAL state, next_state : STATE_TYPE := Healthy_state; begin process(clk, reset)begin if reset = '0' then faulty_counter_out <= (others => '0'); healthy_counter_out <= (others => '0'); state <= Reset_state; elsif clk'event and clk = '1' then faulty_counter_out <= faulty_counter_in; healthy_counter_out <= healthy_counter_in; state <= next_state; end if; end process; process(faulty_packet, reset_counters, faulty_counter_out)begin if reset_counters = '1' then faulty_counter_in <= (others => '0'); elsif faulty_packet = '1' then faulty_counter_in <= faulty_counter_out + 1; else faulty_counter_in <= faulty_counter_out; end if; end process; process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin if reset_counters = '1' then healthy_counter_in <= (others => '0'); elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then healthy_counter_in <= healthy_counter_out + 1; else healthy_counter_in <= healthy_counter_out; end if; end process; process(healthy_counter_out, faulty_counter_out) begin reset_counters <= '0'; DET <= '0'; NET <= '0'; if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then NET <= '1'; reset_counters <= '1'; end if; if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then DET <= '1'; reset_counters <= '1'; end if; end process; process (NET, DET, state)begin Healthy <= '0'; Intermittent <= '0'; Faulty <= '0'; case state is when Healthy_state => if NET = '1' then next_state <= Healthy_state; elsif DET = '1' then next_state <= Intermittent_state; Intermittent <= '1'; else next_state <= Healthy_state; end if; when Intermittent_state => if NET = '1' then next_state <= Healthy_state; Healthy <= '1'; elsif DET = '1' then next_state <= Faulty_state; Faulty <= '1'; else next_state <= Intermittent_state; end if; when Faulty_state => next_state <= Faulty_state; when Reset_state => next_state <= Healthy_state; Healthy <= '1'; end case; end process; END;

gpl-3.0

Project-Bonfire/EHA

RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/counter_threshold.vhd

6

3894

--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand -- This design is based on the proposed method, discussed in the following publication: -- "A Fault Prediction Module for a Fault Tolerant NoC Operation" -- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C. library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity counter_threshold_classifier is generic ( counter_depth: integer := 8; healthy_counter_threshold: integer := 4; faulty_counter_threshold: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; faulty_packet, Healthy_packet: in std_logic; Healthy, Intermittent, Faulty: out std_logic ); end counter_threshold_classifier; architecture behavior of counter_threshold_classifier is signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0); signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0); signal NET: std_logic; --no error threshold signal DET: std_logic; --detected error threshold signal reset_counters: std_logic; TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state); SIGNAL state, next_state : STATE_TYPE := Healthy_state; begin process(clk, reset)begin if reset = '0' then faulty_counter_out <= (others => '0'); healthy_counter_out <= (others => '0'); state <= Reset_state; elsif clk'event and clk = '1' then faulty_counter_out <= faulty_counter_in; healthy_counter_out <= healthy_counter_in; state <= next_state; end if; end process; process(faulty_packet, reset_counters, faulty_counter_out)begin if reset_counters = '1' then faulty_counter_in <= (others => '0'); elsif faulty_packet = '1' then faulty_counter_in <= faulty_counter_out + 1; else faulty_counter_in <= faulty_counter_out; end if; end process; process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin if reset_counters = '1' then healthy_counter_in <= (others => '0'); elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then healthy_counter_in <= healthy_counter_out + 1; else healthy_counter_in <= healthy_counter_out; end if; end process; process(healthy_counter_out, faulty_counter_out) begin reset_counters <= '0'; DET <= '0'; NET <= '0'; if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then NET <= '1'; reset_counters <= '1'; end if; if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then DET <= '1'; reset_counters <= '1'; end if; end process; process (NET, DET, state)begin Healthy <= '0'; Intermittent <= '0'; Faulty <= '0'; case state is when Healthy_state => if NET = '1' then next_state <= Healthy_state; elsif DET = '1' then next_state <= Intermittent_state; Intermittent <= '1'; else next_state <= Healthy_state; end if; when Intermittent_state => if NET = '1' then next_state <= Healthy_state; Healthy <= '1'; elsif DET = '1' then next_state <= Faulty_state; Faulty <= '1'; else next_state <= Intermittent_state; end if; when Faulty_state => next_state <= Faulty_state; when Reset_state => next_state <= Healthy_state; Healthy <= '1'; end case; end process; END;

gpl-3.0

Project-Bonfire/EHA

RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/plasma.vhd

3

15291

--------------------------------------------------------------------- -- TITLE: Plasma (CPU core with memory) -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 6/4/02 -- FILENAME: plasma.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- This entity combines the CPU core with memory and a UART. -- -- Memory Map: -- 0x00000000 - 0x0000ffff Internal RAM (8KB) -- 0x10000000 - 0x100fffff External RAM (1MB) -- Access all Misc registers with 32-bit accesses -- 0x20000000 Uart Write (will pause CPU if busy) -- 0x20000000 Uart Read -- 0x20000010 IRQ Mask -- 0x20000020 IRQ Status -- 0x20000030 GPIO0 Out Set bits -- 0x20000040 GPIO0 Out Clear bits -- 0x20000050 GPIOA In -- 0x20000060 Counter -- 0x20000070 Ethernet transmit count -- IRQ bits: -- 7 GPIO31 -- 6 ^GPIO31 -- 5 EthernetSendDone -- 4 EthernetReceive -- 3 Counter(18) -- 2 ^Counter(18) -- 1 ^UartWriteBusy -- 0 UartDataAvailable -- modified by: Siavoosh Payandeh Azad -- Change logs: -- * An NI has been instantiated! -- * some changes has been applied to the ports of the CPU to facilitate the new NI! --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity plasma is generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM"; log_file : string := "UNUSED"; ethernet : std_logic := '0'; use_cache : std_logic := '0'; current_address : integer := 0; stim_file: string :="code.txt"); port(clk : in std_logic; reset : in std_logic; uart_write : out std_logic; uart_read : in std_logic; address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); mem_pause_in : in std_logic; no_ddr_start : out std_logic; no_ddr_stop : out std_logic; gpio0_out : out std_logic_vector(31 downto 0); gpioA_in : in std_logic_vector(31 downto 0); credit_in : in std_logic; valid_out: out std_logic; TX: out std_logic_vector(31 downto 0); credit_out : out std_logic; valid_in: in std_logic; RX: in std_logic_vector(31 downto 0); link_faults: in std_logic_vector(4 downto 0); turn_faults: in std_logic_vector(19 downto 0); Rxy_reconf_PE: out std_logic_vector(7 downto 0); Cx_reconf_PE: out std_logic_vector(3 downto 0); Reconfig_command : out std_logic ); end; --entity plasma architecture logic of plasma is signal address_next : std_logic_vector(31 downto 2); signal byte_we_next : std_logic_vector(3 downto 0); signal cpu_address : std_logic_vector(31 downto 0); signal cpu_byte_we : std_logic_vector(3 downto 0); signal cpu_data_w : std_logic_vector(31 downto 0); signal cpu_data_r : std_logic_vector(31 downto 0); signal cpu_pause : std_logic; signal data_read_uart : std_logic_vector(7 downto 0); signal write_enable : std_logic; signal eth_pause_in : std_logic; signal eth_pause : std_logic; signal mem_busy : std_logic; signal enable_misc : std_logic; signal enable_uart : std_logic; signal enable_uart_read : std_logic; signal enable_uart_write : std_logic; signal enable_eth : std_logic; signal gpio0_reg : std_logic_vector(31 downto 0); signal uart_write_busy : std_logic; signal uart_data_avail : std_logic; signal irq_mask_reg : std_logic_vector(7 downto 0); signal irq_status : std_logic_vector(7 downto 0); signal irq : std_logic; signal irq_eth_rec : std_logic; signal irq_eth_send : std_logic; signal counter_reg : std_logic_vector(31 downto 0); signal ram_enable : std_logic; signal ram_byte_we : std_logic_vector(3 downto 0); signal ram_address, ram_address_late : std_logic_vector(31 downto 2); signal ram_data_w : std_logic_vector(31 downto 0); signal ram_data_r, ram_data_r_ni : std_logic_vector(31 downto 0); signal NI_irq_out : std_logic; --signal NI_read_flag : std_logic; --signal NI_write_flag : std_logic; signal cache_access : std_logic; signal cache_checking : std_logic; signal cache_miss : std_logic; signal cache_hit : std_logic; constant reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111"; constant reserved_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; constant reserved_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"; begin --architecture write_enable <= '1' when cpu_byte_we /= "0000" else '0'; mem_busy <= eth_pause or mem_pause_in; cache_hit <= cache_checking and not cache_miss; cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy cache_miss or --Cache wait (cpu_address(28) and not cache_hit and mem_busy); --DDR or flash irq_status <= gpioA_in(31) & not gpioA_in(31) & irq_eth_send & irq_eth_rec & counter_reg(18) & not counter_reg(18) & not uart_write_busy & uart_data_avail; irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29); gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0); enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0'; enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0'; enable_uart_read <= enable_uart and not write_enable; enable_uart_write <= enable_uart and write_enable; enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0'; cpu_address(1 downto 0) <= "00"; u1_cpu: mlite_cpu generic map (memory_type => memory_type) PORT MAP ( clk => clk, reset_in => reset, intr_in => irq, --NI_read_flag => NI_read_flag, --NI_write_flag => NI_write_flag, address_next => address_next, --before rising_edge(clk) byte_we_next => byte_we_next, address => cpu_address(31 downto 2), --after rising_edge(clk) byte_we => cpu_byte_we, data_w => cpu_data_w, data_r => cpu_data_r, mem_pause => cpu_pause); opt_cache: if use_cache = '0' generate cache_access <= '0'; cache_checking <= '0'; cache_miss <= '0'; end generate; opt_cache2: if use_cache = '1' generate --Control 4KB unified cache that uses the upper 4KB of the 8KB --internal RAM. Only lowest 2MB of DDR is cached. u_cache: cache generic map (memory_type => memory_type) PORT MAP ( clk => clk, reset => reset, address_next => address_next, byte_we_next => byte_we_next, cpu_address => cpu_address(31 downto 2), mem_busy => mem_busy, cache_access => cache_access, --access 4KB cache cache_checking => cache_checking, --checking if cache hit cache_miss => cache_miss); --cache miss end generate; --opt_cache2 no_ddr_start <= not eth_pause and cache_checking; no_ddr_stop <= not eth_pause and cache_miss; eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking); misc_proc: process(clk, reset, cpu_address, enable_misc, ram_data_r, ram_address_late, ram_data_r_ni, data_read, data_read_uart, cpu_pause, irq_mask_reg, irq_status, gpio0_reg, write_enable, cache_checking, gpioA_in, counter_reg, cpu_data_w) begin case cpu_address(30 downto 28) is when "000" => --internal RAM if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address) or (ram_address_late = reserved_counter_address)) then cpu_data_r <= ram_data_r_ni; else cpu_data_r <= ram_data_r; end if; when "001" => --external RAM if cache_checking = '1' then --cpu_data_r <= ram_data_r; --cache if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address) or (ram_address_late = reserved_counter_address)) then cpu_data_r <= ram_data_r_ni; else cpu_data_r <= ram_data_r; --cache end if; else cpu_data_r <= data_read; --DDR end if; when "010" => --misc case cpu_address(6 downto 4) is when "000" => --uart cpu_data_r <= ZERO(31 downto 8) & data_read_uart; when "001" => --irq_mask cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg; when "010" => --irq_status cpu_data_r <= ZERO(31 downto 8) & irq_status; when "011" => --gpio0 cpu_data_r <= gpio0_reg; when "101" => --gpioA cpu_data_r <= gpioA_in; when "110" => --counter cpu_data_r <= counter_reg; when others => cpu_data_r <= gpioA_in; end case; when "011" => --flash cpu_data_r <= data_read; when others => cpu_data_r <= ZERO; end case; if reset = '1' then irq_mask_reg <= ZERO(7 downto 0); gpio0_reg <= ZERO; counter_reg <= ZERO; elsif rising_edge(clk) then counter_reg <= bv_inc(counter_reg); if cpu_pause = '0' then if enable_misc = '1' and write_enable = '1' then if cpu_address(6 downto 4) = "001" then irq_mask_reg <= cpu_data_w(7 downto 0); elsif cpu_address(6 downto 4) = "011" then gpio0_reg <= gpio0_reg or cpu_data_w; elsif cpu_address(6 downto 4) = "100" then gpio0_reg <= gpio0_reg and not cpu_data_w; elsif cpu_address(6 downto 4) = "110" then counter_reg <= cpu_data_w; end if; end if; end if; end if; end process; process(ram_address, reset, clk)begin if reset = '1' then ram_address_late <= (others => '0'); elsif clk'event and clk = '1' then ram_address_late <= ram_address; end if; end process; ram_proc: process(cache_access, cache_miss, address_next, cpu_address, byte_we_next, cpu_data_w, data_read) begin if cache_access = '1' then --Check if cache hit or write through ram_enable <= '1'; ram_byte_we <= byte_we_next; ram_address(31 downto 2) <= ZERO(31 downto 16) & "0001" & address_next(11 downto 2); ram_data_w <= cpu_data_w; elsif cache_miss = '1' then --Update cache after cache miss ram_enable <= '1'; ram_byte_we <= "1111"; ram_address(31 downto 2) <= ZERO(31 downto 16) & "0001" & cpu_address(11 downto 2); ram_data_w <= data_read; else --Normal non-cache access if address_next(30 downto 28) = "000" then ram_enable <= '1'; else ram_enable <= '0'; end if; ram_byte_we <= byte_we_next; ram_address(31 downto 2) <= address_next(31 downto 2); ram_data_w <= cpu_data_w; end if; end process; u2_ram: ram generic map (memory_type => memory_type, stim_file => stim_file) port map ( clk => clk, reset => reset, enable => ram_enable, write_byte_enable => ram_byte_we, address => ram_address, data_write => ram_data_w, data_read => ram_data_r); u3_uart: uart generic map (log_file => log_file) port map( clk => clk, reset => reset, enable_read => enable_uart_read, enable_write => enable_uart_write, data_in => cpu_data_w(7 downto 0), data_out => data_read_uart, uart_read => uart_read, uart_write => uart_write, busy_write => uart_write_busy, data_avail => uart_data_avail); dma_gen: if ethernet = '0' generate address <= cpu_address(31 downto 2); byte_we <= cpu_byte_we; data_write <= cpu_data_w; eth_pause <= '0'; gpio0_out(28 downto 24) <= ZERO(28 downto 24); irq_eth_rec <= '0'; irq_eth_send <= '0'; end generate; dma_gen2: if ethernet = '1' generate u4_eth: eth_dma port map( clk => clk, reset => reset, enable_eth => gpio0_reg(24), select_eth => enable_eth, rec_isr => irq_eth_rec, send_isr => irq_eth_send, address => address, --to DDR byte_we => byte_we, data_write => data_write, data_read => data_read, pause_in => eth_pause_in, mem_address => cpu_address(31 downto 2), --from CPU mem_byte_we => cpu_byte_we, data_w => cpu_data_w, pause_out => eth_pause, E_RX_CLK => gpioA_in(20), E_RX_DV => gpioA_in(19), E_RXD => gpioA_in(18 downto 15), E_TX_CLK => gpioA_in(14), E_TX_EN => gpio0_out(28), E_TXD => gpio0_out(27 downto 24)); end generate; u4_ni: NI generic map(current_address => current_address, SHMU_address => 0) port map ( clk => clk, reset => reset, enable => ram_enable, write_byte_enable => ram_byte_we, address => ram_address, data_write => ram_data_w, data_read => ram_data_r_ni, --NI_read_flag => NI_read_flag, --NI_write_flag => NI_write_flag, irq_out => NI_irq_out, credit_in => credit_in, valid_out => valid_out, TX => TX, credit_out => credit_out, valid_in => valid_in, RX => RX, link_faults => link_faults, turn_faults => turn_faults, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command => Reconfig_command ); end; --architecture logic

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_min_area_pkg.vhd

9

20310

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gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/updn_cntr.vhd

9

10023

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MJu6CgyUu9Rx7DcIJ1WYxtXlEf9M4WTCKxGxEQurf0wS9A8H1bgDo0mC890fMV9dGN8tlX9O0g8S Qo5Og3Qumg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ExWc9QkINx2fRYuZ4iSBIH4TVBU1flfUsD9t3OrI2kQ7DlcI+fe5CuJcHvn+4Eus+9Wj67q3dDNV 9dTH4+uTaBy8FMiinsFEBZgTCvLxjbkS7iDmyXPI6KoCg/drEbxmfK4PV9mTNoUm3QKU9Y1th135 zhhgH++Bd5h0Yysnh1U= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 08n8ceY25YWVAFoupqatlCl2rQz9SVENaon0KM72325O4WrZvgMUUROAdmvJAokRNgBam69d5hNf xK5eJgBApza+ZtJFfqI0CAMrdGpYjgWPbArqOYKTurrSxBx8saXjrSL2QFgUZA4cNsCQ0uDVJVqq ONMD/XJ9DxfoLnqhDfJJyu3ZcyW9RhDLzRkQlmNgXTdXGOBg+S4hLOdDuw4duyjwO8Zl35W152xw TySG49Ck4Om1VmF1ShBCjba3IUSK7zs0pB0pu4Y92K4ZcyRcFTZH2Nzwoo2IT67U645QWZrx4RGs 6uw00dS+OG4oSyyos+jKqstWrXK2CofN0Ko4aw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block j56kiWofr2kH1KQ9xxDRg1jv14wUx9T6gxwuCzRqJTgwMbZuCIhkYwpvUbNXEhD4SeMtH1aHaw8I HU4/UsUhBGYYINu90+vVVssqtZqYezl0Nl/L02zbNiom/Dcfb1SE2BsMaX/Y0HPVjgmrrOx/fGMe C7AQOpjLh5c81sn4jZU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block NJ5es1ZDqQ8NebX7NTnnmCSOJyin4Et3d+KOKh4tAtxiLfoNquxSeHAiNj0Mn2TMlCjLWp3/qGex H5xI9z0f4NPkHvs1NHfEtN/GeliNl7P+BvtaqAGawR14m0bHMQsiASq3wM6WugIs+T47dSQMVvzB PVI6FwE4b6vk9QtADFwXOrsVdXANiM690qPkx78Y5rX9ny+T0xTzkjqTSubBOQo3ncYLtd7f2o/N tjzBXZ9EvIm7bWwxaobF/n78sQ4/ZZBrdpNkgYIOha1BEVmsDbTnNsr7vVz0grGedBz10Fagv/G1 QARm/sMZyl/SJB2IhoBmSqL7CEQwh7gAdf8m7g== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5680) `protect data_block qZEl5eIT9NHWEZg7a7CsgYvd+eNj/jmFWkXx9V/kL39W3LQ9JT3ElU3FPR7V0E/A0OTVLkJO/1oI WMAmUdXHewTih+z0cwDSPwInrsmVe4GaVZlk6h2llkKC272touXNfFaB977TWsGkFPA9NqzLAuQd zrAKDzRWA0V3G2cvXCMkjvqBGL7ABo3OvvBOs6WaONSMDw7FowL3uA7fK+Ume2dkq1oTrj0cJm3+ 5SRUze8/iydDfzO0uSWWIihfo2FIAgufY1ovtHLnOHXyoChuyfAcqITec0GcQJPrDCsziXrBscQI s9xmfsx1YeKS7bWejvN+MX2Hr8Zx9oCZtKtD506fOlp1pgMqQ8irjagQsNWmgAcR+nsOrXaYNqNM iOeI0WRGXKkyQuTB2mHThm099Jg/lrsI2LxCkUAkRMF8AgKJuvU8DvqBUdqyS+7MYqeuHbHyXqfm Q3ws+UtLNGZAPsYCkEWWXJ+lnj5xsh+CAUAzUXynjIX6IIbJHzfSYunZQWXZQaKPy9T+RKmaapox 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gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/fifo16_patch/fifo16_patch_top.vhd

9

11515

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block cPZ7+eHDLjmNfVUj8WvKqXLAnPtyLm0s9aYSxSzHsqbVkwztD0TQZP6rapbcQM3whT4sRRe0Nv72 4hG04ccfPg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block pDGgn+8ERDtvyySodmphmnLIurqM6Ql+NZFaA+4rCgAMlfgC9XqIc5lR1N3M2RxHZcDKAzfijmgq wUVBrbuleWBsgTB0E9cQb1vaYOPRfnUmsBAEMlSBrOybJO2x97XdjtnNdx21f5BsMSmSL99k84uC D3w/Q2EtG2sVqfsQ0Uw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ux0E7ic7ddrM05MHFP6SN01PL8t1fArCWREGsYjS2ONcF2IPi6qGxKv2j6Bz1/ksI2IdqxEwhMND Xwur5QkftdAoX842VLyoS+RhDtjOuzxClBPUN6Vp5PhuRj5IeqN65zqr7zc9VOA1EmoOY/R8fBEz Yo5b5k2v7CH1jlqgBhYliwBu+iM8gR/saVfjlxNHAqq9lCHEmlTh+cLc7U9e4drEHfwIEzJax4pV 3UJYu2YsQBbZsIHHMUvLM6+80Ox+YDCN03PRmISy/UeZ5/ptqjgXOo4VTQz/KgxyxlOsplJzflag /DihISoV8c87bVCFlaELwfvYcWhO1XAm5g9qhw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block EYV2fiDAQh47256HEG+lsKBNLjtKVHQOJbaPpVgeYOluFA28J//O8rDaD+o6fukMY9UOhT21+W74 eqHFBt7pa0zrz16/ZAQqs46TsLmKJqugsbZtphRz1JMU5+zfR/c9k4K1/CLB357EkoC+1fU3gPxX pYsfqy24jhagQ349Nkg= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block bLJwmBFChIRX3l4b6zFqLjuzCEYMRmsSJsdKazWL8VLHQck3Qbxi50EZ4DPvqyxFcGnmBE7UdkS7 4whktutIv5Nf1TltNTuRrHFt9yCzZZ6BdoFh+UCXBHV7BgHaQemox6pN6HmtyrHs/jrWfynM8H6t pU9SNjG6QssLUAwOZXNFRv/EjDI33IJZniMh9ZUY+WTbOHlRmddCkAQ/EToYAcRPx9uv3iXiInys pN4Rxd27ZVxvkywvgA5u8skaQRlT206DpSLUGlrIRAaS08vPKOsqgNQdxiJRL4d3ATCXWh3AnfD/ hm0Ex7zx8yOCRtwA7vyU88q8ARmDTL+GPaSknQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6784) `protect data_block PEdyL/6maIPEePxPLZVmqWWjenOPjeFM0R0RyvI7Avm7KfW53geXamljlX/E066mv+Vp43jjGrbP 6MK5bjJ5Tog8BU5NYsSoIhhS3IaQpNBaNKkRqkHD9cFHua0Z9DJ+tQ+RUCUed7RBfO638ZkoYAIx 6mj4CJ2AOYBs8LX5tkj4kzo5OzeefCdaeeXb4BDaAb35QCyFf1VYbLz6qCw0Y38Jz6H8ixF2iHir N3zEuoFOUATKeJRoMdlyElzw4yBC6DB2QuFwZ2iT4tWVstEGGfCpWJYZ93LtsqI2ljfAHolVcavQ OQj0eA0aTHwuoWGs7MxnFDdLwUaXHVm7E2kq9M+H2eM1BzRCcxJQhP3DE588qJO8fvKeVC+mlSZq Y2xN9U1iWa2WscgSu/W/YGNG1rXN4IxYGEr9fkTOO9ZCYsQLE7ZSQBACak09TOlmZZGccR0e7C+9 CX/tS4bIHAImn1p/8lTqA2SadcT+6Ji855uRd2ES0/1ANkt0Rcj7cXO8aI4TNaBdwOAZEogH0wGG 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gpl-3.0

Project-Bonfire/EHA

RTL/Router/credit_based/Checkers/Modules_with_checkers_integrated/All_checkers/New_SHMU_on_Node/LBDR_packet_drop_checkers/LBDR_packet_drop_with_checkers.vhd

6

27011

--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity LBDR_packet_drop is generic ( cur_addr_rst: integer := 5; Rxy_rst: integer := 60; Cx_rst: integer := 15; NoC_size: integer := 4 ); port ( reset: in std_logic; clk: in std_logic; Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic; empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); dst_addr: in std_logic_vector(NoC_size-1 downto 0); packet_drop_order: out std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic; -- Checker outputs -- Routing part checkers err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order, -- Cx_Reconf checkers err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added -- Rxy_Reconf checkers err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end LBDR_packet_drop; architecture behavior of LBDR_packet_drop is signal Cx, Cx_in: std_logic_vector(3 downto 0); signal Temp_Cx, Temp_Cx_in: std_logic_vector(3 downto 0); signal reconfig_cx, reconfig_cx_in: std_logic; signal ReConf_FF_in, ReConf_FF_out: std_logic; signal Rxy, Rxy_in: std_logic_vector(7 downto 0); signal Rxy_tmp, Rxy_tmp_in: std_logic_vector(7 downto 0); signal cur_addr: std_logic_vector(NoC_size-1 downto 0); signal N1, E1, W1, S1 :std_logic :='0'; signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic; signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic; signal grants: std_logic; signal packet_drop, packet_drop_in: std_logic; -- Signal(s) required for checker(s) signal packet_drop_order_sig: std_logic; component LBDR_packet_drop_routing_part_pseudo_checkers is generic ( cur_addr_rst: integer := 5; NoC_size: integer := 4 ); port ( empty: in std_logic; flit_type: in std_logic_vector(2 downto 0); Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic; grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic; dst_addr: in std_logic_vector(NoC_size-1 downto 0); Cx: in std_logic_vector(3 downto 0); Rxy: in std_logic_vector(7 downto 0); packet_drop: in std_logic; N1_out, E1_out, W1_out, S1_out: in std_logic; Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic; grants: in std_logic; packet_drop_order: in std_logic; packet_drop_in: in std_logic; -- Checker outputs err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot, err_grants_mismatch, err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order : out std_logic ); end component; component Cx_Reconf_pseudo_checkers is port ( reconfig_cx: in std_logic; -- * flit_type: in std_logic_vector(2 downto 0); -- * empty: in std_logic; -- * grants: in std_logic; -- * Cx_in: in std_logic_vector(3 downto 0); -- * Temp_Cx: in std_logic_vector(3 downto 0); -- * reconfig_cx_in: in std_logic; -- * Cx: in std_logic_vector(3 downto 0); -- * Cx_reconf_PE: in std_logic_vector(3 downto 0); -- newly added Reconfig_command : in std_logic; -- newly added Faulty_C_N: in std_logic; -- * Faulty_C_E: in std_logic; -- * Faulty_C_W: in std_logic; -- * Faulty_C_S: in std_logic; -- * Temp_Cx_in: in std_logic_vector(3 downto 0); -- * -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal : out std_logic -- Added ); end component; component Rxy_Reconf_pseudo_checkers is port ( ReConf_FF_out: in std_logic; Rxy: in std_logic_vector(7 downto 0); Rxy_tmp: in std_logic_vector(7 downto 0); Reconfig_command : in std_logic; flit_type: in std_logic_vector(2 downto 0); grants: in std_logic; empty: in std_logic; Rxy_reconf_PE: in std_logic_vector(7 downto 0); Rxy_in: in std_logic_vector(7 downto 0); Rxy_tmp_in: in std_logic_vector(7 downto 0); ReConf_FF_in: in std_logic; err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal : out std_logic ); end component; begin packet_drop_order <= packet_drop_order_sig; -- LBDR packet drop routing part checkers instantiation LBDR_packet_drop_routing_part_checkers: LBDR_packet_drop_routing_part_pseudo_checkers generic map (cur_addr_rst => cur_addr_rst, NoC_size => NoC_size) port map ( empty => empty, flit_type => flit_type, Req_N_FF => Req_N_FF, Req_E_FF => Req_E_FF, Req_W_FF => Req_W_FF, Req_S_FF => Req_S_FF, Req_L_FF => Req_L_FF, grant_N => grant_N, grant_E => grant_E, grant_W => grant_W, grant_S => grant_S, grant_L => grant_L, dst_addr => dst_addr, Cx => Cx, Rxy => Rxy, packet_drop => packet_drop, N1_out => N1, E1_out => E1, W1_out => W1, S1_out => S1, Req_N_in => Req_N_in, Req_E_in => Req_E_in, Req_W_in => Req_W_in, Req_S_in => Req_S_in, Req_L_in => Req_L_in, grants => grants, packet_drop_order => packet_drop_order_sig, packet_drop_in => packet_drop_in, -- Checker outputs err_header_empty_Requests_FF_Requests_in => err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => err_grants_onehot, err_grants_mismatch => err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_not_Req_L_in => err_dst_addr_cur_addr_not_Req_L_in, err_dst_addr_cur_addr_Req_L_in => err_dst_addr_cur_addr_Req_L_in, err_header_not_empty_Req_N_in => err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => err_header_not_empty_Req_S_in, err_header_not_empty_packet_drop_in => err_header_not_empty_packet_drop_in, err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal => err_header_not_empty_dst_addr_cur_addr_equal_packet_drop_in_packet_drop_equal, err_header_empty_packet_drop_in_packet_drop_equal => err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => err_packet_drop_order ); -- LBDR packet drop Cx Reconfiguration module checkers instantiation Cx_Reconf_checkers: Cx_Reconf_pseudo_checkers port map ( reconfig_cx => reconfig_cx, flit_type => flit_type, empty => empty, grants => grants, Cx_in => Cx_in, Temp_Cx => Temp_Cx, reconfig_cx_in => reconfig_cx_in, Cx => Cx, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command => Reconfig_command, Faulty_C_N => Faulty_C_N, Faulty_C_E => Faulty_C_E, Faulty_C_W => Faulty_C_W, Faulty_C_S => Faulty_C_S, Temp_Cx_in => Temp_Cx_in, -- Checker Outputs err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal ); -- LBDR packet drop Rxy Reconfiguration checkers instantiation Rxy_Reconf_checkers : Rxy_Reconf_pseudo_checkers port map ( ReConf_FF_out => ReConf_FF_out, Rxy => Rxy, Rxy_tmp => Rxy_tmp, Reconfig_command => Reconfig_command, flit_type => flit_type, grants => grants, empty => empty, Rxy_reconf_PE => Rxy_reconf_PE, Rxy_in => Rxy_in, Rxy_tmp_in => Rxy_tmp_in, ReConf_FF_in => ReConf_FF_in, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); grants <= grant_N or grant_E or grant_W or grant_S or grant_L; cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length)); N1 <= '1' when dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) else '0'; E1 <= '1' when cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) else '0'; W1 <= '1' when dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) else '0'; S1 <= '1' when cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) else '0'; process(clk, reset) begin if reset = '0' then Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length)); Rxy_tmp <= (others => '0'); Req_N_FF <= '0'; Req_E_FF <= '0'; Req_W_FF <= '0'; Req_S_FF <= '0'; Req_L_FF <= '0'; Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length)); Temp_Cx <= (others => '0'); ReConf_FF_out <= '0'; reconfig_cx <= '0'; packet_drop <= '0'; elsif clk'event and clk = '1' then Rxy <= Rxy_in; Rxy_tmp <= Rxy_tmp_in; Req_N_FF <= Req_N_in; Req_E_FF <= Req_E_in; Req_W_FF <= Req_W_in; Req_S_FF <= Req_S_in; Req_L_FF <= Req_L_in; ReConf_FF_out <= ReConf_FF_in; Cx <= Cx_in; reconfig_cx <= reconfig_cx_in; Temp_Cx <= Temp_Cx_in; packet_drop <= packet_drop_in; end if; end process; -- The combionational part process(Reconfig_command, Rxy_reconf_PE, Rxy_tmp, ReConf_FF_out, Rxy, flit_type, grants, empty)begin Rxy_tmp_in <= Rxy_tmp; if ReConf_FF_out= '1' and flit_type = "100" and empty = '0' and grants = '1' then Rxy_in <= Rxy_tmp; ReConf_FF_in <= '0'; else Rxy_in <= Rxy; if Reconfig_command = '1'then Rxy_tmp_in <= Rxy_reconf_PE; ReConf_FF_in <= '1'; else Rxy_tmp_in <= Rxy_tmp; ReConf_FF_in <= ReConf_FF_out; end if; end if; end process; process(Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Cx, Temp_Cx, flit_type, reconfig_cx, empty, grants, Cx_reconf_PE, Reconfig_command) begin Temp_Cx_in <= Temp_Cx; if reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' then Cx_in <= Temp_Cx; reconfig_cx_in <= '0'; else Cx_in <= Cx; if (Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= not(Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N) and Cx; elsif Reconfig_command = '1' then reconfig_cx_in <= '1'; Temp_Cx_in <= Cx_reconf_PE; else reconfig_cx_in <= reconfig_cx; end if; end if; end process; Req_N <= Req_N_FF; Req_E <= Req_E_FF; Req_W <= Req_W_FF; Req_S <= Req_S_FF; Req_L <= Req_L_FF; process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants, packet_drop, dst_addr, cur_addr) begin packet_drop_in <= packet_drop; if flit_type = "001" and empty = '0' then Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0); Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1); Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2); Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3); if dst_addr = cur_addr then Req_L_in <= '1'; else Req_L_in <= Req_L_FF; -- Added to remove latch possibility. Correct ?? end if; if ((((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0)) or (((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1)) or (((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2)) or (((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3))) ='0' and dst_addr /= cur_addr then packet_drop_in <= '1'; end if; elsif flit_type = "100" and empty = '0' and grants = '1' then Req_N_in <= '0'; Req_E_in <= '0'; Req_W_in <= '0'; Req_S_in <= '0'; Req_L_in <= '0'; else Req_N_in <= Req_N_FF; Req_E_in <= Req_E_FF; Req_W_in <= Req_W_FF; Req_S_in <= Req_S_FF; Req_L_in <= Req_L_FF; end if; if flit_type = "100" and empty = '0' then if packet_drop = '1' then packet_drop_in <= '0'; end if; end if; end process; packet_drop_order_sig <= packet_drop; END;

gpl-3.0

Project-Bonfire/EHA

RTL/Router/credit_based/RTL/FIFO_one_hot_credit_based_packet_drop.vhd

3

16426

--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FIFO_credit_based is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; credit_out: out std_logic; empty_out: out std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end FIFO_credit_based; architecture behavior of FIFO_credit_based is signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0); signal full, empty: std_logic; signal read_en, write_en: std_logic; signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0); constant fake_tail : std_logic_vector := "10000000000000000000000000000001"; alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3); signal faulty_packet_in, faulty_packet_out: std_logic; signal xor_all, fault_out: std_logic; type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop); signal state_out, state_in : state_type; signal fake_credit, credit_in, write_fake_flit: std_logic; signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0); begin -------------------------------------------------------------------------------------------- -- block diagram of the FIFO! -------------------------------------------------------------------------------------------- -- circular buffer structure -- <--- WriteP -- --------------------------------- -- | 3 | 2 | 1 | 0 | -- --------------------------------- -- <--- readP -------------------------------------------------------------------------------------------- -- Packet drop state machine -- +---+ No +---+ No -- | | Flit | | Flit -- | v | v -- healthy +--------+ +--------+ -- +---header-->| | | |-------------------+ -- | +->| Header |---Healthy body-->| Body |------------+ | -- | | +--------+ +--------+ | | -- | | | ^ | Healthy | ^ Healthy | -- | | | | | body | | Tail | -- | | | | | +---+ | | -- | | | | | v | -- +--------+ | | | | +--------+ | -- No +-->| | | | | +-----------------Healthy Tail------>| | | -- Flit| | IDLE | | | | | Tail |--)--+ -- +---| | | | +-----------Healthy Header--------------| | | | -- +--------+ | | +--------+ | | -- ^ | ^ | Faulty No Faulty | | -- | | | | Flit Flit Flit | | -- | | | | +------------+ +---+ +---+ | | -- | | | + --Healthy------+ | | | | | | | -- | | | header | v | v | v | | -- | | | +------------------+ | | -- | | +----Healthy Tail-----| Packet | | | -- | +-------Faulty Flit----->| Drop |<-----------------------+ | -- | +------------------+ | -- +-------------------------------------------------No Flit------------------+ -- ------------------------------------------------------------------------------------------------ process (clk, reset)begin if reset = '0' then read_pointer <= "0001"; write_pointer <= "0001"; FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0'); fake_credit_counter <= (others=>'0'); faulty_packet_out <= '0'; credit_out <= '0'; state_out <= Idle; elsif clk'event and clk = '1' then write_pointer <= write_pointer_in; read_pointer <= read_pointer_in; state_out <= state_in; faulty_packet_out <= faulty_packet_in; credit_out <= credit_in; fake_credit_counter <= fake_credit_counter_in; if write_en = '1' then --write into the memory FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in; end if; end if; end process; -- anything below here is pure combinational -- combinatorial part process(fake_credit, read_en, fake_credit_counter) begin fake_credit_counter_in <= fake_credit_counter; credit_in <= '0'; if fake_credit = '1' and read_en = '1' then fake_credit_counter_in <= fake_credit_counter + 1 ; end if; if (read_en ='1' or fake_credit = '1') then credit_in <= '1'; end if; if read_en = '0' and fake_credit = '0' and fake_credit_counter > 0 then fake_credit_counter_in <= fake_credit_counter - 1 ; credit_in <= '1'; end if; end process; process(valid_in, RX) begin if valid_in = '1' then xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1)); else xor_all <= '0'; end if; end process; process(valid_in, RX, xor_all)begin fault_out <= '0'; if valid_in = '1' and xor_all /= RX(0) then fault_out <= '1'; end if; end process; process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin -- this is the default value of the memory! case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; --some defaults fake_credit <= '0'; state_in <= state_out; faulty_packet_in <= faulty_packet_out; write_fake_flit <= '0'; case(state_out) is when Idle => if fault_out = '0' then if valid_in = '1' then state_in <= Header_flit; else state_in <= state_out; end if; else fake_credit <= '1'; FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; when Header_flit => if valid_in = '1' then if fault_out = '0' then if flit_type = "010" then state_in <= Body_flit; elsif flit_type ="100" then state_in <= Tail_flit; else -- we should not be here! state_in <= state_out; end if; else write_fake_flit <= '1'; case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; else state_in <= state_out; end if; when Body_flit => if valid_in = '1' then if fault_out = '0' then if flit_type = "010" then state_in <= state_out; elsif flit_type = "100" then state_in <= Tail_flit; else -- we should not be here! state_in <= state_out; end if; else write_fake_flit <= '1'; case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; else state_in <= state_out; end if; when Tail_flit => if valid_in = '1' then if fault_out = '0' then if flit_type = "001" then state_in <= Header_flit; else state_in <= state_out; end if; else fake_credit <= '1'; FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; state_in <= Packet_drop; faulty_packet_in <= '1'; end if; else state_in <= Idle; end if; when Packet_drop => if faulty_packet_out = '1' then if valid_in = '1' and flit_type = "001" and fault_out = '0' then faulty_packet_in <= '0'; state_in <= Header_flit; write_fake_flit <= '1'; case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; faulty_packet_in <= '0'; state_in <= Idle; fake_credit <= '1'; else if valid_in = '1' then fake_credit <= '1'; end if; FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; state_in <= state_out; end if; else -- we should not be here! state_in <= state_out; end if; when others => state_in <= state_out; end case; end process; process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin case( read_pointer ) is when "0001" => Data_out <= FIFO_MEM_1; when "0010" => Data_out <= FIFO_MEM_2; when "0100" => Data_out <= FIFO_MEM_3; when "1000" => Data_out <= FIFO_MEM_4; when others => Data_out <= FIFO_MEM_1; end case ; end process; read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty; empty_out <= empty; process(write_en, write_pointer)begin if write_en = '1' then write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3); else write_pointer_in <= write_pointer; end if; end process; process(read_en, empty, read_pointer)begin if (read_en = '1' and empty = '0') then read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3); else read_pointer_in <= read_pointer; end if; end process; process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then write_en <= '1'; else write_en <= '0'; end if; end process; process(write_pointer, read_pointer) begin if read_pointer = write_pointer then empty <= '1'; else empty <= '0'; end if; -- if write_pointer = read_pointer>>1 then if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then full <= '1'; else full <= '0'; end if; end process; end;

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_output_block.vhd

9

17048

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gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_output_block.vhd

9

17048

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ZDbLXMCW/rFA4qQp7M4XtRAVOMy7+62OqdKd3dOe4Jvb/C2JADukHaa3oslAf5TtlaTLr3ozEohl VKGhLio1ig== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Y/syMaBfRSQ9MD98NKAleGixPcntMfRl9i4DpBCi/l65gO8EpoXWOhQZbbZ/maNd7yin7yuO19Yn GGuE9YDWOl8XBpG3phkcKzJdSu0mKYd+0AQJj9q1lFv6qrGMoUttsl/IpN2yMUpz5fUapnIBd6rb mRz2FHrHicaebKc88GU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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gpl-3.0

Project-Bonfire/EHA

RTL/Router/credit_based/RTL/New_SHMU_on_Node/shifter.vhd

16

3063

--------------------------------------------------------------------- -- TITLE: Shifter Unit -- AUTHOR: Steve Rhoads ([email protected]) -- Matthias Gruenewald -- DATE CREATED: 2/2/01 -- FILENAME: shifter.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the 32-bit shifter unit. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity shifter is generic(shifter_type : string := "DEFAULT"); port(value : in std_logic_vector(31 downto 0); shift_amount : in std_logic_vector(4 downto 0); shift_func : in shift_function_type; c_shift : out std_logic_vector(31 downto 0)); end; --entity shifter architecture logic of shifter is -- type shift_function_type is ( -- shift_nothing, shift_left_unsigned, -- shift_right_signed, shift_right_unsigned); signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0); signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0); signal fills : std_logic_vector(31 downto 16); begin fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED and value(31) = '1' else "0000000000000000"; shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value; shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L; shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L; shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L; shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L; shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value; shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R; shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R; shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R; shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R; GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or shift_func = SHIFT_RIGHT_SIGNED else ZERO; end generate; AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z'); c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z'); c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z'); end generate; end; --architecture logic

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_read_wrapper.vhd

9

56990

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gpl-3.0

Project-Bonfire/EHA

RTL/Chip_Designs/IMMORTAL_Chip_2017/network_files/Allocator_with_checkers_with_FI/Arbiter_in_one_hot_with_checkers_with_FI.vhd

3

13338

--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use work.component_pack.all; -- Is this like the old arbiter in the router with handshaking FC ?? entity Arbiter_in is port ( reset: in std_logic; clk: in std_logic; Req_X_N, Req_X_E, Req_X_W, Req_X_S, Req_X_L: in std_logic; -- From LBDR modules X_N, X_E, X_W, X_S, X_L: out std_logic; -- Grants given to LBDR requests (encoded as one-hot) -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_Req_N, err_IDLE_grant_N,err_North_Req_N, err_North_grant_N, err_East_Req_E, err_East_grant_E, err_West_Req_W, err_West_grant_W, err_South_Req_S,err_South_grant_S,err_Local_Req_L, err_Local_grant_L, err_IDLE_Req_E, err_IDLE_grant_E, err_North_Req_E, err_North_grant_E, err_East_Req_W, err_East_grant_W, err_West_Req_S, err_West_grant_S, err_South_Req_L, err_South_grant_L, err_Local_Req_N, err_Local_grant_N, err_IDLE_Req_W, err_IDLE_grant_W, err_North_Req_W, err_North_grant_W, err_East_Req_S, err_East_grant_S, err_West_Req_L, err_West_grant_L, err_South_Req_N, err_South_grant_N, err_Local_Req_E, err_Local_grant_E, err_IDLE_Req_S, err_IDLE_grant_S, err_North_Req_S, err_North_grant_S, err_East_Req_L, err_East_grant_L, err_West_Req_N, err_West_grant_N, err_South_Req_E, err_South_grant_E, err_Local_Req_W, err_Local_grant_W, err_IDLE_Req_L, err_IDLE_grant_L, err_North_Req_L, err_North_grant_L, err_East_Req_N, err_East_grant_N, err_West_Req_E, err_West_grant_E, err_South_Req_W, err_South_grant_W, err_Local_Req_S, err_Local_grant_S, err_state_in_onehot, err_no_request_grants, err_request_no_grants, err_no_Req_N_grant_N, err_no_Req_E_grant_E, err_no_Req_W_grant_W, err_no_Req_S_grant_S, err_no_Req_L_grant_L : out std_logic ); end Arbiter_in; architecture behavior of Arbiter_in is component shift_register_serial_in is generic ( REG_WIDTH: integer := 32 ); port ( TCK, reset : in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0) ); end component; ---------------------------------------- -- Signals related to fault injection -- ---------------------------------------- -- Total: 7 bits signal FI_add_sta: std_logic_vector (6 downto 0); -- 5 bits for fault injection location address (ceil of log2(17) = 5) -- 2 bits for type of fault (SA0 or SA1) signal non_faulty_signals: std_logic_vector (16 downto 0); -- 17 bits for internal- and output-related signals (non-faulty) signal faulty_signals: std_logic_vector(16 downto 0); -- 17 bits for internal- and output-related signals (with single stuck-at fault injected in one of them) ---------------------------------------- ---------------------------------------- --TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local); --SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0); --SIGNAL state, state_in : STATE_TYPE := IDLE; SIGNAL state, state_in : STD_LOGIC_VECTOR (5 downto 0) := IDLE; SIGNAL X_N_sig, X_E_sig, X_W_sig, X_S_sig, X_L_sig: std_logic; -- needed for connecting output ports -- of Arbiter_in to checker inputs -- Signal(s) used for creating the chain of injected fault locations -- Total: 17 bits ??!! -- Arbiter_in internal-related signals signal state_faulty, state_in_faulty: std_logic_vector(5 downto 0); -- Arbiter_in output-related signals signal X_N_sig_faulty, X_E_sig_faulty, X_W_sig_faulty, X_S_sig_faulty, X_L_sig_faulty: std_logic; begin ------------------------------------- ---- Related to fault injection ----- ------------------------------------- -- Total: 17 bits -- for X_N, ... , X_L output signals, not sure whether to include them or the signals with _sig suffix in their names ??!! non_faulty_signals <= state & state_in & X_N_sig & X_E_sig & X_W_sig & X_S_sig & X_L_sig; -- Fault injector module instantiation FI: fault_injector generic map(DATA_WIDTH => 17, ADDRESS_WIDTH => 5) port map (data_in=> non_faulty_signals , address => FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals ); -- Extracting faulty values for internal- and output-related signals -- Total: 17 bits state_faulty <= faulty_signals (16 downto 11); state_in_faulty <= faulty_signals (10 downto 5); X_N_sig_faulty <= faulty_signals (4); X_E_sig_faulty <= faulty_signals (3); X_W_sig_faulty <= faulty_signals (2); X_S_sig_faulty <= faulty_signals (1); X_L_sig_faulty <= faulty_signals (0); -- Total: 7 bits SR: shift_register_serial_in generic map(REG_WIDTH => 7) port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta ); ------------------------------------- ------------------------------------- -- Becuase of checkers we did this X_N <= X_N_sig; X_E <= X_E_sig; X_W <= X_W_sig; X_S <= X_S_sig; X_L <= X_L_sig; -- Arbiter_in Checkers module instantiation ARBITER_IN_CHECKERS: Arbiter_in_one_hot_checkers port map ( req_X_N => req_X_N, -- _sig not needed, because it is an input port req_X_E => req_X_E, -- _sig not needed, because it is an input port req_X_W => req_X_W, -- _sig not needed, because it is an input port req_X_S => req_X_S, -- _sig not needed, because it is an input port req_X_L => req_X_L, -- _sig not needed, because it is an input port state => state_faulty, -- _sig not needed, because it is an input port state_in => state_in_faulty, -- _sig not needed, because it is an internal signal X_N => X_N_sig_faulty, X_E => X_E_sig_faulty, X_W => X_W_sig_faulty, X_S => X_S_sig_faulty, X_L => X_L_sig_faulty, -- Checker outputs err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal, err_IDLE_Req_N => err_IDLE_Req_N, err_IDLE_grant_N => err_IDLE_grant_N, err_North_Req_N => err_North_Req_N, err_North_grant_N => err_North_grant_N, err_East_Req_E => err_East_Req_E, err_East_grant_E => err_East_grant_E, err_West_Req_W => err_West_Req_W, err_West_grant_W => err_West_grant_W, err_South_Req_S => err_South_Req_S, err_South_grant_S => err_South_grant_S, err_Local_Req_L => err_Local_Req_L, err_Local_grant_L => err_Local_grant_L, err_IDLE_Req_E => err_IDLE_Req_E, err_IDLE_grant_E => err_IDLE_grant_E, err_North_Req_E => err_North_Req_E, err_North_grant_E => err_North_grant_E, err_East_Req_W => err_East_Req_W, err_East_grant_W => err_East_grant_W, err_West_Req_S => err_West_Req_S, err_West_grant_S => err_West_grant_S, err_South_Req_L => err_South_Req_L, err_South_grant_L => err_South_grant_L, err_Local_Req_N => err_Local_Req_N, err_Local_grant_N => err_Local_grant_N, err_IDLE_Req_W => err_IDLE_Req_W, err_IDLE_grant_W => err_IDLE_grant_W, err_North_Req_W => err_North_Req_W, err_North_grant_W => err_North_grant_W, err_East_Req_S => err_East_Req_S, err_East_grant_S => err_East_grant_S, err_West_Req_L => err_West_Req_L, err_West_grant_L => err_West_grant_L, err_South_Req_N => err_South_Req_N, err_South_grant_N => err_South_grant_N, err_Local_Req_E => err_Local_Req_E, err_Local_grant_E => err_Local_grant_E, err_IDLE_Req_S => err_IDLE_Req_S, err_IDLE_grant_S => err_IDLE_grant_S, err_North_Req_S => err_North_Req_S, err_North_grant_S => err_North_grant_S, err_East_Req_L => err_East_Req_L, err_East_grant_L => err_East_grant_L, err_West_Req_N => err_West_Req_N, err_West_grant_N => err_West_grant_N, err_South_Req_E => err_South_Req_E, err_South_grant_E => err_South_grant_E, err_Local_Req_W => err_Local_Req_W, err_Local_grant_W => err_Local_grant_W, err_IDLE_Req_L => err_IDLE_Req_L, err_IDLE_grant_L => err_IDLE_grant_L, err_North_Req_L => err_North_Req_L, err_North_grant_L => err_North_grant_L, err_East_Req_N => err_East_Req_N, err_East_grant_N => err_East_grant_N, err_West_Req_E => err_West_Req_E, err_West_grant_E => err_West_grant_E, err_South_Req_W => err_South_Req_W, err_South_grant_W => err_South_grant_W, err_Local_Req_S => err_Local_Req_S, err_Local_grant_S => err_Local_grant_S, err_state_in_onehot => err_state_in_onehot, err_no_request_grants => err_no_request_grants, err_request_no_grants => err_request_no_grants, err_no_Req_N_grant_N => err_no_Req_N_grant_N, err_no_Req_E_grant_E => err_no_Req_E_grant_E, err_no_Req_W_grant_W => err_no_Req_W_grant_W, err_no_Req_S_grant_S => err_no_Req_S_grant_S, err_no_Req_L_grant_L => err_no_Req_L_grant_L ); -- Sequential part process (clk, reset)begin if reset = '0' then state <= IDLE; elsif clk'event and clk ='1'then state <= state_in; end if; end process; -- anything below here is pure combinational -- Main Logic of Arbiter_in process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L) begin X_N_sig <= '0'; X_E_sig <= '0'; X_W_sig <= '0'; X_S_sig <= '0'; X_L_sig <= '0'; case state is when IDLE => -- In the arbiter for hand-shaking FC router, L had the highest priority (L, N, E, W, S) -- Here it seems N has the higest priority, is it fine ? if req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; else state_in <= state; end if; when North => if req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; else state_in <= state; end if; when East => if req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; else state_in <= state; end if; when West => if req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; else state_in <= state; end if; when South => if req_X_S = '1' then state_in <= South; X_S_sig <= '1'; elsif req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; else state_in <= state; end if; when others => if req_X_L = '1' then state_in <= Local; X_L_sig <= '1'; elsif req_X_N ='1' then state_in <= North; X_N_sig <= '1'; elsif req_X_E = '1' then state_in <= East; X_E_sig <= '1'; elsif req_X_W = '1' then state_in <= West; X_W_sig <= '1'; elsif req_X_S = '1' then state_in <= South; X_S_sig <= '1'; else state_in <= state; end if; end case; end process; end;

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/dmem.vhd

9

12163

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block An6KsaiYrulwxqqCTyrSzzHcxhHI84q3UlaJ2ztMp0Y91rLK0dC0j2isQ24fiJZ0WhzYiZrCc0eG Whj66v/AMA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block PUXNoMyJk/CLuUZRXW6yA9w/aCvSD4KS0m+rQqTC9OMFAlMWa21jzZ1fElvoVCAArSjuCdB7ZUz6 VMCtVTWHmFRjDLUo6rJ56jZUnw7f+LD41SvmGWJAmWaSVCc030C9+ThQIs70xbnGcVnwZLoBcA6M p0jFfCvKHFeZTpbjvgs= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block UUAaUpoxmLITpPzkE5LmCRGKvZ0+JBe+f5cb87Lcc1AZMOyA9lnrCCHuEefru5gs9XsGILXZhTC5 nizT/MXh7Xtgf759AFdAyzC/KFttobnssXP1vjnVvnKS6dvQcRlbbZ0hxZ/8hvlhD7Heuoc71w2R kAxAKqVsKgxbbnTW+du2JF9Isee91EVej9zj1NYhuytNxf51EcF8VB+dssd2hcKYL0r+K2iEWqiq fGBVxPr2IUxXkoYk21Ucs5MaZvN4jYsVQWUUi4yOGBlVJng1LIj57/NE4WXUVAs7ni7c4N6d77xf /WNH+naxugwBnBiYVNJiEulZP9UdK0BsbbC+iA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block IDLw/3tQFeSorgOJ91Bg4RMVGmlWTvk0dAJHaR5H7TD+L+abFlQ0WuArltEBRxeeJodt8YWLRbva iMEf0MsflEGPr5xCr5v/0Nay8R88AcSroabyDH8N64M6yCye00ulFfXR6VOLurDD4nMFaphpVQ4p 9PqRf7HD33FJIZQ7ht4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block BKKj9+Qx1I58JoS/BxXZl3fLldE3jrRrg27/9nODwp2GR5QXBRqyf/M2GPdsdjaeSMgu3PZ2OLmk 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gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_top.vhd

9

40066

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block N69BdjVBL3zr447/IslHpcQt6uxnKlEGffBeT6O/HPhIhs63hO+yBTBpbZe83b9oQQkb3iO1iekX AN7IS+Oj8A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Q2gSgSjShBThnpN7ocpVeIiupKozmKwVJ1Ka9owDuAS9y4GGTKN6eXAv6ND3rH3bK2m5rmiGc2dQ GqvMSafR3R5aQyLhHV0vE9ItdvwRv/PiR6RGhNqN3zMe7lJ+6AH2FuJN2tV2YbHEWsMpvrS/ozM1 eW8vym4p2Nmkhc0/Q74= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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gpl-3.0

Project-Bonfire/EHA

RTL/Chip_Designs/IMMORTAL_Chip_2017/plasma_RTL/ram_xilinx.vhd

3

181451

--------------------------------------------------------------------- -- TITLE: Random Access Memory for Xilinx -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 11/06/05 -- FILENAME: ram_xilinx.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements Plasma internal RAM as RAMB for Spartan 3x -- -- Compile the MIPS C and assembly code into "test.axf". -- Run convert.exe to change "test.axf" to "code.txt" which -- will contain the hex values of the opcodes. -- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd", -- to create the "ram_image.vhd" file that will have the opcodes -- correctly placed inside the INIT_00 => strings. -- Then include ram_image.vhd in the simulation/synthesis. -- -- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache -- if the DDR cache is enabled. --------------------------------------------------------------------- -- UPDATED: 09/07/10 Olivier Rinaudo ([email protected]) -- new behaviour: 8KB expandable to 64KB of internal RAM -- -- MEMORY MAP -- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache) -- 2000..3FFF : 8KB 16KB block1 -- 4000..5FFF : 8KB 24KB block2 -- 6000..7FFF : 8KB 32KB block3 -- 8000..9FFF : 8KB 40KB block4 -- A000..BFFF : 8KB 48KB block5 -- C000..DFFF : 8KB 56KB block6 -- E000..FFFF : 8KB 64KB block7 --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.mlite_pack.all; library UNISIM; use UNISIM.vcomponents.all; entity ram is generic(memory_type : string := "DEFAULT"; --Number of 8KB blocks of internal RAM, up to 64KB (1 to 8) block_count : integer := 1); port(clk : in std_logic; enable : in std_logic; reset : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0)); end; --entity ram architecture logic of ram is --type type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0); --Which 8KB block alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13); --Address within a 8KB block (without lower two bits) alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2); --Block enable with 1 bit per memory block signal block_enable: std_logic_vector(7 downto 0); --Block Data Out signal block_do: mem32_vector(7 downto 0); --Remember which block was selected signal block_sel_buf: std_logic_vector(2 downto 0); begin block_enable<= "00000001" when (enable='1') and (block_sel="000") else "00000010" when (enable='1') and (block_sel="001") else "00000100" when (enable='1') and (block_sel="010") else "00001000" when (enable='1') and (block_sel="011") else "00010000" when (enable='1') and (block_sel="100") else "00100000" when (enable='1') and (block_sel="101") else "01000000" when (enable='1') and (block_sel="110") else "10000000" when (enable='1') and (block_sel="111") else "00000000"; proc_blocksel: process (clk, block_sel) is begin if rising_edge(clk) then block_sel_buf <= block_sel; end if; end process; proc_do: process (block_do, block_sel_buf) is begin data_read <= block_do(conv_integer(block_sel_buf)); end process; -- BLOCKS generation block0: if (block_count > 0) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(0)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(0), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block0 block1: if (block_count > 1) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(1)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(1), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block1 block2: if (block_count > 2) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(2)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(2), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block2 block3: if (block_count > 3) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(3)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(3), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block3 block4: if (block_count > 4) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(4)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(4), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block4 block5: if (block_count > 5) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(5)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(5), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block5 block6: if (block_count > 6) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(6)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(6), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block6 block7: if (block_count > 7) generate begin ram_byte3 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(31 downto 24), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(31 downto 24), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(3)); ram_byte2 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(23 downto 16), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(23 downto 16), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(2)); ram_byte1 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(15 downto 8), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(15 downto 8), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(1)); ram_byte0 : RAMB16_S9 generic map ( INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000" ) port map ( DO => block_do(7)(7 downto 0), DOP => open, ADDR => block_addr, CLK => clk, DI => data_write(7 downto 0), DIP => ZERO(0 downto 0), EN => block_enable(7), SSR => ZERO(0), WE => write_byte_enable(0)); end generate; --block7 end; --architecture logic

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/Kintex7_160T_experimental/Kintex7_160T_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/builtin/builtin_extdepth_low_latency.vhd

9

37992

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MZXEstTSOPKn8d5gf+3b10LFSw1L9kvafhezpuljrAF/7ghdUav62CewvwgRX4SemyQaR291yKZu bGSff5WMXg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block kLYSw7WMBCamT+m4atNFnoIZxka3g3JtON0cEggFoebXF71E9cyWqze2b5I3JNud2dq0mGJH86Cd tM81uqf2Xg9WhxjI6FuBts9Vex6Dv6Nj04kCYSbuxNDshz7+gd5ia/7qUkXzcA4guNI5WUF1UBV6 vDQhVHruydJ1Ww/FftE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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gpl-3.0

julioamerico/prj_crc_ip

src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/acb_96_bit/_primary.vhd

3

2560

library verilog; use verilog.vl_types.all; entity acb_96_bit is generic( ANALOG_QUAD_NUM : integer := 6; ACB_BYTES_NUM_PER_QUAD: integer := 12; WARNING_MSGS_ON : integer := 1 ); port( ACB_RST : in vl_logic; ACB_WEN : in vl_logic; ACB_ADDR : in vl_logic_vector(7 downto 0); ACB_WDATA : in vl_logic_vector(7 downto 0); ACB_RDATA : out vl_logic_vector(7 downto 0); AQO_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQO_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQO_AC_CONFIG : out vl_logic_vector(7 downto 0); AQO_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ0_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ1_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ1_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ1_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ1_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ1_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ2_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ2_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ2_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ2_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ2_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ3_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ3_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ3_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ3_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ3_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ4_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ4_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ4_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ4_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ4_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); AQ5_AV1_CONFIG : out vl_logic_vector(3 downto 0); AQ5_AV2_CONFIG : out vl_logic_vector(3 downto 0); AQ5_AC_CONFIG : out vl_logic_vector(7 downto 0); AQ5_AT_CONFIG : out vl_logic_vector(7 downto 0); AQ5_DAC_MUX_SEL : out vl_logic_vector(1 downto 0); DAC0_CONFIG : out vl_logic_vector(1 downto 0); DAC1_CONFIG : out vl_logic_vector(1 downto 0); DAC2_CONFIG : out vl_logic_vector(1 downto 0) ); end acb_96_bit;

gpl-3.0

hanw/Open-Source-FPGA-Bitcoin-Miner

projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/golden_ticket_fifo/blk_mem_gen_v8_0/blk_mem_axi_regs_fwd.vhd

9

9351

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block la25uVBWzC1l+JHhEL6c+Ts7V7z+YIo/kFZc/YoRuvF5aU3MaKWYyPlXeCJ89353nfhHkbdLXV4F nVVuxP9FyQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block nFg9pYQINwZA2M/ydTMPKxrCQrNDHt3RlR7cY6SpFxjoLHLbXhL1bAq6n1q9+Q2qjz6EazfBZ93K U0YpNGqnr+nqc2C5nb40zW2yQvfS4Rbw8mxQ73/lihHzruwr8kDVsMtt0iBxWrTieJOIk8/NeR2G +o/W4ndnrUAG/PfyIlA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block xuoFtB1eDGz1GlFErAZaPAS93bvbE5a9X5zV34MxLp8Ua9ky7RLKZwzWPuhW7tLpYh2ua4RSttmk dPsfayFAITrAU/dQAVWx4DUGO5t03cUgdN7ppPZLi5GX/MA95IxftPz2MIzhpH84Js1AO4luqQQc 5QxN9DH7mAIM0GVXwc0f48uoH19eD0/e7ciNMenZDiYHLFC4ACagzRoMnKlK4ZA6RSc1NIW6GfKa 8M1WYwzf0B7d/GeCgTpBG0FjkWha1+PPC3tNpTIzfUCoG9hESZTSV5bYv92St+WQ6sNnwG37tVqa iLDinljZPypL6xhmjimXUoCa+m62LGDkqdf4vQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P0dE5V9VUBP3x9gSL+lY/6kDeo+z3sDkMBilzcCbklSLv8Zh2uayd3oG98fq3BDs4Zyl2NIOR+4/ c3oQeFRXzhjxpRyK4NBrcY5gN80k3yvSH2WYV0Ha2x+39Jj8yQO/MunO8ZTCspwLwcHXnNHZNsHb SEAg+QS9ELaciwfw5D8= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block t3we8GV+pUi+tUpE/sSsfp+bLGtsUa2GACR/MBRAx8Rup76KD0FtZguzgORfNW3U/RRXivPYEwx2 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gpl-3.0

Project-Bonfire/EHA

RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/uart.vhd

6

7018

--------------------------------------------------------------------- -- TITLE: UART -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 5/29/02 -- FILENAME: uart.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the UART. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; use ieee.std_logic_textio.all; use ieee.std_logic_unsigned.all; use std.textio.all; use work.mlite_pack.all; entity uart is generic(log_file : string := "UNUSED"); port(clk : in std_logic; reset : in std_logic; enable_read : in std_logic; enable_write : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); uart_read : in std_logic; uart_write : out std_logic; busy_write : out std_logic; data_avail : out std_logic); end; --entity uart architecture logic of uart is signal delay_write_reg : std_logic_vector(9 downto 0); signal bits_write_reg : std_logic_vector(3 downto 0); signal data_write_reg : std_logic_vector(8 downto 0); signal delay_read_reg : std_logic_vector(9 downto 0); signal bits_read_reg : std_logic_vector(3 downto 0); signal data_read_reg : std_logic_vector(7 downto 0); signal data_save_reg : std_logic_vector(17 downto 0); signal busy_write_sig : std_logic; signal read_value_reg : std_logic_vector(6 downto 0); signal uart_read2 : std_logic; begin uart_proc: process(clk, reset, enable_read, enable_write, data_in, data_write_reg, bits_write_reg, delay_write_reg, data_read_reg, bits_read_reg, delay_read_reg, data_save_reg, read_value_reg, uart_read2, busy_write_sig, uart_read) constant COUNT_VALUE : std_logic_vector(9 downto 0) := -- "0100011110"; --33MHz/2/57600Hz = 0x11e -- "1101100100"; --50MHz/57600Hz = 0x364 "0110110010"; --25MHz/57600Hz = 0x1b2 -- Plasma IF uses div2 -- "0011011001"; --12.5MHz/57600Hz = 0xd9 -- "0000000100"; --for debug (shorten read_value_reg) begin uart_read2 <= read_value_reg(read_value_reg'length - 1); if reset = '1' then data_write_reg <= ZERO(8 downto 1) & '1'; bits_write_reg <= "0000"; delay_write_reg <= ZERO(9 downto 0); read_value_reg <= ONES(read_value_reg'length-1 downto 0); data_read_reg <= ZERO(7 downto 0); bits_read_reg <= "0000"; delay_read_reg <= ZERO(9 downto 0); data_save_reg <= ZERO(17 downto 0); elsif rising_edge(clk) then --Write UART if bits_write_reg = "0000" then --nothing left to write? if enable_write = '1' then delay_write_reg <= ZERO(9 downto 0); --delay before next bit bits_write_reg <= "1010"; --number of bits to write data_write_reg <= data_in & '0'; --remember data & start bit end if; else if delay_write_reg /= COUNT_VALUE then delay_write_reg <= delay_write_reg + 1; --delay before next bit else delay_write_reg <= ZERO(9 downto 0); --reset delay bits_write_reg <= bits_write_reg - 1; --bits left to write data_write_reg <= '1' & data_write_reg(8 downto 1); end if; end if; --Average uart_read signal if uart_read = '1' then if read_value_reg /= ONES(read_value_reg'length - 1 downto 0) then read_value_reg <= read_value_reg + 1; end if; else if read_value_reg /= ZERO(read_value_reg'length - 1 downto 0) then read_value_reg <= read_value_reg - 1; end if; end if; --Read UART if delay_read_reg = ZERO(9 downto 0) then --done delay for read? if bits_read_reg = "0000" then --nothing left to read? if uart_read2 = '0' then --wait for start bit delay_read_reg <= '0' & COUNT_VALUE(9 downto 1); --half period bits_read_reg <= "1001"; --bits left to read end if; else delay_read_reg <= COUNT_VALUE; --initialize delay bits_read_reg <= bits_read_reg - 1; --bits left to read data_read_reg <= uart_read2 & data_read_reg(7 downto 1); end if; else delay_read_reg <= delay_read_reg - 1; --delay end if; --Control character buffer if bits_read_reg = "0000" and delay_read_reg = COUNT_VALUE then if data_save_reg(8) = '0' or (enable_read = '1' and data_save_reg(17) = '0') then --Empty buffer data_save_reg(8 downto 0) <= '1' & data_read_reg; else --Second character in buffer data_save_reg(17 downto 9) <= '1' & data_read_reg; if enable_read = '1' then data_save_reg(8 downto 0) <= data_save_reg(17 downto 9); end if; end if; elsif enable_read = '1' then data_save_reg(17) <= '0'; --data_available data_save_reg(8 downto 0) <= data_save_reg(17 downto 9); end if; end if; --rising_edge(clk) uart_write <= data_write_reg(0); if bits_write_reg /= "0000" -- Comment out the following line for full UART simulation (much slower) and log_file = "UNUSED" then busy_write_sig <= '1'; else busy_write_sig <= '0'; end if; busy_write <= busy_write_sig; data_avail <= data_save_reg(8); data_out <= data_save_reg(7 downto 0); end process; --uart_proc -- synthesis_off uart_logger: if log_file /= "UNUSED" generate uart_proc: process(clk, enable_write, data_in) file store_file : text open write_mode is log_file; variable hex_file_line : line; variable c : character; variable index : natural; variable line_length : natural := 0; begin if rising_edge(clk) and busy_write_sig = '0' then if enable_write = '1' then index := conv_integer(data_in(6 downto 0)); if index /= 10 then c := character'val(index); write(hex_file_line, c); line_length := line_length + 1; end if; if index = 10 or line_length >= 72 then --The following line may have to be commented out for synthesis writeline(store_file, hex_file_line); line_length := 0; end if; end if; --uart_sel end if; --rising_edge(clk) end process; --uart_proc end generate; --uart_logger -- synthesis_on end; --architecture logic

gpl-3.0

freecores/usb_fpga_1_11

examples/usb-fpga-1.15y/ucecho/fpga/ucecho.vhd

6

737

library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ucecho is port( pc : in unsigned(7 downto 0); pb : out std_logic_vector(7 downto 0); CS : in std_logic; CLK : in std_logic -- SCL : in std_logic; -- SDA : in std_logic ); end ucecho; architecture RTL of ucecho is --signal declaration signal pb_buf : unsigned(7 downto 0); begin pb <= std_logic_vector( pb_buf ) when CS = '1' else (others => 'Z'); dpUCECHO: process(CLK) begin if CLK' event and CLK = '1' then if ( pc >= 97 ) and ( pc <= 122) then pb_buf <= pc - 32; else pb_buf <= pc; end if; end if; end process dpUCECHO; end RTL;

gpl-3.0

mistryalok/Zedboard

learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/vhdl/image_filter_PaintMask_32_0_1080_1920_s.vhd

2

24811

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity image_filter_PaintMask_32_0_1080_1920_s is port ( ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_start : IN STD_LOGIC; ap_done : OUT STD_LOGIC; ap_continue : IN STD_LOGIC; ap_idle : OUT STD_LOGIC; ap_ready : OUT STD_LOGIC; p_src_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_src_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_0_V_empty_n : IN STD_LOGIC; p_src_data_stream_0_V_read : OUT STD_LOGIC; p_src_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_1_V_empty_n : IN STD_LOGIC; p_src_data_stream_1_V_read : OUT STD_LOGIC; p_src_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_src_data_stream_2_V_empty_n : IN STD_LOGIC; p_src_data_stream_2_V_read : OUT STD_LOGIC; p_mask_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_mask_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_mask_data_stream_V_dout : IN STD_LOGIC_VECTOR (7 downto 0); p_mask_data_stream_V_empty_n : IN STD_LOGIC; p_mask_data_stream_V_read : OUT STD_LOGIC; p_dst_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_dst_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0); p_dst_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_0_V_full_n : IN STD_LOGIC; p_dst_data_stream_0_V_write : OUT STD_LOGIC; p_dst_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_1_V_full_n : IN STD_LOGIC; p_dst_data_stream_1_V_write : OUT STD_LOGIC; p_dst_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0); p_dst_data_stream_2_V_full_n : IN STD_LOGIC; p_dst_data_stream_2_V_write : OUT STD_LOGIC ); end; architecture behav of image_filter_PaintMask_32_0_1080_1920_s is constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001"; constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010"; constant ap_ST_pp0_stg0_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100"; constant ap_ST_st6_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011"; constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000"; constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111"; signal ap_done_reg : STD_LOGIC := '0'; signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; signal ap_sig_bdd_23 : BOOLEAN; signal p_4_reg_194 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_bdd_71 : BOOLEAN; signal exitcond4_fu_210_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; signal ap_sig_bdd_83 : BOOLEAN; signal i_V_fu_215_p2 : STD_LOGIC_VECTOR (10 downto 0); signal i_V_reg_280 : STD_LOGIC_VECTOR (10 downto 0); signal exitcond_fu_225_p2 : STD_LOGIC_VECTOR (0 downto 0); signal exitcond_reg_285 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_pp0_stg0_fsm_2 : STD_LOGIC; signal ap_sig_bdd_94 : BOOLEAN; signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0'; signal ap_sig_bdd_111 : BOOLEAN; signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0'; signal ap_reg_ppstg_exitcond_reg_285_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_bdd_125 : BOOLEAN; signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0'; signal j_V_fu_230_p2 : STD_LOGIC_VECTOR (10 downto 0); signal tmp_39_fu_242_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_39_reg_294 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_40_fu_250_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_40_reg_299 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_41_fu_258_p3 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_41_reg_304 : STD_LOGIC_VECTOR (7 downto 0); signal p_s_reg_183 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_cseq_ST_st6_fsm_3 : STD_LOGIC; signal ap_sig_bdd_158 : BOOLEAN; signal p_cast_fu_206_p1 : STD_LOGIC_VECTOR (11 downto 0); signal p_4_cast_fu_221_p1 : STD_LOGIC_VECTOR (11 downto 0); signal tmp_37_fu_236_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0); begin -- the current state (ap_CS_fsm) of the state machine. -- ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_CS_fsm <= ap_ST_st1_fsm_0; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; -- ap_done_reg assign process. -- ap_done_reg_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_done_reg <= ap_const_logic_0; else if ((ap_const_logic_1 = ap_continue)) then ap_done_reg <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond4_fu_210_p2 = ap_const_lv1_0)))) then ap_done_reg <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it0 assign process. -- ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0)))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_0; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it0 <= ap_const_logic_1; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it1 assign process. -- ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (exitcond_fu_225_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_1; elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0))))) then ap_reg_ppiten_pp0_it1 <= ap_const_logic_0; end if; end if; end if; end process; -- ap_reg_ppiten_pp0_it2 assign process. -- ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst = '1') then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; else if (not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2))))) then ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0))) then ap_reg_ppiten_pp0_it2 <= ap_const_logic_0; end if; end if; end if; end process; -- p_4_reg_194 assign process. -- p_4_reg_194_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and (exitcond_fu_225_p2 = ap_const_lv1_0))) then p_4_reg_194 <= j_V_fu_230_p2; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (exitcond4_fu_210_p2 = ap_const_lv1_0))) then p_4_reg_194 <= ap_const_lv11_0; end if; end if; end process; -- p_s_reg_183 assign process. -- p_s_reg_183_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not(ap_sig_bdd_71))) then p_s_reg_183 <= ap_const_lv11_0; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_3)) then p_s_reg_183 <= i_V_reg_280; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then ap_reg_ppstg_exitcond_reg_285_pp0_it1 <= exitcond_reg_285; exitcond_reg_285 <= exitcond_fu_225_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then i_V_reg_280 <= i_V_fu_215_p2; end if; end if; end process; -- assign process. -- process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then tmp_39_reg_294 <= tmp_39_fu_242_p3; tmp_40_reg_299 <= tmp_40_fu_250_p3; tmp_41_reg_304 <= tmp_41_fu_258_p3; end if; end if; end process; -- the next state (ap_NS_fsm) of the state machine. -- ap_NS_fsm_assign_proc : process (ap_CS_fsm, ap_sig_bdd_71, exitcond4_fu_210_p2, exitcond_fu_225_p2, ap_reg_ppiten_pp0_it0, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin case ap_CS_fsm is when ap_ST_st1_fsm_0 => if (not(ap_sig_bdd_71)) then ap_NS_fsm <= ap_ST_st2_fsm_1; else ap_NS_fsm <= ap_ST_st1_fsm_0; end if; when ap_ST_st2_fsm_1 => if (not((exitcond4_fu_210_p2 = ap_const_lv1_0))) then ap_NS_fsm <= ap_ST_st1_fsm_0; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_pp0_stg0_fsm_2 => if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; elsif ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))) and not((exitcond_fu_225_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1))))) then ap_NS_fsm <= ap_ST_st6_fsm_3; else ap_NS_fsm <= ap_ST_pp0_stg0_fsm_2; end if; when ap_ST_st6_fsm_3 => ap_NS_fsm <= ap_ST_st2_fsm_1; when others => ap_NS_fsm <= "XXXX"; end case; end process; -- ap_done assign process. -- ap_done_assign_proc : process(ap_done_reg, exitcond4_fu_210_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond4_fu_210_p2 = ap_const_lv1_0))))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; -- ap_idle assign process. -- ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) begin if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; -- ap_ready assign process. -- ap_ready_assign_proc : process(exitcond4_fu_210_p2, ap_sig_cseq_ST_st2_fsm_1) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((exitcond4_fu_210_p2 = ap_const_lv1_0)))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; -- ap_sig_bdd_111 assign process. -- ap_sig_bdd_111_assign_proc : process(p_src_data_stream_0_V_empty_n, p_src_data_stream_1_V_empty_n, p_src_data_stream_2_V_empty_n, p_mask_data_stream_V_empty_n, exitcond_reg_285) begin ap_sig_bdd_111 <= (((p_src_data_stream_0_V_empty_n = ap_const_logic_0) and (exitcond_reg_285 = ap_const_lv1_0)) or ((exitcond_reg_285 = ap_const_lv1_0) and (p_src_data_stream_1_V_empty_n = ap_const_logic_0)) or ((exitcond_reg_285 = ap_const_lv1_0) and (p_src_data_stream_2_V_empty_n = ap_const_logic_0)) or ((exitcond_reg_285 = ap_const_lv1_0) and (p_mask_data_stream_V_empty_n = ap_const_logic_0))); end process; -- ap_sig_bdd_125 assign process. -- ap_sig_bdd_125_assign_proc : process(p_dst_data_stream_0_V_full_n, p_dst_data_stream_1_V_full_n, p_dst_data_stream_2_V_full_n, ap_reg_ppstg_exitcond_reg_285_pp0_it1) begin ap_sig_bdd_125 <= (((p_dst_data_stream_0_V_full_n = ap_const_logic_0) and (ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1)) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (p_dst_data_stream_1_V_full_n = ap_const_logic_0)) or ((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (p_dst_data_stream_2_V_full_n = ap_const_logic_0))); end process; -- ap_sig_bdd_158 assign process. -- ap_sig_bdd_158_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_158 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; -- ap_sig_bdd_23 assign process. -- ap_sig_bdd_23_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; -- ap_sig_bdd_71 assign process. -- ap_sig_bdd_71_assign_proc : process(ap_start, ap_done_reg) begin ap_sig_bdd_71 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1)); end process; -- ap_sig_bdd_83 assign process. -- ap_sig_bdd_83_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_83 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; -- ap_sig_bdd_94 assign process. -- ap_sig_bdd_94_assign_proc : process(ap_CS_fsm) begin ap_sig_bdd_94 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; -- ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. -- ap_sig_cseq_ST_pp0_stg0_fsm_2_assign_proc : process(ap_sig_bdd_94) begin if (ap_sig_bdd_94) then ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_pp0_stg0_fsm_2 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st1_fsm_0 assign process. -- ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23) begin if (ap_sig_bdd_23) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st2_fsm_1 assign process. -- ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_83) begin if (ap_sig_bdd_83) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; end if; end process; -- ap_sig_cseq_ST_st6_fsm_3 assign process. -- ap_sig_cseq_ST_st6_fsm_3_assign_proc : process(ap_sig_bdd_158) begin if (ap_sig_bdd_158) then ap_sig_cseq_ST_st6_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_st6_fsm_3 <= ap_const_logic_0; end if; end process; exitcond4_fu_210_p2 <= "1" when (p_cast_fu_206_p1 = p_dst_rows_V_read) else "0"; exitcond_fu_225_p2 <= "1" when (p_4_cast_fu_221_p1 = p_dst_cols_V_read) else "0"; i_V_fu_215_p2 <= std_logic_vector(unsigned(p_s_reg_183) + unsigned(ap_const_lv11_1)); j_V_fu_230_p2 <= std_logic_vector(unsigned(p_4_reg_194) + unsigned(ap_const_lv11_1)); p_4_cast_fu_221_p1 <= std_logic_vector(resize(unsigned(p_4_reg_194),12)); p_cast_fu_206_p1 <= std_logic_vector(resize(unsigned(p_s_reg_183),12)); p_dst_data_stream_0_V_din <= tmp_39_reg_294; -- p_dst_data_stream_0_V_write assign process. -- p_dst_data_stream_0_V_write_assign_proc : process(ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_reg_285_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_dst_data_stream_0_V_write <= ap_const_logic_1; else p_dst_data_stream_0_V_write <= ap_const_logic_0; end if; end process; p_dst_data_stream_1_V_din <= tmp_40_reg_299; -- p_dst_data_stream_1_V_write assign process. -- p_dst_data_stream_1_V_write_assign_proc : process(ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_reg_285_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_dst_data_stream_1_V_write <= ap_const_logic_1; else p_dst_data_stream_1_V_write <= ap_const_logic_0; end if; end process; p_dst_data_stream_2_V_din <= tmp_41_reg_304; -- p_dst_data_stream_2_V_write assign process. -- p_dst_data_stream_2_V_write_assign_proc : process(ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_reg_ppstg_exitcond_reg_285_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_lv1_0 = ap_reg_ppstg_exitcond_reg_285_pp0_it1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_dst_data_stream_2_V_write <= ap_const_logic_1; else p_dst_data_stream_2_V_write <= ap_const_logic_0; end if; end process; -- p_mask_data_stream_V_read assign process. -- p_mask_data_stream_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_mask_data_stream_V_read <= ap_const_logic_1; else p_mask_data_stream_V_read <= ap_const_logic_0; end if; end process; -- p_src_data_stream_0_V_read assign process. -- p_src_data_stream_0_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_src_data_stream_0_V_read <= ap_const_logic_1; else p_src_data_stream_0_V_read <= ap_const_logic_0; end if; end process; -- p_src_data_stream_1_V_read assign process. -- p_src_data_stream_1_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_src_data_stream_1_V_read <= ap_const_logic_1; else p_src_data_stream_1_V_read <= ap_const_logic_0; end if; end process; -- p_src_data_stream_2_V_read assign process. -- p_src_data_stream_2_V_read_assign_proc : process(exitcond_reg_285, ap_sig_cseq_ST_pp0_stg0_fsm_2, ap_sig_bdd_111, ap_reg_ppiten_pp0_it1, ap_sig_bdd_125, ap_reg_ppiten_pp0_it2) begin if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_2) and (exitcond_reg_285 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1) and not(((ap_sig_bdd_111 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1)) or (ap_sig_bdd_125 and (ap_const_logic_1 = ap_reg_ppiten_pp0_it2)))))) then p_src_data_stream_2_V_read <= ap_const_logic_1; else p_src_data_stream_2_V_read <= ap_const_logic_0; end if; end process; tmp_37_fu_236_p2 <= "1" when (p_mask_data_stream_V_dout = ap_const_lv8_0) else "0"; tmp_39_fu_242_p3 <= p_src_data_stream_0_V_dout when (tmp_37_fu_236_p2(0) = '1') else ap_const_lv8_FF; tmp_40_fu_250_p3 <= p_src_data_stream_1_V_dout when (tmp_37_fu_236_p2(0) = '1') else ap_const_lv8_0; tmp_41_fu_258_p3 <= p_src_data_stream_2_V_dout when (tmp_37_fu_236_p2(0) = '1') else ap_const_lv8_0; end behav;

gpl-3.0

mistryalok/Zedboard

learning/training/MSD/s09/axi_dma_sg/vivado/project_1/project_1.srcs/sources_1/ipshared/xilinx.com/lib_fifo_v1_0/ca55fafe/hdl/src/vhdl/sync_fifo_fg.vhd

7

69796

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The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: sync_fifo_fg.vhd -- -- Description: -- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new -- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on -- the fly" call of FIFO Generator during design implementation. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- sync_fifo_fg.vhd -- | -- |-- fifo_generator_v4_3 -- | -- |-- fifo_generator_v9_3 -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- Revision: $Revision: 1.5.2.68 $ -- Date: $1/16/2008$ -- -- History: -- DET 1/16/2008 Initial Version -- -- DET 7/30/2008 for EDK 11.1 -- ~~~~~~ -- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3 -- ^^^^^^ -- -- MSH and DET 3/2/2009 For Lava SP2 -- ~~~~~~ -- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6 -- devices. -- - IfGen used so that legacy FPGA families still use Fifo Generator -- version 4.3. -- ^^^^^^ -- -- DET 4/9/2009 EDK 11.2 -- ~~~~~~ -- - Replaced FIFO Generator version 5.1 with 5.2. -- ^^^^^^ -- -- -- DET 2/9/2010 for EDK 12.1 -- ~~~~~~ -- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3. -- ^^^^^^ -- -- DET 3/10/2010 For EDK 12.x -- ~~~~~~ -- -- Per CR553307 -- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1. -- ^^^^^^ -- -- DET 6/18/2010 EDK_MS2 -- ~~~~~~ -- -- Per IR565916 -- - Added derivative part type checks for S6 or V6. -- ^^^^^^ -- -- DET 8/30/2010 EDK_MS4 -- ~~~~~~ -- -- Per CR573867 -- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2. -- - Added all of the AXI parameters and ports. They are not used -- in this application. -- - Updated method for derivative part support using new family -- aliasing function in family_support.vhd. -- - Incorporated an implementation to deal with unsupported FPGA -- parts passed in on the C_FAMILY parameter. -- ^^^^^^ -- -- DET 10/4/2010 EDK 13.1 -- ~~~~~~ -- - Updated the FIFO Generator version from V7.2 to 7.3. -- ^^^^^^ -- -- DET 12/8/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR586109 -- - Updated the FIFO Generator version from V7.3 to 8.1. -- ^^^^^^ -- -- DET 3/2/2011 EDK 13.2 -- ~~~~~~ -- -- Per CR595473 -- - Update to use fifo_generator_v8_2 -- ^^^^^^ -- -- -- RBODDU 08/18/2011 EDK 13.3 -- ~~~~~~ -- - Update to use fifo_generator_v8_3 -- ^^^^^^ -- -- RBODDU 06/07/2012 EDK 14.2 -- ~~~~~~ -- - Update to use fifo_generator_v9_1 -- ^^^^^^ -- RBODDU 06/11/2012 EDK 14.4 -- ~~~~~~ -- - Update to use fifo_generator_v9_2 -- ^^^^^^ -- RBODDU 07/12/2012 EDK 14.5 -- ~~~~~~ -- - Update to use fifo_generator_v9_3 -- ^^^^^^ -- RBODDU 07/12/2012 EDK 14.5 -- ~~~~~~ -- - Update to use fifo_generator_v12_0 -- - Added sleep, wr_rst_busy, and rd_rst_busy signals -- - Changed FULL_FLAGS_RST_VAL to '1' -- ^^^^^^ -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library fifo_generator_v12_0; use fifo_generator_v12_0.all; ------------------------------------------------------------------------------- entity sync_fifo_fg is generic ( C_FAMILY : String := "virtex5"; -- new for FIFO Gen C_DCOUNT_WIDTH : integer := 4 ; C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo C_HAS_DCOUNT : integer := 1 ; C_HAS_RD_ACK : integer := 0 ; C_HAS_RD_ERR : integer := 0 ; C_HAS_WR_ACK : integer := 0 ; C_HAS_WR_ERR : integer := 0 ; C_HAS_ALMOST_FULL : integer := 0 ; C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM C_PORTS_DIFFER : integer := 0 ; C_RD_ACK_LOW : integer := 0 ; C_USE_EMBEDDED_REG : integer := 0 ; C_READ_DATA_WIDTH : integer := 16; C_READ_DEPTH : integer := 16; C_RD_ERR_LOW : integer := 0 ; C_WR_ACK_LOW : integer := 0 ; C_WR_ERR_LOW : integer := 0 ; C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through C_WRITE_DATA_WIDTH : integer := 16; C_WRITE_DEPTH : integer := 16; C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8 ); port ( Clk : in std_logic; Sinit : in std_logic; Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0); Wr_en : in std_logic; Rd_en : in std_logic; Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0); Almost_full : out std_logic; Full : out std_logic; Empty : out std_logic; Rd_ack : out std_logic; Wr_ack : out std_logic; Rd_err : out std_logic; Wr_err : out std_logic; Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0) ); end entity sync_fifo_fg; architecture implementation of sync_fifo_fg is -- Function delarations function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val*2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; end function log2; ------------------------------------------------------------------- -- Function -- -- Function Name: GetMaxDepth -- -- Function Description: -- Returns the largest value of either Write depth or Read depth -- requested by input parameters. -- ------------------------------------------------------------------- function GetMaxDepth (rd_depth : integer; wr_depth : integer) return integer is Variable max_value : integer := 0; begin If (rd_depth < wr_depth) Then max_value := wr_depth; else max_value := rd_depth; End if; return(max_value); end function GetMaxDepth; ------------------------------------------------------------------- -- Function -- -- Function Name: GetMemType -- -- Function Description: -- Generates the required integer value for the FG instance assignment -- of the C_MEMORY_TYPE parameter. Derived from -- the input memory type parameter C_MEMORY_TYPE. -- -- FIFO Generator values -- 0 = Any -- 1 = BRAM -- 2 = Distributed Memory -- 3 = Shift Registers -- ------------------------------------------------------------------- function GetMemType (inputmemtype : integer) return integer is Variable memtype : Integer := 0; begin If (inputmemtype = 0) Then -- distributed Memory memtype := 2; else memtype := 1; -- BRAM End if; return(memtype); end function GetMemType; -- Constant Declarations ---------------------------------------------- -- changing this to C_FAMILY Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd -- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily")); -- lib_fifo supports all families Constant FAMILY_IS_SUPPORTED : boolean := true; --Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and -- FAMILY_IS_SUPPORTED; --Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and -- FAMILY_IS_SUPPORTED; -- Calculate associated FIFO characteristics Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH); Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1; Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1; -- Get the integer value for a Block memory type fifo generator call Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE); -- Set the required integer value for the FG instance assignment -- of the C_IMPLEMENTATION_TYPE parameter. Derived from -- the input memory type parameter C_MEMORY_TYPE. -- -- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO) -- 1 = Common Clock Shift Register (Synchronous FIFO) -- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO) -- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls -- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls -- Constant FG_IMP_TYPE : integer := 0; -- The programable thresholds are not used so this is housekeeping. Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3; Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4; -- Constant zeros for programmable threshold inputs signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- Signals signal sig_full : std_logic; signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0); signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0); --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal ALMOST_EMPTY : std_logic; signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0); signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0); signal PROG_FULL : std_logic; signal PROG_EMPTY : std_logic; signal SBITERR : std_logic; signal DBITERR : std_logic; signal WR_RST_BUSY : std_logic; signal RD_RST_BUSY : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BID : std_logic_vector(3 DOWNTO 0); signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_BUSER : std_logic_vector(0 downto 0); signal S_AXI_BVALID : std_logic; -- AXI Full/Lite Master Write Channel (Read side) signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0); signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWUSER : std_logic_vector(0 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_WID : std_logic_vector(3 DOWNTO 0); signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0); signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0); signal M_AXI_WLAST : std_logic; signal M_AXI_WUSER : std_logic_vector(0 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_BREADY : std_logic; -- AXI Full/Lite Slave Read Channel (Write side) signal S_AXI_ARREADY : std_logic; signal S_AXI_RID : std_logic_vector(3 DOWNTO 0); signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0); signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_RLAST : std_logic; signal S_AXI_RUSER : std_logic_vector(0 downto 0); signal S_AXI_RVALID : std_logic; -- AXI Full/Lite Master Read Channel (Read side) signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0); signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARUSER : std_logic_vector(0 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_RREADY : std_logic; -- AXI Streaming Slave Signals (Write side) signal S_AXIS_TREADY : std_logic; -- AXI Streaming Master Signals (Read side) signal M_AXIS_TVALID : std_logic; signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0); signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TLAST : std_logic; signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0); signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_SBITERR : std_logic; signal AXI_AW_DBITERR : std_logic; signal AXI_AW_OVERFLOW : std_logic; signal AXI_AW_UNDERFLOW : std_logic; signal AXI_AW_PROG_FULL : STD_LOGIC; signal AXI_AW_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Data Channel Signals signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_SBITERR : std_logic; signal AXI_W_DBITERR : std_logic; signal AXI_W_OVERFLOW : std_logic; signal AXI_W_UNDERFLOW : std_logic; signal AXI_W_PROG_FULL : STD_LOGIC; signal AXI_W_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Response Channel Signals signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_SBITERR : std_logic; signal AXI_B_DBITERR : std_logic; signal AXI_B_OVERFLOW : std_logic; signal AXI_B_UNDERFLOW : std_logic; signal AXI_B_PROG_FULL : STD_LOGIC; signal AXI_B_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Address Channel Signals signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_SBITERR : std_logic; signal AXI_AR_DBITERR : std_logic; signal AXI_AR_OVERFLOW : std_logic; signal AXI_AR_UNDERFLOW : std_logic; signal AXI_AR_PROG_FULL : STD_LOGIC; signal AXI_AR_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Data Channel Signals signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_SBITERR : std_logic; signal AXI_R_DBITERR : std_logic; signal AXI_R_OVERFLOW : std_logic; signal AXI_R_UNDERFLOW : std_logic; signal AXI_R_PROG_FULL : STD_LOGIC; signal AXI_R_PROG_EMPTY : STD_LOGIC; -- AXI Streaming FIFO Related Signals signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_SBITERR : std_logic; signal AXIS_DBITERR : std_logic; signal AXIS_OVERFLOW : std_logic; signal AXIS_UNDERFLOW : std_logic; signal AXIS_PROG_FULL : STD_LOGIC; signal AXIS_PROG_EMPTY : STD_LOGIC; begin --(architecture implementation) ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_FAMILY -- -- If Generate Description: -- This IfGen is implemented if an unsupported FPGA family -- is passed in on the C_FAMILY parameter, -- ------------------------------------------------------------ -- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate -- begin -- synthesis translate_off ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_ASSERTION -- -- Process Description: -- Generate a simulation error assertion for an unsupported -- FPGA family string passed in on the C_FAMILY parameter. -- ------------------------------------------------------------- -- DO_ASSERTION : process -- begin -- Wait until second rising clock edge to issue assertion -- Wait until Clk = '1'; -- wait until Clk = '0'; -- Wait until Clk = '1'; -- Report an error in simulation environment -- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!" -- severity ERROR; -- Wait;-- halt this process -- end process DO_ASSERTION; -- synthesis translate_on -- Tie outputs to logic low or logic high as required -- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0); -- Almost_full <= '0' ; -- : out std_logic; -- Full <= '0' ; -- : out std_logic; -- Empty <= '1' ; -- : out std_logic; -- Rd_ack <= '0' ; -- : out std_logic; -- Wr_ack <= '0' ; -- : out std_logic; -- Rd_err <= '1' ; -- : out std_logic; -- Wr_err <= '1' ; -- : out std_logic -- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0); -- end generate GEN_NO_FAMILY; ------------------------------------------------------------ -- If Generate -- -- Label: V6_S6_AND_LATER -- -- If Generate Description: -- This IfGen implements the fifo using fifo_generator_v9_3 -- when the designated FPGA Family is Spartan-6, Virtex-6 or -- later. -- ------------------------------------------------------------ FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate begin UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu") generate begin Full <= sig_full or WR_RST_BUSY; end generate UltraScale_device; Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu") generate begin Full <= sig_full; end generate Series7_device; -- Create legacy data count by concatonating the Full flag to the -- MS Bit position of the FIFO data count -- This is per the Fifo Generator Migration Guide sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt; Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto FGEN_CNT_WIDTH-C_DCOUNT_WIDTH); ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen FIFO Generator Call module for -- BRAM implementations of a legacy Sync FIFO -- ------------------------------------------------------------------------------- I_SYNC_FIFO_BRAM : entity fifo_generator_v12_0.fifo_generator_v12_0 generic map( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ??? C_DEFAULT_VALUE => "BlankString", -- what to do here ??? C_DIN_WIDTH => C_WRITE_DATA_WIDTH, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => C_READ_DATA_WIDTH, C_ENABLE_RLOCS => 0, -- not supported C_FAMILY => FAMILY_TO_USE, C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 1, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => C_HAS_DCOUNT, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => C_HAS_WR_ERR, C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO C_HAS_RD_RST => 0, -- not used for sync FIFO C_HAS_RST => 0, -- not used for sync FIFO C_HAS_SRST => 1, C_HAS_UNDERFLOW => C_HAS_RD_ERR, C_HAS_VALID => C_HAS_RD_ACK, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO C_HAS_WR_RST => 0, -- not used for sync FIFO C_IMPLEMENTATION_TYPE => FG_IMP_TYPE, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => FG_MEM_TYPE, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => C_WR_ERR_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, C_RD_DEPTH => MAX_DEPTH, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH, C_UNDERFLOW_LOW => C_RD_ERR_LOW, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129 C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => C_RD_ACK_LOW, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, C_WR_DEPTH => MAX_DEPTH, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_AXI_LEN_WIDTH => 8, -- : integer := 8; C_AXI_LOCK_WIDTH => 2, -- : integer := 2; C_HAS_AXI_ID => 0, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) port map( backup => '0', backup_marker => '0', clk => Clk, rst => '0', srst => Sinit, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => Din, wr_en => Wr_en, rd_en => Rd_en, prog_empty_thresh => PROG_RDTHRESH_ZEROS, prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, prog_full_thresh => PROG_WRTHRESH_ZEROS, prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, int_clk => '0', injectdbiterr => '0', -- new FG 5.1/5.2 injectsbiterr => '0', -- new FG 5.1/5.2 sleep => '0', dout => Dout, full => sig_full, almost_full => Almost_full, wr_ack => Wr_ack, overflow => Wr_err, empty => Empty, almost_empty => ALMOST_EMPTY, valid => Rd_ack, underflow => Rd_err, data_count => sig_prim_fg_datacnt, rd_data_count => RD_DATA_COUNT, wr_data_count => WR_DATA_COUNT, prog_full => PROG_FULL, prog_empty => PROG_EMPTY, sbiterr => SBITERR, dbiterr => DBITERR, wr_rst_busy => WR_RST_BUSY, rd_rst_busy => RD_RST_BUSY, -- AXI Global Signal m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); end generate FAMILY_SUPPORTED; end implementation;

gpl-3.0

davidhorrocks/1541UltimateII

fpga/io/uart_lite/vhdl_source/uart_peripheral.vhd

5

4651

library ieee; use ieee.std_logic_1164.all; entity uart_peripheral is generic ( tx_fifo : boolean := true; divisor : natural := 417 ); port ( clock : in std_logic; reset : in std_logic; bus_select : in std_logic; bus_write : in std_logic; bus_addr : in std_logic_vector(1 downto 0); bus_wdata : in std_logic_vector(7 downto 0); bus_rdata : out std_logic_vector(7 downto 0); uart_irq : out std_logic; txd : out std_logic; rxd : in std_logic ); end uart_peripheral; architecture gideon of uart_peripheral is signal dotx : std_logic; signal done : std_logic; signal rxchar : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal rxfifo_get : std_logic; signal rxfifo_dout : std_logic_vector(7 downto 0); signal rxfifo_full : std_logic; signal rxfifo_dav : std_logic; signal overflow : std_logic; signal flags : std_logic_vector(7 downto 0); signal imask : std_logic_vector(7 downto 6); signal txfifo_get : std_logic; signal txfifo_put : std_logic; signal txfifo_dout : std_logic_vector(7 downto 0); signal txfifo_full : std_logic := '1'; signal txfifo_dav : std_logic; signal dotx_d : std_logic; signal txchar : std_logic_vector(7 downto 0); begin my_tx: entity work.tx generic map (divisor) port map ( clk => clock, reset => reset, dotx => dotx, txchar => txchar, txd => txd, done => done ); my_rx: entity work.rx generic map (divisor) port map ( clk => clock, reset => reset, rxd => rxd, rxchar => rxchar, rx_ack => rx_ack ); my_rxfifo: entity work.srl_fifo generic map ( Width => 8, Threshold => 12 ) port map ( clock => clock, reset => reset, GetElement => rxfifo_get, PutElement => rx_ack, FlushFifo => '0', DataIn => rxchar, DataOut => rxfifo_dout, SpaceInFifo => open, AlmostFull => rxfifo_full, DataInFifo => rxfifo_dav ); gentx: if tx_fifo generate my_txfifo: entity work.srl_fifo generic map ( Width => 8, Threshold => 12 ) port map ( clock => clock, reset => reset, GetElement => txfifo_get, PutElement => txfifo_put, FlushFifo => '0', DataIn => bus_wdata, DataOut => txfifo_dout, SpaceInFifo => open, AlmostFull => txfifo_full, DataInFifo => txfifo_dav ); end generate; process(bus_select, bus_write, bus_addr, txfifo_dav, bus_wdata, txfifo_dout, done) begin if not tx_fifo then txfifo_put <= '0'; txchar <= bus_wdata; if bus_select='1' and bus_write='1' and bus_addr="00" then dotx <= '1'; else dotx <= '0'; end if; else -- there is a fifo dotx <= txfifo_dav and done; txchar <= txfifo_dout; if bus_select='1' and bus_write='1' and bus_addr="00" then txfifo_put <= '1'; else txfifo_put <= '0'; end if; end if; end process; process(clock) begin if rising_edge(clock) then rxfifo_get <= '0'; dotx_d <= dotx; txfifo_get <= dotx_d; if rxfifo_full='1' and rx_ack='1' then overflow <= '1'; end if; if bus_select='1' and bus_write='1' then case bus_addr is when "00" => -- dout null; -- covered by combi statement when "01" => -- din rxfifo_get <= '1'; when "10" => -- clear flags overflow <= overflow and not bus_wdata(0); when "11" => -- interrupt control imask <= bus_wdata(7 downto 6); when others => null; end case; end if; if reset='1' then overflow <= '0'; imask <= (others => '0'); end if; end if; end process; flags(0) <= overflow; flags(1) <= '0'; flags(2) <= '0'; flags(3) <= '0'; flags(4) <= txfifo_full; flags(5) <= rxfifo_full; flags(6) <= done; flags(7) <= rxfifo_dav; with bus_addr select bus_rdata <= rxfifo_dout when "00", flags when "10", imask & "000000" when "11", X"00" when others; uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0'; end gideon;

gpl-3.0

davidhorrocks/1541UltimateII

target/simulation/packages/vhdl_bfm/wave_pkg.vhd

5

5471

------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 - Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Wave package ------------------------------------------------------------------------------- -- File : wave_pkg.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This package provides ways to write (and maybe in future read) -- .wav files. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tl_flat_memory_model_pkg.all; use work.tl_file_io_pkg.all; package wave_pkg is type t_wave_channel is record number_of_samples : integer; memory : h_mem_object; end record; type t_wave_channel_array is array(natural range <>) of t_wave_channel; procedure open_channel(chan : out t_wave_channel); procedure push_sample(chan : inout t_wave_channel; sample : integer); procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array); end package; package body wave_pkg is procedure open_channel(chan : out t_wave_channel) is variable ch : t_wave_channel; begin register_mem_model("path", "channel", ch.memory); ch.number_of_samples := 0; chan := ch; end procedure; procedure push_sample(chan : inout t_wave_channel; sample : integer) is variable s : integer; begin s := sample; if s > 32767 then s := 32767; end if; if s < -32768 then s := -32768; end if; write_memory_int(chan.memory, chan.number_of_samples, s); chan.number_of_samples := chan.number_of_samples + 1; end procedure; procedure write_vector_le(x : std_logic_vector; file f : t_binary_file; r : inout t_binary_file_rec) is variable bytes : integer := (x'length + 7) / 8; variable xa : std_logic_vector(7+bytes*8 downto 0); begin xa := (others => '0'); xa(x'length-1 downto 0) := x; for i in 0 to bytes-1 loop write_byte(f, xa(i*8+7 downto i*8), r); end loop; end procedure; procedure write_int_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is variable x_slv : std_logic_vector(31 downto 0); begin x_slv := std_logic_vector(to_signed(x, 32)); write_vector_le(x_slv, f, r); end procedure; procedure write_short_le(x : integer; file f : t_binary_file; r : inout t_binary_file_rec) is variable x_slv : std_logic_vector(15 downto 0); begin x_slv := std_logic_vector(to_signed(x, 16)); write_vector_le(x_slv, f, r); end procedure; procedure write_wave(name: string; rate : integer; channels : t_wave_channel_array) is file myfile : t_binary_file; variable myrec : t_binary_file_rec; variable stat : file_open_status; variable file_size : integer; variable data_size : integer; variable max_length : integer; begin -- open file file_open(stat, myfile, name, write_mode); assert (stat = open_ok) report "Could not open file " & name & " for writing." severity failure; init_record(myrec); max_length := 0; for i in channels'range loop if channels(i).number_of_samples > max_length then max_length := channels(i).number_of_samples; end if; end loop; data_size := (max_length * channels'length * 2); file_size := 12 + 16 + 8 + data_size; -- header write_vector_le(X"46464952", myfile, myrec); -- "RIFF" write_int_le (file_size-8, myfile, myrec); write_vector_le(X"45564157", myfile, myrec); -- "WAVE" -- chunk header write_vector_le(X"20746D66", myfile, myrec); -- "fmt " write_int_le (16, myfile, myrec); write_short_le (1, myfile, myrec); -- compression code = uncompressed write_short_le (channels'length, myfile, myrec); write_int_le (rate, myfile, myrec); -- sample rate write_int_le (rate * channels'length * 2, myfile, myrec); -- Bps write_short_le (channels'length * 2, myfile, myrec); -- alignment write_short_le (16, myfile, myrec); -- bits per sample write_vector_le(X"61746164", myfile, myrec); -- "data" write_int_le (data_size, myfile, myrec); -- now write out all data! for i in 0 to max_length-1 loop for j in channels'range loop write_short_le(read_memory_int(channels(j).memory, i), myfile, myrec); end loop; end loop; purge(myfile, myrec); file_close(myfile); end procedure; end;

gpl-3.0

freecores/light8080

vhdl/light8080.vhdl

1

52124

--############################################################################## -- light8080 : Intel 8080 binary compatible core --############################################################################## -- v1.1 (20 sep 2008) Microcode bug in INR fixed. -- v1.0 (05 nov 2007) First release. Jose A. Ruiz. -- -- This file and all the light8080 project files are freeware (See COPYING.TXT) --############################################################################## -- (See timing diagrams at bottom of file. More comprehensive explainations can -- be found in the design notes) --############################################################################## library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --############################################################################## -- vma : enable a memory or io r/w access. -- io : access in progress is io (and not memory) -- rd : read memory or io -- wr : write memory or io -- data_out : data output -- addr_out : memory and io address -- data_in : data input -- halt : halt status (1 when in halt state) -- inte : interrupt status (1 when enabled) -- intr : interrupt request -- inta : interrupt acknowledge -- reset : synchronous reset -- clk : clock -- -- (see timing diagrams at bottom of file) --############################################################################## entity light8080 is Port ( addr_out : out std_logic_vector(15 downto 0); inta : out std_logic; inte : out std_logic; halt : out std_logic; intr : in std_logic; vma : out std_logic; io : out std_logic; rd : out std_logic; wr : out std_logic; fetch : out std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); clk : in std_logic; reset : in std_logic ); end light8080; --############################################################################## -- All memory and io accesses are synchronous (rising clock edge). Signal vma -- works as the master memory and io synchronous enable. More specifically: -- -- * All memory/io control signals (io,rd,wr) are valid only when vma is -- high. They never activate when vms is inactive. -- * Signals data_out and address are only valid when vma='1'. The high -- address byte is 0x00 for all io accesses. -- * Signal data_in should be valid by the end of the cycle after vma='1', -- data is clocked in by the rising clock edge. -- -- All signals are assumed to be synchronous to the master clock. Prevention of -- metastability, if necessary, is up to you. -- -- Signal reset needs to be active for just 1 clock cycle (it is sampled on a -- positive clock edge and is subject to setup and hold times). -- Once reset is deasserted, the first fetch at address 0x0000 will happen 4 -- cycles later. -- -- Signal intr is sampled on all positive clock edges. If asserted when inte is -- high, interrupts will be disabled, inta will be asserted high and a fetch -- cycle will occur. The fetched instruction will be executed normally, except -- PC will not be valid in any subsequent fetch cycles of the same instruction, -- and will not be incremented (In practice, the same as the original 8080). -- inta will remain high for the duration of the fetched instruction (in the -- original 8080 it was high only for the opcode fetch cycle). -- PC will not be autoincremented while inta is high, but it can be explicitly -- modified (e.g. RTS, CALL, etc.). Again, the same as the original. -- Interrupts will be disabled upon assertion of inta, and remain disabled -- until explicitly enabled by the program (as in the original). -- -- The above means that any instruction can be supplied in an inta cycle, -- either single byte or multibyte. See the design notes. --############################################################################## architecture microcoded of light8080 is -- addr_low: low byte of address signal addr_low : std_logic_vector(7 downto 0); -- IR: instruction register. some bits left unused. signal IR : std_logic_vector(7 downto 0); -- s_field: IR field, sss source reg code signal s_field : std_logic_vector(2 downto 0); -- d_field: IR field, ddd destination reg code signal d_field : std_logic_vector(2 downto 0); -- p_field: IR field, pp 16-bit reg pair code signal p_field : std_logic_vector(1 downto 0); -- rbh: 1 when p_field=11, used in reg bank addressing for 'special' regs signal rbh : std_logic; -- 1 when P=11 (special case) -- alu_op: uinst field, ALU operation code signal alu_op : std_logic_vector(3 downto 0); -- DI: data input to ALU block from data_in, unregistered signal DI : std_logic_vector(7 downto 0); -- uc_addr: microcode (ucode) address signal uc_addr : std_logic_vector(7 downto 0); -- next_uc_addr: computed next microcode address (uaddr++/jump/ret/fetch) signal next_uc_addr : std_logic_vector(8 downto 0); -- uc_jmp_addr: uinst field, absolute ucode jump address signal uc_jmp_addr : std_logic_vector(7 downto 0); -- uc_ret_address: ucode return address saved in previous jump signal uc_ret_addr : std_logic_vector(7 downto 0); -- addr_plus_1: uaddr + 1 signal addr_plus_1 : std_logic_vector(7 downto 0); -- do_reset: reset, delayed 1 cycle -- used to reset the microcode sequencer signal do_reset : std_logic; -- uc_flags1: uinst field, encoded flag of group 1 (see ucode file) signal uc_flags1 : std_logic_vector(2 downto 0); -- uc_flags2: uinst field, encoded flag of group 2 (see ucode file) signal uc_flags2 : std_logic_vector(2 downto 0); -- uc_addr_sel: selection of next uc_addr, composition of 4 flags signal uc_addr_sel : std_logic_vector(3 downto 0); -- NOTE: see microcode file for information on flags signal uc_jsr : std_logic; -- uinst field, decoded 'jsr' flag signal uc_tjsr : std_logic; -- uinst field, decoded 'tjsr' flag signal uc_decode : std_logic; -- uinst field, decoded 'decode' flag signal uc_end : std_logic; -- uinst field, decoded 'end' flag signal condition_reg :std_logic; -- registered tjst condition -- condition: tjsr condition (computed ccc condition from '80 instructions) signal condition : std_logic; -- condition_sel: IR field, ccc condition code signal condition_sel :std_logic_vector(2 downto 0); signal uc_do_jmp : std_logic; -- uinst jump (jsr/tjsr) flag, pipelined signal uc_do_ret : std_logic; -- ret flag, pipelined signal uc_halt_flag : std_logic; -- uinst field, decoded 'halt' flag signal uc_halt : std_logic; -- halt command signal halt_reg : std_logic; -- halt status reg, output as 'halt' signal signal uc_ei : std_logic; -- uinst field, decoded 'ei' flag signal uc_di : std_logic; -- uinst field, decoded 'ei' flag signal inte_reg : std_logic; -- inte status reg, output as 'inte' signal signal int_pending : std_logic; -- intr requested, inta not active yet signal inta_reg : std_logic; -- inta status reg, output as 'inta' signal clr_t1 : std_logic; -- uinst field, explicitly erase T1 signal do_clr_t1 : std_logic; -- clr_t1 pipelined signal clr_t2 : std_logic; -- uinst field, explicitly erase T2 signal do_clr_t2 : std_logic; -- clr_t2 pipelined signal ucode : std_logic_vector(31 downto 0); -- microcode word signal ucode_field2 : std_logic_vector(24 downto 0); -- pipelined microcode -- microcode ROM : see design notes and microcode source file type t_rom is array (0 to 511) of std_logic_vector(31 downto 0); signal rom : t_rom := ( "00000000000000000000000000000000", -- 000 "00000000000001001000000001000100", -- 001 "00000000000001000000000001000100", -- 002 "10111101101001001000000001001101", -- 003 "10110110101001000000000001001101", -- 004 "00100000000000000000000000000000", -- 005 "00000000000000000000000000000000", -- 006 "11100100000000000000000000000000", -- 007 "00000000101010000000000000000000", -- 008 "00000100000100000000000001010111", -- 009 "00001000000000000000110000011001", -- 00a "00000100000100000000000001010111", -- 00b "00000000101010000000000010010111", -- 00c "00001000000000000000110000011100", -- 00d "00001000000000000000110000011111", -- 00e "00000100000100000000000001010111", -- 00f "00001000000000000000110000011111", -- 010 "00001000000000000000110000011100", -- 011 "00001000000000000000110000011111", -- 012 "00000000000110001000000001010111", -- 013 "00001000000000000000110000011111", -- 014 "00000100000110000000000001010111", -- 015 "00001000000000000000110000101110", -- 016 "00001000000000000000110000100010", -- 017 "00000100000000111000000001010111", -- 018 "00001000000000000000110000101110", -- 019 "00000000101000111000000010010111", -- 01a "00001000000000000000110000100101", -- 01b "00001000000000000000110000101110", -- 01c "10111101101001100000000001001101", -- 01d "10110110101001101000000001001101", -- 01e "00000000100000101000000001010111", -- 01f "00001000000000000000110000100010", -- 020 "00000100000000100000000001010111", -- 021 "00001000000000000000110000101110", -- 022 "00000000101000101000000010010111", -- 023 "10111101101001100000000001001101", -- 024 "10111010101001101000000001001101", -- 025 "00000000101000100000000010010111", -- 026 "00001000000000000000110000100101", -- 027 "00001000000000000000110000101000", -- 028 "00000100000000111000000001010111", -- 029 "00000000101000111000000010010111", -- 02a "00001000000000000000110000101011", -- 02b "00000000101000010000000000000000", -- 02c "00000000000001010000000001010111", -- 02d "00000000101000011000000000000000", -- 02e "00000000000001011000000001010111", -- 02f "00000000101000100000000000000000", -- 030 "00000000000000010000000001010111", -- 031 "00000000101000101000000000000000", -- 032 "00000000000000011000000001010111", -- 033 "00000000101001010000000000000000", -- 034 "00000000000000100000000001010111", -- 035 "00000000101001011000000000000000", -- 036 "00000100000000101000000001010111", -- 037 "00001000000000000000110000011111", -- 038 "00000100011000111000001101001100", -- 039 "00001000000000000000110000011111", -- 03a "00000100011000111000001101001101", -- 03b "00001000000000000000110000011111", -- 03c "00000100011000111000001101001110", -- 03d "00001000000000000000110000011111", -- 03e "00000100011000111000001101001111", -- 03f "00001000000000000000110000011111", -- 040 "00000100011000111000001101000100", -- 041 "00001000000000000000110000011111", -- 042 "00000100011000111000001101000101", -- 043 "00001000000000000000110000011111", -- 044 "00000100011000111000001101000110", -- 045 "00001000000000000000110000011111", -- 046 "00000100011000111000001110001110", -- 047 "00000000101010000000000000000000", -- 048 "00000100011000111000001101001100", -- 049 "00000000101010000000000000000000", -- 04a "00000100011000111000001101001101", -- 04b "00000000101010000000000000000000", -- 04c "00000100011000111000001101001110", -- 04d "00000000101010000000000000000000", -- 04e "00000100011000111000001101001111", -- 04f "00000000101010000000000000000000", -- 050 "00000100011000111000001101000100", -- 051 "00000000101010000000000000000000", -- 052 "00000100011000111000001101000101", -- 053 "00000000101010000000000000000000", -- 054 "00000100011000111000001101000110", -- 055 "00000000101010000000000000000000", -- 056 "00000100011000111000001110001110", -- 057 "00001000000000000000110000011001", -- 058 "00000100011000111000001101001100", -- 059 "00001000000000000000110000011001", -- 05a "00000100011000111000001101001101", -- 05b "00001000000000000000110000011001", -- 05c "00000100011000111000001101001110", -- 05d "00001000000000000000110000011001", -- 05e "00000100011000111000001101001111", -- 05f "00001000000000000000110000011001", -- 060 "00000100011000111000001101000100", -- 061 "00001000000000000000110000011001", -- 062 "00000100011000111000001101000101", -- 063 "00001000000000000000110000011001", -- 064 "00000100011000111000001101000110", -- 065 "00001000000000000000110000011001", -- 066 "00000100011000111000001110001110", -- 067 "10111100101100000000001001001101", -- 068 "00000100000000000000000000000000", -- 069 "00001000000000000000110000011001", -- 06a "10111100000000000000001010001101", -- 06b "00001000000000000000110000011100", -- 06c "10111100011100000000001001001111", -- 06d "00000100000000000000000000000000", -- 06e "00001000000000000000110000011001", -- 06f "11000000000000000000000000000000", -- 070 "10111100011001010000001010001111", -- 071 "00001000000000000000110000011100", -- 072 "10111100101110001000000001001101", -- 073 "10100100101110000000000001001101", -- 074 "10111100011110001000000001001111", -- 075 "10100100011110000000000001001111", -- 076 "00000000011110001000000000000000", -- 077 "00000000101000101000000101001100", -- 078 "00000000011110000000000000000000", -- 079 "00000100101000100000000101001101", -- 07a "00000000101000111000000010101000", -- 07b "00000100101000111000001101101000", -- 07c "00000100101000111000000101000000", -- 07d "00000100101000111000000101000001", -- 07e "00000100101000111000000101000010", -- 07f "00000100101000111000000101000011", -- 080 "00000100101000111000000001000111", -- 081 "00000100000000000000000100101100", -- 082 "00000100000000000000000100101101", -- 083 "00001000000000000000110000101110", -- 084 "00000000101001100000000000000000", -- 085 "00000000000001001000000001010111", -- 086 "00000000101001101000000000000000", -- 087 "00000100000001000000000001010111", -- 088 "00000100000000000000000000000000", -- 089 "00001000000000000000110000101110", -- 08a "00010000000000000000100000000101", -- 08b "00001000000000000000110000101110", -- 08c "11000000101001000000000010010111", -- 08d "00001000000000000000110000110100", -- 08e "11000000101001001000000010010111", -- 08f "00001000000000000000110000110100", -- 090 "00000000101001100000000000000000", -- 091 "00000000000001001000000001010111", -- 092 "00000000101001101000000000000000", -- 093 "00000100000001000000000001010111", -- 094 "00001000000000000000110000101110", -- 095 "00010000000000000000100000001101", -- 096 "00001000000000000000110000111001", -- 097 "00000000000001001000000001010111", -- 098 "00001000000000000000110000111001", -- 099 "00000100000001000000000001010111", -- 09a "00010000000000000000100000010111", -- 09b "11000000101001000000000010010111", -- 09c "00001000000000000000110000110100", -- 09d "11000000101001001000000010010111", -- 09e "00001000000000000000110000110100", -- 09f "11000000000001001000000001011111", -- 0a0 "00000100000001000000000001000100", -- 0a1 "00000000101000101000000000000000", -- 0a2 "00000000000001001000000001010111", -- 0a3 "00000000101000100000000000000000", -- 0a4 "00000100000001000000000001010111", -- 0a5 "11000000101110000000000010010111", -- 0a6 "00001000000000000000110000110100", -- 0a7 "11000000101110001000000010010111", -- 0a8 "00001000000000000000110000110100", -- 0a9 "00000100000000000000000000000000", -- 0aa "11000000101000111000000010010111", -- 0ab "00001000000000000000110000110100", -- 0ac "11000000000000000000000010110000", -- 0ad "00001000000000000000110000110100", -- 0ae "00000100000000000000000000000000", -- 0af "00001000000000000000110000111001", -- 0b0 "00000000000110001000000001010111", -- 0b1 "00001000000000000000110000111001", -- 0b2 "00000100000110000000000001010111", -- 0b3 "00001000000000000000110000111001", -- 0b4 "00000000000000110000001101010111", -- 0b5 "00001000000000000000110000111001", -- 0b6 "00000100000000111000000001010111", -- 0b7 "00001000000000000000110000111001", -- 0b8 "00000000000001100000000001010111", -- 0b9 "00001000000000000000110000111001", -- 0ba "00000000000001101000000001010111", -- 0bb "11000000101000100000000010010111", -- 0bc "00001000000000000000110000110100", -- 0bd "11000000101000101000000010010111", -- 0be "00001000000000000000110000110100", -- 0bf "00000000101001100000000000000000", -- 0c0 "00000000000000101000000001010111", -- 0c1 "00000000101001101000000000000000", -- 0c2 "00000100000000100000000001010111", -- 0c3 "00000000101000101000000000000000", -- 0c4 "00000000000001111000000001010111", -- 0c5 "00000000101000100000000000000000", -- 0c6 "00000100000001110000000001010111", -- 0c7 "01100100000000000000000000000000", -- 0c8 "01000100000000000000000000000000", -- 0c9 "00000000000001101000000001010111", -- 0ca "00001000000000000000110000011111", -- 0cb "00000000000001100000000001010111", -- 0cc "00000000000000000000000000000000", -- 0cd "00000001101001100000000000000000", -- 0ce "10010110101001101000000000000000", -- 0cf "00000100100000111000000001010111", -- 0d0 "00000000000001101000000001010111", -- 0d1 "00001000000000000000110000011111", -- 0d2 "00000000000001100000000001010111", -- 0d3 "00000000101000111000000010010111", -- 0d4 "00000001101001100000000000000000", -- 0d5 "10011010101001101000000000000000", -- 0d6 "00000100000000000000000000000000", -- 0d7 "11100100000000000000000000000000", -- 0d8 "00000001101000101000000000000000", -- 0d9 "00010110101000100000000000000000", -- 0da "00001100100001010000000001010111", -- 0db "00000001101000101000000000000000", -- 0dc "00011010101000100000000000000000", -- 0dd "00000100000000000000000000000000", -- 0de "10111101101001001000000001001101", -- 0df "10110110101001000000000001001101", -- 0e0 "00001100100000000000000010010111", -- 0e1 "00000001101001100000000000000000", -- 0e2 "00010110101001101000000000000000", -- 0e3 "00001100100000000000000000000000", -- 0e4 "00000001101001100000000000000000", -- 0e5 "00011010101001101000000000000000", -- 0e6 "00000100000000000000000000000000", -- 0e7 "00000001101110001000000000000000", -- 0e8 "00010110101110000000000000000000", -- 0e9 "00001100100000000000000000000000", -- 0ea "00000001101110001000000000000000", -- 0eb "00011010101110000000000000000000", -- 0ec "00000100000000000000000000000000", -- 0ed "10111101101001001000000001001101", -- 0ee "10110110101001000000000001001101", -- 0ef "00000000100001100000000001010111", -- 0f0 "10111101101001001000000001001101", -- 0f1 "10110110101001000000000001001101", -- 0f2 "00001100100001101000000001010111", -- 0f3 "10111100011001111000000001001111", -- 0f4 "10100000011001110000000001001111", -- 0f5 "00000001101001111000000000000000", -- 0f6 "00011010101001110000000000000000", -- 0f7 "00001100000000000000000000000000", -- 0f8 "10111101101001111000000001001101", -- 0f9 "10110110101001110000000001001101", -- 0fa "00001100100000000000000000000000", -- 0fb "00000100000000000000000000000000", -- 0fc "00000100000000000000000000000000", -- 0fd "00000100000000000000000000000000", -- 0fe "00000100000000000000000000000000", -- 0ff "00001000000000000000100000001001", -- 100 "00001000000000000000000000010010", -- 101 "00001000000000000000000000101010", -- 102 "00001000000000000000010000110011", -- 103 "00001000000000000000010000101000", -- 104 "00001000000000000000010000101101", -- 105 "00001000000000000000000000001110", -- 106 "00001000000000000000010000111101", -- 107 "00001000000000000000000000000000", -- 108 "00001000000000000000010000110111", -- 109 "00001000000000000000000000101000", -- 10a "00001000000000000000010000110101", -- 10b "00001000000000000000010000101000", -- 10c "00001000000000000000010000101101", -- 10d "00001000000000000000000000001110", -- 10e "00001000000000000000010000111110", -- 10f "00001000000000000000000000000000", -- 110 "00001000000000000000000000010010", -- 111 "00001000000000000000000000101010", -- 112 "00001000000000000000010000110011", -- 113 "00001000000000000000010000101000", -- 114 "00001000000000000000010000101101", -- 115 "00001000000000000000000000001110", -- 116 "00001000000000000000010000111111", -- 117 "00001000000000000000000000000000", -- 118 "00001000000000000000010000110111", -- 119 "00001000000000000000000000101000", -- 11a "00001000000000000000010000110101", -- 11b "00001000000000000000010000101000", -- 11c "00001000000000000000010000101101", -- 11d "00001000000000000000000000001110", -- 11e "00001000000000000000100000000000", -- 11f "00001000000000000000000000000000", -- 120 "00001000000000000000000000010010", -- 121 "00001000000000000000000000100010", -- 122 "00001000000000000000010000110011", -- 123 "00001000000000000000010000101000", -- 124 "00001000000000000000010000101101", -- 125 "00001000000000000000000000001110", -- 126 "00001000000000000000010000111011", -- 127 "00001000000000000000000000000000", -- 128 "00001000000000000000010000110111", -- 129 "00001000000000000000000000011100", -- 12a "00001000000000000000010000110101", -- 12b "00001000000000000000010000101000", -- 12c "00001000000000000000010000101101", -- 12d "00001000000000000000000000001110", -- 12e "00001000000000000000100000000001", -- 12f "00001000000000000000000000000000", -- 130 "00001000000000000000000000010010", -- 131 "00001000000000000000000000011001", -- 132 "00001000000000000000010000110011", -- 133 "00001000000000000000010000101010", -- 134 "00001000000000000000010000101111", -- 135 "00001000000000000000000000010000", -- 136 "00001000000000000000100000000011", -- 137 "00001000000000000000000000000000", -- 138 "00001000000000000000010000110111", -- 139 "00001000000000000000000000010110", -- 13a "00001000000000000000010000110101", -- 13b "00001000000000000000010000101000", -- 13c "00001000000000000000010000101101", -- 13d "00001000000000000000000000001110", -- 13e "00001000000000000000100000000010", -- 13f "00001000000000000000000000001000", -- 140 "00001000000000000000000000001000", -- 141 "00001000000000000000000000001000", -- 142 "00001000000000000000000000001000", -- 143 "00001000000000000000000000001000", -- 144 "00001000000000000000000000001000", -- 145 "00001000000000000000000000001010", -- 146 "00001000000000000000000000001000", -- 147 "00001000000000000000000000001000", -- 148 "00001000000000000000000000001000", -- 149 "00001000000000000000000000001000", -- 14a "00001000000000000000000000001000", -- 14b "00001000000000000000000000001000", -- 14c "00001000000000000000000000001000", -- 14d "00001000000000000000000000001010", -- 14e "00001000000000000000000000001000", -- 14f "00001000000000000000000000001000", -- 150 "00001000000000000000000000001000", -- 151 "00001000000000000000000000001000", -- 152 "00001000000000000000000000001000", -- 153 "00001000000000000000000000001000", -- 154 "00001000000000000000000000001000", -- 155 "00001000000000000000000000001010", -- 156 "00001000000000000000000000001000", -- 157 "00001000000000000000000000001000", -- 158 "00001000000000000000000000001000", -- 159 "00001000000000000000000000001000", -- 15a "00001000000000000000000000001000", -- 15b "00001000000000000000000000001000", -- 15c "00001000000000000000000000001000", -- 15d "00001000000000000000000000001010", -- 15e "00001000000000000000000000001000", -- 15f "00001000000000000000000000001000", -- 160 "00001000000000000000000000001000", -- 161 "00001000000000000000000000001000", -- 162 "00001000000000000000000000001000", -- 163 "00001000000000000000000000001000", -- 164 "00001000000000000000000000001000", -- 165 "00001000000000000000000000001010", -- 166 "00001000000000000000000000001000", -- 167 "00001000000000000000000000001000", -- 168 "00001000000000000000000000001000", -- 169 "00001000000000000000000000001000", -- 16a "00001000000000000000000000001000", -- 16b "00001000000000000000000000001000", -- 16c "00001000000000000000000000001000", -- 16d "00001000000000000000000000001010", -- 16e "00001000000000000000000000001000", -- 16f "00001000000000000000000000001100", -- 170 "00001000000000000000000000001100", -- 171 "00001000000000000000000000001100", -- 172 "00001000000000000000000000001100", -- 173 "00001000000000000000000000001100", -- 174 "00001000000000000000000000001100", -- 175 "00001000000000000000110000011000", -- 176 "00001000000000000000000000001100", -- 177 "00001000000000000000000000001000", -- 178 "00001000000000000000000000001000", -- 179 "00001000000000000000000000001000", -- 17a "00001000000000000000000000001000", -- 17b "00001000000000000000000000001000", -- 17c "00001000000000000000000000001000", -- 17d "00001000000000000000000000001010", -- 17e "00001000000000000000000000001000", -- 17f "00001000000000000000010000001000", -- 180 "00001000000000000000010000001000", -- 181 "00001000000000000000010000001000", -- 182 "00001000000000000000010000001000", -- 183 "00001000000000000000010000001000", -- 184 "00001000000000000000010000001000", -- 185 "00001000000000000000010000011000", -- 186 "00001000000000000000010000001000", -- 187 "00001000000000000000010000001010", -- 188 "00001000000000000000010000001010", -- 189 "00001000000000000000010000001010", -- 18a "00001000000000000000010000001010", -- 18b "00001000000000000000010000001010", -- 18c "00001000000000000000010000001010", -- 18d "00001000000000000000010000011010", -- 18e "00001000000000000000010000001010", -- 18f "00001000000000000000010000001100", -- 190 "00001000000000000000010000001100", -- 191 "00001000000000000000010000001100", -- 192 "00001000000000000000010000001100", -- 193 "00001000000000000000010000001100", -- 194 "00001000000000000000010000001100", -- 195 "00001000000000000000010000011100", -- 196 "00001000000000000000010000001100", -- 197 "00001000000000000000010000001110", -- 198 "00001000000000000000010000001110", -- 199 "00001000000000000000010000001110", -- 19a "00001000000000000000010000001110", -- 19b "00001000000000000000010000001110", -- 19c "00001000000000000000010000001110", -- 19d "00001000000000000000010000011110", -- 19e "00001000000000000000010000001110", -- 19f "00001000000000000000010000010000", -- 1a0 "00001000000000000000010000010000", -- 1a1 "00001000000000000000010000010000", -- 1a2 "00001000000000000000010000010000", -- 1a3 "00001000000000000000010000010000", -- 1a4 "00001000000000000000010000010000", -- 1a5 "00001000000000000000010000100000", -- 1a6 "00001000000000000000010000010000", -- 1a7 "00001000000000000000010000010010", -- 1a8 "00001000000000000000010000010010", -- 1a9 "00001000000000000000010000010010", -- 1aa "00001000000000000000010000010010", -- 1ab "00001000000000000000010000010010", -- 1ac "00001000000000000000010000010010", -- 1ad "00001000000000000000010000100010", -- 1ae "00001000000000000000010000010010", -- 1af "00001000000000000000010000010100", -- 1b0 "00001000000000000000010000010100", -- 1b1 "00001000000000000000010000010100", -- 1b2 "00001000000000000000010000010100", -- 1b3 "00001000000000000000010000010100", -- 1b4 "00001000000000000000010000010100", -- 1b5 "00001000000000000000010000100100", -- 1b6 "00001000000000000000010000010100", -- 1b7 "00001000000000000000010000010110", -- 1b8 "00001000000000000000010000010110", -- 1b9 "00001000000000000000010000010110", -- 1ba "00001000000000000000010000010110", -- 1bb "00001000000000000000010000010110", -- 1bc "00001000000000000000010000010110", -- 1bd "00001000000000000000010000100110", -- 1be "00001000000000000000010000010110", -- 1bf "00001000000000000000100000011011", -- 1c0 "00001000000000000000100000110000", -- 1c1 "00001000000000000000100000001010", -- 1c2 "00001000000000000000100000000100", -- 1c3 "00001000000000000000100000010101", -- 1c4 "00001000000000000000100000100110", -- 1c5 "00001000000000000000000000111000", -- 1c6 "00001000000000000000100000011100", -- 1c7 "00001000000000000000100000011011", -- 1c8 "00001000000000000000100000010111", -- 1c9 "00001000000000000000100000001010", -- 1ca "00001000000000000000000000000000", -- 1cb "00001000000000000000100000010101", -- 1cc "00001000000000000000100000001100", -- 1cd "00001000000000000000000000111010", -- 1ce "00001000000000000000100000011100", -- 1cf "00001000000000000000100000011011", -- 1d0 "00001000000000000000100000110000", -- 1d1 "00001000000000000000100000001010", -- 1d2 "00001000000000000000110000010001", -- 1d3 "00001000000000000000100000010101", -- 1d4 "00001000000000000000100000100110", -- 1d5 "00001000000000000000000000111100", -- 1d6 "00001000000000000000100000011100", -- 1d7 "00001000000000000000100000011011", -- 1d8 "00001000000000000000000000000000", -- 1d9 "00001000000000000000100000001010", -- 1da "00001000000000000000110000001010", -- 1db "00001000000000000000100000010101", -- 1dc "00001000000000000000000000000000", -- 1dd "00001000000000000000000000111110", -- 1de "00001000000000000000100000011100", -- 1df "00001000000000000000100000011011", -- 1e0 "00001000000000000000100000110000", -- 1e1 "00001000000000000000100000001010", -- 1e2 "00001000000000000000100000111000", -- 1e3 "00001000000000000000100000010101", -- 1e4 "00001000000000000000100000100110", -- 1e5 "00001000000000000000010000000000", -- 1e6 "00001000000000000000100000011100", -- 1e7 "00001000000000000000100000011011", -- 1e8 "00001000000000000000100000100010", -- 1e9 "00001000000000000000100000001010", -- 1ea "00001000000000000000000000101100", -- 1eb "00001000000000000000100000010101", -- 1ec "00001000000000000000000000000000", -- 1ed "00001000000000000000010000000010", -- 1ee "00001000000000000000100000011100", -- 1ef "00001000000000000000100000011011", -- 1f0 "00001000000000000000100000110100", -- 1f1 "00001000000000000000100000001010", -- 1f2 "00001000000000000000110000001001", -- 1f3 "00001000000000000000100000010101", -- 1f4 "00001000000000000000100000101011", -- 1f5 "00001000000000000000010000000100", -- 1f6 "00001000000000000000100000011100", -- 1f7 "00001000000000000000100000011011", -- 1f8 "00001000000000000000110000000100", -- 1f9 "00001000000000000000100000001010", -- 1fa "00001000000000000000110000001000", -- 1fb "00001000000000000000100000010101", -- 1fc "00001000000000000000000000000000", -- 1fd "00001000000000000000010000000110", -- 1fe "00001000000000000000100000011100" -- 1ff ); -- end of microcode ROM signal load_al : std_logic; -- uinst field, load AL reg from rbank signal load_addr : std_logic; -- uinst field, enable external addr reg load signal load_t1 : std_logic; -- uinst field, load reg T1 signal load_t2 : std_logic; -- uinst field, load reg T2 signal mux_in : std_logic; -- uinst field, T1/T2 input data selection signal load_do : std_logic; -- uinst field, pipelined, load DO reg -- rb_addr_sel: uinst field, rbank address selection: (sss,ddd,pp,ra_field) signal rb_addr_sel : std_logic_vector(1 downto 0); -- ra_field: uinst field, explicit reg bank address signal ra_field : std_logic_vector(3 downto 0); signal rbank_data : std_logic_vector(7 downto 0); -- rbank output signal alu_output : std_logic_vector(7 downto 0); -- ALU output -- data_output: datapath output: ALU output vs. F reg signal data_output : std_logic_vector(7 downto 0); signal T1 : std_logic_vector(7 downto 0); -- T1 reg (ALU operand) signal T2 : std_logic_vector(7 downto 0); -- T2 reg (ALU operand) -- alu_input: data loaded into T1, T2: rbank data vs. DI signal alu_input : std_logic_vector(7 downto 0); signal we_rb : std_logic; -- uinst field, commands a write to the rbank signal inhibit_pc_increment : std_logic; -- avoid PC changes (during INTA) signal rbank_rd_addr: std_logic_vector(3 downto 0); -- rbank rd addr signal rbank_wr_addr: std_logic_vector(3 downto 0); -- rbank wr addr signal DO : std_logic_vector(7 downto 0); -- data output reg -- Register bank as an array of 16 bytes (asynch. LUT ram) type t_reg_bank is array(0 to 15) of std_logic_vector(7 downto 0); -- Register bank : BC, DE, HL, AF, [PC, XY, ZW, SP] signal rbank : t_reg_bank; signal flag_reg : std_logic_vector(7 downto 0); -- F register -- flag_pattern: uinst field, F update pattern: which flags are updated signal flag_pattern : std_logic_vector(1 downto 0); signal flag_s : std_logic; -- new computed S flag signal flag_z : std_logic; -- new computed Z flag signal flag_p : std_logic; -- new computed P flag signal flag_cy : std_logic; -- new computed C flag signal flag_cy_1 : std_logic; -- C flag computed from arith/logic operation signal flag_cy_2 : std_logic; -- C flag computed from CPC circuit signal do_cy_op : std_logic; -- ALU explicit CY operation (CPC, etc.) signal do_cy_op_d : std_logic; -- do_cy_op, pipelined signal do_cpc : std_logic; -- ALU operation is CPC signal do_cpc_d : std_logic; -- do_cpc, pipelined signal do_daa : std_logic; -- ALU operation is DAA signal flag_ac : std_logic; -- new computed half carry flag -- flag_aux_cy: new computed half carry flag (used in 16-bit ops) signal flag_aux_cy : std_logic; signal load_psw : std_logic; -- load F register -- aux carry computation and control signals signal use_aux : std_logic; -- decoded from flags in 1st phase signal use_aux_cy : std_logic; -- 2nd phase signal signal reg_aux_cy : std_logic; signal aux_cy_in : std_logic; signal set_aux_cy : std_logic; signal set_aux : std_logic; -- ALU control signals -- together they select ALU operation signal alu_fn : std_logic_vector(1 downto 0); signal use_logic : std_logic; -- logic/arith mux control signal mux_fn : std_logic_vector(1 downto 0); signal use_psw : std_logic; -- ALU/F mux control -- ALU arithmetic operands and result signal arith_op1 : std_logic_vector(8 downto 0); signal arith_op2 : std_logic_vector(8 downto 0); signal arith_op2_sgn: std_logic_vector(8 downto 0); signal arith_res : std_logic_vector(8 downto 0); signal arith_res8 : std_logic_vector(7 downto 0); -- ALU DAA intermediate signals (DAA has fully dedicated logic) signal daa_res : std_logic_vector(8 downto 0); signal daa_res8 : std_logic_vector(7 downto 0); signal daa_res9 : std_logic_vector(8 downto 0); signal daa_test1 : std_logic; signal daa_test1a : std_logic; signal daa_test2 : std_logic; signal daa_test2a : std_logic; signal arith_daa_res :std_logic_vector(7 downto 0); signal cy_daa : std_logic; -- ALU CY flag intermediate signals signal cy_in_sgn : std_logic; signal cy_in : std_logic; signal cy_in_gated : std_logic; signal cy_adder : std_logic; signal cy_arith : std_logic; signal cy_shifter : std_logic; -- ALU intermediate results signal logic_res : std_logic_vector(7 downto 0); signal shift_res : std_logic_vector(7 downto 0); signal alu_mux1 : std_logic_vector(7 downto 0); begin DI <= data_in; process(clk) -- IR register, load when uc_decode flag activates begin if clk'event and clk='1' then if uc_decode = '1' then IR <= DI; end if; end if; end process; s_field <= IR(2 downto 0); -- IR field extraction : sss reg code d_field <= IR(5 downto 3); -- ddd reg code p_field <= IR(5 downto 4); -- pp 16-bit reg pair code --############################################################################## -- Microcode sequencer process(clk) -- do_reset is reset delayed 1 cycle begin if clk'event and clk='1' then do_reset <= reset; end if; end process; uc_flags1 <= ucode(31 downto 29); uc_flags2 <= ucode(28 downto 26); -- microcode address control flags are gated by do_reset (reset has priority) uc_do_ret <= '1' when uc_flags2 = "011" and do_reset = '0' else '0'; uc_jsr <= '1' when uc_flags2 = "010" and do_reset = '0' else '0'; uc_tjsr <= '1' when uc_flags2 = "100" and do_reset = '0' else '0'; uc_decode <= '1' when uc_flags1 = "001" and do_reset = '0' else '0'; uc_end <= '1' when (uc_flags2 = "001" or (uc_tjsr='1' and condition_reg='0')) and do_reset = '0' else '0'; -- other microinstruction flags are decoded uc_halt_flag <= '1' when uc_flags1 = "111" else '0'; uc_halt <= '1' when uc_halt_flag='1' and inta_reg='0' else '0'; uc_ei <= '1' when uc_flags1 = "011" else '0'; uc_di <= '1' when uc_flags1 = "010" or inta_reg='1' else '0'; -- clr_t1/2 clears T1/T2 when explicitly commanded; T2 and T1 clear implicitly -- at the end of each instruction (by uc_decode) clr_t2 <= '1' when uc_flags2 = "001" else '0'; clr_t1 <= '1' when uc_flags1 = "110" else '0'; use_aux <= '1' when uc_flags1 = "101" else '0'; set_aux <= '1' when uc_flags2 = "111" else '0'; load_al <= ucode(24); load_addr <= ucode(25); do_cy_op_d <= '1' when ucode(5 downto 2)="1011" else '0'; -- decode CY ALU op do_cpc_d <= ucode(0); -- decode CPC ALU op -- uinst jump command, either unconditional or on a given condition uc_do_jmp <= uc_jsr or (uc_tjsr and condition_reg); vma <= load_addr; -- addr is valid, either for memmory or io -- assume the only uinst that does memory access in the range 0..f is 'fetch' fetch <= '1' when uc_addr(7 downto 4)=X"0" and load_addr='1' else '0'; -- external bus interface control signals io <= '1' when uc_flags1="100" else '0'; -- IO access (vs. memory) rd <= '1' when uc_flags2="101" else '0'; -- RD access wr <= '1' when uc_flags2="110" else '0'; -- WR access uc_jmp_addr <= ucode(11 downto 10) & ucode(5 downto 0); uc_addr_sel <= uc_do_ret & uc_do_jmp & uc_decode & uc_end; addr_plus_1 <= uc_addr + 1; -- TODO simplify this!! -- NOTE: when end='1' we jump either to the FETCH ucode ot to the HALT ucode -- depending on the value of the halt signal. -- We use the unregistered uc_halt instead of halt_reg because otherwise #end -- should be on the cycle following #halt, wasting a cycle. -- This means that the flag #halt has to be used with #end or will be ignored. with uc_addr_sel select next_uc_addr <= '0'&uc_ret_addr when "1000", -- ret '0'&uc_jmp_addr when "0100", -- jsr/tjsr '0'&addr_plus_1 when "0000", -- uaddr++ "000000"&uc_halt&"11" when "0001", -- end: go to fetch/halt uaddr '1'&DI when others; -- decode fetched address -- Note how we used DI (containing instruction opcode) as a microcode address -- read microcode rom process (clk) begin if clk'event and clk='1' then ucode <= rom(conv_integer(next_uc_addr)); end if; end process; -- microcode address register process (clk) begin if clk'event and clk='1' then if reset = '1' then uc_addr <= X"00"; else uc_addr <= next_uc_addr(7 downto 0); end if; end if; end process; -- ucode address 1-level 'return stack' process (clk) begin if clk'event and clk='1' then if reset = '1' then uc_ret_addr <= X"00"; elsif uc_do_jmp='1' then uc_ret_addr <= addr_plus_1; end if; end if; end process; alu_op <= ucode(3 downto 0); -- pipeline uinst field2 for 1-cycle delayed execution. -- note the same rbank addr field is used in cycles 1 and 2; this enforces -- some constraints on uinst programming but simplifies the system. process(clk) begin if clk'event and clk='1' then ucode_field2 <= do_cy_op_d & do_cpc_d & clr_t2 & clr_t1 & set_aux & use_aux & rbank_rd_addr & ucode(14 downto 4) & alu_op; end if; end process; --#### HALT logic process(clk) begin if clk'event and clk='1' then if reset = '1' or int_pending = '1' then --inta_reg halt_reg <= '0'; else if uc_halt = '1' then halt_reg <= '1'; end if; end if; end if; end process; halt <= halt_reg; --#### INTE logic -- inte_reg = '1' means interrupts ENABLED process(clk) begin if clk'event and clk='1' then if reset = '1' then inte_reg <= '0'; else if uc_di='1' or uc_ei='1' then inte_reg <= uc_ei; end if; end if; end if; end process; inte <= inte_reg; -- interrupts are ignored when inte='0' process(clk) begin if clk'event and clk='1' then if reset = '1' then int_pending <= '0'; else if intr = '1' and inte_reg = '1' and int_pending = '0' then int_pending <= '1'; else if inte_reg = '1' and uc_end='1' then int_pending <= '0'; end if; end if; end if; end if; end process; --#### INTA logic -- INTA goes high from END to END, that is for the entire time the instruction -- takes to fetch and execute; in the original 8080 it was asserted only for -- the M1 cycle. -- All instructions can be used in an inta cycle, including XTHL which was -- forbidden in the original 8080. -- It's up to you figuring out which cycle is which in multibyte instructions. process(clk) begin if clk'event and clk='1' then if reset = '1' then inta_reg <= '0'; else if int_pending = '1' and uc_end='1' then -- enter INTA state inta_reg <= '1'; else -- exit INTA state -- NOTE: don't reset inta when exiting halt state (uc_halt_flag='1'). -- If we omit this condition, when intr happens on halt state, inta -- will only last for 1 cycle, because in halt state uc_end is -- always asserted. if uc_end = '1' and uc_halt_flag='0' then inta_reg <= '0'; end if; end if; end if; end if; end process; inta <= inta_reg; --############################################################################## -- Datapath -- extract pipelined microcode fields ra_field <= ucode(18 downto 15); load_t1 <= ucode(23); load_t2 <= ucode(22); mux_in <= ucode(21); rb_addr_sel <= ucode(20 downto 19); load_do <= ucode_field2(7); set_aux_cy <= ucode_field2(20); do_clr_t1 <= ucode_field2(21); do_clr_t2 <= ucode_field2(22); -- T1 register process (clk) begin if clk'event and clk='1' then if reset = '1' or uc_decode = '1' or do_clr_t1='1' then T1 <= X"00"; else if load_t1 = '1' then T1 <= alu_input; end if; end if; end if; end process; -- T2 register process (clk) begin if clk'event and clk='1' then if reset = '1' or uc_decode = '1' or do_clr_t2='1' then T2 <= X"00"; else if load_t2 = '1' then T2 <= alu_input; end if; end if; end if; end process; -- T1/T2 input data mux alu_input <= rbank_data when mux_in = '1' else DI; -- register bank address mux logic rbh <= '1' when p_field = "11" else '0'; with rb_addr_sel select rbank_rd_addr <= ra_field when "00", "0"&s_field when "01", "0"&d_field when "10", rbh&p_field&ra_field(0) when others; -- RBank writes are inhibited in INTA state, but only for PC increments. inhibit_pc_increment <= '1' when inta_reg='1' and use_aux_cy='1' and rbank_wr_addr(3 downto 1) = "100" else '0'; we_rb <= ucode_field2(6) and not inhibit_pc_increment; -- Register bank logic -- NOTE: read is asynchronous, while write is synchronous; but note also -- that write phase for a given uinst happens the cycle after the read phase. -- This way we give the ALU time to do its job. rbank_wr_addr <= ucode_field2(18 downto 15); process(clk) begin if clk'event and clk='1' then if we_rb = '1' then rbank(conv_integer(rbank_wr_addr)) <= alu_output; end if; end if; end process; rbank_data <= rbank(conv_integer(rbank_rd_addr)); -- should we read F register or ALU output? use_psw <= '1' when ucode_field2(5 downto 4)="11" else '0'; data_output <= flag_reg when use_psw = '1' else alu_output; process (clk) begin if clk'event and clk='1' then if load_do = '1' then DO <= data_output; end if; end if; end process; --############################################################################## -- ALU alu_fn <= ucode_field2(1 downto 0); use_logic <= ucode_field2(2); mux_fn <= ucode_field2(4 downto 3); --#### make sure this is "00" in the microcode when no F updates should happen! flag_pattern <= ucode_field2(9 downto 8); use_aux_cy <= ucode_field2(19); do_cpc <= ucode_field2(23); do_cy_op <= ucode_field2(24); do_daa <= '1' when ucode_field2(5 downto 2) = "1010" else '0'; aux_cy_in <= reg_aux_cy when set_aux_cy = '0' else '1'; -- carry input selection: normal or aux (for 16 bit increments)? cy_in <= flag_reg(0) when use_aux_cy = '0' else aux_cy_in; -- carry is not used (0) in add/sub operations cy_in_gated <= cy_in and alu_fn(0); --##### Adder/substractor -- zero extend adder operands to 9 bits to ease CY output synthesis -- use zero extension because we're only interested in cy from 7 to 8 arith_op1 <= '0' & T2; arith_op2 <= '0' & T1; -- The adder/substractor is done in 2 stages to help XSL synth it properly -- Other codings result in 1 adder + a substractor + 1 mux -- do 2nd op 2's complement if substracting... arith_op2_sgn <= arith_op2 when alu_fn(1) = '0' else not arith_op2; -- ...and complement cy input too cy_in_sgn <= cy_in_gated when alu_fn(1) = '0' else not cy_in_gated; -- once 2nd operand has been negated (or not) add operands normally arith_res <= arith_op1 + arith_op2_sgn + cy_in_sgn; -- take only 8 bits; 9th bit of adder is cy output arith_res8 <= arith_res(7 downto 0); cy_adder <= arith_res(8); --##### DAA dedicated logic -- Note a DAA takes 2 cycles to complete! --daa_test1a='1' when daa_res9(7 downto 4) > 0x06 daa_test1a <= arith_op2(3) and (arith_op2(2) or arith_op2(1) or arith_op2(0)); daa_test1 <= '1' when flag_reg(4)='1' or daa_test1a='1' else '0'; process(clk) begin if clk'event and clk='1' then if reset='1' then daa_res9 <= "000000000"; else if daa_test1='1' then daa_res9 <= arith_op2 + "000000110"; else daa_res9 <= arith_op2; end if; end if; end if; end process; --daa_test2a='1' when daa_res9(7 downto 4) > 0x06 FIXME unused? daa_test2a <= daa_res9(7) and (daa_res9(6) or daa_res9(5) or daa_res9(4)); daa_test2 <= '1' when flag_reg(0)='1' or daa_test1a='1' else '0'; daa_res <= '0'&daa_res9(7 downto 0) + "01100000" when daa_test2='1' else daa_res9; cy_daa <= daa_res(8); -- DAA vs. adder mux arith_daa_res <= daa_res(7 downto 0) when do_daa='1' else arith_res8; -- DAA vs. adder CY mux cy_arith <= cy_daa when do_daa='1' else cy_adder; --##### Logic operations block logic_res <= T1 and T2 when alu_fn = "00" else T1 xor T2 when alu_fn = "01" else T1 or T2 when alu_fn = "10" else not T1; --##### Shifter shifter: for i in 1 to 6 generate begin shift_res(i) <= T1(i-1) when alu_fn(0) = '0' else T1(i+1); end generate; shift_res(0) <= T1(7) when alu_fn = "00" else -- rot left cy_in when alu_fn = "10" else -- rot left through carry T1(1); -- rot right shift_res(7) <= T1(0) when alu_fn = "01" else -- rot right cy_in when alu_fn = "11" else -- rot right through carry T1(6); -- rot left cy_shifter <= T1(7) when alu_fn(0) = '0' else -- left T1(0); -- right alu_mux1 <= logic_res when use_logic = '1' else shift_res; with mux_fn select alu_output <= alu_mux1 when "00", arith_daa_res when "01", not alu_mux1 when "10", "00"&d_field&"000" when others; -- RST --###### flag computation flag_s <= alu_output(7); flag_p <= not(alu_output(7) xor alu_output(6) xor alu_output(5) xor alu_output(4) xor alu_output(3) xor alu_output(2) xor alu_output(1) xor alu_output(0)); flag_z <= '1' when alu_output=X"00" else '0'; flag_ac <= (arith_op1(4) xor arith_op2_sgn(4) xor alu_output(4)); flag_cy_1 <= cy_arith when use_logic = '1' else cy_shifter; flag_cy_2 <= not flag_reg(0) when do_cpc='0' else '1'; -- cmc, stc flag_cy <= flag_cy_1 when do_cy_op='0' else flag_cy_2; flag_aux_cy <= cy_adder; -- auxiliary carry reg process(clk) begin if clk'event and clk='1' then if reset='1' or uc_decode = '1' then reg_aux_cy <= '1'; -- inits to 0 every instruction else reg_aux_cy <= flag_aux_cy; end if; end if; end process; -- load PSW from ALU (i.e. POP AF) or from flag signals load_psw <= '1' when we_rb='1' and rbank_wr_addr="0110" else '0'; -- The F register has been split in two separate groupt that always update -- together (C and all others). -- F register, flags S,Z,AC,P process(clk) begin if clk'event and clk='1' then if reset='1' then flag_reg(7) <= '0'; flag_reg(6) <= '0'; flag_reg(4) <= '0'; flag_reg(2) <= '0'; elsif flag_pattern(1) = '1' then if load_psw = '1' then flag_reg(7) <= alu_output(7); flag_reg(6) <= alu_output(6); flag_reg(4) <= alu_output(4); flag_reg(2) <= alu_output(2); else flag_reg(7) <= flag_s; flag_reg(6) <= flag_z; flag_reg(4) <= flag_ac; flag_reg(2) <= flag_p; end if; end if; end if; end procesS; -- F register, flag C process(clk) begin if clk'event and clk='1' then if reset = '1' then flag_reg(0) <= '0'; elsif flag_pattern(0) = '1' then if load_psw = '1' then flag_reg(0) <= alu_output(0); else flag_reg(0) <= flag_cy; end if; end if; end if; end procesS; flag_reg(5) <= '0'; -- constant flag flag_reg(3) <= '0'; -- constant flag flag_reg(1) <= '1'; -- constant flag --##### Condition computation condition_sel <= d_field(2 downto 0); with condition_sel select condition <= not flag_reg(6) when "000", -- NZ flag_reg(6) when "001", -- Z not flag_reg(0) when "010", -- NC flag_reg(0) when "011", -- C not flag_reg(2) when "100", -- PO flag_reg(2) when "101", -- PE not flag_reg(7) when "110", -- P flag_reg(7) when others;-- M -- condition is registered to shorten the delay path; the extra 1-cycle -- delay is not relevant because conditions are tested in the next instruction -- at the earliest, and there's at least the fetch uinsts intervening. process(clk) begin if clk'event and clk='1' then if reset = '1' then condition_reg <= '0'; else condition_reg <= condition; end if; end if; end process; -- low byte address register process(clk) begin if clk'event and clk='1' then if reset = '1' then addr_low <= X"00"; elsif load_al = '1' then addr_low <= rbank_data; end if; end if; end process; -- note external address registers (high byte) are loaded directly from rbank addr_out <= rbank_data & addr_low; data_out <= DO; end microcoded; -------------------------------------------------------------------------------- -- Timing diagram 1: RD and WR cycles -------------------------------------------------------------------------------- -- 1 2 3 4 5 6 7 8 -- __ __ __ __ __ __ __ __ -- clk __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__ -- -- addr_o xxxxxxxxxxxxxx< ADR >xxxxxxxxxxx< ADR >xxxxxxxxxxx -- -- data_i xxxxxxxxxxxxxxxxxxxx< Din >xxxxxxxxxxxxxxxxxxxxxxx -- -- data_o xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx< Dout>xxxxxxxxxxx -- _____ _____ -- vma_o ______________/ \___________/ \___________ -- _____ -- rd_o ______________/ \_____________________________ -- _____ -- wr_o ________________________________/ \___________ -- -- (functional diagram, actual time delays not shown) -------------------------------------------------------------------------------- -- This diagram shows a read cycle and a write cycle back to back. -- In clock edges (4) and (7), the address is loaded into the external -- synchronous RAM address register. -- In clock edge (5), read data is loaded into the CPU. -- In clock edge (7), write data is loaded into the external synchronous RAM. -- In actual operation, the CPU does about 1 rd/wr cycle for each 5 clock -- cycles, which is a waste of RAM bandwidth. --

gpl-3.0

dhmeves/ece-485

ece-485-project-2/sign_extend.vhd

1

3179

library IEEE; use ieee.std_logic_1164.all; entity sign_extend is port( instr15_0 : in std_logic_vector(15 downto 0); clk, rst, pre, ce : in std_logic; output : out std_logic_vector(31 downto 0) ); end sign_extend; architecture behav of sign_extend is signal output_buf, output_buf0 : std_logic; begin DFF1 : entity work.d_flip_flop(behav) port map(clk, instr15_0(0), rst, pre, ce, output(0)); DFF2 : entity work.d_flip_flop(behav) port map(clk, instr15_0(1), rst, pre, ce, output(1)); DFF3 : entity work.d_flip_flop(behav) port map(clk, instr15_0(2), rst, pre, ce, output(2)); DFF4 : entity work.d_flip_flop(behav) port map(clk, instr15_0(3), rst, pre, ce, output(3)); DFF5 : entity work.d_flip_flop(behav) port map(clk, instr15_0(4), rst, pre, ce, output(4)); DFF6 : entity work.d_flip_flop(behav) port map(clk, instr15_0(5), rst, pre, ce, output(5)); DFF7 : entity work.d_flip_flop(behav) port map(clk, instr15_0(6), rst, pre, ce, output(6)); DFF8 : entity work.d_flip_flop(behav) port map(clk, instr15_0(7), rst, pre, ce, output(7)); DFF9 : entity work.d_flip_flop(behav) port map(clk, instr15_0(8), rst, pre, ce, output(8)); DFF10 : entity work.d_flip_flop(behav) port map(clk, instr15_0(9), rst, pre, ce, output(9)); DFF11 : entity work.d_flip_flop(behav) port map(clk, instr15_0(10), rst, pre, ce, output(10)); DFF12 : entity work.d_flip_flop(behav) port map(clk, instr15_0(11), rst, pre, ce, output(11)); DFF13 : entity work.d_flip_flop(behav) port map(clk, instr15_0(12), rst, pre, ce, output(12)); DFF14 : entity work.d_flip_flop(behav) port map(clk, instr15_0(13), rst, pre, ce, output(13)); DFF15 : entity work.d_flip_flop(behav) port map(clk, instr15_0(14), rst, pre, ce, output(14)); DFF16 : entity work.d_flip_flop(behav) port map(clk, instr15_0(15), rst, pre, ce, output(15)); output_buf0 <= instr15_0(15) when rst = '0' else '0' when rst = '1'; output_buf <= output_buf0 when pre = '0' else '1' when pre = '1'; output(16) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(17) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(18) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(19) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(20) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(21) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(22) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(23) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(24) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(25) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(26) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(27) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(28) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(29) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(30) <= '0' when output_buf = '0' else '1' when output_buf = '1'; output(31) <= '0' when output_buf = '0' else '1' when output_buf = '1'; end behav;

gpl-3.0

freecores/gpib_controller

vhdl/test/gpib_DT_Test.vhd

1

13686

-------------------------------------------------------------------------------- --This file is part of fpga_gpib_controller. -- -- Fpga_gpib_controller is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Fpga_gpib_controller is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------------------------------- -- Author: Andrzej Paluch -- -- Create Date: 23:21:05 10/21/2011 -- Design Name: -- Module Name: /windows/h/projekty/elektronika/USB_to_HPIB/usbToHpib/test_scr//gpibInterfaceTest.vhd -- Project Name: usbToHpib -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: gpibInterface -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; use work.gpibComponents.all; use work.helperComponents.all; ENTITY gpib_DT_Test IS END gpib_DT_Test; ARCHITECTURE behavior OF gpib_DT_Test IS -- Component Declaration for the Unit Under Test (UUT) component gpibCableEmulator is port ( -- interface signals DIO_1 : in std_logic_vector (7 downto 0); output_valid_1 : in std_logic; DIO_2 : in std_logic_vector (7 downto 0); output_valid_2 : in std_logic; DIO : out std_logic_vector (7 downto 0); -- attention ATN_1 : in std_logic; ATN_2 : in std_logic; ATN : out std_logic; -- data valid DAV_1 : in std_logic; DAV_2 : in std_logic; DAV : out std_logic; -- not ready for data NRFD_1 : in std_logic; NRFD_2 : in std_logic; NRFD : out std_logic; -- no data accepted NDAC_1 : in std_logic; NDAC_2 : in std_logic; NDAC : out std_logic; -- end or identify EOI_1 : in std_logic; EOI_2 : in std_logic; EOI : out std_logic; -- service request SRQ_1 : in std_logic; SRQ_2 : in std_logic; SRQ : out std_logic; -- interface clear IFC_1 : in std_logic; IFC_2 : in std_logic; IFC : out std_logic; -- remote enable REN_1 : in std_logic; REN_2 : in std_logic; REN : out std_logic ); end component; -- inputs common signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal T1 : std_logic_vector(7 downto 0) := "00000100"; -- inputs 1 signal data_1 : std_logic_vector(7 downto 0) := (others => '0'); signal status_byte_1 : std_logic_vector(7 downto 0) := (others => '0'); signal rdy_1 : std_logic := '0'; signal nba_1 : std_logic := '0'; signal ltn_1 : std_logic := '0'; signal lun_1 : std_logic := '0'; signal lon_1 : std_logic := '0'; signal ton_1 : std_logic := '0'; signal endOf_1 : std_logic := '0'; signal gts_1 : std_logic := '0'; signal rpp_1 : std_logic := '0'; signal tcs_1 : std_logic := '0'; signal tca_1 : std_logic := '0'; signal sic_1 : std_logic := '0'; signal rsc_1 : std_logic := '0'; signal sre_1 : std_logic := '0'; signal rtl_1 : std_logic := '0'; signal rsv_1 : std_logic := '0'; signal ist_1 : std_logic := '0'; signal lpe_1 : std_logic := '0'; -- inputs 2 signal data_2 : std_logic_vector(7 downto 0) := (others => '0'); signal status_byte_2 : std_logic_vector(7 downto 0) := (others => '0'); signal rdy_2 : std_logic := '0'; signal nba_2 : std_logic := '0'; signal ltn_2 : std_logic := '0'; signal lun_2 : std_logic := '0'; signal lon_2 : std_logic := '0'; signal ton_2 : std_logic := '0'; signal endOf_2 : std_logic := '0'; signal gts_2 : std_logic := '0'; signal rpp_2 : std_logic := '0'; signal tcs_2 : std_logic := '0'; signal tca_2 : std_logic := '0'; signal sic_2 : std_logic := '0'; signal rsc_2 : std_logic := '0'; signal sre_2 : std_logic := '0'; signal rtl_2 : std_logic := '0'; signal rsv_2 : std_logic := '0'; signal ist_2 : std_logic := '0'; signal lpe_2 : std_logic := '0'; -- outputs 1 signal dvd_1 : std_logic; signal wnc_1 : std_logic; signal tac_1 : std_logic; signal cwrc_1 : std_logic; signal cwrd_1 : std_logic; signal clr_1 : std_logic; signal trg_1 : std_logic; signal atl_1 : std_logic; signal att_1 : std_logic; signal mla_1 : std_logic; signal lsb_1 : std_logic; signal spa_1 : std_logic; signal ppr_1 : std_logic; signal sreq_1 : std_logic; signal isLocal_1 : std_logic; signal currentSecAddr_1 : std_logic_vector (4 downto 0); -- outputs 2 signal dvd_2 : std_logic; signal wnc_2 : std_logic; signal tac_2 : std_logic; signal cwrc_2 : std_logic; signal cwrd_2 : std_logic; signal clr_2 : std_logic; signal trg_2 : std_logic; signal atl_2 : std_logic; signal att_2 : std_logic; signal mla_2 : std_logic; signal lsb_2 : std_logic; signal spa_2 : std_logic; signal ppr_2 : std_logic; signal sreq_2 : std_logic; signal isLocal_2 : std_logic; signal currentSecAddr_2 : std_logic_vector (4 downto 0); -- common signal DO : std_logic_vector (7 downto 0); signal DI_1 : std_logic_vector (7 downto 0); signal output_valid_1 : std_logic; signal DI_2 : std_logic_vector (7 downto 0); signal output_valid_2 : std_logic; signal ATN_1, ATN_2, ATN : std_logic; signal DAV_1, DAV_2, DAV : std_logic; signal NRFD_1, NRFD_2, NRFD : std_logic; signal NDAC_1, NDAC_2, NDAC : std_logic; signal EOI_1, EOI_2, EOI : std_logic; signal SRQ_1, SRQ_2, SRQ : std_logic; signal IFC_1, IFC_2, IFC : std_logic; signal REN_1, REN_2, REN : std_logic; -- gpib reader signal buf_interrupt : std_logic; signal data_available : std_logic; signal last_byte_addr : std_logic_vector (3 downto 0); signal end_of_stream : std_logic; signal byte_addr : std_logic_vector (3 downto 0); signal data_out : std_logic_vector (7 downto 0); signal reset_buffer : std_logic := '0'; signal dataSecAddr : std_logic_vector (4 downto 0); -- gpib writer signal w_last_byte_addr : std_logic_vector (3 downto 0) := (others => '0'); signal w_end_of_stream : std_logic := '0'; signal w_data_available : std_logic := '0'; signal w_buf_interrupt : std_logic; signal w_data_in : std_logic_vector (7 downto 0); signal w_byte_addr : std_logic_vector (3 downto 0); signal w_reset_buffer : std_logic := '0'; type WR_BUF_TYPE is array (0 to 15) of std_logic_vector (7 downto 0); signal w_write_buffer : WR_BUF_TYPE; -- Clock period definitions constant clk_period : time := 2ps; BEGIN -- Instantiate the Unit Under Test (UUT) gpib1: gpibInterface PORT MAP ( clk => clk, reset => reset, isLE => '0', isTE => '0', lpeUsed => '0', fixedPpLine => "000", eosUsed => '0', eosMark => "00000000", myListAddr => "00001", myTalkAddr => "00001", secAddrMask => (others => '0'), data => data_1, status_byte => status_byte_1, T1 => T1, rdy => rdy_1, nba => nba_1, ltn => ltn_1, lun => lun_1, lon => lon_1, ton => ton_1, endOf => endOf_1, gts => gts_1, rpp => rpp_1, tcs => tcs_1, tca => tca_1, sic => sic_1, rsc => rsc_1, sre => sre_1, rtl => rtl_1, rsv => rsv_1, ist => ist_1, lpe => lpe_1, dvd => dvd_1, wnc => wnc_1, tac => tac_1, cwrc => cwrc_1, cwrd => cwrd_1, clr => clr_1, trg => trg_1, atl => atl_1, att => att_1, mla => mla_1, lsb => lsb_1, spa => spa_1, ppr => ppr_1, sreq => sreq_1, isLocal => isLocal_1, currentSecAddr => currentSecAddr_1, DI => DO, DO => DI_1, output_valid => output_valid_1, ATN_in => ATN, ATN_out => ATN_1, DAV_in => DAV, DAV_out => DAV_1, NRFD_in => NRFD, NRFD_out => NRFD_1, NDAC_in => NDAC, NDAC_out => NDAC_1, EOI_in => EOI, EOI_out => EOI_1, SRQ_in => SRQ, SRQ_out => SRQ_1, IFC_in => IFC, IFC_out => IFC_1, REN_in => REN, REN_out => REN_1 ); -- Instantiate the Unit Under Test (UUT) gpib2: gpibInterface PORT MAP ( clk => clk, reset => reset, isLE => '0', isTE => '0', lpeUsed => '0', fixedPpLine => "000", eosUsed => '0', eosMark => "00000000", myListAddr => "00010", myTalkAddr => "00010", secAddrMask => (others => '0'), data => data_2, status_byte => status_byte_2, T1 => T1, rdy => rdy_2, nba => nba_2, ltn => ltn_2, lun => lun_2, lon => lon_2, ton => ton_2, endOf => endOf_2, gts => gts_2, rpp => rpp_2, tcs => tcs_2, tca => tca_2, sic => sic_2, rsc => rsc_2, sre => sre_2, rtl => rtl_2, rsv => rsv_2, ist => ist_2, lpe => lpe_2, dvd => dvd_2, wnc => wnc_2, tac => tac_2, cwrc => cwrc_2, cwrd => cwrd_2, clr => clr_2, trg => trg_2, atl => atl_2, att => att_2, mla => mla_2, lsb => lsb_2, spa => spa_2, ppr => ppr_2, sreq => sreq_2, isLocal => isLocal_2, currentSecAddr => currentSecAddr_2, DI => DO, DO => DI_2, output_valid => output_valid_2, ATN_in => ATN, ATN_out => ATN_2, DAV_in => DAV, DAV_out => DAV_2, NRFD_in => NRFD, NRFD_out => NRFD_2, NDAC_in => NDAC, NDAC_out => NDAC_2, EOI_in => EOI, EOI_out => EOI_2, SRQ_in => SRQ, SRQ_out => SRQ_2, IFC_in => IFC, IFC_out => IFC_2, REN_in => REN, REN_out => REN_2 ); ce: gpibCableEmulator port map ( -- interface signals DIO_1 => DI_1, output_valid_1 => output_valid_1, DIO_2 => DI_2, output_valid_2 => output_valid_2, DIO => DO, -- attention ATN_1 => ATN_1, ATN_2 => ATN_2, ATN => ATN, DAV_1 => DAV_1, DAV_2 => DAV_2, DAV => DAV, NRFD_1 => NRFD_1, NRFD_2 => NRFD_2, NRFD => NRFD, NDAC_1 => NDAC_1, NDAC_2 => NDAC_2, NDAC => NDAC, EOI_1 => EOI_1, EOI_2 => EOI_2, EOI => EOI, SRQ_1 => SRQ_1, SRQ_2 => SRQ_2, SRQ => SRQ, IFC_1 => IFC_1, IFC_2 => IFC_2, IFC => IFC, REN_1 => REN_1, REN_2 => REN_2, REN => REN ); gr: gpibReader generic map (ADDR_WIDTH => 4) port map ( clk => clk, reset => reset, ------------------------------------------------------------------------ ------ GPIB interface -------------------------------------------------- ------------------------------------------------------------------------ data_in => DO, dvd => dvd_2, atl => atl_2, lsb => lsb_2, rdy => rdy_2, ------------------------------------------------------------------------ ------ external interface ---------------------------------------------- ------------------------------------------------------------------------ isLE => '0', secAddr => (others => '0'), dataSecAddr => dataSecAddr, buf_interrupt => buf_interrupt, data_available => data_available, last_byte_addr => last_byte_addr, end_of_stream => end_of_stream, byte_addr => byte_addr, data_out => data_out, reset_buffer => reset_buffer ); w_data_in <= w_write_buffer(conv_integer(w_byte_addr)); gw: gpibWriter generic map (ADDR_WIDTH => 4) port map ( clk => clk, reset => reset, ------------------------------------------------------------------------ ------ GPIB interface -------------------------------------------------- ------------------------------------------------------------------------ data_out => data_1, wnc => wnc_1, spa => spa_1, nba => nba_1, endOf => endOf_1, att => att_1, cwrc => cwrc_1, ------------------------------------------------------------------------ ------ external interface ---------------------------------------------- ------------------------------------------------------------------------ isTE => '0', secAddr => (others => '0'), dataSecAddr => (others => '0'), last_byte_addr => w_last_byte_addr, end_of_stream => w_end_of_stream, data_available => w_data_available, buf_interrupt => w_buf_interrupt, data_in => w_data_in, byte_addr => w_byte_addr, reset_buffer => w_reset_buffer ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 10 clock periods. reset <= '1'; wait for clk_period*10; reset <= '0'; wait for clk_period*10; -- requests system control rsc_1 <= '1'; -- interface clear sic_1 <= '1'; wait until IFC_1 = '1'; sic_1 <= '0'; wait until IFC_1 = '0'; assert trg_1 = '0'; assert trg_2 = '0'; -- send GET (device clear) w_write_buffer(0) <= "00001000"; w_last_byte_addr <= "0000"; w_data_available <= '1'; wait until w_buf_interrupt='1'; assert trg_1 = '0'; assert trg_2 = '0'; w_reset_buffer <= '1'; wait for clk_period*2; w_reset_buffer <= '0'; -- gpib2 to listen w_write_buffer(0) <= "00100010"; w_last_byte_addr <= "0000"; w_data_available <= '1'; wait until w_buf_interrupt='1'; assert trg_1 = '0'; assert trg_2 = '0'; w_reset_buffer <= '1'; wait for clk_period*2; w_reset_buffer <= '0'; -- send GET w_write_buffer(0) <= "00001000"; w_last_byte_addr <= "0000"; w_data_available <= '1'; wait until w_buf_interrupt='1'; assert trg_1 = '0'; assert trg_2 = '1'; report "$$$ END OF TEST - DT (device trigger) $$$"; wait; end process; END;

gpl-3.0

freecores/gpib_controller

vhdl/src/gpib_helper/MemoryBlock_by_logic.vhd

1

2416

-------------------------------------------------------------------------------- --This file is part of fpga_gpib_controller. -- -- Fpga_gpib_controller is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Fpga_gpib_controller is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------------------------------- -- Entity: MemoryBlock -- Date:2011-11-14 -- Author: Andrzej Paluch -- -- Description ${cursor} -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library UNISIM; use UNISIM.vcomponents.all; use work.utilPkg.all; use work.helperComponents.all; entity MemoryBlock is port ( reset : in std_logic; clk : in std_logic; ------------------------------------------------- p1_addr : in std_logic_vector(10 downto 0); p1_data_in : in std_logic_vector(7 downto 0); p1_strobe : in std_logic; p1_data_out : out std_logic_vector(7 downto 0); ------------------------------------------------- p2_addr : in std_logic_vector(10 downto 0); p2_data_in : in std_logic_vector(7 downto 0); p2_strobe : in std_logic; p2_data_out : out std_logic_vector(7 downto 0) ); end MemoryBlock; architecture arch of MemoryBlock is type mem is array(0 to 31) of std_logic_vector(7 downto 0); signal memory : mem; signal addrP1, addrP2 : integer range 0 to 31; begin addrP1 <= conv_integer(UNSIGNED(p1_addr)); addrP2 <= conv_integer(UNSIGNED(p2_addr)); process(reset, clk) begin if reset = '1' then elsif rising_edge(clk) then p1_data_out <= memory(addrP1); p2_data_out <= memory(addrP2); if p1_strobe = '1' then memory(addrP1) <= p1_data_in; end if; if p2_strobe = '1' then memory(addrP2) <= p2_data_in; end if; end if; end process; end arch;

gpl-3.0

freecores/gpib_controller

vhdl/src/gpib/if_func_PP.vhd

1

4923

-------------------------------------------------------------------------------- --This file is part of fpga_gpib_controller. -- -- Fpga_gpib_controller is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Fpga_gpib_controller is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>. ---------------------------------------------------------------------------------- -- Author: Andrzej Paluch -- -- Create Date: 01:04:57 10/03/2011 -- Design Name: -- Module Name: if_func_PP - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.utilPkg.all; entity if_func_PP is port( -- device inputs clk : in std_logic; -- clock -- settings lpeUsed : std_logic; fixedPpLine : in std_logic_vector (2 downto 0); -- local commands pon : in std_logic; -- power on lpe : in std_logic; -- local poll enable ist : in std_logic; -- individual status -- state inputs ACDS : in std_logic; -- accept data state LADS : in std_logic; -- listener address state (L or LE) -- data input dio_data : in std_logic_vector(3 downto 0); -- byte from data lines -- remote command inputs IDY : in std_logic; -- identify PPE : in std_logic; -- parallel poll enable PPD : in std_logic; -- parallel poll disable PPC : in std_logic; -- parallel poll configure PPU : in std_logic; -- parallel poll unconfigure PCG : in std_logic; -- primary command group -- remote command outputs PPR : out std_logic; -- paralel poll response -- PPR command data ppBitValue : out std_logic; -- bit value ppLineNumber : out std_logic_vector (2 downto 0); -- reported states PPAS : out std_logic -- parallel poll active state ); end if_func_PP; architecture Behavioral of if_func_PP is -- states type PP_STATE_1 is ( -- parallel poll idle state ST_PPIS, -- parallel poll standby state ST_PPSS, -- parallel poll active state ST_PPAS ); -- states type PP_STATE_2 is ( -- parallel poll unaddressed to configure state ST_PUCS, -- parallel poll addressed to configure state ST_PACS ); -- current state signal current_state_1 : PP_STATE_1; signal current_state_2 : PP_STATE_2; -- predicates signal pred1, pred2, pred3, pred4, pred5 : boolean; -- memorized PP metadata signal S : std_logic; signal lineAddr : std_logic_vector (2 downto 0); begin -- state machine process - PP_STATE_1 process(pon, clk) begin if pon = '1' then current_state_1 <= ST_PPIS; elsif rising_edge(clk) then case current_state_1 is ------------------ when ST_PPIS => if pred1 then S <= dio_data(3); lineAddr <= dio_data(2 downto 0); current_state_1 <= ST_PPSS; end if; ------------------ when ST_PPSS => if pred3 then current_state_1 <= ST_PPAS; elsif pred2 then current_state_1 <= ST_PPIS; end if; ------------------ when ST_PPAS => if not pred3 then current_state_1 <= ST_PPSS; end if; ------------------ when others => current_state_1 <= ST_PPIS; end case; end if; end process; -- state machine process - PP_STATE_2 process(pon, clk) begin if pon = '1' then current_state_2 <= ST_PUCS; elsif rising_edge(clk) then case current_state_2 is ------------------ when ST_PUCS => if pred4 then current_state_2 <= ST_PACS; end if; ------------------ when ST_PACS => if pred5 then current_state_2 <= ST_PUCS; end if; ------------------ when others => current_state_2 <= ST_PUCS; end case; end if; end process; ppBitValue <= (not S xor ist) when lpeUsed='0' else ist; ppLineNumber <= lineAddr when lpeUsed='0' else fixedPpLine; PPR <= to_stdl(current_state_1 = ST_PPAS); PPAS <= to_stdl(current_state_1 = ST_PPAS); -- predicates with lpeUsed select pred1 <= is_1(lpe) when '1', PPE='1' and current_state_2=ST_PACS and ACDS='1' when others; with lpeUsed select pred2 <= is_1(not lpe) when '1', ((PPD='1' and current_state_2=ST_PACS) or PPU='1') and ACDS='1' when others; pred3 <= IDY='1'; pred4 <= PPC='1' and LADS='1' and ACDS='1'; pred5 <= PCG='1' and PPC='0' and ACDS='1'; end Behavioral;

gpl-3.0

MonsieurOenologue/Paprotto

subNbits.vhd

1

983

--Libraries imports library ieee; use ieee.std_logic_1164.all; --Entity declaration ENTITY subNbits IS GENERIC( N : IN NATURAL := 16 ); PORT( A, B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); Cin : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); Cout : OUT STD_LOGIC ); END; --Architecture behavior ARCHITECTURE behavior OF subNbits IS COMPONENT minNbits IS GENERIC( N : IN NATURAL := 16 ); PORT( A : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ); END COMPONENT; COMPONENT faG IS GENERIC( N : IN NATURAL := 16 ); PORT( A, B : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); Cin : IN STD_LOGIC; S : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0); Cout : OUT STD_LOGIC ); END COMPONENT; SIGNAL tempB : STD_LOGIC_VECTOR(N-1 DOWNTO 0); SIGNAL tempCo : STD_LOGIC_VECTOR(N-1 DOWNTO 0); BEGIN min : minNbits GENERIC MAP (N) PORT MAP (B, tempB); add : faG GENERIC MAP (N) PORT MAP (A, tempB, Cin, S, Cout); END;

gpl-3.0

MonsieurOenologue/Paprotto

topLevel.vhd

1

817

--Libraries imports library ieee; use ieee.std_logic_1164.all; --Entity declaration ENTITY topLevel IS PORT( BT : IN STD_LOGIC_VECTOR(2 DOWNTO 0); SW : IN STD_LOGIC_VECTOR(15 DOWNTO 0); LEDG : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END; --Architecture behavior ARCHITECTURE behavior OF topLevel IS COMPONENT Paprotto IS GENERIC( N : IN NATURAL := 16 ); PORT( clk : IN STD_LOGIC; reset : IN std_logic; run : IN std_logic; code : IN std_logic_vector(15 DOWNTO 0); done : OUT std_logic; overflow : OUT std_logic ); END COMPONENT; SIGNAL databus : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN databus <= (OTHERS => '0'); LEDG(0) <= BT(0); CPU : Paprotto GENERIC MAP (16) PORT MAP(BT(2), BT(1), BT(0), SW, databus(1), LEDG(1)); END;

gpl-3.0

iamllama/EE2020

ee2020.ip_user_files/ipstatic/hdl/c_addsub_v12_0_vh_rfs.vhd

1

402790

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block fgcHMpDB8YeTXYpoTsmWZ+EpGtmp4ttE4rhLnGC39GZlQ/zJoTz5jsPoaLlJ4UWaOu8wsqCjidiH ybd7UHh7Iw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Ce9yJwkNvACWlmAFVwVRYhOdCIZZzBisSiZXBvx+NUYf+lxZv1vyZmKRIRYhYQFaRqRT7XkpC1Ec t+dZjN7MGpN15tip1+lCNk6nbQTIhD1RPmDELP6pl456iOpiQ/ZN6oyRQX4m6uADI4VCap54SPA7 xDAZ2Ihv8VRQzQqKu2s= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 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gpl-3.0

iamllama/EE2020

ee2020.ip_user_files/ipstatic/hdl/lib_pkg_v1_0_rfs.vhd

6

16353

-- Processor Common Library Package ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: lib_pkg.vhd -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- need conversion function to convert reals/integers to std logic vectors use ieee.std_logic_arith.conv_std_logic_vector; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package lib_pkg is ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- type CHAR_TO_INT_TYPE is array (character) of integer; -- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer; -- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63); ------------------------------------------------------------------------------- -- Function and Procedure Declarations ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer; function min2 (num1, num2 : integer) return integer; function Addr_Bits(x,y : std_logic_vector) return integer; function clog2(x : positive) return natural; function pad_power2 ( in_num : integer ) return integer; function pad_4 ( in_num : integer ) return integer; function log2(x : natural) return integer; function pwr(x: integer; y: integer) return integer; function String_To_Int(S : string) return integer; function itoa (int : integer) return string; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- the RESET_ACTIVE constant should denote the logic level of an active reset constant RESET_ACTIVE : std_logic := '1'; -- table containing strings representing hex characters for conversion to -- integers constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE := ('0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4, '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, 'A'|'a' => 10, 'B'|'b' => 11, 'C'|'c' => 12, 'D'|'d' => 13, 'E'|'e' => 14, 'F'|'f' => 15, others => -1); end lib_pkg; package body lib_pkg is ------------------------------------------------------------------------------- -- Function Definitions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Function max2 -- -- This function returns the greater of two numbers. ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer is begin if num1 >= num2 then return num1; else return num2; end if; end function max2; ------------------------------------------------------------------------------- -- Function min2 -- -- This function returns the lesser of two numbers. ------------------------------------------------------------------------------- function min2 (num1, num2 : integer) return integer is begin if num1 <= num2 then return num1; else return num2; end if; end function min2; ------------------------------------------------------------------------------- -- Function Addr_bits -- -- function to convert an address range (base address and an upper address) -- into the number of upper address bits needed for decoding a device -- select signal. will handle slices and big or little endian ------------------------------------------------------------------------------- function Addr_Bits(x,y : std_logic_vector) return integer is variable addr_xor : std_logic_vector(x'range); variable count : integer := 0; begin assert x'length = y'length and (x'ascending xnor y'ascending) report "Addr_Bits: arguments are not the same type" severity ERROR; addr_xor := x xor y; for i in x'range loop if addr_xor(i) = '1' then return count; end if; count := count + 1; end loop; return x'length; end Addr_Bits; -------------------------------------------------------------------------------- -- Function clog2 - returns the integer ceiling of the base 2 logarithm of x, -- i.e., the least integer greater than or equal to log2(x). -------------------------------------------------------------------------------- function clog2(x : positive) return natural is variable r : natural := 0; variable rp : natural := 1; -- rp tracks the value 2**r begin while rp < x loop -- Termination condition T: x <= 2**r -- Loop invariant L: 2**(r-1) < x r := r + 1; if rp > integer'high - rp then exit; end if; -- If doubling rp overflows -- the integer range, the doubled value would exceed x, so safe to exit. rp := rp + rp; end loop; -- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r return r; -- end clog2; ------------------------------------------------------------------------------- -- Function pad_power2 -- -- This function returns the next power of 2 from the input number. If the -- input number is a power of 2, this function returns the input number. -- -- This function is used to round up the number of masters to the next power -- of 2 if the number of masters is not already a power of 2. -- -- Input argument 0, which is not a power of two, is accepted and returns 0. -- Input arguments less than 0 are not allowed. ------------------------------------------------------------------------------- -- function pad_power2 (in_num : integer ) return integer is begin if in_num = 0 then return 0; else return 2**(clog2(in_num)); end if; end pad_power2; ------------------------------------------------------------------------------- -- Function pad_4 -- -- This function returns the next multiple of 4 from the input number. If the -- input number is a multiple of 4, this function returns the input number. -- ------------------------------------------------------------------------------- -- function pad_4 (in_num : integer ) return integer is variable out_num : integer; begin out_num := (((in_num-1)/4) + 1)*4; return out_num; end pad_4; ------------------------------------------------------------------------------- -- Function log2 -- returns number of bits needed to encode x choices -- x = 0 returns 0 -- x = 1 returns 0 -- x = 2 returns 1 -- x = 4 returns 2, etc. ------------------------------------------------------------------------------- -- function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val*2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; end function log2; ------------------------------------------------------------------------------- -- Function pwr -- x**y -- negative numbers not allowed for y ------------------------------------------------------------------------------- function pwr(x: integer; y: integer) return integer is variable z : integer := 1; begin if y = 0 then return 1; else for i in 1 to y loop z := z * x; end loop; return z; end if; end function pwr; ------------------------------------------------------------------------------- -- Function itoa -- -- The itoa function converts an integer to a text string. -- This function is required since `image doesn't work in Synplicity -- Valid input range is -9999 to 9999 ------------------------------------------------------------------------------- -- function itoa (int : integer) return string is type table is array (0 to 9) of string (1 to 1); constant LUT : table := ("0", "1", "2", "3", "4", "5", "6", "7", "8", "9"); variable str1 : string(1 to 1); variable str2 : string(1 to 2); variable str3 : string(1 to 3); variable str4 : string(1 to 4); variable str5 : string(1 to 5); variable abs_int : natural; variable thousands_place : natural; variable hundreds_place : natural; variable tens_place : natural; variable ones_place : natural; variable sign : integer; begin abs_int := abs(int); if abs_int > int then sign := -1; else sign := 1; end if; thousands_place := abs_int/1000; hundreds_place := (abs_int-thousands_place*1000)/100; tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10; ones_place := (abs_int-thousands_place*1000-hundreds_place*100-tens_place*10); if sign>0 then if thousands_place>0 then str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif hundreds_place>0 then str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str3; elsif tens_place>0 then str2 := LUT(tens_place) & LUT(ones_place); return str2; else str1 := LUT(ones_place); return str1; end if; else if thousands_place>0 then str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str5; elsif hundreds_place>0 then str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif tens_place>0 then str3 := "-" & LUT(tens_place) & LUT(ones_place); return str3; else str2 := "-" & LUT(ones_place); return str2; end if; end if; end itoa; ----------------------------------------------------------------------------- -- Function String_To_Int -- -- Converts a string of hex character to an integer -- accept negative numbers ----------------------------------------------------------------------------- function String_To_Int(S : String) return Integer is variable Result : integer := 0; variable Temp : integer := S'Left; variable Negative : integer := 1; begin for I in S'Left to S'Right loop if (S(I) = '-') then Temp := 0; Negative := -1; else Temp := STRHEX_TO_INT_TABLE(S(I)); if (Temp = -1) then assert false report "Wrong value in String_To_Int conversion " & S(I) severity error; end if; end if; Result := Result * 16 + Temp; end loop; return (Negative * Result); end String_To_Int; end package body lib_pkg;

gpl-3.0

kjellhar/ArtixPi

spi_test/src/hdl/spi_slave_old.vhd

1

5579

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 06/16/2016 04:17:04 AM -- Design Name: -- Module Name: spi_slave - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity spi_slave is Generic ( N : positive := 8; CPOL : std_logic := '0'; CPHA : std_logic := '0' ); Port ( clk : in STD_LOGIC; -- External SPI signals spi_ss_n : in STD_LOGIC; spi_clk : in STD_LOGIC; spi_mosi : in STD_LOGIC; spi_miso : out STD_LOGIC; -- Internal data signals di : out STD_LOGIC_VECTOR (N-1 downto 0); -- Data received from SPI do : in STD_LOGIC_VECTOR (N-1 downto 0); -- Data to be transmitted over SPI di_valid : out std_logic; -- High for one clock cycle to indicate a new word is present do_wren : in std_logic; -- Write a data word to the transmit register do_wrack : out std_logic); -- High for one clock cycle when the transmission starts. -- The next data word can be written as soon as this signal goes low. end spi_slave; architecture Behavioral of spi_slave is -- constants to control FlipFlop synthesis constant CAPTURE_EDGE : std_logic := (CPOL xnor CPHA); constant CHANGE_EDGE : std_logic := (CPOL xor CPHA); type spi_state_t is ( IDLE, INIT_TRANSACTION, SHIFTING_DATA, WORD_COMPLETE ); signal spi_state : spi_state_t := IDLE; signal spi_state_next : spi_state_t; signal spi_clk_buf : std_logic := CPOL; signal spi_capture_edge : std_logic; signal spi_change_edge : std_logic; signal di_buf : std_logic; signal di_reg : std_logic_vector(N-1 downto 0); signal do_reg : std_logic_vector(N-1 downto 0); signal do_i : std_logic_vector(N-1 downto 0); signal bit_counter : integer range 0 to N-1 := 0; begin -- state register process begin wait until rising_edge (clk); if spi_ss_n='1' then spi_state <= IDLE; else spi_state <= spi_state_next; end if; end process; -- Next state logic process ( spi_state, spi_ss_n, bit_counter) begin spi_state_next <= spi_state; case (spi_state) is when IDLE => if spi_ss_n='0' then spi_state_next <= INIT_TRANSACTION; end if; when INIT_TRANSACTION => spi_state_next <= SHIFTING_DATA; when SHIFTING_DATA => if bit_counter=N-1 then spi_state_next <= WORD_COMPLETE; end if; when WORD_COMPLETE => if bit_counter = 0 then spi_state_next <= INIT_TRANSACTION; end if; when others => spi_state_next <= IDLE; end case; end process; -- SPI clock edge detector process begin wait until rising_edge(clk); spi_clk_buf <= spi_clk; if (spi_clk_buf= not spi_clk) and spi_clk=CAPTURE_EDGE then spi_capture_edge <= '1'; else spi_capture_edge <= '0'; end if; if (spi_clk_buf= not spi_clk) and spi_clk=CHANGE_EDGE then spi_change_edge <= '1'; else spi_change_edge <= '0'; end if; end process; -- Input shift register process begin wait until rising_edge(clk); di_buf <= spi_mosi; if spi_capture_edge='1' then di_reg <= di_reg(N-2 downto 0) & di_buf; bit_counter <= bit_counter + 1; end if; end process; -- output received data word process begin wait until rising_edge(clk); di_valid <= '0'; if spi_state=WORD_COMPLETE and bit_counter=0 then di <= di_reg; di_valid <= '1'; end if; end process; -- get data word for tx process begin wait until rising_edge(clk); if do_wren='1' then do_i <= do; end if; end process; -- output shift register process begin wait until rising_edge(clk); do_wrack <= '0'; if spi_state = IDLE then do_reg <= X"00"; elsif spi_state = INIT_TRANSACTION then do_reg <= do_i; do_wrack <= '1'; elsif spi_change_edge='1' and bit_counter /= 0 then do_reg <= do_reg(N-2 downto 0) & '0'; end if; end process; spi_miso <= do_reg(7); end Behavioral;

gpl-3.0

aylons/concordic

hdl/modules/cordic_vectoring/cordic_vectoring_wb.vhd

1

9110

------------------------------------------------------------------------------- -- Title : Wishbonized vectoring CORDIC -- Project : ------------------------------------------------------------------------------- -- File : cordic_vectoring_wb.vhd -- Author : aylons <aylons@LNLS190> -- Company : -- Created : 2014-09-03 -- Last update: 2014-11-19 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Wishbonized version of the CORDIC in vectoring mode. This -- module is transparent for both TGD and ADR, but to reduce area use, it may -- me set to only accept a maximum number of simultaneous data points being -- calculated. It may also accept parallel or serial I/Q data. ------------------------------------------------------------------------------- -- Copyright (c) 2014 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2014-09-03 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.genram_pkg.all; use work.wb_stream_pkg.all; ------------------------------------------------------------------------------- -- Input data structure: -- I = (g_width*2)-1 downto g_width -- Q = g_width-1 downto 0; -- Output data structure: -- mag = (g_width*2)-1 downto g_width -- phase = g_width-1 downto 0 entity cordic_vectoring_wb is generic ( g_stages : natural := 32; g_width : natural := 32; g_simultaneous : natural := 4; g_parallel : boolean := true; g_tgd_width : natural := 4; g_adr_width : natural := 3; g_input_buffer : natural := 4; g_output_buffer : natural := 2 ); port ( clk_i : in std_logic; rst_i : in std_logic; ce_i : in std_logic; snk_i : in t_wbs_sink_in; snk_o : out t_wbs_sink_out; src_i : in t_wbs_source_in; src_o : out t_wbs_source_out ); end entity cordic_vectoring_wb; ------------------------------------------------------------------------------- architecture str of cordic_vectoring_wb is signal data_sink, data_source : std_logic_vector(g_width*2-1 downto 0) := (others => '0'); signal metadata_sink, metadata_source : std_logic_vector(g_tgd_width + g_adr_width - 1 downto 0); signal I : std_logic_vector(g_width-1 downto 0) := (others => '0'); signal Q : std_logic_vector(g_width-1 downto 0) := (others => '0'); signal mag : std_logic_vector(g_width-1 downto 0) := (others => '0'); signal phase : std_logic_vector(g_width-1 downto 0) := (others => '0'); signal tgd_sink : std_logic_vector(g_tgd_width-1 downto 0) := (others => '0'); signal adr_sink : std_logic_vector(g_adr_width-1 downto 0) := (others => '0'); signal valid_sink : std_logic := '0'; signal tgd_source : std_logic_vector(g_tgd_width-1 downto 0) := (others => '0'); signal adr_source : std_logic_vector(g_adr_width-1 downto 0) := (others => '0'); signal valid_source : std_logic := '0'; signal source_req : std_logic; signal ack_sink : std_logic; signal ack_source : std_logic; signal full_meta : std_logic; signal rst_n : std_logic; ----------------------------------------------------------------------------- -- Internal signal declarations ----------------------------------------------------------------------------- component cordic_vectoring_slv is generic ( g_stages : natural; g_width : natural); port ( x_i : in std_logic_vector(g_width-1 downto 0) := (others => '0'); y_i : in std_logic_vector(g_width-1 downto 0) := (others => '0'); clk_i : in std_logic; ce_i : in std_logic; valid_i : in std_logic; rst_i : in std_logic; mag_o : out std_logic_vector(g_width-1 downto 0) := (others => '0'); phase_o : out std_logic_vector(g_width-1 downto 0) := (others => '0'); valid_o : out std_logic); end component cordic_vectoring_slv; component decoupled_fifo is generic ( g_fifo_width : natural; g_fifo_depth : natural); port ( rst_n_i : in std_logic; clk_i : in std_logic; d_i : in std_logic_vector(g_fifo_width-1 downto 0); we_i : in std_logic; rd_i : in std_logic; full_o : out std_logic; d_o : out std_logic_vector(g_fifo_width-1 downto 0); valid_o : out std_logic); end component decoupled_fifo; component generic_shiftreg_fifo is generic ( g_data_width : integer; g_size : integer); port ( rst_n_i : in std_logic := '1'; clk_i : in std_logic; d_i : in std_logic_vector(g_data_width-1 downto 0); we_i : in std_logic; q_o : out std_logic_vector(g_data_width-1 downto 0); rd_i : in std_logic; full_o : out std_logic; almost_full_o : out std_logic; q_valid_o : out std_logic); end component generic_shiftreg_fifo; component xwb_stream_sink is generic ( g_data_width : natural; g_addr_width : natural; g_tgd_width : natural; g_buffer_depth : natural); port ( clk_i : in std_logic; rst_n_i : in std_logic; snk_i : in t_wbs_sink_in; snk_o : out t_wbs_sink_out; addr_o : out std_logic_vector(g_adr_width-1 downto 0); data_o : out std_logic_vector(g_data_width-1 downto 0); tgd_o : out std_logic_vector(g_tgd_width-1 downto 0); error_o : out std_logic; dvalid_o : out std_logic; dreq_i : in std_logic); end component xwb_stream_sink; component xwb_stream_source is generic ( g_data_width : natural; g_addr_width : natural; g_tgd_width : natural; g_buffer_depth : natural); port ( clk_i : in std_logic; rst_n_i : in std_logic; src_i : in t_wbs_source_in; src_o : out t_wbs_source_out; addr_i : in std_logic_vector(g_adr_width-1 downto 0); data_i : in std_logic_vector(g_data_width-1 downto 0); tgd_i : in std_logic_vector(g_tgd_width-1 downto 0); dvalid_i : in std_logic; error_i : in std_logic; dreq_o : out std_logic); end component xwb_stream_source; begin -- architecture str rst_n <= not(rst_i); cmp_wb_sink : xwb_stream_sink generic map ( g_data_width => g_width*2, g_addr_width => g_adr_width, g_tgd_width => g_tgd_width, g_buffer_depth => g_input_buffer) port map ( clk_i => clk_i, rst_n_i => rst_n, snk_i => snk_i, snk_o => snk_o, addr_o => adr_sink, data_o => data_sink, tgd_o => tgd_sink, error_o => open, -- no error treatment dvalid_o => valid_sink, dreq_i => ack_sink); I <= data_sink(g_width*2-1 downto g_width); Q <= data_sink(g_width-1 downto 0); cmp_cordic : cordic_vectoring_slv generic map ( g_stages => g_stages, g_width => g_width) port map ( x_i => I, y_i => Q, clk_i => clk_i, ce_i => ce_i, valid_i => ack_sink, rst_i => rst_i, mag_o => mag, phase_o => phase, valid_o => valid_source); data_source(g_width*2-1 downto g_width) <= mag; data_source(g_width-1 downto 0) <= phase; -- Metadata metadata_sink <= tgd_sink & adr_sink; ack_sink <= not(full_meta) and ce_i and valid_sink; ack_source <= source_req and ce_i and valid_source; -- Stop accepting new data if full cmp_metadata : decoupled_fifo generic map( g_fifo_width => g_adr_width + g_tgd_width, g_fifo_depth => g_simultaneous) port map ( rst_n_i => rst_n, clk_i => clk_i, d_i => metadata_sink, we_i => ack_sink, rd_i => ack_source, d_o => metadata_source, full_o => full_meta); tgd_source <= metadata_source(g_tgd_width + g_adr_width - 1 downto g_adr_width); adr_source <= metadata_source(g_adr_width - 1 downto 0); cmp_wb_source : xwb_stream_source generic map ( g_data_width => g_width*2, g_addr_width => g_adr_width, g_tgd_width => g_tgd_width, g_buffer_depth => g_output_buffer) port map ( clk_i => clk_i, rst_n_i => rst_n, src_i => src_i, src_o => src_o, addr_i => adr_source, data_i => data_source, tgd_i => tgd_source, dvalid_i => ack_source, error_i => '0', --error is only forwarded through TGD dreq_o => source_req); end architecture str; -------------------------------------------------------------------------------

gpl-3.0

iamllama/EE2020

ee2020.ip_user_files/ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd

1

38936

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nj298JyQhLqfjZVk `protect end_protected

gpl-3.0

thequbit/af_paper

code/xilinx/pixel_difference_2d.vhd

1

1935

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity pixel_difference_2d is Port ( i_clk : in STD_LOGIC; i_reset : in STD_LOGIC; i_R : in STD_LOGIC_VECTOR (7 downto 0); i_G : in STD_LOGIC_VECTOR (7 downto 0); i_B : in STD_LOGIC_VECTOR (7 downto 0); i_framevalid : in STD_LOGIC; i_linevalid : in STD_LOGIC; o_focusvalue : out STD_LOGIC_VECTOR(31 downto 0); o_dv : out STD_LOGIC ); end pixel_difference_2d; architecture Behavioral of pixel_difference_2d is COMPONENT color_space_converter PORT( i_clk : IN std_logic; i_reset : IN std_logic; i_R : IN std_logic_vector(7 downto 0); i_G : IN std_logic_vector(7 downto 0); i_B : IN std_logic_vector(7 downto 0); i_framevalid : IN std_logic; i_linevalid : IN std_logic; o_Y : OUT std_logic_vector(7 downto 0); o_framevalid : OUT std_logic; o_linevalid : OUT std_logic ); END COMPONENT; COMPONENT focus_calculation_pixel_difference_2d PORT( i_clk : IN std_logic; i_reset : IN std_logic; i_framevalid : IN std_logic; i_linevalid : IN std_logic; i_Y : IN std_logic_vector(7 downto 0); o_focusvalue : OUT std_logic_vector(31 downto 0); o_dv : OUT std_logic ); END COMPONENT; signal s_framevalid : STD_LOGIC; signal s_linevalid : STD_LOGIC; signal s_Y : STD_LOGIC_VECTOR(7 downto 0); begin Inst_color_space_converter: color_space_converter PORT MAP( i_clk => i_clk, i_reset => i_reset, i_R => i_R, i_G => i_G, i_B => i_B, i_framevalid => i_framevalid, i_linevalid => i_linevalid, o_Y => s_Y, o_framevalid => s_framevalid, o_linevalid => s_linevalid ); Inst_focus_calculation: focus_calculation_pixel_difference_2d PORT MAP( i_clk => i_clk, i_reset => i_reset, i_framevalid => s_framevalid, i_linevalid => s_linevalid, i_Y => s_Y, o_focusvalue => o_focusvalue, o_dv => o_dv ); end Behavioral;

gpl-3.0

iamllama/EE2020

ee2020.ip_user_files/ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd

1

94635

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block US61vRgaZan+kknoy1SnPxYNjkAw9TnKUufX6w+IcDeMGtqyYNromlIoLLZTg7jQub7nmjw8eWCP cY1aOfugKQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Cx+xG/jU1l+emWfaLPy7CXAXh1exaDmq8ZyJFnbt9CiAkRn3KSw//ly11TqIhymDcuIoqbSi8MB5 XrNKColQ8j763aa+JmESdVAhEDb3vw6vtSFZhbGzZ+gjqujywOuXpV4RLNfzGSHZi3T16jM00CVJ fZxkJaQO9Fnkhwc8+vQ= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 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gpl-3.0

suoto/hdlcc

.ci/test_support/test_project/basic_library/two_entities_one_file.vhd

1

96

entity entity_a is end entity; entity entity_a is end entity; entity entity_b is end entity;

gpl-3.0

hiyuh/nvc

test/regress/issue59.vhd

5

752

package p is pure function f( i : boolean ) return integer; end package p; package body p is pure function f( i : boolean ) return integer is begin if (i = false) then return 0; else return 1; end if; end function f; end package body p; ------------------------------------------------------------------------------- use work.p.all; package q is constant d : integer := f(true) + 1; end package q; package body q is end package body q; ------------------------------------------------------------------------------- use work.q.all; entity issue59 is begin assert (d = 2); end entity issue59; architecture a of issue59 is begin end architecture a;

gpl-3.0

hiyuh/nvc

test/regress/issue204.vhd

5

228

entity issue204 is end entity; architecture a of issue204 is type enum_t is (a, b); begin main : process begin assert enum_t'leftof(b) = a; assert enum_t'rightof(a) = b; wait; end process; end architecture;

gpl-3.0

hiyuh/nvc

test/sem/issue221.vhd

5

723

package fred4 is type fred4_t is protected impure function is_empty return boolean; impure function hi_there return string; end protected fred4_t; end package fred4; package body fred4 is type fred4_t is protected body ---------------------------------------- impure function is_empty return boolean is begin return TRUE; end function is_empty; ---------------------------------------- impure function hi_there return string is begin if is_empty then return "perfect"; else return "we have a problem"; end if; end function hi_there; ---------------------------------------- end protected body fred4_t; end package body fred4;

gpl-3.0

dobairoland/ZyEHW

hw/hdl/axi_evol.vhd

1

14526

-- Copyright (C) 2014 Roland Dobai -- -- This file is part of ZyEHW. -- -- ZyEHW is free software: you can redistribute it and/or modify it under the -- terms of the GNU General Public License as published by the Free Software -- Foundation, either version 3 of the License, or (at your option) any later -- version. -- -- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY -- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS -- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more -- details. -- -- You should have received a copy of the GNU General Public License along -- with ZyEHW. If not, see <http://www.gnu.org/licenses/>. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.zyehw_pkg.all; entity axi_evol is port ( s_axi_aclk: in std_logic; s_axi_aresetn: in std_logic; s_axi_arvalid: in std_logic; s_axi_awvalid: in std_logic; s_axi_bready: in std_logic; s_axi_rready: in std_logic; s_axi_wvalid: in std_logic; s_axi_arprot: in std_logic_vector(2 downto 0); s_axi_awprot: in std_logic_vector(2 downto 0); s_axi_araddr: in std_logic_vector(31 downto 0); s_axi_awaddr: in std_logic_vector(31 downto 0); s_axi_wdata: in std_logic_vector(31 downto 0); s_axi_wstrb: in std_logic_vector(3 downto 0); s_axi_arready: out std_logic; s_axi_awready: out std_logic; s_axi_bvalid: out std_logic; s_axi_rvalid: out std_logic; s_axi_wready: out std_logic; s_axi_bresp: out std_logic_vector(1 downto 0); s_axi_rresp: out std_logic_vector(1 downto 0); s_axi_rdata: out std_logic_vector(31 downto 0); end_flag: in std_logic; start_rst: in std_logic; fitness: in fitness_arr_t; fifo_rderr: in std_logic; fifo_wrerr: in std_logic; frame_count: in frame_count_t; start_flag: out std_logic; chromosome: out mux_chromosome_arr_t ); end axi_evol; architecture beh_axi_evol of axi_evol is constant addr_width: integer:= 32; constant data_width: integer:= 32; constant numregisters: integer:= 1 -- control/status + population -- fitness + population *( -- chromosome 2*( -- a and b inputs columns*rows -- PEs *input_sel_width/data_width ) + 1 -- out multiplexers ); constant w32bytes: integer:= data_width/8; constant word_bits: integer:= integer(ceil(log2(real(w32bytes)))); constant reg_bits: integer:= integer(ceil(log2(real(numregisters)))); signal writeaddr, readaddr: std_logic_vector(reg_bits-1 downto 0); signal awready: std_logic; signal wready: std_logic; signal bvalid: std_logic; signal arready: std_logic; signal rdata: std_logic_vector(addr_width-1 downto 0); signal rvalid: std_logic; subtype reg_t is std_logic_vector(data_width-1 downto 0); type regs_t is array (0 to numregisters-1) of reg_t; signal databus: std_logic_vector(data_width-1 downto 0); signal regs: regs_t; signal reg_rden: std_logic; signal reg_wren: std_logic; begin -- Only the start_flag and the chromosome are real registers here. -- The end_flag, fifo_rderr, fifo_wrerr are read together with start_flag -- and are read-only. The fitness is also read-only. -- Addressing -- mux bits: -- (31..28) (27..24) (23..20) (19..16) (15..12) (11..8) (7..4) (3..0) -- -- regs(0) - (3) fifo_wrerr, (2) fifo_rderr, (1) end_flag, (0) start_flag -- Individual 0: -- regs( 1) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs( 2) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs( 3) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs( 4) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs( 5) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs( 6) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs( 7) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs( 8) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs( 9) - (3..2) filter_switch, (1..0) out_select -- Individual 1: -- regs(10) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(11) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(12) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(13) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(14) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(15) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(16) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(17) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(18) - (3..2) filter_switch, (1..0) out_select -- Individual 2: -- regs(19) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(20) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(21) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(22) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(23) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(24) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(25) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(26) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(27) - (3..2) filter_switch, (1..0) out_select -- Individual 3: -- regs(28) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(29) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(30) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(31) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(32) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(33) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(34) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(35) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(36) - (3..2) filter_switch, (1..0) out_select -- Individual 4: -- regs(37) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(38) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(39) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(40) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(41) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(42) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(43) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(44) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(45) - (3..2) filter_switch, (1..0) out_select -- Individual 5: -- regs(46) - b_mux(3, 0), a_mux(3, 0), ..., b_mux(0, 0), a_mux(0, 0) -- regs(47) - b_mux(3, 1), a_mux(3, 1), ..., b_mux(0, 1), a_mux(0, 1) -- regs(48) - b_mux(3, 2), a_mux(3, 2), ..., b_mux(0, 2), a_mux(0, 2) -- regs(49) - b_mux(3, 3), a_mux(3, 3), ..., b_mux(0, 3), a_mux(0, 3) -- regs(50) - b_mux(3, 4), a_mux(3, 4), ..., b_mux(0, 4), a_mux(0, 4) -- regs(51) - b_mux(3, 5), a_mux(3, 5), ..., b_mux(0, 5), a_mux(0, 5) -- regs(52) - b_mux(3, 6), a_mux(3, 6), ..., b_mux(0, 6), a_mux(0, 6) -- regs(53) - b_mux(3, 7), a_mux(3, 7), ..., b_mux(0, 7), a_mux(0, 7) -- regs(54) - (3..2) filter_switch, (1..0) out_select -- regs(55) - fitness of individual 0 -- regs(56) - fitness of individual 1 -- regs(57) - fitness of individual 2 -- regs(58) - fitness of individual 3 -- regs(59) - fitness of individual 4 -- regs(60) - fitness of individual 5 start_flag <= regs(0)(0); regs(0)(1) <= end_flag; regs(0)(2) <= fifo_rderr; regs(0)(3) <= fifo_wrerr; regs(0)(reg_t'high downto 4) <= frame_count; chrom_intconn: for i in 0 to population-1 generate chrom_col: for j in 0 to columns-1 generate chrom_row: for k in 0 to rows-1 generate chromosome(i).a_mux(k, j) <= regs(i*(columns+1)+j+1)( input_sel_width*(2*k+1)-1 downto input_sel_width*2*k); chromosome(i).b_mux(k, j) <= regs(i*(columns+1)+j+1)( input_sel_width*2*(k+1)-1 downto input_sel_width*(2*k+1)); end generate; end generate; chromosome(i).out_select <= regs((i+1)*(columns+1))( output_sel_width-1 downto 0*output_sel_width); chromosome(i).filter_switch <= regs((i+1)*(columns+1))( 2*output_sel_width-1 downto 1*output_sel_width); end generate; fitness_intconn: for i in numregisters-population to numregisters-1 generate regs(i)(fitness_t'range) <= fitness(i-(numregisters-population)); regs(i)(reg_t'high downto fitness_t'high+1) <= (others => '0'); end generate; s_axi_awready <= awready; s_axi_wready <= wready; s_axi_bvalid <= bvalid; s_axi_arready <= arready; s_axi_rdata <= rdata; s_axi_rvalid <= rvalid; reg_wren <= wready and s_axi_wvalid and awready and s_axi_awvalid; reg_rden <= arready and s_axi_arvalid and (not rvalid); process (s_axi_aclk) begin if rising_edge(s_axi_aclk) then if s_axi_aresetn = '0' then awready <= '0'; writeaddr <= (others => '0'); wready <= '0'; bvalid <= '0'; arready <= '0'; readaddr <= (others => '1'); rvalid <= '0'; rdata <= (others => '0'); else if (awready = '0' and s_axi_awvalid = '1' and s_axi_wvalid = '1') then awready <= '1'; else awready <= '0'; end if; if (awready = '0' and s_axi_awvalid = '1' and s_axi_wvalid = '1') then writeaddr <= s_axi_awaddr(reg_bits+word_bits-1 downto word_bits); end if; if (wready = '0' and s_axi_wvalid = '1' and s_axi_awvalid = '1') then wready <= '1'; else wready <= '0'; end if; if (awready = '1' and s_axi_awvalid = '1' and wready = '1' and s_axi_wvalid = '1' and bvalid = '0') then bvalid <= '1'; elsif (s_axi_bready = '1' and bvalid = '1') then bvalid <= '0'; end if; if (arready = '0' and s_axi_arvalid = '1') then arready <= '1'; readaddr <= s_axi_araddr(reg_bits+word_bits-1 downto word_bits); else arready <= '0'; end if; if (arready = '1' and s_axi_arvalid = '1' and rvalid = '0') then rvalid <= '1'; elsif (rvalid = '1' and s_axi_rready = '1') then rvalid <= '0'; end if; if (reg_rden = '1') then rdata <= databus; end if; end if; end if; end process; registers: for i in regs'range generate -- in the control register only the start bit is writable (and is -- resetable by the signal from the cgp core) control_wr: if i = 0 generate process (s_axi_aclk, start_rst) is begin if start_rst = '1' then regs(0)(0) <= '0'; else if rising_edge(s_axi_aclk) then if (reg_wren = '1' and writeaddr = std_logic_vector(to_unsigned(0, reg_bits))) then if s_axi_wstrb(0) = '1' then regs(0)(0) <= s_axi_wdata(0); end if; end if; end if; end if; end process; end generate; -- the chromosome registers are resetable and writable regular -- registers chromosome_wr: if ((i > 0) and (i < (numregisters-population))) generate write_process: process (s_axi_aclk) is begin if rising_edge(s_axi_aclk) then if s_axi_aresetn = '0' then regs(i) <= (others => '0'); else if (reg_wren = '1' and writeaddr = std_logic_vector(to_unsigned(i, reg_bits))) then for j in 0 to w32bytes-1 loop if s_axi_wstrb(j) = '1' then regs(i)((j+1)*8-1 downto j*8) <= s_axi_wdata((j+1)*8-1 downto j*8); end if; end loop; end if; end if; end if; end process; end generate; -- the fitness registers are read-only end generate; databusgen: for i in regs'range generate process (regs, readaddr, s_axi_aresetn) begin if s_axi_aresetn = '0' then databus <= (others => '1'); else if readaddr = std_logic_vector(to_unsigned(i, reg_bits)) then databus <= regs(i); else databus <= (others => 'Z'); end if; end if; end process; end generate; end beh_axi_evol;

gpl-3.0

hiyuh/nvc

test/regress/func11.vhd

5

403

entity func11 is end entity; architecture test of func11 is function foo(x : integer) return integer is begin return x + 1; end function; function foo(x : integer) return real is begin return real(x) + 1.0; end function; begin process is begin assert foo(1) = 2; assert foo(1) = 2.0; wait; end process; end architecture;

gpl-3.0

hiyuh/nvc

test/parse/extended.vhd

4

264

-- Test extended identifiers architecture foo of bar is signal \foo bar\ : integer; signal \a\\b\ : integer; signal \Thing!!! \ : integer; signal \name\ : integer; signal name : integer; begin \foo.bar.baz\ <= \hello\; end architecture;

gpl-3.0

hiyuh/nvc

test/regress/func14.vhd

5

772

entity func14 is end entity; architecture test of func14 is begin one: process is function func(x : integer) return integer is begin return x * 2; end function; variable y : integer; begin y := 2; wait for 1 ns; assert func(y) = 4; y := 4; wait for 1 ns; assert func(y) = 8; wait; end process; two: process is function func(x : integer) return integer is begin return x / 2; end function; variable y : integer; begin y := 2; wait for 1 ns; assert func(y) = 1; y := 4; wait for 1 ns; assert func(y) = 2; wait; end process; end architecture;

gpl-3.0

hiyuh/nvc

test/regress/attr9.vhd

3

454

entity attr9 is end entity; architecture test of attr9 is begin process is type my_small_int is range 1 to 10; begin assert integer'value("1") = 1; assert natural'value(" 12_3") = 123; assert my_small_int'value("5 ") = 5; assert boolean'value("true") = true; assert boolean'value("FALSE") = false; assert character'value("'x' ") = 'x'; wait; end process; end architecture;

gpl-3.0

hiyuh/nvc

test/regress/bitvec.vhd

3

679

entity bitvec is end entity; architecture test of bitvec is function get_bitvec(x, y : integer) return bit_vector is variable r : bit_vector(x to y) := "00"; begin return r; end function; begin process is variable b : bit_vector(3 downto 0); begin b := "1101"; assert not b = "0010"; assert (b and "1010") = "1000"; assert (b or "0110") = "1111"; assert (b xor "0111") = "1010"; assert (b xnor "0111") = "0101"; assert (b nand "1010") = "0111"; assert (b nor "0110") = "0000"; assert get_bitvec(1, 2) = "00"; wait; end process; end architecture;

gpl-3.0